s5pc1xx: update cache routines

Because of v7_flush_dcache_all is moved to omap3/cache.S
and s5pc110 needs cache routines, update s5pc1xx cache routines.

l2_cache_enable and l2_caceh_disable are moved from cache.c to cache.S
and invalidate_dcache is modified for SoC specific.

Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This commit is contained in:
Minkyu Kang
2009-12-18 15:03:51 +09:00
parent 824df58fc0
commit e7ae13a57b
4 changed files with 130 additions and 23 deletions

View File

@@ -0,0 +1,32 @@
/*
* Copyright (C) 2009 Samsung Electrnoics
* Minkyu Kang <mk7.kang@samsung.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _SYS_PROTO_H_
#define _SYS_PROTO_H_
u32 get_device_type(void);
void invalidate_dcache(u32);
void l2_cache_disable(void);
void l2_cache_enable(void);
#endif

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@@ -47,8 +47,6 @@
#undef CONFIG_SKIP_RELOCATE_UBOOT
#define CONFIG_L2_OFF
/* input clock of PLL: SMDKC100 has 12MHz input clock */
#define CONFIG_SYS_CLK_FREQ 12000000