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Merge branch 'master' of git://git.denx.de/u-boot

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This commit is contained in:
Stefano Babic
2015-02-13 11:17:01 +01:00
parent 258c98f8d3 bd2a4888b1
commit e72d344386
1061 changed files with 48502 additions and 24941 deletions
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99
include/_exports.h
View File

@@ -1,32 +1,73 @@
/*
* You do not need to use #ifdef around functions that may not exist
* You need to use #ifdef around functions that may not exist
* in the final configuration (such as i2c).
* use a dummyfunction as first parameter to EXPORT_FUNC.
* As an example see the CONFIG_CMD_I2C section below
*/
EXPORT_FUNC(get_version)
EXPORT_FUNC(getc)
EXPORT_FUNC(tstc)
EXPORT_FUNC(putc)
EXPORT_FUNC(puts)
EXPORT_FUNC(printf)
EXPORT_FUNC(install_hdlr)
EXPORT_FUNC(free_hdlr)
EXPORT_FUNC(malloc)
EXPORT_FUNC(free)
EXPORT_FUNC(udelay)
EXPORT_FUNC(get_timer)
EXPORT_FUNC(vprintf)
EXPORT_FUNC(do_reset)
EXPORT_FUNC(getenv)
EXPORT_FUNC(setenv)
EXPORT_FUNC(simple_strtoul)
EXPORT_FUNC(strict_strtoul)
EXPORT_FUNC(simple_strtol)
EXPORT_FUNC(strcmp)
EXPORT_FUNC(i2c_write)
EXPORT_FUNC(i2c_read)
EXPORT_FUNC(spi_init)
EXPORT_FUNC(spi_setup_slave)
EXPORT_FUNC(spi_free_slave)
EXPORT_FUNC(spi_claim_bus)
EXPORT_FUNC(spi_release_bus)
EXPORT_FUNC(spi_xfer)
#ifndef EXPORT_FUNC
#define EXPORT_FUNC(a, b, c, ...)
#endif
EXPORT_FUNC(get_version, unsigned long, get_version, void)
EXPORT_FUNC(getc, int, getc, void)
EXPORT_FUNC(tstc, int, tstc, void)
EXPORT_FUNC(putc, void, putc, const char)
EXPORT_FUNC(puts, void, puts, const char *)
EXPORT_FUNC(printf, int, printf, const char*, ...)
#if defined(CONFIG_X86) || defined(CONFIG_PPC)
EXPORT_FUNC(irq_install_handler, void, install_hdlr,
int, interrupt_handler_t, void*)
EXPORT_FUNC(irq_free_handler, void, free_hdlr, int)
#else
EXPORT_FUNC(dummy, void, install_hdlr, void)
EXPORT_FUNC(dummy, void, free_hdlr, void)
#endif
EXPORT_FUNC(malloc, void *, malloc, size_t)
EXPORT_FUNC(free, void, free, void *)
EXPORT_FUNC(udelay, void, udelay, unsigned long)
EXPORT_FUNC(get_timer, unsigned long, get_timer, unsigned long)
EXPORT_FUNC(vprintf, int, vprintf, const char *, va_list)
EXPORT_FUNC(do_reset, int, do_reset, cmd_tbl_t *,
int , int , char * const [])
EXPORT_FUNC(getenv, char *, getenv, const char*)
EXPORT_FUNC(setenv, int, setenv, const char *, const char *)
EXPORT_FUNC(simple_strtoul, unsigned long, simple_strtoul,
const char *, char **, unsigned int)
EXPORT_FUNC(strict_strtoul, int, strict_strtoul,
const char *, unsigned int , unsigned long *)
EXPORT_FUNC(simple_strtol, long, simple_strtol,
const char *, char **, unsigned int)
EXPORT_FUNC(strcmp, int, strcmp, const char *cs, const char *ct)
#if defined(CONFIG_CMD_I2C) && \
(!defined(CONFIG_DM_I2C) || defined(CONFIG_DM_I2C_COMPAT))
EXPORT_FUNC(i2c_write, int, i2c_write, uchar, uint, int , uchar * , int)
EXPORT_FUNC(i2c_read, int, i2c_read, uchar, uint, int , uchar * , int)
#else
EXPORT_FUNC(dummy, void, i2c_write, void)
EXPORT_FUNC(dummy, void, i2c_read, void)
#endif
#if !defined(CONFIG_CMD_SPI) || defined(CONFIG_DM_SPI)
EXPORT_FUNC(dummy, void, spi_init, void)
EXPORT_FUNC(dummy, void, spi_setup_slave, void)
EXPORT_FUNC(dummy, void, spi_free_slave, void)
#else
EXPORT_FUNC(spi_init, void, spi_init, void)
EXPORT_FUNC(spi_setup_slave, struct spi_slave *, spi_setup_slave,
unsigned int, unsigned int, unsigned int, unsigned int)
EXPORT_FUNC(spi_free_slave, void, spi_free_slave, struct spi_slave *)
#endif
#ifndef CONFIG_CMD_SPI
EXPORT_FUNC(dummy, void, spi_claim_bus, void)
EXPORT_FUNC(dummy, void, spi_release_bus, void)
EXPORT_FUNC(dummy, void, spi_xfer, void)
#else
EXPORT_FUNC(spi_claim_bus, int, spi_claim_bus, struct spi_slave *)
EXPORT_FUNC(spi_release_bus, void, spi_release_bus, struct spi_slave *)
EXPORT_FUNC(spi_xfer, int, spi_xfer, struct spi_slave *,
unsigned int, const void *, void *, unsigned long)
#endif
EXPORT_FUNC(ustrtoul, unsigned long, ustrtoul,
const char *, char **, unsigned int)
EXPORT_FUNC(ustrtoull, unsigned long long, ustrtoull,
const char *, char **, unsigned int)

260
include/asm-generic/atomic-long.h Normal file
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@@ -0,0 +1,260 @@
#ifndef _ASM_GENERIC_ATOMIC_LONG_H
#define _ASM_GENERIC_ATOMIC_LONG_H
/*
* Copyright (C) 2005 Silicon Graphics, Inc.
* Christoph Lameter
*
* Allows to provide arch independent atomic definitions without the need to
* edit all arch specific atomic.h files.
*/
#include <asm/types.h>
/*
* Suppport for atomic_long_t
*
* Casts for parameters are avoided for existing atomic functions in order to
* avoid issues with cast-as-lval under gcc 4.x and other limitations that the
* macros of a platform may have.
*/
#if BITS_PER_LONG == 64
typedef atomic64_t atomic_long_t;
#define ATOMIC_LONG_INIT(i) ATOMIC64_INIT(i)
static inline long atomic_long_read(atomic_long_t *l)
{
atomic64_t *v = (atomic64_t *)l;
return (long)atomic64_read(v);
}
static inline void atomic_long_set(atomic_long_t *l, long i)
{
atomic64_t *v = (atomic64_t *)l;
atomic64_set(v, i);
}
static inline void atomic_long_inc(atomic_long_t *l)
{
atomic64_t *v = (atomic64_t *)l;
atomic64_inc(v);
}
static inline void atomic_long_dec(atomic_long_t *l)
{
atomic64_t *v = (atomic64_t *)l;
atomic64_dec(v);
}
static inline void atomic_long_add(long i, atomic_long_t *l)
{
atomic64_t *v = (atomic64_t *)l;
atomic64_add(i, v);
}
static inline void atomic_long_sub(long i, atomic_long_t *l)
{
atomic64_t *v = (atomic64_t *)l;
atomic64_sub(i, v);
}
static inline int atomic_long_sub_and_test(long i, atomic_long_t *l)
{
atomic64_t *v = (atomic64_t *)l;
return atomic64_sub_and_test(i, v);
}
static inline int atomic_long_dec_and_test(atomic_long_t *l)
{
atomic64_t *v = (atomic64_t *)l;
return atomic64_dec_and_test(v);
}
static inline int atomic_long_inc_and_test(atomic_long_t *l)
{
atomic64_t *v = (atomic64_t *)l;
return atomic64_inc_and_test(v);
}
static inline int atomic_long_add_negative(long i, atomic_long_t *l)
{
atomic64_t *v = (atomic64_t *)l;
return atomic64_add_negative(i, v);
}
static inline long atomic_long_add_return(long i, atomic_long_t *l)
{
atomic64_t *v = (atomic64_t *)l;
return (long)atomic64_add_return(i, v);
}
static inline long atomic_long_sub_return(long i, atomic_long_t *l)
{
atomic64_t *v = (atomic64_t *)l;
return (long)atomic64_sub_return(i, v);
}
static inline long atomic_long_inc_return(atomic_long_t *l)
{
atomic64_t *v = (atomic64_t *)l;
return (long)atomic64_inc_return(v);
}
static inline long atomic_long_dec_return(atomic_long_t *l)
{
atomic64_t *v = (atomic64_t *)l;
return (long)atomic64_dec_return(v);
}
static inline long atomic_long_add_unless(atomic_long_t *l, long a, long u)
{
atomic64_t *v = (atomic64_t *)l;
return (long)atomic64_add_unless(v, a, u);
}
#define atomic_long_inc_not_zero(l) atomic64_inc_not_zero((atomic64_t *)(l))
#define atomic_long_cmpxchg(l, old, new) \
(atomic64_cmpxchg((atomic64_t *)(l), (old), (new)))
#define atomic_long_xchg(v, new) \
(atomic64_xchg((atomic64_t *)(v), (new)))
#else /* BITS_PER_LONG == 64 */
typedef atomic_t atomic_long_t;
#define ATOMIC_LONG_INIT(i) ATOMIC_INIT(i)
static inline long atomic_long_read(atomic_long_t *l)
{
atomic_t *v = (atomic_t *)l;
return (long)atomic_read(v);
}
static inline void atomic_long_set(atomic_long_t *l, long i)
{
atomic_t *v = (atomic_t *)l;
atomic_set(v, i);
}
static inline void atomic_long_inc(atomic_long_t *l)
{
atomic_t *v = (atomic_t *)l;
atomic_inc(v);
}
static inline void atomic_long_dec(atomic_long_t *l)
{
atomic_t *v = (atomic_t *)l;
atomic_dec(v);
}
static inline void atomic_long_add(long i, atomic_long_t *l)
{
atomic_t *v = (atomic_t *)l;
atomic_add(i, v);
}
static inline void atomic_long_sub(long i, atomic_long_t *l)
{
atomic_t *v = (atomic_t *)l;
atomic_sub(i, v);
}
#ifndef __UBOOT__
static inline int atomic_long_sub_and_test(long i, atomic_long_t *l)
{
atomic_t *v = (atomic_t *)l;
return atomic_sub_and_test(i, v);
}
static inline int atomic_long_dec_and_test(atomic_long_t *l)
{
atomic_t *v = (atomic_t *)l;
return atomic_dec_and_test(v);
}
static inline int atomic_long_inc_and_test(atomic_long_t *l)
{
atomic_t *v = (atomic_t *)l;
return atomic_inc_and_test(v);
}
static inline int atomic_long_add_negative(long i, atomic_long_t *l)
{
atomic_t *v = (atomic_t *)l;
return atomic_add_negative(i, v);
}
static inline long atomic_long_add_return(long i, atomic_long_t *l)
{
atomic_t *v = (atomic_t *)l;
return (long)atomic_add_return(i, v);
}
static inline long atomic_long_sub_return(long i, atomic_long_t *l)
{
atomic_t *v = (atomic_t *)l;
return (long)atomic_sub_return(i, v);
}
static inline long atomic_long_inc_return(atomic_long_t *l)
{
atomic_t *v = (atomic_t *)l;
return (long)atomic_inc_return(v);
}
static inline long atomic_long_dec_return(atomic_long_t *l)
{
atomic_t *v = (atomic_t *)l;
return (long)atomic_dec_return(v);
}
static inline long atomic_long_add_unless(atomic_long_t *l, long a, long u)
{
atomic_t *v = (atomic_t *)l;
return (long)atomic_add_unless(v, a, u);
}
#define atomic_long_inc_not_zero(l) atomic_inc_not_zero((atomic_t *)(l))
#define atomic_long_cmpxchg(l, old, new) \
(atomic_cmpxchg((atomic_t *)(l), (old), (new)))
#define atomic_long_xchg(v, new) \
(atomic_xchg((atomic_t *)(v), (new)))
#endif /* __UBOOT__ */
#endif /* BITS_PER_LONG == 64 */
#endif /* _ASM_GENERIC_ATOMIC_LONG_H */

2
include/asm-generic/global_data.h
View File

@@ -73,7 +73,7 @@ typedef struct global_data {
const void *fdt_blob; /* Our device tree, NULL if none */
void *new_fdt; /* Relocated FDT */
unsigned long fdt_size; /* Space reserved for relocated FDT */
void **jt; /* jump table */
struct jt_funcs *jt; /* jump table */
char env_buf[32]; /* buffer for getenv() before reloc. */
#ifdef CONFIG_TRACE
void *trace_buff; /* The trace buffer */

265
include/asm-generic/gpio.h
View File

@@ -10,6 +10,15 @@
/*
* Generic GPIO API for U-Boot
*
* --
* NB: This is deprecated. Please use the driver model functions instead:
*
* - gpio_request_by_name()
* - dm_gpio_get_value() etc.
*
* For now we need a dm_ prefix on some functions to avoid name collision.
* --
*
* GPIOs are numbered from 0 to GPIO_COUNT-1 which value is defined
* by the SOC/architecture.
*
@@ -26,6 +35,7 @@
*/
/**
* @deprecated Please use driver model instead
* Request a GPIO. This should be called before any of the other functions
* are used on this GPIO.
*
@@ -39,6 +49,7 @@
int gpio_request(unsigned gpio, const char *label);
/**
* @deprecated Please use driver model instead
* Stop using the GPIO. This function should not alter pin configuration.
*
* @param gpio GPIO number
@@ -47,6 +58,7 @@ int gpio_request(unsigned gpio, const char *label);
int gpio_free(unsigned gpio);
/**
* @deprecated Please use driver model instead
* Make a GPIO an input.
*
* @param gpio GPIO number
@@ -55,6 +67,7 @@ int gpio_free(unsigned gpio);
int gpio_direction_input(unsigned gpio);
/**
* @deprecated Please use driver model instead
* Make a GPIO an output, and set its value.
*
* @param gpio GPIO number
@@ -64,6 +77,7 @@ int gpio_direction_input(unsigned gpio);
int gpio_direction_output(unsigned gpio, int value);
/**
* @deprecated Please use driver model instead
* Get a GPIO's value. This will work whether the GPIO is an input
* or an output.
*
@@ -73,6 +87,7 @@ int gpio_direction_output(unsigned gpio, int value);
int gpio_get_value(unsigned gpio);
/**
* @deprecated Please use driver model instead
* Set an output GPIO's value. The GPIO must already be an output or
* this function may have no effect.
*
@@ -95,6 +110,34 @@ enum gpio_func_t {
struct udevice;
struct gpio_desc {
struct udevice *dev; /* Device, NULL for invalid GPIO */
unsigned long flags;
#define GPIOD_REQUESTED (1 << 0) /* Requested/claimed */
#define GPIOD_IS_OUT (1 << 1) /* GPIO is an output */
#define GPIOD_IS_IN (1 << 2) /* GPIO is an output */
#define GPIOD_ACTIVE_LOW (1 << 3) /* value has active low */
#define GPIOD_IS_OUT_ACTIVE (1 << 4) /* set output active */
uint offset; /* GPIO offset within the device */
/*
* We could consider adding the GPIO label in here. Possibly we could
* use this structure for internal GPIO information.
*/
};
/**
* dm_gpio_is_valid() - Check if a GPIO is gpio_is_valie
*
* @desc: GPIO description containing device, offset and flags,
* previously returned by gpio_request_by_name()
* @return true if valid, false if not
*/
static inline bool dm_gpio_is_valid(struct gpio_desc *desc)
{
return desc->dev != NULL;
}
/**
* gpio_get_status() - get the current GPIO status as a string
*
@@ -106,6 +149,8 @@ struct udevice;
* which means this is GPIO bank b, offset 4, currently set to input, current
* value 1, [x] means that it is requested and the owner is 'sdmmc_cd'
*
* TODO(sjg@chromium.org): This should use struct gpio_desc
*
* @dev: Device to check
* @offset: Offset of device GPIO to check
* @buf: Place to put string
@@ -118,6 +163,8 @@ int gpio_get_status(struct udevice *dev, int offset, char *buf, int buffsize);
*
* Note this returns GPIOF_UNUSED if the GPIO is not requested.
*
* TODO(sjg@chromium.org): This should use struct gpio_desc
*
* @dev: Device to check
* @offset: Offset of device GPIO to check
* @namep: If non-NULL, this is set to the nane given when the GPIO
@@ -135,6 +182,8 @@ int gpio_get_function(struct udevice *dev, int offset, const char **namep);
* Note this does not return GPIOF_UNUSED - it will always return the GPIO
* driver's view of a pin function, even if it is not correctly set up.
*
* TODO(sjg@chromium.org): This should use struct gpio_desc
*
* @dev: Device to check
* @offset: Offset of device GPIO to check
* @namep: If non-NULL, this is set to the nane given when the GPIO
@@ -155,6 +204,8 @@ int gpio_get_raw_function(struct udevice *dev, int offset, const char **namep);
int gpio_requestf(unsigned gpio, const char *fmt, ...)
__attribute__ ((format (__printf__, 2, 3)));
struct fdtdec_phandle_args;
/**
* struct struct dm_gpio_ops - Driver model GPIO operations
*
@@ -198,6 +249,33 @@ struct dm_gpio_ops {
* @return current function - GPIOF_...
*/
int (*get_function)(struct udevice *dev, unsigned offset);
/**
* xlate() - Translate phandle arguments into a GPIO description
*
* This function should set up the fields in desc according to the
* information in the arguments. The uclass will have set up:
*
* @desc->dev to @dev
* @desc->flags to 0
* @desc->offset to the value of the first argument in args, if any,
* otherwise -1 (which is invalid)
*
* This method is optional so if the above defaults suit it can be
* omitted. Typical behaviour is to set up the GPIOD_ACTIVE_LOW flag
* in desc->flags.
*
* Note that @dev is passed in as a parameter to follow driver model
* uclass conventions, even though it is already available as
* desc->dev.
*
* @dev: GPIO device
* @desc: Place to put GPIO description
* @args: Arguments provided in descripion
* @return 0 if OK, -ve on error
*/
int (*xlate)(struct udevice *dev, struct gpio_desc *desc,
struct fdtdec_phandle_args *args);
};
/**
@@ -268,4 +346,191 @@ int gpio_lookup_name(const char *name, struct udevice **devp,
*/
unsigned gpio_get_values_as_int(const int *gpio_list);
/**
* gpio_request_by_name() - Locate and request a GPIO by name
*
* This operates by looking up the given list name in the device (device
* tree property) and requesting the GPIO for use. The property must exist
* in @dev's node.
*
* Use @flags to specify whether the GPIO should be an input or output. In
* principle this can also come from the device tree binding but most
* bindings don't provide this information. Specifically, when the GPIO uclass
* calls the xlate() method, it can return default flags, which are then
* ORed with this @flags.
*
* If we find that requesting the GPIO is not always needed we could add a
* new function or a new GPIOD_NO_REQUEST flag.
*
* At present driver model has no reference counting so if one device
* requests a GPIO which subsequently is unbound, the @desc->dev pointer
* will be invalid. However this will only happen if the GPIO device is
* unbound, not if it is removed, so this seems like a reasonable limitation
* for now. There is no real use case for unbinding drivers in normal
* operation.
*
* The device tree binding is doc/device-tree-bindings/gpio/gpio.txt in
* generate terms and each specific device may add additional details in
* a binding file in the same directory.
*
* @dev: Device requesting the GPIO
* @list_name: Name of GPIO list (e.g. "board-id-gpios")
* @index: Index number of the GPIO in that list use request (0=first)
* @desc: Returns GPIO description information. If there is no such
* GPIO, dev->dev will be NULL.
* @flags: Indicates the GPIO input/output settings (GPIOD_...)
* @return 0 if OK, -ENOENT if the GPIO does not exist, -EINVAL if there is
* something wrong with the list, or other -ve for another error (e.g.
* -EBUSY if a GPIO was already requested)
*/
int gpio_request_by_name(struct udevice *dev, const char *list_name,
int index, struct gpio_desc *desc, int flags);
/**
* gpio_request_list_by_name() - Request a list of GPIOs
*
* Reads all the GPIOs from a list and requetss them. See
* gpio_request_by_name() for additional details. Lists should not be
* misused to hold unrelated or optional GPIOs. They should only be used
* for things like parallel data lines. A zero phandle terminates the list
* the list.
*
* This function will either succeed, and request all GPIOs in the list, or
* fail and request none (it will free already-requested GPIOs in case of
* an error part-way through).
*
* @dev: Device requesting the GPIO
* @list_name: Name of GPIO list (e.g. "board-id-gpios")
* @desc_list: Returns a list of GPIO description information
* @max_count: Maximum number of GPIOs to return (@desc_list must be at least
* this big)
* @flags: Indicates the GPIO input/output settings (GPIOD_...)
* @return number of GPIOs requested, or -ve on error
*/
int gpio_request_list_by_name(struct udevice *dev, const char *list_name,
struct gpio_desc *desc_list, int max_count,
int flags);
/**
* gpio_get_list_count() - Returns the number of GPIOs in a list
*
* Counts the GPIOs in a list. See gpio_request_by_name() for additional
* details.
*
* @dev: Device requesting the GPIO
* @list_name: Name of GPIO list (e.g. "board-id-gpios")
* @return number of GPIOs (0 for an empty property) or -ENOENT if the list
* does not exist
*/
int gpio_get_list_count(struct udevice *dev, const char *list_name);
/**
* gpio_request_by_name_nodev() - request GPIOs without a device
*
* This is a version of gpio_request_list_by_name() that does not use a
* device. Avoid it unless the caller is not yet using driver model
*/
int gpio_request_by_name_nodev(const void *blob, int node,
const char *list_name,
int index, struct gpio_desc *desc, int flags);
/**
* gpio_request_list_by_name_nodev() - request GPIOs without a device
*
* This is a version of gpio_request_list_by_name() that does not use a
* device. Avoid it unless the caller is not yet using driver model
*/
int gpio_request_list_by_name_nodev(const void *blob, int node,
const char *list_name,
struct gpio_desc *desc_list, int max_count,
int flags);
/**
* dm_gpio_free() - Free a single GPIO
*
* This frees a single GPIOs previously returned from gpio_request_by_name().
*
* @dev: Device which requested the GPIO
* @desc: GPIO to free
* @return 0 if OK, -ve on error
*/
int dm_gpio_free(struct udevice *dev, struct gpio_desc *desc);
/**
* gpio_free_list() - Free a list of GPIOs
*
* This frees a list of GPIOs previously returned from
* gpio_request_list_by_name().
*
* @dev: Device which requested the GPIOs
* @desc: List of GPIOs to free
* @count: Number of GPIOs in the list
* @return 0 if OK, -ve on error
*/
int gpio_free_list(struct udevice *dev, struct gpio_desc *desc, int count);
/**
* gpio_free_list_nodev() - free GPIOs without a device
*
* This is a version of gpio_free_list() that does not use a
* device. Avoid it unless the caller is not yet using driver model
*/
int gpio_free_list_nodev(struct gpio_desc *desc, int count);
/**
* dm_gpio_get_value() - Get the value of a GPIO
*
* This is the driver model version of the existing gpio_get_value() function
* and should be used instead of that.
*
* For now, these functions have a dm_ prefix since they conflict with
* existing names.
*
* @desc: GPIO description containing device, offset and flags,
* previously returned by gpio_request_by_name()
* @return GPIO value (0 for inactive, 1 for active) or -ve on error
*/
int dm_gpio_get_value(struct gpio_desc *desc);
int dm_gpio_set_value(struct gpio_desc *desc, int value);
/**
* dm_gpio_set_dir() - Set the direction for a GPIO
*
* This sets up the direction according tot the provided flags. It will do
* nothing unless the direction is actually specified.
*
* @desc: GPIO description containing device, offset and flags,
* previously returned by gpio_request_by_name()
* @return 0 if OK, -ve on error
*/
int dm_gpio_set_dir(struct gpio_desc *desc);
/**
* dm_gpio_set_dir_flags() - Set direction using specific flags
*
* This is like dm_gpio_set_dir() except that the flags value is provided
* instead of being used from desc->flags. This is needed because in many
* cases the GPIO description does not include direction information.
* Note that desc->flags is updated by this function.
*
* @desc: GPIO description containing device, offset and flags,
* previously returned by gpio_request_by_name()
* @flags: New flags to use
* @return 0 if OK, -ve on error, in which case desc->flags is not updated
*/
int dm_gpio_set_dir_flags(struct gpio_desc *desc, ulong flags);
/**
* gpio_get_number() - Get the global GPIO number of a GPIO
*
* This should only be used for debugging or interest. It returns the nummber
* that should be used for gpio_get_value() etc. to access this GPIO.
*
* @desc: GPIO description containing device, offset and flags,
* previously returned by gpio_request_by_name()
* @return GPIO number, or -ve if not found
*/
int gpio_get_number(struct gpio_desc *desc);
#endif /* _ASM_GENERIC_GPIO_H_ */

38
include/atmel_lcd.h Normal file
View File

@@ -0,0 +1,38 @@
/*
* atmel_lcd.h - Atmel LCD Controller structures
*
* (C) Copyright 2001
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _ATMEL_LCD_H_
#define _ATMEL_LCD_H_
typedef struct vidinfo {
ushort vl_col; /* Number of columns (i.e. 640) */
ushort vl_row; /* Number of rows (i.e. 480) */
u_long vl_clk; /* pixel clock in ps */
/* LCD configuration register */
u_long vl_sync; /* Horizontal / vertical sync */
u_long vl_bpix; /* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8, 4 = 16 */
u_long vl_tft; /* 0 = passive, 1 = TFT */
u_long vl_cont_pol_low; /* contrast polarity is low */
u_long vl_clk_pol; /* clock polarity */
/* Horizontal control register. */
u_long vl_hsync_len; /* Length of horizontal sync */
u_long vl_left_margin; /* Time from sync to picture */
u_long vl_right_margin; /* Time from picture to sync */
/* Vertical control register. */
u_long vl_vsync_len; /* Length of vertical sync */
u_long vl_upper_margin; /* Time from sync to picture */
u_long vl_lower_margin; /* Time from picture to sync */
u_long mmio; /* Memory mapped registers */
} vidinfo_t;
#endif

8
include/axp221.h
View File

@@ -12,7 +12,6 @@
#define AXP223_DEVICE_ADDR 0x3a3
#define AXP223_RUNTIME_ADDR 0x2d
#define AXP223_DEVICE_MODE_DATA 0x7c3e00
/* Page 0 addresses */
#define AXP221_CHIP_ID 0x03
@@ -26,6 +25,9 @@
#define AXP221_OUTPUT_CTRL1_ALDO1_EN (1 << 6)
#define AXP221_OUTPUT_CTRL1_ALDO2_EN (1 << 7)
#define AXP221_OUTPUT_CTRL2 0x12
#define AXP221_OUTPUT_CTRL2_ELDO1_EN (1 << 0)
#define AXP221_OUTPUT_CTRL2_ELDO2_EN (1 << 1)
#define AXP221_OUTPUT_CTRL2_ELDO3_EN (1 << 2)
#define AXP221_OUTPUT_CTRL2_DLDO1_EN (1 << 3)
#define AXP221_OUTPUT_CTRL2_DLDO2_EN (1 << 4)
#define AXP221_OUTPUT_CTRL2_DLDO3_EN (1 << 5)
@@ -37,6 +39,9 @@
#define AXP221_DLDO2_CTRL 0x16
#define AXP221_DLDO3_CTRL 0x17
#define AXP221_DLDO4_CTRL 0x18
#define AXP221_ELDO1_CTRL 0x19
#define AXP221_ELDO2_CTRL 0x1a
#define AXP221_ELDO3_CTRL 0x1b
#define AXP221_DCDC1_CTRL 0x21
#define AXP221_DCDC2_CTRL 0x22
#define AXP221_DCDC3_CTRL 0x23
@@ -69,6 +74,7 @@ int axp221_set_dldo4(unsigned int mvolt);
int axp221_set_aldo1(unsigned int mvolt);
int axp221_set_aldo2(unsigned int mvolt);
int axp221_set_aldo3(unsigned int mvolt);
int axp221_set_eldo(int eldo_num, unsigned int mvolt);
int axp221_init(void);
int axp221_get_sid(unsigned int *sid);
int axp_drivebus_enable(void);

5
include/bootstage.h
View File

@@ -86,9 +86,9 @@ enum bootstage_id {
BOOTSTAGE_ID_POST_FAIL_R, /* Post failure reported after reloc */
/*
* This set is reported ony by x86, and the meaning is different. In
* This set is reported only by x86, and the meaning is different. In
* this case we are reporting completion of a particular stage.
* This should probably change in he x86 code (which doesn't report
* This should probably change in the x86 code (which doesn't report
* errors in any case), but discussion this can perhaps wait until we
* have a generic board implementation.
*/
@@ -194,6 +194,7 @@ enum bootstage_id {
BOOTSTAGE_ID_MAIN_CPU_READY,
BOOTSTAGE_ID_ACCUM_LCD,
BOOTSTAGE_ID_ACCUM_SCSI,
/* a few spare for the user, from here */
BOOTSTAGE_ID_USER,

14
include/common.h
View File

@@ -183,6 +183,7 @@ typedef void (interrupt_handler_t)(void *);
/*
* Function Prototypes
*/
int dram_init(void);
void hang (void) __attribute__ ((noreturn));
@@ -228,12 +229,13 @@ int run_command_list(const char *cmd, int len, int flag);
extern char console_buffer[];
/* arch/$(ARCH)/lib/board.c */
void board_init_f(ulong);
void board_init_r (gd_t *, ulong) __attribute__ ((noreturn));
int checkboard (void);
int checkflash (void);
int checkdram (void);
int last_stage_init(void);
void board_init_f(ulong);
void board_init_r(gd_t *, ulong) __attribute__ ((noreturn));
int checkboard(void);
int show_board_info(void);
int checkflash(void);
int checkdram(void);
int last_stage_init(void);
extern ulong monitor_flash_len;
int mac_read_from_eeprom(void);
extern u8 __dtb_dt_begin[]; /* embedded device tree blob */

33
include/config_distro_bootcmd.h
View File

@@ -13,7 +13,7 @@
#define BOOTENV_SHARED_BLKDEV_BODY(devtypel) \
"if " #devtypel " dev ${devnum}; then " \
"setenv devtype " #devtypel "; " \
"run scan_dev_for_boot; " \
"run scan_dev_for_boot_part; " \
"fi\0"
#define BOOTENV_SHARED_BLKDEV(devtypel) \
@@ -90,15 +90,8 @@
#endif
#ifdef CONFIG_CMD_USB
#define BOOTENV_RUN_USB_INIT "run usb_init; "
#define BOOTENV_SET_USB_NEED_INIT "setenv usb_need_init; "
#define BOOTENV_RUN_USB_INIT "usb start; "
#define BOOTENV_SHARED_USB \
"usb_init=" \
"if ${usb_need_init}; then " \
"setenv usb_need_init false; " \
"usb start 0; " \
"fi\0" \
\
"usb_boot=" \
BOOTENV_RUN_USB_INIT \
BOOTENV_SHARED_BLKDEV_BODY(usb)
@@ -106,7 +99,6 @@
#define BOOTENV_DEV_NAME_USB BOOTENV_DEV_NAME_BLKDEV
#else
#define BOOTENV_RUN_USB_INIT
#define BOOTENV_SET_USB_NEED_INIT
#define BOOTENV_SHARED_USB
#define BOOTENV_DEV_USB \
BOOT_TARGET_DEVICES_references_USB_without_CONFIG_CMD_USB
@@ -118,7 +110,7 @@
#define BOOTENV_DEV_DHCP(devtypeu, devtypel, instance) \
"bootcmd_dhcp=" \
BOOTENV_RUN_USB_INIT \
"if dhcp ${scriptaddr} boot.scr.uimg; then " \
"if dhcp ${scriptaddr} ${boot_script_dhcp}; then " \
"source ${scriptaddr}; " \
"fi\0"
#define BOOTENV_DEV_NAME_DHCP(devtypeu, devtypel, instance) \
@@ -162,8 +154,8 @@
BOOTENV_SHARED_IDE \
"boot_prefixes=/ /boot/\0" \
"boot_scripts=boot.scr.uimg boot.scr\0" \
"boot_script_dhcp=boot.scr.uimg\0" \
BOOTENV_BOOT_TARGETS \
"bootpart=1\0" \
\
"boot_extlinux=" \
"sysboot ${devtype} ${devnum}:${bootpart} any " \
@@ -194,17 +186,30 @@
"done\0" \
\
"scan_dev_for_boot=" \
"echo Scanning ${devtype} ${devnum}...; " \
"echo Scanning ${devtype} ${devnum}:${bootpart}...; " \
"for prefix in ${boot_prefixes}; do " \
"run scan_dev_for_extlinux; " \
"run scan_dev_for_scripts; " \
"done\0" \
\
"scan_dev_for_boot_part=" \
"part list ${devtype} ${devnum} devplist; " \
"for bootpart in ${devplist}; do " \
"if fstype ${devtype} ${devnum}:${bootpart} " \
"bootfstype; then " \
"run scan_dev_for_boot; " \
"fi; " \
"done\0" \
\
BOOT_TARGET_DEVICES(BOOTENV_DEV) \
\
"bootcmd=" BOOTENV_SET_USB_NEED_INIT BOOTENV_SET_SCSI_NEED_INIT \
"distro_bootcmd=" BOOTENV_SET_SCSI_NEED_INIT \
"for target in ${boot_targets}; do " \
"run bootcmd_${target}; " \
"done\0"
#ifndef CONFIG_BOOTCOMMAND
#define CONFIG_BOOTCOMMAND "run distro_bootcmd"
#endif
#endif /* _CONFIG_CMD_DISTRO_BOOTCMD_H */

1
include/configs/BSC9131RDB.h
View File

@@ -433,6 +433,7 @@ extern unsigned long get_sdram_size(void);
#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
#define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTDELAY 10 /* -1 disable auto-boot */
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \

1
include/configs/BSC9132QDS.h
View File

@@ -675,6 +675,7 @@ combinations. this should be removed later
#define CONFIG_UBOOTPATH "u-boot.bin"
#define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTDELAY 10 /* -1 disable auto-boot */
#ifdef CONFIG_SDCARD
#define CONFIG_DEF_HWCONFIG "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"

2
include/configs/C29XPCIE.h
View File

@@ -581,4 +581,6 @@
#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
#include <asm/fsl_secure_boot.h>
#endif /* __CONFIG_H */

750
include/configs/CATcenter.h
View File

@@ -1,750 +0,0 @@
/*
* ueberarbeitet durch Christoph Seyfert
*
* (C) Copyright 2004-2005 DENX Software Engineering,
* Wolfgang Grandegger <wg@denx.de>
* (C) Copyright 2003
* DAVE Srl
*
* http://www.dave-tech.it
* http://www.wawnet.biz
* mailto:info@wawnet.biz
*
* Credits: Stefan Roese, Wolfgang Denk
*
* SPDX-License-Identifier: GPL-2.0+
*/
/*
* board/config.h - configuration options, board specific
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_PPCHAMELEON_MODULE_BA 0 /* Basic Model */
#define CONFIG_PPCHAMELEON_MODULE_ME 1 /* Medium Model */
#define CONFIG_PPCHAMELEON_MODULE_HI 2 /* High-End Model */
#ifndef CONFIG_PPCHAMELEON_MODULE_MODEL
#define CONFIG_PPCHAMELEON_MODULE_MODEL CONFIG_PPCHAMELEON_MODULE_BA
#endif
/* Only one of the following two symbols must be defined (default is 25 MHz)
* CONFIG_PPCHAMELEON_CLK_25
* CONFIG_PPCHAMELEON_CLK_33
*/
#if (!defined(CONFIG_PPCHAMELEON_CLK_25) && !defined(CONFIG_PPCHAMELEON_CLK_33))
#define CONFIG_PPCHAMELEON_CLK_25
#endif
#if (defined(CONFIG_PPCHAMELEON_CLK_25) && defined(CONFIG_PPCHAMELEON_CLK_33))
#error "* Two external frequencies (SysClk) are defined! *"
#endif
#undef CONFIG_PPCHAMELEON_SMI712
/*
* Debug stuff
*/
#undef __DEBUG_START_FROM_SRAM__
#define __DISABLE_MACHINE_EXCEPTION__
#ifdef __DEBUG_START_FROM_SRAM__
#define CONFIG_SYS_DUMMY_FLASH_SIZE 1024*1024*4
#endif
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_405EP 1 /* This is a PPC405 CPU */
#define CONFIG_PPCHAMELEONEVB 1 /* ...on a PPChameleonEVB board */
#define CONFIG_SYS_TEXT_BASE 0xFFFB0000 /* Reserve 320 kB for Monitor */
#define CONFIG_SYS_LDSCRIPT "board/dave/PPChameleonEVB/u-boot.lds"
#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
#ifdef CONFIG_PPCHAMELEON_CLK_25
# define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */
#elif (defined (CONFIG_PPCHAMELEON_CLK_33))
#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
#else
# error "* External frequency (SysClk) not defined! *"
#endif
#define CONFIG_CONS_INDEX 2 /* Use UART1 */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
#define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#define CONFIG_VERSION_VARIABLE 1 /* add version variable */
#define CONFIG_IDENT_STRING "1"
#undef CONFIG_BOOTARGS
/* Ethernet stuff */
#define CONFIG_ENV_OVERWRITE /* Let the user to change the Ethernet MAC addresses */
#define CONFIG_ETHADDR 00:50:C2:1E:AF:FE
#define CONFIG_HAS_ETH1
#define CONFIG_ETH1ADDR 00:50:C2:1E:AF:FD
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_PPC4xx_EMAC
#undef CONFIG_EXT_PHY
#define CONFIG_MII 1 /* MII PHY management */
#ifndef CONFIG_EXT_PHY
#define CONFIG_PHY_ADDR 1 /* EMAC0 PHY address */
#define CONFIG_PHY1_ADDR 16 /* EMAC1 PHY address */
#else
#define CONFIG_PHY_ADDR 2 /* PHY address */
#endif
#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ
#define CONFIG_TIMESTAMP /* Print image info with timestamp */
/*
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ELF
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_MII
#define CONFIG_CMD_NAND
#define CONFIG_CMD_NFS
#define CONFIG_CMD_SNTP
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/
#define CONFIG_SYS_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */
#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
#define CONFIG_SYS_BASE_BAUD 691200
/* The following table includes the supported baudrates */
#define CONFIG_SYS_BAUDRATE_TABLE \
{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
57600, 115200, 230400, 460800, 921600 }
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
/*-----------------------------------------------------------------------
* NAND-FLASH stuff
*-----------------------------------------------------------------------
*/
#define CONFIG_SYS_NAND0_BASE 0xFF400000
#define CONFIG_SYS_NAND1_BASE 0xFF000000
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE }
#define NAND_BIG_DELAY_US 25
/* For CATcenter there is only NAND on the module */
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define NAND_NO_RB
#define CONFIG_SYS_NAND0_CE (0x80000000 >> 1) /* our CE is GPIO1 */
#define CONFIG_SYS_NAND0_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
#define CONFIG_SYS_NAND0_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
#define CONFIG_SYS_NAND0_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
#define CONFIG_SYS_NAND1_CE (0x80000000 >> 14) /* our CE is GPIO14 */
#define CONFIG_SYS_NAND1_CLE (0x80000000 >> 15) /* our CLE is GPIO15 */
#define CONFIG_SYS_NAND1_ALE (0x80000000 >> 16) /* our ALE is GPIO16 */
#define CONFIG_SYS_NAND1_RDY (0x80000000 >> 31) /* our RDY is GPIO31 */
#define MACRO_NAND_DISABLE_CE(nandptr) do \
{ \
switch((unsigned long)nandptr) \
{ \
case CONFIG_SYS_NAND0_BASE: \
out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND0_CE); \
break; \
case CONFIG_SYS_NAND1_BASE: \
out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND1_CE); \
break; \
} \
} while(0)
#define MACRO_NAND_ENABLE_CE(nandptr) do \
{ \
switch((unsigned long)nandptr) \
{ \
case CONFIG_SYS_NAND0_BASE: \
out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND0_CE); \
break; \
case CONFIG_SYS_NAND1_BASE: \
out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND1_CE); \
break; \
} \
} while(0)
#define MACRO_NAND_CTL_CLRALE(nandptr) do \
{ \
switch((unsigned long)nandptr) \
{ \
case CONFIG_SYS_NAND0_BASE: \
out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND0_ALE); \
break; \
case CONFIG_SYS_NAND1_BASE: \
out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND1_ALE); \
break; \
} \
} while(0)
#define MACRO_NAND_CTL_SETALE(nandptr) do \
{ \
switch((unsigned long)nandptr) \
{ \
case CONFIG_SYS_NAND0_BASE: \
out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND0_ALE); \
break; \
case CONFIG_SYS_NAND1_BASE: \
out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND1_ALE); \
break; \
} \
} while(0)
#define MACRO_NAND_CTL_CLRCLE(nandptr) do \
{ \
switch((unsigned long)nandptr) \
{ \
case CONFIG_SYS_NAND0_BASE: \
out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND0_CLE); \
break; \
case CONFIG_SYS_NAND1_BASE: \
out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND1_CLE); \
break; \
} \
} while(0)
#define MACRO_NAND_CTL_SETCLE(nandptr) do { \
switch((unsigned long)nandptr) { \
case CONFIG_SYS_NAND0_BASE: \
out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND0_CLE); \
break; \
case CONFIG_SYS_NAND1_BASE: \
out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND1_CLE); \
break; \
} \
} while(0)
#ifdef NAND_NO_RB
/* constant delay (see also tR in the datasheet) */
#define NAND_WAIT_READY(nand) do { \
udelay(12); \
} while (0)
#else
/* use the R/B pin */
/* TBD */
#endif
#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
/*-----------------------------------------------------------------------
* PCI stuff
*-----------------------------------------------------------------------
*/
#if 0 /* No PCI on CATcenter */
#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
#define PCI_HOST_FORCE 1 /* configure as pci host */
#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
#define CONFIG_PCI /* include pci support */
#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
#undef CONFIG_PCI_PNP /* do pci plug-and-play */
/* resource configuration */
#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* PCI Vendor ID: IBM */
#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: --- */
#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
#define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */
#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
#endif /* No PCI */
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
*/
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_FLASH_BASE 0xFFFC0000
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
* FLASH organization
*/
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
/*
* The following defines are added for buggy IOP480 byte interface.
* All other boards should use the standard values (CPCI405 etc.)
*/
#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
/*-----------------------------------------------------------------------
* Environment Variable setup
*/
#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
#define CONFIG_ENV_ADDR 0xFFFF8000 /* environment starts at the first small sector */
#define CONFIG_ENV_SECT_SIZE 0x2000 /* 8196 bytes may be used for env vars*/
#define CONFIG_ENV_ADDR_REDUND 0xFFFFA000
#define CONFIG_ENV_SIZE_REDUND 0x2000
#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
#define CONFIG_SYS_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */
#define CONFIG_SYS_NVRAM_SIZE 242 /* NVRAM size */
/*-----------------------------------------------------------------------
* I2C EEPROM (CAT24WC16) for environment
*/
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_PPC4XX
#define CONFIG_SYS_I2C_PPC4XX_CH0
#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
/* mask of address bits that overflow into the "EEPROM chip address" */
/*#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07*/
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
/* 16 byte page write mode using*/
/* last 4 bits of the address */
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
/*
* Init Memory Controller:
*
* BR0/1 and OR0/1 (FLASH)
*/
#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
/*-----------------------------------------------------------------------
* External Bus Controller (EBC) Setup
*/
/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
#define CONFIG_SYS_EBC_PB0AP 0x92015480
#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
/* Memory Bank 1 (External SRAM) initialization */
/* Since this must replace NOR Flash, we use the same settings for CS0 */
#define CONFIG_SYS_EBC_PB1AP 0x92015480
#define CONFIG_SYS_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit */
/* Memory Bank 2 (Flash Bank 1, NAND-FLASH) initialization */
#define CONFIG_SYS_EBC_PB2AP 0x92015480
#define CONFIG_SYS_EBC_PB2CR 0xFF458000 /* BAS=0xFF4,BS=4MB,BU=R/W,BW=8bit */
/* Memory Bank 3 (Flash Bank 2, NAND-FLASH) initialization */
#define CONFIG_SYS_EBC_PB3AP 0x92015480
#define CONFIG_SYS_EBC_PB3CR 0xFF058000 /* BAS=0xFF0,BS=4MB,BU=R/W,BW=8bit */
#ifdef CONFIG_PPCHAMELEON_SMI712
/*
* Video console (graphic: SMI LynxEM)
*/
#define CONFIG_VIDEO
#define CONFIG_CFB_CONSOLE
#define CONFIG_VIDEO_SMI_LYNXEM
#define CONFIG_VIDEO_LOGO
/*#define CONFIG_VIDEO_BMP_LOGO*/
#define CONFIG_CONSOLE_EXTRA_INFO
#define CONFIG_VGA_AS_SINGLE_DEVICE
/* This is the base address (on 405EP-side) used to generate I/O accesses on PCI bus */
#define CONFIG_SYS_ISA_IO 0xE8000000
/* see also drivers/video/videomodes.c */
#define CONFIG_SYS_DEFAULT_VIDEO_MODE 0x303
#endif
/*-----------------------------------------------------------------------
* FPGA stuff
*/
/* FPGA internal regs */
#define CONFIG_SYS_FPGA_MODE 0x00
#define CONFIG_SYS_FPGA_STATUS 0x02
#define CONFIG_SYS_FPGA_TS 0x04
#define CONFIG_SYS_FPGA_TS_LOW 0x06
#define CONFIG_SYS_FPGA_TS_CAP0 0x10
#define CONFIG_SYS_FPGA_TS_CAP0_LOW 0x12
#define CONFIG_SYS_FPGA_TS_CAP1 0x14
#define CONFIG_SYS_FPGA_TS_CAP1_LOW 0x16
#define CONFIG_SYS_FPGA_TS_CAP2 0x18
#define CONFIG_SYS_FPGA_TS_CAP2_LOW 0x1a
#define CONFIG_SYS_FPGA_TS_CAP3 0x1c
#define CONFIG_SYS_FPGA_TS_CAP3_LOW 0x1e
/* FPGA Mode Reg */
#define CONFIG_SYS_FPGA_MODE_CF_RESET 0x0001
#define CONFIG_SYS_FPGA_MODE_TS_IRQ_ENABLE 0x0100
#define CONFIG_SYS_FPGA_MODE_TS_IRQ_CLEAR 0x1000
#define CONFIG_SYS_FPGA_MODE_TS_CLEAR 0x2000
/* FPGA Status Reg */
#define CONFIG_SYS_FPGA_STATUS_DIP0 0x0001
#define CONFIG_SYS_FPGA_STATUS_DIP1 0x0002
#define CONFIG_SYS_FPGA_STATUS_DIP2 0x0004
#define CONFIG_SYS_FPGA_STATUS_FLASH 0x0008
#define CONFIG_SYS_FPGA_STATUS_TS_IRQ 0x1000
#define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
#define CONFIG_SYS_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/
/* FPGA program pin configuration */
#define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
#define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
#define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
#define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */
#define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in data cache)
*/
/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
#define CONFIG_SYS_TEMP_STACK_OCM 1
/* On Chip Memory location */
#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
* Definitions for GPIO setup (PPC405EP specific)
*
* GPIO0[0] - External Bus Controller BLAST output
* GPIO0[1-9] - Instruction trace outputs -> GPIO
* GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
* GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
* GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
* GPIO0[24-27] - UART0 control signal inputs/outputs
* GPIO0[28-29] - UART1 data signal input/output
* GPIO0[30] - EMAC0 input
* GPIO0[31] - EMAC1 reject packet as output
*/
#define CONFIG_SYS_GPIO0_OSRL 0x40000550
#define CONFIG_SYS_GPIO0_OSRH 0x00000110
#define CONFIG_SYS_GPIO0_ISR1L 0x00000000
/*#define CONFIG_SYS_GPIO0_ISR1H 0x15555445*/
#define CONFIG_SYS_GPIO0_ISR1H 0x15555444
#define CONFIG_SYS_GPIO0_TSRL 0x00000000
#define CONFIG_SYS_GPIO0_TSRH 0x00000000
#define CONFIG_SYS_GPIO0_TCR 0xF7FF8014
#define CONFIG_NO_SERIAL_EEPROM
/*--------------------------------------------------------------------*/
#ifdef CONFIG_NO_SERIAL_EEPROM
/*
!-----------------------------------------------------------------------
! Defines for entry options.
! Note: Because the 405EP SDRAM controller does not support ECC, ECC DIMMs that
! are plugged in the board will be utilized as non-ECC DIMMs.
!-----------------------------------------------------------------------
*/
#undef AUTO_MEMORY_CONFIG
#define DIMM_READ_ADDR 0xAB
#define DIMM_WRITE_ADDR 0xAA
/* Defines for CPC0_PLLMR1 Register fields */
#define PLL_ACTIVE 0x80000000
#define CPC0_PLLMR1_SSCS 0x80000000
#define PLL_RESET 0x40000000
#define CPC0_PLLMR1_PLLR 0x40000000
/* Feedback multiplier */
#define PLL_FBKDIV 0x00F00000
#define CPC0_PLLMR1_FBDV 0x00F00000
#define PLL_FBKDIV_16 0x00000000
#define PLL_FBKDIV_1 0x00100000
#define PLL_FBKDIV_2 0x00200000
#define PLL_FBKDIV_3 0x00300000
#define PLL_FBKDIV_4 0x00400000
#define PLL_FBKDIV_5 0x00500000
#define PLL_FBKDIV_6 0x00600000
#define PLL_FBKDIV_7 0x00700000
#define PLL_FBKDIV_8 0x00800000
#define PLL_FBKDIV_9 0x00900000
#define PLL_FBKDIV_10 0x00A00000
#define PLL_FBKDIV_11 0x00B00000
#define PLL_FBKDIV_12 0x00C00000
#define PLL_FBKDIV_13 0x00D00000
#define PLL_FBKDIV_14 0x00E00000
#define PLL_FBKDIV_15 0x00F00000
/* Forward A divisor */
#define PLL_FWDDIVA 0x00070000
#define CPC0_PLLMR1_FWDVA 0x00070000
#define PLL_FWDDIVA_8 0x00000000
#define PLL_FWDDIVA_7 0x00010000
#define PLL_FWDDIVA_6 0x00020000
#define PLL_FWDDIVA_5 0x00030000
#define PLL_FWDDIVA_4 0x00040000
#define PLL_FWDDIVA_3 0x00050000
#define PLL_FWDDIVA_2 0x00060000
#define PLL_FWDDIVA_1 0x00070000
/* Forward B divisor */
#define PLL_FWDDIVB 0x00007000
#define CPC0_PLLMR1_FWDVB 0x00007000
#define PLL_FWDDIVB_8 0x00000000
#define PLL_FWDDIVB_7 0x00001000
#define PLL_FWDDIVB_6 0x00002000
#define PLL_FWDDIVB_5 0x00003000
#define PLL_FWDDIVB_4 0x00004000
#define PLL_FWDDIVB_3 0x00005000
#define PLL_FWDDIVB_2 0x00006000
#define PLL_FWDDIVB_1 0x00007000
/* PLL tune bits */
#define PLL_TUNE_MASK 0x000003FF
#define PLL_TUNE_2_M_3 0x00000133 /* 2 <= M <= 3 */
#define PLL_TUNE_4_M_6 0x00000134 /* 3 < M <= 6 */
#define PLL_TUNE_7_M_10 0x00000138 /* 6 < M <= 10 */
#define PLL_TUNE_11_M_14 0x0000013C /* 10 < M <= 14 */
#define PLL_TUNE_15_M_40 0x0000023E /* 14 < M <= 40 */
#define PLL_TUNE_VCO_LOW 0x00000000 /* 500MHz <= VCO <= 800MHz */
#define PLL_TUNE_VCO_HI 0x00000080 /* 800MHz < VCO <= 1000MHz */
/* Defines for CPC0_PLLMR0 Register fields */
/* CPU divisor */
#define PLL_CPUDIV 0x00300000
#define CPC0_PLLMR0_CCDV 0x00300000
#define PLL_CPUDIV_1 0x00000000
#define PLL_CPUDIV_2 0x00100000
#define PLL_CPUDIV_3 0x00200000
#define PLL_CPUDIV_4 0x00300000
/* PLB divisor */
#define PLL_PLBDIV 0x00030000
#define CPC0_PLLMR0_CBDV 0x00030000
#define PLL_PLBDIV_1 0x00000000
#define PLL_PLBDIV_2 0x00010000
#define PLL_PLBDIV_3 0x00020000
#define PLL_PLBDIV_4 0x00030000
/* OPB divisor */
#define PLL_OPBDIV 0x00003000
#define CPC0_PLLMR0_OPDV 0x00003000
#define PLL_OPBDIV_1 0x00000000
#define PLL_OPBDIV_2 0x00001000
#define PLL_OPBDIV_3 0x00002000
#define PLL_OPBDIV_4 0x00003000
/* EBC divisor */
#define PLL_EXTBUSDIV 0x00000300
#define CPC0_PLLMR0_EPDV 0x00000300
#define PLL_EXTBUSDIV_2 0x00000000
#define PLL_EXTBUSDIV_3 0x00000100
#define PLL_EXTBUSDIV_4 0x00000200
#define PLL_EXTBUSDIV_5 0x00000300
/* MAL divisor */
#define PLL_MALDIV 0x00000030
#define CPC0_PLLMR0_MPDV 0x00000030
#define PLL_MALDIV_1 0x00000000
#define PLL_MALDIV_2 0x00000010
#define PLL_MALDIV_3 0x00000020
#define PLL_MALDIV_4 0x00000030
/* PCI divisor */
#define PLL_PCIDIV 0x00000003
#define CPC0_PLLMR0_PPFD 0x00000003
#define PLL_PCIDIV_1 0x00000000
#define PLL_PCIDIV_2 0x00000001
#define PLL_PCIDIV_3 0x00000002
#define PLL_PCIDIV_4 0x00000003
#ifdef CONFIG_PPCHAMELEON_CLK_25
/* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 25.0 MHz input clock to the 405EP) */
#define PPCHAMELEON_PLLMR0_133_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \
PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
PLL_MALDIV_1 | PLL_PCIDIV_4)
#define PPCHAMELEON_PLLMR1_133_133_33_66_33 (PLL_FBKDIV_8 | \
PLL_FWDDIVA_6 | PLL_FWDDIVB_4 | \
PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
#define PPCHAMELEON_PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
PLL_MALDIV_1 | PLL_PCIDIV_4)
#define PPCHAMELEON_PLLMR1_200_100_50_33 (PLL_FBKDIV_8 | \
PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \
PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
#define PPCHAMELEON_PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
PLL_MALDIV_1 | PLL_PCIDIV_4)
#define PPCHAMELEON_PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8 | \
PLL_FWDDIVA_3 | PLL_FWDDIVB_4 | \
PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
#define PPCHAMELEON_PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
PLL_MALDIV_1 | PLL_PCIDIV_2)
#define PPCHAMELEON_PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10 | \
PLL_FWDDIVA_3 | PLL_FWDDIVB_4 | \
PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
#elif (defined (CONFIG_PPCHAMELEON_CLK_33))
/* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 33.3MHz input clock to the 405EP) */
#define PPCHAMELEON_PLLMR0_133_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \
PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
PLL_MALDIV_1 | PLL_PCIDIV_4)
#define PPCHAMELEON_PLLMR1_133_133_33_66_33 (PLL_FBKDIV_4 | \
PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \
PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
#define PPCHAMELEON_PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
PLL_MALDIV_1 | PLL_PCIDIV_4)
#define PPCHAMELEON_PLLMR1_200_100_50_33 (PLL_FBKDIV_6 | \
PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \
PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
#define PPCHAMELEON_PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
PLL_MALDIV_1 | PLL_PCIDIV_4)
#define PPCHAMELEON_PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8 | \
PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
#define PPCHAMELEON_PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
PLL_MALDIV_1 | PLL_PCIDIV_2)
#define PPCHAMELEON_PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10 | \
PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
#else
#error "* External frequency (SysClk) not defined! *"
#endif
#if (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_HI)
/* Model HI */
#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_333_111_37_55_55
#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_333_111_37_55_55
#define CONFIG_SYS_OPB_FREQ 55555555
/* Model ME */
#elif (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_ME)
#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_266_133_33_66_33
#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_266_133_33_66_33
#define CONFIG_SYS_OPB_FREQ 66666666
#else
/* Model BA (default) */
#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_133_133_33_66_33
#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_133_133_33_66_33
#define CONFIG_SYS_OPB_FREQ 66666666
#endif
#endif /* CONFIG_NO_SERIAL_EEPROM */
#define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */
#define NAND_CACHE_PAGES 16 /* size of nand cache in 512 bytes pages */
/*
* JFFS2 partitions
*
*/
/* No command line, one static partition */
#undef CONFIG_CMD_MTDPARTS
#define CONFIG_JFFS2_DEV "nand"
#define CONFIG_JFFS2_PART_SIZE 0x00200000
#define CONFIG_JFFS2_PART_OFFSET 0x00000000
/* mtdparts command line support
*
* Note: fake mtd_id used, no linux mtd map file
*/
/*
#define CONFIG_CMD_MTDPARTS
#define MTDIDS_DEFAULT "nand0=catcenter"
#define MTDPARTS_DEFAULT "mtdparts=catcenter:2m(nand)"
*/
#endif /* __CONFIG_H */

403
include/configs/IceCube.h
View File

@@ -1,403 +0,0 @@
/*
* (C) Copyright 2003-2005
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_MPC5200 1 /* This is a MPC5200 CPU */
#define CONFIG_ICECUBE 1 /* ... on IceCube board */
/*
* Valid values for CONFIG_SYS_TEXT_BASE are:
* 0xFFF00000 boot high (standard configuration)
* 0xFF000000 boot low for 16 MiB boards
* 0xFF800000 boot low for 8 MiB boards
* 0x00100000 boot from RAM (for testing only)
*/
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0xFFF00000
#endif
#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/*
* Serial console configuration
*/
#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
/*
* PCI Mapping:
* 0x40000000 - 0x4fffffff - PCI Memory
* 0x50000000 - 0x50ffffff - PCI IO Space
*/
#define CONFIG_PCI
#if defined(CONFIG_PCI)
#define CONFIG_PCI_PNP 1
#define CONFIG_PCI_SCAN_SHOW 1
#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
#define CONFIG_PCI_MEM_BUS 0x40000000
#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
#define CONFIG_PCI_MEM_SIZE 0x10000000
#define CONFIG_PCI_IO_BUS 0x50000000
#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
#define CONFIG_PCI_IO_SIZE 0x01000000
#endif
#define CONFIG_SYS_XLB_PIPELINING 1
#define CONFIG_MII 1
#define CONFIG_EEPRO100 1
#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
#define CONFIG_NS8382X 1
/* Partitions */
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_ISO_PARTITION
/* USB */
#define CONFIG_USB_OHCI_NEW
#define CONFIG_USB_STORAGE
#define CONFIG_SYS_OHCI_BE_CONTROLLER
#undef CONFIG_SYS_USB_OHCI_BOARD_INIT
#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
#define CONFIG_SYS_USB_OHCI_REGS_BASE MPC5XXX_USB
#define CONFIG_SYS_USB_OHCI_SLOT_NAME "mpc5200"
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
#define CONFIG_TIMESTAMP /* Print image info with timestamp */
/*
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_FAT
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IDE
#define CONFIG_CMD_NFS
#define CONFIG_CMD_SNTP
#define CONFIG_CMD_USB
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
#endif
#if (CONFIG_SYS_TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
# define CONFIG_SYS_LOWBOOT 1
# define CONFIG_SYS_LOWBOOT16 1
#endif
#if (CONFIG_SYS_TEXT_BASE == 0xFF800000) /* Boot low with 8 MB Flash */
#if defined(CONFIG_LITE5200B)
# error CONFIG_SYS_LOWBOOT08 is incompatible with the Lite5200B
#else
# define CONFIG_SYS_LOWBOOT 1
# define CONFIG_SYS_LOWBOOT08 1
#endif
#endif
/*
* Autobooting
*/
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#define CONFIG_PREBOOT "echo;" \
"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
"addip=setenv bootargs ${bootargs} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
":${hostname}:${netdev}:off panic=1\0" \
"flash_nfs=run nfsargs addip;" \
"bootm ${kernel_addr}\0" \
"flash_self=run ramargs addip;" \
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_82xx\0" \
"bootfile=/tftpboot/MPC5200/uImage\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
/*
* IPB Bus clocking configuration.
*/
#if defined(CONFIG_LITE5200B)
#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
#else
#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
#endif
/* pass open firmware flat tree */
#define CONFIG_OF_LIBFDT 1
#define CONFIG_OF_BOARD_SETUP 1
#define OF_CPU "PowerPC,5200@0"
#define OF_SOC "soc5200@f0000000"
#define OF_TBCLK (bd->bi_busfreq / 4)
#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000"
/*
* I2C configuration
*/
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
#define CONFIG_SYS_I2C_SLAVE 0x7F
/*
* EEPROM configuration
*/
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70
/*
* Flash configuration
*/
#if defined(CONFIG_LITE5200B)
#define CONFIG_SYS_FLASH_BASE 0xFE000000
#define CONFIG_SYS_FLASH_SIZE 0x01000000
#if !defined(CONFIG_SYS_LOWBOOT)
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x01760000 + 0x00800000)
#else /* CONFIG_SYS_LOWBOOT */
#if defined(CONFIG_SYS_LOWBOOT08)
# error CONFIG_SYS_LOWBOOT08 is incompatible with the Lite5200B
#endif
#if defined(CONFIG_SYS_LOWBOOT16)
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x01060000)
#endif
#endif /* CONFIG_SYS_LOWBOOT */
#else /* !CONFIG_LITE5200B (IceCube)*/
#define CONFIG_SYS_FLASH_BASE 0xFF000000
#define CONFIG_SYS_FLASH_SIZE 0x01000000
#if !defined(CONFIG_SYS_LOWBOOT)
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00740000 + 0x00800000)
#else /* CONFIG_SYS_LOWBOOT */
#if defined(CONFIG_SYS_LOWBOOT08)
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000 + 0x00800000)
#endif
#if defined(CONFIG_SYS_LOWBOOT16)
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000)
#endif
#endif /* CONFIG_SYS_LOWBOOT */
#endif /* CONFIG_LITE5200B */
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of memory banks */
#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */
#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
#undef CONFIG_FLASH_16BIT /* Flash is 8-bit */
#if defined(CONFIG_LITE5200B)
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_CS1_START,CONFIG_SYS_CS0_START}
#endif
/*
* Environment settings
*/
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_SIZE 0x10000
#if defined(CONFIG_LITE5200B)
#define CONFIG_ENV_SECT_SIZE 0x20000
#else
#define CONFIG_ENV_SECT_SIZE 0x10000
#endif
#define CONFIG_ENV_OVERWRITE 1
/*
* Memory map
*/
#define CONFIG_SYS_MBAR 0xF0000000
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
/* Use SRAM until RAM will be available */
#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
# define CONFIG_SYS_RAMBOOT 1
#endif
#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
#define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*
* Ethernet configuration
*/
#define CONFIG_MPC5xxx_FEC 1
#define CONFIG_MPC5xxx_FEC_MII100
/*
* Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
*/
/* #define CONFIG_MPC5xxx_FEC_MII10 */
#define CONFIG_PHY_ADDR 0x00
/*
* GPIO configuration
*/
#ifdef CONFIG_MPC5200_DDR
#define CONFIG_SYS_GPS_PORT_CONFIG 0x90000004
#else
#define CONFIG_SYS_GPS_PORT_CONFIG 0x10000004
#endif
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */
#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
#if defined(CONFIG_CMD_KGDB)
# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
/*
* Various low-level settings
*/
#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
#define CONFIG_SYS_HID0_FINAL HID0_ICE
#if defined(CONFIG_LITE5200B)
#define CONFIG_SYS_CS1_START CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_CS1_SIZE CONFIG_SYS_FLASH_SIZE
#define CONFIG_SYS_CS1_CFG 0x00047800
#define CONFIG_SYS_CS0_START (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE)
#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_CS0_START
#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
#define CONFIG_SYS_BOOTCS_CFG 0x00047800
#else /* IceCube aka Lite5200 */
#ifdef CONFIG_MPC5200_DDR
#define CONFIG_SYS_BOOTCS_START (CONFIG_SYS_CS1_START + CONFIG_SYS_CS1_SIZE)
#define CONFIG_SYS_BOOTCS_SIZE 0x00800000
#define CONFIG_SYS_BOOTCS_CFG 0x00047801
#define CONFIG_SYS_CS1_START CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_CS1_SIZE 0x00800000
#define CONFIG_SYS_CS1_CFG 0x00047800
#else /* !CONFIG_MPC5200_DDR */
#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
#define CONFIG_SYS_BOOTCS_CFG 0x00047801
#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
#endif /* CONFIG_MPC5200_DDR */
#endif /*CONFIG_LITE5200B */
#define CONFIG_SYS_CS_BURST 0x00000000
#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
#define CONFIG_SYS_RESET_ADDRESS 0xff000000
/*-----------------------------------------------------------------------
* USB stuff
*-----------------------------------------------------------------------
*/
#define CONFIG_USB_CLOCK 0x0001BBBB
#define CONFIG_USB_CONFIG 0x00001000
/*-----------------------------------------------------------------------
* IDE/ATA stuff Supports IDE harddisk
*-----------------------------------------------------------------------
*/
#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
#undef CONFIG_IDE_LED /* LED for ide not supported */
#define CONFIG_IDE_RESET /* reset for ide supported */
#define CONFIG_IDE_PREINIT
#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 1 drive per IDE bus */
#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
/* Offset for data I/O */
#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
/* Offset for normal register accesses */
#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
/* Offset for alternate registers */
#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
/* Interval between registers */
#define CONFIG_SYS_ATA_STRIDE 4
#define CONFIG_ATAPI 1
#endif /* __CONFIG_H */

735
include/configs/MPC8360EMDS.h
View File

@@ -1,735 +0,0 @@
/*
* Copyright (C) 2006,2011 Freescale Semiconductor, Inc.
*
* Dave Liu <daveliu@freescale.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* High Level Configuration Options
*/
#define CONFIG_E300 1 /* E300 family */
#define CONFIG_QE 1 /* Has QE */
#define CONFIG_MPC8360 1 /* MPC8360 CPU specific */
#define CONFIG_MPC8360EMDS 1 /* MPC8360EMDS board specific */
#define CONFIG_SYS_TEXT_BASE 0xFE000000
#undef CONFIG_PQ_MDS_PIB /* POWERQUICC MDS Platform IO Board */
#undef CONFIG_PQ_MDS_PIB_ATM /* QOC3 ATM card */
/*
* System Clock Setup
*/
#ifdef CONFIG_CLKIN_33MHZ
#ifdef CONFIG_PCISLAVE
#define CONFIG_83XX_PCICLK 33330000 /* in HZ */
#else
#define CONFIG_83XX_CLKIN 33330000 /* in Hz */
#endif
#ifndef CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_CLK_FREQ 33330000
#endif
#elif defined(CONFIG_CLKIN_66MHZ)
#ifdef CONFIG_PCISLAVE
#define CONFIG_83XX_PCICLK 66000000 /* in HZ */
#else
#define CONFIG_83XX_CLKIN 66000000 /* in Hz */
#endif
#ifndef CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_CLK_FREQ 66000000
#endif
#else
#error Unknown oscillator frequency.
#endif
/*
* Hardware Reset Configuration Word
*/
#ifdef CONFIG_CLKIN_33MHZ
#define CONFIG_SYS_HRCW_LOW (\
HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
HRCWL_DDR_TO_SCB_CLK_1X1 |\
HRCWL_CSB_TO_CLKIN_8X1 |\
HRCWL_VCO_1X2 |\
HRCWL_CE_PLL_VCO_DIV_4 |\
HRCWL_CE_PLL_DIV_1X1 |\
HRCWL_CE_TO_PLL_1X15 |\
HRCWL_CORE_TO_CSB_2X1)
#elif defined(CONFIG_CLKIN_66MHZ)
#define CONFIG_SYS_HRCW_LOW (\
HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
HRCWL_DDR_TO_SCB_CLK_1X1 |\
HRCWL_CSB_TO_CLKIN_4X1 |\
HRCWL_VCO_1X2 |\
HRCWL_CE_PLL_VCO_DIV_4 |\
HRCWL_CE_PLL_DIV_1X1 |\
HRCWL_CE_TO_PLL_1X6 |\
HRCWL_CORE_TO_CSB_2X1)
#endif
#ifdef CONFIG_PCISLAVE
#define CONFIG_SYS_HRCW_HIGH (\
HRCWH_PCI_AGENT |\
HRCWH_PCI1_ARBITER_DISABLE |\
HRCWH_PCICKDRV_DISABLE |\
HRCWH_CORE_ENABLE |\
HRCWH_FROM_0XFFF00100 |\
HRCWH_BOOTSEQ_DISABLE |\
HRCWH_SW_WATCHDOG_DISABLE |\
HRCWH_ROM_LOC_LOCAL_16BIT)
#else
#define CONFIG_SYS_HRCW_HIGH (\
HRCWH_PCI_HOST |\
HRCWH_PCI1_ARBITER_ENABLE |\
HRCWH_PCICKDRV_ENABLE |\
HRCWH_CORE_ENABLE |\
HRCWH_FROM_0X00000100 |\
HRCWH_BOOTSEQ_DISABLE |\
HRCWH_SW_WATCHDOG_DISABLE |\
HRCWH_ROM_LOC_LOCAL_16BIT)
#endif
/*
* System IO Config
*/
#define CONFIG_SYS_SICRH 0x00000000
#define CONFIG_SYS_SICRL 0x40000000
#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
#define CONFIG_BOARD_EARLY_INIT_R
/*
* IMMR new address
*/
#define CONFIG_SYS_IMMR 0xE0000000
/*
* DDR Setup
*/
#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
/* + 256M */
#define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000)
#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
| DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
#define CONFIG_SYS_83XX_DDR_USES_CS0
#define CONFIG_DDR_ECC /* support DDR ECC function */
#define CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */
/*
* DDRCDR - DDR Control Driver Register
*/
#define CONFIG_SYS_DDRCDR_VALUE 0x80080001
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
#if defined(CONFIG_SPD_EEPROM)
/*
* Determine DDR configuration from I2C interface.
*/
#define SPD_EEPROM_ADDRESS 0x52 /* DDR SODIMM */
#else
/*
* Manually set up DDR parameters
*/
#define CONFIG_SYS_DDR_SIZE 256 /* MB */
#if defined(CONFIG_DDR_II)
#define CONFIG_SYS_DDRCDR 0x80080001
#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f
#define CONFIG_SYS_DDR_CS0_CONFIG 0x80330102
#define CONFIG_SYS_DDR_TIMING_0 0x00220802
#define CONFIG_SYS_DDR_TIMING_1 0x38357322
#define CONFIG_SYS_DDR_TIMING_2 0x2f9048c8
#define CONFIG_SYS_DDR_TIMING_3 0x00000000
#define CONFIG_SYS_DDR_CLK_CNTL 0x02000000
#define CONFIG_SYS_DDR_MODE 0x47d00432
#define CONFIG_SYS_DDR_MODE2 0x8000c000
#define CONFIG_SYS_DDR_INTERVAL 0x03cf0080
#define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000
#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
#else
#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
| CSCONFIG_ROW_BIT_13 \
| CSCONFIG_COL_BIT_9)
#define CONFIG_SYS_DDR_CS1_CONFIG CONFIG_SYS_DDR_CS0_CONFIG
#define CONFIG_SYS_DDR_TIMING_1 0x37344321 /* tCL-tRCD-tRP-tRAS=2.5-3-3-7 */
#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* may need tuning */
#define CONFIG_SYS_DDR_CONTROL 0x42008000 /* Self refresh,2T timing */
#define CONFIG_SYS_DDR_MODE 0x20000162 /* DLL,normal,seq,4/2.5 */
#define CONFIG_SYS_DDR_INTERVAL 0x045b0100 /* page mode */
#endif
#endif
/*
* Memory test
*/
#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
#define CONFIG_SYS_MEMTEST_END 0x00100000
/*
* The reserved memory
*/
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_RAMBOOT
#else
#undef CONFIG_SYS_RAMBOOT
#endif
/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
/*
* Initial RAM Base Address Setup
*/
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
#define CONFIG_SYS_GBL_DATA_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/*
* Local Bus Configuration & Clock Setup
*/
#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
#define CONFIG_SYS_LBC_LBCR 0x00000000
/*
* FLASH on the Local Bus
*/
#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
#define CONFIG_SYS_FLASH_SIZE 32 /* max FLASH size is 32M */
#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
/* Window base at flash base */
#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB)
#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
| BR_PS_16 /* 16 bit port */ \
| BR_MS_GPCM /* MSEL = GPCM */ \
| BR_V) /* valid */
#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
| OR_GPCM_XAM \
| OR_GPCM_CSNT \
| OR_GPCM_ACS_DIV2 \
| OR_GPCM_XACS \
| OR_GPCM_SCY_15 \
| OR_GPCM_TRLX_SET \
| OR_GPCM_EHTR_SET \
| OR_GPCM_EAD)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
#undef CONFIG_SYS_FLASH_CHECKSUM
/*
* BCSR on the Local Bus
*/
#define CONFIG_SYS_BCSR 0xF8000000
/* Access window base at BCSR base */
#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR
#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_64KB)
#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \
| BR_PS_8 \
| BR_MS_GPCM \
| BR_V)
#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \
| OR_GPCM_XAM \
| OR_GPCM_CSNT \
| OR_GPCM_XACS \
| OR_GPCM_SCY_15 \
| OR_GPCM_TRLX_SET \
| OR_GPCM_EHTR_SET \
| OR_GPCM_EAD)
/* 0xFFFFE9F7 */
/*
* SDRAM on the Local Bus
*/
#define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* SDRAM base address */
#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
#define CONFIG_SYS_LB_SDRAM /* if board has SRDAM on local bus */
#ifdef CONFIG_SYS_LB_SDRAM
#define CONFIG_SYS_LBLAWBAR2 0
#define CONFIG_SYS_LBLAWAR2 (LBLAWAR_EN | LBLAWAR_64MB)
/*local bus BR2, OR2 definition for SDRAM if soldered on the EPB board */
/*
* Base Register 2 and Option Register 2 configure SDRAM.
*
* For BR2, need:
* Base address = BR[0:16] = dynamic
* port size = 32-bits = BR2[19:20] = 11
* no parity checking = BR2[21:22] = 00
* SDRAM for MSEL = BR2[24:26] = 011
* Valid = BR[31] = 1
*
* 0 4 8 12 16 20 24 28
* xxxx xxxx xxxx xxxx x001 1000 0110 0001 = 00001861
*/
/* Port size=32bit, MSEL=DRAM */
#define CONFIG_SYS_BR2 (BR_PS_32 | BR_MS_SDRAM | BR_V) /* 0xF0001861 */
/*
* The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
*
* For OR2, need:
* 64MB mask for AM, OR2[0:7] = 1111 1100
* XAM, OR2[17:18] = 11
* 9 columns OR2[19-21] = 010
* 13 rows OR2[23-25] = 100
* EAD set for extra time OR[31] = 1
*
* 0 4 8 12 16 20 24 28
* 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
*/
#define CONFIG_SYS_OR2 (MEG_TO_AM(CONFIG_SYS_LBC_SDRAM_SIZE) \
| OR_SDRAM_XAM \
| ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \
| ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \
| OR_SDRAM_EAD)
/* 0xFC006901 */
/* LB sdram refresh timer, about 6us */
#define CONFIG_SYS_LBC_LSRT 0x32000000
/* LB refresh timer prescal, 266MHz/32 */
#define CONFIG_SYS_LBC_MRTPR 0x20000000
#define CONFIG_SYS_LBC_LSDMR_COMMON 0x0063b723
/*
* SDRAM Controller configuration sequence.
*/
#define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
#define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
#define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
#define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
#define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
#endif
/*
* Windows to access Platform I/O Boards (PIB) via local bus
*/
#define CONFIG_SYS_PIB_BASE 0xF8008000
#define CONFIG_SYS_PIB_WINDOW_SIZE (32 * 1024)
/* [RFC] This LBLAW only covers the 2nd window (CS5) */
#define CONFIG_SYS_LBLAWBAR3_PRELIM \
CONFIG_SYS_PIB_BASE + CONFIG_SYS_PIB_WINDOW_SIZE
#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
/*
* CS4 on Local Bus, to PIB
*/
/* CS4 base address at 0xf8008000 */
#define CONFIG_SYS_BR4_PRELIM (CONFIG_SYS_PIB_BASE \
| BR_PS_8 \
| BR_MS_GPCM \
| BR_V)
/* 0xF8008801 */
#define CONFIG_SYS_OR4_PRELIM (OR_AM_32KB \
| OR_GPCM_XAM \
| OR_GPCM_CSNT \
| OR_GPCM_XACS \
| OR_GPCM_SCY_15 \
| OR_GPCM_TRLX_SET \
| OR_GPCM_EHTR_SET \
| OR_GPCM_EAD)
/* 0xffffe9f7 */
/*
* CS5 on Local Bus, to PIB
*/
/* CS5 base address at 0xf8010000 */
#define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_PIB_BASE + \
CONFIG_SYS_PIB_WINDOW_SIZE) \
| BR_PS_8 \
| BR_MS_GPCM \
| BR_V)
/* 0xF8010801 */
#define CONFIG_SYS_OR5_PRELIM (CONFIG_SYS_PIB_BASE \
| OR_GPCM_XAM \
| OR_GPCM_CSNT \
| OR_GPCM_XACS \
| OR_GPCM_SCY_15 \
| OR_GPCM_TRLX_SET \
| OR_GPCM_EHTR_SET \
| OR_GPCM_EAD)
/* 0xffffe9f7 */
/*
* Serial Port
*/
#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
/* Use the HUSH parser */
#define CONFIG_SYS_HUSH_PARSER
/* pass open firmware flat tree */
#define CONFIG_OF_LIBFDT 1
#define CONFIG_OF_BOARD_SETUP 1
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED 400000
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
#define CONFIG_SYS_I2C_NOPROBES { {0, 0x52} }
/*
* Config on-board RTC
*/
#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
/*
* General PCI
* Addresses are mapped 1-1.
*/
#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
#define CONFIG_SYS_PCI1_IO_PHYS 0xE0300000
#define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
#define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
#ifdef CONFIG_PCI
#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_83XX_PCI_STREAMING
#undef CONFIG_EEPRO100
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
#endif /* CONFIG_PCI */
#define CONFIG_HWCONFIG 1
/*
* QE UEC ethernet configuration
*/
#define CONFIG_UEC_ETH
#define CONFIG_ETHPRIME "UEC0"
#define CONFIG_PHY_MODE_NEED_CHANGE
#define CONFIG_UEC_ETH1 /* GETH1 */
#ifdef CONFIG_UEC_ETH1
#define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE
#define CONFIG_SYS_UEC1_TX_CLK QE_CLK9
#define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH
#define CONFIG_SYS_UEC1_PHY_ADDR 0
#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
#define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000
#endif
#define CONFIG_UEC_ETH2 /* GETH2 */
#ifdef CONFIG_UEC_ETH2
#define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */
#define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE
#define CONFIG_SYS_UEC2_TX_CLK QE_CLK4
#define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH
#define CONFIG_SYS_UEC2_PHY_ADDR 1
#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
#define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
#endif
/*
* Environment
*/
#ifndef CONFIG_SYS_RAMBOOT
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_ADDR \
(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
#define CONFIG_ENV_SECT_SIZE 0x20000
#define CONFIG_ENV_SIZE 0x2000
#else
#define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
#define CONFIG_ENV_SIZE 0x2000
#endif
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
/*
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_PING
#define CONFIG_CMD_I2C
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_SDRAM
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
#endif
#if defined(CONFIG_SYS_RAMBOOT)
#undef CONFIG_CMD_SAVEENV
#undef CONFIG_CMD_LOADS
#endif
#undef CONFIG_WATCHDOG /* watchdog disabled */
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#endif
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
/*
* For booting Linux, the board info and command line data
* have to be in the first 256 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
/*
* Core HID Setup
*/
#define CONFIG_SYS_HID0_INIT 0x000000000
#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
HID0_ENABLE_INSTRUCTION_CACHE)
#define CONFIG_SYS_HID2 HID2_HBE
/*
* MMU Setup
*/
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
#define CONFIG_BAT_RW
/* DDR/LBC SDRAM: cacheable */
#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
| BATL_PP_RW \
| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
| BATU_BL_256M \
| BATU_VS \
| BATU_VP)
#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
/* IMMRBAR & PCI IO: cache-inhibit and guarded */
#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \
| BATL_PP_RW \
| BATL_CACHEINHIBIT \
| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \
| BATU_BL_4M \
| BATU_VS \
| BATU_VP)
#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
/* BCSR: cache-inhibit and guarded */
#define CONFIG_SYS_IBAT2L (CONFIG_SYS_BCSR \
| BATL_PP_RW \
| BATL_CACHEINHIBIT \
| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT2U (CONFIG_SYS_BCSR \
| BATU_BL_128K \
| BATU_VS \
| BATU_VP)
#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
/* FLASH: icache cacheable, but dcache-inhibit and guarded */
#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE \
| BATL_PP_RW \
| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE \
| BATU_BL_32M \
| BATU_VS \
| BATU_VP)
#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE \
| BATL_PP_RW \
| BATL_CACHEINHIBIT \
| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
/* DDR/LBC SDRAM next 256M: cacheable */
#define CONFIG_SYS_IBAT4L (CONFIG_SYS_SDRAM_BASE2 \
| BATL_PP_RW \
| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT4U (CONFIG_SYS_SDRAM_BASE2 \
| BATU_BL_256M \
| BATU_VS \
| BATU_VP)
#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
/* Stack in dcache: cacheable, no memory coherence */
#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
#define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \
| BATU_BL_128K \
| BATU_VS \
| BATU_VP)
#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
#ifdef CONFIG_PCI
/* PCI MEM space: cacheable */
#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MEM_PHYS \
| BATL_PP_RW \
| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MEM_PHYS \
| BATU_BL_256M \
| BATU_VS \
| BATU_VP)
#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
/* PCI MMIO space: cache-inhibit and guarded */
#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI1_MMIO_PHYS \
| BATL_PP_RW \
| BATL_CACHEINHIBIT \
| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI1_MMIO_PHYS \
| BATU_BL_256M \
| BATU_VS \
| BATU_VP)
#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
#else
#define CONFIG_SYS_IBAT6L (0)
#define CONFIG_SYS_IBAT6U (0)
#define CONFIG_SYS_IBAT7L (0)
#define CONFIG_SYS_IBAT7U (0)
#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
#endif
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
#endif
/*
* Environment Configuration
*/
#define CONFIG_ENV_OVERWRITE
#if defined(CONFIG_UEC_ETH)
#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1
#endif
#define CONFIG_BAUDRATE 115200
#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"consoledev=ttyS0\0" \
"ramdiskaddr=1000000\0" \
"ramdiskfile=ramfs.83xx\0" \
"fdtaddr=780000\0" \
"fdtfile=mpc836x_mds.dtb\0" \
""
#define CONFIG_NFSBOOTCOMMAND \
"setenv bootargs root=/dev/nfs rw " \
"nfsroot=$serverip:$rootpath " \
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
"$netdev:off " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $loadaddr $bootfile;" \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr - $fdtaddr"
#define CONFIG_RAMBOOTCOMMAND \
"setenv bootargs root=/dev/ram rw " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $ramdiskaddr $ramdiskfile;" \
"tftp $loadaddr $bootfile;" \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr $ramdiskaddr $fdtaddr"
#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
#endif /* __CONFIG_H */

620
include/configs/MPC8360ERDK.h
View File

@@ -1,620 +0,0 @@
/*
* Copyright (C) 2006 Freescale Semiconductor, Inc.
* Dave Liu <daveliu@freescale.com>
*
* Copyright (C) 2007 Logic Product Development, Inc.
* Peter Barada <peterb@logicpd.com>
*
* Copyright (C) 2007 MontaVista Software, Inc.
* Anton Vorontsov <avorontsov@ru.mvista.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* High Level Configuration Options
*/
#define CONFIG_E300 1 /* E300 family */
#define CONFIG_QE 1 /* Has QE */
#define CONFIG_MPC8360 1 /* MPC8360 CPU specific */
#define CONFIG_MPC8360ERDK 1 /* MPC8360ERDK board specific */
#define CONFIG_SYS_TEXT_BASE 0xFF800000
/*
* System Clock Setup
*/
#ifdef CONFIG_CLKIN_33MHZ
#define CONFIG_83XX_CLKIN 33333333
#define CONFIG_SYS_CLK_FREQ 33333333
#define CONFIG_PCI_33M 1
#define HRCWL_CSB_TO_CLKIN_MPC8360ERDK HRCWL_CSB_TO_CLKIN_10X1
#else
#define CONFIG_83XX_CLKIN 66000000
#define CONFIG_SYS_CLK_FREQ 66000000
#define CONFIG_PCI_66M 1
#define HRCWL_CSB_TO_CLKIN_MPC8360ERDK HRCWL_CSB_TO_CLKIN_5X1
#endif /* CONFIG_CLKIN_33MHZ */
/*
* Hardware Reset Configuration Word
*/
#define CONFIG_SYS_HRCW_LOW (\
HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
HRCWL_DDR_TO_SCB_CLK_1X1 |\
HRCWL_CSB_TO_CLKIN_MPC8360ERDK |\
HRCWL_CORE_TO_CSB_2X1 |\
HRCWL_CE_TO_PLL_1X15)
#define CONFIG_SYS_HRCW_HIGH (\
HRCWH_PCI_HOST |\
HRCWH_PCI1_ARBITER_ENABLE |\
HRCWH_PCICKDRV_ENABLE |\
HRCWH_CORE_ENABLE |\
HRCWH_FROM_0X00000100 |\
HRCWH_BOOTSEQ_DISABLE |\
HRCWH_SW_WATCHDOG_DISABLE |\
HRCWH_ROM_LOC_LOCAL_16BIT |\
HRCWH_SECONDARY_DDR_DISABLE |\
HRCWH_BIG_ENDIAN |\
HRCWH_LALE_EARLY)
/*
* System IO Config
*/
#define CONFIG_SYS_SICRH 0x00000000
#define CONFIG_SYS_SICRL 0x40000000
#define CONFIG_BOARD_EARLY_INIT_R
/*
* IMMR new address
*/
#define CONFIG_SYS_IMMR 0xE0000000
/*
* DDR Setup
*/
#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
| DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
#define CONFIG_SYS_83XX_DDR_USES_CS0
#define CONFIG_DDR_ECC /* support DDR ECC function */
#define CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */
/*
* DDRCDR - DDR Control Driver Register
*/
#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN \
| DDRCDR_ODT \
| DDRCDR_Q_DRN)
/* 0x80080001 */
#undef CONFIG_SPD_EEPROM /* Do not use SPD EEPROM for DDR setup */
/*
* Manually set up DDR parameters
*/
#define CONFIG_DDR_II
#define CONFIG_SYS_DDR_SIZE 256 /* MB */
#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f
#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
| CSCONFIG_ROW_BIT_13 \
| CSCONFIG_COL_BIT_10 \
| CSCONFIG_ODT_WR_ONLY_CURRENT)
#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 \
| SDRAM_CFG_ECC_EN)
#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000
#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
#define CONFIG_SYS_DDR_INTERVAL ((256 << SDRAM_INTERVAL_BSTOPRE_SHIFT) \
| (1115 << SDRAM_INTERVAL_REFINT_SHIFT))
#define CONFIG_SYS_DDR_MODE 0x47800432
#define CONFIG_SYS_DDR_MODE2 0x8000c000
#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
(9 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
(3 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
(3 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
(0 << TIMING_CFG0_WWT_SHIFT) | \
(0 << TIMING_CFG0_RRT_SHIFT) | \
(0 << TIMING_CFG0_WRT_SHIFT) | \
(0 << TIMING_CFG0_RWT_SHIFT))
#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_30) | \
(2 << TIMING_CFG1_WRTORD_SHIFT) | \
(2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
(3 << TIMING_CFG1_WRREC_SHIFT) | \
(10 << TIMING_CFG1_REFREC_SHIFT) | \
(3 << TIMING_CFG1_ACTTORW_SHIFT) | \
(8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
(3 << TIMING_CFG1_PRETOACT_SHIFT))
#define CONFIG_SYS_DDR_TIMING_2 ((9 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
(4 << TIMING_CFG2_CKE_PLS_SHIFT) | \
(2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
(2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
(2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
(0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
(0 << TIMING_CFG2_CPO_SHIFT))
#define CONFIG_SYS_DDR_TIMING_3 0x00000000
/*
* Memory test
*/
#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
#define CONFIG_SYS_MEMTEST_END 0x00100000
/*
* The reserved memory
*/
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#define CONFIG_SYS_FLASH_BASE 0xFF800000 /* FLASH base address */
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_RAMBOOT
#else
#undef CONFIG_SYS_RAMBOOT
#endif
#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
/*
* Initial RAM Base Address Setup
*/
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
#define CONFIG_SYS_GBL_DATA_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/*
* Local Bus Configuration & Clock Setup
*/
#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
#define CONFIG_SYS_LBC_LBCR 0x00000000
/*
* FLASH on the Local Bus
*/
#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
#define CONFIG_SYS_FLASH_SIZE 8 /* max FLASH size is 32M */
#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use intel Flash protection. */
/* Window base at flash base */
#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB)
#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
| BR_PS_16 /* 16 bit port */ \
| BR_MS_GPCM /* MSEL = GPCM */ \
| BR_V) /* valid */
#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
| OR_UPM_XAM \
| OR_GPCM_CSNT \
| OR_GPCM_ACS_DIV2 \
| OR_GPCM_XACS \
| OR_GPCM_SCY_15 \
| OR_GPCM_TRLX_SET \
| OR_GPCM_EHTR_SET \
| OR_GPCM_EAD)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
#undef CONFIG_SYS_FLASH_CHECKSUM
/*
* NAND flash on the local bus
*/
#define CONFIG_SYS_NAND_BASE 0x60000000
#define CONFIG_CMD_NAND 1
#define CONFIG_NAND_FSL_UPM 1
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
/*
* [RFC] Comment said 4KB window; code said 256MB window; OR1 says 64MB
* ... What's correct?
*/
#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_256MB)
/* Port size 8 bit, UPMA */
#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \
| BR_PS_8 \
| BR_MS_UPMA \
| BR_V)
/* 0x60000881 */
#define CONFIG_SYS_OR1_PRELIM (OR_AM_64MB | OR_UPM_EAD)
/* 0xFC000001 */
/*
* Fujitsu MB86277 (MINT) graphics controller
*/
#define CONFIG_SYS_VIDEO_BASE 0x70000000
#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VIDEO_BASE
#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_64MB)
/* Port size 32 bit, UPMB */
#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VIDEO_BASE \
| BR_PS_32 \
| BR_MS_UPMB \
| BR_V)
/* 0x000018a1 */
#define CONFIG_SYS_OR2_PRELIM (OR_AM_64MB | OR_UPM_EAD)
/* 0xFC000001 */
/*
* Serial Port
*/
#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
/* Use the HUSH parser */
#define CONFIG_SYS_HUSH_PARSER
/* Pass open firmware flat tree */
#define CONFIG_OF_LIBFDT 1
#define CONFIG_OF_BOARD_SETUP 1
#define CONFIG_OF_STDOUT_VIA_ALIAS
/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED 400000
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
#define CONFIG_SYS_FSL_I2C2_SPEED 400000
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
#define CONFIG_SYS_I2C_NOPROBES { {0, 0x52} }
/*
* General PCI
* Addresses are mapped 1-1.
*/
#define CONFIG_PCI
#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
#define CONFIG_SYS_PCI1_IO_BASE 0xE0300000
#define CONFIG_SYS_PCI1_IO_PHYS 0xE0300000
#define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
#ifdef CONFIG_PCI
#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#undef CONFIG_EEPRO100
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
#endif /* CONFIG_PCI */
/*
* QE UEC ethernet configuration
*/
#define CONFIG_UEC_ETH
#define CONFIG_ETHPRIME "UEC0"
#define CONFIG_UEC_ETH1 /* GETH1 */
#ifdef CONFIG_UEC_ETH1
#define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE
#define CONFIG_SYS_UEC1_TX_CLK QE_CLK9
#define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH
#define CONFIG_SYS_UEC1_PHY_ADDR 2
#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_RXID
#define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000
#endif
#define CONFIG_UEC_ETH2 /* GETH2 */
#ifdef CONFIG_UEC_ETH2
#define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */
#define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE
#define CONFIG_SYS_UEC2_TX_CLK QE_CLK4
#define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH
#define CONFIG_SYS_UEC2_PHY_ADDR 4
#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_RXID
#define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
#endif
/*
* Environment
*/
#ifndef CONFIG_SYS_RAMBOOT
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
#define CONFIG_ENV_SIZE 0x20000
#else /* CONFIG_SYS_RAMBOOT */
#define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
#define CONFIG_ENV_SIZE 0x2000
#endif /* CONFIG_SYS_RAMBOOT */
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
/*
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_PING
#define CONFIG_CMD_I2C
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DHCP
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
#endif
#if defined(CONFIG_SYS_RAMBOOT)
#undef CONFIG_CMD_SAVEENV
#undef CONFIG_CMD_LOADS
#endif
#undef CONFIG_WATCHDOG /* watchdog disabled */
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#endif
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
/*
* For booting Linux, the board info and command line data
* have to be in the first 256 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
/*
* Core HID Setup
*/
#define CONFIG_SYS_HID0_INIT 0x000000000
#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
HID0_ENABLE_INSTRUCTION_CACHE)
#define CONFIG_SYS_HID2 HID2_HBE
/*
* MMU Setup
*/
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/* DDR: cache cacheable */
#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
| BATL_PP_RW \
| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
| BATU_BL_256M \
| BATU_VS \
| BATU_VP)
#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
/* IMMRBAR & PCI IO: cache-inhibit and guarded */
#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \
| BATL_PP_RW \
| BATL_CACHEINHIBIT \
| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \
| BATU_BL_4M \
| BATU_VS \
| BATU_VP)
#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
/* NAND: cache-inhibit and guarded */
#define CONFIG_SYS_IBAT2L (CONFIG_SYS_NAND_BASE \
| BATL_PP_RW \
| BATL_CACHEINHIBIT \
| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT2U (CONFIG_SYS_NAND_BASE \
| BATU_BL_64M \
| BATU_VS \
| BATU_VP)
#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
/* FLASH: icache cacheable, but dcache-inhibit and guarded */
#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE \
| BATL_PP_RW \
| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE \
| BATU_BL_32M \
| BATU_VS \
| BATU_VP)
#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE \
| BATL_PP_RW \
| BATL_CACHEINHIBIT \
| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
/* Stack in dcache: cacheable, no memory coherence */
#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR \
| BATL_PP_RW)
#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR \
| BATU_BL_128K \
| BATU_VS \
| BATU_VP)
#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
#define CONFIG_SYS_IBAT5L (CONFIG_SYS_VIDEO_BASE \
| BATL_PP_RW \
| BATL_CACHEINHIBIT \
| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT5U (CONFIG_SYS_VIDEO_BASE \
| BATU_BL_64M \
| BATU_VS \
| BATU_VP)
#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
#ifdef CONFIG_PCI
/* PCI MEM space: cacheable */
#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MEM_PHYS \
| BATL_PP_RW \
| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MEM_PHYS \
| BATU_BL_256M \
| BATU_VS \
| BATU_VP)
#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
/* PCI MMIO space: cache-inhibit and guarded */
#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI1_MMIO_PHYS \
| BATL_PP_RW \
| BATL_CACHEINHIBIT \
| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI1_MMIO_PHYS \
| BATU_BL_256M \
| BATU_VS \
| BATU_VP)
#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
#else /* CONFIG_PCI */
#define CONFIG_SYS_IBAT6L (0)
#define CONFIG_SYS_IBAT6U (0)
#define CONFIG_SYS_IBAT7L (0)
#define CONFIG_SYS_IBAT7U (0)
#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
#endif /* CONFIG_PCI */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
#endif
/*
* Environment Configuration
*/
#define CONFIG_ENV_OVERWRITE
#if defined(CONFIG_UEC_ETH)
#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1
#define CONFIG_HAS_ETH2
#define CONFIG_HAS_ETH3
#endif
#define CONFIG_BAUDRATE 115200
#define CONFIG_LOADADDR a00000
#define CONFIG_HOSTNAME mpc8360erdk
#define CONFIG_BOOTFILE "uImage"
#define CONFIG_ROOTPATH "/nfsroot/"
#define CONFIG_BOOTDELAY 2 /* -1 disables auto-boot */
#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"consoledev=ttyS0\0" \
"loadaddr=a00000\0" \
"fdtaddr=900000\0" \
"fdtfile=mpc836x_rdk.dtb\0" \
"fsfile=fs\0" \
"ubootfile=u-boot.bin\0" \
"mtdparts=mtdparts=60000000.nand-flash:4096k(kernel),128k(dtb),"\
"-(rootfs)\0" \
"setbootargs=setenv bootargs console=$consoledev,$baudrate " \
"$mtdparts panic=1\0" \
"adddhcpargs=setenv bootargs $bootargs ip=on\0" \
"addnfsargs=setenv bootargs $bootargs ip=$ipaddr:$serverip:" \
"$gatewayip:$netmask:$hostname:$netdev:off " \
"root=/dev/nfs rw nfsroot=$serverip:$rootpath\0" \
"addnandargs=setenv bootargs $bootargs root=/dev/mtdblock3 " \
"rootfstype=jffs2 rw\0" \
"tftp_get_uboot=tftp 100000 $ubootfile\0" \
"tftp_get_kernel=tftp $loadaddr $bootfile\0" \
"tftp_get_dtb=tftp $fdtaddr $fdtfile\0" \
"tftp_get_fs=tftp c00000 $fsfile\0" \
"nand_erase_kernel=nand erase 0 400000\0" \
"nand_erase_dtb=nand erase 400000 20000\0" \
"nand_erase_fs=nand erase 420000 3be0000\0" \
"nand_write_kernel=nand write.jffs2 $loadaddr 0 400000\0" \
"nand_write_dtb=nand write.jffs2 $fdtaddr 400000 20000\0" \
"nand_write_fs=nand write.jffs2 c00000 420000 $filesize\0" \
"nand_read_kernel=nand read.jffs2 $loadaddr 0 400000\0" \
"nand_read_dtb=nand read.jffs2 $fdtaddr 400000 20000\0" \
"nor_reflash=protect off ff800000 ff87ffff ; " \
"erase ff800000 ff87ffff ; " \
"cp.b 100000 ff800000 $filesize\0" \
"nand_reflash_kernel=run tftp_get_kernel nand_erase_kernel " \
"nand_write_kernel\0" \
"nand_reflash_dtb=run tftp_get_dtb nand_erase_dtb nand_write_dtb\0"\
"nand_reflash_fs=run tftp_get_fs nand_erase_fs nand_write_fs\0" \
"nand_reflash=run nand_reflash_kernel nand_reflash_dtb " \
"nand_reflash_fs\0" \
"boot_m=bootm $loadaddr - $fdtaddr\0" \
"dhcpboot=dhcp ; run setbootargs adddhcpargs tftp_get_dtb boot_m\0"\
"nfsboot=run setbootargs addnfsargs tftp_get_kernel tftp_get_dtb "\
"boot_m\0" \
"nandboot=run setbootargs addnandargs nand_read_kernel nand_read_dtb "\
"boot_m\0" \
""
#define CONFIG_BOOTCOMMAND "run dhcpboot"
#endif /* __CONFIG_H */

2
include/configs/MPC837XERDB.h
View File

@@ -15,6 +15,8 @@
#define CONFIG_E300 1 /* E300 family */
#define CONFIG_MPC837x 1 /* MPC837x CPU specific */
#define CONFIG_MPC837XERDB 1
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_SYS_TEXT_BASE 0xFE000000

808
include/configs/P1_P2_RDB.h
View File

@@ -1,808 +0,0 @@
/*
* Copyright 2009-2011 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
/*
* P1 P2 RDB board configuration file
* This file is intended to address a set of Low End and Ultra Low End
* Freescale SOCs of QorIQ series(RDB platforms).
* Currently only P2020RDB
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#ifdef CONFIG_36BIT
#define CONFIG_PHYS_64BIT
#endif
#ifdef CONFIG_P1011RDB
#define CONFIG_P1011
#define CONFIG_SYS_L2_SIZE (256 << 10)
#endif
#ifdef CONFIG_P1020RDB
#define CONFIG_P1020
#define CONFIG_SYS_L2_SIZE (256 << 10)
#endif
#ifdef CONFIG_P2010RDB
#define CONFIG_P2010
#define CONFIG_SYS_L2_SIZE (512 << 10)
#endif
#ifdef CONFIG_P2020RDB
#define CONFIG_P2020
#define CONFIG_SYS_L2_SIZE (512 << 10)
#endif
#ifdef CONFIG_SDCARD
#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
#define CONFIG_SPL_ENV_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SPL_MMC_MINIMAL
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_I2C_SUPPORT
#define CONFIG_SYS_TEXT_BASE 0x11001000
#define CONFIG_SPL_TEXT_BASE 0xf8f81000
#define CONFIG_SPL_PAD_TO 0x20000
#define CONFIG_SPL_MAX_SIZE (128 * 1024)
#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
#define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
#define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
#define CONFIG_SYS_MMC_U_BOOT_OFFS (129 << 10)
#define CONFIG_SYS_MPC85XX_NO_RESETVEC
#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
#define CONFIG_SPL_MMC_BOOT
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SPL_COMMON_INIT_DDR
#endif
#endif
#ifdef CONFIG_SPIFLASH
#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
#define CONFIG_SPL_ENV_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_SPI_SUPPORT
#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SPL_SPI_FLASH_MINIMAL
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_I2C_SUPPORT
#define CONFIG_SYS_TEXT_BASE 0x11001000
#define CONFIG_SPL_TEXT_BASE 0xf8f81000
#define CONFIG_SPL_PAD_TO 0x20000
#define CONFIG_SPL_MAX_SIZE (128 * 1024)
#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10)
#define CONFIG_SYS_MPC85XX_NO_RESETVEC
#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
#define CONFIG_SPL_SPI_BOOT
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SPL_COMMON_INIT_DDR
#endif
#endif
#ifdef CONFIG_NAND
#ifdef CONFIG_TPL_BUILD
#define CONFIG_SPL_NAND_BOOT
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_ENV_SUPPORT
#define CONFIG_SPL_NAND_INIT
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_I2C_SUPPORT
#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
#define CONFIG_SPL_COMMON_INIT_DDR
#define CONFIG_SPL_MAX_SIZE (128 << 10)
#define CONFIG_SPL_TEXT_BASE 0xf8f81000
#define CONFIG_SYS_MPC85XX_NO_RESETVEC
#define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10)
#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
#define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
#elif defined(CONFIG_SPL_BUILD)
#define CONFIG_SPL_INIT_MINIMAL
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
#define CONFIG_SPL_TEXT_BASE 0xff800000
#define CONFIG_SPL_MAX_SIZE 4096
#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
#define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
#define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
#define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
#endif /* not CONFIG_TPL_BUILD */
#define CONFIG_SPL_PAD_TO 0x20000
#define CONFIG_TPL_PAD_TO 0x20000
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
#define CONFIG_SYS_TEXT_BASE 0x11001000
#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
#endif
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0xeff40000
#endif
#ifndef CONFIG_RESET_VECTOR_ADDRESS
#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
#endif
#ifndef CONFIG_SYS_MONITOR_BASE
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
#else
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#endif
#endif
/* High Level Configuration Options */
#define CONFIG_BOOKE 1 /* BOOKE */
#define CONFIG_E500 1 /* BOOKE e500 family */
#define CONFIG_FSL_ELBC 1 /* Enable eLBC Support */
#define CONFIG_PCI 1 /* Enable PCI/PCIE */
#if defined(CONFIG_PCI)
#define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
#define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#endif /* #if defined(CONFIG_PCI) */
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
#if defined(CONFIG_PCI)
#define CONFIG_E1000 1 /* E1000 pci Ethernet card*/
#endif
#ifndef __ASSEMBLY__
extern unsigned long get_board_sys_clk(unsigned long dummy);
#endif
#define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on P1_P2 RDB */
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /*sysclk for P1_P2 RDB */
#if defined(CONFIG_P2020) || defined(CONFIG_P1020)
#define CONFIG_MP
#endif
#define CONFIG_HWCONFIG
/*
* These can be toggled for performance analysis, otherwise use default.
*/
#define CONFIG_L2_CACHE /* toggle L2 cache */
#define CONFIG_BTB /* toggle branch predition */
#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
#define CONFIG_ENABLE_36BIT_PHYS 1
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_ADDR_MAP 1
#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
#endif
#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x1fffffff
#define CONFIG_PANIC_HANG /* do not reset board on panic */
/*
* Config the L2 Cache as L2 SRAM
*/
#if defined(CONFIG_SPL_BUILD)
#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
#define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10)
#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
#if defined(CONFIG_P2020RDB)
#define CONFIG_SPL_RELOC_MALLOC_SIZE (364 << 10)
#else
#define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10)
#endif
#elif defined(CONFIG_NAND)
#ifdef CONFIG_TPL_BUILD
#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
#define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
#else
#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
#define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000)
#define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
#endif /* CONFIG_TPL_BUILD */
#endif
#endif
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
#endif
/* DDR Setup */
#define CONFIG_SYS_FSL_DDR2
#undef CONFIG_FSL_DDR_INTERACTIVE
#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
#if defined(CONFIG_P1011RDB) || defined(CONFIG_P1020RDB)
/*
* P1020 and it's derivatives support max 32bit DDR width
* So Reduce available DDR size
*/
#define CONFIG_SYS_SDRAM_SIZE 512
#else
#define CONFIG_SYS_SDRAM_SIZE 1024
#endif
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL 1
#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
#define CONFIG_SYS_DDR_ERR_DIS 0x00000000
#define CONFIG_SYS_DDR_SBE 0x00FF0000
/*
* Memory map
*
* 0x0000_0000 0x3fff_ffff DDR 1G cacheablen
* 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
* 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
*
* Localbus cacheable (TBD)
* 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
*
* Localbus non-cacheable
* 0xef00_0000 0xefff_ffff FLASH 16M non-cacheable
* 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable
* 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable
* 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
* 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
*/
/*
* Local Bus Definitions
*/
#define CONFIG_SYS_FLASH_BASE 0xef000000 /* start of FLASH 16M */
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_FLASH_BASE_PHYS 0xfef000000ull
#else
#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
#endif
#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
BR_PS_16 | BR_V)
#define CONFIG_FLASH_OR_PRELIM 0xff000ff7
#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
#define CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
#undef CONFIG_SYS_FLASH_CHECKSUM
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
#define CONFIG_MISC_INIT_R
#define CONFIG_HWCONFIG
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
/* The assembler doesn't like typecast */
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
#else
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
#endif
#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
- GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/
#define CONFIG_SYS_NAND_BASE 0xff800000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
#else
#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
#endif
#define CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_NAND_FSL_ELBC 1
#define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
/* NAND flash config */
#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
| BR_PS_8 /* Port Size = 8 bit */ \
| BR_MS_FCM /* MSEL = FCM */ \
| BR_V) /* valid */
#define CONFIG_SYS_NAND_OR_PRELIM (0xFFF80000 /* length 32K */ \
| OR_FCM_CSCT \
| OR_FCM_CST \
| OR_FCM_CHT \
| OR_FCM_SCY_1 \
| OR_FCM_TRLX \
| OR_FCM_EHTR)
#ifdef CONFIG_NAND
#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
#define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
#define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
#else
#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
#endif
#define CONFIG_SYS_VSC7385_BASE 0xffb00000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull
#else
#define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE
#endif
#define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE) \
| BR_PS_8 | BR_V)
#define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX | \
OR_GPCM_EHTR | OR_GPCM_EAD)
/* Serial Port - controlled on board with jumper J8
* open - index 2
* shorted - index 1
*/
#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
#define CONFIG_NS16550_MIN_FUNCTIONS
#endif
#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
/* Use the HUSH parser */
#define CONFIG_SYS_HUSH_PARSER
/*
* Pass open firmware flat tree
*/
#define CONFIG_OF_LIBFDT 1
#define CONFIG_OF_BOARD_SETUP 1
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
/* new uImage format support */
#define CONFIG_FIT 1
#define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */
/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
#define CONFIG_SYS_FSL_I2C_SPEED 400000
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
#define CONFIG_SYS_FSL_I2C2_SPEED 400000
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
/*
* I2C2 EEPROM
*/
#define CONFIG_ID_EEPROM
#ifdef CONFIG_ID_EEPROM
#define CONFIG_SYS_I2C_EEPROM_NXID
#endif
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_EEPROM_BUS_NUM 1
#define CONFIG_SYS_I2C_PCA9557_ADDR 0x18
#define CONFIG_RTC_DS1337
#define CONFIG_SYS_RTC_DS1337_NOOSC
#define CONFIG_SYS_I2C_RTC_ADDR 0x68
/* eSPI - Enhanced SPI */
#define CONFIG_FSL_ESPI
#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_SPANSION
#define CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_SPEED 10000000
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
/*
* General PCI
* Memory space is mapped 1-1, but I/O space must start from 0.
*/
#if defined(CONFIG_PCI)
/* controller 2, Slot 2, tgtid 2, Base address 9000 */
#define CONFIG_SYS_PCIE2_NAME "Slot 1"
#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
#else
#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
#endif
#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
#else
#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
#endif
#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
/* controller 1, Slot 1, tgtid 1, Base address a000 */
#define CONFIG_SYS_PCIE1_NAME "Slot 2"
#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
#else
#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
#endif
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
#else
#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
#endif
#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
#undef CONFIG_RTL8139
#ifdef CONFIG_RTL8139
/* This macro is used by RTL8139 but not defined in PPC architecture */
#define KSEG1ADDR(x) (x)
#define _IO_BASE 0x00000000
#endif
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CONFIG_DOS_PARTITION
#endif /* CONFIG_PCI */
#if defined(CONFIG_TSEC_ENET)
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
#define CONFIG_TSEC1 1
#define CONFIG_TSEC1_NAME "eTSEC1"
#define CONFIG_TSEC2 1
#define CONFIG_TSEC2_NAME "eTSEC2"
#define CONFIG_TSEC3 1
#define CONFIG_TSEC3_NAME "eTSEC3"
#define TSEC1_PHY_ADDR 2
#define TSEC2_PHY_ADDR 0
#define TSEC3_PHY_ADDR 1
#define CONFIG_VSC7385_ENET
#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
#define TSEC3_PHYIDX 0
/* Vitesse 7385 */
#ifdef CONFIG_VSC7385_ENET
/* The size of the VSC7385 firmware image */
#define CONFIG_VSC7385_IMAGE_SIZE 8192
#endif
#define CONFIG_ETHPRIME "eTSEC1"
#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
#endif /* CONFIG_TSEC_ENET */
/*
* Environment
*/
#ifdef CONFIG_SPIFLASH
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SPI_BUS 0
#define CONFIG_ENV_SPI_CS 0
#define CONFIG_ENV_SPI_MAX_HZ 10000000
#define CONFIG_ENV_SPI_MODE 0
#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
#define CONFIG_ENV_SECT_SIZE 0x10000
#define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
#elif defined(CONFIG_SDCARD)
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_FSL_FIXED_MMC_LOCATION
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_ENV_OFFSET (512 * 0x800)
#define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
#elif defined(CONFIG_NAND)
#ifdef CONFIG_TPL_BUILD
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
#else
#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
#endif
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OFFSET (1024 * 1024)
#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
#elif defined(CONFIG_SYS_RAMBOOT)
#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
#define CONFIG_ENV_SIZE 0x2000
#else
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
#endif
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_DATE
#define CONFIG_CMD_ELF
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_SETEXPR
#define CONFIG_CMD_REGINFO
#if defined(CONFIG_PCI)
#define CONFIG_CMD_NET
#define CONFIG_CMD_PCI
#endif
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_MMC 1
#ifdef CONFIG_MMC
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
#define CONFIG_CMD_MMC
#define CONFIG_DOS_PARTITION
#define CONFIG_FSL_ESDHC
#define CONFIG_GENERIC_MMC
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
#ifdef CONFIG_P2020
#define CONFIG_SYS_FSL_ESDHC_USE_PIO /* P2020 eSDHC DMA is not functional*/
#endif
#endif
#define CONFIG_HAS_FSL_DR_USB
#if defined(CONFIG_HAS_FSL_DR_USB)
#define CONFIG_USB_EHCI
#ifdef CONFIG_USB_EHCI
#define CONFIG_CMD_USB
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_USB_EHCI_FSL
#define CONFIG_USB_STORAGE
#endif
#endif
#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#define CONFIG_DOS_PARTITION
#endif
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_CMDLINE_EDITING /* Command-line editing */
#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
/* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
/*
* For booting Linux, the board info and command line data
* have to be in the first 64 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CONFIG_SYS_BOOTMAPSZ (64 << 20)/* Initial Memory map for Linux*/
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#endif
/*
* Environment Configuration
*/
#if defined(CONFIG_TSEC_ENET)
#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1
#define CONFIG_HAS_ETH2
#endif
#define CONFIG_HOSTNAME P2020RDB
#define CONFIG_ROOTPATH "/opt/nfsroot"
#define CONFIG_BOOTFILE "uImage"
#define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */
/* default location for tftp and bootm */
#define CONFIG_LOADADDR 1000000
#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
#define CONFIG_BAUDRATE 115200
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
"loadaddr=1000000\0" \
"tftpflash=tftpboot $loadaddr $uboot; " \
"protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
" +$filesize; " \
"erase " __stringify(CONFIG_SYS_TEXT_BASE) \
" +$filesize; " \
"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
" $filesize; " \
"protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
" +$filesize; " \
"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
" $filesize\0" \
"consoledev=ttyS0\0" \
"ramdiskaddr=2000000\0" \
"ramdiskfile=rootfs.ext2.gz.uboot\0" \
"fdtaddr=c00000\0" \
"fdtfile=p2020rdb.dtb\0" \
"bdev=sda1\0" \
"jffs2nor=mtdblock3\0" \
"norbootaddr=ef080000\0" \
"norfdtaddr=ef040000\0" \
"jffs2nand=mtdblock9\0" \
"nandbootaddr=100000\0" \
"nandfdtaddr=80000\0" \
"nandimgsize=400000\0" \
"nandfdtsize=80000\0" \
"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \
"vscfw_addr=ef000000\0" \
"othbootargs=ramdisk_size=600000\0" \
"usbfatboot=setenv bootargs root=/dev/ram rw " \
"console=$consoledev,$baudrate $othbootargs; " \
"usb start;" \
"fatload usb 0:2 $loadaddr $bootfile;" \
"fatload usb 0:2 $fdtaddr $fdtfile;" \
"fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
"bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
"usbext2boot=setenv bootargs root=/dev/ram rw " \
"console=$consoledev,$baudrate $othbootargs; " \
"usb start;" \
"ext2load usb 0:4 $loadaddr $bootfile;" \
"ext2load usb 0:4 $fdtaddr $fdtfile;" \
"ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
"bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
"norboot=setenv bootargs root=/dev/$jffs2nor rw " \
"console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
"bootm $norbootaddr - $norfdtaddr\0" \
"nandboot=setenv bootargs root=/dev/$jffs2nand rw rootfstype=jffs2 " \
"console=$consoledev,$baudrate $othbootargs;" \
"nand read 2000000 $nandbootaddr $nandimgsize;" \
"nand read 3000000 $nandfdtaddr $nandfdtsize;" \
"bootm 2000000 - 3000000;\0"
#define CONFIG_NFSBOOTCOMMAND \
"setenv bootargs root=/dev/nfs rw " \
"nfsroot=$serverip:$rootpath " \
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $loadaddr $bootfile;" \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr - $fdtaddr"
#define CONFIG_HDBOOT \
"setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
"console=$consoledev,$baudrate $othbootargs;" \
"usb start;" \
"ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
"ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
"bootm $loadaddr - $fdtaddr"
#define CONFIG_RAMBOOTCOMMAND \
"setenv bootargs root=/dev/ram rw " \
"console=$consoledev,$baudrate $othbootargs; " \
"tftp $ramdiskaddr $ramdiskfile;" \
"tftp $loadaddr $bootfile;" \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr $ramdiskaddr $fdtaddr"
#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
#endif /* __CONFIG_H */

547
include/configs/P2020COME.h
View File

@@ -1,547 +0,0 @@
/*
* Copyright 2009-2010,2012 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/* The P2020COME board is only booted via the Freescale On-Chip ROM */
#define CONFIG_SYS_RAMBOOT
#define CONFIG_SYS_EXTRA_ENV_RELOC
#define CONFIG_SYS_TEXT_BASE 0xf8f80000
#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc
#ifdef CONFIG_SDCARD
#define CONFIG_RAMBOOT_SDCARD 1
#endif
#ifdef CONFIG_SPIFLASH
#define CONFIG_RAMBOOT_SPIFLASH 1
#endif
#ifndef CONFIG_SYS_MONITOR_BASE
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#endif
/* High Level Configuration Options */
#define CONFIG_BOOKE 1 /* BOOKE */
#define CONFIG_E500 1 /* BOOKE e500 family */
#define CONFIG_P2020 1
#define CONFIG_P2020COME 1
#define CONFIG_FSL_ELBC 1 /* Enable eLBC Support */
#define CONFIG_MP
#define CONFIG_PCI 1 /* Enable PCI/PCIE */
#if defined(CONFIG_PCI)
#define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */
#define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */
#define CONFIG_PCIE3 1 /* PCIE controller 3 (slot 3) */
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#endif /* #if defined(CONFIG_PCI) */
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
#if defined(CONFIG_PCI)
#define CONFIG_E1000 1 /* E1000 pci Ethernet card */
#endif
#ifndef __ASSEMBLY__
extern unsigned long get_board_ddr_clk(unsigned long dummy);
extern unsigned long get_board_sys_clk(unsigned long dummy);
#endif
/*
* For P2020COME DDRCLK and SYSCLK are from the same oscillator
* For DA phase the SYSCLK is 66MHz
* For EA phase the SYSCLK is 100MHz
*/
#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0)
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
#define CONFIG_HWCONFIG
/*
* These can be toggled for performance analysis, otherwise use default.
*/
#define CONFIG_L2_CACHE /* toggle L2 cache */
#define CONFIG_BTB /* toggle branch prediction */
#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
#define CONFIG_ENABLE_36BIT_PHYS 1
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_ADDR_MAP 1
#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
#endif
#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x1fffffff
#define CONFIG_PANIC_HANG /* do not reset board on panic */
/*
* Config the L2 Cache as L2 SRAM
*/
#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull
#else
#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
#endif
#define CONFIG_SYS_L2_SIZE (512 << 10)
#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR \
+ CONFIG_SYS_L2_SIZE)
#define CONFIG_SYS_CCSRBAR 0xffe00000
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
/* DDR Setup */
#define CONFIG_SYS_FSL_DDR3
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
#define CONFIG_DDR_SPD
#define CONFIG_DDR_ECC
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#define CONFIG_SYS_SDRAM_SIZE 2048ULL /* DDR size on P2020COME */
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL 2
#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
#define CONFIG_SYS_DDR_ERR_DIS 0x00000000
#define CONFIG_SYS_DDR_SBE 0x00ff0000
#define CONFIG_SYS_SPD_BUS_NUM 1
#define SPD_EEPROM_ADDRESS 0x53
/*
* Memory map
*
* 0x0000_0000 0x7fff_ffff DDR3 2G Cacheable
* 0x8000_0000 0x9fff_ffff PCI Express 3 Mem 1G non-cacheable
* 0xa000_0000 0xbfff_ffff PCI Express 2 Mem 1G non-cacheable
* 0xc000_0000 0xdfff_ffff PCI Express 1 Mem 1G non-cacheable
* 0xffc1_0000 0xffc1_ffff PCI Express 3 IO 64K non-cacheable
* 0xffc2_0000 0xffc2_ffff PCI Express 2 IO 64K non-cacheable
* 0xffc3_0000 0xffc3_ffff PCI Express 1 IO 64K non-cacheable
*
* 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
* 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
*/
/*
* Local Bus Definitions
*/
/* There is no NOR Flash on P2020COME */
#define CONFIG_SYS_NO_FLASH
#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
#define CONFIG_HWCONFIG
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
/* the assembler doesn't like typecast */
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
#else
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
#endif
#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
- GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
/* Serial Port - controlled on board with jumper J8
* open - index 2
* shorted - index 1
*/
#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
/* Use the HUSH parser */
#define CONFIG_SYS_HUSH_PARSER
/*
* Pass open firmware flat tree
*/
#define CONFIG_OF_LIBFDT 1
#define CONFIG_OF_BOARD_SETUP 1
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
/* new uImage format support */
#define CONFIG_FIT 1
#define CONFIG_FIT_VERBOSE 1
/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED 400000
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
#define CONFIG_SYS_FSL_I2C2_SPEED 400000
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
/*
* I2C2 EEPROM
*/
#define CONFIG_ID_EEPROM
#ifdef CONFIG_ID_EEPROM
#define CONFIG_SYS_I2C_EEPROM_NXID
#endif
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
#define CONFIG_SYS_I2C_EEPROM_ADDR2 0x18
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_EEPROM_BUS_NUM 0
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
/*
* eSPI - Enhanced SPI
*/
#define CONFIG_FSL_ESPI
#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_SPEED 10000000
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
/*
* General PCI
* Memory space is mapped 1-1, but I/O space must start from 0.
*/
#if defined(CONFIG_PCI)
/* controller 3, Slot 3, tgtid 3, Base address 8000 */
#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
#define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc10000
#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc10000
#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
/* controller 2, Slot 2, tgtid 2, Base address 9000 */
#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc20000
#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000
#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
/* controller 1, Slot 1, tgtid 1, Base address a000 */
#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc30000
#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc30000
#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
#undef CONFIG_RTL8139
#ifdef CONFIG_RTL8139
/* This macro is used by RTL8139 but not defined in PPC architecture */
#define KSEG1ADDR(x) (x)
#define _IO_BASE 0x00000000
#endif
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CONFIG_DOS_PARTITION
#endif /* CONFIG_PCI */
#if defined(CONFIG_TSEC_ENET)
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
#define CONFIG_TSEC1 1
#define CONFIG_TSEC1_NAME "eTSEC1"
#define CONFIG_TSEC2 1
#define CONFIG_TSEC2_NAME "eTSEC2"
#define CONFIG_TSEC3 1
#define CONFIG_TSEC3_NAME "eTSEC3"
#define TSEC1_PHY_ADDR 0
#define TSEC2_PHY_ADDR 2
#define TSEC3_PHY_ADDR 1
#undef CONFIG_VSC7385_ENET
#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
#define TSEC3_PHYIDX 0
#define CONFIG_ETHPRIME "eTSEC1"
#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
#endif /* CONFIG_TSEC_ENET */
/*
* Environment
*/
#if defined(CONFIG_RAMBOOT_SDCARD)
#define CONFIG_ENV_IS_IN_MMC 1
#define CONFIG_FSL_FIXED_MMC_LOCATION
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_SYS_MMC_ENV_DEV 0
#elif defined(CONFIG_RAMBOOT_SPIFLASH)
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SPI_BUS 0
#define CONFIG_ENV_SPI_CS 0
#define CONFIG_ENV_SPI_MAX_HZ 10000000
#define CONFIG_ENV_SPI_MODE 0
#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
#define CONFIG_ENV_SECT_SIZE 0x10000
#define CONFIG_ENV_SIZE 0x2000
#endif
#define CONFIG_LOADS_ECHO 1
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_ELF
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_SETEXPR
#define CONFIG_CMD_REGINFO
#if defined(CONFIG_PCI)
#define CONFIG_CMD_NET
#define CONFIG_CMD_PCI
#endif
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_MMC 1
#ifdef CONFIG_MMC
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
#define CONFIG_CMD_MMC
#define CONFIG_DOS_PARTITION
#define CONFIG_FSL_ESDHC
#define CONFIG_GENERIC_MMC
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
#endif /* CONFIG_MMC */
#define CONFIG_HAS_FSL_DR_USB
#ifdef CONFIG_HAS_FSL_DR_USB
#define CONFIG_USB_EHCI
#ifdef CONFIG_USB_EHCI
#define CONFIG_CMD_USB
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_USB_EHCI_FSL
#define CONFIG_USB_STORAGE
#endif
#endif
#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#define CONFIG_DOS_PARTITION
#endif
/* Misc Extra Settings */
#define CONFIG_CMD_DHCP 1
#define CONFIG_CMD_DATE 1
#define CONFIG_RTC_M41T62 1
#define CONFIG_SYS_RTC_BUS_NUM 1
#define CONFIG_SYS_I2C_RTC_ADDR 0x68
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_CMDLINE_EDITING /* Command-line editing */
#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
/* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
/*
* For booting Linux, the board info and command line data
* have to be in the first 64 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CONFIG_SYS_BOOTMAPSZ (64 << 20)
#define CONFIG_SYS_BOOTM_LEN (64 << 20)
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#endif
/*
* Environment Configuration
*/
/* The mac addresses for all ethernet interface */
#if defined(CONFIG_TSEC_ENET)
#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1
#define CONFIG_HAS_ETH2
#define CONFIG_HAS_ETH3
#endif
#define CONFIG_HOSTNAME unknown
#define CONFIG_ROOTPATH "/opt/nfsroot"
#define CONFIG_BOOTFILE "uImage"
#define CONFIG_UBOOTPATH u-boot.bin
/* default location for tftp and bootm */
#define CONFIG_LOADADDR 1000000
#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
#define CONFIG_BAUDRATE 115200
#define CONFIG_EXTRA_ENV_SETTINGS \
"hwconfig=fsl_ddr:ecc=on\0" \
"bootcmd=run sdboot\0" \
"sdboot=setenv bootargs root=/dev/mmcblk0p2 rw " \
"rootdelay=$rootdelaysecond console=$consoledev,$baudrate "\
"$othbootargs; mmcinfo; " \
"ext2load mmc 0:2 $loadaddr /boot/$bootfile; " \
"ext2load mmc 0:2 $fdtaddr /boot/$fdtfile; " \
"bootm $loadaddr - $fdtaddr\0" \
"sdfatboot=setenv bootargs root=/dev/ram rw " \
"rootdelay=$rootdelaysecond console=$consoledev,$baudrate "\
"$othbootargs; mmcinfo; " \
"fatload mmc 0:1 $loadaddr $bootfile; " \
"fatload mmc 0:1 $fdtaddr $fdtfile; " \
"fatload mmc 0:1 $ramdiskaddr $ramdiskfile; " \
"bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
"usbboot=setenv bootargs root=/dev/sda1 rw " \
"rootdelay=$rootdelaysecond console=$consoledev,$baudrate "\
"$othbootargs; " \
"usb start; " \
"ext2load usb 0:1 $loadaddr /boot/$bootfile; " \
"ext2load usb 0:1 $fdtaddr /boot/$fdtfile; " \
"bootm $loadaddr - $fdtaddr\0" \
"usbfatboot=setenv bootargs root=/dev/ram rw " \
"console=$consoledev,$baudrate $othbootargs; " \
"usb start; " \
"fatload usb 0:2 $loadaddr $bootfile; " \
"fatload usb 0:2 $fdtaddr $fdtfile; " \
"fatload usb 0:2 $ramdiskaddr $ramdiskfile; " \
"bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
"usbext2boot=setenv bootargs root=/dev/ram rw " \
"console=$consoledev,$baudrate $othbootargs; " \
"usb start; " \
"ext2load usb 0:4 $loadaddr $bootfile; " \
"ext2load usb 0:4 $fdtaddr $fdtfile; " \
"ext2load usb 0:4 $ramdiskaddr $ramdiskfile; " \
"bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
"upgradespi=sf probe 0; " \
"setenv startaddr 0; " \
"setenv erasesize a0000; " \
"tftp 1000000 $tftppath/$uboot_spi; " \
"sf erase $startaddr $erasesize; " \
"sf write 1000000 $startaddr $filesize; " \
"sf erase 100000 120000\0" \
"clearspienv=sf probe 0;sf erase 100000 20000\0" \
"othbootargs=ramdisk_size=700000 cache-sram-size=0x10000\0" \
"netdev=eth0\0" \
"rootdelaysecond=15\0" \
"uboot_nor=u-boot-nor.bin\0" \
"uboot_spi=u-boot-p2020.spi\0" \
"uboot_sd=u-boot-p2020.bin\0" \
"consoledev=ttyS0\0" \
"ramdiskaddr=2000000\0" \
"ramdiskfile=rootfs-dev.ext2.img\0" \
"fdtaddr=c00000\0" \
"fdtfile=uImage-2.6.32-p2020.dtb\0" \
"tftppath=p2020\0"
#define CONFIG_HDBOOT \
"setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
"console=$consoledev,$baudrate $othbootargs;" \
"usb start;" \
"ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
"ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
"bootm $loadaddr - $fdtaddr"
#define CONFIG_NFSBOOTCOMMAND \
"setenv bootargs root=/dev/nfs rw " \
"nfsroot=$serverip:$rootpath " \
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "\
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $loadaddr $tftppath/$bootfile;" \
"tftp $fdtaddr $tftppath/$fdtfile;" \
"bootm $loadaddr - $fdtaddr"
#define CONFIG_RAMBOOTCOMMAND \
"setenv bootargs root=/dev/ram rw " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $ramdiskaddr $tftppath/$ramdiskfile;" \
"tftp $loadaddr $tftppath/$bootfile;" \
"tftp $fdtaddr $tftppath/$fdtfile;" \
"bootm $loadaddr $ramdiskaddr $fdtaddr"
#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
#endif /* __CONFIG_H */

751
include/configs/P2020DS.h
View File

@@ -1,751 +0,0 @@
/*
* Copyright 2007-2012 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
/*
* p2020ds board configuration file
*
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#include "../board/freescale/common/ics307_clk.h"
#ifdef CONFIG_36BIT
#define CONFIG_PHYS_64BIT
#endif
#ifdef CONFIG_SDCARD
#define CONFIG_SYS_RAMBOOT
#define CONFIG_SYS_EXTRA_ENV_RELOC
#define CONFIG_SYS_TEXT_BASE 0xf8f40000
#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc
#endif
#ifdef CONFIG_SPIFLASH
#define CONFIG_SYS_RAMBOOT
#define CONFIG_SYS_EXTRA_ENV_RELOC
#define CONFIG_SYS_TEXT_BASE 0xf8f40000
#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc
#endif
/* High Level Configuration Options */
#define CONFIG_BOOKE 1 /* BOOKE */
#define CONFIG_E500 1 /* BOOKE e500 family */
#define CONFIG_P2020 1
#define CONFIG_P2020DS 1
#define CONFIG_MP 1 /* support multiple processors */
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0xeff40000
#endif
#ifndef CONFIG_RESET_VECTOR_ADDRESS
#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
#endif
#define CONFIG_SYS_SRIO
#define CONFIG_SRIO1 /* SRIO port 1 */
#define CONFIG_SRIO2 /* SRIO port 2 */
#define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */
#define CONFIG_PCI 1 /* Enable PCI/PCIE */
#define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
#define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */
#define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
#define CONFIG_E1000 1 /* Defind e1000 pci Ethernet card*/
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() /* ddrclk for MPC85xx */
#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
/*
* These can be toggled for performance analysis, otherwise use default.
*/
#define CONFIG_L2_CACHE /* toggle L2 cache */
#define CONFIG_BTB /* toggle branch predition */
#define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */
#define CONFIG_ENABLE_36BIT_PHYS 1
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_ADDR_MAP 1
#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
#endif
#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x00400000
#define CONFIG_PANIC_HANG /* do not reset board on panic */
/*
* Config the L2 Cache
*/
#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull
#else
#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
#endif
#define CONFIG_SYS_L2_SIZE (512 << 10)
#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
#define CONFIG_SYS_CCSRBAR 0xffe00000
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
/* DDR Setup */
#define CONFIG_VERY_BIG_RAM
#ifdef CONFIG_DDR2
#define CONFIG_SYS_FSL_DDR2
#else
#define CONFIG_SYS_FSL_DDR3 1
#endif
/* ECC will be enabled based on perf_mode environment variable */
/* #define CONFIG_DDR_ECC */
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL 2
/* I2C addresses of SPD EEPROMs */
#define CONFIG_DDR_SPD
#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD EEPROM located on I2C bus 0 */
#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
/* These are used when DDR doesn't use SPD. */
#define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR is 1GB */
/* Default settings for "stable" mode */
#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
#define CONFIG_SYS_DDR_CS1_BNDS 0x00000000
#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
#define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000
#define CONFIG_SYS_DDR_TIMING_3 0x00020000
#define CONFIG_SYS_DDR_TIMING_0 0x00330804
#define CONFIG_SYS_DDR_TIMING_1 0x6f6b4846
#define CONFIG_SYS_DDR_TIMING_2 0x0fa890d4
#define CONFIG_SYS_DDR_MODE_1 0x00421422
#define CONFIG_SYS_DDR_MODE_2 0x00000000
#define CONFIG_SYS_DDR_MODE_CTRL 0x00000000
#define CONFIG_SYS_DDR_INTERVAL 0x61800100
#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
#define CONFIG_SYS_DDR_CLK_CTRL 0x02000000
#define CONFIG_SYS_DDR_TIMING_4 0x00220001
#define CONFIG_SYS_DDR_TIMING_5 0x03402400
#define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600
#define CONFIG_SYS_DDR_WRLVL_CNTL 0x8655A608
#define CONFIG_SYS_DDR_CONTROL 0xE7000000 /* Type = DDR3: ECC enabled, No Interleaving */
#define CONFIG_SYS_DDR_CONTROL2 0x24400011
#define CONFIG_SYS_DDR_CDR1 0x00040000
#define CONFIG_SYS_DDR_CDR2 0x00000000
#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
#define CONFIG_SYS_DDR_ERR_DIS 0x00000000
#define CONFIG_SYS_DDR_SBE 0x00010000
/* Settings that differ for "performance" mode */
#define CONFIG_SYS_DDR_CS0_BNDS_PERF 0x0000007F /* Interleaving Enabled */
#define CONFIG_SYS_DDR_CS1_BNDS_PERF 0x00000000 /* Interleaving Enabled */
#define CONFIG_SYS_DDR_CS1_CONFIG_PERF 0x80014202
#define CONFIG_SYS_DDR_TIMING_1_PERF 0x5d5b4543
#define CONFIG_SYS_DDR_TIMING_2_PERF 0x0fa890ce
#define CONFIG_SYS_DDR_CONTROL_PERF 0xC7004000 /* Type = DDR3: ECC disabled, cs0-cs1 interleaving */
/*
* The following set of values were tested for DDR2
* with a DDR3 to DDR2 interposer
*
#define CONFIG_SYS_DDR_TIMING_3 0x00000000
#define CONFIG_SYS_DDR_TIMING_0 0x00260802
#define CONFIG_SYS_DDR_TIMING_1 0x3935d322
#define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
#define CONFIG_SYS_DDR_MODE_1 0x00480432
#define CONFIG_SYS_DDR_MODE_2 0x00000000
#define CONFIG_SYS_DDR_INTERVAL 0x06180100
#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
#define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
#define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
#define CONFIG_SYS_DDR_CONTROL 0xC3008000
#define CONFIG_SYS_DDR_CONTROL2 0x04400010
*
*/
/*
* Memory map
*
* 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
* 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
* 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
* 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
*
* Localbus cacheable (TBD)
* 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
*
* Localbus non-cacheable
* 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable
* 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable
* 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable
* 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0
* 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
* 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
*/
/*
* Local Bus Definitions
*/
#define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
#else
#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
#endif
#define CONFIG_FLASH_BR_PRELIM \
(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V)
#define CONFIG_FLASH_OR_PRELIM 0xf8000ff7
#define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
#define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
#define CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
#define CONFIG_HWCONFIG /* enable hwconfig */
#define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */
#ifdef CONFIG_FSL_NGPIXIS
#define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
#ifdef CONFIG_PHYS_64BIT
#define PIXIS_BASE_PHYS 0xfffdf0000ull
#else
#define PIXIS_BASE_PHYS PIXIS_BASE
#endif
#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
#define PIXIS_LBMAP_SWITCH 7
#define PIXIS_LBMAP_MASK 0xf0
#define PIXIS_LBMAP_SHIFT 4
#define PIXIS_LBMAP_ALTBANK 0x20
#endif
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
/* The assembler doesn't like typecast */
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
#else
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
#endif
#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
#define CONFIG_SYS_NAND_BASE 0xffa00000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
#else
#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
#endif
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\
CONFIG_SYS_NAND_BASE + 0x40000, \
CONFIG_SYS_NAND_BASE + 0x80000,\
CONFIG_SYS_NAND_BASE + 0xC0000}
#define CONFIG_SYS_MAX_NAND_DEVICE 4
#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_CMD_NAND 1
#define CONFIG_NAND_FSL_ELBC 1
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
/* NAND flash config */
#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
| BR_PS_8 /* Port Size = 8bit */ \
| BR_MS_FCM /* MSEL = FCM */ \
| BR_V) /* valid */
#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
| OR_FCM_PGS /* Large Page*/ \
| OR_FCM_CSCT \
| OR_FCM_CST \
| OR_FCM_CHT \
| OR_FCM_SCY_1 \
| OR_FCM_TRLX \
| OR_FCM_EHTR)
#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
#define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
#define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
| BR_PS_8 /* Port Size = 8bit */ \
| BR_MS_FCM /* MSEL = FCM */ \
| BR_V) /* valid */
#define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
#define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000) \
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
| BR_PS_8 /* Port Size = 8bit */ \
| BR_MS_FCM /* MSEL = FCM */ \
| BR_V) /* valid */
#define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
#define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000) \
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
| BR_PS_8 /* Port Size = 8bit */ \
| BR_MS_FCM /* MSEL = FCM */ \
| BR_V) /* valid */
#define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
/* Serial Port - controlled on board with jumper J8
* open - index 2
* shorted - index 1
*/
#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
/* Use the HUSH parser */
#define CONFIG_SYS_HUSH_PARSER
/*
* Pass open firmware flat tree
*/
#define CONFIG_OF_LIBFDT 1
#define CONFIG_OF_BOARD_SETUP 1
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
#define CONFIG_SYS_FSL_I2C_SPEED 400000
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
#define CONFIG_SYS_FSL_I2C2_SPEED 400000
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
/*
* I2C2 EEPROM
*/
#define CONFIG_ID_EEPROM
#ifdef CONFIG_ID_EEPROM
#define CONFIG_SYS_I2C_EEPROM_NXID
#endif
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_EEPROM_BUS_NUM 0
/*
* eSPI - Enhanced SPI
*/
#define CONFIG_FSL_ESPI
#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_SPANSION
#define CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_SPEED 10000000
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
/*
* General PCI
* Memory space is mapped 1-1, but I/O space must start from 0.
*/
/* controller 3, Slot 1, tgtid 3, Base address b000 */
#define CONFIG_SYS_PCIE3_NAME "Slot 1"
#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull
#else
#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
#define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
#endif
#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull
#else
#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000
#endif
#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
/* controller 2, direct to uli, tgtid 2, Base address 9000 */
#define CONFIG_SYS_PCIE2_NAME "ULI"
#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
#else
#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
#endif
#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
#else
#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
#endif
#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
/* controller 1, Slot 2, tgtid 1, Base address a000 */
#define CONFIG_SYS_PCIE1_NAME "Slot 2"
#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
#else
#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
#endif
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull
#else
#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
#endif
#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
#if defined(CONFIG_PCI)
/*PCIE video card used*/
#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT
/* video */
#undef CONFIG_VIDEO
#if defined(CONFIG_VIDEO)
#define CONFIG_BIOSEMU
#define CONFIG_CFB_CONSOLE
#define CONFIG_VIDEO_SW_CURSOR
#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_ATI_RADEON_FB
#define CONFIG_VIDEO_LOGO
/*#define CONFIG_CONSOLE_CURSOR*/
#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
#endif
/* SRIO1 uses the same window as PCIE2 mem window */
#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
#else
#define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
#endif
#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */
/* SRIO2 uses the same window as PCIE1 mem window */
#define CONFIG_SYS_SRIO2_MEM_VIRT 0xc0000000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc40000000ull
#else
#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc0000000
#endif
#define CONFIG_SYS_SRIO2_MEM_SIZE 0x20000000 /* 512M */
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CONFIG_DOS_PARTITION
#define CONFIG_SCSI_AHCI
#ifdef CONFIG_SCSI_AHCI
#define CONFIG_LIBATA
#define CONFIG_SATA_ULI5288
#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
#define CONFIG_SYS_SCSI_MAX_LUN 1
#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
#define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE
#endif /* SCSI */
#endif /* CONFIG_PCI */
#if defined(CONFIG_TSEC_ENET)
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
#define CONFIG_TSEC1 1
#define CONFIG_TSEC1_NAME "eTSEC1"
#define CONFIG_TSEC2 1
#define CONFIG_TSEC2_NAME "eTSEC2"
#define CONFIG_TSEC3 1
#define CONFIG_TSEC3_NAME "eTSEC3"
#define CONFIG_FSL_SGMII_RISER 1
#define SGMII_RISER_PHY_OFFSET 0x1b
#ifdef CONFIG_FSL_SGMII_RISER
#define CONFIG_SYS_TBIPA_VALUE 0x10 /* avoid conflict with eTSEC4 paddr */
#endif
#define TSEC1_PHY_ADDR 0
#define TSEC2_PHY_ADDR 1
#define TSEC3_PHY_ADDR 2
#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
#define TSEC3_PHYIDX 0
#define CONFIG_ETHPRIME "eTSEC1"
#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
#endif /* CONFIG_TSEC_ENET */
/*
* Environment
*/
#if defined(CONFIG_SDCARD)
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_FSL_FIXED_MMC_LOCATION
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_SYS_MMC_ENV_DEV 0
#elif defined(CONFIG_SPIFLASH)
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SPI_BUS 0
#define CONFIG_ENV_SPI_CS 0
#define CONFIG_ENV_SPI_MAX_HZ 10000000
#define CONFIG_ENV_SPI_MODE 0
#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
#define CONFIG_ENV_SECT_SIZE 0x10000
#else
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
#endif
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_PING
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
#define CONFIG_CMD_ELF
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_SETEXPR
#define CONFIG_CMD_REGINFO
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
#define CONFIG_CMD_NET
#define CONFIG_CMD_SCSI
#define CONFIG_CMD_EXT2
#endif
/*
* USB
*/
#define CONFIG_HAS_FSL_DR_USB
#ifdef CONFIG_HAS_FSL_DR_USB
#define CONFIG_USB_EHCI
#ifdef CONFIG_USB_EHCI
#define CONFIG_CMD_USB
#define CONFIG_USB_STORAGE
#define CONFIG_USB_EHCI_FSL
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#endif
#endif
/*
* SDHC/MMC
*/
#define CONFIG_MMC
#ifdef CONFIG_MMC
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
#define CONFIG_CMD_MMC
#define CONFIG_GENERIC_MMC
#endif
#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#define CONFIG_DOS_PARTITION
#endif
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_CMDLINE_EDITING /* Command-line editing */
#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
/*
* For booting Linux, the board info and command line data
* have to be in the first 64 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#endif
/*
* Environment Configuration
*/
/* The mac addresses for all ethernet interface */
#if defined(CONFIG_TSEC_ENET)
#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1
#define CONFIG_HAS_ETH2
#endif
#define CONFIG_IPADDR 192.168.1.254
#define CONFIG_HOSTNAME unknown
#define CONFIG_ROOTPATH "/opt/nfsroot"
#define CONFIG_BOOTFILE "uImage"
#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
#define CONFIG_SERVERIP 192.168.1.1
#define CONFIG_GATEWAYIP 192.168.1.1
#define CONFIG_NETMASK 255.255.255.0
/* default location for tftp and bootm */
#define CONFIG_LOADADDR 1000000
#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
#define CONFIG_BAUDRATE 115200
#define CONFIG_EXTRA_ENV_SETTINGS \
"perf_mode=performance\0" \
"hwconfig=fsl_ddr:ctlr_intlv=bank,bank_intlv=cs0_cs1;" \
"usb1:dr_mode=host,phy_type=ulpi\0" \
"netdev=eth0\0" \
"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
"tftpflash=tftpboot $loadaddr $uboot; " \
"protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
"erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
"protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
"satabootcmd=setenv bootargs root=/dev/$bdev rw " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $loadaddr $bootfile;" \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr - $fdtaddr" \
"consoledev=ttyS0\0" \
"ramdiskaddr=2000000\0" \
"ramdiskfile=p2020ds/ramdisk.uboot\0" \
"fdtaddr=c00000\0" \
"othbootargs=cache-sram-size=0x10000\0" \
"fdtfile=p2020ds/p2020ds.dtb\0" \
"bdev=sda3\0" \
"partition=scsi 0:0\0"
#define CONFIG_HDBOOT \
"setenv bootargs root=/dev/$bdev rw " \
"console=$consoledev,$baudrate $othbootargs;" \
"ext2load $partition $loadaddr $bootfile;" \
"ext2load $partition $fdtaddr $fdtfile;" \
"bootm $loadaddr - $fdtaddr"
#define CONFIG_NFSBOOTCOMMAND \
"setenv bootargs root=/dev/nfs rw " \
"nfsroot=$serverip:$rootpath " \
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $loadaddr $bootfile;" \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr - $fdtaddr"
#define CONFIG_RAMBOOTCOMMAND \
"setenv bootargs root=/dev/ram rw " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $ramdiskaddr $ramdiskfile;" \
"tftp $loadaddr $bootfile;" \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr $ramdiskaddr $fdtaddr"
#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
#endif /* __CONFIG_H */

342
include/configs/PM520.h
View File

@@ -1,342 +0,0 @@
/*
* (C) Copyright 2003-2005
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_MPC5200
#define CONFIG_PM520 1 /* PM520 board */
#define CONFIG_SYS_TEXT_BASE 0xfff00000
#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33MHz */
#define CONFIG_MISC_INIT_R
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/*
* Serial console configuration
*/
#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
#define CONFIG_BAUDRATE 9600 /* ... at 9600 bps */
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
/*
* PCI Mapping:
* 0x40000000 - 0x4fffffff - PCI Memory
* 0x50000000 - 0x50ffffff - PCI IO Space
*/
#define CONFIG_PCI 1
#define CONFIG_PCI_PNP 1
#define CONFIG_PCI_SCAN_SHOW 1
#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
#define CONFIG_PCI_MEM_BUS 0x40000000
#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
#define CONFIG_PCI_MEM_SIZE 0x10000000
#define CONFIG_PCI_IO_BUS 0x50000000
#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
#define CONFIG_PCI_IO_SIZE 0x01000000
#define CONFIG_MII 1
#define CONFIG_EEPRO100 1
#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
#undef CONFIG_NS8382X
/* Partitions */
#define CONFIG_DOS_PARTITION
/* USB */
#if 1
#define CONFIG_USB_OHCI
#define CONFIG_USB_STORAGE
#endif
/*
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_BEDBUG
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_FAT
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IDE
#define CONFIG_CMD_NFS
#define CONFIG_CMD_SNTP
#define CONFIG_CMD_USB
#define CONFIG_CMD_PCI
/*
* Autobooting
*/
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#define CONFIG_PREBOOT "echo;" \
"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"hostname=pm520\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
"addip=setenv bootargs ${bootargs} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
":${hostname}:${netdev}:off panic=1\0" \
"flash_nfs=run nfsargs addip;" \
"bootm ${kernel_addr}\0" \
"flash_self=run ramargs addip;" \
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk30/ppc_82xx\0" \
"bootfile=/tftpboot/PM520/uImage\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
/*
* IPB Bus clocking configuration.
*/
#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
/*
* I2C configuration
*/
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
#define CONFIG_SYS_I2C_SLAVE 0x7F
/*
* EEPROM configuration
*/
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x58
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
/*
* RTC configuration
*/
#define CONFIG_RTC_PCF8563
#define CONFIG_SYS_I2C_RTC_ADDR 0x51
#define CONFIG_SYS_DOC_BASE 0xE0000000
#define CONFIG_SYS_DOC_SIZE 0x00100000
#if defined(CONFIG_BOOT_ROM)
/*
* Flash configuration (8,16 or 32 MB)
* TEXT base always at 0xFFF00000
* ENV_ADDR always at 0xFFF40000
* FLASH_BASE at 0xFA000000 for 64 MB
* 0xFC000000 for 32 MB
* 0xFD000000 for 16 MB
* 0xFD800000 for 8 MB
*/
#define CONFIG_SYS_FLASH_BASE 0xFA000000
#define CONFIG_SYS_FLASH_SIZE 0x04000000
#define CONFIG_SYS_BOOTROM_BASE 0xFFF00000
#define CONFIG_SYS_BOOTROM_SIZE 0x00080000
#define CONFIG_ENV_ADDR (0xFDF00000 + 0x40000)
#else
/*
* Flash configuration (8,16 or 32 MB)
* TEXT base always at 0xFFF00000
* ENV_ADDR always at 0xFFF40000
* FLASH_BASE at 0xFC000000 for 64 MB
* 0xFE000000 for 32 MB
* 0xFF000000 for 16 MB
* 0xFF800000 for 8 MB
*/
#define CONFIG_SYS_FLASH_BASE 0xFC000000
#define CONFIG_SYS_FLASH_SIZE 0x04000000
#define CONFIG_ENV_ADDR (0xFFF00000 + 0x40000)
#endif
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */
#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
#define CONFIG_SYS_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */
#define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */
#define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */
#undef CONFIG_FLASH_16BIT /* Flash is 32-bit */
/*
* Environment settings
*/
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_SIZE 0x10000
#define CONFIG_ENV_SECT_SIZE 0x40000
#define CONFIG_ENV_OVERWRITE 1
/*
* Memory map
*/
#define CONFIG_SYS_MBAR 0xf0000000
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
/* Use SRAM until RAM will be available */
#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
# define CONFIG_SYS_RAMBOOT 1
#endif
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*
* Ethernet configuration
*/
#define CONFIG_MPC5xxx_FEC 1
#define CONFIG_MPC5xxx_FEC_MII100
/*
* Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
*/
/* #define CONFIG_MPC5xxx_FEC_MII10 */
#define CONFIG_PHY_ADDR 0x00
/*
* GPIO configuration
*/
#define CONFIG_SYS_GPS_PORT_CONFIG 0x10000004
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
#if defined(CONFIG_CMD_KGDB)
# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
/*
* Various low-level settings
*/
#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
#define CONFIG_SYS_HID0_FINAL HID0_ICE
#if defined(CONFIG_BOOT_ROM)
#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_BOOTROM_BASE
#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_BOOTROM_SIZE
#define CONFIG_SYS_BOOTCS_CFG 0x00047800
#define CONFIG_SYS_CS0_START CONFIG_SYS_BOOTROM_BASE
#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_BOOTROM_SIZE
#define CONFIG_SYS_CS1_START CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_CS1_SIZE CONFIG_SYS_FLASH_SIZE
#define CONFIG_SYS_CS1_CFG 0x0004FF00
#else
#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
#define CONFIG_SYS_BOOTCS_CFG 0x0004FF00
#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
#define CONFIG_SYS_CS1_START CONFIG_SYS_DOC_BASE
#define CONFIG_SYS_CS1_SIZE CONFIG_SYS_DOC_SIZE
#define CONFIG_SYS_CS1_CFG 0x00047800
#endif
#define CONFIG_SYS_CS_BURST 0x00000000
#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
#define CONFIG_SYS_RESET_ADDRESS 0xff000000
/*-----------------------------------------------------------------------
* USB stuff
*-----------------------------------------------------------------------
*/
#define CONFIG_USB_CLOCK 0x0001BBBB
#define CONFIG_USB_CONFIG 0x00005000
/*-----------------------------------------------------------------------
* IDE/ATA stuff Supports IDE harddisk
*-----------------------------------------------------------------------
*/
#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
#undef CONFIG_IDE_LED /* LED for ide not supported */
#undef CONFIG_IDE_RESET /* reset for ide supported */
#define CONFIG_IDE_PREINIT
#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drive per IDE bus */
#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
/* Offset for data I/O */
#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
/* Offset for normal register accesses */
#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
/* Offset for alternate registers */
#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
/* Interval between registers */
#define CONFIG_SYS_ATA_STRIDE 4
#endif /* __CONFIG_H */

777
include/configs/PPChameleonEVB.h
View File

@@ -1,777 +0,0 @@
/*
* (C) Copyright 2003-2005
* Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
*
* (C) Copyright 2003
* DAVE Srl
*
* http://www.dave-tech.it
* http://www.wawnet.biz
* mailto:info@wawnet.biz
*
* Credits: Stefan Roese, Wolfgang Denk
*
* SPDX-License-Identifier: GPL-2.0+
*/
/*
* board/config.h - configuration options, board specific
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_PPCHAMELEON_MODULE_BA 0 /* Basic Model */
#define CONFIG_PPCHAMELEON_MODULE_ME 1 /* Medium Model */
#define CONFIG_PPCHAMELEON_MODULE_HI 2 /* High-End Model */
#ifndef CONFIG_PPCHAMELEON_MODULE_MODEL
#define CONFIG_PPCHAMELEON_MODULE_MODEL CONFIG_PPCHAMELEON_MODULE_BA
#endif
/* Only one of the following two symbols must be defined (default is 25 MHz)
* CONFIG_PPCHAMELEON_CLK_25
* CONFIG_PPCHAMELEON_CLK_33
*/
#if (!defined(CONFIG_PPCHAMELEON_CLK_25) && !defined(CONFIG_PPCHAMELEON_CLK_33))
#define CONFIG_PPCHAMELEON_CLK_25
#endif
#if (defined(CONFIG_PPCHAMELEON_CLK_25) && defined(CONFIG_PPCHAMELEON_CLK_33))
#error "* Two external frequencies (SysClk) are defined! *"
#endif
#undef CONFIG_PPCHAMELEON_SMI712
/*
* Debug stuff
*/
#undef __DEBUG_START_FROM_SRAM__
#define __DISABLE_MACHINE_EXCEPTION__
#ifdef __DEBUG_START_FROM_SRAM__
#define CONFIG_SYS_DUMMY_FLASH_SIZE 1024*1024*4
#endif
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_405EP 1 /* This is a PPC405 CPU */
#define CONFIG_PPCHAMELEONEVB 1 /* ...on a PPChameleonEVB board */
#define CONFIG_SYS_TEXT_BASE 0xFFFB0000 /* Reserve 320 kB for Monitor */
#define CONFIG_SYS_LDSCRIPT "board/dave/PPChameleonEVB/u-boot.lds"
#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
#ifdef CONFIG_PPCHAMELEON_CLK_25
# define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */
#elif (defined (CONFIG_PPCHAMELEON_CLK_33))
# define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
#else
# error "* External frequency (SysClk) not defined! *"
#endif
#define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#undef CONFIG_BOOTARGS
/* Ethernet stuff */
#define CONFIG_ENV_OVERWRITE /* Let the user to change the Ethernet MAC addresses */
#define CONFIG_ETHADDR 00:50:c2:1e:af:fe
#define CONFIG_HAS_ETH1
#define CONFIG_ETH1ADDR 00:50:c2:1e:af:fd
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#undef CONFIG_EXT_PHY
#define CONFIG_PPC4xx_EMAC
#define CONFIG_MII 1 /* MII PHY management */
#ifndef CONFIG_EXT_PHY
#define CONFIG_PHY_ADDR 1 /* EMAC0 PHY address */
#define CONFIG_PHY1_ADDR 2 /* EMAC1 PHY address */
#else
#define CONFIG_PHY_ADDR 2 /* PHY address */
#endif
#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ
/*
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ELF
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_MII
#define CONFIG_CMD_NAND
#define CONFIG_CMD_NFS
#define CONFIG_CMD_PCI
#define CONFIG_CMD_SNTP
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_RTC_M41T11 1 /* uses a M41T00 RTC */
#define CONFIG_SYS_I2C_RTC_ADDR 0x68
#define CONFIG_SYS_M41T11_BASE_YEAR 1900
/*
* SDRAM configuration (please see cpu/ppc/sdram.[ch])
*/
#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
/* SDRAM timings used in datasheet */
#define CONFIG_SYS_SDRAM_CL 2
#define CONFIG_SYS_SDRAM_tRP 20
#define CONFIG_SYS_SDRAM_tRC 65
#define CONFIG_SYS_SDRAM_tRCD 20
#undef CONFIG_SYS_SDRAM_tRFC
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#define CONFIG_CONS_INDEX 1 /* Use UART0 */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
#define CONFIG_SYS_BASE_BAUD 691200
/* The following table includes the supported baudrates */
#define CONFIG_SYS_BAUDRATE_TABLE \
{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
57600, 115200, 230400, 460800, 921600 }
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
/*-----------------------------------------------------------------------
* NAND-FLASH stuff
*-----------------------------------------------------------------------
*/
/*
* nand device 1 on dave (PPChameleonEVB) needs more time,
* so we just introduce additional wait in nand_wait(),
* effectively for both devices.
*/
#define PPCHAMELON_NAND_TIMER_HACK
#define CONFIG_SYS_NAND0_BASE 0xFF400000
#define CONFIG_SYS_NAND1_BASE 0xFF000000
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE, CONFIG_SYS_NAND1_BASE }
#define NAND_BIG_DELAY_US 25
#define CONFIG_SYS_MAX_NAND_DEVICE 2 /* Max number of NAND devices */
#define CONFIG_SYS_NAND0_CE (0x80000000 >> 1) /* our CE is GPIO1 */
#define CONFIG_SYS_NAND0_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
#define CONFIG_SYS_NAND0_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
#define CONFIG_SYS_NAND0_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
#define CONFIG_SYS_NAND1_CE (0x80000000 >> 14) /* our CE is GPIO14 */
#define CONFIG_SYS_NAND1_RDY (0x80000000 >> 31) /* our RDY is GPIO31 */
#define CONFIG_SYS_NAND1_CLE (0x80000000 >> 15) /* our CLE is GPIO15 */
#define CONFIG_SYS_NAND1_ALE (0x80000000 >> 16) /* our ALE is GPIO16 */
#define MACRO_NAND_DISABLE_CE(nandptr) do \
{ \
switch((unsigned long)nandptr) \
{ \
case CONFIG_SYS_NAND0_BASE: \
out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND0_CE); \
break; \
case CONFIG_SYS_NAND1_BASE: \
out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND1_CE); \
break; \
} \
} while(0)
#define MACRO_NAND_ENABLE_CE(nandptr) do \
{ \
switch((unsigned long)nandptr) \
{ \
case CONFIG_SYS_NAND0_BASE: \
out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND0_CE); \
break; \
case CONFIG_SYS_NAND1_BASE: \
out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND1_CE); \
break; \
} \
} while(0)
#define MACRO_NAND_CTL_CLRALE(nandptr) do \
{ \
switch((unsigned long)nandptr) \
{ \
case CONFIG_SYS_NAND0_BASE: \
out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND0_ALE); \
break; \
case CONFIG_SYS_NAND1_BASE: \
out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND1_ALE); \
break; \
} \
} while(0)
#define MACRO_NAND_CTL_SETALE(nandptr) do \
{ \
switch((unsigned long)nandptr) \
{ \
case CONFIG_SYS_NAND0_BASE: \
out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND0_ALE); \
break; \
case CONFIG_SYS_NAND1_BASE: \
out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND1_ALE); \
break; \
} \
} while(0)
#define MACRO_NAND_CTL_CLRCLE(nandptr) do \
{ \
switch((unsigned long)nandptr) \
{ \
case CONFIG_SYS_NAND0_BASE: \
out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND0_CLE); \
break; \
case CONFIG_SYS_NAND1_BASE: \
out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND1_CLE); \
break; \
} \
} while(0)
#define MACRO_NAND_CTL_SETCLE(nandptr) do { \
switch((unsigned long)nandptr) { \
case CONFIG_SYS_NAND0_BASE: \
out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND0_CLE); \
break; \
case CONFIG_SYS_NAND1_BASE: \
out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND1_CLE); \
break; \
} \
} while(0)
/*-----------------------------------------------------------------------
* PCI stuff
*-----------------------------------------------------------------------
*/
#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
#define PCI_HOST_FORCE 1 /* configure as pci host */
#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
#define CONFIG_PCI /* include pci support */
#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
#undef CONFIG_PCI_PNP /* do pci plug-and-play */
/* resource configuration */
#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* PCI Vendor ID: IBM */
#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: --- */
#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
#define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */
#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
*/
#define CONFIG_SYS_SDRAM_BASE 0x00000000
/* Reserve 256 kB for Monitor */
/*
#define CONFIG_SYS_FLASH_BASE 0xFFFC0000
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
*/
/* Reserve 320 kB for Monitor */
#define CONFIG_SYS_FLASH_BASE 0xFFFB0000
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_MONITOR_LEN (320 * 1024)
#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
* FLASH organization
*/
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
/*
* The following defines are added for buggy IOP480 byte interface.
* All other boards should use the standard values (CPCI405 etc.)
*/
#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
/*-----------------------------------------------------------------------
* Environment Variable setup
*/
#ifdef ENVIRONMENT_IN_EEPROM
#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
#define CONFIG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */
#define CONFIG_ENV_SIZE 0x700 /* 2048-256 bytes may be used for env vars (total size of a CAT24WC16 is 2048 bytes)*/
#else /* DEFAULT: environment in flash, using redundand flash sectors */
#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
#define CONFIG_ENV_ADDR 0xFFFF8000 /* environment starts at the first small sector */
#define CONFIG_ENV_SECT_SIZE 0x2000 /* 8196 bytes may be used for env vars*/
#define CONFIG_ENV_ADDR_REDUND 0xFFFFA000
#define CONFIG_ENV_SIZE_REDUND 0x2000
#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
#endif /* ENVIRONMENT_IN_EEPROM */
#define CONFIG_SYS_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */
#define CONFIG_SYS_NVRAM_SIZE 242 /* NVRAM size */
/*-----------------------------------------------------------------------
* I2C EEPROM (CAT24WC16) for environment
*/
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_PPC4XX
#define CONFIG_SYS_I2C_PPC4XX_CH0
#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
/* mask of address bits that overflow into the "EEPROM chip address" */
/*#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07*/
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
/* 16 byte page write mode using*/
/* last 4 bits of the address */
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
/*
* Init Memory Controller:
*
* BR0/1 and OR0/1 (FLASH)
*/
#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
/*-----------------------------------------------------------------------
* External Bus Controller (EBC) Setup
*/
/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
#define CONFIG_SYS_EBC_PB0AP 0x92015480
#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
/* Memory Bank 1 (External SRAM) initialization */
/* Since this must replace NOR Flash, we use the same settings for CS0 */
#define CONFIG_SYS_EBC_PB1AP 0x92015480
#define CONFIG_SYS_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit */
/* Memory Bank 2 (Flash Bank 1, NAND-FLASH) initialization */
#define CONFIG_SYS_EBC_PB2AP 0x92015480
#define CONFIG_SYS_EBC_PB2CR 0xFF458000 /* BAS=0xFF4,BS=4MB,BU=R/W,BW=8bit */
/* Memory Bank 3 (Flash Bank 2, NAND-FLASH) initialization */
#define CONFIG_SYS_EBC_PB3AP 0x92015480
#define CONFIG_SYS_EBC_PB3CR 0xFF058000 /* BAS=0xFF0,BS=4MB,BU=R/W,BW=8bit */
#ifdef CONFIG_PPCHAMELEON_SMI712
/*
* Video console (graphic: SMI LynxEM)
*/
#define CONFIG_VIDEO
#define CONFIG_CFB_CONSOLE
#define CONFIG_VIDEO_SMI_LYNXEM
#define CONFIG_VIDEO_LOGO
/*#define CONFIG_VIDEO_BMP_LOGO*/
#define CONFIG_CONSOLE_EXTRA_INFO
#define CONFIG_VGA_AS_SINGLE_DEVICE
/* This is the base address (on 405EP-side) used to generate I/O accesses on PCI bus */
#define CONFIG_SYS_ISA_IO 0xE8000000
/* see also drivers/video/videomodes.c */
#define CONFIG_SYS_DEFAULT_VIDEO_MODE 0x303
#endif
/*-----------------------------------------------------------------------
* FPGA stuff
*/
/* FPGA internal regs */
#define CONFIG_SYS_FPGA_MODE 0x00
#define CONFIG_SYS_FPGA_STATUS 0x02
#define CONFIG_SYS_FPGA_TS 0x04
#define CONFIG_SYS_FPGA_TS_LOW 0x06
#define CONFIG_SYS_FPGA_TS_CAP0 0x10
#define CONFIG_SYS_FPGA_TS_CAP0_LOW 0x12
#define CONFIG_SYS_FPGA_TS_CAP1 0x14
#define CONFIG_SYS_FPGA_TS_CAP1_LOW 0x16
#define CONFIG_SYS_FPGA_TS_CAP2 0x18
#define CONFIG_SYS_FPGA_TS_CAP2_LOW 0x1a
#define CONFIG_SYS_FPGA_TS_CAP3 0x1c
#define CONFIG_SYS_FPGA_TS_CAP3_LOW 0x1e
/* FPGA Mode Reg */
#define CONFIG_SYS_FPGA_MODE_CF_RESET 0x0001
#define CONFIG_SYS_FPGA_MODE_TS_IRQ_ENABLE 0x0100
#define CONFIG_SYS_FPGA_MODE_TS_IRQ_CLEAR 0x1000
#define CONFIG_SYS_FPGA_MODE_TS_CLEAR 0x2000
/* FPGA Status Reg */
#define CONFIG_SYS_FPGA_STATUS_DIP0 0x0001
#define CONFIG_SYS_FPGA_STATUS_DIP1 0x0002
#define CONFIG_SYS_FPGA_STATUS_DIP2 0x0004
#define CONFIG_SYS_FPGA_STATUS_FLASH 0x0008
#define CONFIG_SYS_FPGA_STATUS_TS_IRQ 0x1000
#define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
#define CONFIG_SYS_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/
/* FPGA program pin configuration */
#define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
#define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
#define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
#define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */
#define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in data cache)
*/
/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
#define CONFIG_SYS_TEMP_STACK_OCM 1
/* On Chip Memory location */
#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
* Definitions for GPIO setup (PPC405EP specific)
*
* GPIO0[0] - External Bus Controller BLAST output
* GPIO0[1-9] - Instruction trace outputs -> GPIO
* GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
* GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
* GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
* GPIO0[24-27] - UART0 control signal inputs/outputs
* GPIO0[28-29] - UART1 data signal input/output
* GPIO0[30] - EMAC0 input
* GPIO0[31] - EMAC1 reject packet as output
*/
#define CONFIG_SYS_GPIO0_OSRL 0x40000550
#define CONFIG_SYS_GPIO0_OSRH 0x00000110
#define CONFIG_SYS_GPIO0_ISR1L 0x00000000
/*#define CONFIG_SYS_GPIO0_ISR1H 0x15555445*/
#define CONFIG_SYS_GPIO0_ISR1H 0x15555444
#define CONFIG_SYS_GPIO0_TSRL 0x00000000
#define CONFIG_SYS_GPIO0_TSRH 0x00000000
#define CONFIG_SYS_GPIO0_TCR 0xF7FF8014
#define CONFIG_NO_SERIAL_EEPROM
/*--------------------------------------------------------------------*/
#ifdef CONFIG_NO_SERIAL_EEPROM
/*
!-----------------------------------------------------------------------
! Defines for entry options.
! Note: Because the 405EP SDRAM controller does not support ECC, ECC DIMMs that
! are plugged in the board will be utilized as non-ECC DIMMs.
!-----------------------------------------------------------------------
*/
#undef AUTO_MEMORY_CONFIG
#define DIMM_READ_ADDR 0xAB
#define DIMM_WRITE_ADDR 0xAA
/* Defines for CPC0_PLLMR1 Register fields */
#define PLL_ACTIVE 0x80000000
#define CPC0_PLLMR1_SSCS 0x80000000
#define PLL_RESET 0x40000000
#define CPC0_PLLMR1_PLLR 0x40000000
/* Feedback multiplier */
#define PLL_FBKDIV 0x00F00000
#define CPC0_PLLMR1_FBDV 0x00F00000
#define PLL_FBKDIV_16 0x00000000
#define PLL_FBKDIV_1 0x00100000
#define PLL_FBKDIV_2 0x00200000
#define PLL_FBKDIV_3 0x00300000
#define PLL_FBKDIV_4 0x00400000
#define PLL_FBKDIV_5 0x00500000
#define PLL_FBKDIV_6 0x00600000
#define PLL_FBKDIV_7 0x00700000
#define PLL_FBKDIV_8 0x00800000
#define PLL_FBKDIV_9 0x00900000
#define PLL_FBKDIV_10 0x00A00000
#define PLL_FBKDIV_11 0x00B00000
#define PLL_FBKDIV_12 0x00C00000
#define PLL_FBKDIV_13 0x00D00000
#define PLL_FBKDIV_14 0x00E00000
#define PLL_FBKDIV_15 0x00F00000
/* Forward A divisor */
#define PLL_FWDDIVA 0x00070000
#define CPC0_PLLMR1_FWDVA 0x00070000
#define PLL_FWDDIVA_8 0x00000000
#define PLL_FWDDIVA_7 0x00010000
#define PLL_FWDDIVA_6 0x00020000
#define PLL_FWDDIVA_5 0x00030000
#define PLL_FWDDIVA_4 0x00040000
#define PLL_FWDDIVA_3 0x00050000
#define PLL_FWDDIVA_2 0x00060000
#define PLL_FWDDIVA_1 0x00070000
/* Forward B divisor */
#define PLL_FWDDIVB 0x00007000
#define CPC0_PLLMR1_FWDVB 0x00007000
#define PLL_FWDDIVB_8 0x00000000
#define PLL_FWDDIVB_7 0x00001000
#define PLL_FWDDIVB_6 0x00002000
#define PLL_FWDDIVB_5 0x00003000
#define PLL_FWDDIVB_4 0x00004000
#define PLL_FWDDIVB_3 0x00005000
#define PLL_FWDDIVB_2 0x00006000
#define PLL_FWDDIVB_1 0x00007000
/* PLL tune bits */
#define PLL_TUNE_MASK 0x000003FF
#define PLL_TUNE_2_M_3 0x00000133 /* 2 <= M <= 3 */
#define PLL_TUNE_4_M_6 0x00000134 /* 3 < M <= 6 */
#define PLL_TUNE_7_M_10 0x00000138 /* 6 < M <= 10 */
#define PLL_TUNE_11_M_14 0x0000013C /* 10 < M <= 14 */
#define PLL_TUNE_15_M_40 0x0000023E /* 14 < M <= 40 */
#define PLL_TUNE_VCO_LOW 0x00000000 /* 500MHz <= VCO <= 800MHz */
#define PLL_TUNE_VCO_HI 0x00000080 /* 800MHz < VCO <= 1000MHz */
/* Defines for CPC0_PLLMR0 Register fields */
/* CPU divisor */
#define PLL_CPUDIV 0x00300000
#define CPC0_PLLMR0_CCDV 0x00300000
#define PLL_CPUDIV_1 0x00000000
#define PLL_CPUDIV_2 0x00100000
#define PLL_CPUDIV_3 0x00200000
#define PLL_CPUDIV_4 0x00300000
/* PLB divisor */
#define PLL_PLBDIV 0x00030000
#define CPC0_PLLMR0_CBDV 0x00030000
#define PLL_PLBDIV_1 0x00000000
#define PLL_PLBDIV_2 0x00010000
#define PLL_PLBDIV_3 0x00020000
#define PLL_PLBDIV_4 0x00030000
/* OPB divisor */
#define PLL_OPBDIV 0x00003000
#define CPC0_PLLMR0_OPDV 0x00003000
#define PLL_OPBDIV_1 0x00000000
#define PLL_OPBDIV_2 0x00001000
#define PLL_OPBDIV_3 0x00002000
#define PLL_OPBDIV_4 0x00003000
/* EBC divisor */
#define PLL_EXTBUSDIV 0x00000300
#define CPC0_PLLMR0_EPDV 0x00000300
#define PLL_EXTBUSDIV_2 0x00000000
#define PLL_EXTBUSDIV_3 0x00000100
#define PLL_EXTBUSDIV_4 0x00000200
#define PLL_EXTBUSDIV_5 0x00000300
/* MAL divisor */
#define PLL_MALDIV 0x00000030
#define CPC0_PLLMR0_MPDV 0x00000030
#define PLL_MALDIV_1 0x00000000
#define PLL_MALDIV_2 0x00000010
#define PLL_MALDIV_3 0x00000020
#define PLL_MALDIV_4 0x00000030
/* PCI divisor */
#define PLL_PCIDIV 0x00000003
#define CPC0_PLLMR0_PPFD 0x00000003
#define PLL_PCIDIV_1 0x00000000
#define PLL_PCIDIV_2 0x00000001
#define PLL_PCIDIV_3 0x00000002
#define PLL_PCIDIV_4 0x00000003
#ifdef CONFIG_PPCHAMELEON_CLK_25
/* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 25.0 MHz input clock to the 405EP) */
#define PPCHAMELEON_PLLMR0_133_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \
PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
PLL_MALDIV_1 | PLL_PCIDIV_4)
#define PPCHAMELEON_PLLMR1_133_133_33_66_33 (PLL_FBKDIV_8 | \
PLL_FWDDIVA_6 | PLL_FWDDIVB_4 | \
PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
#define PPCHAMELEON_PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
PLL_MALDIV_1 | PLL_PCIDIV_4)
#define PPCHAMELEON_PLLMR1_200_100_50_33 (PLL_FBKDIV_8 | \
PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \
PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
#define PPCHAMELEON_PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
PLL_MALDIV_1 | PLL_PCIDIV_4)
#define PPCHAMELEON_PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8 | \
PLL_FWDDIVA_3 | PLL_FWDDIVB_4 | \
PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
#define PPCHAMELEON_PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
PLL_MALDIV_1 | PLL_PCIDIV_2)
#define PPCHAMELEON_PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10 | \
PLL_FWDDIVA_3 | PLL_FWDDIVB_4 | \
PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
#elif (defined (CONFIG_PPCHAMELEON_CLK_33))
/* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 33.3MHz input clock to the 405EP) */
#define PPCHAMELEON_PLLMR0_133_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \
PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
PLL_MALDIV_1 | PLL_PCIDIV_4)
#define PPCHAMELEON_PLLMR1_133_133_33_66_33 (PLL_FBKDIV_4 | \
PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \
PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
#define PPCHAMELEON_PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
PLL_MALDIV_1 | PLL_PCIDIV_4)
#define PPCHAMELEON_PLLMR1_200_100_50_33 (PLL_FBKDIV_6 | \
PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \
PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
#define PPCHAMELEON_PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
PLL_MALDIV_1 | PLL_PCIDIV_4)
#define PPCHAMELEON_PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8 | \
PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
#define PPCHAMELEON_PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
PLL_MALDIV_1 | PLL_PCIDIV_2)
#define PPCHAMELEON_PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10 | \
PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
#else
#error "* External frequency (SysClk) not defined! *"
#endif
#if (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_HI)
/* Model HI */
#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_333_111_37_55_55
#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_333_111_37_55_55
#define CONFIG_SYS_OPB_FREQ 55555555
/* Model ME */
#elif (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_ME)
#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_266_133_33_66_33
#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_266_133_33_66_33
#define CONFIG_SYS_OPB_FREQ 66666666
#else
/* Model BA (default) */
#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_133_133_33_66_33
#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_133_133_33_66_33
#define CONFIG_SYS_OPB_FREQ 66666666
#endif
#endif /* CONFIG_NO_SERIAL_EEPROM */
#define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */
#define NAND_CACHE_PAGES 16 /* size of nand cache in 512 bytes pages */
/*
* JFFS2 partitions
*/
/* No command line, one static partition */
#undef CONFIG_CMD_MTDPARTS
#define CONFIG_JFFS2_DEV "nand0"
#define CONFIG_JFFS2_PART_SIZE 0x00400000
#define CONFIG_JFFS2_PART_OFFSET 0x00000000
/* mtdparts command line support */
/*
#define CONFIG_CMD_MTDPARTS
#define MTDIDS_DEFAULT "nor0=PPChameleon-0,nand0=ppchameleonevb-nand"
*/
/* 256 kB U-boot image */
/*
#define MTDPARTS_DEFAULT "mtdparts=PPChameleon-0:1m(kernel1),1m(kernel2)," \
"1792k(user),256k(u-boot);" \
"ppchameleonevb-nand:-(nand)"
*/
/* 320 kB U-boot image */
/*
#define MTDPARTS_DEFAULT "mtdparts=PPChameleon-0:1m(kernel1),1m(kernel2)," \
"1728k(user),320k(u-boot);" \
"ppchameleonevb-nand:-(nand)"
*/
#endif /* __CONFIG_H */

3
include/configs/T102xQDS.h
View File

@@ -35,7 +35,10 @@
#define CONFIG_ENV_OVERWRITE
#define CONFIG_DEEP_SLEEP
#if defined(CONFIG_DEEP_SLEEP)
#define CONFIG_SILENT_CONSOLE
#define CONFIG_BOARD_EARLY_INIT_F
#endif
#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xqds/t1024_pbi.cfg

23
include/configs/T102xRDB.h
View File

@@ -36,7 +36,10 @@
/* support deep sleep */
#define CONFIG_DEEP_SLEEP
#if defined(CONFIG_DEEP_SLEEP)
#define CONFIG_SILENT_CONSOLE
#define CONFIG_BOARD_EARLY_INIT_F
#endif
#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg
@@ -51,7 +54,7 @@
#define CONFIG_SPL_I2C_SUPPORT
#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_SYS_TEXT_BASE 0x00201000
#define CONFIG_SYS_TEXT_BASE 0x30001000
#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
#define CONFIG_SPL_PAD_TO 0x40000
#define CONFIG_SPL_MAX_SIZE 0x28000
@@ -67,21 +70,21 @@
#ifdef CONFIG_NAND
#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
#define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000
#define CONFIG_SYS_NAND_U_BOOT_START 0x30000000
#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
#define CONFIG_SPL_NAND_BOOT
#endif
#ifdef CONFIG_SPIFLASH
#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
#define CONFIG_SPL_SPI_SUPPORT
#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SPL_SPI_FLASH_MINIMAL
#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000)
#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000)
#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
#ifndef CONFIG_SPL_BUILD
@@ -91,12 +94,12 @@
#endif
#ifdef CONFIG_SDCARD
#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SPL_MMC_MINIMAL
#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
#define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000)
#define CONFIG_SYS_MMC_U_BOOT_START (0x00200000)
#define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000)
#define CONFIG_SYS_MMC_U_BOOT_START (0x30000000)
#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
#ifndef CONFIG_SPL_BUILD
@@ -759,8 +762,10 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_FMAN_ENET
#define CONFIG_PHYLIB_10G
#define CONFIG_PHY_REALTEK
#define CONFIG_PHY_AQUANTIA
#define RGMII_PHY1_ADDR 0x2
#define RGMII_PHY2_ADDR 0x6
#define SGMII_PHY1_ADDR 0x2
#define FM1_10GEC1_PHY_ADDR 0x1
#endif

9
include/configs/T1040QDS.h
View File

@@ -47,7 +47,10 @@
/* support deep sleep */
#define CONFIG_DEEP_SLEEP
#if defined(CONFIG_DEEP_SLEEP)
#define CONFIG_SILENT_CONSOLE
#define CONFIG_BOARD_EARLY_INIT_F
#endif
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0xeff40000
@@ -689,6 +692,12 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
#endif
/* Enable VSC9953 L2 Switch driver */
#define CONFIG_VSC9953
#define CONFIG_VSC9953_CMD
#define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x14
#define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x18
/*
* Dynamic MTD Partition support with mtdparts
*/

8
include/configs/T104xRDB.h
View File

@@ -726,6 +726,14 @@
#define CONFIG_SYS_RGMII1_PHY_ADDR 0x01
#define CONFIG_SYS_RGMII2_PHY_ADDR 0x02
/* Enable VSC9953 L2 Switch driver on T1040 SoC */
#ifdef CONFIG_T1040RDB
#define CONFIG_VSC9953
#define CONFIG_VSC9953_CMD
#define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x04
#define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x08
#endif
#define CONFIG_MII /* MII PHY management */
#define CONFIG_ETHPRIME "FM1@DTSEC4"
#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */

386
include/configs/Total5200.h
View File

@@ -1,386 +0,0 @@
/*
* (C) Copyright 2003-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2004
* Mark Jonas, Freescale Semiconductor, mark.jonas@freescale.com.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* Check valid setting of revision define.
* Total5100 and Total5200 Rev.1 are identical except for the processor.
*/
#if (CONFIG_TOTAL5200_REV!=1 && CONFIG_TOTAL5200_REV!=2)
#error CONFIG_TOTAL5200_REV must be 1 or 2
#endif
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_MPC5200 1 /* This is a MPC5200 CPU */
#define CONFIG_TOTAL5200 1 /* ... on Total5200 board */
/*
* Valid values for CONFIG_SYS_TEXT_BASE are:
* 0xFFF00000 boot high (standard configuration)
* 0xFE000000 boot low
* 0x00100000 boot from RAM (for testing only)
*/
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0xFFF00000
#endif
#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/*
* Serial console configuration
*/
#define CONFIG_PSC_CONSOLE 3 /* console is on PSC3 */
#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
/*
* Video console
*/
#define CONFIG_VIDEO
#define CONFIG_VIDEO_SED13806
#define CONFIG_VIDEO_SED13806_16BPP
#define CONFIG_CFB_CONSOLE
#define CONFIG_VIDEO_LOGO
/* #define CONFIG_VIDEO_BMP_LOGO */
#define CONFIG_CONSOLE_EXTRA_INFO
#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_VIDEO_SW_CURSOR
#define CONFIG_SPLASH_SCREEN
/*
* PCI Mapping:
* 0x40000000 - 0x4fffffff - PCI Memory
* 0x50000000 - 0x50ffffff - PCI IO Space
*/
#define CONFIG_PCI 1
#define CONFIG_PCI_PNP 1
#define CONFIG_PCI_SCAN_SHOW 1
#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
#define CONFIG_PCI_MEM_BUS 0x40000000
#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
#define CONFIG_PCI_MEM_SIZE 0x10000000
#define CONFIG_PCI_IO_BUS 0x50000000
#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
#define CONFIG_PCI_IO_SIZE 0x01000000
#define CONFIG_MII 1
#define CONFIG_EEPRO100 1
#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
#define CONFIG_NS8382X 1
/* Partitions */
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
/* USB */
#define CONFIG_USB_OHCI
#define CONFIG_USB_STORAGE
/*
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_PCI
#define CONFIG_CMD_BMP
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_FAT
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IDE
#define CONFIG_CMD_PING
#define CONFIG_CMD_USB
#if (CONFIG_SYS_TEXT_BASE == 0xFE000000) /* Boot low */
# define CONFIG_SYS_LOWBOOT 1
#endif
/*
* Autobooting
*/
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#define CONFIG_PREBOOT \
"setenv stdout serial;setenv stderr serial;" \
"echo;" \
"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
"addip=setenv bootargs ${bootargs} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
":${hostname}:${netdev}:off panic=1\0" \
"flash_nfs=run nfsargs addip;" \
"bootm ${kernel_addr}\0" \
"flash_self=run ramargs addip;" \
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_82xx\0" \
"bootfile=/tftpboot/MPC5200/uImage\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
/*
* IPB Bus clocking configuration.
*/
#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
/*
* I2C configuration
*/
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
#define CONFIG_SYS_I2C_MODULE 1 /* Select I2C module #1 or #2 */
#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
#define CONFIG_SYS_I2C_SLAVE 0x7F
/*
* EEPROM configuration
*/
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70
/*
* Flash configuration
*/
#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
#if CONFIG_TOTAL5200_REV==2
# define CONFIG_SYS_MAX_FLASH_BANKS 3 /* max num of flash banks */
# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS5_START, CONFIG_SYS_CS4_START, CONFIG_SYS_BOOTCS_START }
#else
# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_BOOTCS_START }
#endif
#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */
#if CONFIG_TOTAL5200_REV==1
# define CONFIG_SYS_FLASH_BASE 0xFE000000
# define CONFIG_SYS_FLASH_SIZE 0x02000000
#elif CONFIG_TOTAL5200_REV==2
# define CONFIG_SYS_FLASH_BASE 0xFA000000
# define CONFIG_SYS_FLASH_SIZE 0x06000000
#endif /* CONFIG_TOTAL5200_REV */
#if defined(CONFIG_SYS_LOWBOOT)
# define CONFIG_ENV_ADDR 0xFE040000
#else /* CONFIG_SYS_LOWBOOT */
# define CONFIG_ENV_ADDR 0xFFF40000
#endif /* CONFIG_SYS_LOWBOOT */
/*
* Environment settings
*/
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_SIZE 0x40000
#define CONFIG_ENV_SECT_SIZE 0x40000
#define CONFIG_ENV_OVERWRITE 1
/*
* Memory map
*/
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
#define CONFIG_SYS_MBAR 0xF0000000 /* 64 kB */
#define CONFIG_SYS_FPGA_BASE 0xF0010000 /* 64 kB */
#define CONFIG_SYS_CPLD_BASE 0xF0020000 /* 64 kB */
#define CONFIG_SYS_LCD_BASE 0xF1000000 /* 4096 kB */
/* Use SRAM until RAM will be available */
#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
# define CONFIG_SYS_RAMBOOT 1
#endif
#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*
* Ethernet configuration
*/
#define CONFIG_MPC5xxx_FEC 1
#define CONFIG_MPC5xxx_FEC_SEVENWIRE
/* dummy, 7-wire FEC does not have phy address */
#define CONFIG_PHY_ADDR 0x00
/*
* GPIO configuration
*
* CS1: SDRAM CS1 disabled, gpio_wkup_6 enabled 0
* Reserved 0
* ALTs: CAN1/2 on PSC2, SPI on PSC3 00
* CS7: Interrupt GPIO on PSC3_5 0
* CS8: Interrupt GPIO on PSC3_4 0
* ATA: reset default, changed in ATA driver 00
* IR_USB_CLK: IrDA/USB 48MHz clock gen. int., pin is GPIO 0
* IRDA: reset default, changed in IrDA driver 000
* ETHER: reset default, changed in Ethernet driver 0000
* PCI_DIS: reset default, changed in PCI driver 0
* USB_SE: reset default, changed in USB driver 0
* USB: reset default, changed in USB driver 00
* PSC3: SPI and UART functionality without CD 1100
* Reserved 0
* PSC2: CAN1/2 001
* Reserved 0
* PSC1: reset default, changed in AC'97 driver 000
*
*/
#define CONFIG_SYS_GPS_PORT_CONFIG 0x00000C10
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
#if defined(CONFIG_CMD_KGDB)
# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
/*
* Various low-level settings
*/
#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
#define CONFIG_SYS_HID0_FINAL HID0_ICE
#if CONFIG_TOTAL5200_REV==1
# define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
# define CONFIG_SYS_BOOTCS_SIZE 0x02000000 /* 32 MB */
# define CONFIG_SYS_BOOTCS_CFG 0x0004DF00 /* 4WS, MX, AL, CE, AS_25, DS_32 */
# define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
# define CONFIG_SYS_CS0_SIZE 0x02000000 /* 32 MB */
#else
# define CONFIG_SYS_BOOTCS_START (CONFIG_SYS_CS4_START + CONFIG_SYS_CS4_SIZE)
# define CONFIG_SYS_BOOTCS_SIZE 0x02000000 /* 32 MB */
# define CONFIG_SYS_BOOTCS_CFG 0x0004DF00 /* 4WS, MX, AL, CE, AS_25, DS_32 */
# define CONFIG_SYS_CS4_START (CONFIG_SYS_CS5_START + CONFIG_SYS_CS5_SIZE)
# define CONFIG_SYS_CS4_SIZE 0x02000000 /* 32 MB */
# define CONFIG_SYS_CS4_CFG 0x0004DF00 /* 4WS, MX, AL, CE, AS_25, DS_32 */
# define CONFIG_SYS_CS5_START CONFIG_SYS_FLASH_BASE
# define CONFIG_SYS_CS5_SIZE 0x02000000 /* 32 MB */
# define CONFIG_SYS_CS5_CFG 0x0004DF00 /* 4WS, MX, AL, CE, AS_25, DS_32 */
#endif
#define CONFIG_SYS_CS1_START CONFIG_SYS_FPGA_BASE
#define CONFIG_SYS_CS1_SIZE 0x00010000 /* 64 kB */
#define CONFIG_SYS_CS1_CFG 0x0019FF00 /* 25WS, MX, AL, AA, CE, AS_25, DS_32 */
#define CONFIG_SYS_CS2_START CONFIG_SYS_LCD_BASE
#define CONFIG_SYS_CS2_SIZE 0x00400000 /* 4096 kB */
#define CONFIG_SYS_CS2_CFG 0x0032FD0C /* 50WS, MX, AL, AA, CE, AS_25, DS_16, endian swapping */
#if CONFIG_TOTAL5200_REV==1
# define CONFIG_SYS_CS3_START CONFIG_SYS_CPLD_BASE
# define CONFIG_SYS_CS3_SIZE 0x00010000 /* 64 kB */
# define CONFIG_SYS_CS3_CFG 0x000ADF00 /* 10WS, MX, AL, CE, AS_25, DS_32 */
#else
# define CONFIG_SYS_CS3_START CONFIG_SYS_CPLD_BASE
# define CONFIG_SYS_CS3_SIZE 0x00010000 /* 64 kB */
# define CONFIG_SYS_CS3_CFG 0x000AD800 /* 10WS, MX, AL, CE, AS_24, DS_8 */
#endif
#define CONFIG_SYS_CS_BURST 0x00000000
#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
/*-----------------------------------------------------------------------
* USB stuff
*-----------------------------------------------------------------------
*/
#define CONFIG_USB_CLOCK 0x0001BBBB
#define CONFIG_USB_CONFIG 0x00001000
/*-----------------------------------------------------------------------
* IDE/ATA stuff Supports IDE harddisk
*-----------------------------------------------------------------------
*/
#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
#undef CONFIG_IDE_LED /* LED for ide not supported */
#define CONFIG_IDE_RESET /* reset for ide supported */
#define CONFIG_IDE_PREINIT
#define CONFIG_SYS_ATA_CS_ON_I2C2
#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
/* Offset for data I/O */
#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
/* Offset for normal register accesses */
#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
/* Offset for alternate registers */
#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
/* Interval between registers */
#define CONFIG_SYS_ATA_STRIDE 4
#endif /* __CONFIG_H */

7
include/configs/am335x_evm.h
View File

@@ -19,13 +19,11 @@
#include <configs/ti_am335x_common.h>
#ifndef CONFIG_SPL_BUILD
#ifndef CONFIG_FIT
# define CONFIG_FIT
#endif
# define CONFIG_TIMESTAMP
# define CONFIG_LZO
# ifdef CONFIG_ENABLE_VBOOT
# define CONFIG_FIT_SIGNATURE
# define CONFIG_RSA
# endif
#endif
#define CONFIG_SYS_BOOTM_LEN (16 << 20)
@@ -239,6 +237,7 @@
#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
/* NAND: driver related configs */
#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_NAND_OMAP_GPMC_PREFETCH
#define CONFIG_NAND_OMAP_ELM
#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \

91
include/configs/arcangel4-be.h
View File

@@ -1,91 +0,0 @@
/*
* Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _CONFIG_ARCANGEL4_H_
#define _CONFIG_ARCANGEL4_H_
/*
* CPU configuration
*/
#define CONFIG_SYS_BIG_ENDIAN
#define CONFIG_ARC700
#define CONFIG_ARC_MMU_VER 3
#define CONFIG_SYS_CACHELINE_SIZE 64
#define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ
/*
* Board configuration
*/
#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is in RAM already */
#define CONFIG_ARCH_EARLY_INIT_R
/*
* Memory configuration
*/
#define CONFIG_SYS_TEXT_BASE 0x81000000
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_SYS_SDRAM_SIZE 0x10000000 /* 256 Mb */
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_MALLOC_LEN 0x200000 /* 2 MB */
#define CONFIG_SYS_BOOTM_LEN 0x2000000 /* 32 MB */
#define CONFIG_SYS_LOAD_ADDR 0x82000000
#define CONFIG_SYS_NO_FLASH
/*
* UART configuration
*
*/
#define CONFIG_ARC_SERIAL
#define CONFIG_ARC_UART_BASE 0xC0FC1000
#define CONFIG_BAUDRATE 115200
/*
* Command line configuration
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_ELF
#define CONFIG_OF_LIBFDT
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_MAXARGS 16
/*
* Environment settings
*/
#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_ENV_SIZE 0x00200 /* 512 bytes */
#define CONFIG_ENV_OFFSET 0
/*
* Environment configuration
*/
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTFILE "uImage"
#define CONFIG_BOOTARGS "console=ttyARC0,115200n8"
#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
/*
* Console configuration
*/
#define CONFIG_SYS_LONGHELP
#define CONFIG_SYS_PROMPT "arcangel4# "
#define CONFIG_SYS_CBSIZE 256
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
#endif /* _CONFIG_ARCANGEL4_H_ */

12
include/configs/arcangel4.h
View File

@@ -10,23 +10,11 @@
/*
* CPU configuration
*/
#define CONFIG_ARC700
#define CONFIG_ARC_MMU_VER 3
#define CONFIG_SYS_CACHELINE_SIZE 64
#define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ
/*
* Board configuration
*/
#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is in RAM already */
#define CONFIG_ARCH_EARLY_INIT_R
/*
* Memory configuration
*/
#define CONFIG_SYS_TEXT_BASE 0x81000000
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000

2
include/configs/arndale.h
View File

@@ -51,8 +51,6 @@
/* PMIC */
#define CONFIG_PMIC
#define CONFIG_POWER_I2C
#define CONFIG_POWER_MAX77686
#define CONFIG_PREBOOT

6
include/configs/at91sam9260ek.h
View File

@@ -90,7 +90,6 @@
#define CONFIG_CMD_PING 1
#define CONFIG_CMD_DHCP 1
#define CONFIG_CMD_NAND 1
#define CONFIG_CMD_MMC
#define CONFIG_CMD_FAT
#define CONFIG_CMD_USB 1
@@ -133,14 +132,17 @@
# define CONFIG_MACH_TYPE MACH_TYPE_AT91SAM9260EK
#endif
/* DataFlash */
#ifndef CONFIG_AT91SAM9G20EK_2MMC
/* DataFlash */
#define CONFIG_ATMEL_DATAFLASH_SPI
#define CONFIG_HAS_DATAFLASH 1
#define CONFIG_SYS_MAX_DATAFLASH_BANKS 2
#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */
#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1 0xD0000000 /* CS1 */
#define AT91_SPI_CLK 15000000
#else
/* Enable MMC. The MCCK is conflicted with DataFlash */
#define CONFIG_CMD_MMC
#endif
#ifdef CONFIG_AT91SAM9G20EK

11
include/configs/at91sam9x5ek.h
View File

@@ -203,11 +203,12 @@
"bootm 0x22000000"
#else /* CONFIG_SYS_USE_MMC */
/* bootstrap + u-boot + env + linux in mmc */
#define CONFIG_ENV_IS_IN_MMC
/* For FAT system, most cases it should be in the reserved sector */
#define CONFIG_ENV_OFFSET 0x2000
#define CONFIG_ENV_SIZE 0x1000
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_ENV_IS_IN_FAT
#define CONFIG_FAT_WRITE
#define FAT_ENV_INTERFACE "mmc"
#define FAT_ENV_FILE "uboot.env"
#define FAT_ENV_DEVICE_AND_PART "0"
#define CONFIG_ENV_SIZE 0x4000
#endif
#ifdef CONFIG_SYS_USE_MMC

15
include/configs/axs101.h
View File

@@ -10,22 +10,8 @@
/*
* CPU configuration
*/
#define CONFIG_ARC700
#define CONFIG_ARC_MMU_VER 3
#define CONFIG_SYS_CACHELINE_SIZE 32
#define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ
/* NAND controller DMA doesn't work correctly with D$ enabled */
#define CONFIG_SYS_DCACHE_OFF
/*
* Board configuration
*/
#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is in RAM already */
#define CONFIG_ARCH_EARLY_INIT_R
#define ARC_FPGA_PERIPHERAL_BASE 0xE0000000
#define ARC_APB_PERIPHERAL_BASE 0xF0000000
#define ARC_DWMMC_BASE (ARC_FPGA_PERIPHERAL_BASE + 0x15000)
@@ -34,7 +20,6 @@
/*
* Memory configuration
*/
#define CONFIG_SYS_TEXT_BASE 0x81000000
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000

2
include/configs/bct-brettl2.h
View File

@@ -97,7 +97,7 @@
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_OFFSET 0x4000
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_SECT_SIZE 0x10000
#define CONFIG_ENV_SECT_SIZE 0x12000
#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
#define ENV_IS_EMBEDDED

8
include/configs/chromebook_link.h
View File

@@ -20,6 +20,7 @@
#define CONFIG_DCACHE_RAM_MRC_VAR_SIZE 0x4000
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_MISC_INIT_R
#define CONFIG_NR_DRAM_BANKS 8
#define CONFIG_X86_MRC_ADDR 0xfffa0000
@@ -63,6 +64,13 @@
#define CONFIG_CMD_CROS_EC
#define CONFIG_ARCH_EARLY_INIT_R
#undef CONFIG_ENV_IS_NOWHERE
#undef CONFIG_ENV_SIZE
#define CONFIG_ENV_SIZE 0x1000
#define CONFIG_ENV_SECT_SIZE 0x1000
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_OFFSET 0x003f8000
#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,vga,serial\0" \
"stdout=vga,serial\0" \
"stderr=vga,serial\0"

4
include/configs/corvus.h
View File

@@ -18,6 +18,7 @@
#define MACH_TYPE_CORVUS 2066
#define CONFIG_MACH_TYPE MACH_TYPE_CORVUS
#define CONFIG_SYS_GENERIC_BOARD
/*
* Warning: changing CONFIG_SYS_TEXT_BASE requires
@@ -106,6 +107,7 @@
/* our CLE is AD22 */
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC8
#endif
/* Ethernet */
@@ -171,7 +173,6 @@
#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_GPIO_SUPPORT
#define CONFIG_SYS_NAND_ENABLE_PIN_SPL (2*32 + 14)
#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_BASE
@@ -184,7 +185,6 @@
#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_SIZE (256*1024*1024)
#define CONFIG_SYS_NAND_PAGE_SIZE 2048
#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \

390
include/configs/cpci5200.h
View File

@@ -1,390 +0,0 @@
/*
* (C) Copyright 2003-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
/*************************************************************************
* (c) 2005 esd gmbh Hannover
*
*
* from IceCube.h file
* by Reinhard Arlt reinhard.arlt@esd-electronics.com
*
*************************************************************************/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
#define CONFIG_ICECUBE 1 /* ... on IceCube board */
#define CONFIG_CPCI5200 1 /* ... on CPCI5200 board */
#define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0xFFF00000 /* Standard: boot high */
#endif
#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/*
* Serial console configuration
*/
#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
#define CONFIG_BAUDRATE 9600 /* ... at 115200 bps */
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
/*
* PCI Mapping:
* 0x40000000 - 0x4fffffff - PCI Memory
* 0x50000000 - 0x50ffffff - PCI IO Space
*/
#if 1
#define CONFIG_PCI 1
#if 1
#define CONFIG_PCI_PNP 1
#endif
#define CONFIG_PCI_SCAN_SHOW 1
#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
#define CONFIG_PCI_MEM_BUS 0x40000000
#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
#define CONFIG_PCI_MEM_SIZE 0x10000000
#define CONFIG_PCI_IO_BUS 0x50000000
#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
#define CONFIG_PCI_IO_SIZE 0x01000000
#endif
#define CONFIG_MII
#if 0 /* test-only !!! */
#define CONFIG_EEPRO100 1
#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
#define CONFIG_NS8382X 1
#endif
/* Partitions */
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
/* USB */
#if 0
#define CONFIG_USB_OHCI
#define CONFIG_USB_STORAGE
#endif
/*
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
#endif
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_FAT
#define CONFIG_CMD_IDE
#define CONFIG_CMD_I2C
#define CONFIG_CMD_BSP
#define CONFIG_CMD_ELF
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_DATE
#if (CONFIG_SYS_TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
# define CONFIG_SYS_LOWBOOT 1
# define CONFIG_SYS_LOWBOOT16 1
#endif
#if (CONFIG_SYS_TEXT_BASE == 0xFF800000) /* Boot low with 8 MB Flash */
# define CONFIG_SYS_LOWBOOT 1
# define CONFIG_SYS_LOWBOOT08 1
#endif
/*
* Autobooting
*/
#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
#define CONFIG_PREBOOT "echo;" \
"echo Welcome to esd CPU CPCI/5200;" \
"echo"
#undef CONFIG_BOOTARGS
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"flash_vxworks0=run ata_vxworks_args;setenv loadaddr ff000000;bootvx\0" \
"flash_vxworks1=run ata_vxworks_args;setenv loadaddr ff200000:bootvx\0" \
"net_vxworks=phypower 1;sleep 2;tftp ${loadaddr} ${image};run vxworks_args;bootvx\0" \
"vxworks_args=setenv bootargs fec(0,0)${host}:${image} h=${serverip} e=${ipaddr} g=${gatewayip} u=${user} ${pass} tn=${target} s=${script}\0" \
"ata_vxworks_args=setenv bootargs /ata0/vxWorks h=${serverip} e=${ipaddr} g=${gatewayip} u=${user} ${pass} tn=${target} s=${script} o=fec0 \0" \
"loadaddr=01000000\0" \
"serverip=192.168.2.99\0" \
"gatewayip=10.0.0.79\0" \
"user=mu\0" \
"target=cpci5200.esd\0" \
"script=cpci5200.bat\0" \
"image=/tftpboot/vxWorks_cpci5200\0" \
"ipaddr=10.0.13.196\0" \
"netmask=255.255.0.0\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_vxworks0"
#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */
#define CONFIG_SYS_NVRAM_BASE_ADDR 0xfd010000
#define CONFIG_SYS_NVRAM_SIZE 32*1024
/*
* IPB Bus clocking configuration.
*/
#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
/*
* I2C configuration
*/
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
#define CONFIG_SYS_I2C_MODULE 1 /* Select I2C module #1 or #2 */
#define CONFIG_SYS_I2C_SPEED 86000 /* 100 kHz */
#define CONFIG_SYS_I2C_SLAVE 0x7F
/*
* EEPROM configuration
*/
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
#define CONFIG_SYS_I2C_MULTI_EEPROMS 1
/*
* Flash configuration
*/
#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
#define CONFIG_SYS_FLASH_BASE 0xFE000000
#define CONFIG_SYS_FLASH_SIZE 0x02000000
#define CONFIG_SYS_FLASH_INCREMENT 0x01000000
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00000000)
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of memory banks */
#define CONFIG_SYS_MAX_FLASH_SECT 128
#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware protection */
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
/*
* Environment settings
*/
#if 1 /* test-only */
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_SIZE 0x20000
#define CONFIG_ENV_SECT_SIZE 0x20000
#define CONFIG_ENV_OVERWRITE 1
#else
#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
#define CONFIG_ENV_OFFSET 0x0000 /* environment starts at the beginning of the EEPROM */
#define CONFIG_ENV_SIZE 0x0400 /* 8192 bytes may be used for env vars */
/* total size of a CAT24WC32 is 8192 bytes */
#define CONFIG_ENV_OVERWRITE 1
#endif
/*
* Memory map
*/
#define CONFIG_SYS_MBAR 0xF0000000
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
/* Use SRAM until RAM will be available */
#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
# define CONFIG_SYS_RAMBOOT 1
#endif
#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*
* Ethernet configuration
*/
#define CONFIG_MPC5xxx_FEC 1
#define CONFIG_MPC5xxx_FEC_MII100
/*
* Define CONFIG_FEC_10MBIT to force FEC at 10Mb
*/
/* #define CONFIG_FEC_10MBIT 1 */
#define CONFIG_PHY_ADDR 0x00
#define CONFIG_UDP_CHECKSUM 1
/*
* GPIO configuration
*/
#define CONFIG_SYS_GPS_PORT_CONFIG 0x01052444
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
#define CONFIG_SYS_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */
#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
#if defined(CONFIG_CMD_KGDB)
# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
/*
* Various low-level settings
*/
#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
#define CONFIG_SYS_HID0_FINAL HID0_ICE
#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
#define CONFIG_SYS_BOOTCS_CFG 0x0004DD00
#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
#define CONFIG_SYS_CS1_START 0xfd000000
#define CONFIG_SYS_CS1_SIZE 0x00010000
#define CONFIG_SYS_CS1_CFG 0x10101410
#define CONFIG_SYS_CS3_START 0xfd010000
#define CONFIG_SYS_CS3_SIZE 0x00010000
#define CONFIG_SYS_CS3_CFG 0x10109410
#define CONFIG_SYS_CS_BURST 0x00000000
#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
#define CONFIG_SYS_RESET_ADDRESS 0xff000000
/*-----------------------------------------------------------------------
* USB stuff
*-----------------------------------------------------------------------
*/
#define CONFIG_USB_CLOCK 0x0001BBBB
#define CONFIG_USB_CONFIG 0x00001000
/*-----------------------------------------------------------------------
* IDE/ATA stuff Supports IDE harddisk
*-----------------------------------------------------------------------
*/
#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
#undef CONFIG_IDE_LED /* LED for ide not supported */
#define CONFIG_IDE_RESET /* reset for ide supported */
#define CONFIG_IDE_PREINIT
#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
/* Offset for data I/O */
#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
/* Offset for normal register accesses */
#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
/* Offset for alternate registers */
#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
/* Interval between registers */
#define CONFIG_SYS_ATA_STRIDE 4
/*-----------------------------------------------------------------------
* CPLD stuff
*/
#define CONFIG_SYS_FPGA_XC95XL 1 /* using Xilinx XC95XL CPLD */
#define CONFIG_SYS_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for CPLD */
/* CPLD program pin configuration */
#define CONFIG_SYS_FPGA_PRG 0x20000000 /* JTAG TMS pin (ppc output) */
#define CONFIG_SYS_FPGA_CLK 0x10000000 /* JTAG TCK pin (ppc output) */
#define CONFIG_SYS_FPGA_DATA 0x20000000 /* JTAG TDO->TDI data pin (ppc output) */
#define CONFIG_SYS_FPGA_DONE 0x10000000 /* JTAG TDI->TDO pin (ppc input) */
#define JTAG_GPIO_ADDR_TMS (CONFIG_SYS_MBAR + 0xB10) /* JTAG TMS pin (GPS data out value reg.) */
#define JTAG_GPIO_ADDR_TCK (CONFIG_SYS_MBAR + 0xC0C) /* JTAG TCK pin (GPW data out value reg.) */
#define JTAG_GPIO_ADDR_TDI (CONFIG_SYS_MBAR + 0xC0C) /* JTAG TDO->TDI pin (GPW data out value reg.) */
#define JTAG_GPIO_ADDR_TDO (CONFIG_SYS_MBAR + 0xB14) /* JTAG TDI->TDO pin (GPS data in value reg.) */
#define JTAG_GPIO_ADDR_CFG (CONFIG_SYS_MBAR + 0xB00)
#define JTAG_GPIO_CFG_SET 0x00000000
#define JTAG_GPIO_CFG_RESET 0x00F00000
#define JTAG_GPIO_ADDR_EN_TMS (CONFIG_SYS_MBAR + 0xB04)
#define JTAG_GPIO_TMS_EN_SET 0x20000000 /* Enable for GPIO */
#define JTAG_GPIO_TMS_EN_RESET 0x00000000
#define JTAG_GPIO_ADDR_DDR_TMS (CONFIG_SYS_MBAR + 0xB0C)
#define JTAG_GPIO_TMS_DDR_SET 0x20000000 /* Set as output */
#define JTAG_GPIO_TMS_DDR_RESET 0x00000000
#define JTAG_GPIO_ADDR_EN_TCK (CONFIG_SYS_MBAR + 0xC00)
#define JTAG_GPIO_TCK_EN_SET 0x20000000 /* Enable for GPIO */
#define JTAG_GPIO_TCK_EN_RESET 0x00000000
#define JTAG_GPIO_ADDR_DDR_TCK (CONFIG_SYS_MBAR + 0xC08)
#define JTAG_GPIO_TCK_DDR_SET 0x20000000 /* Set as output */
#define JTAG_GPIO_TCK_DDR_RESET 0x00000000
#define JTAG_GPIO_ADDR_EN_TDI (CONFIG_SYS_MBAR + 0xC00)
#define JTAG_GPIO_TDI_EN_SET 0x10000000 /* Enable as GPIO */
#define JTAG_GPIO_TDI_EN_RESET 0x00000000
#define JTAG_GPIO_ADDR_DDR_TDI (CONFIG_SYS_MBAR + 0xC08)
#define JTAG_GPIO_TDI_DDR_SET 0x10000000 /* Set as output */
#define JTAG_GPIO_TDI_DDR_RESET 0x00000000
#define JTAG_GPIO_ADDR_EN_TDO (CONFIG_SYS_MBAR + 0xB04)
#define JTAG_GPIO_TDO_EN_SET 0x10000000 /* Enable as GPIO */
#define JTAG_GPIO_TDO_EN_RESET 0x00000000
#define JTAG_GPIO_ADDR_DDR_TDO (CONFIG_SYS_MBAR + 0xB0C)
#define JTAG_GPIO_TDO_DDR_SET 0x00000000
#define JTAG_GPIO_TDO_DDR_RESET 0x10000000 /* Set as input */
#endif /* __CONFIG_H */

49
include/configs/db-mv784mp-gp.h
View File

@@ -11,6 +11,8 @@
* High Level Configuration Options (easy to change)
*/
#define CONFIG_ARMADA_XP /* SOC Family Name */
#define CONFIG_DB_784MP_GP /* Board target name for DDR training */
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_DISPLAY_BOARDINFO_LATE
@@ -65,4 +67,51 @@
*/
#include "mv-common.h"
/*
* Memory layout while starting into the bin_hdr via the
* BootROM:
*
* 0x4000.4000 - 0x4003.4000 headers space (192KiB)
* 0x4000.4030 bin_hdr start address
* 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB)
* 0x4007.fffc BootROM stack top
*
* The address space between 0x4007.fffc and 0x400f.fff is not locked in
* L2 cache thus cannot be used.
*/
/* SPL */
/* Defines for SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE 0x40004030
#define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030)
#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10))
#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
CONFIG_SPL_BSS_MAX_SIZE)
#define CONFIG_SYS_SPL_MALLOC_SIZE (16 << 10)
#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_I2C_SUPPORT
#define CONFIG_SPL_LDSCRIPT "arch/arm/mvebu-common/u-boot-spl.lds"
/* SPL related SPI defines */
#define CONFIG_SPL_SPI_SUPPORT
#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SPL_SPI_BUS 0
#define CONFIG_SPL_SPI_CS 0
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
#define CONFIG_SYS_MVEBU_DDR
#define CONFIG_SPD_EEPROM 0x4e
#endif /* _CONFIG_DB_MV7846MP_GP_H */

2
include/configs/dockstar.h
View File

@@ -12,6 +12,8 @@
#ifndef _CONFIG_DOCKSTAR_H
#define _CONFIG_DOCKSTAR_H
#define CONFIG_SYS_GENERIC_BOARD
/*
* Version number information
*/

7
include/configs/exynos5-common.h
View File

@@ -126,12 +126,11 @@
#define SPI_FLASH_UBOOT_POS (CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE)
/* I2C */
#define CONFIG_SYS_I2C_INIT_BOARD
#define CONFIG_SYS_I2C
#define CONFIG_DM_I2C
#define CONFIG_DM_I2C_COMPAT
#define CONFIG_CMD_I2C
#define CONFIG_SYS_I2C_S3C24X0_SPEED 100000 /* 100 Kbps */
#define CONFIG_SYS_I2C_S3C24X0
#define CONFIG_I2C_MULTI_BUS
#define CONFIG_SYS_I2C_S3C24X0_SPEED 100000 /* 100 Kbps */
#define CONFIG_SYS_I2C_S3C24X0_SLAVE 0x0
#define CONFIG_I2C_EDID

3
include/configs/exynos5250-common.h
View File

@@ -28,9 +28,6 @@
#define CONFIG_SYS_INIT_SP_ADDR CONFIG_IRAM_STACK
/* PMIC */
#define CONFIG_POWER_MAX77686
/* Sound */
#define CONFIG_CMD_SOUND
#ifdef CONFIG_CMD_SOUND

60
include/configs/galileo.h Normal file
View File

@@ -0,0 +1,60 @@
/*
* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
/*
* board/config.h - configuration options, board specific
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#include <configs/x86-common.h>
#define CONFIG_SYS_MONITOR_LEN (1 << 20)
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_X86_SERIAL
/* ns16550 UART is memory-mapped in Quark SoC */
#undef CONFIG_SYS_NS16550_PORT_MAPPED
#define CONFIG_PCI_MEM_BUS 0x90000000
#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
#define CONFIG_PCI_MEM_SIZE 0x20000000
#define CONFIG_PCI_PREF_BUS 0xb0000000
#define CONFIG_PCI_PREF_PHYS CONFIG_PCI_PREF_BUS
#define CONFIG_PCI_PREF_SIZE 0x20000000
#define CONFIG_PCI_IO_BUS 0x2000
#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
#define CONFIG_PCI_IO_SIZE 0xe000
#define CONFIG_SYS_EARLY_PCI_INIT
#define CONFIG_PCI_PNP
#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial\0" \
"stdout=serial\0" \
"stderr=serial\0"
/* SATA is not supported in Quark SoC */
#undef CONFIG_SCSI_AHCI
#undef CONFIG_CMD_SCSI
/* Video is not supported in Quark SoC */
#undef CONFIG_VIDEO
#undef CONFIG_CFB_CONSOLE
/* SD/MMC support */
#define CONFIG_MMC
#define CONFIG_SDHCI
#define CONFIG_GENERIC_MMC
#define CONFIG_MMC_SDMA
#define CONFIG_CMD_MMC
#endif /* __CONFIG_H */

2
include/configs/goflexhome.h
View File

@@ -15,6 +15,8 @@
#ifndef _CONFIG_GOFLEXHOME_H
#define _CONFIG_GOFLEXHOME_H
#define CONFIG_SYS_GENERIC_BOARD
/*
* Version number information
*/

82
include/configs/guruplug.h
View File

@@ -1,5 +1,6 @@
/*
* (C) Copyright 2009
* (C) Copyright 2009-2014
* Gerald Kerma <dreagle@doukki.net>
* Marvell Semiconductor <www.marvell.com>
* Written-by: Siddarth Gore <gores@marvell.com>
*
@@ -9,6 +10,8 @@
#ifndef _CONFIG_GURUPLUG_H
#define _CONFIG_GURUPLUG_H
#define CONFIG_SYS_GENERIC_BOARD
/*
* Version number information
*/
@@ -22,18 +25,37 @@
#define CONFIG_MACH_GURUPLUG /* Machine type */
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
/*
* Compression configuration
*/
#define CONFIG_BZIP2
#define CONFIG_LZMA
#define CONFIG_LZO
/*
* Enable device tree support
*/
#define CONFIG_OF_LIBFDT
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
/*
* Commands configuration
*/
#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
#include <config_cmd_default.h>
#define CONFIG_CMD_BOOTZ
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ENV
#define CONFIG_CMD_FAT
#define CONFIG_CMD_IDE
#define CONFIG_CMD_MII
#define CONFIG_CMD_NAND
#define CONFIG_CMD_PING
#define CONFIG_CMD_USB
#define CONFIG_CMD_IDE
#define CONFIG_CMD_FAT
/*
* mv-common.h should be defined after CMD configs since it used them
@@ -55,24 +77,38 @@
* it has to be rounded to sector size
*/
#define CONFIG_ENV_SIZE 0x20000 /* 128k */
#define CONFIG_ENV_ADDR 0x60000
#define CONFIG_ENV_OFFSET 0x60000 /* env starts here */
#define CONFIG_ENV_OFFSET 0xE0000 /* env starts here */
/*
* Default environment variables
*/
#define CONFIG_BOOTCOMMAND "setenv ethact egiga0; " \
"${x_bootcmd_ethernet}; setenv ethact egiga1; " \
"${x_bootcmd_ethernet}; ${x_bootcmd_usb}; ${x_bootcmd_kernel}; "\
"setenv bootargs ${x_bootargs} ${x_bootargs_root}; " \
"bootm 0x6400000;"
#define CONFIG_BOOTCOMMAND \
"setenv bootargs ${console} ${mtdparts} ${bootargs_root}; " \
"ubi part root; " \
"ubifsmount ubi:rootfs; " \
"ubifsload 0x800000 ${kernel}; " \
"ubifsload 0x700000 ${fdt}; " \
"ubifsumount; " \
"fdt addr 0x700000; fdt resize; fdt chosen; " \
"bootz 0x800000 - 0x700000"
#define CONFIG_EXTRA_ENV_SETTINGS \
"x_bootcmd_ethernet=ping 192.168.2.1\0" \
"x_bootcmd_usb=usb start\0" \
"x_bootcmd_kernel=nand read.e 0x6400000 0x100000 0x400000\0" \
"x_bootargs=console=ttyS0,115200\0" \
"x_bootargs_root=ubi.mtd=2 root=ubi0:rootfs rootfstype=ubifs\0"
#define CONFIG_MTDPARTS \
"mtdparts=orion_nand:" \
"896K(uboot),128K(uboot_env)," \
"-@1M(root)\0"
#define CONFIG_EXTRA_ENV_SETTINGS \
"console=console=ttyS0,115200\0" \
"mtdids=nand0=orion_nand\0" \
"mtdparts="CONFIG_MTDPARTS \
"kernel=/boot/zImage\0" \
"fdt=/boot/guruplug-server-plus.dtb\0" \
"bootargs_root=ubi.mtd=2 root=ubi0:rootfs rootfstype=ubifs rw\0"
#define MTDIDS_DEFAULT "nand0=orion_nand"
#define MTDPARTS_DEFAULT \
"mtdparts="CONFIG_MTDPARTS
/*
* Ethernet Driver configuration
@@ -89,6 +125,20 @@
#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
#endif /*CONFIG_MVSATA_IDE*/
/*
* File system
*/
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_EXT4
#define CONFIG_CMD_FAT
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_UBI
#define CONFIG_CMD_UBIFS
#define CONFIG_RBTREE
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
#define CONFIG_CMD_MTDPARTS
#define CONFIG_SYS_ALT_MEMTEST
#endif /* _CONFIG_GURUPLUG_H */

2
include/configs/ib62x0.h
View File

@@ -9,6 +9,8 @@
#ifndef _CONFIG_IB62x0_H
#define _CONFIG_IB62x0_H
#define CONFIG_SYS_GENERIC_BOARD
/*
* Version number information
*/

2
include/configs/ibf-dsp561.h
View File

@@ -82,7 +82,7 @@
#define CONFIG_ENV_OFFSET 0x4000
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_SECT_SIZE 0x10000 /* Total Size of Environment Sector */
#define CONFIG_ENV_SECT_SIZE 0x12000 /* Total Size of Environment Sector */
#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
#define ENV_IS_EMBEDDED
#else

2
include/configs/iconnect.h
View File

@@ -9,6 +9,8 @@
#ifndef _CONFIG_ICONNECT_H
#define _CONFIG_ICONNECT_H
#define CONFIG_SYS_GENERIC_BOARD
/*
* Version number information
*/

3
include/configs/ids8313.h
View File

@@ -575,12 +575,9 @@
#define CONFIG_VERSION_VARIABLE
#define CONFIG_FIT
#define CONFIG_FIT_SIGNATURE
#define CONFIG_IMAGE_FORMAT_LEGACY
#define CONFIG_CMD_FDT
#define CONFIG_CMD_HASH
#define CONFIG_RSA
#define CONFIG_SHA1
#define CONFIG_SHA256

2
include/configs/ip04.h
View File

@@ -61,7 +61,7 @@
#define CONFIG_EBIU_AMBCTL0_VAL 0xffc2ffc2
#define CONFIG_EBIU_AMBCTL1_VAL 0xffc2ffc2
#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
#define CONFIG_SYS_MONITOR_LEN (384 * 1024)
#define CONFIG_SYS_MALLOC_LEN (128 * 1024)

41
include/configs/ls1021aqds.h
View File

@@ -19,6 +19,11 @@
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_DEEP_SLEEP
#if defined(CONFIG_DEEP_SLEEP)
#define CONFIG_SILENT_CONSOLE
#endif
/*
* Size of malloc() pool
*/
@@ -72,7 +77,8 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_SPL_PAD_TO 0x1c000
#define CONFIG_SYS_TEXT_BASE 0x82000000
#define CONFIG_SYS_SPL_MALLOC_START 0x80200000
#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \
CONFIG_SYS_MONITOR_LEN)
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
#define CONFIG_SPL_BSS_START_ADDR 0x80100000
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
@@ -365,11 +371,16 @@ unsigned long get_board_ddr_clk(void);
/*
* Serial Port
*/
#ifdef CONFIG_LPUART
#define CONFIG_FSL_LPUART
#define CONFIG_LPUART_32B_REG
#else
#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
#endif
#define CONFIG_BAUDRATE 115200
@@ -385,6 +396,7 @@ unsigned long get_board_ddr_clk(void);
*/
#define I2C_MUX_PCA_ADDR_PRI 0x77
#define I2C_MUX_CH_DEFAULT 0x8
#define I2C_MUX_CH_CH7301 0xC
/*
* MMC
@@ -426,6 +438,25 @@ unsigned long get_board_ddr_clk(void);
#endif
#endif
/*
* Video
*/
#define CONFIG_FSL_DCU_FB
#ifdef CONFIG_FSL_DCU_FB
#define CONFIG_VIDEO
#define CONFIG_CMD_BMP
#define CONFIG_CFB_CONSOLE
#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO
#define CONFIG_FSL_DIU_CH7301
#define CONFIG_SYS_I2C_DVI_BUS_NUM 0
#define CONFIG_SYS_I2C_QIXIS_ADDR 0x66
#define CONFIG_SYS_I2C_DVI_ADDR 0x75
#endif
/*
* eTSEC
*/
@@ -508,11 +539,19 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_SYS_QE_FW_ADDR 0x67f40000
#ifdef CONFIG_LPUART
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
"fdt_high=0xcfffffff\0" \
"initrd_high=0xcfffffff\0" \
"hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
#else
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
"fdt_high=0xcfffffff\0" \
"initrd_high=0xcfffffff\0" \
"hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
#endif
/*
* Miscellaneous configurable options

12
include/configs/ls1021atwr.h
View File

@@ -186,11 +186,16 @@
/*
* Serial Port
*/
#ifdef CONFIG_LPUART
#define CONFIG_FSL_LPUART
#define CONFIG_LPUART_32B_REG
#else
#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
#endif
#define CONFIG_BAUDRATE 115200
@@ -325,10 +330,17 @@
#define CONFIG_BOOTDELAY 3
#ifdef CONFIG_LPUART
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
"initrd_high=0xcfffffff\0" \
"fdt_high=0xcfffffff\0"
#else
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
"initrd_high=0xcfffffff\0" \
"fdt_high=0xcfffffff\0"
#endif
/*
* Miscellaneous configurable options

15
include/configs/malta.h
View File

@@ -38,8 +38,6 @@
#define CONFIG_SYS_MHZ 250 /* arbitrary value */
#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
#define CONFIG_SWAP_IO_SPACE
/*
* Memory map
*/
@@ -73,6 +71,7 @@
sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS 16
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_AUTO_COMPLETE
#define CONFIG_CMDLINE_EDITING
@@ -108,6 +107,16 @@
#define CONFIG_ENV_ADDR \
(CONFIG_SYS_FLASH_BASE + (4 << 20) - CONFIG_ENV_SIZE)
/*
* IDE/ATA
*/
#define CONFIG_SYS_IDE_MAXBUS 1
#define CONFIG_SYS_IDE_MAXDEVICE 2
#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_ISA_IO_BASE_ADDRESS
#define CONFIG_SYS_ATA_IDE0_OFFSET 0x01f0
#define CONFIG_SYS_ATA_DATA_OFFSET 0
#define CONFIG_SYS_ATA_REG_OFFSET 0
/*
* Commands
*/
@@ -120,6 +129,8 @@
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ELF
#define CONFIG_CMD_IDE
#define CONFIG_CMD_PCI
#define CONFIG_CMD_PING

49
include/configs/maxbcm.h
View File

@@ -43,6 +43,8 @@
#define CONFIG_SF_DEFAULT_SPEED 1000000
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_SPI_FLASH_SPANSION
#define CONFIG_SPI_FLASH_BAR
/* Environment in SPI NOR flash */
#define CONFIG_ENV_IS_IN_SPI_FLASH
@@ -65,4 +67,51 @@
*/
#include "mv-common.h"
/*
* Memory layout while starting into the bin_hdr via the
* BootROM:
*
* 0x4000.4000 - 0x4003.4000 headers space (192KiB)
* 0x4000.4030 bin_hdr start address
* 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB)
* 0x4007.fffc BootROM stack top
*
* The address space between 0x4007.fffc and 0x400f.fff is not locked in
* L2 cache thus cannot be used.
*/
/* SPL */
/* Defines for SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE 0x40004030
#define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030)
#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10))
#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
CONFIG_SPL_BSS_MAX_SIZE)
#define CONFIG_SYS_SPL_MALLOC_SIZE (16 << 10)
#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_I2C_SUPPORT
#define CONFIG_SPL_LDSCRIPT "arch/arm/mvebu-common/u-boot-spl.lds"
/* SPL related SPI defines */
#define CONFIG_SPL_SPI_SUPPORT
#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SPL_SPI_BUS 0
#define CONFIG_SPL_SPI_CS 0
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
#define CONFIG_SYS_MVEBU_DDR
#define CONFIG_DDR_FIXED_SIZE (1 << 20) /* 1GiB */
#endif /* _CONFIG_DB_MV7846MP_GP_H */

319
include/configs/mecp5200.h
View File

@@ -1,319 +0,0 @@
/*
* (C) Copyright 2003-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
/*************************************************************************
* (c) 2005 esd gmbh Hannover
*
*
* from IceCube.h file
* by Reinhard Arlt reinhard.arlt@esd-electronics.com
*
*************************************************************************/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
#define CONFIG_ICECUBE 1 /* ... on IceCube board */
#define CONFIG_MECP5200 1 /* ... on MECP5200 board */
#define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0xFFF00000
#endif
#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/*
* Serial console configuration
*/
#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
#if 0 /* test-only */
#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
#else
#define CONFIG_BAUDRATE 9600 /* ... at 115200 bps */
#endif
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
#define CONFIG_MII
#if 0 /* test-only !!! */
#define CONFIG_EEPRO100 1
#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
#define CONFIG_NS8382X 1
#endif
/* Partitions */
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
/* USB */
#if 0
#define CONFIG_USB_OHCI
#define CONFIG_USB_STORAGE
#endif
/*
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_FAT
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IDE
#define CONFIG_CMD_BSP
#define CONFIG_CMD_ELF
#if (CONFIG_SYS_TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
# define CONFIG_SYS_LOWBOOT 1
# define CONFIG_SYS_LOWBOOT16 1
#endif
#if (CONFIG_SYS_TEXT_BASE == 0xFF800000) /* Boot low with 8 MB Flash */
# define CONFIG_SYS_LOWBOOT 1
# define CONFIG_SYS_LOWBOOT08 1
#endif
/*
* Autobooting
*/
#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
#define CONFIG_PREBOOT "echo;" \
"echo Welcome to CBX-CPU5200 (mecp5200);" \
"echo"
#undef CONFIG_BOOTARGS
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"flash_vxworks0=run ata_vxworks_args;setenv loadaddr ff000000;bootvx\0" \
"flash_vxworks1=run ata_vxworks_args;setenv loadaddr ff200000:bootvx\0" \
"net_vxworks=tftp $(loadaddr) $(image);run vxworks_args;bootvx\0" \
"vxworks_args=setenv bootargs fec(0,0)$(host):$(image) h=$(serverip) e=$(ipaddr) g=$(gatewayip) u=$(user) $(pass) tn=$(target) s=$(script)\0" \
"ata_vxworks_args=setenv bootargs /ata0/vxWorks h=$(serverip) e=$(ipaddr) g=$(gatewayip) u=$(user) $(pass) tn=$(target) s=$(script) o=fec0 \0" \
"loadaddr=01000000\0" \
"serverip=192.168.2.99\0" \
"gatewayip=10.0.0.79\0" \
"user=mu\0" \
"target=mecp5200.esd\0" \
"script=mecp5200.bat\0" \
"image=/tftpboot/vxWorks_mecp5200\0" \
"ipaddr=10.0.13.196\0" \
"netmask=255.255.0.0\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_vxworks0"
/*
* IPB Bus clocking configuration.
*/
#undef CONFIG_SYS_IPBSPEED_133 /* define for 133MHz speed */
/*
* I2C configuration
*/
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
#define CONFIG_SYS_I2C_SPEED 86000 /* 100 kHz */
#define CONFIG_SYS_I2C_SLAVE 0x7F
/*
* EEPROM configuration
*/
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
#define CONFIG_SYS_I2C_MULTI_EEPROMS 1
/*
* Flash configuration
*/
#define CONFIG_SYS_FLASH_BASE 0xFFC00000
#define CONFIG_SYS_FLASH_SIZE 0x00400000
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x003E0000)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
#define CONFIG_SYS_MAX_FLASH_SECT 512
#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
/*
* Environment settings
*/
#if 1 /* test-only */
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_SIZE 0x10000
#define CONFIG_ENV_SECT_SIZE 0x10000
#define CONFIG_ENV_OVERWRITE 1
#else
#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
#define CONFIG_ENV_OFFSET 0x0000 /* environment starts at the beginning of the EEPROM */
#define CONFIG_ENV_SIZE 0x0400 /* 8192 bytes may be used for env vars*/
/* total size of a CAT24WC32 is 8192 bytes */
#define CONFIG_ENV_OVERWRITE 1
#endif
#define CONFIG_FLASH_CFI_DRIVER 1 /* Flash is CFI conformant */
#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware protection */
#if 0
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
#endif
#define CONFIG_SYS_FLASH_INCREMENT 0x00400000 /* size of flash bank */
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
#define CONFIG_SYS_FLASH_EMPTY_INFO 1 /* show if bank is empty */
/*
* Memory map
*/
#define CONFIG_SYS_MBAR 0xF0000000
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
/* Use SRAM until RAM will be available */
#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
# define CONFIG_SYS_RAMBOOT 1
#endif
#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*
* Ethernet configuration
*/
#define CONFIG_MPC5xxx_FEC 1
#define CONFIG_MPC5xxx_FEC_MII100
/*
* Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
*/
/* #define CONFIG_MPC5xxx_FEC_MII10 */
#define CONFIG_PHY_ADDR 0x00
#define CONFIG_UDP_CHECKSUM 1
/*
* GPIO configuration
*/
#define CONFIG_SYS_GPS_PORT_CONFIG 0x01052444
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
#define CONFIG_SYS_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */
#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
#if defined(CONFIG_CMD_KGDB)
# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
/*
* Various low-level settings
*/
#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
#define CONFIG_SYS_HID0_FINAL HID0_ICE
#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
#define CONFIG_SYS_BOOTCS_CFG 0x00085d00
#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
#define CONFIG_SYS_CS1_START 0xfd000000
#define CONFIG_SYS_CS1_SIZE 0x00010000
#define CONFIG_SYS_CS1_CFG 0x10101410
#define CONFIG_SYS_CS_BURST 0x00000000
#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
#define CONFIG_SYS_RESET_ADDRESS 0xff000000
/*-----------------------------------------------------------------------
* USB stuff
*-----------------------------------------------------------------------
*/
#define CONFIG_USB_CLOCK 0x0001BBBB
#define CONFIG_USB_CONFIG 0x00001000
/*-----------------------------------------------------------------------
* IDE/ATA stuff Supports IDE harddisk
*-----------------------------------------------------------------------
*/
#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
#undef CONFIG_IDE_LED /* LED for ide not supported */
#define CONFIG_IDE_RESET /* reset for ide supported */
#define CONFIG_IDE_PREINIT
#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
/* Offset for data I/O */
#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
/* Offset for normal register accesses */
#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
/* Offset for alternate registers */
#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
/* Interval between registers */
#define CONFIG_SYS_ATA_STRIDE 4
#endif /* __CONFIG_H */

97
include/configs/microblaze-generic.h
View File

@@ -106,62 +106,22 @@
# define CONFIG_XILINX_TB_WATCHDOG
#endif
/*
* memory layout - Example
* CONFIG_SYS_TEXT_BASE = 0x1200_0000; defined in config.mk
* CONFIG_SYS_SRAM_BASE = 0x1000_0000;
* CONFIG_SYS_SRAM_SIZE = 0x0400_0000; 64MB
*
* CONFIG_SYS_MONITOR_LEN = 0x40000
* CONFIG_SYS_MALLOC_LEN = 3 * CONFIG_SYS_MONITOR_LEN = 0xC0000
*
* CONFIG_SYS_GBL_DATA_OFFSET = 0x1000_0000 + 0x0400_0000 - 0x1000 = 0x13FF_F000
* CONFIG_SYS_MONITOR_BASE = 0x13FF_F000 - CONFIG_SYS_MONITOR_LEN = 0x13FB_F000
* CONFIG_SYS_MALLOC_BASE = 0x13FB_F000 - CONFIG_SYS_MALLOC_LEN = 0x13EF_F000
*
* 0x1000_0000 CONFIG_SYS_SDRAM_BASE
* MEMTEST_AREA 64kB
* FREE
* 0x1200_0000 CONFIG_SYS_TEXT_BASE
* U-BOOT code
* 0x1202_0000
* FREE
*
* STACK
* 0x13EF_F000 CONFIG_SYS_MALLOC_BASE
* MALLOC_AREA 768kB Alloc
* 0x13FB_F000 CONFIG_SYS_MONITOR_BASE
* MONITOR_CODE 256kB Env
* 0x13FF_F000 CONFIG_SYS_GBL_DATA_OFFSET
* GLOBAL_DATA 4kB bd, gd
* 0x1400_0000 CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE
*/
#ifndef CONFIG_OF_CONTROL
/* ddr sdram - main memory */
#define CONFIG_SYS_SDRAM_BASE XILINX_RAM_START
#define CONFIG_SYS_SDRAM_SIZE XILINX_RAM_SIZE
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x1000)
# define CONFIG_SYS_SDRAM_BASE XILINX_RAM_START
# define CONFIG_SYS_SDRAM_SIZE XILINX_RAM_SIZE
#endif
/* global pointer */
/* start of global data */
#define CONFIG_SYS_GBL_DATA_OFFSET \
(CONFIG_SYS_SDRAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_MALLOC_LEN 0xC0000
#ifndef CONFIG_SPL_BUILD
# define CONFIG_SYS_MALLOC_F_LEN 1024
#else
# define CONFIG_SYS_MALLOC_SIMPLE
# define CONFIG_SYS_MALLOC_F_LEN 0x150
#endif
/* monitor code */
#define SIZE 0x40000
#define CONFIG_SYS_MONITOR_LEN SIZE
#define CONFIG_SYS_MONITOR_BASE \
(CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_GBL_DATA_OFFSET \
- CONFIG_SYS_MONITOR_LEN - GENERATED_BD_INFO_SIZE)
#define CONFIG_SYS_MONITOR_END \
(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
#define CONFIG_SYS_MALLOC_LEN (SIZE * 3)
#define CONFIG_SYS_MALLOC_BASE \
(CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
/* stack */
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_MALLOC_BASE
/* Stack location before relocation */
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_TEXT_BASE
/*
* CFI flash memory layout - Example
@@ -452,7 +412,10 @@
#define CONFIG_SPL_LDSCRIPT "arch/microblaze/cpu/u-boot-spl.lds"
#define CONFIG_SPL_RAM_DEVICE
#define CONFIG_SPL_NOR_SUPPORT
#ifdef CONFIG_SYS_FLASH_BASE
# define CONFIG_SPL_NOR_SUPPORT
# define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_FLASH_BASE
#endif
/* for booting directly linux */
#define CONFIG_SPL_OS_BOOT
@@ -468,36 +431,20 @@
/* BRAM start */
#define CONFIG_SYS_INIT_RAM_ADDR 0x0
/* BRAM size - will be generated */
#define CONFIG_SYS_INIT_RAM_SIZE 0x10000
/* Stack pointer prior relocation, must situated at on-chip RAM */
#define CONFIG_SYS_SPL_MALLOC_END (CONFIG_SYS_INIT_RAM_ADDR + \
#define CONFIG_SYS_INIT_RAM_SIZE 0x100000
# define CONFIG_SPL_STACK_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100
/*
* The main reason to do it in this way is that MALLOC_START
* can't be defined - common/spl/spl.c
*/
#if (CONFIG_SYS_SPL_MALLOC_SIZE != 0)
# define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_SPL_MALLOC_END - \
CONFIG_SYS_SPL_MALLOC_SIZE)
# define CONFIG_SPL_STACK_ADDR CONFIG_SYS_SPL_MALLOC_START
#else
# define CONFIG_SPL_STACK_ADDR CONFIG_SYS_SPL_MALLOC_END
#endif
CONFIG_SYS_MALLOC_F_LEN)
/* Just for sure that there is a space for stack */
#define CONFIG_SPL_STACK_SIZE 0x100
#define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
#define CONFIG_SPL_MAX_FOOTPRINT (CONFIG_SYS_INIT_RAM_SIZE - \
CONFIG_SYS_INIT_RAM_ADDR - \
GENERATED_GBL_DATA_SIZE - \
CONFIG_SYS_SPL_MALLOC_SIZE - \
CONFIG_SYS_MALLOC_F_LEN - \
CONFIG_SPL_STACK_SIZE)
#endif /* __CONFIG_H */

72
include/configs/minnowmax.h Normal file
View File

@@ -0,0 +1,72 @@
/*
* Copyright (C) 2015 Google, Inc
*
* SPDX-License-Identifier: GPL-2.0+
*/
/*
* board/config.h - configuration options, board specific
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#include <configs/x86-common.h>
#define CONFIG_SYS_MONITOR_LEN (1 << 20)
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_X86_SERIAL
#define CONFIG_SMSC_LPC47M
#define CONFIG_PCI_MEM_BUS 0xd0000000
#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
#define CONFIG_PCI_MEM_SIZE 0x10000000
#define CONFIG_PCI_PREF_BUS 0xc0000000
#define CONFIG_PCI_PREF_PHYS CONFIG_PCI_PREF_BUS
#define CONFIG_PCI_PREF_SIZE 0x10000000
#define CONFIG_PCI_IO_BUS 0x2000
#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
#define CONFIG_PCI_IO_SIZE 0xe000
#define CONFIG_SYS_EARLY_PCI_INIT
#define CONFIG_PCI_PNP
#define CONFIG_RTL8169
#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,vga,serial\0" \
"stdout=vga,serial\0" \
"stderr=vga,serial\0"
#define CONFIG_SCSI_DEV_LIST \
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA}
#define CONFIG_SPI_FLASH_SST
#define CONFIG_MMC
#define CONFIG_SDHCI
#define CONFIG_GENERIC_MMC
#define CONFIG_MMC_SDMA
#define CONFIG_CMD_MMC
#undef CONFIG_USB_MAX_CONTROLLER_COUNT
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_X86_OPTION_ROM_FILE vga.bin
#define CONFIG_X86_OPTION_ROM_ADDR 0xfff90000
#ifndef CONFIG_SYS_COREBOOT
#define CONFIG_VIDEO_VESA
#endif
#define VIDEO_IO_OFFSET 0
#define CONFIG_X86EMU_RAW_IO
#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_FIT_SIGNATURE
#define CONFIG_RSA
/* Avoid a warning in the Realtek Ethernet driver */
#define CONFIG_SYS_CACHELINE_SIZE 16
#endif /* __CONFIG_H */

1
include/configs/nokia_rx51.h
View File

@@ -28,6 +28,7 @@
#define CONFIG_OMAP3_RX51 /* working with RX51 */
#define CONFIG_SYS_L2CACHE_OFF /* pretend there is no L2 CACHE */
#define CONFIG_OMAP_COMMON
#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_MACH_TYPE MACH_TYPE_NOKIA_RX51

5
include/configs/odroid.h
View File

@@ -177,12 +177,11 @@
/* I2C */
#define CONFIG_CMD_I2C
#define CONFIG_SYS_I2C
#define CONFIG_DM_I2C
#define CONFIG_DM_I2C_COMPAT
#define CONFIG_SYS_I2C_S3C24X0
#define CONFIG_SYS_I2C_S3C24X0_SPEED 100000
#define CONFIG_SYS_I2C_S3C24X0_SLAVE 0
#define CONFIG_MAX_I2C_NUM 8
#define CONFIG_SYS_I2C_INIT_BOARD
/* POWER */
#define CONFIG_POWER

18
include/configs/omap3_igep00x0.h
View File

@@ -29,11 +29,21 @@
#define CONFIG_REVISION_TAG 1
/* define to enable boot progress via leds */
#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020) || \
(CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030)
#define CONFIG_SHOW_BOOT_PROGRESS
/* Status LED */
#define CONFIG_STATUS_LED
#define CONFIG_BOARD_SPECIFIC_LED
#define CONFIG_GPIO_LED
#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020)
#define RED_LED_GPIO 27
#endif
#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030)
#define RED_LED_GPIO 16
#endif
#define RED_LED_DEV 0
#define STATUS_LED_BIT RED_LED_GPIO
#define STATUS_LED_STATE STATUS_LED_ON
#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
#define STATUS_LED_BOOT RED_LED_DEV
/* GPIO banks */
#define CONFIG_OMAP3_GPIO_3 /* GPIO64 .. 95 is in GPIO bank 3 */

372
include/configs/pf5200.h
View File

@@ -1,372 +0,0 @@
/*
* (C) Copyright 2003-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
/*************************************************************************
* (c) 2005 esd gmbh Hannover
*
*
* from IceCube.h file
* by Reinhard Arlt reinhard.arlt@esd-electronics.com
*
*************************************************************************/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
#define CONFIG_ICECUBE 1 /* ... on IceCube board */
#define CONFIG_PF5200 1 /* ... on PF5200 board */
#define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0xFFF00000
#endif
#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/*
* Serial console configuration
*/
#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
#if 0 /* test-only */
#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
#else
#define CONFIG_BAUDRATE 9600 /* ... at 115200 bps */
#endif
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
/*
* PCI Mapping:
* 0x40000000 - 0x4fffffff - PCI Memory
* 0x50000000 - 0x50ffffff - PCI IO Space
*/
#define CONFIG_PCI 1
#define CONFIG_PCI_PNP 1
#define CONFIG_PCI_SCAN_SHOW 1
#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
#define CONFIG_PCI_MEM_BUS 0x40000000
#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
#define CONFIG_PCI_MEM_SIZE 0x10000000
#define CONFIG_PCI_IO_BUS 0x50000000
#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
#define CONFIG_PCI_IO_SIZE 0x01000000
#define CONFIG_MII 1
#if 0 /* test-only !!! */
#define CONFIG_EEPRO100 1
#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
#define CONFIG_NS8382X 1
#endif
/* Partitions */
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
/* USB */
#if 0
#define CONFIG_USB_OHCI
#define CONFIG_USB_STORAGE
#endif
/*
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_BSP
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_ELF
#define CONFIG_CMD_FAT
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IDE
#define CONFIG_CMD_PCI
#if (CONFIG_SYS_TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
# define CONFIG_SYS_LOWBOOT 1
# define CONFIG_SYS_LOWBOOT16 1
#endif
#if (CONFIG_SYS_TEXT_BASE == 0xFF800000) /* Boot low with 8 MB Flash */
# define CONFIG_SYS_LOWBOOT 1
# define CONFIG_SYS_LOWBOOT08 1
#endif
/*
* Autobooting
*/
#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
#define CONFIG_PREBOOT "echo;" \
"echo Welcome to ParaFinder pf5200;" \
"echo"
#undef CONFIG_BOOTARGS
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"flash_vxworks0=run ata_vxworks_args;setenv loadaddr ff000000;bootvx\0" \
"flash_vxworks1=run ata_vxworks_args;setenv loadaddr ff200000:bootvx\0" \
"net_vxworks=phypower 1;sleep 2;tftp ${loadaddr} ${image};run vxworks_args;bootvx\0" \
"vxworks_args=setenv bootargs fec(0,0)${host}:${image} h=${serverip} e=${ipaddr} g=${gatewayip} u=${user} ${pass} tn=${target} s=${script}\0" \
"ata_vxworks_args=setenv bootargs /ata0/vxWorks h=${serverip} e=${ipaddr} g=${gatewayip} u=${user} ${pass} tn=${target} s=${script} o=fec0 \0" \
"loadaddr=01000000\0" \
"serverip=192.168.2.99\0" \
"gatewayip=10.0.0.79\0" \
"user=mu\0" \
"target=pf5200.esd\0" \
"script=pf5200.bat\0" \
"image=/tftpboot/vxWorks_pf5200\0" \
"ipaddr=10.0.13.196\0" \
"netmask=255.255.0.0\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_vxworks0"
/*
* IPB Bus clocking configuration.
*/
#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
/*
* I2C configuration
*/
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
#define CONFIG_SYS_I2C_SPEED 86000 /* 100 kHz */
#define CONFIG_SYS_I2C_SLAVE 0x7F
/*
* EEPROM configuration
*/
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
#define CONFIG_SYS_I2C_MULTI_EEPROMS 1
/*
* Flash configuration
*/
#define CONFIG_SYS_FLASH_BASE 0xFE000000
#define CONFIG_SYS_FLASH_SIZE 0x02000000
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00000000)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
#define CONFIG_SYS_MAX_FLASH_SECT 512
#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
/*
* Environment settings
*/
#if 1 /* test-only */
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SIZE 0x10000
#define CONFIG_ENV_SECT_SIZE 0x10000
#define CONFIG_ENV_OVERWRITE 1
#else
#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
#define CONFIG_ENV_OFFSET 0x0000 /* environment starts at the beginning of the EEPROM */
#define CONFIG_ENV_SIZE 0x0400 /* 8192 bytes may be used for env vars */
/* total size of a CAT24WC32 is 8192 bytes */
#define CONFIG_ENV_OVERWRITE 1
#endif
/*
* Memory map
*/
#define CONFIG_SYS_MBAR 0xF0000000
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
/* Use SRAM until RAM will be available */
#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
# define CONFIG_SYS_RAMBOOT 1
#endif
#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*
* Ethernet configuration
*/
#define CONFIG_MPC5xxx_FEC 1
#define CONFIG_MPC5xxx_FEC_MII100
/*
* Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
*/
/* #define CONFIG_MPC5xxx_FEC_MII10 */
#define CONFIG_PHY_ADDR 0x00
#define CONFIG_UDP_CHECKSUM 1
/*
* GPIO configuration
*/
#define CONFIG_SYS_GPS_PORT_CONFIG 0x01052444
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
#define CONFIG_SYS_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */
#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
#if defined(CONFIG_CMD_KGDB)
# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
/*
* Various low-level settings
*/
#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
#define CONFIG_SYS_HID0_FINAL HID0_ICE
#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
#define CONFIG_SYS_BOOTCS_CFG 0x0004DD00
#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
#define CONFIG_SYS_CS1_START 0xfd000000
#define CONFIG_SYS_CS1_SIZE 0x00010000
#define CONFIG_SYS_CS1_CFG 0x10101410
#define CONFIG_SYS_CS_BURST 0x00000000
#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
#define CONFIG_SYS_RESET_ADDRESS 0xff000000
/*-----------------------------------------------------------------------
* USB stuff
*-----------------------------------------------------------------------
*/
#define CONFIG_USB_CLOCK 0x0001BBBB
#define CONFIG_USB_CONFIG 0x00001000
/*-----------------------------------------------------------------------
* IDE/ATA stuff Supports IDE harddisk
*-----------------------------------------------------------------------
*/
#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
#undef CONFIG_IDE_LED /* LED for ide not supported */
#define CONFIG_IDE_RESET /* reset for ide supported */
#define CONFIG_IDE_PREINIT
#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
/* Offset for data I/O */
#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
/* Offset for normal register accesses */
#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
/* Offset for alternate registers */
#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
/* Interval between registers */
#define CONFIG_SYS_ATA_STRIDE 4
/*-----------------------------------------------------------------------
* CPLD stuff
*/
#define CONFIG_SYS_FPGA_XC95XL 1 /* using Xilinx XC95XL CPLD */
#define CONFIG_SYS_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for CPLD */
/* CPLD program pin configuration */
#define CONFIG_SYS_FPGA_PRG 0x20000000 /* JTAG TMS pin (ppc output) */
#define CONFIG_SYS_FPGA_CLK 0x10000000 /* JTAG TCK pin (ppc output) */
#define CONFIG_SYS_FPGA_DATA 0x20000000 /* JTAG TDO->TDI data pin (ppc output) */
#define CONFIG_SYS_FPGA_DONE 0x10000000 /* JTAG TDI->TDO pin (ppc input) */
#define JTAG_GPIO_ADDR_TMS (CONFIG_SYS_MBAR + 0xB10) /* JTAG TMS pin (GPS data out value reg.) */
#define JTAG_GPIO_ADDR_TCK (CONFIG_SYS_MBAR + 0xC0C) /* JTAG TCK pin (GPW data out value reg.) */
#define JTAG_GPIO_ADDR_TDI (CONFIG_SYS_MBAR + 0xC0C) /* JTAG TDO->TDI pin (GPW data out value reg.) */
#define JTAG_GPIO_ADDR_TDO (CONFIG_SYS_MBAR + 0xB14) /* JTAG TDI->TDO pin (GPS data in value reg.) */
#define JTAG_GPIO_ADDR_CFG (CONFIG_SYS_MBAR + 0xB00)
#define JTAG_GPIO_CFG_SET 0x00000000
#define JTAG_GPIO_CFG_RESET 0x00F00000
#define JTAG_GPIO_ADDR_EN_TMS (CONFIG_SYS_MBAR + 0xB04)
#define JTAG_GPIO_TMS_EN_SET 0x20000000 /* Enable for GPIO */
#define JTAG_GPIO_TMS_EN_RESET 0x00000000
#define JTAG_GPIO_ADDR_DDR_TMS (CONFIG_SYS_MBAR + 0xB0C)
#define JTAG_GPIO_TMS_DDR_SET 0x20000000 /* Set as output */
#define JTAG_GPIO_TMS_DDR_RESET 0x00000000
#define JTAG_GPIO_ADDR_EN_TCK (CONFIG_SYS_MBAR + 0xC00)
#define JTAG_GPIO_TCK_EN_SET 0x20000000 /* Enable for GPIO */
#define JTAG_GPIO_TCK_EN_RESET 0x00000000
#define JTAG_GPIO_ADDR_DDR_TCK (CONFIG_SYS_MBAR + 0xC08)
#define JTAG_GPIO_TCK_DDR_SET 0x20000000 /* Set as output */
#define JTAG_GPIO_TCK_DDR_RESET 0x00000000
#define JTAG_GPIO_ADDR_EN_TDI (CONFIG_SYS_MBAR + 0xC00)
#define JTAG_GPIO_TDI_EN_SET 0x10000000 /* Enable as GPIO */
#define JTAG_GPIO_TDI_EN_RESET 0x00000000
#define JTAG_GPIO_ADDR_DDR_TDI (CONFIG_SYS_MBAR + 0xC08)
#define JTAG_GPIO_TDI_DDR_SET 0x10000000 /* Set as output */
#define JTAG_GPIO_TDI_DDR_RESET 0x00000000
#define JTAG_GPIO_ADDR_EN_TDO (CONFIG_SYS_MBAR + 0xB04)
#define JTAG_GPIO_TDO_EN_SET 0x10000000 /* Enable as GPIO */
#define JTAG_GPIO_TDO_EN_RESET 0x00000000
#define JTAG_GPIO_ADDR_DDR_TDO (CONFIG_SYS_MBAR + 0xB0C)
#define JTAG_GPIO_TDO_DDR_SET 0x00000000
#define JTAG_GPIO_TDO_DDR_RESET 0x10000000 /* Set as input */
#endif /* __CONFIG_H */

2
include/configs/pogo_e02.h
View File

@@ -13,6 +13,8 @@
#ifndef _CONFIG_POGO_E02_H
#define _CONFIG_POGO_E02_H
#define CONFIG_SYS_GENERIC_BOARD
/*
* Machine type definition and ID
*/

10
include/configs/sama5d3_xplained.h
View File

@@ -169,13 +169,14 @@
"bootz 0x22000000 - 0x21000000"
#elif CONFIG_SYS_USE_MMC
/* bootstrap + u-boot + env in sd card */
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_ENV_OFFSET 0x2000
#define CONFIG_ENV_SIZE 0x1000
#define CONFIG_ENV_IS_IN_FAT
#define FAT_ENV_INTERFACE "mmc"
#define FAT_ENV_FILE "uboot.env"
#define FAT_ENV_DEVICE_AND_PART "0"
#define CONFIG_ENV_SIZE 0x4000
#define CONFIG_BOOTCOMMAND "fatload mmc 0:1 0x21000000 at91-sama5d3_xplained.dtb; " \
"fatload mmc 0:1 0x22000000 zImage; " \
"bootz 0x22000000 - 0x21000000"
#define CONFIG_SYS_MMC_ENV_DEV 0
#else
#define CONFIG_ENV_IS_NOWHERE
#endif
@@ -246,6 +247,7 @@
#define CONFIG_SYS_NAND_OOBSIZE 64
#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
#endif

10
include/configs/sama5d3xek.h
View File

@@ -191,6 +191,7 @@
#if defined(CONFIG_CMD_USB) || defined(CONFIG_CMD_MMC)
#define CONFIG_CMD_FAT
#define CONFIG_FAT_WRITE
#endif
#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
@@ -215,13 +216,14 @@
"bootm 0x22000000 - 0x21000000"
#elif CONFIG_SYS_USE_MMC
/* bootstrap + u-boot + env in sd card */
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_ENV_OFFSET 0x2000
#define CONFIG_ENV_SIZE 0x1000
#define CONFIG_ENV_IS_IN_FAT
#define FAT_ENV_INTERFACE "mmc"
#define FAT_ENV_FILE "uboot.env"
#define FAT_ENV_DEVICE_AND_PART "0"
#define CONFIG_ENV_SIZE 0x4000
#define CONFIG_BOOTCOMMAND "fatload mmc 0:1 0x21000000 dtb; " \
"fatload mmc 0:1 0x22000000 uImage; " \
"bootm 0x22000000 - 0x21000000"
#define CONFIG_SYS_MMC_ENV_DEV 0
#else
#define CONFIG_ENV_IS_NOWHERE
#endif

64
include/configs/sama5d4_xplained.h
View File

@@ -20,7 +20,9 @@
#define CONFIG_ARCH_CPU_INIT
#ifndef CONFIG_SPL_BUILD
#define CONFIG_SKIP_LOWLEVEL_INIT
#endif
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_DISPLAY_CPUINFO
@@ -66,8 +68,12 @@
#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS
#define CONFIG_SYS_SDRAM_SIZE 0x20000000
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_INIT_SP_ADDR 0x210000
#else
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
#endif
#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
@@ -121,6 +127,14 @@
#define CONFIG_USB_STORAGE
#endif
/* USB device */
#define CONFIG_USB_GADGET
#define CONFIG_USB_GADGET_DUALSPEED
#define CONFIG_USB_GADGET_ATMEL_USBA
#define CONFIG_USB_ETHER
#define CONFIG_USB_ETH_RNDIS
#define CONFIG_USBNET_MANUFACTURER "Atmel SAMA5D4EK"
#if defined(CONFIG_CMD_USB) || defined(CONFIG_CMD_MMC)
#define CONFIG_CMD_FAT
#define CONFIG_DOS_PARTITION
@@ -213,4 +227,54 @@
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
/* SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE 0x200000
#define CONFIG_SPL_MAX_SIZE 0x10000
#define CONFIG_SPL_BSS_START_ADDR 0x20000000
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_GPIO_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SYS_MONITOR_LEN (512 << 10)
#ifdef CONFIG_SYS_USE_MMC
#define CONFIG_SPL_LDSCRIPT arch/arm/cpu/at91-common/u-boot-spl.lds
#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#define CONFIG_SPL_FAT_SUPPORT
#define CONFIG_SPL_LIBDISK_SUPPORT
#elif CONFIG_SYS_USE_NANDFLASH
#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_BASE
#define CONFIG_PMECC_CAP 8
#define CONFIG_PMECC_SECTOR_SIZE 512
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_SIZE 0x1000
#define CONFIG_SYS_NAND_PAGE_COUNT 64
#define CONFIG_SYS_NAND_OOBSIZE 224
#define CONFIG_SYS_NAND_BLOCK_SIZE 0x40000
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
#elif CONFIG_SYS_USE_SERIALFLASH
#define CONFIG_SPL_SPI_SUPPORT
#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
#endif
#endif

64
include/configs/sama5d4ek.h
View File

@@ -20,7 +20,9 @@
#define CONFIG_ARCH_CPU_INIT
#ifndef CONFIG_SPL_BUILD
#define CONFIG_SKIP_LOWLEVEL_INIT
#endif
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_DISPLAY_CPUINFO
@@ -66,8 +68,12 @@
#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS
#define CONFIG_SYS_SDRAM_SIZE 0x20000000
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_INIT_SP_ADDR 0x210000
#else
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
#endif
#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
@@ -121,6 +127,14 @@
#define CONFIG_USB_STORAGE
#endif
/* USB device */
#define CONFIG_USB_GADGET
#define CONFIG_USB_GADGET_DUALSPEED
#define CONFIG_USB_GADGET_ATMEL_USBA
#define CONFIG_USB_ETHER
#define CONFIG_USB_ETH_RNDIS
#define CONFIG_USBNET_MANUFACTURER "Atmel SAMA5D4EK"
#if defined(CONFIG_CMD_USB) || defined(CONFIG_CMD_MMC)
#define CONFIG_CMD_FAT
#define CONFIG_DOS_PARTITION
@@ -211,4 +225,54 @@
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
/* SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE 0x200000
#define CONFIG_SPL_MAX_SIZE 0x10000
#define CONFIG_SPL_BSS_START_ADDR 0x20000000
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_GPIO_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SYS_MONITOR_LEN (512 << 10)
#ifdef CONFIG_SYS_USE_MMC
#define CONFIG_SPL_LDSCRIPT arch/arm/cpu/at91-common/u-boot-spl.lds
#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#define CONFIG_SPL_FAT_SUPPORT
#define CONFIG_SPL_LIBDISK_SUPPORT
#elif CONFIG_SYS_USE_NANDFLASH
#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_BASE
#define CONFIG_PMECC_CAP 8
#define CONFIG_PMECC_SECTOR_SIZE 512
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_SIZE 0x1000
#define CONFIG_SYS_NAND_PAGE_COUNT 64
#define CONFIG_SYS_NAND_OOBSIZE 224
#define CONFIG_SYS_NAND_BLOCK_SIZE 0x40000
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
#elif CONFIG_SYS_USE_SERIALFLASH
#define CONFIG_SPL_SPI_SUPPORT
#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
#endif
#endif

4
include/configs/sandbox.h
View File

@@ -23,7 +23,6 @@
#define CONFIG_BOOTSTAGE
#define CONFIG_BOOTSTAGE_REPORT
#define CONFIG_DM
#define CONFIG_CMD_DEMO
#define CONFIG_CMD_DM
#define CONFIG_DM_DEMO
@@ -41,9 +40,6 @@
#define CONFIG_OF_LIBFDT
#define CONFIG_LMB
#define CONFIG_FIT
#define CONFIG_FIT_SIGNATURE
#define CONFIG_RSA
#define CONFIG_CMD_FDT
#define CONFIG_ANDROID_BOOT_IMAGE

9
include/configs/sheevaplug.h
View File

@@ -10,6 +10,8 @@
#ifndef _CONFIG_SHEEVAPLUG_H
#define _CONFIG_SHEEVAPLUG_H
#define CONFIG_SYS_GENERIC_BOARD
/*
* Version number information
*/
@@ -30,6 +32,11 @@
#define CONFIG_LZMA
#define CONFIG_LZO
/*
* Enable device tree support
*/
#define CONFIG_OF_LIBFDT
/*
* Miscellaneous configurable options
*/
@@ -49,6 +56,7 @@
#define CONFIG_CMD_NAND
#define CONFIG_CMD_PING
#define CONFIG_CMD_USB
/*
* mv-common.h should be defined after CMD configs since it used them
* to enable certain macros
@@ -139,6 +147,5 @@
#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
#define CONFIG_MTD_PARTITIONS
#define CONFIG_CMD_MTDPARTS
#define CONFIG_LZO
#endif /* _CONFIG_SHEEVAPLUG_H */

2
include/configs/smdk5250.h
View File

@@ -18,6 +18,8 @@
#include <configs/exynos5250-common.h>
/* PMIC */
#define CONFIG_POWER_MAX77686
#define CONFIG_BOARD_COMMON
#define CONFIG_ARCH_EARLY_INIT_R

1
include/configs/snapper9260.h
View File

@@ -34,7 +34,6 @@
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SKIP_RELOCATE_UBOOT
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_FIT

1
include/configs/snow.h
View File

@@ -22,6 +22,7 @@
#define CONFIG_CROS_EC_I2C /* Support CROS_EC over I2C */
#define CONFIG_POWER_TPS65090_I2C
#define CONFIG_DM_CROS_EC
#define CONFIG_BOARD_COMMON
#define CONFIG_ARCH_EARLY_INIT_R

1
include/configs/sun4i.h
View File

@@ -13,7 +13,6 @@
*/
#define CONFIG_CLK_FULL_SPEED 1008000000
#define CONFIG_SYS_PROMPT "sun4i# "
#define CONFIG_MACH_TYPE 4104
#ifdef CONFIG_USB_EHCI

1
include/configs/sun5i.h
View File

@@ -13,7 +13,6 @@
*/
#define CONFIG_CLK_FULL_SPEED 1008000000
#define CONFIG_SYS_PROMPT "sun5i# "
#define CONFIG_MACH_TYPE 4138
#ifdef CONFIG_USB_EHCI

2
include/configs/sun6i.h
View File

@@ -16,8 +16,6 @@
*/
#define CONFIG_CLK_FULL_SPEED 1008000000
#define CONFIG_SYS_PROMPT "sun6i# "
#ifdef CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_SUNXI
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2

1
include/configs/sun7i.h
View File

@@ -14,7 +14,6 @@
*/
#define CONFIG_CLK_FULL_SPEED 912000000
#define CONFIG_SYS_PROMPT "sun7i# "
#define CONFIG_MACH_TYPE 4283
#ifdef CONFIG_USB_EHCI

2
include/configs/sun8i.h
View File

@@ -14,8 +14,6 @@
*/
#define CONFIG_CLK_FULL_SPEED 1008000000
#define CONFIG_SYS_PROMPT "sun8i# "
#ifdef CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_SUNXI
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1

18
include/configs/sunxi-common.h
View File

@@ -40,6 +40,8 @@
*/
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_SYS_PROMPT "sunxi# "
/* Serial & console */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
@@ -83,6 +85,9 @@
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_SETEXPR
#define CONFIG_PARTITION_UUIDS
#define CONFIG_CMD_PART
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_CMDLINE_TAG
#define CONFIG_INITRD_TAG
@@ -179,7 +184,10 @@
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00080000 /* 512 KiB */
/* I2C */
#if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER
#define CONFIG_SPL_I2C_SUPPORT
#endif
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MVTWSI
#define CONFIG_SYS_I2C_SPEED 400000
@@ -247,8 +255,16 @@
#endif
#ifdef CONFIG_USB_EHCI
#define CONFIG_CMD_USB
#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
#endif
#ifdef CONFIG_USB_MUSB_SUNXI
#define CONFIG_MUSB_HOST
#define CONFIG_MUSB_PIO_ONLY
#endif
#if defined CONFIG_USB_EHCI || defined CONFIG_USB_MUSB_SUNXI
#define CONFIG_CMD_USB
#define CONFIG_USB_STORAGE
#endif

32
include/configs/taurus.h
View File

@@ -21,11 +21,13 @@
*/
#include <asm/hardware.h>
#define MACH_TYPE_TAURUS 2067
#define MACH_TYPE_AXM 2068
#define CONFIG_SYS_GENERIC_BOARD
#if defined(CONFIG_SPL_BUILD)
#define CONFIG_SYS_THUMB_BUILD
#define CONFIG_SYS_ICACHE_OFF
#define CONFIG_SYS_DCACHE_OFF
#endif
/*
* Warning: changing CONFIG_SYS_TEXT_BASE requires
* adapting the initial boot program.
@@ -116,6 +118,12 @@
#define CONFIG_RMII
#define CONFIG_AT91_WANTS_COMMON_PHY
#define CONFIG_AT91SAM9_WATCHDOG
#if !defined(CONFIG_SPL_BUILD)
/* Enable the watchdog */
#define CONFIG_HW_WATCHDOG
#endif
/* USB */
#if defined(CONFIG_BOARD_TAURUS)
#define CONFIG_USB_ATMEL
@@ -137,6 +145,19 @@
#define TAURUS_SPI_MASK (1 << 4)
#define TAURUS_SPI_CS_PIN AT91_PIN_PA3
#if defined(CONFIG_SPL_BUILD)
/* SPL related */
#undef CONFIG_SPL_OS_BOOT /* Not supported by existing map */
#define CONFIG_SPL_SPI_SUPPORT
#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
#define CONFIG_SF_DEFAULT_BUS 0
#define CONFIG_SF_DEFAULT_SPEED 10000000
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
#endif
/* load address */
#define CONFIG_SYS_LOAD_ADDR 0x22000000
@@ -171,8 +192,11 @@
/* Defines for SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE 0x0
#define CONFIG_SPL_MAX_SIZE (11 * 1024)
#define CONFIG_SPL_MAX_SIZE (14 * 1024)
#define CONFIG_SPL_STACK (16 * 1024)
#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \
CONFIG_SYS_MALLOC_LEN)
#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN
#define CONFIG_SPL_BSS_START_ADDR CONFIG_SPL_MAX_SIZE
#define CONFIG_SPL_BSS_MAX_SIZE (3 * 1024)

10
include/configs/tb100.h
View File

@@ -12,21 +12,11 @@
/*
* CPU configuration
*/
#define CONFIG_ARC700
#define CONFIG_ARC_MMU_VER 3
#define CONFIG_SYS_CACHELINE_SIZE 32
#define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ
/*
* Board configuration
*/
#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_ARCH_EARLY_INIT_R
/*
* Memory configuration
*/
#define CONFIG_SYS_TEXT_BASE 0x84000000
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000

2
include/configs/ti_am335x_common.h
View File

@@ -20,7 +20,9 @@
#define CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC
#ifndef CONFIG_SPL_BUILD
#ifndef CONFIG_DM
# define CONFIG_DM
#endif
# define CONFIG_CMD_DM
# define CONFIG_DM_GPIO
# define CONFIG_DM_SERIAL

22
include/configs/uniphier.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (C) 2012-2014 Panasonic Corporation
* Copyright (C) 2012-2015 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
@@ -43,6 +43,9 @@
#define CONFIG_SDRAM1_SIZE 0x10000000
#endif
#define CONFIG_I2C_EEPROM
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
/*
* Support card address map
*/
@@ -92,6 +95,8 @@
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_MISC_INIT_F
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_EARLY_INIT_R
#define CONFIG_BOARD_LATE_INIT
@@ -232,11 +237,16 @@
"image_offset=0x00080000\0" \
"image_size=0x00f00000\0" \
"verify=n\0" \
"norboot=run add_default_bootargs;" \
"nandupdate=nand erase 0 0x100000 &&" \
"tftpboot u-boot-spl.bin &&" \
"nand write $loadaddr 0 0x10000 &&" \
"tftpboot u-boot-dtb.img &&" \
"nand write $loadaddr 0x10000 0xf0000\0" \
"norboot=run add_default_bootargs &&" \
"bootm $image_offset\0" \
"nandboot=run add_default_bootargs;" \
"nand read $loadaddr $image_offset $image_size;" \
"bootm\0" \
"nandboot=run add_default_bootargs &&" \
"nand read $loadaddr $image_offset $image_size &&" \
"bootm\0" \
"add_default_bootargs=setenv bootargs $bootargs" \
" console=ttyS0,$baudrate\0" \
@@ -266,8 +276,6 @@
#define CONFIG_SPL_TEXT_BASE 0x00100000
#endif
#define CONFIG_BOARD_POSTCLK_INIT
#ifndef CONFIG_SPL_BUILD
#define CONFIG_SKIP_LOWLEVEL_INIT
#endif

33
include/configs/vexpress_aemv8a.h
View File

@@ -11,9 +11,9 @@
/* We use generic board for v8 Versatile Express */
#define CONFIG_SYS_GENERIC_BOARD
#ifdef CONFIG_BASE_FVP
#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP
#ifndef CONFIG_SEMIHOSTING
#error CONFIG_BASE_FVP requires CONFIG_SEMIHOSTING
#error CONFIG_TARGET_VEXPRESS64_BASE_FVP requires CONFIG_SEMIHOSTING
#endif
#define CONFIG_BOARD_LATE_INIT
#define CONFIG_ARMV8_SWITCH_TO_EL1
@@ -21,8 +21,9 @@
#define CONFIG_REMAKE_ELF
#ifndef CONFIG_BASE_FVP
/* Base FVP not using GICv3 yet */
#if !defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP) && \
!defined(CONFIG_TARGET_VEXPRESS64_JUNO)
/* Base FVP and Juno not using GICv3 yet */
#define CONFIG_GICV3
#endif
@@ -40,10 +41,13 @@
#define CONFIG_BOOTP_VCI_STRING "U-boot.armv8.vexpress_aemv8a"
/* Link Definitions */
#ifdef CONFIG_BASE_FVP
#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP
/* ATF loads u-boot here for BASE_FVP model */
#define CONFIG_SYS_TEXT_BASE 0x88000000
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x03f00000)
#elif CONFIG_TARGET_VEXPRESS64_JUNO
#define CONFIG_SYS_TEXT_BASE 0xe0000000
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
#else
#define CONFIG_SYS_TEXT_BASE 0x80000000
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
@@ -54,7 +58,7 @@
/* SMP Spin Table Definitions */
#ifdef CONFIG_BASE_FVP
#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP
#define CPU_RELEASE_ADDR (CONFIG_SYS_SDRAM_BASE + 0x03f00000)
#else
#define CPU_RELEASE_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
@@ -88,10 +92,15 @@
#define V2M_KMI0 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(6))
#define V2M_KMI1 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(7))
#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
#define V2M_UART0 0x7ff80000
#define V2M_UART1 0x7ff70000
#else /* Not Juno */
#define V2M_UART0 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(9))
#define V2M_UART1 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(10))
#define V2M_UART2 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(11))
#define V2M_UART3 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(12))
#endif
#define V2M_WDT (V2M_PA_CS3 + V2M_PERIPH_OFFSET(15))
@@ -119,9 +128,12 @@
#define GICR_BASE (0x2f100000)
#else
#ifdef CONFIG_BASE_FVP
#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP
#define GICD_BASE (0x2f000000)
#define GICC_BASE (0x2c000000)
#elif CONFIG_TARGET_VEXPRESS64_JUNO
#define GICD_BASE (0x2C010000)
#define GICC_BASE (0x2C02f000)
#else
#define GICD_BASE (0x2C001000)
#define GICC_BASE (0x2C002000)
@@ -140,7 +152,11 @@
/* PL011 Serial Configuration */
#define CONFIG_PL011_SERIAL
#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
#define CONFIG_PL011_CLOCK 7273800
#else
#define CONFIG_PL011_CLOCK 24000000
#endif
#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \
(void *)CONFIG_SYS_SERIAL1}
#define CONFIG_CONS_INDEX 0
@@ -161,6 +177,7 @@
#define CONFIG_CMD_ENV
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_IMI
#define CONFIG_CMD_LOADB
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_MII
#define CONFIG_CMD_NET
@@ -191,7 +208,7 @@
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
/* Initial environment variables */
#ifdef CONFIG_BASE_FVP
#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP
#define CONFIG_EXTRA_ENV_SETTINGS \
"kernel_name=uImage\0" \
"kernel_addr_r=0x80000000\0" \

2
include/configs/vexpress_common.h
View File

@@ -122,7 +122,7 @@
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_SYS_L2CACHE_OFF 1
#define CONFIG_INITRD_TAG 1
#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_OF_LIBFDT 1
/* Size of malloc() pool */

6
include/configs/x86-common.h
View File

@@ -39,7 +39,6 @@
/* SATA AHCI storage */
#define CONFIG_SCSI_AHCI
#define CONFIG_SATA_INTEL
#ifdef CONFIG_SCSI_AHCI
#define CONFIG_LIBATA
#define CONFIG_SYS_64BIT_LBA
@@ -179,6 +178,7 @@
#define VIDEO_FB_16BPP_WORD_SWAP
#define CONFIG_I8042_KBD
#define CONFIG_CFB_CONSOLE
#define CONFIG_CONSOLE_SCROLL_LINES 5
/*-----------------------------------------------------------------------
* CPU Features
@@ -210,6 +210,7 @@
#define CONFIG_CMD_SF_TEST
#define CONFIG_CMD_SPI
#define CONFIG_SPI
#define CONFIG_OF_SPI_FLASH
/*-----------------------------------------------------------------------
* Environment configuration
@@ -243,6 +244,9 @@
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTSTAGE
#define CONFIG_CMD_BOOTSTAGE
#define CONFIG_CMD_USB
#define CONFIG_EXTRA_ENV_SETTINGS \

83
include/configs/zynq-common.h
View File

@@ -47,6 +47,17 @@
# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
# define CONFIG_PHYLIB
# define CONFIG_PHY_MARVELL
# define CONFIG_BOOTP_SERVERIP
# define CONFIG_BOOTP_BOOTPATH
# define CONFIG_BOOTP_GATEWAY
# define CONFIG_BOOTP_HOSTNAME
# define CONFIG_BOOTP_MAY_FAIL
# if !defined(CONFIG_ZYNQ_GEM_EMIO0)
# define CONFIG_ZYNQ_GEM_EMIO0 0
# endif
# if !defined(CONFIG_ZYNQ_GEM_EMIO1)
# define CONFIG_ZYNQ_GEM_EMIO1 0
# endif
#endif
/* SPI */
@@ -90,6 +101,55 @@
# define CONFIG_USB_ULPI
# define CONFIG_EHCI_IS_TDI
# define CONFIG_USB_MAX_CONTROLLER_COUNT 2
# define CONFIG_CI_UDC /* ChipIdea CI13xxx UDC */
# define CONFIG_USB_GADGET
# define CONFIG_USB_GADGET_DUALSPEED
# define CONFIG_USBDOWNLOAD_GADGET
# define CONFIG_SYS_DFU_DATA_BUF_SIZE 0x600000
# define DFU_DEFAULT_POLL_TIMEOUT 300
# define CONFIG_DFU_FUNCTION
# define CONFIG_DFU_RAM
# define CONFIG_USB_GADGET_VBUS_DRAW 2
# define CONFIG_G_DNL_VENDOR_NUM 0x03FD
# define CONFIG_G_DNL_PRODUCT_NUM 0x0300
# define CONFIG_G_DNL_MANUFACTURER "Xilinx"
# define CONFIG_USB_GADGET
# define CONFIG_USB_CABLE_CHECK
# define CONFIG_CMD_DFU
# define CONFIG_CMD_THOR_DOWNLOAD
# define CONFIG_THOR_FUNCTION
# define DFU_ALT_INFO_RAM \
"dfu_ram_info=" \
"set dfu_alt_info " \
"${kernel_image} ram 0x3000000 0x500000\\\\;" \
"${devicetree_image} ram 0x2A00000 0x20000\\\\;" \
"${ramdisk_image} ram 0x2000000 0x600000\0" \
"dfu_ram=run dfu_ram_info && dfu 0 ram 0\0" \
"thor_ram=run dfu_ram_info && thordown 0 ram 0\0"
# if defined(CONFIG_ZYNQ_SDHCI0) || defined(CONFIG_ZYNQ_SDHCI1)
# define CONFIG_DFU_MMC
# define DFU_ALT_INFO_MMC \
"dfu_mmc_info=" \
"set dfu_alt_info " \
"${kernel_image} fat 0 1\\\\;" \
"${devicetree_image} fat 0 1\\\\;" \
"${ramdisk_image} fat 0 1\0" \
"dfu_mmc=run dfu_mmc_info && dfu 0 mmc 0\0" \
"thor_mmc=run dfu_mmc_info && thordown 0 mmc 0\0"
# define DFU_ALT_INFO \
DFU_ALT_INFO_RAM \
DFU_ALT_INFO_MMC
# else
# define DFU_ALT_INFO \
DFU_ALT_INFO_RAM
# endif
#endif
#if !defined(DFU_ALT_INFO)
# define DFU_ALT_INFO
#endif
#if defined(CONFIG_ZYNQ_SDHCI) || defined(CONFIG_ZYNQ_USB)
@@ -100,6 +160,7 @@
# define CONFIG_DOS_PARTITION
# define CONFIG_CMD_EXT4
# define CONFIG_CMD_EXT4_WRITE
# define CONFIG_CMD_FS_GENERIC
#endif
#define CONFIG_SYS_I2C_ZYNQ
@@ -121,12 +182,6 @@
# define CONFIG_SYS_EEPROM_SIZE 1024 /* Bytes */
#endif
#define CONFIG_BOOTP_SERVERIP
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_MAY_FAIL
/* Total Size of Environment Sector */
#define CONFIG_ENV_SIZE (128 << 10)
@@ -159,16 +214,17 @@
"cp.b ${nor_flash_off} ${load_addr} ${fit_size} && " \
"bootm ${load_addr}\0" \
"sdboot=echo Copying FIT from SD to RAM... && " \
"fatload mmc 0 ${load_addr} ${fit_image} && " \
"load mmc 0 ${load_addr} ${fit_image} && " \
"bootm ${load_addr}\0" \
"jtagboot=echo TFTPing FIT to RAM... && " \
"tftpboot ${load_addr} ${fit_image} && " \
"bootm ${load_addr}\0" \
"usbboot=if usb start; then " \
"echo Copying FIT from USB to RAM... && " \
"fatload usb 0 ${load_addr} ${fit_image} && " \
"load usb 0 ${load_addr} ${fit_image} && " \
"bootm ${load_addr}\0" \
"fi\0"
"fi\0" \
DFU_ALT_INFO
#define CONFIG_BOOTCOMMAND "run $modeboot"
#define CONFIG_BOOTDELAY 3 /* -1 to Disable autoboot */
@@ -181,6 +237,7 @@
#define CONFIG_CMDLINE_EDITING
#define CONFIG_AUTO_COMPLETE
#define CONFIG_BOARD_LATE_INIT
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SYS_LONGHELP
#define CONFIG_CLOCKS
#define CONFIG_CMD_CLK
@@ -198,7 +255,7 @@
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x1000)
#define CONFIG_SYS_MALLOC_LEN 0x400000
#define CONFIG_SYS_MALLOC_LEN 0xC00000
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
@@ -219,17 +276,11 @@
#define CONFIG_OF_LIBFDT
/* FIT support */
#define CONFIG_FIT
#define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */
#define CONFIG_IMAGE_FORMAT_LEGACY /* enable also legacy image format */
/* FDT support */
#define CONFIG_DISPLAY_BOARDINFO_LATE
/* RSA support */
#define CONFIG_FIT_SIGNATURE
#define CONFIG_RSA
/* Extend size of kernel image for uncompression */
#define CONFIG_SYS_BOOTM_LEN (60 * 1024 * 1024)

3
include/cros_ec.h
View File

@@ -13,6 +13,7 @@
#include <ec_commands.h>
#include <fdtdec.h>
#include <cros_ec_message.h>
#include <asm/gpio.h>
#ifndef CONFIG_DM_CROS_EC
/* Which interface is the device on? */
@@ -39,7 +40,7 @@ struct cros_ec_dev {
unsigned int bus_num; /* Bus number (for I2C) */
unsigned int max_frequency; /* Maximum interface frequency */
#endif
struct fdt_gpio_state ec_int; /* GPIO used as EC interrupt line */
struct gpio_desc ec_int; /* GPIO used as EC interrupt line */
int protocol_version; /* Protocol version to use */
int optimise_flash_write; /* Don't write erased flash blocks */

4
include/dm-demo.h
View File

@@ -25,10 +25,14 @@ struct dm_demo_pdata {
struct demo_ops {
int (*hello)(struct udevice *dev, int ch);
int (*status)(struct udevice *dev, int *status);
int (*set_light)(struct udevice *dev, int light);
int (*get_light)(struct udevice *dev);
};
int demo_hello(struct udevice *dev, int ch);
int demo_status(struct udevice *dev, int *status);
int demo_set_light(struct udevice *dev, int light);
int demo_get_light(struct udevice *dev);
int demo_list(void);
int demo_parse_dt(struct udevice *dev);

29
include/dm/device.h
View File

@@ -26,6 +26,9 @@ struct driver_info;
/* DM should init this device prior to relocation */
#define DM_FLAG_PRE_RELOC (1 << 2)
/* DM is responsible for allocating and freeing parent_platdata */
#define DM_FLAG_ALLOC_PARENT_PDATA (1 << 3)
/**
* struct udevice - An instance of a driver
*
@@ -46,6 +49,7 @@ struct driver_info;
* @driver: The driver used by this device
* @name: Name of device, typically the FDT node name
* @platdata: Configuration data for this device
* @parent_platdata: The parent bus's configuration data for this device
* @of_offset: Device tree node offset for this device (- for none)
* @of_id: Pointer to the udevice_id structure which created the device
* @parent: Parent of this device, or NULL for the top level device
@@ -65,6 +69,7 @@ struct udevice {
struct driver *driver;
const char *name;
void *platdata;
void *parent_platdata;
int of_offset;
const struct udevice_id *of_id;
struct udevice *parent;
@@ -127,6 +132,7 @@ struct udevice_id {
* @remove: Called to remove a device, i.e. de-activate it
* @unbind: Called to unbind a device from its driver
* @ofdata_to_platdata: Called before probe to decode device tree data
* @child_post_bind: Called after a new child has been bound
* @child_pre_probe: Called before a child device is probed. The device has
* memory allocated but it has not yet been probed.
* @child_post_remove: Called after a child device is removed. The device
@@ -146,6 +152,9 @@ struct udevice_id {
* device_probe_child() pass it in. So far the use case for allocating it
* is SPI, but I found that unsatisfactory. Since it is here I will leave it
* until things are clearer.
* @per_child_platdata_auto_alloc_size: A bus likes to store information about
* its children. If non-zero this is the size of this data, to be allocated
* in the child's parent_platdata pointer.
* @ops: Driver-specific operations. This is typically a list of function
* pointers defined by the driver, to implement driver functions required by
* the uclass.
@@ -160,11 +169,13 @@ struct driver {
int (*remove)(struct udevice *dev);
int (*unbind)(struct udevice *dev);
int (*ofdata_to_platdata)(struct udevice *dev);
int (*child_post_bind)(struct udevice *dev);
int (*child_pre_probe)(struct udevice *dev);
int (*child_post_remove)(struct udevice *dev);
int priv_auto_alloc_size;
int platdata_auto_alloc_size;
int per_child_auto_alloc_size;
int per_child_platdata_auto_alloc_size;
const void *ops; /* driver-specific operations */
uint32_t flags;
};
@@ -183,6 +194,16 @@ struct driver {
*/
void *dev_get_platdata(struct udevice *dev);
/**
* dev_get_parent_platdata() - Get the parent platform data for a device
*
* This checks that dev is not NULL, but no other checks for now
*
* @dev Device to check
* @return parent's platform data, or NULL if none
*/
void *dev_get_parent_platdata(struct udevice *dev);
/**
* dev_get_parentdata() - Get the parent data for a device
*
@@ -224,6 +245,14 @@ struct udevice *dev_get_parent(struct udevice *child);
*/
ulong dev_get_of_data(struct udevice *dev);
/*
* device_get_uclass_id() - return the uclass ID of a device
*
* @dev: Device to check
* @return uclass ID for the device
*/
enum uclass_id device_get_uclass_id(struct udevice *dev);
/**
* device_get_child() - Get the child of a device by index
*

3
include/dm/test.h
View File

@@ -67,6 +67,8 @@ enum {
struct dm_test_priv {
int ping_total;
int op_count[DM_TEST_OP_COUNT];
int uclass_flag;
int uclass_total;
};
/**
@@ -88,6 +90,7 @@ struct dm_test_uclass_priv {
*
* @sum: Test value used to check parent data works correctly
* @flag: Used to track calling of parent operations
* @uclass_flag: Used to track calling of parent operations by uclass
*/
struct dm_test_parent_data {
int sum;

1
include/dm/uclass-id.h
View File

@@ -33,6 +33,7 @@ enum uclass_id {
UCLASS_I2C, /* I2C bus */
UCLASS_I2C_GENERIC, /* Generic I2C device */
UCLASS_I2C_EEPROM, /* I2C EEPROM device */
UCLASS_MOD_EXP, /* RSA Mod Exp device */
UCLASS_COUNT,
UCLASS_INVALID = -1,

11
include/dm/uclass-internal.h
View File

@@ -43,6 +43,17 @@ int uclass_bind_device(struct udevice *dev);
*/
int uclass_unbind_device(struct udevice *dev);
/**
* uclass_pre_probe_child() - Deal with a child that is about to be probed
*
* Perform any pre-processing that is needed by the uclass before it can be
* probed.
*
* @dev: Pointer to the device
* #return 0 on success, -ve on error
*/
int uclass_pre_probe_child(struct udevice *dev);
/**
* uclass_post_probe_device() - Deal with a device that has just been probed
*

21
include/dm/uclass.h
View File

@@ -40,6 +40,9 @@ struct uclass {
struct udevice;
/* Members of this uclass sequence themselves with aliases */
#define DM_UC_FLAG_SEQ_ALIAS (1 << 0)
/**
* struct uclass_driver - Driver for the uclass
*
@@ -52,6 +55,7 @@ struct udevice;
* @pre_unbind: Called before a device is unbound from this uclass
* @post_probe: Called after a new device is probed
* @pre_remove: Called before a device is removed
* @child_post_bind: Called after a child is bound to a device in this uclass
* @init: Called to set up the uclass
* @destroy: Called to destroy the uclass
* @priv_auto_alloc_size: If non-zero this is the size of the private data
@@ -60,8 +64,16 @@ struct udevice;
* @per_device_auto_alloc_size: Each device can hold private data owned
* by the uclass. If required this will be automatically allocated if this
* value is non-zero.
* @per_child_auto_alloc_size: Each child device (of a parent in this
* uclass) can hold parent data for the device/uclass. This value is only
* used as a falback if this member is 0 in the driver.
* @per_child_platdata_auto_alloc_size: A bus likes to store information about
* its children. If non-zero this is the size of this data, to be allocated
* in the child device's parent_platdata pointer. This value is only used as
* a falback if this member is 0 in the driver.
* @ops: Uclass operations, providing the consistent interface to devices
* within the uclass.
* @flags: Flags for this uclass (DM_UC_...)
*/
struct uclass_driver {
const char *name;
@@ -70,11 +82,16 @@ struct uclass_driver {
int (*pre_unbind)(struct udevice *dev);
int (*post_probe)(struct udevice *dev);
int (*pre_remove)(struct udevice *dev);
int (*child_post_bind)(struct udevice *dev);
int (*child_pre_probe)(struct udevice *dev);
int (*init)(struct uclass *class);
int (*destroy)(struct uclass *class);
int priv_auto_alloc_size;
int per_device_auto_alloc_size;
int per_child_auto_alloc_size;
int per_child_platdata_auto_alloc_size;
const void *ops;
uint32_t flags;
};
/* Declare a new uclass_driver */
@@ -141,6 +158,8 @@ int uclass_get_device_by_of_offset(enum uclass_id id, int node,
/**
* uclass_first_device() - Get the first device in a uclass
*
* The device returned is probed if necessary, and ready for use
*
* @id: Uclass ID to look up
* @devp: Returns pointer to the first device in that uclass, or NULL if none
* @return 0 if OK (found or not found), -1 on error
@@ -150,6 +169,8 @@ int uclass_first_device(enum uclass_id id, struct udevice **devp);
/**
* uclass_next_device() - Get the next device in a uclass
*
* The device returned is probed if necessary, and ready for use
*
* @devp: On entry, pointer to device to lookup. On exit, returns pointer
* to the next device in the same uclass, or NULL if none
* @return 0 if OK (found or not found), -1 on error

83
include/dt-bindings/mrc/quark.h Normal file
View File

@@ -0,0 +1,83 @@
/*
* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*
* Intel Quark MRC bindings include several properties
* as part of an Intel Quark MRC node. In most cases,
* the value of these properties uses the standard values
* defined in this header.
*/
#ifndef _DT_BINDINGS_QRK_MRC_H_
#define _DT_BINDINGS_QRK_MRC_H_
/* MRC platform data flags */
#define MRC_FLAG_ECC_EN 0x00000001
#define MRC_FLAG_SCRAMBLE_EN 0x00000002
#define MRC_FLAG_MEMTEST_EN 0x00000004
/* 0b DDR "fly-by" topology else 1b DDR "tree" topology */
#define MRC_FLAG_TOP_TREE_EN 0x00000008
/* If set ODR signal is asserted to DRAM devices on writes */
#define MRC_FLAG_WR_ODT_EN 0x00000010
/* DRAM width */
#define DRAM_WIDTH_X8 0
#define DRAM_WIDTH_X16 1
#define DRAM_WIDTH_X32 2
/* DRAM speed */
#define DRAM_FREQ_800 0
#define DRAM_FREQ_1066 1
/* DRAM type */
#define DRAM_TYPE_DDR3 0
#define DRAM_TYPE_DDR3L 1
/* DRAM rank mask */
#define DRAM_RANK(n) (1 << (n))
/* DRAM channel mask */
#define DRAM_CHANNEL(n) (1 << (n))
/* DRAM channel width */
#define DRAM_CHANNEL_WIDTH_X8 0
#define DRAM_CHANNEL_WIDTH_X16 1
#define DRAM_CHANNEL_WIDTH_X32 2
/* DRAM address mode */
#define DRAM_ADDR_MODE0 0
#define DRAM_ADDR_MODE1 1
#define DRAM_ADDR_MODE2 2
/* DRAM refresh rate */
#define DRAM_REFRESH_RATE_195US 1
#define DRAM_REFRESH_RATE_39US 2
#define DRAM_REFRESH_RATE_785US 3
/* DRAM SR temprature range */
#define DRAM_SRT_RANGE_NORMAL 0
#define DRAM_SRT_RANGE_EXTENDED 1
/* DRAM ron value */
#define DRAM_RON_34OHM 0
#define DRAM_RON_40OHM 1
/* DRAM rtt nom value */
#define DRAM_RTT_NOM_40OHM 0
#define DRAM_RTT_NOM_60OHM 1
#define DRAM_RTT_NOM_120OHM 2
/* DRAM rd odt value */
#define DRAM_RD_ODT_OFF 0
#define DRAM_RD_ODT_60OHM 1
#define DRAM_RD_ODT_120OHM 2
#define DRAM_RD_ODT_180OHM 3
/* DRAM density */
#define DRAM_DENSITY_512M 0
#define DRAM_DENSITY_1G 1
#define DRAM_DENSITY_2G 2
#define DRAM_DENSITY_4G 3
#endif /* _DT_BINDINGS_QRK_MRC_H_ */

22
include/exports.h
View File

@@ -3,6 +3,8 @@
#ifndef __ASSEMBLY__
struct spi_slave;
/* These are declarations of exported functions available in C code */
unsigned long get_version(void);
int getc(void);
@@ -10,22 +12,23 @@ int tstc(void);
void putc(const char);
void puts(const char*);
int printf(const char* fmt, ...);
void install_hdlr(int, void (*interrupt_handler_t)(void *), void*);
void install_hdlr(int, interrupt_handler_t, void*);
void free_hdlr(int);
void *malloc(size_t);
void free(void*);
void __udelay(unsigned long);
unsigned long get_timer(unsigned long);
int vprintf(const char *, va_list);
unsigned long simple_strtoul(const char *cp,char **endp,unsigned int base);
unsigned long simple_strtoul(const char *cp, char **endp, unsigned int base);
int strict_strtoul(const char *cp, unsigned int base, unsigned long *res);
char *getenv (const char *name);
int setenv (const char *varname, const char *varvalue);
long simple_strtol(const char *cp,char **endp,unsigned int base);
int strcmp(const char * cs,const char * ct);
long simple_strtol(const char *cp, char **endp, unsigned int base);
int strcmp(const char *cs, const char *ct);
unsigned long ustrtoul(const char *cp, char **endp, unsigned int base);
unsigned long long ustrtoull(const char *cp, char **endp, unsigned int base);
#if defined(CONFIG_CMD_I2C)
#if defined(CONFIG_CMD_I2C) && \
(!defined(CONFIG_DM_I2C) || defined(CONFIG_DM_I2C_COMPAT))
int i2c_write (uchar, uint, int , uchar* , int);
int i2c_read (uchar, uint, int , uchar* , int);
#endif
@@ -34,15 +37,14 @@ void app_startup(char * const *);
#endif /* ifndef __ASSEMBLY__ */
enum {
#define EXPORT_FUNC(x) XF_ ## x ,
struct jt_funcs {
#define EXPORT_FUNC(impl, res, func, ...) res(*func)(__VA_ARGS__);
#include <_exports.h>
#undef EXPORT_FUNC
XF_MAX
};
#define XF_VERSION 6
#define XF_VERSION 7
#if defined(CONFIG_X86)
extern gd_t *global_data;

81
include/exynos_lcd.h Normal file
View File

@@ -0,0 +1,81 @@
/*
* exynos_lcd.h - Exynos LCD Controller structures
*
* (C) Copyright 2001
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _EXYNOS_LCD_H_
#define _EXYNOS_LCD_H_
enum {
FIMD_RGB_INTERFACE = 1,
FIMD_CPU_INTERFACE = 2,
};
enum exynos_fb_rgb_mode_t {
MODE_RGB_P = 0,
MODE_BGR_P = 1,
MODE_RGB_S = 2,
MODE_BGR_S = 3,
};
typedef struct vidinfo {
ushort vl_col; /* Number of columns (i.e. 640) */
ushort vl_row; /* Number of rows (i.e. 480) */
ushort vl_width; /* Width of display area in millimeters */
ushort vl_height; /* Height of display area in millimeters */
/* LCD configuration register */
u_char vl_freq; /* Frequency */
u_char vl_clkp; /* Clock polarity */
u_char vl_oep; /* Output Enable polarity */
u_char vl_hsp; /* Horizontal Sync polarity */
u_char vl_vsp; /* Vertical Sync polarity */
u_char vl_dp; /* Data polarity */
u_char vl_bpix; /* Bits per pixel */
/* Horizontal control register. Timing from data sheet */
u_char vl_hspw; /* Horz sync pulse width */
u_char vl_hfpd; /* Wait before of line */
u_char vl_hbpd; /* Wait end of line */
/* Vertical control register. */
u_char vl_vspw; /* Vertical sync pulse width */
u_char vl_vfpd; /* Wait before of frame */
u_char vl_vbpd; /* Wait end of frame */
u_char vl_cmd_allow_len; /* Wait end of frame */
unsigned int win_id;
unsigned int init_delay;
unsigned int power_on_delay;
unsigned int reset_delay;
unsigned int interface_mode;
unsigned int mipi_enabled;
unsigned int dp_enabled;
unsigned int cs_setup;
unsigned int wr_setup;
unsigned int wr_act;
unsigned int wr_hold;
unsigned int logo_on;
unsigned int logo_width;
unsigned int logo_height;
int logo_x_offset;
int logo_y_offset;
unsigned long logo_addr;
unsigned int rgb_mode;
unsigned int resolution;
/* parent clock name(MPLL, EPLL or VPLL) */
unsigned int pclk_name;
/* ratio value for source clock from parent clock. */
unsigned int sclk_div;
unsigned int dual_lcd_enabled;
} vidinfo_t;
void init_panel_info(vidinfo_t *vid);
#endif

14
include/fdt_simplefb.h Normal file
View File

@@ -0,0 +1,14 @@
/*
* Simplefb device tree support
*
* (C) Copyright 2015
* Stephen Warren <swarren@wwwdotorg.org>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _FDT_SIMPLEFB_H_
#define _FDT_SIMPLEFB_H_
int lcd_dt_simplefb_add_node(void *blob);
int lcd_dt_simplefb_enable_existing_node(void *blob);
#endif

125
include/fdtdec.h
View File

@@ -115,9 +115,6 @@ enum fdt_compat_id {
COMPAT_NVIDIA_TEGRA20_USB, /* Tegra20 USB port */
COMPAT_NVIDIA_TEGRA30_USB, /* Tegra30 USB port */
COMPAT_NVIDIA_TEGRA114_USB, /* Tegra114 USB port */
COMPAT_NVIDIA_TEGRA114_I2C, /* Tegra114 I2C w/single clock source */
COMPAT_NVIDIA_TEGRA20_I2C, /* Tegra20 i2c */
COMPAT_NVIDIA_TEGRA20_DVC, /* Tegra20 dvc (really just i2c) */
COMPAT_NVIDIA_TEGRA20_EMC, /* Tegra20 memory controller */
COMPAT_NVIDIA_TEGRA20_EMC_TABLE, /* Tegra20 memory timing table */
COMPAT_NVIDIA_TEGRA20_KBC, /* Tegra20 Keyboard */
@@ -127,9 +124,6 @@ enum fdt_compat_id {
COMPAT_NVIDIA_TEGRA124_SDMMC, /* Tegra124 SDMMC controller */
COMPAT_NVIDIA_TEGRA30_SDMMC, /* Tegra30 SDMMC controller */
COMPAT_NVIDIA_TEGRA20_SDMMC, /* Tegra20 SDMMC controller */
COMPAT_NVIDIA_TEGRA20_SFLASH, /* Tegra 2 SPI flash controller */
COMPAT_NVIDIA_TEGRA20_SLINK, /* Tegra 2 SPI SLINK controller */
COMPAT_NVIDIA_TEGRA114_SPI, /* Tegra 114 SPI controller */
COMPAT_NVIDIA_TEGRA124_PCIE, /* Tegra 124 PCIe controller */
COMPAT_NVIDIA_TEGRA30_PCIE, /* Tegra 30 PCIe controller */
COMPAT_NVIDIA_TEGRA20_PCIE, /* Tegra 20 PCIe controller */
@@ -140,7 +134,6 @@ enum fdt_compat_id {
COMPAT_SAMSUNG_S3C2440_I2C, /* Exynos I2C Controller */
COMPAT_SAMSUNG_EXYNOS5_SOUND, /* Exynos Sound */
COMPAT_WOLFSON_WM8994_CODEC, /* Wolfson WM8994 Sound Codec */
COMPAT_SAMSUNG_EXYNOS_SPI, /* Exynos SPI */
COMPAT_GOOGLE_CROS_EC, /* Google CROS_EC Protocol */
COMPAT_GOOGLE_CROS_EC_KEYB, /* Google CROS_EC Keyboard */
COMPAT_SAMSUNG_EXYNOS_EHCI, /* Exynos EHCI controller */
@@ -173,42 +166,64 @@ enum fdt_compat_id {
COMPAT_INTEL_MODEL_206AX, /* Intel Model 206AX CPU */
COMPAT_INTEL_GMA, /* Intel Graphics Media Accelerator */
COMPAT_AMS_AS3722, /* AMS AS3722 PMIC */
COMPAT_INTEL_ICH_SPI, /* Intel ICH7/9 SPI controller */
COMPAT_INTEL_QRK_MRC, /* Intel Quark MRC */
COMPAT_COUNT,
};
/* GPIOs are numbered from 0 */
enum {
FDT_GPIO_NONE = -1U, /* an invalid GPIO used to end our list */
FDT_GPIO_ACTIVE_LOW = 1 << 0, /* input is active low (else high) */
#define MAX_PHANDLE_ARGS 16
struct fdtdec_phandle_args {
int node;
int args_count;
uint32_t args[MAX_PHANDLE_ARGS];
};
/* This is the state of a GPIO pin as defined by the fdt */
struct fdt_gpio_state {
const char *name; /* name of the fdt property defining this */
uint gpio; /* GPIO number, or FDT_GPIO_NONE if none */
u8 flags; /* FDT_GPIO_... flags */
};
/* This tells us whether a fdt_gpio_state record is valid or not */
#define fdt_gpio_isvalid(x) ((x)->gpio != FDT_GPIO_NONE)
/**
* Read the GPIO taking into account the polarity of the pin.
* fdtdec_parse_phandle_with_args() - Find a node pointed by phandle in a list
*
* @param gpio pointer to the decoded gpio
* @return value of the gpio if successful, < 0 if unsuccessful
*/
int fdtdec_get_gpio(struct fdt_gpio_state *gpio);
/**
* Write the GPIO taking into account the polarity of the pin.
* This function is useful to parse lists of phandles and their arguments.
*
* Example:
*
* phandle1: node1 {
* #list-cells = <2>;
* }
*
* phandle2: node2 {
* #list-cells = <1>;
* }
*
* node3 {
* list = <&phandle1 1 2 &phandle2 3>;
* }
*
* To get a device_node of the `node2' node you may call this:
* fdtdec_parse_phandle_with_args(blob, node3, "list", "#list-cells", 0, 1,
* &args);
*
* (This function is a modified version of __of_parse_phandle_with_args() from
* Linux 3.18)
*
* @blob: Pointer to device tree
* @src_node: Offset of device tree node containing a list
* @list_name: property name that contains a list
* @cells_name: property name that specifies the phandles' arguments count,
* or NULL to use @cells_count
* @cells_count: Cell count to use if @cells_name is NULL
* @index: index of a phandle to parse out
* @out_args: optional pointer to output arguments structure (will be filled)
* @return 0 on success (with @out_args filled out if not NULL), -ENOENT if
* @list_name does not exist, a phandle was not found, @cells_name
* could not be found, the arguments were truncated or there were too
* many arguments.
*
* @param gpio pointer to the decoded gpio
* @return 0 if successful
*/
int fdtdec_set_gpio(struct fdt_gpio_state *gpio, int val);
int fdtdec_parse_phandle_with_args(const void *blob, int src_node,
const char *list_name,
const char *cells_name,
int cell_count, int index,
struct fdtdec_phandle_args *out_args);
/**
* Find the next numbered alias for a peripheral. This is used to enumerate
@@ -590,50 +605,6 @@ const u32 *fdtdec_locate_array(const void *blob, int node,
*/
int fdtdec_get_bool(const void *blob, int node, const char *prop_name);
/**
* Decode a single GPIOs from an FDT.
*
* If the property is not found, then the GPIO structure will still be
* initialised, with gpio set to FDT_GPIO_NONE. This makes it easy to
* provide optional GPIOs.
*
* @param blob FDT blob to use
* @param node Node to look at
* @param prop_name Node property name
* @param gpio gpio elements to fill from FDT
* @return 0 if ok, -FDT_ERR_NOTFOUND if the property is missing.
*/
int fdtdec_decode_gpio(const void *blob, int node, const char *prop_name,
struct fdt_gpio_state *gpio);
/**
* Decode a list of GPIOs from an FDT. This creates a list of GPIOs with no
* terminating item.
*
* @param blob FDT blob to use
* @param node Node to look at
* @param prop_name Node property name
* @param gpio Array of gpio elements to fill from FDT. This will be
* untouched if either 0 or an error is returned
* @param max_count Maximum number of elements allowed
* @return number of GPIOs read if ok, -FDT_ERR_BADLAYOUT if max_count would
* be exceeded, or -FDT_ERR_NOTFOUND if the property is missing.
*/
int fdtdec_decode_gpios(const void *blob, int node, const char *prop_name,
struct fdt_gpio_state *gpio, int max_count);
/**
* Set up a GPIO pin according to the provided gpio information. At present this
* just requests the GPIO.
*
* If the gpio is FDT_GPIO_NONE, no action is taken. This makes it easy to
* deal with optional GPIOs.
*
* @param gpio GPIO info to use for set up
* @return 0 if all ok or gpio was FDT_GPIO_NONE; -1 on error
*/
int fdtdec_setup_gpio(struct fdt_gpio_state *gpio);
/**
* Look in the FDT for a config item with the given name and return its value
* as a 32-bit integer. The property must have at least 4 bytes of data. The

27
include/fpga.h
View File

@@ -49,18 +49,19 @@ typedef enum {
} bitstream_type;
/* root function definitions */
extern void fpga_init(void);
extern int fpga_add(fpga_type devtype, void *desc);
extern int fpga_count(void);
extern int fpga_load(int devnum, const void *buf, size_t bsize,
bitstream_type bstype);
extern int fpga_fsload(int devnum, const void *buf, size_t size,
fpga_fs_info *fpga_fsinfo);
extern int fpga_loadbitstream(int devnum, char *fpgadata, size_t size,
bitstream_type bstype);
extern int fpga_dump(int devnum, const void *buf, size_t bsize);
extern int fpga_info(int devnum);
extern const fpga_desc *const fpga_validate(int devnum, const void *buf,
size_t bsize, char *fn);
void fpga_init(void);
int fpga_add(fpga_type devtype, void *desc);
int fpga_count(void);
const fpga_desc *const fpga_get_desc(int devnum);
int fpga_load(int devnum, const void *buf, size_t bsize,
bitstream_type bstype);
int fpga_fsload(int devnum, const void *buf, size_t size,
fpga_fs_info *fpga_fsinfo);
int fpga_loadbitstream(int devnum, char *fpgadata, size_t size,
bitstream_type bstype);
int fpga_dump(int devnum, const void *buf, size_t bsize);
int fpga_info(int devnum);
const fpga_desc *const fpga_validate(int devnum, const void *buf,
size_t bsize, char *fn);
#endif /* _FPGA_H_ */

6
include/fs.h
View File

@@ -109,4 +109,10 @@ int do_save(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[],
int do_fs_uuid(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[],
int fstype);
/*
* Determine the type of the specified filesystem and print it. Optionally it is
* possible to store the type directly in env.
*/
int do_fs_type(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
#endif /* _FS_H */

6
include/fsl_ddr.h
View File

@@ -23,9 +23,15 @@
#ifdef CONFIG_SYS_FSL_DDR_LE
#define ddr_in32(a) in_le32(a)
#define ddr_out32(a, v) out_le32(a, v)
#define ddr_setbits32(a, v) setbits_le32(a, v)
#define ddr_clrbits32(a, v) clrbits_le32(a, v)
#define ddr_clrsetbits32(a, clear, set) clrsetbits_le32(a, clear, set)
#else
#define ddr_in32(a) in_be32(a)
#define ddr_out32(a, v) out_be32(a, v)
#define ddr_setbits32(a, v) setbits_be32(a, v)
#define ddr_clrbits32(a, v) clrbits_be32(a, v)
#define ddr_clrsetbits32(a, clear, set) clrsetbits_be32(a, clear, set)
#endif
#define _DDR_ADDR CONFIG_SYS_FSL_DDR_ADDR

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