8xx, kup4k/kup4x: configuration changes, code cleanup
- nfs-options removed - hda->sda changed - mtd parts added - loadaddress changed - cmd-line length increased - lcd stuff removed - code cleanup (use I/O accessors etc.) Signed-off-by: Klaus Heydeck <heydeck@kieback-peter.de>
This commit is contained in:
Heiko Schocher
committed by
Wolfgang Denk
Wolfgang Denk
parent
958e120643
commit
e604e40916
@@ -1,5 +1,5 @@
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/*
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* (C) Copyright 2000-2005
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* (C) Copyright 2000-2010
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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* Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de
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*
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@@ -42,46 +42,46 @@
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#undef CONFIG_8xx_CONS_SMC2
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#undef CONFIG_8xx_CONS_NONE
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#define CONFIG_BAUDRATE 115200 /* console baudrate */
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#if 0
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#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
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#else
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#define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */
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#endif
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#define CONFIG_BOARD_TYPES 1 /* support board types */
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#undef CONFIG_BOOTARGS
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"slot_a_boot=setenv bootargs root=/dev/hda2 ip=off;" \
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"run addhw; diskboot 200000 0:1; bootm 200000\0" \
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"slot_b_boot=setenv bootargs root=/dev/hda2 ip=off;" \
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"run addhw; diskboot 200000 2:1; bootm 200000\0" \
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"nfs_boot=dhcp; run nfsargs addip addhw; bootm 200000\0" \
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"slot_a_boot=setenv bootargs root=/dev/sda2 ip=off;" \
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"run addhw; mw.b 400000 00 80; diskboot 400000 0:1; bootm 400000\0" \
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"slot_b_boot=setenv bootargs root=/dev/sda2 ip=off;" \
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"run addhw; mw.b 400000 00 80; diskboot 400000 2:1; bootm 400000\0" \
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"nfs_boot=mw.b 400000 00 80; dhcp; run nfsargs addip addhw; bootm 400000\0" \
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"fat_boot=mw.b 400000 00 80; fatload ide 2:1 400000 st.bin; run addhw; \
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bootm 400000 \0" \
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"panic_boot=echo No Bootdevice !!! reset\0" \
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"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0" \
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"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${rootpath}\0" \
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"ramargs=setenv bootargs root=/dev/ram rw\0" \
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"addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}" \
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"addip=setenv bootargs ${bootargs} ip=${ipaddr}::${gatewayip}" \
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":${netmask}:${hostname}:${netdev}:off\0" \
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"addhw=setenv bootargs ${bootargs} hw=${hw} key1=${key1} panic=1\0" \
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"addhw=setenv bootargs ${bootargs} ${mtdparts} console=${console} ${debug} \
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hw=${hw} key1=${key1} panic=1 mem=${mem}\0" \
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"console=ttyCPM0,115200\0" \
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"netdev=eth0\0" \
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"contrast=55\0" \
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"contrast=20\0" \
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"silent=1\0" \
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"mtdparts=" MTDPARTS_DEFAULT "\0" \
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"load=tftp 200000 bootloader-4k.bitmap;tftp 100000 bootloader-4k.bin\0" \
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"update=protect off 1:0-7;era 1:0-7;cp.b 100000 40000000 ${filesize};" \
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"update=protect off 1:0-9;era 1:0-9;cp.b 100000 40000000 ${filesize};" \
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"cp.b 200000 40050000 14000\0"
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#define CONFIG_BOOTCOMMAND \
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"run slot_a_boot;run slot_b_boot;run nfs_boot;run panic_boot"
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"run fat_boot;run slot_b_boot;run slot_a_boot;run nfs_boot;run panic_boot"
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#define CONFIG_PREBOOT "setenv preboot; saveenv"
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#define CONFIG_MISC_INIT_R 1
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#define CONFIG_MISC_INIT_F 1
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
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#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
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#define CONFIG_WATCHDOG 1 /* watchdog enabled */
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@@ -98,19 +98,17 @@
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_MAC_PARTITION
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#define CONFIG_DOS_PARTITION
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/*
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* enable I2C and select the hardware/software driver
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*/
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#undef CONFIG_HARD_I2C /* I2C with hardware support */
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#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
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#undef CONFIG_HARD_I2C /* I2C with hardware support */
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#define CONFIG_SOFT_I2C /* I2C bit-banged */
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#define CONFIG_SYS_I2C_SPEED 93000 /* 93 kHz is supposed to work */
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#define CONFIG_SYS_I2C_SLAVE 0xFE
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#define CONFIG_SYS_I2C_SPEED 93000 /* 93 kHz is supposed to work */
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#define CONFIG_SYS_I2C_SLAVE 0xFE
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#ifdef CONFIG_SOFT_I2C
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/*
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@@ -130,14 +128,12 @@
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#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
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#endif /* CONFIG_SOFT_I2C */
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/*-----------------------------------------------------------------------
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* I2C Configuration
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*/
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#define CONFIG_SYS_I2C_PICIO_ADDR 0x21 /* PCF8574 IO Expander */
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#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* PCF8563 RTC */
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#define CONFIG_SYS_I2C_PICIO_ADDR 0x21 /* PCF8574 IO Expander */
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#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* PCF8563 RTC */
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/* List of I2C addresses to be verified by POST */
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@@ -145,27 +141,13 @@
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CONFIG_SYS_I2C_RTC_ADDR, \
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}
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#define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */
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#define CONFIG_SYS_DISCOVER_PHY
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#define CONFIG_MII
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#if 0
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#define CONFIG_ETHADDR 00:0B:64:00:00:00 /* our OUI from IEEE */
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#endif
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#define CONFIG_KUP4K_LOGO 0x40050000 /* Address of logo bitmap */
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/* Define to allow the user to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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#if 1
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/* POST support */
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#define CONFIG_POST (CONFIG_SYS_POST_CPU | \
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CONFIG_SYS_POST_RTC | \
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CONFIG_SYS_POST_I2C)
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#endif
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/*
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* Command line configuration.
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@@ -176,7 +158,9 @@
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_IDE
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_NFS
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#define CONFIG_CMD_FAT
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#define CONFIG_CMD_SNTP
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#ifdef CONFIG_POST
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@@ -191,18 +175,21 @@
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
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#endif
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
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/* Print Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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#define CONFIG_SYS_MEMTEST_START 0x000400000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0x002C00000 /* 4 ... 44 MB in DRAM */
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#define CONFIG_SYS_MEMTEST_START 0x000400000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0x005C00000 /* 4 ... 92 MB in DRAM */
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#define CONFIG_SYS_ALT_MEMTEST 1
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#define CONFIG_SYS_MEMTEST_SCRATCH 0x90000200 /* using latch as scratch register */
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#define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */
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#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */
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#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
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#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 115200 }
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@@ -259,19 +246,22 @@
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#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
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#define CONFIG_ENV_SECT_SIZE 0x10000
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/* Address and size of Redundant Environment Sector */
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#if 0
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#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
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#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
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#endif
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/*-----------------------------------------------------------------------
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* Dynamic MTD partition support
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*/
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#define MTDPARTS_DEFAULT "mtdparts=40000000.flash:256k(u-boot)," \
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"64k(env)," \
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"128k(splash)," \
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"512k(etc)," \
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"64k(hw-info)"
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/*-----------------------------------------------------------------------
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* Hardware Information Block
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*/
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#if 1
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#define CONFIG_SYS_HWINFO_OFFSET 0x000F0000 /* offset of HW Info block */
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#define CONFIG_SYS_HWINFO_SIZE 0x00000100 /* size of HW Info block */
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#define CONFIG_SYS_HWINFO_MAGIC 0x4B26500D /* 'K&P<CR>' */
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#endif
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#define CONFIG_SYS_HWINFO_MAGIC 0x4B26500D /* 'K&P<CR>' */
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/*-----------------------------------------------------------------------
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* Cache Configuration
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*/
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@@ -286,12 +276,7 @@
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*-----------------------------------------------------------------------
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* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
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*/
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#if 0 && defined(CONFIG_WATCHDOG) /* KUP uses external TPS3705 WD */
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#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
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SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
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#else
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#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
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#endif
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/*-----------------------------------------------------------------------
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* SIUMCR - SIU Module Configuration 11-6
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@@ -391,7 +376,6 @@
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/* Offset for alternate registers */
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#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
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/*-----------------------------------------------------------------------
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*
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*-----------------------------------------------------------------------
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@@ -416,18 +400,20 @@
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/*
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* FLASH timing:
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*/
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#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
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OR_SCY_2_CLK | OR_EHTR | OR_BI)
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#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV2 | OR_CSNT_SAM | \
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OR_SCY_5_CLK | OR_EHTR | OR_BI)
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#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
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#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
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#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
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#define CONFIG_SYS_OR0_REMAP \
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(CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
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#define CONFIG_SYS_OR0_PRELIM \
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(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
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#define CONFIG_SYS_BR0_PRELIM \
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((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
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/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
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#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
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/*
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* Memory Periodic Timer Prescaler
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*
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@@ -475,7 +461,39 @@
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/*
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* MAMR settings for SDRAM
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*/
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#define CONFIG_SYS_MAMR 0x80802114
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/* 8 column SDRAM */
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#define CONFIG_SYS_MAMR_8COL 0x68802114
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/* 9 column SDRAM */
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#define CONFIG_SYS_MAMR_9COL 0x68904114
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/*
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* Chip Selects
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*/
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#define CONFIG_SYS_OR0
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#define CONFIG_SYS_BR0
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#define CONFIG_SYS_OR1_8COL 0xFF000A00
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#define CONFIG_SYS_BR1_8COL 0x00000081
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#define CONFIG_SYS_OR2_8COL 0xFE000A00
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#define CONFIG_SYS_BR2_8COL 0x01000081
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#define CONFIG_SYS_OR3_8COL 0xFC000A00
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#define CONFIG_SYS_BR3_8COL 0x02000081
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#define CONFIG_SYS_OR1_9COL 0xFE000A00
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#define CONFIG_SYS_BR1_9COL 0x00000081
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#define CONFIG_SYS_OR2_9COL 0xFE000A00
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#define CONFIG_SYS_BR2_9COL 0x02000081
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#define CONFIG_SYS_OR3_9COL 0xFE000A00
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#define CONFIG_SYS_BR3_9COL 0x04000081
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#define CONFIG_SYS_OR4 0xFFFF8926
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#define CONFIG_SYS_BR4 0x90000401
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#define CONFIG_SYS_OR5 0xFFC007F0 /* EPSON: 4 MB 17 WS or externel TA */
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#define CONFIG_SYS_BR5 0x80080801 /* Start at 0x80080000 */
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#define LATCH_ADDR 0x90000200
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/*
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* Internal Definitions
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@@ -487,11 +505,10 @@
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#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */
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#if 0
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#define CONFIG_AUTOBOOT_PROMPT \
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"Boote in %d Sekunden - stop mit \"2\"\n", bootdelay
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#endif
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#define CONFIG_AUTOBOOT_STOP_STR "." /* easy to stop for now */
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#define CONFIG_SILENT_CONSOLE 1
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#define CONFIG_AUTOBOOT_STOP_STR "."
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#define CONFIG_SILENT_CONSOLE 1
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#define CONFIG_SYS_DEVICE_NULLDEV 1 /* enble null device */
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#define CONFIG_VERSION_VARIABLE 1
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#endif /* __CONFIG_H */
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@@ -35,23 +35,20 @@
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* (easy to change)
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*/
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#define CONFIG_MPC859T 1 /* This is a MPC859T CPU */
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#define CONFIG_KUP4X 1 /* ...on a KUP4X module */
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#define CONFIG_MPC859T 1 /* This is a MPC859T CPU */
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#define CONFIG_KUP4X 1 /* ...on a KUP4X module */
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#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
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#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
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#undef CONFIG_8xx_CONS_SMC2
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#undef CONFIG_8xx_CONS_NONE
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#define CONFIG_BAUDRATE 115200 /* console baudrate */
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#if 0
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#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
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#else
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#define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */
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#endif
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#define CONFIG_BAUDRATE 115200 /* console baudrate */
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#define CONFIG_BOARD_TYPES 1 /* support board types */
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#define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */
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#define CONFIG_SYS_8XX_FACT 8 /* Multiply by 8 */
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#define CONFIG_SYS_8XX_XIN 16000000 /* 16 MHz in */
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#define CONFIG_BOARD_TYPES 1 /* support board types */
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#define CONFIG_SYS_8XX_FACT 8 /* Multiply by 8 */
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#define CONFIG_SYS_8XX_XIN 16000000 /* 16 MHz in */
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#define MPC8XX_HZ ((CONFIG_SYS_8XX_XIN) * (CONFIG_SYS_8XX_FACT))
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@@ -67,9 +64,9 @@
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"slot_a_boot=setenv bootargs root=/dev/hda2 ip=off;" \
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"run addhw;diskboot 200000 0:1;bootm 200000\0" \
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"usb_boot=setenv bootargs root=/dev/sda2 ip=off;\
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run addhw; sleep 2; usb reset; usb scan; usbboot 200000 0:1;\
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usb stop; bootm 200000\0" \
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"usb_boot=setenv bootargs root=/dev/sda2 ip=off; \
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run addhw; sleep 2; usb reset; usb scan; usbboot 200000 0:1; \
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usb stop; bootm 200000\0" \
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"nfs_boot=dhcp;run nfsargs addip addhw;bootm 200000\0" \
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"panic_boot=echo No Bootdevice !!! reset\0" \
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"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0" \
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@@ -84,14 +81,14 @@
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"cp.b 200000 40040000 14000\0"
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#define CONFIG_BOOTCOMMAND \
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"run usb_boot;run_slot_a_boot;run nfs_boot;run panic_boot"
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"run usb_boot;run slot_a_boot;run nfs_boot;run panic_boot"
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#define CONFIG_MISC_INIT_R 1
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#define CONFIG_MISC_INIT_F 1
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
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#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
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#define CONFIG_WATCHDOG 1 /* watchdog enabled */
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@@ -144,8 +141,8 @@
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* I2C Configuration
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*/
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#define CONFIG_SYS_I2C_PICIO_ADDR 0x21 /* PCF8574 IO Expander */
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#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* PCF8563 RTC */
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#define CONFIG_SYS_I2C_PICIO_ADDR 0x21 /* PCF8574 IO Expander */
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#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* PCF8563 RTC */
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/* List of I2C addresses to be verified by POST */
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@@ -160,22 +157,16 @@
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#define CONFIG_SYS_DISCOVER_PHY
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#define CONFIG_MII
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#if 0
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#define CONFIG_ETHADDR 00:0B:64:80:00:00 /* our OUI from IEEE */
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#endif
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#undef CONFIG_KUP4K_LOGO
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/* Define to allow the user to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
|
||||
|
||||
|
||||
#if 1
|
||||
/* POST support */
|
||||
|
||||
#define CONFIG_POST (CONFIG_SYS_POST_CPU | \
|
||||
CONFIG_SYS_POST_RTC | \
|
||||
CONFIG_SYS_POST_I2C)
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
@@ -426,9 +417,12 @@
|
||||
#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
|
||||
OR_SCY_2_CLK | OR_EHTR | OR_BI)
|
||||
|
||||
#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
|
||||
#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
|
||||
#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
|
||||
#define CONFIG_SYS_OR0_REMAP \
|
||||
(CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
|
||||
#define CONFIG_SYS_OR0_PRELIM \
|
||||
(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
|
||||
#define CONFIG_SYS_BR0_PRELIM \
|
||||
((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
|
||||
|
||||
|
||||
/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
|
||||
@@ -443,6 +437,15 @@
|
||||
#define CONFIG_SYS_MAMR 0x80802114
|
||||
|
||||
|
||||
/*
|
||||
* Chip Selects
|
||||
*/
|
||||
|
||||
#define CONFIG_SYS_OR4 0xFFFF8926
|
||||
#define CONFIG_SYS_BR4 0x90000401
|
||||
|
||||
#define LATCH_ADDR 0x90000200
|
||||
|
||||
/*
|
||||
* Internal Definitions
|
||||
*
|
||||
@@ -453,10 +456,7 @@
|
||||
|
||||
|
||||
#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */
|
||||
#if 0
|
||||
#define CONFIG_AUTOBOOT_PROMPT \
|
||||
"Boote in %d Sekunden - stop mit \"2\"\n", bootdelay
|
||||
#endif
|
||||
|
||||
#define CONFIG_AUTOBOOT_STOP_STR "." /* easy to stop for now */
|
||||
#define CONFIG_SILENT_CONSOLE 1
|
||||
|
||||
|
||||
Reference in New Issue
Block a user