powerpc/p1010rdb: add p1010rdb-pb support with updating p1010rdb-pa
- Rename old P1010RDB board as P1010RDB-PA. - Add support for new P1010RDB-PB board. - Some optimization. For more details, see board/freescale/p1010rdb/README. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> [York Sun: fix conflicts in boards.cfg] Acked-by: York Sun <yorksun@freescale.com>
This commit is contained in:
Shengzhou Liu
York Sun
@@ -120,7 +120,11 @@
|
||||
#endif
|
||||
|
||||
/* controller 2, Slot 2, tgtid 2, Base address 9000 */
|
||||
#if defined(CONFIG_P1010RDB_PA)
|
||||
#define CONFIG_SYS_PCIE2_NAME "PCIe Slot"
|
||||
#elif defined(CONFIG_P1010RDB_PB)
|
||||
#define CONFIG_SYS_PCIE2_NAME "mini PCIe Slot"
|
||||
#endif
|
||||
#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
|
||||
@@ -200,25 +204,24 @@ extern unsigned long get_sdram_size(void);
|
||||
#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
|
||||
#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
|
||||
#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
|
||||
|
||||
#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
|
||||
#define CONFIG_SYS_DDR_SR_CNTR 0x00000000
|
||||
#define CONFIG_SYS_DDR_RCW_1 0x00000000
|
||||
#define CONFIG_SYS_DDR_RCW_2 0x00000000
|
||||
#define CONFIG_SYS_DDR_CONTROL 0x470C0000 /* Type = DDR3 */
|
||||
#define CONFIG_SYS_DDR_CONTROL_2 0x04401010
|
||||
#define CONFIG_SYS_DDR_CONTROL 0xc70c0008 /* Type = DDR3 */
|
||||
#define CONFIG_SYS_DDR_CONTROL_2 0x24401000
|
||||
#define CONFIG_SYS_DDR_TIMING_4 0x00000001
|
||||
#define CONFIG_SYS_DDR_TIMING_5 0x03402400
|
||||
|
||||
#define CONFIG_SYS_DDR_TIMING_3_800 0x00020000
|
||||
#define CONFIG_SYS_DDR_TIMING_0_800 0x00330004
|
||||
#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6B4644
|
||||
#define CONFIG_SYS_DDR_TIMING_3_800 0x00030000
|
||||
#define CONFIG_SYS_DDR_TIMING_0_800 0x00110104
|
||||
#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644
|
||||
#define CONFIG_SYS_DDR_TIMING_2_800 0x0FA888CF
|
||||
#define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000
|
||||
#define CONFIG_SYS_DDR_MODE_1_800 0x40461520
|
||||
#define CONFIG_SYS_DDR_MODE_2_800 0x8000c000
|
||||
#define CONFIG_SYS_DDR_MODE_1_800 0x00441420
|
||||
#define CONFIG_SYS_DDR_MODE_2_800 0x00000000
|
||||
#define CONFIG_SYS_DDR_INTERVAL_800 0x0C300100
|
||||
#define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8655A608
|
||||
#define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608
|
||||
|
||||
/* settings for DDR3 at 667MT/s */
|
||||
#define CONFIG_SYS_DDR_TIMING_3_667 0x00010000
|
||||
@@ -315,6 +318,8 @@ extern unsigned long get_sdram_size(void);
|
||||
| CSPR_MSEL_NAND \
|
||||
| CSPR_V)
|
||||
#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
|
||||
|
||||
#if defined(CONFIG_P1010RDB_PA)
|
||||
#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
|
||||
| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
|
||||
| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
|
||||
@@ -322,13 +327,26 @@ extern unsigned long get_sdram_size(void);
|
||||
| CSOR_NAND_PGS_512 /* Page Size = 512b */ \
|
||||
| CSOR_NAND_SPRZ_16 /* Spare size = 16 */ \
|
||||
| CSOR_NAND_PB(32)) /* 32 Pages Per Block */
|
||||
#define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
|
||||
|
||||
#elif defined(CONFIG_P1010RDB_PB)
|
||||
#define CONFIG_SYS_NAND_ONFI_DETECTION
|
||||
#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
|
||||
| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
|
||||
| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
|
||||
| CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
|
||||
| CSOR_NAND_PGS_4K /* Page Size = 4K */ \
|
||||
| CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
|
||||
| CSOR_NAND_PB(128)) /*Pages Per Block = 128 */
|
||||
#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1
|
||||
#define CONFIG_MTD_NAND_VERIFY_WRITE
|
||||
#define CONFIG_CMD_NAND
|
||||
#define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
|
||||
|
||||
#if defined(CONFIG_P1010RDB_PA)
|
||||
/* NAND Flash Timing Params */
|
||||
#define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \
|
||||
FTIM0_NAND_TWP(0x0C) | \
|
||||
@@ -343,6 +361,23 @@ extern unsigned long get_sdram_size(void);
|
||||
FTIM2_NAND_TWHRE(0x0f)
|
||||
#define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04)
|
||||
|
||||
#elif defined(CONFIG_P1010RDB_PB)
|
||||
/* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */
|
||||
/* ONFI NAND Flash mode0 Timing Params */
|
||||
#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07)| \
|
||||
FTIM0_NAND_TWP(0x18) | \
|
||||
FTIM0_NAND_TWCHT(0x07) | \
|
||||
FTIM0_NAND_TWH(0x0a))
|
||||
#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32)| \
|
||||
FTIM1_NAND_TWBE(0x39) | \
|
||||
FTIM1_NAND_TRR(0x0e) | \
|
||||
FTIM1_NAND_TRP(0x18))
|
||||
#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
|
||||
FTIM2_NAND_TREH(0x0a) | \
|
||||
FTIM2_NAND_TWHRE(0x1e))
|
||||
#define CONFIG_SYS_NAND_FTIM3 0x0
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_NAND_DDR_LAW 11
|
||||
|
||||
/* Set up IFC registers for boot location NOR/NAND */
|
||||
@@ -475,10 +510,20 @@ extern unsigned long get_sdram_size(void);
|
||||
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
|
||||
#define I2C_PCA9557_ADDR1 0x18
|
||||
#define I2C_PCA9557_ADDR2 0x19
|
||||
#define I2C_PCA9557_BUS_NUM 0
|
||||
|
||||
/* I2C EEPROM */
|
||||
#undef CONFIG_ID_EEPROM
|
||||
#if defined(CONFIG_P1010RDB_PB)
|
||||
#define CONFIG_ID_EEPROM
|
||||
#ifdef CONFIG_ID_EEPROM
|
||||
#define CONFIG_SYS_I2C_EEPROM_NXID
|
||||
#endif
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
|
||||
#define CONFIG_SYS_EEPROM_BUS_NUM 0
|
||||
#define MAX_NUM_PORTS 9 /* for 128Bytes EEPROM */
|
||||
#endif
|
||||
/* enable read and write access to EEPROM */
|
||||
#define CONFIG_CMD_EEPROM
|
||||
#define CONFIG_SYS_I2C_MULTI_EEPROMS
|
||||
@@ -602,9 +647,14 @@ extern unsigned long get_sdram_size(void);
|
||||
#define CONFIG_ENV_SIZE 0x2000
|
||||
#elif defined(CONFIG_NAND)
|
||||
#define CONFIG_ENV_IS_IN_NAND
|
||||
#if defined(CONFIG_P1010RDB_PA)
|
||||
#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
|
||||
#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */
|
||||
#elif defined(CONFIG_P1010RDB_PB)
|
||||
#define CONFIG_ENV_SIZE (16 * 1024)
|
||||
#define CONFIG_ENV_RANGE (32 * CONFIG_ENV_SIZE) /* new block size 512K */
|
||||
#endif
|
||||
#define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
|
||||
#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
|
||||
#elif defined(CONFIG_SYS_RAMBOOT)
|
||||
#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
|
||||
@@ -697,7 +747,6 @@ extern unsigned long get_sdram_size(void);
|
||||
#define CONFIG_HAS_ETH2
|
||||
#endif
|
||||
|
||||
#define CONFIG_HOSTNAME P1010RDB
|
||||
#define CONFIG_ROOTPATH "/opt/nfsroot"
|
||||
#define CONFIG_BOOTFILE "uImage"
|
||||
#define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */
|
||||
@@ -736,7 +785,31 @@ extern unsigned long get_sdram_size(void);
|
||||
"ext2load usb 0:4 $loadaddr $bootfile;" \
|
||||
"ext2load usb 0:4 $fdtaddr $fdtfile;" \
|
||||
"ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
|
||||
"bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
|
||||
"bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
|
||||
CONFIG_BOOTMODE
|
||||
|
||||
#if defined(CONFIG_P1010RDB_PA)
|
||||
#define CONFIG_BOOTMODE \
|
||||
"boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
|
||||
"mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \
|
||||
"boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
|
||||
"mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \
|
||||
"boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \
|
||||
"mw.b ffb00011 0; mw.b ffb00017 1; reset\0"
|
||||
|
||||
#elif defined(CONFIG_P1010RDB_PB)
|
||||
#define CONFIG_BOOTMODE \
|
||||
"boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
|
||||
"i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \
|
||||
"boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
|
||||
"i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \
|
||||
"boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0;" \
|
||||
"i2c mw 19 1 8; i2c mw 19 3 f7; reset\0" \
|
||||
"boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0;" \
|
||||
"i2c mw 19 1 0; i2c mw 19 3 f7; reset\0" \
|
||||
"boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0;" \
|
||||
"i2c mw 19 1 4; i2c mw 19 3 f3; reset\0"
|
||||
#endif
|
||||
|
||||
#define CONFIG_RAMBOOTCOMMAND \
|
||||
"setenv bootargs root=/dev/ram rw " \
|
||||
|
||||
Reference in New Issue
Block a user