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Merge branch 'master' of git://git.denx.de/u-boot

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This commit is contained in:
Ben Warren
2008-06-08 22:04:22 -07:00
parent 0e38c938ed 8155efbd7a
commit e44f3ea4e8
209 changed files with 8604 additions and 1283 deletions
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2
include/ACEX1K.h
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@@ -77,6 +77,8 @@ typedef struct {
#endif
#define Altera_EP1K100_SIZE (166965*8)
#define Altera_EP2C8_SIZE 247942
#define Altera_EP2C20_SIZE 586562
#define Altera_EP2C35_SIZE 883905
/* Descriptor Macros

5
include/asm-arm/arch-at91sam9/at91_pmc.h
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@@ -96,4 +96,9 @@
#define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */
#define AT91_PMC_IMR (AT91_PMC + 0x6c) /* Interrupt Mask Register */
#define AT91_PMC_PROT (AT91_PMC + 0xe4) /* Protect Register [AT91CAP9 revC only] */
#define AT91_PMC_PROTKEY 0x504d4301 /* Activation Code */
#define AT91_PMC_VER (AT91_PMC + 0xfc) /* PMC Module Version [AT91CAP9 only] */
#endif

14
include/asm-arm/arch-at91sam9/at91cap9.h
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@@ -101,12 +101,24 @@
#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS)
#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS)
#define AT91_SCKCR (0xfffffd50 - AT91_BASE_SYS)
#define AT91_GPBR_REVB (0xfffffd50 - AT91_BASE_SYS)
#define AT91_GPBR_REVC (0xfffffd60 - AT91_BASE_SYS)
#define AT91_USART0 AT91CAP9_BASE_US0
#define AT91_USART1 AT91CAP9_BASE_US1
#define AT91_USART2 AT91CAP9_BASE_US2
/*
* SCKCR flags
*/
#define AT91CAP9_SCKCR_RCEN (1 << 0) /* RC Oscillator Enable */
#define AT91CAP9_SCKCR_OSC32EN (1 << 1) /* 32kHz Oscillator Enable */
#define AT91CAP9_SCKCR_OSC32BYP (1 << 2) /* 32kHz Oscillator Bypass */
#define AT91CAP9_SCKCR_OSCSEL (1 << 3) /* Slow Clock Selector */
#define AT91CAP9_SCKCR_OSCSEL_RC (0 << 3)
#define AT91CAP9_SCKCR_OSCSEL_32 (1 << 3)
/*
* Internal Memory.
*/

105
include/asm-arm/arch-at91sam9/at91sam9261.h Normal file
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@@ -0,0 +1,105 @@
/*
* [origin: Linux kernel include/asm-arm/arch-at91/at91sam9261.h]
*
* Copyright (C) SAN People
*
* Common definitions.
* Based on AT91SAM9261 datasheet revision E. (Preliminary)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91SAM9261_H
#define AT91SAM9261_H
/*
* Peripheral identifiers/interrupts.
*/
#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
#define AT91_ID_SYS 1 /* System Peripherals */
#define AT91SAM9261_ID_PIOA 2 /* Parallel IO Controller A */
#define AT91SAM9261_ID_PIOB 3 /* Parallel IO Controller B */
#define AT91SAM9261_ID_PIOC 4 /* Parallel IO Controller C */
#define AT91SAM9261_ID_US0 6 /* USART 0 */
#define AT91SAM9261_ID_US1 7 /* USART 1 */
#define AT91SAM9261_ID_US2 8 /* USART 2 */
#define AT91SAM9261_ID_MCI 9 /* Multimedia Card Interface */
#define AT91SAM9261_ID_UDP 10 /* USB Device Port */
#define AT91SAM9261_ID_TWI 11 /* Two-Wire Interface */
#define AT91SAM9261_ID_SPI0 12 /* Serial Peripheral Interface 0 */
#define AT91SAM9261_ID_SPI1 13 /* Serial Peripheral Interface 1 */
#define AT91SAM9261_ID_SSC0 14 /* Serial Synchronous Controller 0 */
#define AT91SAM9261_ID_SSC1 15 /* Serial Synchronous Controller 1 */
#define AT91SAM9261_ID_SSC2 16 /* Serial Synchronous Controller 2 */
#define AT91SAM9261_ID_TC0 17 /* Timer Counter 0 */
#define AT91SAM9261_ID_TC1 18 /* Timer Counter 1 */
#define AT91SAM9261_ID_TC2 19 /* Timer Counter 2 */
#define AT91SAM9261_ID_UHP 20 /* USB Host port */
#define AT91SAM9261_ID_LCDC 21 /* LDC Controller */
#define AT91SAM9261_ID_IRQ0 29 /* Advanced Interrupt Controller (IRQ0) */
#define AT91SAM9261_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */
#define AT91SAM9261_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */
/*
* User Peripheral physical base addresses.
*/
#define AT91SAM9261_BASE_TCB0 0xfffa0000
#define AT91SAM9261_BASE_TC0 0xfffa0000
#define AT91SAM9261_BASE_TC1 0xfffa0040
#define AT91SAM9261_BASE_TC2 0xfffa0080
#define AT91SAM9261_BASE_UDP 0xfffa4000
#define AT91SAM9261_BASE_MCI 0xfffa8000
#define AT91SAM9261_BASE_TWI 0xfffac000
#define AT91SAM9261_BASE_US0 0xfffb0000
#define AT91SAM9261_BASE_US1 0xfffb4000
#define AT91SAM9261_BASE_US2 0xfffb8000
#define AT91SAM9261_BASE_SSC0 0xfffbc000
#define AT91SAM9261_BASE_SSC1 0xfffc0000
#define AT91SAM9261_BASE_SSC2 0xfffc4000
#define AT91SAM9261_BASE_SPI0 0xfffc8000
#define AT91SAM9261_BASE_SPI1 0xfffcc000
#define AT91_BASE_SYS 0xffffea00
/*
* System Peripherals (offset from AT91_BASE_SYS)
*/
#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS)
#define AT91_SMC (0xffffec00 - AT91_BASE_SYS)
#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
#define AT91_PIOA (0xfffff400 - AT91_BASE_SYS)
#define AT91_PIOB (0xfffff600 - AT91_BASE_SYS)
#define AT91_PIOC (0xfffff800 - AT91_BASE_SYS)
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS)
#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS)
#define AT91_USART0 AT91SAM9261_BASE_US0
#define AT91_USART1 AT91SAM9261_BASE_US1
#define AT91_USART2 AT91SAM9261_BASE_US2
/*
* Internal Memory.
*/
#define AT91SAM9261_SRAM_BASE 0x00300000 /* Internal SRAM base address */
#define AT91SAM9261_SRAM_SIZE 0x00028000 /* Internal SRAM size (160Kb) */
#define AT91SAM9261_ROM_BASE 0x00400000 /* Internal ROM base address */
#define AT91SAM9261_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */
#define AT91SAM9261_UHP_BASE 0x00500000 /* USB Host controller */
#define AT91SAM9261_LCDC_BASE 0x00600000 /* LDC controller */
#endif

64
include/asm-arm/arch-at91sam9/at91sam9261_matrix.h Normal file
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@@ -0,0 +1,64 @@
/*
* [origin: Linux kernel include/asm-arm/arch-at91/at91sam9261_matrix.h]
*
* Copyright (C) 2007 Atmel Corporation.
*
* Memory Controllers (MATRIX, EBI) - System peripherals registers.
* Based on AT91SAM9261 datasheet revision D.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91SAM9261_MATRIX_H
#define AT91SAM9261_MATRIX_H
#define AT91_MATRIX_MCFG (AT91_MATRIX + 0x00) /* Master Configuration Register */
#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x04) /* Slave Configuration Register 0 */
#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x08) /* Slave Configuration Register 1 */
#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x0C) /* Slave Configuration Register 2 */
#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x10) /* Slave Configuration Register 3 */
#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x14) /* Slave Configuration Register 4 */
#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
#define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */
#define AT91_MATRIX_TCR (AT91_MATRIX + 0x24) /* TCM Configuration Register */
#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */
#define AT91_MATRIX_ITCM_0 (0 << 0)
#define AT91_MATRIX_ITCM_16 (5 << 0)
#define AT91_MATRIX_ITCM_32 (6 << 0)
#define AT91_MATRIX_ITCM_64 (7 << 0)
#define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */
#define AT91_MATRIX_DTCM_0 (0 << 4)
#define AT91_MATRIX_DTCM_16 (5 << 4)
#define AT91_MATRIX_DTCM_32 (6 << 4)
#define AT91_MATRIX_DTCM_64 (7 << 4)
#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x30) /* EBI Chip Select Assignment Register */
#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */
#define AT91_MATRIX_CS1A_SMC (0 << 1)
#define AT91_MATRIX_CS1A_SDRAMC (1 << 1)
#define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */
#define AT91_MATRIX_CS3A_SMC (0 << 3)
#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
#define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */
#define AT91_MATRIX_CS4A_SMC (0 << 4)
#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4)
#define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */
#define AT91_MATRIX_CS5A_SMC (0 << 5)
#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5)
#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
#define AT91_MATRIX_USBPUCR (AT91_MATRIX + 0x34) /* USB Pad Pull-Up Control Register */
#define AT91_MATRIX_USBPUCR_PUON (1 << 30) /* USB Device PAD Pull-up Enable */
#endif

127
include/asm-arm/arch-at91sam9/at91sam9263.h Normal file
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@@ -0,0 +1,127 @@
/*
* [origin: Linux kernel include/asm-arm/arch-at91/at91sam9263.h]
*
* (C) 2007 Atmel Corporation.
*
* Common definitions.
* Based on AT91SAM9263 datasheet revision B (Preliminary).
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91SAM9263_H
#define AT91SAM9263_H
/*
* Peripheral identifiers/interrupts.
*/
#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
#define AT91_ID_SYS 1 /* System Peripherals */
#define AT91SAM9263_ID_PIOA 2 /* Parallel IO Controller A */
#define AT91SAM9263_ID_PIOB 3 /* Parallel IO Controller B */
#define AT91SAM9263_ID_PIOCDE 4 /* Parallel IO Controller C, D and E */
#define AT91SAM9263_ID_US0 7 /* USART 0 */
#define AT91SAM9263_ID_US1 8 /* USART 1 */
#define AT91SAM9263_ID_US2 9 /* USART 2 */
#define AT91SAM9263_ID_MCI0 10 /* Multimedia Card Interface 0 */
#define AT91SAM9263_ID_MCI1 11 /* Multimedia Card Interface 1 */
#define AT91SAM9263_ID_CAN 12 /* CAN */
#define AT91SAM9263_ID_TWI 13 /* Two-Wire Interface */
#define AT91SAM9263_ID_SPI0 14 /* Serial Peripheral Interface 0 */
#define AT91SAM9263_ID_SPI1 15 /* Serial Peripheral Interface 1 */
#define AT91SAM9263_ID_SSC0 16 /* Serial Synchronous Controller 0 */
#define AT91SAM9263_ID_SSC1 17 /* Serial Synchronous Controller 1 */
#define AT91SAM9263_ID_AC97C 18 /* AC97 Controller */
#define AT91SAM9263_ID_TCB 19 /* Timer Counter 0, 1 and 2 */
#define AT91SAM9263_ID_PWMC 20 /* Pulse Width Modulation Controller */
#define AT91SAM9263_ID_EMAC 21 /* Ethernet */
#define AT91SAM9263_ID_2DGE 23 /* 2D Graphic Engine */
#define AT91SAM9263_ID_UDP 24 /* USB Device Port */
#define AT91SAM9263_ID_ISI 25 /* Image Sensor Interface */
#define AT91SAM9263_ID_LCDC 26 /* LCD Controller */
#define AT91SAM9263_ID_DMA 27 /* DMA Controller */
#define AT91SAM9263_ID_UHP 29 /* USB Host port */
#define AT91SAM9263_ID_IRQ0 30 /* Advanced Interrupt Controller (IRQ0) */
#define AT91SAM9263_ID_IRQ1 31 /* Advanced Interrupt Controller (IRQ1) */
/*
* User Peripheral physical base addresses.
*/
#define AT91SAM9263_BASE_UDP 0xfff78000
#define AT91SAM9263_BASE_TCB0 0xfff7c000
#define AT91SAM9263_BASE_TC0 0xfff7c000
#define AT91SAM9263_BASE_TC1 0xfff7c040
#define AT91SAM9263_BASE_TC2 0xfff7c080
#define AT91SAM9263_BASE_MCI0 0xfff80000
#define AT91SAM9263_BASE_MCI1 0xfff84000
#define AT91SAM9263_BASE_TWI 0xfff88000
#define AT91SAM9263_BASE_US0 0xfff8c000
#define AT91SAM9263_BASE_US1 0xfff90000
#define AT91SAM9263_BASE_US2 0xfff94000
#define AT91SAM9263_BASE_SSC0 0xfff98000
#define AT91SAM9263_BASE_SSC1 0xfff9c000
#define AT91SAM9263_BASE_AC97C 0xfffa0000
#define AT91SAM9263_BASE_SPI0 0xfffa4000
#define AT91SAM9263_BASE_SPI1 0xfffa8000
#define AT91SAM9263_BASE_CAN 0xfffac000
#define AT91SAM9263_BASE_PWMC 0xfffb8000
#define AT91SAM9263_BASE_EMAC 0xfffbc000
#define AT91SAM9263_BASE_ISI 0xfffc4000
#define AT91SAM9263_BASE_2DGE 0xfffc8000
#define AT91_BASE_SYS 0xffffe000
/*
* System Peripherals (offset from AT91_BASE_SYS)
*/
#define AT91_ECC0 (0xffffe000 - AT91_BASE_SYS)
#define AT91_SDRAMC0 (0xffffe200 - AT91_BASE_SYS)
#define AT91_SMC0 (0xffffe400 - AT91_BASE_SYS)
#define AT91_ECC1 (0xffffe600 - AT91_BASE_SYS)
#define AT91_SDRAMC1 (0xffffe800 - AT91_BASE_SYS)
#define AT91_SMC1 (0xffffea00 - AT91_BASE_SYS)
#define AT91_MATRIX (0xffffec00 - AT91_BASE_SYS)
#define AT91_CCFG (0xffffed10 - AT91_BASE_SYS)
#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS)
#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
#define AT91_PIOA (0xfffff200 - AT91_BASE_SYS)
#define AT91_PIOB (0xfffff400 - AT91_BASE_SYS)
#define AT91_PIOC (0xfffff600 - AT91_BASE_SYS)
#define AT91_PIOD (0xfffff800 - AT91_BASE_SYS)
#define AT91_PIOE (0xfffffa00 - AT91_BASE_SYS)
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
#define AT91_RTT0 (0xfffffd20 - AT91_BASE_SYS)
#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
#define AT91_RTT1 (0xfffffd50 - AT91_BASE_SYS)
#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
#define AT91_USART0 AT91SAM9263_BASE_US0
#define AT91_USART1 AT91SAM9263_BASE_US1
#define AT91_USART2 AT91SAM9263_BASE_US2
#define AT91_SMC AT91_SMC0
/*
* Internal Memory.
*/
#define AT91SAM9263_SRAM0_BASE 0x00300000 /* Internal SRAM 0 base address */
#define AT91SAM9263_SRAM0_SIZE (80 * SZ_1K) /* Internal SRAM 0 size (80Kb) */
#define AT91SAM9263_ROM_BASE 0x00400000 /* Internal ROM base address */
#define AT91SAM9263_ROM_SIZE SZ_128K /* Internal ROM size (128Kb) */
#define AT91SAM9263_SRAM1_BASE 0x00500000 /* Internal SRAM 1 base address */
#define AT91SAM9263_SRAM1_SIZE SZ_16K /* Internal SRAM 1 size (16Kb) */
#define AT91SAM9263_LCDC_BASE 0x00700000 /* LCD Controller */
#define AT91SAM9263_DMAC_BASE 0x00800000 /* DMA Controller */
#define AT91SAM9263_UHP_BASE 0x00a00000 /* USB Host controller */
#endif

129
include/asm-arm/arch-at91sam9/at91sam9263_matrix.h Normal file
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@@ -0,0 +1,129 @@
/*
* [origin: Linux kernel include/asm-arm/arch-at91/at91sam9263_matrix.h]
*
* Copyright (C) 2006 Atmel Corporation.
*
* Memory Controllers (MATRIX, EBI) - System peripherals registers.
* Based on AT91SAM9263 datasheet revision B (Preliminary).
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91SAM9263_MATRIX_H
#define AT91SAM9263_MATRIX_H
#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */
#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */
#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */
#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */
#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */
#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */
#define AT91_MATRIX_MCFG6 (AT91_MATRIX + 0x18) /* Master Configuration Register 6 */
#define AT91_MATRIX_MCFG7 (AT91_MATRIX + 0x1C) /* Master Configuration Register 7 */
#define AT91_MATRIX_MCFG8 (AT91_MATRIX + 0x20) /* Master Configuration Register 8 */
#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
#define AT91_MATRIX_ULBT_FOUR (2 << 0)
#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */
#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */
#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */
#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */
#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */
#define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */
#define AT91_MATRIX_SCFG6 (AT91_MATRIX + 0x58) /* Slave Configuration Register 6 */
#define AT91_MATRIX_SCFG7 (AT91_MATRIX + 0x5C) /* Slave Configuration Register 7 */
#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */
#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */
#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */
#define AT91_MATRIX_PRBS0 (AT91_MATRIX + 0x84) /* Priority Register B for Slave 0 */
#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */
#define AT91_MATRIX_PRBS1 (AT91_MATRIX + 0x8C) /* Priority Register B for Slave 1 */
#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */
#define AT91_MATRIX_PRBS2 (AT91_MATRIX + 0x94) /* Priority Register B for Slave 2 */
#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */
#define AT91_MATRIX_PRBS3 (AT91_MATRIX + 0x9C) /* Priority Register B for Slave 3 */
#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */
#define AT91_MATRIX_PRBS4 (AT91_MATRIX + 0xA4) /* Priority Register B for Slave 4 */
#define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */
#define AT91_MATRIX_PRBS5 (AT91_MATRIX + 0xAC) /* Priority Register B for Slave 5 */
#define AT91_MATRIX_PRAS6 (AT91_MATRIX + 0xB0) /* Priority Register A for Slave 6 */
#define AT91_MATRIX_PRBS6 (AT91_MATRIX + 0xB4) /* Priority Register B for Slave 6 */
#define AT91_MATRIX_PRAS7 (AT91_MATRIX + 0xB8) /* Priority Register A for Slave 7 */
#define AT91_MATRIX_PRBS7 (AT91_MATRIX + 0xBC) /* Priority Register B for Slave 7 */
#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */
#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
#define AT91_MATRIX_M6PR (3 << 24) /* Master 6 Priority */
#define AT91_MATRIX_M7PR (3 << 28) /* Master 7 Priority */
#define AT91_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */
#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */
#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
#define AT91_MATRIX_RCB2 (1 << 2)
#define AT91_MATRIX_RCB3 (1 << 3)
#define AT91_MATRIX_RCB4 (1 << 4)
#define AT91_MATRIX_RCB5 (1 << 5)
#define AT91_MATRIX_RCB6 (1 << 6)
#define AT91_MATRIX_RCB7 (1 << 7)
#define AT91_MATRIX_RCB8 (1 << 8)
#define AT91_MATRIX_TCMR (AT91_MATRIX + 0x114) /* TCM Configuration Register */
#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */
#define AT91_MATRIX_ITCM_0 (0 << 0)
#define AT91_MATRIX_ITCM_16 (5 << 0)
#define AT91_MATRIX_ITCM_32 (6 << 0)
#define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */
#define AT91_MATRIX_DTCM_0 (0 << 4)
#define AT91_MATRIX_DTCM_16 (5 << 4)
#define AT91_MATRIX_DTCM_32 (6 << 4)
#define AT91_MATRIX_EBI0CSA (AT91_MATRIX + 0x120) /* EBI0 Chip Select Assignment Register */
#define AT91_MATRIX_EBI0_CS1A (1 << 1) /* Chip Select 1 Assignment */
#define AT91_MATRIX_EBI0_CS1A_SMC (0 << 1)
#define AT91_MATRIX_EBI0_CS1A_SDRAMC (1 << 1)
#define AT91_MATRIX_EBI0_CS3A (1 << 3) /* Chip Select 3 Assignment */
#define AT91_MATRIX_EBI0_CS3A_SMC (0 << 3)
#define AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA (1 << 3)
#define AT91_MATRIX_EBI0_CS4A (1 << 4) /* Chip Select 4 Assignment */
#define AT91_MATRIX_EBI0_CS4A_SMC (0 << 4)
#define AT91_MATRIX_EBI0_CS4A_SMC_CF1 (1 << 4)
#define AT91_MATRIX_EBI0_CS5A (1 << 5) /* Chip Select 5 Assignment */
#define AT91_MATRIX_EBI0_CS5A_SMC (0 << 5)
#define AT91_MATRIX_EBI0_CS5A_SMC_CF2 (1 << 5)
#define AT91_MATRIX_EBI0_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
#define AT91_MATRIX_EBI0_VDDIOMSEL (1 << 16) /* Memory voltage selection */
#define AT91_MATRIX_EBI0_VDDIOMSEL_1_8V (0 << 16)
#define AT91_MATRIX_EBI0_VDDIOMSEL_3_3V (1 << 16)
#define AT91_MATRIX_EBI1CSA (AT91_MATRIX + 0x124) /* EBI1 Chip Select Assignment Register */
#define AT91_MATRIX_EBI1_CS1A (1 << 1) /* Chip Select 1 Assignment */
#define AT91_MATRIX_EBI1_CS1A_SMC (0 << 1)
#define AT91_MATRIX_EBI1_CS1A_SDRAMC (1 << 1)
#define AT91_MATRIX_EBI1_CS2A (1 << 3) /* Chip Select 3 Assignment */
#define AT91_MATRIX_EBI1_CS2A_SMC (0 << 3)
#define AT91_MATRIX_EBI1_CS2A_SMC_SMARTMEDIA (1 << 3)
#define AT91_MATRIX_EBI1_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
#define AT91_MATRIX_EBI1_VDDIOMSEL (1 << 16) /* Memory voltage selection */
#define AT91_MATRIX_EBI1_VDDIOMSEL_1_8V (0 << 16)
#define AT91_MATRIX_EBI1_VDDIOMSEL_3_3V (1 << 16)
#endif

115
include/asm-arm/arch-at91sam9/at91sam9rl.h Normal file
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@@ -0,0 +1,115 @@
/*
* [origin: Linux kernel include/asm-arm/arch-at91/at91sam9rl.h]
*
* Copyright (C) 2007 Atmel Corporation
*
* Common definitions.
* Based on AT91SAM9RL datasheet revision A. (Preliminary)
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*/
#ifndef AT91SAM9RL_H
#define AT91SAM9RL_H
/*
* Peripheral identifiers/interrupts.
*/
#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
#define AT91_ID_SYS 1 /* System Controller */
#define AT91SAM9RL_ID_PIOA 2 /* Parallel IO Controller A */
#define AT91SAM9RL_ID_PIOB 3 /* Parallel IO Controller B */
#define AT91SAM9RL_ID_PIOC 4 /* Parallel IO Controller C */
#define AT91SAM9RL_ID_PIOD 5 /* Parallel IO Controller D */
#define AT91SAM9RL_ID_US0 6 /* USART 0 */
#define AT91SAM9RL_ID_US1 7 /* USART 1 */
#define AT91SAM9RL_ID_US2 8 /* USART 2 */
#define AT91SAM9RL_ID_US3 9 /* USART 3 */
#define AT91SAM9RL_ID_MCI 10 /* Multimedia Card Interface */
#define AT91SAM9RL_ID_TWI0 11 /* TWI 0 */
#define AT91SAM9RL_ID_TWI1 12 /* TWI 1 */
#define AT91SAM9RL_ID_SPI 13 /* Serial Peripheral Interface */
#define AT91SAM9RL_ID_SSC0 14 /* Serial Synchronous Controller 0 */
#define AT91SAM9RL_ID_SSC1 15 /* Serial Synchronous Controller 1 */
#define AT91SAM9RL_ID_TC0 16 /* Timer Counter 0 */
#define AT91SAM9RL_ID_TC1 17 /* Timer Counter 1 */
#define AT91SAM9RL_ID_TC2 18 /* Timer Counter 2 */
#define AT91SAM9RL_ID_PWMC 19 /* Pulse Width Modulation Controller */
#define AT91SAM9RL_ID_TSC 20 /* Touch Screen Controller */
#define AT91SAM9RL_ID_DMA 21 /* DMA Controller */
#define AT91SAM9RL_ID_UDPHS 22 /* USB Device HS */
#define AT91SAM9RL_ID_LCDC 23 /* LCD Controller */
#define AT91SAM9RL_ID_AC97C 24 /* AC97 Controller */
#define AT91SAM9RL_ID_IRQ0 31 /* Advanced Interrupt Controller (IRQ0) */
/*
* User Peripheral physical base addresses.
*/
#define AT91SAM9RL_BASE_TCB0 0xfffa0000
#define AT91SAM9RL_BASE_TC0 0xfffa0000
#define AT91SAM9RL_BASE_TC1 0xfffa0040
#define AT91SAM9RL_BASE_TC2 0xfffa0080
#define AT91SAM9RL_BASE_MCI 0xfffa4000
#define AT91SAM9RL_BASE_TWI0 0xfffa8000
#define AT91SAM9RL_BASE_TWI1 0xfffac000
#define AT91SAM9RL_BASE_US0 0xfffb0000
#define AT91SAM9RL_BASE_US1 0xfffb4000
#define AT91SAM9RL_BASE_US2 0xfffb8000
#define AT91SAM9RL_BASE_US3 0xfffbc000
#define AT91SAM9RL_BASE_SSC0 0xfffc0000
#define AT91SAM9RL_BASE_SSC1 0xfffc4000
#define AT91SAM9RL_BASE_PWMC 0xfffc8000
#define AT91SAM9RL_BASE_SPI 0xfffcc000
#define AT91SAM9RL_BASE_TSC 0xfffd0000
#define AT91SAM9RL_BASE_UDPHS 0xfffd4000
#define AT91SAM9RL_BASE_AC97C 0xfffd8000
#define AT91_BASE_SYS 0xffffc000
/*
* System Peripherals (offset from AT91_BASE_SYS)
*/
#define AT91_DMA (0xffffe600 - AT91_BASE_SYS)
#define AT91_ECC (0xffffe800 - AT91_BASE_SYS)
#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS)
#define AT91_SMC (0xffffec00 - AT91_BASE_SYS)
#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
#define AT91_CCFG (0xffffef10 - AT91_BASE_SYS)
#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
#define AT91_PIOA (0xfffff400 - AT91_BASE_SYS)
#define AT91_PIOB (0xfffff600 - AT91_BASE_SYS)
#define AT91_PIOC (0xfffff800 - AT91_BASE_SYS)
#define AT91_PIOD (0xfffffa00 - AT91_BASE_SYS)
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS)
#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
#define AT91_SCKCR (0xfffffd50 - AT91_BASE_SYS)
#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
#define AT91_RTC (0xfffffe00 - AT91_BASE_SYS)
#define AT91_USART0 AT91SAM9RL_BASE_US0
#define AT91_USART1 AT91SAM9RL_BASE_US1
#define AT91_USART2 AT91SAM9RL_BASE_US2
#define AT91_USART3 AT91SAM9RL_BASE_US3
/*
* Internal Memory.
*/
#define AT91SAM9RL_SRAM_BASE 0x00300000 /* Internal SRAM base address */
#define AT91SAM9RL_SRAM_SIZE SZ_16K /* Internal SRAM size (16Kb) */
#define AT91SAM9RL_ROM_BASE 0x00400000 /* Internal ROM base address */
#define AT91SAM9RL_ROM_SIZE (2 * SZ_16K) /* Internal ROM size (32Kb) */
#define AT91SAM9RL_LCDC_BASE 0x00500000 /* LCD Controller */
#define AT91SAM9RL_UDPHS_BASE 0x00600000 /* USB Device HS controller */
#endif

96
include/asm-arm/arch-at91sam9/at91sam9rl_matrix.h Normal file
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@@ -0,0 +1,96 @@
/*
* [origin: Linux kernel include/asm-arm/arch-at91/at91sam9rl_matrix.h]
*
* Copyright (C) 2007 Atmel Corporation
*
* Memory Controllers (MATRIX, EBI) - System peripherals registers.
* Based on AT91SAM9RL datasheet revision A. (Preliminary)
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*/
#ifndef AT91SAM9RL_MATRIX_H
#define AT91SAM9RL_MATRIX_H
#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */
#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */
#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */
#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */
#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */
#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */
#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
#define AT91_MATRIX_ULBT_FOUR (2 << 0)
#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */
#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */
#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */
#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */
#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */
#define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */
#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */
#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */
#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */
#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */
#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */
#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */
#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */
#define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */
#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */
#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */
#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
#define AT91_MATRIX_RCB2 (1 << 2)
#define AT91_MATRIX_RCB3 (1 << 3)
#define AT91_MATRIX_RCB4 (1 << 4)
#define AT91_MATRIX_RCB5 (1 << 5)
#define AT91_MATRIX_TCMR (AT91_MATRIX + 0x114) /* TCM Configuration Register */
#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */
#define AT91_MATRIX_ITCM_0 (0 << 0)
#define AT91_MATRIX_ITCM_16 (5 << 0)
#define AT91_MATRIX_ITCM_32 (6 << 0)
#define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */
#define AT91_MATRIX_DTCM_0 (0 << 4)
#define AT91_MATRIX_DTCM_16 (5 << 4)
#define AT91_MATRIX_DTCM_32 (6 << 4)
#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x120) /* EBI0 Chip Select Assignment Register */
#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */
#define AT91_MATRIX_CS1A_SMC (0 << 1)
#define AT91_MATRIX_CS1A_SDRAMC (1 << 1)
#define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */
#define AT91_MATRIX_CS3A_SMC (0 << 3)
#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
#define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */
#define AT91_MATRIX_CS4A_SMC (0 << 4)
#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4)
#define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */
#define AT91_MATRIX_CS5A_SMC (0 << 5)
#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5)
#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
#define AT91_MATRIX_VDDIOMSEL (1 << 16) /* Memory voltage selection */
#define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16)
#define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16)
#endif

6
include/asm-arm/arch-at91sam9/clk.h
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@@ -36,4 +36,10 @@ static inline unsigned long get_usart_clk_rate(unsigned int dev_id)
return AT91_MASTER_CLOCK;
}
static inline unsigned long get_lcdc_clk_rate(unsigned int dev_id)
{
return AT91_MASTER_CLOCK;
}
#endif /* __ASM_ARM_ARCH_CLK_H__ */

20
include/asm-arm/arch-at91sam9/hardware.h
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@@ -26,10 +26,19 @@
#define AT91_PMC_UHP AT91SAM926x_PMC_UHP
#elif defined(CONFIG_AT91SAM9261)
#include <asm/arch/at91sam9261.h>
#define AT91_BASE_SPI AT91SAM9261_BASE_SPI0
#define AT91_ID_UHP AT91SAM9261_ID_UHP
#define AT91_PMC_UHP AT91SAM926x_PMC_UHP
#elif defined(CONFIG_AT91SAM9263)
#include <asm/arch/at91sam9263.h>
#define AT91_BASE_EMAC AT91SAM9263_BASE_EMAC
#define AT91_BASE_SPI AT91SAM9263_BASE_SPI0
#define AT91_ID_UHP AT91SAM9263_ID_UHP
#define AT91_PMC_UHP AT91SAM926x_PMC_UHP
#elif defined(CONFIG_AT91SAM9RL)
#include <asm/arch/at91sam9rl.h>
#define AT91_BASE_SPI AT91SAM9RL_BASE_SPI
#define AT91_ID_UHP AT91SAM9RL_ID_UHP
#elif defined(CONFIG_AT91CAP9)
#include <asm/arch/at91cap9.h>
#define AT91_BASE_EMAC AT91CAP9_BASE_EMAC
@@ -42,15 +51,4 @@
#error "Unsupported AT91 processor"
#endif
/*
* container_of - cast a member of a structure out to the containing structure
*
* @ptr: the pointer to the member.
* @type: the type of the container struct this is embedded in.
* @member: the name of the member within the struct.
*/
#define container_of(ptr, type, member) ({ \
const typeof(((type *)0)->member) *__mptr = (ptr); \
(type *)((char *)__mptr - offsetof(type, member)); })
#endif

1
include/asm-avr32/arch-at32ap700x/chip-features.h
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@@ -25,6 +25,7 @@
/* Currently, all the AP700x chips have these */
#define AT32AP700x_CHIP_HAS_USART
#define AT32AP700x_CHIP_HAS_MMCI
#define AT32AP700x_CHIP_HAS_SPI
/* Only AP7000 has ethernet interface */
#ifdef CONFIG_AT32AP7000

10
include/asm-avr32/arch-at32ap700x/clk.h
View File

@@ -58,7 +58,7 @@ static inline unsigned long get_usart_clk_rate(unsigned int dev_id)
return get_pba_clk_rate();
}
#endif
#ifdef AT32AP700x_CHIP_HAS_USART
#ifdef AT32AP700x_CHIP_HAS_MACB
static inline unsigned long get_macb_pclk_rate(unsigned int dev_id)
{
return get_pbb_clk_rate();
@@ -74,6 +74,14 @@ static inline unsigned long get_mci_clk_rate(void)
return get_pbb_clk_rate();
}
#endif
#ifdef AT32AP700x_CHIP_HAS_SPI
static inline unsigned long get_spi_clk_rate(unsigned int dev_id)
{
return get_pba_clk_rate();
}
#endif
extern void clk_init(void);
/* Board code may need the SDRAM base clock as a compile-time constant */
#define SDRAMC_BUS_HZ (MAIN_CLK_RATE >> CFG_CLKDIV_HSB)

4
include/asm-avr32/arch-at32ap700x/gpio.h
View File

@@ -216,5 +216,9 @@ void gpio_enable_macb1(void);
#ifdef AT32AP700x_CHIP_HAS_MMCI
void gpio_enable_mmci(void);
#endif
#ifdef AT32AP700x_CHIP_HAS_SPI
void gpio_enable_spi0(unsigned long cs_mask);
void gpio_enable_spi1(unsigned long cs_mask);
#endif
#endif /* __ASM_AVR32_ARCH_GPIO_H__ */

61
include/asm-avr32/arch-at32ap700x/hmatrix.h Normal file
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@@ -0,0 +1,61 @@
/*
* Copyright (C) 2008 Atmel Corporation
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __ASM_AVR32_ARCH_HMATRIX_H__
#define __ASM_AVR32_ARCH_HMATRIX_H__
#include <asm/hmatrix-common.h>
/* Bitfields in SFR4 (EBI) */
#define HMATRIX_EBI_SDRAM_ENABLE_OFFSET 1
#define HMATRIX_EBI_SDRAM_ENABLE_SIZE 1
#define HMATRIX_EBI_NAND_ENABLE_OFFSET 3
#define HMATRIX_EBI_NAND_ENABLE_SIZE 1
#define HMATRIX_EBI_CF0_ENABLE_OFFSET 4
#define HMATRIX_EBI_CF0_ENABLE_SIZE 1
#define HMATRIX_EBI_CF1_ENABLE_OFFSET 5
#define HMATRIX_EBI_CF1_ENABLE_SIZE 1
#define HMATRIX_EBI_PULLUP_DISABLE_OFFSET 8
#define HMATRIX_EBI_PULLUP_DISABLE_SIZE 1
/* HSB masters */
#define HMATRIX_MASTER_CPU_DCACHE 0
#define HMATRIX_MASTER_CPU_ICACHE 1
#define HMATRIX_MASTER_PDC 2
#define HMATRIX_MASTER_ISI 3
#define HMATRIX_MASTER_USBA 4
#define HMATRIX_MASTER_LCDC 5
#define HMATRIX_MASTER_MACB0 6
#define HMATRIX_MASTER_MACB1 7
#define HMATRIX_MASTER_DMACA_M0 8
#define HMATRIX_MASTER_DMACA_M1 9
/* HSB slaves */
#define HMATRIX_SLAVE_SRAM0 0
#define HMATRIX_SLAVE_SRAM1 1
#define HMATRIX_SLAVE_PBA 2
#define HMATRIX_SLAVE_PBB 3
#define HMATRIX_SLAVE_EBI 4
#define HMATRIX_SLAVE_USBA 5
#define HMATRIX_SLAVE_LCDC 6
#define HMATRIX_SLAVE_DMACA 7
#endif /* __ASM_AVR32_ARCH_HMATRIX_H__ */

232
include/asm-avr32/arch-at32ap700x/hmatrix2.h
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@@ -1,232 +0,0 @@
/*
* Register definition for the High-speed Bus Matrix
*/
#ifndef __ASM_AVR32_HMATRIX2_H__
#define __ASM_AVR32_HMATRIX2_H__
/* HMATRIX2 register offsets */
#define HMATRIX2_MCFG0 0x0000
#define HMATRIX2_MCFG1 0x0004
#define HMATRIX2_MCFG2 0x0008
#define HMATRIX2_MCFG3 0x000c
#define HMATRIX2_MCFG4 0x0010
#define HMATRIX2_MCFG5 0x0014
#define HMATRIX2_MCFG6 0x0018
#define HMATRIX2_MCFG7 0x001c
#define HMATRIX2_MCFG8 0x0020
#define HMATRIX2_MCFG9 0x0024
#define HMATRIX2_MCFG10 0x0028
#define HMATRIX2_MCFG11 0x002c
#define HMATRIX2_MCFG12 0x0030
#define HMATRIX2_MCFG13 0x0034
#define HMATRIX2_MCFG14 0x0038
#define HMATRIX2_MCFG15 0x003c
#define HMATRIX2_SCFG0 0x0040
#define HMATRIX2_SCFG1 0x0044
#define HMATRIX2_SCFG2 0x0048
#define HMATRIX2_SCFG3 0x004c
#define HMATRIX2_SCFG4 0x0050
#define HMATRIX2_SCFG5 0x0054
#define HMATRIX2_SCFG6 0x0058
#define HMATRIX2_SCFG7 0x005c
#define HMATRIX2_SCFG8 0x0060
#define HMATRIX2_SCFG9 0x0064
#define HMATRIX2_SCFG10 0x0068
#define HMATRIX2_SCFG11 0x006c
#define HMATRIX2_SCFG12 0x0070
#define HMATRIX2_SCFG13 0x0074
#define HMATRIX2_SCFG14 0x0078
#define HMATRIX2_SCFG15 0x007c
#define HMATRIX2_PRAS0 0x0080
#define HMATRIX2_PRBS0 0x0084
#define HMATRIX2_PRAS1 0x0088
#define HMATRIX2_PRBS1 0x008c
#define HMATRIX2_PRAS2 0x0090
#define HMATRIX2_PRBS2 0x0094
#define HMATRIX2_PRAS3 0x0098
#define HMATRIX2_PRBS3 0x009c
#define HMATRIX2_PRAS4 0x00a0
#define HMATRIX2_PRBS4 0x00a4
#define HMATRIX2_PRAS5 0x00a8
#define HMATRIX2_PRBS5 0x00ac
#define HMATRIX2_PRAS6 0x00b0
#define HMATRIX2_PRBS6 0x00b4
#define HMATRIX2_PRAS7 0x00b8
#define HMATRIX2_PRBS7 0x00bc
#define HMATRIX2_PRAS8 0x00c0
#define HMATRIX2_PRBS8 0x00c4
#define HMATRIX2_PRAS9 0x00c8
#define HMATRIX2_PRBS9 0x00cc
#define HMATRIX2_PRAS10 0x00d0
#define HMATRIX2_PRBS10 0x00d4
#define HMATRIX2_PRAS11 0x00d8
#define HMATRIX2_PRBS11 0x00dc
#define HMATRIX2_PRAS12 0x00e0
#define HMATRIX2_PRBS12 0x00e4
#define HMATRIX2_PRAS13 0x00e8
#define HMATRIX2_PRBS13 0x00ec
#define HMATRIX2_PRAS14 0x00f0
#define HMATRIX2_PRBS14 0x00f4
#define HMATRIX2_PRAS15 0x00f8
#define HMATRIX2_PRBS15 0x00fc
#define HMATRIX2_MRCR 0x0100
#define HMATRIX2_SFR0 0x0110
#define HMATRIX2_SFR1 0x0114
#define HMATRIX2_SFR2 0x0118
#define HMATRIX2_SFR3 0x011c
#define HMATRIX2_SFR4 0x0120
#define HMATRIX2_SFR5 0x0124
#define HMATRIX2_SFR6 0x0128
#define HMATRIX2_SFR7 0x012c
#define HMATRIX2_SFR8 0x0130
#define HMATRIX2_SFR9 0x0134
#define HMATRIX2_SFR10 0x0138
#define HMATRIX2_SFR11 0x013c
#define HMATRIX2_SFR12 0x0140
#define HMATRIX2_SFR13 0x0144
#define HMATRIX2_SFR14 0x0148
#define HMATRIX2_SFR15 0x014c
#define HMATRIX2_VERSION 0x01fc
/* Bitfields in MCFG0 */
#define HMATRIX2_ULBT_OFFSET 0
#define HMATRIX2_ULBT_SIZE 3
/* Bitfields in SCFG0 */
#define HMATRIX2_SLOT_CYCLE_OFFSET 0
#define HMATRIX2_SLOT_CYCLE_SIZE 8
#define HMATRIX2_DEFMSTR_TYPE_OFFSET 16
#define HMATRIX2_DEFMSTR_TYPE_SIZE 2
#define HMATRIX2_FIXED_DEFMSTR_OFFSET 18
#define HMATRIX2_FIXED_DEFMSTR_SIZE 4
#define HMATRIX2_ARBT_OFFSET 24
#define HMATRIX2_ARBT_SIZE 2
/* Bitfields in PRAS0 */
#define HMATRIX2_M0PR_OFFSET 0
#define HMATRIX2_M0PR_SIZE 4
#define HMATRIX2_M1PR_OFFSET 4
#define HMATRIX2_M1PR_SIZE 4
#define HMATRIX2_M2PR_OFFSET 8
#define HMATRIX2_M2PR_SIZE 4
#define HMATRIX2_M3PR_OFFSET 12
#define HMATRIX2_M3PR_SIZE 4
#define HMATRIX2_M4PR_OFFSET 16
#define HMATRIX2_M4PR_SIZE 4
#define HMATRIX2_M5PR_OFFSET 20
#define HMATRIX2_M5PR_SIZE 4
#define HMATRIX2_M6PR_OFFSET 24
#define HMATRIX2_M6PR_SIZE 4
#define HMATRIX2_M7PR_OFFSET 28
#define HMATRIX2_M7PR_SIZE 4
/* Bitfields in PRBS0 */
#define HMATRIX2_M8PR_OFFSET 0
#define HMATRIX2_M8PR_SIZE 4
#define HMATRIX2_M9PR_OFFSET 4
#define HMATRIX2_M9PR_SIZE 4
#define HMATRIX2_M10PR_OFFSET 8
#define HMATRIX2_M10PR_SIZE 4
#define HMATRIX2_M11PR_OFFSET 12
#define HMATRIX2_M11PR_SIZE 4
#define HMATRIX2_M12PR_OFFSET 16
#define HMATRIX2_M12PR_SIZE 4
#define HMATRIX2_M13PR_OFFSET 20
#define HMATRIX2_M13PR_SIZE 4
#define HMATRIX2_M14PR_OFFSET 24
#define HMATRIX2_M14PR_SIZE 4
#define HMATRIX2_M15PR_OFFSET 28
#define HMATRIX2_M15PR_SIZE 4
/* Bitfields in MRCR */
#define HMATRIX2_RBC0_OFFSET 0
#define HMATRIX2_RBC0_SIZE 1
#define HMATRIX2_RBC1_OFFSET 1
#define HMATRIX2_RBC1_SIZE 1
#define HMATRIX2_RBC2_OFFSET 2
#define HMATRIX2_RBC2_SIZE 1
#define HMATRIX2_RBC3_OFFSET 3
#define HMATRIX2_RBC3_SIZE 1
#define HMATRIX2_RBC4_OFFSET 4
#define HMATRIX2_RBC4_SIZE 1
#define HMATRIX2_RBC5_OFFSET 5
#define HMATRIX2_RBC5_SIZE 1
#define HMATRIX2_RBC6_OFFSET 6
#define HMATRIX2_RBC6_SIZE 1
#define HMATRIX2_RBC7_OFFSET 7
#define HMATRIX2_RBC7_SIZE 1
#define HMATRIX2_RBC8_OFFSET 8
#define HMATRIX2_RBC8_SIZE 1
#define HMATRIX2_RBC9_OFFSET 9
#define HMATRIX2_RBC9_SIZE 1
#define HMATRIX2_RBC10_OFFSET 10
#define HMATRIX2_RBC10_SIZE 1
#define HMATRIX2_RBC11_OFFSET 11
#define HMATRIX2_RBC11_SIZE 1
#define HMATRIX2_RBC12_OFFSET 12
#define HMATRIX2_RBC12_SIZE 1
#define HMATRIX2_RBC13_OFFSET 13
#define HMATRIX2_RBC13_SIZE 1
#define HMATRIX2_RBC14_OFFSET 14
#define HMATRIX2_RBC14_SIZE 1
#define HMATRIX2_RBC15_OFFSET 15
#define HMATRIX2_RBC15_SIZE 1
/* Bitfields in SFR0 */
#define HMATRIX2_SFR_OFFSET 0
#define HMATRIX2_SFR_SIZE 32
/* Bitfields in SFR4 */
#define HMATRIX2_CS1A_OFFSET 1
#define HMATRIX2_CS1A_SIZE 1
#define HMATRIX2_CS3A_OFFSET 3
#define HMATRIX2_CS3A_SIZE 1
#define HMATRIX2_CS4A_OFFSET 4
#define HMATRIX2_CS4A_SIZE 1
#define HMATRIX2_CS5A_OFFSET 5
#define HMATRIX2_CS5A_SIZE 1
#define HMATRIX2_DBPUC_OFFSET 8
#define HMATRIX2_DBPUC_SIZE 1
/* Bitfields in VERSION */
#define HMATRIX2_VERSION_OFFSET 0
#define HMATRIX2_VERSION_SIZE 12
#define HMATRIX2_MFN_OFFSET 16
#define HMATRIX2_MFN_SIZE 3
/* Constants for ULBT */
#define HMATRIX2_ULBT_INFINITE 0
#define HMATRIX2_ULBT_SINGLE 1
#define HMATRIX2_ULBT_FOUR_BEAT 2
#define HMATRIX2_ULBT_SIXTEEN_BEAT 4
/* Constants for DEFMSTR_TYPE */
#define HMATRIX2_DEFMSTR_TYPE_NO_DEFAULT 0
#define HMATRIX2_DEFMSTR_TYPE_LAST_DEFAULT 1
#define HMATRIX2_DEFMSTR_TYPE_FIXED_DEFAULT 2
/* Constants for ARBT */
#define HMATRIX2_ARBT_ROUND_ROBIN 0
#define HMATRIX2_ARBT_FIXED_PRIORITY 1
/* Bit manipulation macros */
#define HMATRIX2_BIT(name) \
(1 << HMATRIX2_##name##_OFFSET)
#define HMATRIX2_BF(name,value) \
(((value) & ((1 << HMATRIX2_##name##_SIZE) - 1)) \
<< HMATRIX2_##name##_OFFSET)
#define HMATRIX2_BFEXT(name,value) \
(((value) >> HMATRIX2_##name##_OFFSET) \
& ((1 << HMATRIX2_##name##_SIZE) - 1))
#define HMATRIX2_BFINS(name,value,old) \
(((old) & ~(((1 << HMATRIX2_##name##_SIZE) - 1) \
<< HMATRIX2_##name##_OFFSET)) \
| HMATRIX2_BF(name,value))
/* Register access macros */
#define hmatrix2_readl(reg) \
readl((void *)HMATRIX_BASE + HMATRIX2_##reg)
#define hmatrix2_writel(reg,value) \
writel((value), (void *)HMATRIX_BASE + HMATRIX2_##reg)
#endif /* __ASM_AVR32_HMATRIX2_H__ */

20
include/asm-avr32/arch-at32ap700x/memory-map.h
View File

@@ -22,6 +22,26 @@
#ifndef __AT32AP7000_MEMORY_MAP_H__
#define __AT32AP7000_MEMORY_MAP_H__
/* Internal and external memories */
#define EBI_SRAM_CS0_BASE 0x00000000
#define EBI_SRAM_CS0_SIZE 0x04000000
#define EBI_SRAM_CS4_BASE 0x04000000
#define EBI_SRAM_CS4_SIZE 0x04000000
#define EBI_SRAM_CS2_BASE 0x08000000
#define EBI_SRAM_CS2_SIZE 0x04000000
#define EBI_SRAM_CS3_BASE 0x0c000000
#define EBI_SRAM_CS3_SIZE 0x04000000
#define EBI_SRAM_CS1_BASE 0x10000000
#define EBI_SRAM_CS1_SIZE 0x10000000
#define EBI_SRAM_CS5_BASE 0x20000000
#define EBI_SRAM_CS5_SIZE 0x04000000
#define EBI_SDRAM_BASE EBI_SRAM_CS1_BASE
#define EBI_SDRAM_SIZE EBI_SRAM_CS1_SIZE
#define INTERNAL_SRAM_BASE 0x24000000
#define INTERNAL_SRAM_SIZE 0x00008000
/* Devices on the High Speed Bus (HSB) */
#define LCDC_BASE 0xFF000000
#define DMAC_BASE 0xFF200000

131
include/asm-avr32/hmatrix-common.h Normal file
View File

@@ -0,0 +1,131 @@
/*
* Copyright (C) 2008 Atmel Corporation
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __ASM_AVR32_HMATRIX_COMMON_H__
#define __ASM_AVR32_HMATRIX_COMMON_H__
/* HMATRIX register offsets */
struct hmatrix_regs {
u32 MCFG[16];
u32 SCFG[16];
struct {
u32 A;
u32 B;
} PRS[16];
u32 MRCR;
u32 __reserved[3];
u32 SFR[16];
};
/* Bitfields in MCFG */
#define HMATRIX_ULBT_OFFSET 0
#define HMATRIX_ULBT_SIZE 3
/* Bitfields in SCFG */
#define HMATRIX_SLOT_CYCLE_OFFSET 0
#define HMATRIX_SLOT_CYCLE_SIZE 8
#define HMATRIX_DEFMSTR_TYPE_OFFSET 16
#define HMATRIX_DEFMSTR_TYPE_SIZE 2
#define HMATRIX_FIXED_DEFMSTR_OFFSET 18
#define HMATRIX_FIXED_DEFMSTR_SIZE 4
#define HMATRIX_ARBT_OFFSET 24
#define HMATRIX_ARBT_SIZE 1
/* Bitfields in PRS.A */
#define HMATRIX_M0PR_OFFSET 0
#define HMATRIX_M0PR_SIZE 4
#define HMATRIX_M1PR_OFFSET 4
#define HMATRIX_M1PR_SIZE 4
#define HMATRIX_M2PR_OFFSET 8
#define HMATRIX_M2PR_SIZE 4
#define HMATRIX_M3PR_OFFSET 12
#define HMATRIX_M3PR_SIZE 4
#define HMATRIX_M4PR_OFFSET 16
#define HMATRIX_M4PR_SIZE 4
#define HMATRIX_M5PR_OFFSET 20
#define HMATRIX_M5PR_SIZE 4
#define HMATRIX_M6PR_OFFSET 24
#define HMATRIX_M6PR_SIZE 4
#define HMATRIX_M7PR_OFFSET 28
#define HMATRIX_M7PR_SIZE 4
/* Bitfields in PRS.B */
#define HMATRIX_M8PR_OFFSET 0
#define HMATRIX_M8PR_SIZE 4
#define HMATRIX_M9PR_OFFSET 4
#define HMATRIX_M9PR_SIZE 4
#define HMATRIX_M10PR_OFFSET 8
#define HMATRIX_M10PR_SIZE 4
#define HMATRIX_M11PR_OFFSET 12
#define HMATRIX_M11PR_SIZE 4
#define HMATRIX_M12PR_OFFSET 16
#define HMATRIX_M12PR_SIZE 4
#define HMATRIX_M13PR_OFFSET 20
#define HMATRIX_M13PR_SIZE 4
#define HMATRIX_M14PR_OFFSET 24
#define HMATRIX_M14PR_SIZE 4
#define HMATRIX_M15PR_OFFSET 28
#define HMATRIX_M15PR_SIZE 4
/* Constants for ULBT */
#define HMATRIX_ULBT_INFINITE 0
#define HMATRIX_ULBT_SINGLE 1
#define HMATRIX_ULBT_FOUR_BEAT 2
#define HMATRIX_ULBT_EIGHT_BEAT 3
#define HMATRIX_ULBT_SIXTEEN_BEAT 4
/* Constants for DEFMSTR_TYPE */
#define HMATRIX_DEFMSTR_TYPE_NO_DEFAULT 0
#define HMATRIX_DEFMSTR_TYPE_LAST_DEFAULT 1
#define HMATRIX_DEFMSTR_TYPE_FIXED_DEFAULT 2
/* Constants for ARBT */
#define HMATRIX_ARBT_ROUND_ROBIN 0
#define HMATRIX_ARBT_FIXED_PRIORITY 1
/* Bit manipulation macros */
#define HMATRIX_BIT(name) \
(1 << HMATRIX_##name##_OFFSET)
#define HMATRIX_BF(name,value) \
(((value) & ((1 << HMATRIX_##name##_SIZE) - 1)) \
<< HMATRIX_##name##_OFFSET)
#define HMATRIX_BFEXT(name,value) \
(((value) >> HMATRIX_##name##_OFFSET) \
& ((1 << HMATRIX_##name##_SIZE) - 1))
#define HMATRIX_BFINS(name,value,old) \
(((old) & ~(((1 << HMATRIX_##name##_SIZE) - 1) \
<< HMATRIX_##name##_OFFSET)) \
| HMATRIX_BF(name,value))
/* Register access macros */
#define __hmatrix_reg(reg) \
(((volatile struct hmatrix_regs *)HMATRIX_BASE)->reg)
#define hmatrix_read(reg) \
(__hmatrix_reg(reg))
#define hmatrix_write(reg, value) \
do { __hmatrix_reg(reg) = (value); } while (0)
#define hmatrix_slave_read(slave, reg) \
hmatrix_read(reg[HMATRIX_SLAVE_##slave])
#define hmatrix_slave_write(slave, reg, value) \
hmatrix_write(reg[HMATRIX_SLAVE_##slave], value)
#endif /* __ASM_AVR32_HMATRIX_COMMON_H__ */

27
include/asm-avr32/sdram.h
View File

@@ -22,15 +22,32 @@
#ifndef __ASM_AVR32_SDRAM_H
#define __ASM_AVR32_SDRAM_H
struct sdram_info {
unsigned long phys_addr;
unsigned int row_bits, col_bits, bank_bits;
unsigned int cas, twr, trc, trp, trcd, tras, txsr;
struct sdram_config {
/* Number of data bits. */
enum {
SDRAM_DATA_16BIT,
SDRAM_DATA_32BIT,
} data_bits;
/* Number of address bits */
uint8_t row_bits, col_bits, bank_bits;
/* SDRAM timings in cycles */
uint8_t cas, twr, trc, trp, trcd, tras, txsr;
/* SDRAM refresh period in cycles */
unsigned long refresh_period;
};
extern unsigned long sdram_init(const struct sdram_info *info);
/*
* Attempt to initialize the SDRAM controller using the specified
* parameters. Return the expected size of the memory area based on
* the number of address and data bits.
*
* The caller should verify that the configuration is correct by
* running a memory test, e.g. get_ram_size().
*/
extern unsigned long sdram_init(void *sdram_base,
const struct sdram_config *config);
#endif /* __ASM_AVR32_SDRAM_H */

7
include/asm-avr32/sections.h
View File

@@ -25,15 +25,8 @@
/* References to section boundaries */
extern char _text[], _etext[];
extern char __flashprog_start[], __flashprog_end[];
extern char _data[], __data_lma[], _edata[], __edata_lma[];
extern char __got_start[], __got_lma[], __got_end[];
extern char _end[];
/*
* Everything in .flashprog will be locked in the icache so it doesn't
* get disturbed when executing flash commands.
*/
#define __flashprog __attribute__((section(".flashprog"), __noinline__))
#endif /* __ASM_AVR32_SECTIONS_H */

11
include/asm-avr32/u-boot.h
View File

@@ -42,15 +42,4 @@ typedef struct bd_info {
#define bi_memstart bi_dram[0].start
#define bi_memsize bi_dram[0].size
/**
* container_of - cast a member of a structure out to the containing structure
*
* @ptr: the pointer to the member.
* @type: the type of the container struct this is embedded in.
* @member: the name of the member within the struct.
*/
#define container_of(ptr, type, member) ({ \
const typeof( ((type *)0)->member ) *__mptr = (ptr); \
(type *)( (char *)__mptr - offsetof(type,member) );})
#endif /* __ASM_U_BOOT_H__ */

143
include/asm-mips/errno.h Normal file
View File

@@ -0,0 +1,143 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1995, 1999, 2001, 2002 by Ralf Baechle
*/
#ifndef _ASM_MIPS_ERRNO_H
#define _ASM_MIPS_ERRNO_H
/*
* These first 34 error codes are from Linux 2.6, <asm-generic/errno-base.h>
*/
#define EPERM 1 /* Operation not permitted */
#define ENOENT 2 /* No such file or directory */
#define ESRCH 3 /* No such process */
#define EINTR 4 /* Interrupted system call */
#define EIO 5 /* I/O error */
#define ENXIO 6 /* No such device or address */
#define E2BIG 7 /* Argument list too long */
#define ENOEXEC 8 /* Exec format error */
#define EBADF 9 /* Bad file number */
#define ECHILD 10 /* No child processes */
#define EAGAIN 11 /* Try again */
#define ENOMEM 12 /* Out of memory */
#define EACCES 13 /* Permission denied */
#define EFAULT 14 /* Bad address */
#define ENOTBLK 15 /* Block device required */
#define EBUSY 16 /* Device or resource busy */
#define EEXIST 17 /* File exists */
#define EXDEV 18 /* Cross-device link */
#define ENODEV 19 /* No such device */
#define ENOTDIR 20 /* Not a directory */
#define EISDIR 21 /* Is a directory */
#define EINVAL 22 /* Invalid argument */
#define ENFILE 23 /* File table overflow */
#define EMFILE 24 /* Too many open files */
#define ENOTTY 25 /* Not a typewriter */
#define ETXTBSY 26 /* Text file busy */
#define EFBIG 27 /* File too large */
#define ENOSPC 28 /* No space left on device */
#define ESPIPE 29 /* Illegal seek */
#define EROFS 30 /* Read-only file system */
#define EMLINK 31 /* Too many links */
#define EPIPE 32 /* Broken pipe */
#define EDOM 33 /* Math argument out of domain of func */
#define ERANGE 34 /* Math result not representable */
/*
* These error numbers are intended to be MIPS ABI compatible
*/
#define ENOMSG 35 /* No message of desired type */
#define EIDRM 36 /* Identifier removed */
#define ECHRNG 37 /* Channel number out of range */
#define EL2NSYNC 38 /* Level 2 not synchronized */
#define EL3HLT 39 /* Level 3 halted */
#define EL3RST 40 /* Level 3 reset */
#define ELNRNG 41 /* Link number out of range */
#define EUNATCH 42 /* Protocol driver not attached */
#define ENOCSI 43 /* No CSI structure available */
#define EL2HLT 44 /* Level 2 halted */
#define EDEADLK 45 /* Resource deadlock would occur */
#define ENOLCK 46 /* No record locks available */
#define EBADE 50 /* Invalid exchange */
#define EBADR 51 /* Invalid request descriptor */
#define EXFULL 52 /* Exchange full */
#define ENOANO 53 /* No anode */
#define EBADRQC 54 /* Invalid request code */
#define EBADSLT 55 /* Invalid slot */
#define EDEADLOCK 56 /* File locking deadlock error */
#define EBFONT 59 /* Bad font file format */
#define ENOSTR 60 /* Device not a stream */
#define ENODATA 61 /* No data available */
#define ETIME 62 /* Timer expired */
#define ENOSR 63 /* Out of streams resources */
#define ENONET 64 /* Machine is not on the network */
#define ENOPKG 65 /* Package not installed */
#define EREMOTE 66 /* Object is remote */
#define ENOLINK 67 /* Link has been severed */
#define EADV 68 /* Advertise error */
#define ESRMNT 69 /* Srmount error */
#define ECOMM 70 /* Communication error on send */
#define EPROTO 71 /* Protocol error */
#define EDOTDOT 73 /* RFS specific error */
#define EMULTIHOP 74 /* Multihop attempted */
#define EBADMSG 77 /* Not a data message */
#define ENAMETOOLONG 78 /* File name too long */
#define EOVERFLOW 79 /* Value too large for defined data type */
#define ENOTUNIQ 80 /* Name not unique on network */
#define EBADFD 81 /* File descriptor in bad state */
#define EREMCHG 82 /* Remote address changed */
#define ELIBACC 83 /* Can not access a needed shared library */
#define ELIBBAD 84 /* Accessing a corrupted shared library */
#define ELIBSCN 85 /* .lib section in a.out corrupted */
#define ELIBMAX 86 /* Attempting to link in too many shared libraries */
#define ELIBEXEC 87 /* Cannot exec a shared library directly */
#define EILSEQ 88 /* Illegal byte sequence */
#define ENOSYS 89 /* Function not implemented */
#define ELOOP 90 /* Too many symbolic links encountered */
#define ERESTART 91 /* Interrupted system call should be restarted */
#define ESTRPIPE 92 /* Streams pipe error */
#define ENOTEMPTY 93 /* Directory not empty */
#define EUSERS 94 /* Too many users */
#define ENOTSOCK 95 /* Socket operation on non-socket */
#define EDESTADDRREQ 96 /* Destination address required */
#define EMSGSIZE 97 /* Message too long */
#define EPROTOTYPE 98 /* Protocol wrong type for socket */
#define ENOPROTOOPT 99 /* Protocol not available */
#define EPROTONOSUPPORT 120 /* Protocol not supported */
#define ESOCKTNOSUPPORT 121 /* Socket type not supported */
#define EOPNOTSUPP 122 /* Operation not supported on transport endpoint */
#define EPFNOSUPPORT 123 /* Protocol family not supported */
#define EAFNOSUPPORT 124 /* Address family not supported by protocol */
#define EADDRINUSE 125 /* Address already in use */
#define EADDRNOTAVAIL 126 /* Cannot assign requested address */
#define ENETDOWN 127 /* Network is down */
#define ENETUNREACH 128 /* Network is unreachable */
#define ENETRESET 129 /* Network dropped connection because of reset */
#define ECONNABORTED 130 /* Software caused connection abort */
#define ECONNRESET 131 /* Connection reset by peer */
#define ENOBUFS 132 /* No buffer space available */
#define EISCONN 133 /* Transport endpoint is already connected */
#define ENOTCONN 134 /* Transport endpoint is not connected */
#define EUCLEAN 135 /* Structure needs cleaning */
#define ENOTNAM 137 /* Not a XENIX named type file */
#define ENAVAIL 138 /* No XENIX semaphores available */
#define EISNAM 139 /* Is a named type file */
#define EREMOTEIO 140 /* Remote I/O error */
#define EINIT 141 /* Reserved */
#define EREMDEV 142 /* Error 142 */
#define ESHUTDOWN 143 /* Cannot send after transport endpoint shutdown */
#define ETOOMANYREFS 144 /* Too many references: cannot splice */
#define ETIMEDOUT 145 /* Connection timed out */
#define ECONNREFUSED 146 /* Connection refused */
#define EHOSTDOWN 147 /* Host is down */
#define EHOSTUNREACH 148 /* No route to host */
#define EWOULDBLOCK EAGAIN /* Operation would block */
#define EALREADY 149 /* Operation already in progress */
#define EINPROGRESS 150 /* Operation now in progress */
#define ESTALE 151 /* Stale NFS file handle */
#define ECANCELED 158 /* AIO operation canceled */
#endif /* _ASM_MIPS_ERRNO_H */

1389
include/asm-mips/mipsregs.h
View File

File diff suppressed because it is too large Load Diff

2
include/asm-ppc/bitops.h
View File

@@ -287,7 +287,7 @@ extern __inline__ int ext2_test_bit(int nr, __const__ void * addr)
#define ext2_find_first_zero_bit(addr, size) \
ext2_find_next_zero_bit((addr), (size), 0)
extern __inline__ unsigned long ext2_find_next_zero_bit(void *addr,
static __inline__ unsigned long ext2_find_next_zero_bit(void *addr,
unsigned long size, unsigned long offset)
{
unsigned int *p = ((unsigned int *) addr) + (offset >> 5);

7
include/asm-ppc/mmu.h
View File

@@ -140,11 +140,16 @@ extern void _tlbia(void); /* invalidate all TLB entries */
typedef enum {
IBAT0 = 0, IBAT1, IBAT2, IBAT3,
DBAT0, DBAT1, DBAT2, DBAT3
DBAT0, DBAT1, DBAT2, DBAT3,
#ifdef CONFIG_HIGH_BATS
IBAT4, IBAT5, IBAT6, IBAT7,
DBAT4, DBAT5, DBAT6, DBAT7
#endif
} ppc_bat_t;
extern int read_bat(ppc_bat_t bat, unsigned long *upper, unsigned long *lower);
extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower);
extern void print_bats(void);
#endif /* __ASSEMBLY__ */

177
include/atmel_lcdc.h Normal file
View File

@@ -0,0 +1,177 @@
/*
* Header file for AT91/AT32 LCD Controller
*
* Data structure and register user interface
*
* Copyright (C) 2007 Atmel Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ATMEL_LCDC_H__
#define __ATMEL_LCDC_H__
#define ATMEL_LCDC_DMABADDR1 0x00
#define ATMEL_LCDC_DMABADDR2 0x04
#define ATMEL_LCDC_DMAFRMPT1 0x08
#define ATMEL_LCDC_DMAFRMPT2 0x0c
#define ATMEL_LCDC_DMAFRMADD1 0x10
#define ATMEL_LCDC_DMAFRMADD2 0x14
#define ATMEL_LCDC_DMAFRMCFG 0x18
#define ATMEL_LCDC_FRSIZE (0x7fffff << 0)
#define ATMEL_LCDC_BLENGTH_OFFSET 24
#define ATMEL_LCDC_BLENGTH (0x7f << ATMEL_LCDC_BLENGTH_OFFSET)
#define ATMEL_LCDC_DMACON 0x1c
#define ATMEL_LCDC_DMAEN (0x1 << 0)
#define ATMEL_LCDC_DMARST (0x1 << 1)
#define ATMEL_LCDC_DMABUSY (0x1 << 2)
#define ATMEL_LCDC_DMAUPDT (0x1 << 3)
#define ATMEL_LCDC_DMA2DEN (0x1 << 4)
#define ATMEL_LCDC_DMA2DCFG 0x20
#define ATMEL_LCDC_ADDRINC_OFFSET 0
#define ATMEL_LCDC_ADDRINC (0xffff)
#define ATMEL_LCDC_PIXELOFF_OFFSET 24
#define ATMEL_LCDC_PIXELOFF (0x1f << 24)
#define ATMEL_LCDC_LCDCON1 0x0800
#define ATMEL_LCDC_BYPASS (1 << 0)
#define ATMEL_LCDC_CLKVAL_OFFSET 12
#define ATMEL_LCDC_CLKVAL (0x1ff << ATMEL_LCDC_CLKVAL_OFFSET)
#define ATMEL_LCDC_LINCNT (0x7ff << 21)
#define ATMEL_LCDC_LCDCON2 0x0804
#define ATMEL_LCDC_DISTYPE (3 << 0)
#define ATMEL_LCDC_DISTYPE_STNMONO (0 << 0)
#define ATMEL_LCDC_DISTYPE_STNCOLOR (1 << 0)
#define ATMEL_LCDC_DISTYPE_TFT (2 << 0)
#define ATMEL_LCDC_SCANMOD (1 << 2)
#define ATMEL_LCDC_SCANMOD_SINGLE (0 << 2)
#define ATMEL_LCDC_SCANMOD_DUAL (1 << 2)
#define ATMEL_LCDC_IFWIDTH (3 << 3)
#define ATMEL_LCDC_IFWIDTH_4 (0 << 3)
#define ATMEL_LCDC_IFWIDTH_8 (1 << 3)
#define ATMEL_LCDC_IFWIDTH_16 (2 << 3)
#define ATMEL_LCDC_PIXELSIZE (7 << 5)
#define ATMEL_LCDC_PIXELSIZE_1 (0 << 5)
#define ATMEL_LCDC_PIXELSIZE_2 (1 << 5)
#define ATMEL_LCDC_PIXELSIZE_4 (2 << 5)
#define ATMEL_LCDC_PIXELSIZE_8 (3 << 5)
#define ATMEL_LCDC_PIXELSIZE_16 (4 << 5)
#define ATMEL_LCDC_PIXELSIZE_24 (5 << 5)
#define ATMEL_LCDC_PIXELSIZE_32 (6 << 5)
#define ATMEL_LCDC_INVVD (1 << 8)
#define ATMEL_LCDC_INVVD_NORMAL (0 << 8)
#define ATMEL_LCDC_INVVD_INVERTED (1 << 8)
#define ATMEL_LCDC_INVFRAME (1 << 9 )
#define ATMEL_LCDC_INVFRAME_NORMAL (0 << 9)
#define ATMEL_LCDC_INVFRAME_INVERTED (1 << 9)
#define ATMEL_LCDC_INVLINE (1 << 10)
#define ATMEL_LCDC_INVLINE_NORMAL (0 << 10)
#define ATMEL_LCDC_INVLINE_INVERTED (1 << 10)
#define ATMEL_LCDC_INVCLK (1 << 11)
#define ATMEL_LCDC_INVCLK_NORMAL (0 << 11)
#define ATMEL_LCDC_INVCLK_INVERTED (1 << 11)
#define ATMEL_LCDC_INVDVAL (1 << 12)
#define ATMEL_LCDC_INVDVAL_NORMAL (0 << 12)
#define ATMEL_LCDC_INVDVAL_INVERTED (1 << 12)
#define ATMEL_LCDC_CLKMOD (1 << 15)
#define ATMEL_LCDC_CLKMOD_ACTIVEDISPLAY (0 << 15)
#define ATMEL_LCDC_CLKMOD_ALWAYSACTIVE (1 << 15)
#define ATMEL_LCDC_MEMOR (1 << 31)
#define ATMEL_LCDC_MEMOR_BIG (0 << 31)
#define ATMEL_LCDC_MEMOR_LITTLE (1 << 31)
#define ATMEL_LCDC_TIM1 0x0808
#define ATMEL_LCDC_VFP (0xffU << 0)
#define ATMEL_LCDC_VBP_OFFSET 8
#define ATMEL_LCDC_VBP (0xffU << ATMEL_LCDC_VBP_OFFSET)
#define ATMEL_LCDC_VPW_OFFSET 16
#define ATMEL_LCDC_VPW (0x3fU << ATMEL_LCDC_VPW_OFFSET)
#define ATMEL_LCDC_VHDLY_OFFSET 24
#define ATMEL_LCDC_VHDLY (0xfU << ATMEL_LCDC_VHDLY_OFFSET)
#define ATMEL_LCDC_TIM2 0x080c
#define ATMEL_LCDC_HBP (0xffU << 0)
#define ATMEL_LCDC_HPW_OFFSET 8
#define ATMEL_LCDC_HPW (0x3fU << ATMEL_LCDC_HPW_OFFSET)
#define ATMEL_LCDC_HFP_OFFSET 21
#define ATMEL_LCDC_HFP (0x7ffU << ATMEL_LCDC_HFP_OFFSET)
#define ATMEL_LCDC_LCDFRMCFG 0x0810
#define ATMEL_LCDC_LINEVAL (0x7ff << 0)
#define ATMEL_LCDC_HOZVAL_OFFSET 21
#define ATMEL_LCDC_HOZVAL (0x7ff << ATMEL_LCDC_HOZVAL_OFFSET)
#define ATMEL_LCDC_FIFO 0x0814
#define ATMEL_LCDC_FIFOTH (0xffff)
#define ATMEL_LCDC_MVAL 0x0818
#define ATMEL_LCDC_DP1_2 0x081c
#define ATMEL_LCDC_DP4_7 0x0820
#define ATMEL_LCDC_DP3_5 0x0824
#define ATMEL_LCDC_DP2_3 0x0828
#define ATMEL_LCDC_DP5_7 0x082c
#define ATMEL_LCDC_DP3_4 0x0830
#define ATMEL_LCDC_DP4_5 0x0834
#define ATMEL_LCDC_DP6_7 0x0838
#define ATMEL_LCDC_DP1_2_VAL (0xff)
#define ATMEL_LCDC_DP4_7_VAL (0xfffffff)
#define ATMEL_LCDC_DP3_5_VAL (0xfffff)
#define ATMEL_LCDC_DP2_3_VAL (0xfff)
#define ATMEL_LCDC_DP5_7_VAL (0xfffffff)
#define ATMEL_LCDC_DP3_4_VAL (0xffff)
#define ATMEL_LCDC_DP4_5_VAL (0xfffff)
#define ATMEL_LCDC_DP6_7_VAL (0xfffffff)
#define ATMEL_LCDC_PWRCON 0x083c
#define ATMEL_LCDC_PWR (1 << 0)
#define ATMEL_LCDC_GUARDT_OFFSET 1
#define ATMEL_LCDC_GUARDT (0x7f << ATMEL_LCDC_GUARDT_OFFSET)
#define ATMEL_LCDC_BUSY (1 << 31)
#define ATMEL_LCDC_CONTRAST_CTR 0x0840
#define ATMEL_LCDC_PS (3 << 0)
#define ATMEL_LCDC_PS_DIV1 (0 << 0)
#define ATMEL_LCDC_PS_DIV2 (1 << 0)
#define ATMEL_LCDC_PS_DIV4 (2 << 0)
#define ATMEL_LCDC_PS_DIV8 (3 << 0)
#define ATMEL_LCDC_POL (1 << 2)
#define ATMEL_LCDC_POL_NEGATIVE (0 << 2)
#define ATMEL_LCDC_POL_POSITIVE (1 << 2)
#define ATMEL_LCDC_ENA (1 << 3)
#define ATMEL_LCDC_ENA_PWMDISABLE (0 << 3)
#define ATMEL_LCDC_ENA_PWMENABLE (1 << 3)
#define ATMEL_LCDC_CONTRAST_VAL 0x0844
#define ATMEL_LCDC_CVAL (0xff)
#define ATMEL_LCDC_IER 0x0848
#define ATMEL_LCDC_IDR 0x084c
#define ATMEL_LCDC_IMR 0x0850
#define ATMEL_LCDC_ISR 0x0854
#define ATMEL_LCDC_ICR 0x0858
#define ATMEL_LCDC_LNI (1 << 0)
#define ATMEL_LCDC_LSTLNI (1 << 1)
#define ATMEL_LCDC_EOFI (1 << 2)
#define ATMEL_LCDC_UFLWI (1 << 4)
#define ATMEL_LCDC_OWRI (1 << 5)
#define ATMEL_LCDC_MERI (1 << 6)
#define ATMEL_LCDC_LUT(n) (0x0c00 + ((n)*4))
#endif /* __ATMEL_LCDC_H__ */

11
include/common.h
View File

@@ -176,6 +176,17 @@ typedef void (interrupt_handler_t)(void *);
(__x > __y) ? __x : __y; })
/**
* container_of - cast a member of a structure out to the containing structure
* @ptr: the pointer to the member.
* @type: the type of the container struct this is embedded in.
* @member: the name of the member within the struct.
*
*/
#define container_of(ptr, type, member) ({ \
const typeof( ((type *)0)->member ) *__mptr = (ptr); \
(type *)( (char *)__mptr - offsetof(type,member) );})
/*
* Function Prototypes
*/

2
include/configs/Alaska8220.h
View File

@@ -31,6 +31,8 @@
#define CONFIG_MPC8220 1
#define CONFIG_ALASKA8220 1 /* ... on Alaska board */
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/* Input clock running at 30Mhz, read Hid1 for the CPU multiplier to
determine the CPU speed. */
#define CFG_MPC8220_CLKIN 30000000/* ... running at 30MHz */

2
include/configs/BC3450.h
View File

@@ -61,6 +61,8 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/*
* Serial console configuration
*/

2
include/configs/CPCI750.h
View File

@@ -61,6 +61,8 @@
#undef CONFIG_ECC /* enable ECC support */
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/* which initialization functions to call for this board */
#define CONFIG_MISC_INIT_R
#define CONFIG_BOARD_PRE_INIT

2
include/configs/IceCube.h
View File

@@ -37,6 +37,8 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/*
* Serial console configuration
*/

2
include/configs/MPC8313ERDB.h
View File

@@ -469,6 +469,8 @@
#define CFG_HID2 HID2_HBE
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/* DDR @ 0x00000000 */
#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10)
#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)

1
include/configs/MPC8315ERDB.h
View File

@@ -453,6 +453,7 @@
/*
* MMU Setup
*/
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/* DDR: cache cacheable */
#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)

1
include/configs/MPC8323ERDB.h
View File

@@ -468,6 +468,7 @@
/*
* MMU Setup
*/
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/* DDR: cache cacheable */
#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)

2
include/configs/MPC832XEMDS.h
View File

@@ -483,6 +483,8 @@
* MMU Setup
*/
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/* DDR: cache cacheable */
#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)

1
include/configs/MPC8349EMDS.h
View File

@@ -626,6 +626,7 @@
#define CFG_HID2 HID2_HBE
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/* DDR @ 0x00000000 */
#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)

1
include/configs/MPC8349ITX.h
View File

@@ -555,6 +555,7 @@ boards, we say we have two, but don't display a message if we find only one. */
#define CFG_HID0_FINAL CFG_HID0_INIT
#define CFG_HID2 HID2_HBE
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/* DDR */
#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)

2
include/configs/MPC8360EMDS.h
View File

@@ -515,6 +515,8 @@
* MMU Setup
*/
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/* DDR: cache cacheable */
#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)

2
include/configs/MPC8360ERDK.h
View File

@@ -419,6 +419,8 @@
* MMU Setup
*/
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/* DDR: cache cacheable */
#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)

1
include/configs/MPC837XEMDS.h
View File

@@ -502,6 +502,7 @@
/*
* MMU Setup
*/
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/* DDR: cache cacheable */
#define CFG_SDRAM_LOWER CFG_SDRAM_BASE

2
include/configs/MPC837XERDB.h
View File

@@ -524,6 +524,8 @@
* MMU Setup
*/
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/* DDR: cache cacheable */
#define CFG_SDRAM_LOWER CFG_SDRAM_BASE
#define CFG_SDRAM_UPPER (CFG_SDRAM_BASE + 0x10000000)

1
include/configs/MPC8610HPCD.h
View File

@@ -55,6 +55,7 @@
#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
#define CONFIG_HIGH_BATS 1 /* High BATs supported & enabled */
#define CONFIG_ALTIVEC 1
/*

1
include/configs/MPC8641HPCN.h
View File

@@ -67,6 +67,7 @@
#define BANK_INTERLEAVING 0x22000000
#define SUPER_BANK_INTERLEAVING 0x23000000
#define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */
#define CONFIG_ALTIVEC 1

2
include/configs/PM520.h
View File

@@ -40,6 +40,8 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/*
* Serial console configuration
*/

2
include/configs/TB5200.h
View File

@@ -42,6 +42,8 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/*
* Serial console configuration
*/

2
include/configs/TOP5200.h
View File

@@ -50,6 +50,8 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/*
* Serial console configuration
*/

2
include/configs/TQM5200.h
View File

@@ -47,6 +47,8 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/*
* Serial console configuration
*/

2
include/configs/TQM834x.h
View File

@@ -423,6 +423,8 @@ extern int tqm834x_num_flash_banks;
#define CFG_HID0_FINAL CFG_HID0_INIT
#define CFG_HID2 HID2_HBE
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/* DDR 0 - 512M */
#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)

2
include/configs/Total5200.h
View File

@@ -48,6 +48,8 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/*
* Serial console configuration
*/

2
include/configs/Yukon8220.h
View File

@@ -31,6 +31,8 @@
#define CONFIG_MPC8220 1
#define CONFIG_YUKON8220 1 /* ... on Yukon board */
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/* Input clock running at 30Mhz, read Hid1 for the CPU multiplier to
determine the CPU speed. */
#define CFG_MPC8220_CLKIN 30000000/* ... running at 30MHz */

2
include/configs/ads5121.h
View File

@@ -372,6 +372,8 @@
#define CFG_HID0_FINAL HID0_ENABLE_MACHINE_CHECK
#define CFG_HID2 HID2_HBE
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/*
* Internal Definitions
*

2
include/configs/aev.h
View File

@@ -41,6 +41,8 @@
#define CONFIG_AEVFIFO 1
#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */

37
include/configs/at91cap9adk.h
View File

@@ -28,6 +28,7 @@
#define __CONFIG_H
/* ARM asynchronous clock */
#define AT91_CPU_NAME "AT91CAP9"
#define AT91_MAIN_CLOCK 200000000 /* from 12 MHz crystal */
#define AT91_MASTER_CLOCK 100000000 /* peripheral = main / 2 */
#define CFG_HZ 1000000 /* 1us resolution */
@@ -55,11 +56,19 @@
#undef CONFIG_USART2
#define CONFIG_USART3 1 /* USART 3 is DBGU */
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
"root=/dev/mtdblock1 rw rootfstype=jffs2"
/* LCD */
#define CONFIG_LCD 1
#define LCD_BPP LCD_COLOR8
#define CONFIG_LCD_LOGO 1
#undef LCD_TEST_PATTERN
#define CONFIG_LCD_INFO 1
#define CONFIG_LCD_INFO_BELOW_LOGO 1
#define CFG_WHITE_ON_BLACK 1
#define CONFIG_ATMEL_LCD 1
#define CONFIG_ATMEL_LCD_BGR555 1
#define CFG_CONSOLE_IS_IN_ENV 1
/* #define CONFIG_ENV_OVERWRITE 1 */
#define CONFIG_BOOTDELAY 3
/*
* BOOTP options
@@ -94,9 +103,9 @@
#define CFG_SPI_WRITE_TOUT (5*CFG_HZ)
#define CFG_MAX_DATAFLASH_BANKS 1
#define CFG_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */
#define AT91_SPI_CLK 20000000
#define DATAFLASH_TCSS (0xFA << 16)
#define DATAFLASH_TCHS (0x8 << 24)
#define AT91_SPI_CLK 15000000
#define DATAFLASH_TCSS (0x1a << 16)
#define DATAFLASH_TCHS (0x1 << 24)
/* NOR flash */
#define CFG_FLASH_CFI 1
@@ -110,6 +119,7 @@
#define NAND_MAX_CHIPS 1
#define CFG_MAX_NAND_DEVICE 1
#define CFG_NAND_BASE 0x40000000
#define CFG_NAND_DBW_8 1
/* Ethernet */
#define CONFIG_MACB 1
@@ -143,7 +153,12 @@
#define CFG_ENV_OFFSET 0x4200
#define CFG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CFG_ENV_OFFSET)
#define CFG_ENV_SIZE 0x4200
#define CONFIG_BOOTCOMMAND "cp.b 0xC003DE00 0x72000000 0x200040; bootm"
#define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x72000000 0x210000; bootm"
#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
"root=/dev/mtdblock1 " \
"mtdparts=physmap-flash.0:-(nor);" \
"at91_nand:-(root) " \
"rw rootfstype=jffs2"
#else
@@ -154,6 +169,12 @@
#define CFG_ENV_ADDR (PHYS_FLASH_1 + CFG_ENV_OFFSET)
#define CFG_ENV_SIZE 0x4000
#define CONFIG_BOOTCOMMAND "cp.b 0x10040000 0x72000000 0x200000; bootm"
#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
"root=/dev/mtdblock4 " \
"mtdparts=physmap-flash.0:16k(bootstrap)ro,"\
"16k(env),224k(uboot)ro,-(linux);" \
"at91_nand:-(root) " \
"rw rootfstype=jffs2"
#endif

25
include/configs/at91sam9260ek.h
View File

@@ -56,10 +56,6 @@
#define CONFIG_USART3 1 /* USART 3 is DBGU */
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
"root=/dev/mtdblock0 rw rootfstype=jffs2"
/* #define CONFIG_ENV_OVERWRITE 1 */
/*
* BOOTP options
@@ -96,7 +92,7 @@
#define CFG_MAX_DATAFLASH_BANKS 2
#define CFG_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */
#define CFG_DATAFLASH_LOGIC_ADDR_CS1 0xD0000000 /* CS1 */
#define AT91_SPI_CLK 33000000
#define AT91_SPI_CLK 15000000
#define DATAFLASH_TCSS (0x1a << 16)
#define DATAFLASH_TCHS (0x1 << 24)
@@ -104,6 +100,7 @@
#define NAND_MAX_CHIPS 1
#define CFG_MAX_NAND_DEVICE 1
#define CFG_NAND_BASE 0x40000000
#define CFG_NAND_DBW_8 1
/* NOR flash - no real flash on this board */
#define CFG_NO_FLASH 1
@@ -142,7 +139,11 @@
#define CFG_ENV_OFFSET 0x4200
#define CFG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CFG_ENV_OFFSET)
#define CFG_ENV_SIZE 0x4200
#define CONFIG_BOOTCOMMAND "cp.b 0xC003DE00 0x22000000 0x200040; bootm"
#define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x22000000 0x210000; bootm"
#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
"root=/dev/mtdblock0 " \
"mtdparts=at91_nand:-(root) " \
"rw rootfstype=jffs2"
#elif CFG_USE_DATAFLASH_CS1
@@ -152,7 +153,11 @@
#define CFG_ENV_OFFSET 0x4200
#define CFG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS1 + CFG_ENV_OFFSET)
#define CFG_ENV_SIZE 0x4200
#define CONFIG_BOOTCOMMAND "cp.b 0xD003DE00 0x22000000 0x200040; bootm"
#define CONFIG_BOOTCOMMAND "cp.b 0xD0042000 0x22000000 0x210000; bootm"
#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
"root=/dev/mtdblock0 " \
"mtdparts=at91_nand:-(root) " \
"rw rootfstype=jffs2"
#else /* CFG_USE_NANDFLASH */
@@ -162,6 +167,12 @@
#define CFG_ENV_OFFSET_REDUND 0x80000
#define CFG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm"
#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
"root=/dev/mtdblock5 " \
"mtdparts=at91_nand:128k(bootstrap)ro," \
"256k(uboot)ro,128k(env1)ro," \
"128k(env2)ro,2M(linux),-(root) " \
"rw rootfstype=jffs2"
#endif

202
include/configs/at91sam9261ek.h Normal file
View File

@@ -0,0 +1,202 @@
/*
* (C) Copyright 2007-2008
* Stelian Pop <stelian.pop@leadtechdesign.com>
* Lead Tech Design <www.leadtechdesign.com>
*
* Configuation settings for the AT91SAM9261EK board.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/* ARM asynchronous clock */
#define AT91_CPU_NAME "AT91SAM9261"
#define AT91_MAIN_CLOCK 198656000 /* from 18.432 MHz crystal */
#define AT91_MASTER_CLOCK 99328000 /* peripheral = main / 2 */
#define CFG_HZ 1000000 /* 1us resolution */
#define AT91_SLOW_CLOCK 32768 /* slow clock */
#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */
#define CONFIG_AT91SAM9261 1 /* It's an Atmel AT91SAM9261 SoC*/
#define CONFIG_AT91SAM9261EK 1 /* on an AT91SAM9261EK Board */
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_INITRD_TAG 1
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SKIP_RELOCATE_UBOOT
/*
* Hardware drivers
*/
#define CONFIG_ATMEL_USART 1
#undef CONFIG_USART0
#undef CONFIG_USART1
#undef CONFIG_USART2
#define CONFIG_USART3 1 /* USART 3 is DBGU */
/* LCD */
#define CONFIG_LCD 1
#define LCD_BPP LCD_COLOR8
#define CONFIG_LCD_LOGO 1
#undef LCD_TEST_PATTERN
#define CONFIG_LCD_INFO 1
#define CONFIG_LCD_INFO_BELOW_LOGO 1
#define CFG_WHITE_ON_BLACK 1
#define CONFIG_ATMEL_LCD 1
#define CONFIG_ATMEL_LCD_BGR555 1
#define CFG_CONSOLE_IS_IN_ENV 1
#define CONFIG_BOOTDELAY 3
/*
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE 1
#define CONFIG_BOOTP_BOOTPATH 1
#define CONFIG_BOOTP_GATEWAY 1
#define CONFIG_BOOTP_HOSTNAME 1
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#undef CONFIG_CMD_BDI
#undef CONFIG_CMD_IMI
#undef CONFIG_CMD_AUTOSCRIPT
#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_LOADS
#undef CONFIG_CMD_IMLS
#define CONFIG_CMD_PING 1
#define CONFIG_CMD_DHCP 1
#define CONFIG_CMD_NAND 1
#define CONFIG_CMD_USB 1
/* SDRAM */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM 0x20000000
#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */
/* DataFlash */
#define CONFIG_HAS_DATAFLASH 1
#define CFG_SPI_WRITE_TOUT (5*CFG_HZ)
#define CFG_MAX_DATAFLASH_BANKS 2
#define CFG_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */
#define CFG_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 /* CS3 */
#define AT91_SPI_CLK 15000000
#define DATAFLASH_TCSS (0x1a << 16)
#define DATAFLASH_TCHS (0x1 << 24)
/* NAND flash */
#define NAND_MAX_CHIPS 1
#define CFG_MAX_NAND_DEVICE 1
#define CFG_NAND_BASE 0x40000000
#define CFG_NAND_DBW_8 1
/* NOR flash - no real flash on this board */
#define CFG_NO_FLASH 1
/* Ethernet */
#define CONFIG_DRIVER_DM9000 1
#define CONFIG_DM9000_BASE 0x30000000
#define DM9000_IO CONFIG_DM9000_BASE
#define DM9000_DATA (CONFIG_DM9000_BASE + 4)
#define CONFIG_DM9000_USE_16BIT 1
#define CONFIG_NET_RETRY_COUNT 20
#define CONFIG_RESET_PHY_R 1
/* USB */
#define CONFIG_USB_OHCI_NEW 1
#define LITTLEENDIAN 1
#define CONFIG_DOS_PARTITION 1
#define CFG_USB_OHCI_CPU_INIT 1
#define CFG_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9261_UHP_BASE */
#define CFG_USB_OHCI_SLOT_NAME "at91sam9261"
#define CFG_USB_OHCI_MAX_ROOT_PORTS 2
#define CONFIG_USB_STORAGE 1
#define CFG_LOAD_ADDR 0x22000000 /* load address */
#define CFG_MEMTEST_START PHYS_SDRAM
#define CFG_MEMTEST_END 0x23e00000
#define CFG_USE_DATAFLASH_CS0 1
#undef CFG_USE_NANDFLASH
#ifdef CFG_USE_DATAFLASH_CS0
/* bootstrap + u-boot + env + linux in dataflash on CS0 */
#define CFG_ENV_IS_IN_DATAFLASH 1
#define CFG_MONITOR_BASE (CFG_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
#define CFG_ENV_OFFSET 0x4200
#define CFG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CFG_ENV_OFFSET)
#define CFG_ENV_SIZE 0x4200
#define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x22000000 0x210000; bootm"
#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
"root=/dev/mtdblock0 " \
"mtdparts=at91_nand:-(root) " \
"rw rootfstype=jffs2"
#else /* CFG_USE_NANDFLASH */
/* bootstrap + u-boot + env + linux in nandflash */
#define CFG_ENV_IS_IN_NAND 1
#define CFG_ENV_OFFSET 0x60000
#define CFG_ENV_OFFSET_REDUND 0x80000
#define CFG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm"
#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
"root=/dev/mtdblock5 " \
"mtdparts=at91_nand:128k(bootstrap)ro," \
"256k(uboot)ro,128k(env1)ro," \
"128k(env2)ro,2M(linux),-(root) " \
"rw rootfstype=jffs2"
#endif
#define CONFIG_BAUDRATE 115200
#define CFG_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
#define CFG_PROMPT "U-Boot> "
#define CFG_CBSIZE 256
#define CFG_MAXARGS 16
#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
#define CFG_LONGHELP 1
#define CONFIG_CMDLINE_EDITING 1
#define ROUND(A, B) (((A) + (B)) & ~((B) - 1))
/*
* Size of malloc() pool
*/
#define CFG_MALLOC_LEN ROUND(3 * CFG_ENV_SIZE + 128*1024, 0x1000)
#define CFG_GBL_DATA_SIZE 128 /* 128 bytes for initial data */
#define CONFIG_STACKSIZE (32*1024) /* regular stack */
#ifdef CONFIG_USE_IRQ
#error CONFIG_USE_IRQ not supported
#endif
#endif

206
include/configs/at91sam9263ek.h Normal file
View File

@@ -0,0 +1,206 @@
/*
* (C) Copyright 2007-2008
* Stelian Pop <stelian.pop@leadtechdesign.com>
* Lead Tech Design <www.leadtechdesign.com>
*
* Configuation settings for the AT91SAM9263EK board.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/* ARM asynchronous clock */
#define AT91_CPU_NAME "AT91SAM9263"
#define AT91_MAIN_CLOCK 199919000 /* from 16.367 MHz crystal */
#define AT91_MASTER_CLOCK 99959500 /* peripheral = main / 2 */
#define CFG_HZ 1000000 /* 1us resolution */
#define AT91_SLOW_CLOCK 32768 /* slow clock */
#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */
#define CONFIG_AT91SAM9263 1 /* It's an Atmel AT91SAM9263 SoC*/
#define CONFIG_AT91SAM9263EK 1 /* on an AT91SAM9263EK Board */
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_INITRD_TAG 1
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SKIP_RELOCATE_UBOOT
/*
* Hardware drivers
*/
#define CONFIG_ATMEL_USART 1
#undef CONFIG_USART0
#undef CONFIG_USART1
#undef CONFIG_USART2
#define CONFIG_USART3 1 /* USART 3 is DBGU */
/* LCD */
#define CONFIG_LCD 1
#define LCD_BPP LCD_COLOR8
#define CONFIG_LCD_LOGO 1
#undef LCD_TEST_PATTERN
#define CONFIG_LCD_INFO 1
#define CONFIG_LCD_INFO_BELOW_LOGO 1
#define CFG_WHITE_ON_BLACK 1
#define CONFIG_ATMEL_LCD 1
#define CONFIG_ATMEL_LCD_BGR555 1
#define CFG_CONSOLE_IS_IN_ENV 1
#define CONFIG_BOOTDELAY 3
/*
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE 1
#define CONFIG_BOOTP_BOOTPATH 1
#define CONFIG_BOOTP_GATEWAY 1
#define CONFIG_BOOTP_HOSTNAME 1
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#undef CONFIG_CMD_BDI
#undef CONFIG_CMD_IMI
#undef CONFIG_CMD_AUTOSCRIPT
#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_LOADS
#undef CONFIG_CMD_IMLS
#define CONFIG_CMD_PING 1
#define CONFIG_CMD_DHCP 1
#define CONFIG_CMD_NAND 1
#define CONFIG_CMD_USB 1
/* SDRAM */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM 0x20000000
#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */
/* DataFlash */
#define CONFIG_HAS_DATAFLASH 1
#define CFG_SPI_WRITE_TOUT (5*CFG_HZ)
#define CFG_MAX_DATAFLASH_BANKS 1
#define CFG_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */
#define AT91_SPI_CLK 15000000
#define DATAFLASH_TCSS (0x1a << 16)
#define DATAFLASH_TCHS (0x1 << 24)
/* NOR flash, if populated */
#if 1
#define CFG_NO_FLASH 1
#else
#define CFG_FLASH_CFI 1
#define CFG_FLASH_CFI_DRIVER 1
#define PHYS_FLASH_1 0x10000000
#define CFG_FLASH_BASE PHYS_FLASH_1
#define CFG_MAX_FLASH_SECT 256
#define CFG_MAX_FLASH_BANKS 1
#endif
/* NAND flash */
#define NAND_MAX_CHIPS 1
#define CFG_MAX_NAND_DEVICE 1
#define CFG_NAND_BASE 0x40000000
#define CFG_NAND_DBW_8 1
/* Ethernet */
#define CONFIG_MACB 1
#define CONFIG_RMII 1
#define CONFIG_NET_MULTI 1
#define CONFIG_NET_RETRY_COUNT 20
#define CONFIG_RESET_PHY_R 1
/* USB */
#define CONFIG_USB_OHCI_NEW 1
#define LITTLEENDIAN 1
#define CONFIG_DOS_PARTITION 1
#define CFG_USB_OHCI_CPU_INIT 1
#define CFG_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */
#define CFG_USB_OHCI_SLOT_NAME "at91sam9263"
#define CFG_USB_OHCI_MAX_ROOT_PORTS 2
#define CONFIG_USB_STORAGE 1
#define CFG_LOAD_ADDR 0x22000000 /* load address */
#define CFG_MEMTEST_START PHYS_SDRAM
#define CFG_MEMTEST_END 0x23e00000
#define CFG_USE_DATAFLASH 1
#undef CFG_USE_NANDFLASH
#ifdef CFG_USE_DATAFLASH
/* bootstrap + u-boot + env + linux in dataflash on CS0 */
#define CFG_ENV_IS_IN_DATAFLASH 1
#define CFG_MONITOR_BASE (CFG_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
#define CFG_ENV_OFFSET 0x4200
#define CFG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CFG_ENV_OFFSET)
#define CFG_ENV_SIZE 0x4200
#define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x22000000 0x210000; bootm"
#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
"root=/dev/mtdblock0 " \
"mtdparts=at91_nand:-(root) "\
"rw rootfstype=jffs2"
#else /* CFG_USE_NANDFLASH */
/* bootstrap + u-boot + env + linux in nandflash */
#define CFG_ENV_IS_IN_NAND 1
#define CFG_ENV_OFFSET 0x60000
#define CFG_ENV_OFFSET_REDUND 0x80000
#define CFG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm"
#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
"root=/dev/mtdblock5 " \
"mtdparts=at91_nand:128k(bootstrap)ro,256k(uboot)ro,128k(env1)ro,128k(env2)ro,2M(linux),-(root) " \
"rw rootfstype=jffs2"
#endif
#define CONFIG_BAUDRATE 115200
#define CFG_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
#define CFG_PROMPT "U-Boot> "
#define CFG_CBSIZE 256
#define CFG_MAXARGS 16
#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
#define CFG_LONGHELP 1
#define CONFIG_CMDLINE_EDITING 1
#define ROUND(A, B) (((A) + (B)) & ~((B) - 1))
/*
* Size of malloc() pool
*/
#define CFG_MALLOC_LEN ROUND(3 * CFG_ENV_SIZE + 128*1024, 0x1000)
#define CFG_GBL_DATA_SIZE 128 /* 128 bytes for initial data */
#define CONFIG_STACKSIZE (32*1024) /* regular stack */
#ifdef CONFIG_USE_IRQ
#error CONFIG_USE_IRQ not supported
#endif
#endif

175
include/configs/at91sam9rlek.h Normal file
View File

@@ -0,0 +1,175 @@
/*
* (C) Copyright 2007-2008
* Stelian Pop <stelian.pop@leadtechdesign.com>
* Lead Tech Design <www.leadtechdesign.com>
*
* Configuation settings for the AT91SAM9RLEK board.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/* ARM asynchronous clock */
#define AT91_CPU_NAME "AT91SAM9RL"
#define AT91_MAIN_CLOCK 200000000 /* from 12.000 MHz crystal */
#define AT91_MASTER_CLOCK 100000000 /* peripheral = main / 2 */
#define CFG_HZ 1000000 /* 1us resolution */
#define AT91_SLOW_CLOCK 32768 /* slow clock */
#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */
#define CONFIG_AT91SAM9RL 1 /* It's an Atmel AT91SAM9RL SoC*/
#define CONFIG_AT91SAM9RLEK 1 /* on an AT91SAM9RLEK Board */
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_INITRD_TAG 1
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SKIP_RELOCATE_UBOOT
/*
* Hardware drivers
*/
#define CONFIG_ATMEL_USART 1
#undef CONFIG_USART0
#undef CONFIG_USART1
#undef CONFIG_USART2
#define CONFIG_USART3 1 /* USART 3 is DBGU */
/* LCD */
#define CONFIG_LCD 1
#define LCD_BPP LCD_COLOR8
#define CONFIG_LCD_LOGO 1
#undef LCD_TEST_PATTERN
#define CONFIG_LCD_INFO 1
#define CONFIG_LCD_INFO_BELOW_LOGO 1
#define CFG_WHITE_ON_BLACK 1
#define CONFIG_ATMEL_LCD 1
#define CONFIG_ATMEL_LCD_RGB565 1
#define CFG_CONSOLE_IS_IN_ENV 1
#define CONFIG_BOOTDELAY 3
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#undef CONFIG_CMD_BDI
#undef CONFIG_CMD_IMI
#undef CONFIG_CMD_AUTOSCRIPT
#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_LOADS
#undef CONFIG_CMD_IMLS
#undef CONFIG_CMD_NET
#undef CONFIG_CMD_USB
#define CONFIG_CMD_NAND 1
/* SDRAM */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM 0x20000000
#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */
/* DataFlash */
#define CONFIG_HAS_DATAFLASH 1
#define CFG_SPI_WRITE_TOUT (5*CFG_HZ)
#define CFG_MAX_DATAFLASH_BANKS 1
#define CFG_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */
#define AT91_SPI_CLK 15000000
#define DATAFLASH_TCSS (0x1a << 16)
#define DATAFLASH_TCHS (0x1 << 24)
/* NOR flash - not present */
#define CFG_NO_FLASH 1
/* NAND flash */
#define NAND_MAX_CHIPS 1
#define CFG_MAX_NAND_DEVICE 1
#define CFG_NAND_BASE 0x40000000
#define CFG_NAND_DBW_8 1
/* Ethernet - not present */
/* USB - not supported */
#define CFG_LOAD_ADDR 0x22000000 /* load address */
#define CFG_MEMTEST_START PHYS_SDRAM
#define CFG_MEMTEST_END 0x23e00000
#define CFG_USE_DATAFLASH 1
#undef CFG_USE_NANDFLASH
#ifdef CFG_USE_DATAFLASH
/* bootstrap + u-boot + env + linux in dataflash on CS0 */
#define CFG_ENV_IS_IN_DATAFLASH 1
#define CFG_MONITOR_BASE (CFG_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
#define CFG_ENV_OFFSET 0x4200
#define CFG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CFG_ENV_OFFSET)
#define CFG_ENV_SIZE 0x4200
#define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x22000000 0x210000; bootm"
#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
"root=/dev/mtdblock0 " \
"mtdparts=at91_nand:-(root) "\
"rw rootfstype=jffs2"
#else /* CFG_USE_NANDFLASH */
/* bootstrap + u-boot + env + linux in nandflash */
#define CFG_ENV_IS_IN_NAND 1
#define CFG_ENV_OFFSET 0x60000
#define CFG_ENV_OFFSET_REDUND 0x80000
#define CFG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm"
#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
"root=/dev/mtdblock5 " \
"mtdparts=at91_nand:128k(bootstrap)ro,256k(uboot)ro,128k(env1)ro,128k(env2)ro,2M(linux),-(root) " \
"rw rootfstype=jffs2"
#endif
#define CONFIG_BAUDRATE 115200
#define CFG_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
#define CFG_PROMPT "U-Boot> "
#define CFG_CBSIZE 256
#define CFG_MAXARGS 16
#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
#define CFG_LONGHELP 1
#define CONFIG_CMDLINE_EDITING 1
#define ROUND(A, B) (((A) + (B)) & ~((B) - 1))
/*
* Size of malloc() pool
*/
#define CFG_MALLOC_LEN ROUND(3 * CFG_ENV_SIZE + 128*1024, 0x1000)
#define CFG_GBL_DATA_SIZE 128 /* 128 bytes for initial data */
#define CONFIG_STACKSIZE (32*1024) /* regular stack */
#ifdef CONFIG_USE_IRQ
#error CONFIG_USE_IRQ not supported
#endif
#endif

26
include/configs/atngw100.h
View File

@@ -24,6 +24,8 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#include <asm/arch/memory-map.h>
#define CONFIG_AVR32 1
#define CONFIG_AT32AP 1
#define CONFIG_AT32AP7000 1
@@ -112,8 +114,11 @@
#define CONFIG_CMD_FAT
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_MMC
#undef CONFIG_CMD_AUTOSCRIPT
#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_SETGETDCR
#undef CONFIG_CMD_XIMG
#define CONFIG_ATMEL_USART 1
#define CONFIG_MACB 1
@@ -137,11 +142,9 @@
#define CFG_MONITOR_BASE CFG_FLASH_BASE
#define CFG_INTRAM_BASE 0x24000000
#define CFG_INTRAM_SIZE 0x8000
#define CFG_SDRAM_BASE 0x10000000
#define CFG_SDRAM_16BIT 1
#define CFG_INTRAM_BASE INTERNAL_SRAM_BASE
#define CFG_INTRAM_SIZE INTERNAL_SRAM_SIZE
#define CFG_SDRAM_BASE EBI_SDRAM_BASE
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_SIZE 65536
@@ -150,27 +153,20 @@
#define CFG_INIT_SP_ADDR (CFG_INTRAM_BASE + CFG_INTRAM_SIZE)
#define CFG_MALLOC_LEN (256*1024)
#define CFG_MALLOC_END \
({ \
DECLARE_GLOBAL_DATA_PTR; \
CFG_SDRAM_BASE + gd->sdram_size; \
})
#define CFG_MALLOC_START (CFG_MALLOC_END - CFG_MALLOC_LEN)
#define CFG_DMA_ALLOC_LEN (16384)
/* Allow 4MB for the kernel run-time image */
#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x00400000)
#define CFG_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000)
#define CFG_BOOTPARAMS_LEN (16 * 1024)
/* Other configuration settings that shouldn't have to change all that often */
#define CFG_PROMPT "Uboot> "
#define CFG_PROMPT "U-Boot> "
#define CFG_CBSIZE 256
#define CFG_MAXARGS 16
#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
#define CFG_LONGHELP 1
#define CFG_MEMTEST_START CFG_SDRAM_BASE
#define CFG_MEMTEST_START EBI_SDRAM_BASE
#define CFG_MEMTEST_END (CFG_MEMTEST_START + 0x1f00000)
#define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }

19
include/configs/atstk1002.h
View File

@@ -24,6 +24,8 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#include <asm/arch/memory-map.h>
#define CONFIG_AVR32 1
#define CONFIG_AT32AP 1
#define CONFIG_AT32AP7000 1
@@ -139,9 +141,9 @@
#define CONFIG_CMD_FAT
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_MMC
#define CONFIG_CMD_REGINFO
#undef CONFIG_CMD_AUTOSCRIPT
#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_SETGETDCR
#undef CONFIG_CMD_XIMG
@@ -170,10 +172,9 @@
#define CFG_MONITOR_BASE CFG_FLASH_BASE
#define CFG_INTRAM_BASE 0x24000000
#define CFG_INTRAM_SIZE 0x8000
#define CFG_SDRAM_BASE 0x10000000
#define CFG_INTRAM_BASE INTERNAL_SRAM_BASE
#define CFG_INTRAM_SIZE INTERNAL_SRAM_SIZE
#define CFG_SDRAM_BASE EBI_SDRAM_BASE
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_SIZE 65536
@@ -185,17 +186,17 @@
#define CFG_DMA_ALLOC_LEN (16384)
/* Allow 4MB for the kernel run-time image */
#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x00400000)
#define CFG_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000)
#define CFG_BOOTPARAMS_LEN (16 * 1024)
/* Other configuration settings that shouldn't have to change all that often */
#define CFG_PROMPT "Uboot> "
#define CFG_PROMPT "U-Boot> "
#define CFG_CBSIZE 256
#define CFG_MAXARGS 8
#define CFG_MAXARGS 16
#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
#define CFG_LONGHELP 1
#define CFG_MEMTEST_START CFG_SDRAM_BASE
#define CFG_MEMTEST_START EBI_SDRAM_BASE
#define CFG_MEMTEST_END (CFG_MEMTEST_START + 0x700000)
#define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }

15
include/configs/atstk1003.h
View File

@@ -24,6 +24,8 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#include <asm/arch/memory-map.h>
#define CONFIG_AVR32 1
#define CONFIG_AT32AP 1
#define CONFIG_AT32AP7001 1
@@ -153,10 +155,9 @@
#define CFG_MONITOR_BASE CFG_FLASH_BASE
#define CFG_INTRAM_BASE 0x24000000
#define CFG_INTRAM_SIZE 0x8000
#define CFG_SDRAM_BASE 0x10000000
#define CFG_INTRAM_BASE INTERNAL_SRAM_BASE
#define CFG_INTRAM_SIZE INTERNAL_SRAM_SIZE
#define CFG_SDRAM_BASE EBI_SDRAM_BASE
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_SIZE 65536
@@ -167,17 +168,17 @@
#define CFG_MALLOC_LEN (256*1024)
/* Allow 4MB for the kernel run-time image */
#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x00400000)
#define CFG_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000)
#define CFG_BOOTPARAMS_LEN (16 * 1024)
/* Other configuration settings that shouldn't have to change all that often */
#define CFG_PROMPT "Uboot> "
#define CFG_PROMPT "U-Boot> "
#define CFG_CBSIZE 256
#define CFG_MAXARGS 16
#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
#define CFG_LONGHELP 1
#define CFG_MEMTEST_START CFG_SDRAM_BASE
#define CFG_MEMTEST_START EBI_SDRAM_BASE
#define CFG_MEMTEST_END (CFG_MEMTEST_START + 0x700000)
#define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }

16
include/configs/atstk1004.h
View File

@@ -24,6 +24,8 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#include <asm/arch/memory-map.h>
#define CONFIG_AVR32 1
#define CONFIG_AT32AP 1
#define CONFIG_AT32AP7002 1
@@ -153,11 +155,9 @@
#define CFG_MONITOR_BASE CFG_FLASH_BASE
#define CFG_INTRAM_BASE 0x24000000
#define CFG_INTRAM_SIZE 0x8000
#define CFG_SDRAM_BASE 0x10000000
#define CFG_SDRAM_16BIT 1
#define CFG_INTRAM_BASE INTERNAL_SRAM_BASE
#define CFG_INTRAM_SIZE INTERNAL_SRAM_SIZE
#define CFG_SDRAM_BASE EBI_SDRAM_BASE
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_SIZE 65536
@@ -168,17 +168,17 @@
#define CFG_MALLOC_LEN (256*1024)
/* Allow 2MB for the kernel run-time image */
#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x00200000)
#define CFG_LOAD_ADDR (EBI_SDRAM_BASE + 0x00200000)
#define CFG_BOOTPARAMS_LEN (16 * 1024)
/* Other configuration settings that shouldn't have to change all that often */
#define CFG_PROMPT "Uboot> "
#define CFG_PROMPT "U-Boot> "
#define CFG_CBSIZE 256
#define CFG_MAXARGS 16
#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
#define CFG_LONGHELP 1
#define CFG_MEMTEST_START CFG_SDRAM_BASE
#define CFG_MEMTEST_START EBI_SDRAM_BASE
#define CFG_MEMTEST_END (CFG_MEMTEST_START + 0x700000)
#define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }

203
include/configs/atstk1006.h Normal file
View File

@@ -0,0 +1,203 @@
/*
* Copyright (C) 2005-2006 Atmel Corporation
*
* Configuration settings for the ATSTK1002 CPU daughterboard
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#include <asm/arch/memory-map.h>
#define CONFIG_AVR32 1
#define CONFIG_AT32AP 1
#define CONFIG_AT32AP7000 1
#define CONFIG_ATSTK1006 1
#define CONFIG_ATSTK1000 1
#define CONFIG_ATSTK1000_EXT_FLASH 1
/*
* Timer clock frequency. We're using the CPU-internal COUNT register
* for this, so this is equivalent to the CPU core clock frequency
*/
#define CFG_HZ 1000
/*
* Set up the PLL to run at 140 MHz, the CPU to run at the PLL
* frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the
* PLL frequency.
* (CFG_OSC0_HZ * CFG_PLL0_MUL) / CFG_PLL0_DIV = PLL MHz
*/
#define CONFIG_PLL 1
#define CFG_POWER_MANAGER 1
#define CFG_OSC0_HZ 20000000
#define CFG_PLL0_DIV 1
#define CFG_PLL0_MUL 7
#define CFG_PLL0_SUPPRESS_CYCLES 16
/*
* Set the CPU running at:
* PLL / (2^CFG_CLKDIV_CPU) = CPU MHz
*/
#define CFG_CLKDIV_CPU 0
/*
* Set the HSB running at:
* PLL / (2^CFG_CLKDIV_HSB) = HSB MHz
*/
#define CFG_CLKDIV_HSB 1
/*
* Set the PBA running at:
* PLL / (2^CFG_CLKDIV_PBA) = PBA MHz
*/
#define CFG_CLKDIV_PBA 2
/*
* Set the PBB running at:
* PLL / (2^CFG_CLKDIV_PBB) = PBB MHz
*/
#define CFG_CLKDIV_PBB 1
/*
* The PLLOPT register controls the PLL like this:
* icp = PLLOPT<2>
* ivco = PLLOPT<1:0>
*
* We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
*/
#define CFG_PLL0_OPT 0x04
#undef CONFIG_USART0
#define CONFIG_USART1 1
#undef CONFIG_USART2
#undef CONFIG_USART3
/* User serviceable stuff */
#define CONFIG_DOS_PARTITION 1
#define CONFIG_CMDLINE_TAG 1
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_INITRD_TAG 1
#define CONFIG_STACKSIZE (2048)
#define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTARGS \
"console=ttyS0 root=mtd3 fbmem=2400k"
#define CONFIG_BOOTCOMMAND \
"fsload; bootm $(fileaddr)"
/*
* Only interrupt autoboot if <space> is pressed. Otherwise, garbage
* data on the serial line may interrupt the boot sequence.
*/
#define CONFIG_BOOTDELAY 1
#define CONFIG_AUTOBOOT 1
#define CONFIG_AUTOBOOT_KEYED 1
#define CONFIG_AUTOBOOT_PROMPT \
"Press SPACE to abort autoboot in %d seconds\n"
#define CONFIG_AUTOBOOT_DELAY_STR "d"
#define CONFIG_AUTOBOOT_STOP_STR " "
/*
* After booting the board for the first time, new ethernet addresses
* should be generated and assigned to the environment variables
* "ethaddr" and "eth1addr". This is normally done during production.
*/
#define CONFIG_OVERWRITE_ETHADDR_ONCE 1
#define CONFIG_NET_MULTI 1
/*
* BOOTP options
*/
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_MMC
#undef CONFIG_CMD_AUTOSCRIPT
#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_SETGETDCR
#undef CONFIG_CMD_XIMG
#define CONFIG_ATMEL_USART 1
#define CONFIG_MACB 1
#define CONFIG_PIO2 1
#define CFG_NR_PIOS 5
#define CFG_HSDRAMC 1
#define CONFIG_MMC 1
#define CFG_DCACHE_LINESZ 32
#define CFG_ICACHE_LINESZ 32
#define CONFIG_NR_DRAM_BANKS 1
/* External flash on STK1000 */
#if 0
#define CFG_FLASH_CFI 1
#define CFG_FLASH_CFI_DRIVER 1
#endif
#define CFG_FLASH_BASE 0x00000000
#define CFG_FLASH_SIZE 0x800000
#define CFG_MAX_FLASH_BANKS 1
#define CFG_MAX_FLASH_SECT 135
#define CFG_MONITOR_BASE CFG_FLASH_BASE
#define CFG_INTRAM_BASE INTERNAL_SRAM_BASE
#define CFG_INTRAM_SIZE INTERNAL_SRAM_SIZE
#define CFG_SDRAM_BASE EBI_SDRAM_BASE
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_SIZE 65536
#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_FLASH_SIZE - CFG_ENV_SIZE)
#define CFG_INIT_SP_ADDR (CFG_INTRAM_BASE + CFG_INTRAM_SIZE)
#define CFG_MALLOC_LEN (256*1024)
#define CFG_DMA_ALLOC_LEN (16384)
/* Allow 4MB for the kernel run-time image */
#define CFG_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000)
#define CFG_BOOTPARAMS_LEN (16 * 1024)
/* Other configuration settings that shouldn't have to change all that often */
#define CFG_PROMPT "U-Boot> "
#define CFG_CBSIZE 256
#define CFG_MAXARGS 16
#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
#define CFG_LONGHELP 1
#define CFG_MEMTEST_START EBI_SDRAM_BASE
#define CFG_MEMTEST_END (CFG_MEMTEST_START + 0x3f00000)
#define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
#endif /* __CONFIG_H */

2
include/configs/canmb.h
View File

@@ -40,6 +40,8 @@
#define CONFIG_BOARD_EARLY_INIT_R
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/*
* Serial console configuration
*/

2
include/configs/cm5200.h
View File

@@ -31,6 +31,8 @@
#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
#define CONFIG_CM5200 1 /* ... on CM5200 platform */
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/*
* Supported commands
*/

2
include/configs/cpci5200.h
View File

@@ -50,6 +50,8 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/*
* Serial console configuration
*/

2
include/configs/hmi1001.h
View File

@@ -40,6 +40,8 @@
#define CONFIG_BOARD_EARLY_INIT_R
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/*
* Serial console configuration
*/

3
include/configs/imx31_litekit.h
View File

@@ -65,7 +65,8 @@
#define CONFIG_HARD_SPI 1
#define CONFIG_MXC_SPI 1
#define CONFIG_MXC_SPI_IFACE 1
#define CONFIG_DEFAULT_SPI_BUS 1
#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_2 | SPI_CS_HIGH)
#define CONFIG_RTC_MC13783 1

2
include/configs/inka4x0.h
View File

@@ -40,6 +40,8 @@
#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/*
* Serial console configuration
*/

2
include/configs/jupiter.h
View File

@@ -41,6 +41,8 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/*
* Serial console configuration
*/

2
include/configs/mcc200.h
View File

@@ -40,6 +40,8 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/*
* Serial console configuration
*

2
include/configs/mecp5200.h
View File

@@ -50,6 +50,8 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/*
* Serial console configuration
*/

1
include/configs/motionpro.h
View File

@@ -35,6 +35,7 @@
#define CONFIG_MPC5200 1 /* More exactly a MPC5200 */
#define CONFIG_MOTIONPRO 1 /* ... on Promess Motion-PRO board */
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/*
* BOOTP options

2
include/configs/mpc7448hpc2.h
View File

@@ -39,7 +39,7 @@
#define CONFIG_MPC7448HPC2
#define CONFIG_74xx
#define CONFIG_750FX /* this option to enable init of extended BATs */
#define CONFIG_HIGH_BATS /* High BATs supported */
#define CONFIG_ALTIVEC /* undef to disable */
#define CFG_BOARD_NAME "MPC7448 HPC II"

1
include/configs/munices.h
View File

@@ -35,6 +35,7 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/*
* Command line configuration.

3
include/configs/mx31ads.h
View File

@@ -62,7 +62,8 @@
#define CONFIG_HARD_SPI 1
#define CONFIG_MXC_SPI 1
#define CONFIG_MXC_SPI_IFACE 1 /* Default SPI interface number */
#define CONFIG_DEFAULT_SPI_BUS 1
#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_2 | SPI_CS_HIGH)
#define CONFIG_RTC_MC13783 1

2
include/configs/o2dnt.h
View File

@@ -37,6 +37,8 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/*
* Serial console configuration
*/

1
include/configs/p3mx.h
View File

@@ -42,6 +42,7 @@
#if defined (CONFIG_P3M750)
#define CONFIG_750FX /* 750GL/GX/FX */
#define CONFIG_HIGH_BATS /* High BATs supported */
#define CFG_BOARD_NAME "P3M750"
#define CFG_BUS_HZ 100000000
#define CFG_BUS_CLK CFG_BUS_HZ

1
include/configs/pf5200.h
View File

@@ -49,6 +49,7 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/*
* Serial console configuration
*/

298
include/configs/quad100hd.h Normal file
View File

@@ -0,0 +1,298 @@
/*
* (C) Copyright 2008
* Gary Jennejohn, DENX Software Engineering GmbH, garyj@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/************************************************************************
* quad100hd.h - configuration for Quad100hd board
***********************************************************************/
#ifndef __CONFIG_H
#define __CONFIG_H
/*-----------------------------------------------------------------------
* High Level Configuration Options
*----------------------------------------------------------------------*/
#define CONFIG_QUAD100HD 1 /* Board is Quad100hd */
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_405EP 1 /* Specifc 405EP support*/
#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
#define PLLMR0_DEFAULT PLLMR0_266_133_66 /* no PCI */
#define PLLMR1_DEFAULT PLLMR1_266_133_66 /* no PCI */
/* the environment is in the EEPROM by default */
#define CFG_ENV_IS_IN_EEPROM
#undef CFG_ENV_IS_IN_FLASH
#define CONFIG_NET_MULTI 1
#define CONFIG_HAS_ETH1 1
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0x01 /* PHY address */
#define CFG_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */
#define CONFIG_PHY_RESET 1
#define CONFIG_PHY_RESET_DELAY 300 /* PHY RESET recovery delay */
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#undef CONFIG_CMD_ASKENV
#undef CONFIG_CMD_CACHE
#define CONFIG_CMD_DHCP
#undef CONFIG_CMD_DIAG
#define CONFIG_CMD_EEPROM
#undef CONFIG_CMD_ELF
#define CONFIG_CMD_I2C
#undef CONFIG_CMD_IRQ
#define CONFIG_CMD_JFFS2
#undef CONFIG_CMD_LOG
#undef CONFIG_CMD_MII
#define CONFIG_CMD_NAND
#undef CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
#undef CONFIG_WATCHDOG /* watchdog disabled */
/*-----------------------------------------------------------------------
* SDRAM
*----------------------------------------------------------------------*/
/*
* SDRAM configuration (please see cpu/ppc/sdram.[ch])
*/
#define CONFIG_SDRAM_BANK0 1
#define CFG_SDRAM_SIZE 0x02000000 /* 32 MB */
/* FIX! SDRAM timings used in datasheet */
#define CFG_SDRAM_CL 3 /* CAS latency */
#define CFG_SDRAM_tRP 20 /* PRECHARGE command period */
#define CFG_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE command period */
#define CFG_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */
#define CFG_SDRAM_tRFC 66 /* Auto refresh period */
/*
* JFFS2
*/
#define CFG_JFFS2_FIRST_BANK 0
#ifdef CFG_KERNEL_IN_JFFS2
#define CFG_JFFS2_FIRST_SECTOR 0 /* JFFS starts at block 0 */
#else /* kernel not in JFFS */
#define CFG_JFFS2_FIRST_SECTOR 8 /* block 0-7 is kernel (1MB = 8 sectors) */
#endif
#define CFG_JFFS2_NUM_BANKS 1
/*-----------------------------------------------------------------------
* Serial Port
*----------------------------------------------------------------------*/
#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */
#define CFG_BASE_BAUD 691200
#define CONFIG_BAUDRATE 115200
#define CONFIG_SERIAL_MULTI
/* The following table includes the supported baudrates */
#define CFG_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
/*-----------------------------------------------------------------------
* Miscellaneous configurable options
*----------------------------------------------------------------------*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#define CFG_LOAD_ADDR 0x100000 /* default load address */
#define CFG_EXTBDINFO 1 /* To use extended board_info (bd_t) */
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
#define CONFIG_LOOPW 1 /* enable loopw command */
#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
/*-----------------------------------------------------------------------
* I2C
*----------------------------------------------------------------------*/
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_EEPROM_ADDR 0x50 /* base address */
#define CFG_I2C_EEPROM_ADDR_LEN 2 /* bytes of address */
#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* 8 byte write page size */
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
#define CFG_EEPROM_SIZE 0x2000
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CFG_SDRAM_BASE _must_ start at 0
*/
#define CFG_SDRAM_BASE 0x00000000
#define CFG_FLASH_BASE 0xFFC00000
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
#define CFG_MONITOR_BASE (TEXT_BASE)
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
* FLASH organization
*/
#define CFG_FLASH_CFI /* The flash is CFI compatible */
#define CFG_FLASH_CFI_DRIVER
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
#define CFG_FLASH_INCREMENT 0 /* there is only one bank */
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
#ifdef CFG_ENV_IS_IN_FLASH
#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
/* the environment is located before u-boot */
#define CFG_ENV_ADDR (TEXT_BASE - CFG_ENV_SECT_SIZE)
/* Address and size of Redundant Environment Sector */
#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR - CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SECT_SIZE)
#endif
#ifdef CFG_ENV_IS_IN_EEPROM
#define CFG_ENV_SIZE 0x400 /* Size of Environment vars */
#define CFG_ENV_OFFSET 0x00000000
#define CFG_ENABLE_CRC_16 1 /* Intrinsyc formatting used crc16 */
#endif
/* partly from PPCBoot */
/* NAND */
#define CONFIG_NAND
#ifdef CONFIG_NAND
#define CFG_NAND_BASE 0x60000000
#define CFG_NAND_CS 10 /* our CS is GPIO10 */
#define CFG_NAND_RDY 23 /* our RDY is GPIO23 */
#define CFG_NAND_CE 24 /* our CE is GPIO24 */
#define CFG_NAND_CLE 31 /* our CLE is GPIO31 */
#define CFG_NAND_ALE 30 /* our ALE is GPIO30 */
#define NAND_MAX_CHIPS 1
#define CFG_MAX_NAND_DEVICE 1
#endif
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in data cache)
*/
/* use on chip memory (OCM) for temperary stack until sdram is tested */
/* see ./cpu/ppc4xx/start.S */
#define CFG_TEMP_STACK_OCM 1
/* On Chip Memory location */
#define CFG_OCM_DATA_ADDR 0xF8000000
#define CFG_OCM_DATA_SIZE 0x1000
#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of OCM */
#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
* External Bus Controller (EBC) Setup
* Taken from PPCBoot board/icecube/icecube.h
*/
/* see ./cpu/ppc4xx/cpu_init.c ./cpu/ppc4xx/ndfc.c */
#define CFG_EBC_PB0AP 0x04002480
/* AMD NOR flash - this corresponds to FLASH_BASE so may be correct */
#define CFG_EBC_PB0CR 0xFFC5A000
#define CFG_EBC_PB1AP 0x04005480
#define CFG_EBC_PB1CR 0x60018000
#define CFG_EBC_PB2AP 0x00000000
#define CFG_EBC_PB2CR 0x00000000
#define CFG_EBC_PB3AP 0x00000000
#define CFG_EBC_PB3CR 0x00000000
#define CFG_EBC_PB4AP 0x00000000
#define CFG_EBC_PB4CR 0x00000000
/*-----------------------------------------------------------------------
* Definitions for GPIO setup (PPC405EP specific)
*
* Taken in part from PPCBoot board/icecube/icecube.h
*/
/* see ./cpu/ppc4xx/cpu_init.c ./cpu/ppc4xx/start.S */
#define CFG_GPIO0_OSRH 0x55555550
#define CFG_GPIO0_OSRL 0x00000110
#define CFG_GPIO0_ISR1H 0x00000000
#define CFG_GPIO0_ISR1L 0x15555445
#define CFG_GPIO0_TSRH 0x00000000
#define CFG_GPIO0_TSRL 0x00000000
#define CFG_GPIO0_TCR 0xFFFF8097
#define CFG_GPIO0_ODR 0x00000000
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
/* ENVIRONMENT VARS */
#define CONFIG_IPADDR 192.168.1.67
#define CONFIG_SERVERIP 192.168.1.50
#define CONFIG_GATEWAYIP 192.168.1.1
#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_LOADADDR 300000
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
/* pass open firmware flat tree */
#define CONFIG_OF_LIBFDT 1
#endif /* __CONFIG_H */

2
include/configs/sbc8349.h
View File

@@ -570,6 +570,8 @@
#define CFG_HID2 HID2_HBE
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/* DDR @ 0x00000000 */
#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)

2
include/configs/smmaco4.h
View File

@@ -42,6 +42,8 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/*
* Serial console configuration
*/

3
include/configs/socrates.h
View File

@@ -227,7 +227,8 @@
*/
#define CFG_PCI_PHYS 0x80000000 /* 1G PCI TLB */
/* PCI is clocked by the external source at 33 MHz */
#define CONFIG_PCI_CLK_FREQ 33000000
#define CFG_PCI1_MEM_BASE 0x80000000
#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */

2
include/configs/sorcery.h
View File

@@ -31,6 +31,8 @@
#define CONFIG_MPC8220 1
#define CONFIG_SORCERY 1 /* Sorcery board */
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/* Input clock running at 60Mhz, read Hid1 for the CPU multiplier to
determine the CPU speed. */
#define CFG_MPC8220_CLKIN 60000000 /* ... running at 60MHz */

2
include/configs/spieval.h
View File

@@ -44,6 +44,8 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/*
* Serial console configuration
*/

2
include/configs/uc101.h
View File

@@ -40,6 +40,8 @@
#define CONFIG_BOARD_EARLY_INIT_R
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/*
* Serial console configuration
*/

2
include/configs/v38b.h
View File

@@ -46,6 +46,8 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/*
* Serial console configuration
*/

30
include/lcd.h
View File

@@ -155,7 +155,35 @@ typedef struct vidinfo {
u_char vl_bpix; /* Bits per pixel, 0 = 1 */
} vidinfo_t;
#endif /* CONFIG_MPC823, CONFIG_PXA250 or CONFIG_MCC200 */
#elif defined(CONFIG_ATMEL_LCD)
typedef struct vidinfo {
u_long vl_col; /* Number of columns (i.e. 640) */
u_long vl_row; /* Number of rows (i.e. 480) */
u_long vl_clk; /* pixel clock in ps */
/* LCD configuration register */
u_long vl_sync; /* Horizontal / vertical sync */
u_long vl_bpix; /* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8, 4 = 16 */
u_long vl_tft; /* 0 = passive, 1 = TFT */
/* Horizontal control register. */
u_long vl_hsync_len; /* Length of horizontal sync */
u_long vl_left_margin; /* Time from sync to picture */
u_long vl_right_margin; /* Time from picture to sync */
/* Vertical control register. */
u_long vl_vsync_len; /* Length of vertical sync */
u_long vl_upper_margin; /* Time from sync to picture */
u_long vl_lower_margin; /* Time from picture to sync */
u_long mmio; /* Memory mapped registers */
} vidinfo_t;
extern vidinfo_t panel_info;
#endif /* CONFIG_MPC823, CONFIG_PXA250 or CONFIG_MCC200 or CONFIG_ATMEL_LCD */
/* Video functions */

4
include/linux/mtd/nand.h
View File

@@ -385,6 +385,10 @@ struct nand_manufacturers {
extern struct nand_flash_dev nand_flash_ids[];
extern struct nand_manufacturers nand_manuf_ids[];
#ifndef NAND_MAX_CHIPS
#define NAND_MAX_CHIPS 8
#endif
/**
* struct nand_bbt_descr - bad block table descriptor
* @options: options for this descriptor

1
include/logbuff.h
View File

@@ -58,6 +58,7 @@ int drv_logbuff_init (void);
void logbuff_init_ptrs (void);
void logbuff_log(char *msg);
void logbuff_reset (void);
unsigned long logbuffer_base (void);
#endif /* CONFIG_LOGBUFFER */

5
include/onenand_uboot.h
View File

@@ -14,6 +14,8 @@
#ifndef __UBOOT_ONENAND_H
#define __UBOOT_ONENAND_H
#include <linux/types.h>
struct kvec {
void *iov_base;
size_t iov_len;
@@ -22,6 +24,9 @@ struct kvec {
typedef int spinlock_t;
typedef int wait_queue_head_t;
struct mtd_info;
struct erase_info;
/* Functions */
extern void onenand_init(void);
extern int onenand_read(struct mtd_info *mtd, loff_t from, size_t len,

150
include/spi.h
View File

@@ -31,22 +31,87 @@
#define SPI_MODE_1 (0|SPI_CPHA)
#define SPI_MODE_2 (SPI_CPOL|0)
#define SPI_MODE_3 (SPI_CPOL|SPI_CPHA)
#define SPI_CS_HIGH 0x04 /* chipselect active high? */
#define SPI_CS_HIGH 0x04 /* CS active high */
#define SPI_LSB_FIRST 0x08 /* per-word bits-on-wire */
#define SPI_3WIRE 0x10 /* SI/SO signals shared */
#define SPI_LOOP 0x20 /* loopback mode */
/*
* The function call pointer type used to drive the chip select.
*/
typedef void (*spi_chipsel_type)(int cs);
/* SPI transfer flags */
#define SPI_XFER_BEGIN 0x01 /* Assert CS before transfer */
#define SPI_XFER_END 0x02 /* Deassert CS after transfer */
/*-----------------------------------------------------------------------
* Representation of a SPI slave, i.e. what we're communicating with.
*
* Drivers are expected to extend this with controller-specific data.
*
* bus: ID of the bus that the slave is attached to.
* cs: ID of the chip select connected to the slave.
*/
struct spi_slave {
unsigned int bus;
unsigned int cs;
};
/*-----------------------------------------------------------------------
* Initialization, must be called once on start up.
*
* TODO: I don't think we really need this.
*/
void spi_init(void);
/*-----------------------------------------------------------------------
* Set up communications parameters for a SPI slave.
*
* This must be called once for each slave. Note that this function
* usually doesn't touch any actual hardware, it only initializes the
* contents of spi_slave so that the hardware can be easily
* initialized later.
*
* bus: Bus ID of the slave chip.
* cs: Chip select ID of the slave chip on the specified bus.
* max_hz: Maximum SCK rate in Hz.
* mode: Clock polarity, clock phase and other parameters.
*
* Returns: A spi_slave reference that can be used in subsequent SPI
* calls, or NULL if one or more of the parameters are not supported.
*/
struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
unsigned int max_hz, unsigned int mode);
/*-----------------------------------------------------------------------
* Free any memory associated with a SPI slave.
*
* slave: The SPI slave
*/
void spi_free_slave(struct spi_slave *slave);
/*-----------------------------------------------------------------------
* Claim the bus and prepare it for communication with a given slave.
*
* This must be called before doing any transfers with a SPI slave. It
* will enable and initialize any SPI hardware as necessary, and make
* sure that the SCK line is in the correct idle state. It is not
* allowed to claim the same bus for several slaves without releasing
* the bus in between.
*
* slave: The SPI slave
*
* Returns: 0 if the bus was claimed successfully, or a negative value
* if it wasn't.
*/
int spi_claim_bus(struct spi_slave *slave);
/*-----------------------------------------------------------------------
* Release the SPI bus
*
* This must be called once for every call to spi_claim_bus() after
* all transfers have finished. It may disable any SPI hardware as
* appropriate.
*
* slave: The SPI slave
*/
void spi_release_bus(struct spi_slave *slave);
/*-----------------------------------------------------------------------
* SPI transfer
@@ -60,28 +125,67 @@ void spi_init(void);
* input data overwrites the output data (since both are buffered by
* temporary variables, this is OK).
*
* If the chipsel() function is not NULL, it is called with a parameter
* of '1' (chip select active) at the start of the transfer and again with
* a parameter of '0' at the end of the transfer.
*
* If the chipsel() function _is_ NULL, it the responsibility of the
* caller to make the appropriate chip select active before calling
* spi_xfer() and making it inactive after spi_xfer() returns.
*
* spi_xfer() interface:
* chipsel: Routine to call to set/clear the chip select:
* if chipsel is NULL, it is not used.
* if(cs), make the chip select active (typically '0').
* if(!cs), make the chip select inactive (typically '1').
* dout: Pointer to a string of bits to send out. The bits are
* held in a byte array and are sent MSB first.
* din: Pointer to a string of bits that will be filled in.
* bitlen: How many bits to write and read.
* slave: The SPI slave which will be sending/receiving the data.
* bitlen: How many bits to write and read.
* dout: Pointer to a string of bits to send out. The bits are
* held in a byte array and are sent MSB first.
* din: Pointer to a string of bits that will be filled in.
* flags: A bitwise combination of SPI_XFER_* flags.
*
* Returns: 0 on success, not 0 on failure
*/
int spi_xfer(spi_chipsel_type chipsel, int bitlen, uchar *dout, uchar *din);
int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
void *din, unsigned long flags);
int spi_select(unsigned int bus, unsigned int dev, unsigned long mode);
/*-----------------------------------------------------------------------
* Determine if a SPI chipselect is valid.
* This function is provided by the board if the low-level SPI driver
* needs it to determine if a given chipselect is actually valid.
*
* Returns: 1 if bus:cs identifies a valid chip on this board, 0
* otherwise.
*/
int spi_cs_is_valid(unsigned int bus, unsigned int cs);
/*-----------------------------------------------------------------------
* Activate a SPI chipselect.
* This function is provided by the board code when using a driver
* that can't control its chipselects automatically (e.g.
* common/soft_spi.c). When called, it should activate the chip select
* to the device identified by "slave".
*/
void spi_cs_activate(struct spi_slave *slave);
/*-----------------------------------------------------------------------
* Deactivate a SPI chipselect.
* This function is provided by the board code when using a driver
* that can't control its chipselects automatically (e.g.
* common/soft_spi.c). When called, it should deactivate the chip
* select to the device identified by "slave".
*/
void spi_cs_deactivate(struct spi_slave *slave);
/*-----------------------------------------------------------------------
* Write 8 bits, then read 8 bits.
* slave: The SPI slave we're communicating with
* byte: Byte to be written
*
* Returns: The value that was read, or a negative value on error.
*
* TODO: This function probably shouldn't be inlined.
*/
static inline int spi_w8r8(struct spi_slave *slave, unsigned char byte)
{
unsigned char dout[2];
unsigned char din[2];
int ret;
dout[0] = byte;
dout[1] = 0;
ret = spi_xfer(slave, 16, dout, din, SPI_XFER_BEGIN | SPI_XFER_END);
return ret < 0 ? ret : din[1];
}
#endif /* _SPI_H_ */

70
include/spi_flash.h Normal file
View File

@@ -0,0 +1,70 @@
/*
* Interface to SPI flash
*
* Copyright (C) 2008 Atmel Corporation
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _SPI_FLASH_H_
#define _SPI_FLASH_H_
#include <spi.h>
struct spi_flash_region {
unsigned int count;
unsigned int size;
};
struct spi_flash {
struct spi_slave *spi;
const char *name;
u32 size;
int (*read)(struct spi_flash *flash, u32 offset,
size_t len, void *buf);
int (*write)(struct spi_flash *flash, u32 offset,
size_t len, const void *buf);
int (*erase)(struct spi_flash *flash, u32 offset,
size_t len);
};
struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs,
unsigned int max_hz, unsigned int spi_mode);
void spi_flash_free(struct spi_flash *flash);
static inline int spi_flash_read(struct spi_flash *flash, u32 offset,
size_t len, void *buf)
{
return flash->read(flash, offset, len, buf);
}
static inline int spi_flash_write(struct spi_flash *flash, u32 offset,
size_t len, const void *buf)
{
return flash->write(flash, offset, len, buf);
}
static inline int spi_flash_erase(struct spi_flash *flash, u32 offset,
size_t len)
{
return flash->erase(flash, offset, len);
}
#endif /* _SPI_FLASH_H_ */