mpc83xx: Migrate SPCR to Kconfig

Migrate the SPCR setting to Kconfig.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
This commit is contained in:
Mario Six
2019-01-21 09:18:13 +01:00
parent 73df96a38e
commit e35012e802
37 changed files with 192 additions and 52 deletions

View File

@@ -33,8 +33,6 @@
#define CONFIG_FSL_SERDES
#define CONFIG_FSL_SERDES1 0xe3000
#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
/*
* DDR Setup
*/

View File

@@ -31,8 +31,6 @@
#define CONFIG_HWCONFIG
#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
/*
* DDR Setup
*/

View File

@@ -20,9 +20,6 @@
*/
#define CONFIG_SYS_SICRL 0x00000000
/* (0-1) Optimize transactions between CSB and the SEC and QUICC Engine block */
#define CONFIG_SYS_SPCR_OPT 1
/*
* DDR Setup
*/

View File

@@ -328,8 +328,6 @@
/*
* System performance
*/
#define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */
#define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */
#define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */
#define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */

View File

@@ -403,8 +403,6 @@ boards, we say we have two, but don't display a message if we find only one. */
/*
* System performance
*/
#define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */
#define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */
#define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */
#define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */
#define CONFIG_SYS_SCCR_USBMPHCM 3 /* USB MPH controller's clock */

View File

@@ -12,9 +12,6 @@
*/
#define CONFIG_E300 1 /* E300 family */
/* System Priority Control Register */
#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC1/2 emergency has highest priority */
/*
* IP blocks clock configuration
*/

View File

@@ -23,9 +23,6 @@
/* System performance - define the value i.e. CONFIG_SYS_XXX
*/
/* System Priority Control Regsiter */
#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC1&2 emergency priority (0-3) */
/* System Clock Configuration Register */
#define CONFIG_SYS_SCCR_TSEC1CM 1 /* eTSEC1 clock mode (0-3) */
#define CONFIG_SYS_SCCR_TSEC2CM 1 /* eTSEC2 clock mode (0-3) */

View File

@@ -21,8 +21,6 @@
#define CONFIG_FSL_SERDES
#define CONFIG_FSL_SERDES1 0xe3000
#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
/*
* DDR Setup
*/

View File

@@ -36,8 +36,6 @@
#define CONFIG_FSL_SERDES
#define CONFIG_FSL_SERDES1 0xe3000
#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
/*
* DDR Setup
*/

View File

@@ -21,8 +21,6 @@
#define CONFIG_FSL_SERDES
#define CONFIG_FSL_SERDES1 0xe3000
#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
/*
* DDR Setup
*/