mpc83xx: Migrate SPCR to Kconfig
Migrate the SPCR setting to Kconfig. Signed-off-by: Mario Six <mario.six@gdsys.cc>
This commit is contained in:
@@ -33,8 +33,6 @@
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#define CONFIG_FSL_SERDES
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#define CONFIG_FSL_SERDES1 0xe3000
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#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
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/*
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* DDR Setup
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*/
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@@ -31,8 +31,6 @@
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#define CONFIG_HWCONFIG
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#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
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/*
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* DDR Setup
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*/
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@@ -20,9 +20,6 @@
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*/
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#define CONFIG_SYS_SICRL 0x00000000
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/* (0-1) Optimize transactions between CSB and the SEC and QUICC Engine block */
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#define CONFIG_SYS_SPCR_OPT 1
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/*
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* DDR Setup
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*/
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@@ -328,8 +328,6 @@
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/*
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* System performance
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*/
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#define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */
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#define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */
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#define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */
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#define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */
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@@ -403,8 +403,6 @@ boards, we say we have two, but don't display a message if we find only one. */
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/*
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* System performance
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*/
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#define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */
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#define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */
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#define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */
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#define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */
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#define CONFIG_SYS_SCCR_USBMPHCM 3 /* USB MPH controller's clock */
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@@ -12,9 +12,6 @@
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*/
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#define CONFIG_E300 1 /* E300 family */
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/* System Priority Control Register */
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#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC1/2 emergency has highest priority */
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/*
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* IP blocks clock configuration
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*/
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@@ -23,9 +23,6 @@
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/* System performance - define the value i.e. CONFIG_SYS_XXX
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*/
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/* System Priority Control Regsiter */
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#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC1&2 emergency priority (0-3) */
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/* System Clock Configuration Register */
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#define CONFIG_SYS_SCCR_TSEC1CM 1 /* eTSEC1 clock mode (0-3) */
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#define CONFIG_SYS_SCCR_TSEC2CM 1 /* eTSEC2 clock mode (0-3) */
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@@ -21,8 +21,6 @@
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#define CONFIG_FSL_SERDES
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#define CONFIG_FSL_SERDES1 0xe3000
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#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
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/*
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* DDR Setup
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*/
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@@ -36,8 +36,6 @@
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#define CONFIG_FSL_SERDES
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#define CONFIG_FSL_SERDES1 0xe3000
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#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
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/*
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* DDR Setup
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*/
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@@ -21,8 +21,6 @@
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#define CONFIG_FSL_SERDES
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#define CONFIG_FSL_SERDES1 0xe3000
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#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
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/*
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* DDR Setup
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*/
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