From eb89025013a6d4b1d9cf307e5a2a087196ee9f02 Mon Sep 17 00:00:00 2001 From: Alper Nebi Yasak Date: Wed, 28 Oct 2020 00:15:10 +0300 Subject: [PATCH 1/6] rockchip: rk3399: Init clocks in U-Boot proper if SPL was not run It's possible to chainload U-Boot proper from the vendor firmware in rk3399 chromebooks, but the way the vendor firmware sets up clocks is somehow different than what U-Boot expects. This causes the display to stay devoid of content even though vidconsole claims to work (with patches in process of being upstreamed). This is meant to be a rk3399 version of commit d3cb46aa8c41 ("rockchip: Init clocks again when chain-loading") which can detect the discrepancy, but this patch instead checks whether SPL (and therefore the clock init) was run via the handoff functionality and runs the init if it was not. Signed-off-by: Alper Nebi Yasak Reviewed-by: Simon Glass Reviewed-by: Kever Yang --- drivers/clk/rockchip/clk_rk3399.c | 22 ++++++++++++++++------ 1 file changed, 16 insertions(+), 6 deletions(-) diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index 478d76d428..3fd863e7bd 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -23,6 +23,8 @@ #include #include +DECLARE_GLOBAL_DATA_PTR; + #if CONFIG_IS_ENABLED(OF_PLATDATA) struct rk3399_clk_plat { struct dtd_rockchip_rk3399_cru dtd; @@ -50,10 +52,9 @@ struct pll_div { .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\ .postdiv1 = _postdiv1, .postdiv2 = _postdiv2}; -#if defined(CONFIG_SPL_BUILD) static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1); static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2, 2); -#else +#if !defined(CONFIG_SPL_BUILD) static const struct pll_div ppll_init_cfg = PLL_DIVISORS(PPLL_HZ, 2, 2, 1); #endif @@ -1293,7 +1294,6 @@ static struct clk_ops rk3399_clk_ops = { .disable = rk3399_clk_disable, }; -#ifdef CONFIG_SPL_BUILD static void rkclk_init(struct rockchip_cru *cru) { u32 aclk_div; @@ -1371,20 +1371,30 @@ static void rkclk_init(struct rockchip_cru *cru) hclk_div << HCLK_PERILP1_DIV_CON_SHIFT | HCLK_PERILP1_PLL_SEL_GPLL << HCLK_PERILP1_PLL_SEL_SHIFT); } -#endif static int rk3399_clk_probe(struct udevice *dev) { -#ifdef CONFIG_SPL_BUILD struct rk3399_clk_priv *priv = dev_get_priv(dev); + bool init_clocks = false; #if CONFIG_IS_ENABLED(OF_PLATDATA) struct rk3399_clk_plat *plat = dev_get_platdata(dev); priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]); #endif - rkclk_init(priv->cru); + +#if defined(CONFIG_SPL_BUILD) + init_clocks = true; +#elif CONFIG_IS_ENABLED(HANDOFF) + if (!(gd->flags & GD_FLG_RELOC)) { + if (!(gd->spl_handoff)) + init_clocks = true; + } #endif + + if (init_clocks) + rkclk_init(priv->cru); + return 0; } From 13634bb6585ec0e789da7504146873fb492456e5 Mon Sep 17 00:00:00 2001 From: Alper Nebi Yasak Date: Wed, 28 Oct 2020 00:15:11 +0300 Subject: [PATCH 2/6] rockchip: gru: Allow setting up clocks in U-Boot proper Commit fe974716326c ("rockchip: rk3288: Allow setting up clocks in U-Boot proper") fixes some clock issues when chainloading U-Boot on rk3288 chromebooks. Part of that change is still available in veyron's board_early_init_r() function. Since chain-loading U-Boot proper from vendor firmware is possible on gru boards as well, do the same thing for them too. On rk3399, this needs to detect whether SPL was run via handoff, so enable that and bloblist kconfigs it needs for chromebook_bob. Signed-off-by: Alper Nebi Yasak Reviewed-by: Simon Glass Reviewed-by: Kever Yang --- board/google/gru/gru.c | 23 +++++++++++++++++++++++ configs/chromebook_bob_defconfig | 5 +++++ 2 files changed, 28 insertions(+) diff --git a/board/google/gru/gru.c b/board/google/gru/gru.c index 7dfbc3ac86..441a1a376a 100644 --- a/board/google/gru/gru.c +++ b/board/google/gru/gru.c @@ -4,6 +4,7 @@ */ #include +#include #include #ifdef CONFIG_SPL_BUILD @@ -31,3 +32,25 @@ int board_early_init_f(void) return 0; } #endif + +#ifndef CONFIG_SPL_BUILD +int board_early_init_r(void) +{ + struct udevice *clk; + int ret; + + /* + * This init is done in SPL, but when chain-loading U-Boot SPL will + * have been skipped. Allow the clock driver to check if it needs + * setting up. + */ + ret = uclass_get_device_by_driver(UCLASS_CLK, + DM_GET_DRIVER(clk_rk3399), &clk); + if (ret) { + debug("%s: CLK init failed: %d\n", __func__, ret); + return ret; + } + + return 0; +} +#endif diff --git a/configs/chromebook_bob_defconfig b/configs/chromebook_bob_defconfig index 4608892fb5..73635f0d13 100644 --- a/configs/chromebook_bob_defconfig +++ b/configs/chromebook_bob_defconfig @@ -19,6 +19,11 @@ CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-gru-bob.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_BOARD_EARLY_INIT_R=y +CONFIG_BLOBLIST=y +CONFIG_BLOBLIST_SIZE=0x1000 +CONFIG_BLOBLIST_ADDR=0x100000 +CONFIG_HANDOFF=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 From a355ece8e678602de89febe30ede17a337c25836 Mon Sep 17 00:00:00 2001 From: Alper Nebi Yasak Date: Thu, 22 Oct 2020 22:43:13 +0300 Subject: [PATCH 3/6] video: rockchip: Restrict EDP, VOP, MIPI files to GPL-2.0 These files have a lot of code in common with their counterparts in coreboot, especially in their earlier revisions: U-Boot | coreboot --------------------------------------|-------------------------------------------- drivers/video/rockchip/: | src/soc/rockchip/: - rk_edp.c (GPL-2.0+) | - common/edp.c (GPL-2.0-only) " | - rk3288/display.c (GPL-2.0-only) " | - rk3399/display.c (GPL-2.0-only) - rk_hdmi.h (GPL-2.0+) | (none) - rk_hdmi.c (GPL-2.0+) | - rk3288/hdmi.c (GPL-2.0-or-later) - rk3288_hdmi.c (GPL-2.0+) | - rk3288/hdmi.c (GPL-2.0-or-later) - rk3399_hdmi.c (GPL-2.0+) | (none) - rk_mipi.h (GPL-2.0+) | (none) - rk_mipi.c (GPL-2.0+) | - rk3399/mipi.c (GPL-2.0-only) - rk3288_mipi.c (GPL-2.0+) | - rk3399/mipi.c (GPL-2.0-only) - rk3399_mipi.c (GPL-2.0+) | - rk3399/mipi.c (GPL-2.0-only) - rk_lvds.c (GPL-2.0+) | (none) - rk_vop.h (GPL-2.0+) | (none) - rk_vop.c (GPL-2.0+) | - common/vop.c (GPL-2.0-only) - rk3288_vop.c (GPL-2.0+) | - common/vop.c (GPL-2.0-only) - rk3399_vop.c (GPL-2.0+) | (none) | arch/arm/include/asm/arch-rockchip/: | src/soc/rockchip/*/include/soc/*: - edp_rk3288.h (GPL-2.0+) | - common/.../edp.h (GPL-2.0-only) " | - rk3288/.../display.h (GPL-2.0-only) " | - rk3399/.../display.h (GPL-2.0-only) - vop_rk3288.h (GPL-2.0+) | - common/.../vop.h (GPL-2.0-only) Restrict the licenses to match coreboot's so that changes from coreboot can be imported to U-Boot as necessary. HDMI files are already 2.0+ there and rk_lvds.c has no counterpart, so keep them as is. Cc: Simon Glass Cc: Philipp Tomsich Cc: Eric Gao Cc: Jacob Chen Signed-off-by: Alper Nebi Yasak Reviewed-by: Simon Glass Reviewed-by: Kever Yang --- arch/arm/include/asm/arch-rockchip/edp_rk3288.h | 2 +- arch/arm/include/asm/arch-rockchip/vop_rk3288.h | 2 +- drivers/video/rockchip/rk3288_mipi.c | 2 +- drivers/video/rockchip/rk3288_vop.c | 2 +- drivers/video/rockchip/rk3399_mipi.c | 2 +- drivers/video/rockchip/rk3399_vop.c | 2 +- drivers/video/rockchip/rk_edp.c | 2 +- drivers/video/rockchip/rk_mipi.c | 2 +- drivers/video/rockchip/rk_mipi.h | 2 +- drivers/video/rockchip/rk_vop.c | 2 +- drivers/video/rockchip/rk_vop.h | 2 +- 11 files changed, 11 insertions(+), 11 deletions(-) diff --git a/arch/arm/include/asm/arch-rockchip/edp_rk3288.h b/arch/arm/include/asm/arch-rockchip/edp_rk3288.h index 105a335dab..94e5bb674f 100644 --- a/arch/arm/include/asm/arch-rockchip/edp_rk3288.h +++ b/arch/arm/include/asm/arch-rockchip/edp_rk3288.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ +/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (c) 2015 Google, Inc * Copyright 2014 Rockchip Inc. diff --git a/arch/arm/include/asm/arch-rockchip/vop_rk3288.h b/arch/arm/include/asm/arch-rockchip/vop_rk3288.h index 872a158b71..52446e97c6 100644 --- a/arch/arm/include/asm/arch-rockchip/vop_rk3288.h +++ b/arch/arm/include/asm/arch-rockchip/vop_rk3288.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ +/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (c) 2015 Google, Inc * Copyright 2014 Rockchip Inc. diff --git a/drivers/video/rockchip/rk3288_mipi.c b/drivers/video/rockchip/rk3288_mipi.c index b232ff0b76..8ac0125b50 100644 --- a/drivers/video/rockchip/rk3288_mipi.c +++ b/drivers/video/rockchip/rk3288_mipi.c @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0+ +// SPDX-License-Identifier: GPL-2.0 /* * Copyright (c) 2017, Fuzhou Rockchip Electronics Co., Ltd * Author: Eric Gao diff --git a/drivers/video/rockchip/rk3288_vop.c b/drivers/video/rockchip/rk3288_vop.c index 68d1507cda..9ec33e6e51 100644 --- a/drivers/video/rockchip/rk3288_vop.c +++ b/drivers/video/rockchip/rk3288_vop.c @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0+ +// SPDX-License-Identifier: GPL-2.0 /* * Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH * Copyright (c) 2015 Google, Inc diff --git a/drivers/video/rockchip/rk3399_mipi.c b/drivers/video/rockchip/rk3399_mipi.c index 113708d97e..e5534c36e6 100644 --- a/drivers/video/rockchip/rk3399_mipi.c +++ b/drivers/video/rockchip/rk3399_mipi.c @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0+ +// SPDX-License-Identifier: GPL-2.0 /* * Copyright (c) 2017, Fuzhou Rockchip Electronics Co., Ltd * Author: Eric Gao diff --git a/drivers/video/rockchip/rk3399_vop.c b/drivers/video/rockchip/rk3399_vop.c index d5a7aa8ac1..55d1be0411 100644 --- a/drivers/video/rockchip/rk3399_vop.c +++ b/drivers/video/rockchip/rk3399_vop.c @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0+ +// SPDX-License-Identifier: GPL-2.0 /* * Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH * Copyright (c) 2015 Google, Inc diff --git a/drivers/video/rockchip/rk_edp.c b/drivers/video/rockchip/rk_edp.c index a032eb6889..c55f7a4f72 100644 --- a/drivers/video/rockchip/rk_edp.c +++ b/drivers/video/rockchip/rk_edp.c @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0+ +// SPDX-License-Identifier: GPL-2.0 /* * Copyright (c) 2015 Google, Inc * Copyright 2014 Rockchip Inc. diff --git a/drivers/video/rockchip/rk_mipi.c b/drivers/video/rockchip/rk_mipi.c index f811913ce5..d125a5ba73 100644 --- a/drivers/video/rockchip/rk_mipi.c +++ b/drivers/video/rockchip/rk_mipi.c @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0+ +// SPDX-License-Identifier: GPL-2.0 /* * Copyright (c) 2017, Fuzhou Rockchip Electronics Co., Ltd * Author: Eric Gao diff --git a/drivers/video/rockchip/rk_mipi.h b/drivers/video/rockchip/rk_mipi.h index 61920f23ad..3d1e440b0e 100644 --- a/drivers/video/rockchip/rk_mipi.h +++ b/drivers/video/rockchip/rk_mipi.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ +/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (c) 2017, Fuzhou Rockchip Electronics Co., Ltd * Author: Eric Gao diff --git a/drivers/video/rockchip/rk_vop.c b/drivers/video/rockchip/rk_vop.c index 9032eb430e..6475b3e2af 100644 --- a/drivers/video/rockchip/rk_vop.c +++ b/drivers/video/rockchip/rk_vop.c @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0+ +// SPDX-License-Identifier: GPL-2.0 /* * Copyright (c) 2015 Google, Inc * Copyright 2014 Rockchip Inc. diff --git a/drivers/video/rockchip/rk_vop.h b/drivers/video/rockchip/rk_vop.h index 8fa2f38939..53a79c04b5 100644 --- a/drivers/video/rockchip/rk_vop.h +++ b/drivers/video/rockchip/rk_vop.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ +/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH */ From c180e2939d3ccb43f89565d6660a0d6f912712b6 Mon Sep 17 00:00:00 2001 From: Hugh Cole-Baker Date: Sun, 8 Nov 2020 14:00:23 +0000 Subject: [PATCH 4/6] rockchip: rockpro64: fix boot from SPI flash on spi1 Commit c4cea2bbf995 ("rockchip: Enable building a SPI ROM image on bob") added an alias spi1 referring to spi@ff1d0000, however there was already an alias spi0 referring to the same node in rockpro64's u-boot.dtsi, and having both aliases present broke booting from SPI flash for this board. Remove the spi0 alias, set the default bus for SPI flash to 1, and enable support for numbered aliases in SPL so that it uses the same bus numbering as U-Boot proper. This fixes booting from U-Boot in SPI flash on the rockpro64 board. Signed-off-by: Hugh Cole-Baker Suggested-by: Simon Glass Fixes: c4cea2bbf995 ("rockchip: Enable building a SPI ROM image on bob") Reviewed-by: Kever Yang --- arch/arm/dts/rk3399-rockpro64-u-boot.dtsi | 4 ---- configs/rockpro64-rk3399_defconfig | 2 ++ 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi b/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi index cb8991aa25..6317b47e41 100644 --- a/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi +++ b/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi @@ -6,10 +6,6 @@ #include "rk3399-u-boot.dtsi" #include "rk3399-sdram-lpddr4-100.dtsi" / { - aliases { - spi0 = &spi1; - }; - chosen { u-boot,spl-boot-order = "same-as-spl", &spi_flash, &sdmmc, &sdhci; }; diff --git a/configs/rockpro64-rk3399_defconfig b/configs/rockpro64-rk3399_defconfig index bfba870407..575b7a20d5 100644 --- a/configs/rockpro64-rk3399_defconfig +++ b/configs/rockpro64-rk3399_defconfig @@ -32,6 +32,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_DM_KEYBOARD=y @@ -41,6 +42,7 @@ CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_SF_DEFAULT_BUS=1 CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y From 7a9c574cf106583b360a6b66f42706eecba96518 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Tue, 10 Nov 2020 11:43:32 +0800 Subject: [PATCH 5/6] rockchip: Enable BINMAN for boards enable SPL_OPTEE Rockchip has many 32bit SoCs and some of them are support SPL_OPTEE now, only boards with SPL_OPTEE support can fit BINMAN well, other boards will fail at initr_binman() in U-Boot proper after below patch, eg. rv1108 board. 83187546ae binman: Support multiple images in the library Fixes: 79030a4861 ("rockchip: Add Single boot image (with binman, pad_cat)") Signed-off-by: Kever Yang --- arch/arm/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index b2f7fcbd6e..5903c09370 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1721,7 +1721,7 @@ config ARCH_STM32MP config ARCH_ROCKCHIP bool "Support Rockchip SoCs" select BLK - select BINMAN if !ARM64 + select BINMAN if SPL_OPTEE select DM select DM_GPIO select DM_I2C From b197c934b11f611dcc1a083d90e68019d1e010cf Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Tue, 10 Nov 2020 10:09:06 +0000 Subject: [PATCH 6/6] rockchip: Pinebook Pro: Fix USB Improve USB config so keyboard and USB-A ports work. Signed-off-by: Peter Robinson --- configs/pinebook-pro-rk3399_defconfig | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/configs/pinebook-pro-rk3399_defconfig b/configs/pinebook-pro-rk3399_defconfig index 1ed54ad0ed..8fbd7280ac 100644 --- a/configs/pinebook-pro-rk3399_defconfig +++ b/configs/pinebook-pro-rk3399_defconfig @@ -55,6 +55,8 @@ CONFIG_SPI_FLASH_WINBOND=y CONFIG_DM_ETH=y CONFIG_NVME=y CONFIG_PCI=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_DM_PMIC_FAN53555=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y @@ -76,8 +78,9 @@ CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y CONFIG_USB_DWC3=y -CONFIG_ROCKCHIP_USB2_PHY=y +CONFIG_USB_DWC3_GENERIC=y CONFIG_USB_KEYBOARD=y +CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_RTL8152=y