From 4bc97a3b816914d8b37e3d1ecac464e6193fd230 Mon Sep 17 00:00:00 2001 From: Mario Six Date: Mon, 21 Jan 2019 09:17:24 +0100 Subject: [PATCH 01/86] mpc83xx: Introduce ARCH_MPC830* Replace CONFIG_MPC830* with proper CONFIG_ARCH_MPC830* Kconfig options. Signed-off-by: Mario Six --- arch/powerpc/cpu/mpc83xx/Kconfig | 17 +++++++++ arch/powerpc/cpu/mpc83xx/spd_sdram.c | 2 +- arch/powerpc/cpu/mpc83xx/speed.c | 38 ++++++++++---------- arch/powerpc/include/asm/arch-mpc83xx/gpio.h | 2 +- arch/powerpc/include/asm/fsl_lbc.h | 2 +- arch/powerpc/include/asm/global_data.h | 6 ++-- arch/powerpc/include/asm/immap_83xx.h | 10 +++--- arch/powerpc/include/asm/mpc8xxx_spi.h | 2 +- board/keymile/km83xx/km83xx.c | 2 +- drivers/qe/qe.c | 2 +- drivers/ram/mpc83xx_sdram.c | 4 +-- include/configs/MPC8308RDB.h | 2 -- include/configs/hrcon.h | 2 -- include/configs/km/km8309-common.h | 2 -- include/configs/km/km83xx-common.h | 2 +- include/configs/mpc8308_p1m.h | 2 -- include/configs/strider.h | 2 -- include/linux/immap_qe.h | 2 +- include/mpc83xx.h | 24 ++++++------- scripts/config_whitelist.txt | 3 -- 20 files changed, 66 insertions(+), 62 deletions(-) diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index 571cf8fc2e..142b924786 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -10,6 +10,7 @@ choice config TARGET_MPC8308_P1M bool "Support mpc8308_p1m" + select ARCH_MPC8308 config TARGET_SBC8349 bool "Support sbc8349" @@ -22,6 +23,7 @@ config TARGET_VME8349 config TARGET_MPC8308RDB bool "Support MPC8308RDB" + select ARCH_MPC8308 select SYS_FSL_ERRATUM_ESDHC111 config TARGET_MPC8313ERDB @@ -74,6 +76,8 @@ config TARGET_KM8360 config TARGET_SUVD3 bool "Support suvd3" + select ARCH_MPC8309 if SYS_EXTRA_OPTIONS="KMTEGR1" + select ARCH_MPC8309 if SYS_EXTRA_OPTIONS="KMVECT1" imply CMD_CRAMFS imply FS_CRAMFS @@ -87,15 +91,28 @@ config TARGET_TQM834X config TARGET_HRCON bool "Support hrcon" + select ARCH_MPC8308 select SYS_FSL_ERRATUM_ESDHC111 config TARGET_STRIDER bool "Support strider" + select ARCH_MPC8308 select SYS_FSL_ERRATUM_ESDHC111 imply CMD_PCA953X endchoice +config ARCH_MPC830X + bool + +config ARCH_MPC8308 + bool + select ARCH_MPC830X + +config ARCH_MPC8309 + bool + select ARCH_MPC830X + source "board/esd/vme8349/Kconfig" source "board/freescale/mpc8308rdb/Kconfig" source "board/freescale/mpc8313erdb/Kconfig" diff --git a/arch/powerpc/cpu/mpc83xx/spd_sdram.c b/arch/powerpc/cpu/mpc83xx/spd_sdram.c index 328a018eb6..97ef77121b 100644 --- a/arch/powerpc/cpu/mpc83xx/spd_sdram.c +++ b/arch/powerpc/cpu/mpc83xx/spd_sdram.c @@ -31,7 +31,7 @@ void board_add_ram_info(int use_default) printf(" (DDR%d", ((ddr->sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) >> SDRAM_CFG_SDRAM_TYPE_SHIFT) - 1); -#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) +#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) if ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) == SDRAM_CFG_DBW_16) puts(", 16-bit"); else if ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) == SDRAM_CFG_DBW_32) diff --git a/arch/powerpc/cpu/mpc83xx/speed.c b/arch/powerpc/cpu/mpc83xx/speed.c index 39bc1c5340..d537af5130 100644 --- a/arch/powerpc/cpu/mpc83xx/speed.c +++ b/arch/powerpc/cpu/mpc83xx/speed.c @@ -85,12 +85,12 @@ int get_clocks(void) u32 lcrr; u32 csb_clk; -#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \ +#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) || \ defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) u32 tsec1_clk; u32 tsec2_clk; u32 usbdr_clk; -#elif defined(CONFIG_MPC8309) +#elif defined(CONFIG_ARCH_MPC8309) u32 usbdr_clk; #endif #ifdef CONFIG_MPC834x @@ -107,7 +107,7 @@ int get_clocks(void) #if defined(CONFIG_FSL_ESDHC) u32 sdhc_clk; #endif -#if !defined(CONFIG_MPC8309) +#if !defined(CONFIG_ARCH_MPC8309) u32 enc_clk; #endif u32 lbiu_clk; @@ -122,7 +122,7 @@ int get_clocks(void) u32 qe_clk; u32 brg_clk; #endif -#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \ +#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) || \ defined(CONFIG_MPC837x) u32 pciexp1_clk; u32 pciexp2_clk; @@ -155,7 +155,7 @@ int get_clocks(void) sccr = im->clk.sccr; -#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \ +#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) || \ defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) { case 0: @@ -176,7 +176,7 @@ int get_clocks(void) } #endif -#if defined(CONFIG_MPC830x) || defined(CONFIG_MPC831x) || \ +#if defined(CONFIG_ARCH_MPC830X) || defined(CONFIG_MPC831x) || \ defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) switch ((sccr & SCCR_USBDRCM) >> SCCR_USBDRCM_SHIFT) { case 0: @@ -197,7 +197,7 @@ int get_clocks(void) } #endif -#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315) || \ +#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC8315) || \ defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) switch ((sccr & SCCR_TSEC2CM) >> SCCR_TSEC2CM_SHIFT) { case 0: @@ -252,7 +252,7 @@ int get_clocks(void) return -6; } #endif -#if !defined(CONFIG_MPC8309) +#if !defined(CONFIG_ARCH_MPC8309) switch ((sccr & SCCR_ENCCM) >> SCCR_ENCCM_SHIFT) { case 0: enc_clk = 0; @@ -317,20 +317,20 @@ int get_clocks(void) i2c1_clk = csb_clk; #elif defined(CONFIG_MPC832x) i2c1_clk = enc_clk; -#elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) +#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) i2c1_clk = enc_clk; #elif defined(CONFIG_FSL_ESDHC) i2c1_clk = sdhc_clk; #elif defined(CONFIG_MPC837x) i2c1_clk = enc_clk; -#elif defined(CONFIG_MPC8309) +#elif defined(CONFIG_ARCH_MPC8309) i2c1_clk = csb_clk; #endif #if !defined(CONFIG_MPC832x) i2c2_clk = csb_clk; /* i2c-2 clk is equal to csb clk */ #endif -#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \ +#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) || \ defined(CONFIG_MPC837x) switch ((sccr & SCCR_PCIEXP1CM) >> SCCR_PCIEXP1CM_SHIFT) { case 0: @@ -448,12 +448,12 @@ int get_clocks(void) #endif gd->arch.csb_clk = csb_clk; -#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \ +#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) || \ defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) gd->arch.tsec1_clk = tsec1_clk; gd->arch.tsec2_clk = tsec2_clk; gd->arch.usbdr_clk = usbdr_clk; -#elif defined(CONFIG_MPC8309) +#elif defined(CONFIG_ARCH_MPC8309) gd->arch.usbdr_clk = usbdr_clk; #endif #if defined(CONFIG_MPC834x) @@ -470,7 +470,7 @@ int get_clocks(void) #if !defined(CONFIG_MPC832x) gd->arch.i2c2_clk = i2c2_clk; #endif -#if !defined(CONFIG_MPC8309) +#if !defined(CONFIG_ARCH_MPC8309) gd->arch.enc_clk = enc_clk; #endif gd->arch.lbiu_clk = lbiu_clk; @@ -483,7 +483,7 @@ int get_clocks(void) gd->arch.qe_clk = qe_clk; gd->arch.brg_clk = brg_clk; #endif -#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \ +#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) || \ defined(CONFIG_MPC837x) gd->arch.pciexp1_clk = pciexp1_clk; gd->arch.pciexp2_clk = pciexp2_clk; @@ -540,7 +540,7 @@ static int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf(" DDR Secondary: %-4s MHz\n", strmhz(buf, gd->arch.mem_sec_clk)); #endif -#if !defined(CONFIG_MPC8309) +#if !defined(CONFIG_ARCH_MPC8309) printf(" SEC: %-4s MHz\n", strmhz(buf, gd->arch.enc_clk)); #endif @@ -558,7 +558,7 @@ static int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf(" SDHC: %-4s MHz\n", strmhz(buf, gd->arch.sdhc_clk)); #endif -#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \ +#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) || \ defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) printf(" TSEC1: %-4s MHz\n", strmhz(buf, gd->arch.tsec1_clk)); @@ -566,7 +566,7 @@ static int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) strmhz(buf, gd->arch.tsec2_clk)); printf(" USB DR: %-4s MHz\n", strmhz(buf, gd->arch.usbdr_clk)); -#elif defined(CONFIG_MPC8309) +#elif defined(CONFIG_ARCH_MPC8309) printf(" USB DR: %-4s MHz\n", strmhz(buf, gd->arch.usbdr_clk)); #endif @@ -574,7 +574,7 @@ static int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf(" USB MPH: %-4s MHz\n", strmhz(buf, gd->arch.usbmph_clk)); #endif -#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \ +#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) || \ defined(CONFIG_MPC837x) printf(" PCIEXP1: %-4s MHz\n", strmhz(buf, gd->arch.pciexp1_clk)); diff --git a/arch/powerpc/include/asm/arch-mpc83xx/gpio.h b/arch/powerpc/include/asm/arch-mpc83xx/gpio.h index 57f783ba14..4e5a352ac6 100644 --- a/arch/powerpc/include/asm/arch-mpc83xx/gpio.h +++ b/arch/powerpc/include/asm/arch-mpc83xx/gpio.h @@ -6,7 +6,7 @@ /* * The MCP83xx's 1-2 GPIO controllers each with 32 bits. */ -#if defined(CONFIG_MPC8313) || defined(CONFIG_MPC8308) || \ +#if defined(CONFIG_MPC8313) || defined(CONFIG_ARCH_MPC8308) || \ defined(CONFIG_MPC8315) #define MPC83XX_GPIO_CTRLRS 1 #elif defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) diff --git a/arch/powerpc/include/asm/fsl_lbc.h b/arch/powerpc/include/asm/fsl_lbc.h index b076d5e838..cf89e186a6 100644 --- a/arch/powerpc/include/asm/fsl_lbc.h +++ b/arch/powerpc/include/asm/fsl_lbc.h @@ -133,7 +133,7 @@ void lbc_sdram_init(void); #define OR_GPCM_EHTR_SHIFT 1 #define OR_GPCM_EHTR_CLEAR 0x00000000 #define OR_GPCM_EHTR_SET 0x00000002 -#if !defined(CONFIG_MPC8308) +#if !defined(CONFIG_ARCH_MPC8308) #define OR_GPCM_EAD 0x00000001 #define OR_GPCM_EAD_SHIFT 0 #endif diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h index d00cee95fb..700e2be0ee 100644 --- a/arch/powerpc/include/asm/global_data.h +++ b/arch/powerpc/include/asm/global_data.h @@ -35,12 +35,12 @@ struct arch_global_data { #else /* There are other clocks in the MPC83XX */ u32 csb_clk; -# if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \ +# if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) || \ defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) u32 tsec1_clk; u32 tsec2_clk; u32 usbdr_clk; -# elif defined(CONFIG_MPC8309) +# elif defined(CONFIG_ARCH_MPC8309) u32 usbdr_clk; # endif # if defined(CONFIG_MPC834x) @@ -53,7 +53,7 @@ struct arch_global_data { u32 enc_clk; u32 lbiu_clk; u32 lclk_clk; -# if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \ +# if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) || \ defined(CONFIG_MPC837x) u32 pciexp1_clk; u32 pciexp2_clk; diff --git a/arch/powerpc/include/asm/immap_83xx.h b/arch/powerpc/include/asm/immap_83xx.h index afef36f262..b10feb546c 100644 --- a/arch/powerpc/include/asm/immap_83xx.h +++ b/arch/powerpc/include/asm/immap_83xx.h @@ -59,12 +59,12 @@ typedef struct sysconf83xx { u32 obir; /* Output Buffer Impedance Register */ u8 res8[0xC]; u32 pecr1; /* PCI Express control register 1 */ -#if defined(CONFIG_MPC830x) +#if defined(CONFIG_ARCH_MPC830X) u32 sdhccr; /* eSDHC Control Registers for MPC830x */ #else u32 pecr2; /* PCI Express control register 2 */ #endif -#if defined(CONFIG_MPC8309) +#if defined(CONFIG_ARCH_MPC8309) u32 can_dbg_ctrl; u32 res9a; u32 gpr1; @@ -604,7 +604,7 @@ typedef struct serdes83xx { * On Chip ROM */ typedef struct rom83xx { -#if defined(CONFIG_MPC8309) +#if defined(CONFIG_ARCH_MPC8309) u8 mem[0x8000]; #else u8 mem[0x10000]; @@ -714,7 +714,7 @@ typedef struct immap { u8 res7[0xC0000]; } immap_t; -#elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315) +#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC8315) typedef struct immap { sysconf83xx_t sysconf; /* System configuration */ wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */ @@ -879,7 +879,7 @@ typedef struct immap { u8 res8[0xC0000]; u8 qe[0x100000]; /* QE block */ } immap_t; -#elif defined(CONFIG_MPC8309) +#elif defined(CONFIG_ARCH_MPC8309) typedef struct immap { sysconf83xx_t sysconf; /* System configuration */ wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */ diff --git a/arch/powerpc/include/asm/mpc8xxx_spi.h b/arch/powerpc/include/asm/mpc8xxx_spi.h index 432be05469..518d0c388a 100644 --- a/arch/powerpc/include/asm/mpc8xxx_spi.h +++ b/arch/powerpc/include/asm/mpc8xxx_spi.h @@ -10,7 +10,7 @@ #include -#if defined(CONFIG_MPC8308) || \ +#if defined(CONFIG_ARCH_MPC8308) || \ defined(CONFIG_MPC8313) || \ defined(CONFIG_MPC8315) || \ defined(CONFIG_MPC834x) || \ diff --git a/board/keymile/km83xx/km83xx.c b/board/keymile/km83xx/km83xx.c index 4818a4994a..ce5126aae6 100644 --- a/board/keymile/km83xx/km83xx.c +++ b/board/keymile/km83xx/km83xx.c @@ -56,7 +56,7 @@ const qe_iop_conf_t qe_iop_conf_tab[] = { {5, 2, 1, 0, 1}, /* UART2_RTS */ {5, 3, 2, 0, 2}, /* UART2_SIN */ {5, 1, 2, 0, 3}, /* UART2_CTS */ -#elif !defined(CONFIG_MPC8309) +#elif !defined(CONFIG_ARCH_MPC8309) /* Local Bus */ {0, 16, 1, 0, 3}, /* LA00 */ {0, 17, 1, 0, 3}, /* LA01 */ diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c index 70d02d3f93..505ae9b45f 100644 --- a/drivers/qe/qe.c +++ b/drivers/qe/qe.c @@ -119,7 +119,7 @@ static void qe_sdma_init(void) */ static u8 thread_snum[] = { /* Evthreads 16-29 are not supported in MPC8309 */ -#if !defined(CONFIG_MPC8309) +#if !defined(CONFIG_ARCH_MPC8309) 0x04, 0x05, 0x0c, 0x0d, 0x14, 0x15, 0x1c, 0x1d, 0x24, 0x25, 0x2c, 0x2d, diff --git a/drivers/ram/mpc83xx_sdram.c b/drivers/ram/mpc83xx_sdram.c index 441baeb6f1..e352329981 100644 --- a/drivers/ram/mpc83xx_sdram.c +++ b/drivers/ram/mpc83xx_sdram.c @@ -179,7 +179,7 @@ static int mpc83xx_sdram_static_init(ofnode node, u32 cs, u32 mapaddr, u32 size) case ODT_RD_NEVER: case ODT_RD_ONLY_CURRENT: case ODT_RD_ONLY_OTHER_CS: - if (!IS_ENABLED(CONFIG_MPC830x) && + if (!IS_ENABLED(CONFIG_ARCH_MPC830X) && !IS_ENABLED(CONFIG_MPC831x) && !IS_ENABLED(CONFIG_MPC8360) && !IS_ENABLED(CONFIG_MPC837x)) { @@ -210,7 +210,7 @@ static int mpc83xx_sdram_static_init(ofnode node, u32 cs, u32 mapaddr, u32 size) case ODT_WR_NEVER: case ODT_WR_ONLY_CURRENT: case ODT_WR_ONLY_OTHER_CS: - if (!IS_ENABLED(CONFIG_MPC830x) && + if (!IS_ENABLED(CONFIG_ARCH_MPC830X) && !IS_ENABLED(CONFIG_MPC831x) && !IS_ENABLED(CONFIG_MPC8360) && !IS_ENABLED(CONFIG_MPC837x)) { diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h index 3827ea464b..7bf91524c8 100644 --- a/include/configs/MPC8308RDB.h +++ b/include/configs/MPC8308RDB.h @@ -12,8 +12,6 @@ * High Level Configuration Options */ #define CONFIG_E300 1 /* E300 family */ -#define CONFIG_MPC830x 1 /* MPC830x family */ -#define CONFIG_MPC8308 1 /* MPC8308 CPU specific */ #ifdef CONFIG_MMC #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h index 52e62778a3..23ed4e54c7 100644 --- a/include/configs/hrcon.h +++ b/include/configs/hrcon.h @@ -13,8 +13,6 @@ */ #define CONFIG_E300 1 /* E300 family */ #define CONFIG_MPC83xx 1 /* MPC83xx family */ -#define CONFIG_MPC830x 1 /* MPC830x family */ -#define CONFIG_MPC8308 1 /* MPC8308 CPU specific */ #define CONFIG_HRCON 1 /* HRCON board specific */ #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR diff --git a/include/configs/km/km8309-common.h b/include/configs/km/km8309-common.h index 0e0b1b4605..3bd334c515 100644 --- a/include/configs/km/km8309-common.h +++ b/include/configs/km/km8309-common.h @@ -14,8 +14,6 @@ */ #define CONFIG_E300 1 /* E300 family */ #define CONFIG_QE 1 /* Has QE */ -#define CONFIG_MPC830x 1 /* MPC830x family */ -#define CONFIG_MPC8309 1 /* MPC8309 CPU specific */ #define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" diff --git a/include/configs/km/km83xx-common.h b/include/configs/km/km83xx-common.h index a76f606e3e..fb2a1cb39a 100644 --- a/include/configs/km/km83xx-common.h +++ b/include/configs/km/km83xx-common.h @@ -135,7 +135,7 @@ #define CONFIG_UEC_ETH #define CONFIG_ETHPRIME "UEC0" -#if !defined(CONFIG_MPC8309) +#if !defined(CONFIG_ARCH_MPC8309) #define CONFIG_UEC_ETH1 /* GETH1 */ #define UEC_VERBOSE_DEBUG 1 #endif diff --git a/include/configs/mpc8308_p1m.h b/include/configs/mpc8308_p1m.h index 98f030388c..c007877276 100644 --- a/include/configs/mpc8308_p1m.h +++ b/include/configs/mpc8308_p1m.h @@ -12,8 +12,6 @@ * High Level Configuration Options */ #define CONFIG_E300 1 /* E300 family */ -#define CONFIG_MPC830x 1 /* MPC830x family */ -#define CONFIG_MPC8308 1 /* MPC8308 CPU specific */ /* * On-board devices diff --git a/include/configs/strider.h b/include/configs/strider.h index 972543d6bd..89e0610871 100644 --- a/include/configs/strider.h +++ b/include/configs/strider.h @@ -13,8 +13,6 @@ */ #define CONFIG_E300 1 /* E300 family */ #define CONFIG_MPC83xx 1 /* MPC83xx family */ -#define CONFIG_MPC830x 1 /* MPC830x family */ -#define CONFIG_MPC8308 1 /* MPC8308 CPU specific */ #define CONFIG_STRIDER 1 /* STRIDER board specific */ #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR diff --git a/include/linux/immap_qe.h b/include/linux/immap_qe.h index 51800096b2..f7bc503ea3 100644 --- a/include/linux/immap_qe.h +++ b/include/linux/immap_qe.h @@ -16,7 +16,7 @@ #define QE_MURAM_SIZE 0xc000UL #define MAX_QE_RISC 2 #define QE_NUM_OF_SNUM 28 -#elif defined(CONFIG_MPC832x) || defined(CONFIG_MPC8309) +#elif defined(CONFIG_MPC832x) || defined(CONFIG_ARCH_MPC8309) #define QE_MURAM_SIZE 0x4000UL #define MAX_QE_RISC 1 #define QE_NUM_OF_SNUM 28 diff --git a/include/mpc83xx.h b/include/mpc83xx.h index a4c5bd3837..e93f50d0b3 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -129,7 +129,7 @@ #define SPCR_TSEC2EP 0x00000003 #define SPCR_TSEC2EP_SHIFT (31-31) -#elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \ +#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) || \ defined(CONFIG_MPC837x) /* SPCR bits - MPC8308, MPC831x and MPC837x specific */ /* TSEC data priority */ @@ -336,7 +336,7 @@ #define SICRH_SPI 0x00000003 #define SICRH_SPI_SD 0x00000001 -#elif defined(CONFIG_MPC8308) +#elif defined(CONFIG_ARCH_MPC8308) /* SICRL bits - MPC8308 specific */ #define SICRL_SPI_PF0 (0 << 28) #define SICRL_SPI_PF1 (1 << 28) @@ -384,7 +384,7 @@ #define SICRH_TSOBI2_V3P3 (0 << 0) #define SICRH_TSOBI2_V2P5 (1 << 0) -#elif defined(CONFIG_MPC8309) +#elif defined(CONFIG_ARCH_MPC8309) /* SICR_1 */ #define SICR_1_UART1_UART1S (0 << (30-2)) #define SICR_1_UART1_UART1RTS (1 << (30-2)) @@ -639,7 +639,7 @@ #define HRCWL_CE_TO_PLL_1X30 0x0000001E #define HRCWL_CE_TO_PLL_1X31 0x0000001F -#elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315) +#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC8315) #define HRCWL_SVCOD 0x30000000 #define HRCWL_SVCOD_SHIFT 28 #define HRCWL_SVCOD_DIV_2 0x00000000 @@ -654,7 +654,7 @@ #define HRCWL_SVCOD_DIV_8 0x10000000 #define HRCWL_SVCOD_DIV_2 0x20000000 #define HRCWL_SVCOD_DIV_1 0x30000000 -#elif defined(CONFIG_MPC8309) +#elif defined(CONFIG_ARCH_MPC8309) #define HRCWL_CEVCOD 0x000000C0 #define HRCWL_CEVCOD_SHIFT 6 @@ -765,7 +765,7 @@ #define HRCWH_ROM_LOC_LOCAL_16BIT 0x00600000 #define HRCWH_ROM_LOC_LOCAL_32BIT 0x00700000 -#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \ +#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) || \ defined(CONFIG_MPC837x) #define HRCWH_ROM_LOC_NAND_SP_8BIT 0x00100000 #define HRCWH_ROM_LOC_NAND_SP_16BIT 0x00200000 @@ -818,7 +818,7 @@ /* * RSR - Reset Status Register */ -#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \ +#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) || \ defined(CONFIG_MPC837x) #define RSR_RSTSRC 0xF0000000 /* Reset source */ #define RSR_RSTSRC_SHIFT 28 @@ -986,7 +986,7 @@ #define SCCR_USBDRCM_2 0x00200000 #define SCCR_USBDRCM_3 0x00300000 -#elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315) +#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC8315) /* SCCR bits - MPC8315/MPC8308 specific */ #define SCCR_TSEC1CM 0xc0000000 #define SCCR_TSEC1CM_SHIFT 30 @@ -1071,7 +1071,7 @@ #define SCCR_SATACM_1 0x00000055 #define SCCR_SATACM_2 0x000000aa #define SCCR_SATACM_3 0x000000ff -#elif defined(CONFIG_MPC8309) +#elif defined(CONFIG_ARCH_MPC8309) /* SCCR bits - MPC8309 specific */ #define SCCR_SDHCCM 0x0c000000 #define SCCR_SDHCCM_SHIFT 26 @@ -1117,7 +1117,7 @@ */ #define CSCONFIG_EN 0x80000000 #define CSCONFIG_AP 0x00800000 -#if defined(CONFIG_MPC830x) || defined(CONFIG_MPC831x) +#if defined(CONFIG_ARCH_MPC830X) || defined(CONFIG_MPC831x) #define CSCONFIG_ODT_RD_NEVER 0x00000000 #define CSCONFIG_ODT_RD_ONLY_CURRENT 0x00100000 #define CSCONFIG_ODT_RD_ONLY_OTHER_CS 0x00200000 @@ -1239,14 +1239,14 @@ #define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000 #define SDRAM_CFG_SDRAM_TYPE_SHIFT 24 #define SDRAM_CFG_DYN_PWR 0x00200000 -#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) +#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) #define SDRAM_CFG_DBW_MASK 0x00180000 #define SDRAM_CFG_DBW_16 0x00100000 #define SDRAM_CFG_DBW_32 0x00080000 #else #define SDRAM_CFG_32_BE 0x00080000 #endif -#if !defined(CONFIG_MPC8308) +#if !defined(CONFIG_ARCH_MPC8308) #define SDRAM_CFG_8_BE 0x00040000 #endif #define SDRAM_CFG_NCAP 0x00020000 diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index b16bc6ae34..d7d1b56359 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -1220,9 +1220,6 @@ CONFIG_MMC_SPI_SPEED CONFIG_MMC_SUNXI_SLOT CONFIG_MMU CONFIG_MONITOR_IS_IN_RAM -CONFIG_MPC8308 -CONFIG_MPC8309 -CONFIG_MPC830x CONFIG_MPC8313 CONFIG_MPC8313ERDB CONFIG_MPC8315 From 9403fc41c71fc4146ab0e890ed90b28fc053791f Mon Sep 17 00:00:00 2001 From: Mario Six Date: Mon, 21 Jan 2019 09:17:25 +0100 Subject: [PATCH 02/86] mpc83xx: Introduce ARCH_MPC831* Replace CONFIG_MPC833* with proper CONFIG_ARCH_MPC833* Kconfig options. Signed-off-by: Mario Six --- arch/powerpc/cpu/mpc83xx/Kconfig | 15 ++++++++ arch/powerpc/cpu/mpc83xx/cpu.c | 2 +- arch/powerpc/cpu/mpc83xx/cpu_init.c | 4 +- arch/powerpc/cpu/mpc83xx/fdt.c | 6 +-- arch/powerpc/cpu/mpc83xx/spd_sdram.c | 2 +- arch/powerpc/cpu/mpc83xx/speed.c | 40 ++++++++++---------- arch/powerpc/include/asm/arch-mpc83xx/gpio.h | 4 +- arch/powerpc/include/asm/global_data.h | 8 ++-- arch/powerpc/include/asm/immap_83xx.h | 4 +- arch/powerpc/include/asm/mpc8xxx_spi.h | 4 +- drivers/ram/mpc83xx_sdram.c | 4 +- include/configs/MPC8313ERDB.h | 2 - include/configs/MPC8315ERDB.h | 2 - include/configs/ids8313.h | 3 -- include/configs/ve8313.h | 2 - include/mpc83xx.h | 20 +++++----- scripts/config_whitelist.txt | 3 -- 17 files changed, 64 insertions(+), 61 deletions(-) diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index 142b924786..20780ba68b 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -17,6 +17,7 @@ config TARGET_SBC8349 config TARGET_VE8313 bool "Support ve8313" + select ARCH_MPC8313 config TARGET_VME8349 bool "Support vme8349" @@ -28,11 +29,13 @@ config TARGET_MPC8308RDB config TARGET_MPC8313ERDB bool "Support MPC8313ERDB" + select ARCH_MPC8313 select BOARD_EARLY_INIT_F select SUPPORT_SPL config TARGET_MPC8315ERDB bool "Support MPC8315ERDB" + select ARCH_MPC8315 select BOARD_EARLY_INIT_F config TARGET_MPC8323ERDB @@ -65,6 +68,7 @@ config TARGET_MPC837XERDB config TARGET_IDS8313 bool "Support ids8313" + select ARCH_MPC8313 select DM imply CMD_DM @@ -113,6 +117,17 @@ config ARCH_MPC8309 bool select ARCH_MPC830X +config ARCH_MPC831X + bool + +config ARCH_MPC8313 + bool + select ARCH_MPC831X + +config ARCH_MPC8315 + bool + select ARCH_MPC831X + source "board/esd/vme8349/Kconfig" source "board/freescale/mpc8308rdb/Kconfig" source "board/freescale/mpc8313erdb/Kconfig" diff --git a/arch/powerpc/cpu/mpc83xx/cpu.c b/arch/powerpc/cpu/mpc83xx/cpu.c index b29f271e9b..8a88068fdb 100644 --- a/arch/powerpc/cpu/mpc83xx/cpu.c +++ b/arch/powerpc/cpu/mpc83xx/cpu.c @@ -18,7 +18,7 @@ #include #include #include -#if defined(CONFIG_BOOTCOUNT_LIMIT) && !defined(CONFIG_MPC831x) +#if defined(CONFIG_BOOTCOUNT_LIMIT) && !defined(CONFIG_ARCH_MPC831X) #include #include #endif diff --git a/arch/powerpc/cpu/mpc83xx/cpu_init.c b/arch/powerpc/cpu/mpc83xx/cpu_init.c index 1555205e06..7d8d5516b4 100644 --- a/arch/powerpc/cpu/mpc83xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc83xx/cpu_init.c @@ -240,7 +240,7 @@ void cpu_init_f (volatile immap_t * im) /* System General Purpose Register */ #ifdef CONFIG_SYS_SICRH -#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC8313) +#if defined(CONFIG_MPC834x) || defined(CONFIG_ARCH_MPC8313) /* regarding to MPC34x manual rev.1 bits 28..29 must be preserved */ __raw_writel((im->sysconf.sicrh & 0x0000000C) | CONFIG_SYS_SICRH, &im->sysconf.sicrh); @@ -312,7 +312,7 @@ void cpu_init_f (volatile immap_t * im) im->gpio[1].dat = CONFIG_SYS_GPIO2_DAT; im->gpio[1].dir = CONFIG_SYS_GPIO2_DIR; #endif -#if defined(CONFIG_USB_EHCI_FSL) && defined(CONFIG_MPC831x) +#if defined(CONFIG_USB_EHCI_FSL) && defined(CONFIG_ARCH_MPC831X) uint32_t temp; struct usb_ehci *ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB1_ADDR; diff --git a/arch/powerpc/cpu/mpc83xx/fdt.c b/arch/powerpc/cpu/mpc83xx/fdt.c index 0ecafd708f..cfd391b78a 100644 --- a/arch/powerpc/cpu/mpc83xx/fdt.c +++ b/arch/powerpc/cpu/mpc83xx/fdt.c @@ -16,7 +16,7 @@ extern void ft_qe_setup(void *blob); DECLARE_GLOBAL_DATA_PTR; #if defined(CONFIG_BOOTCOUNT_LIMIT) && \ - (defined(CONFIG_QE) && !defined(CONFIG_MPC831x)) + (defined(CONFIG_QE) && !defined(CONFIG_ARCH_MPC831X)) #include void fdt_fixup_muram (void *blob) @@ -52,7 +52,7 @@ void ft_cpu_setup(void *blob, bd_t *bd) #if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) ||\ defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3) ||\ defined(CONFIG_HAS_ETH4) || defined(CONFIG_HAS_ETH5) -#ifdef CONFIG_MPC8313 +#ifdef CONFIG_ARCH_MPC8313 /* * mpc8313e erratum IPIC1 swapped TSEC interrupt ID numbers on rev. 1 * h/w (see AN3545). The base device tree in use has rev. 1 ID numbers, @@ -123,7 +123,7 @@ void ft_cpu_setup(void *blob, bd_t *bd) fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); #if defined(CONFIG_BOOTCOUNT_LIMIT) && \ - (defined(CONFIG_QE) && !defined(CONFIG_MPC831x)) + (defined(CONFIG_QE) && !defined(CONFIG_ARCH_MPC831X)) fdt_fixup_muram (blob); #endif } diff --git a/arch/powerpc/cpu/mpc83xx/spd_sdram.c b/arch/powerpc/cpu/mpc83xx/spd_sdram.c index 97ef77121b..3f18aadf19 100644 --- a/arch/powerpc/cpu/mpc83xx/spd_sdram.c +++ b/arch/powerpc/cpu/mpc83xx/spd_sdram.c @@ -31,7 +31,7 @@ void board_add_ram_info(int use_default) printf(" (DDR%d", ((ddr->sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) >> SDRAM_CFG_SDRAM_TYPE_SHIFT) - 1); -#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) +#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) if ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) == SDRAM_CFG_DBW_16) puts(", 16-bit"); else if ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) == SDRAM_CFG_DBW_32) diff --git a/arch/powerpc/cpu/mpc83xx/speed.c b/arch/powerpc/cpu/mpc83xx/speed.c index d537af5130..9f09d2955f 100644 --- a/arch/powerpc/cpu/mpc83xx/speed.c +++ b/arch/powerpc/cpu/mpc83xx/speed.c @@ -85,7 +85,7 @@ int get_clocks(void) u32 lcrr; u32 csb_clk; -#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) || \ +#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) u32 tsec1_clk; u32 tsec2_clk; @@ -101,7 +101,7 @@ int get_clocks(void) #if !defined(CONFIG_MPC832x) u32 i2c2_clk; #endif -#if defined(CONFIG_MPC8315) +#if defined(CONFIG_ARCH_MPC8315) u32 tdm_clk; #endif #if defined(CONFIG_FSL_ESDHC) @@ -122,12 +122,12 @@ int get_clocks(void) u32 qe_clk; u32 brg_clk; #endif -#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) || \ +#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ defined(CONFIG_MPC837x) u32 pciexp1_clk; u32 pciexp2_clk; #endif -#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315) +#if defined(CONFIG_MPC837x) || defined(CONFIG_ARCH_MPC8315) u32 sata_clk; #endif @@ -155,7 +155,7 @@ int get_clocks(void) sccr = im->clk.sccr; -#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) || \ +#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) { case 0: @@ -176,7 +176,7 @@ int get_clocks(void) } #endif -#if defined(CONFIG_ARCH_MPC830X) || defined(CONFIG_MPC831x) || \ +#if defined(CONFIG_ARCH_MPC830X) || defined(CONFIG_ARCH_MPC831X) || \ defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) switch ((sccr & SCCR_USBDRCM) >> SCCR_USBDRCM_SHIFT) { case 0: @@ -197,7 +197,7 @@ int get_clocks(void) } #endif -#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC8315) || \ +#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC8315) || \ defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) switch ((sccr & SCCR_TSEC2CM) >> SCCR_TSEC2CM_SHIFT) { case 0: @@ -216,7 +216,7 @@ int get_clocks(void) /* unknown SCCR_TSEC2CM value */ return -4; } -#elif defined(CONFIG_MPC8313) +#elif defined(CONFIG_ARCH_MPC8313) tsec2_clk = tsec1_clk; if (!(sccr & SCCR_TSEC1ON)) @@ -291,7 +291,7 @@ int get_clocks(void) return -8; } #endif -#if defined(CONFIG_MPC8315) +#if defined(CONFIG_ARCH_MPC8315) switch ((sccr & SCCR_TDMCM) >> SCCR_TDMCM_SHIFT) { case 0: tdm_clk = 0; @@ -317,7 +317,7 @@ int get_clocks(void) i2c1_clk = csb_clk; #elif defined(CONFIG_MPC832x) i2c1_clk = enc_clk; -#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) +#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) i2c1_clk = enc_clk; #elif defined(CONFIG_FSL_ESDHC) i2c1_clk = sdhc_clk; @@ -330,7 +330,7 @@ int get_clocks(void) i2c2_clk = csb_clk; /* i2c-2 clk is equal to csb clk */ #endif -#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) || \ +#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ defined(CONFIG_MPC837x) switch ((sccr & SCCR_PCIEXP1CM) >> SCCR_PCIEXP1CM_SHIFT) { case 0: @@ -369,7 +369,7 @@ int get_clocks(void) } #endif -#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315) +#if defined(CONFIG_MPC837x) || defined(CONFIG_ARCH_MPC8315) switch ((sccr & SCCR_SATA1CM) >> SCCR_SATA1CM_SHIFT) { case 0: sata_clk = 0; @@ -448,7 +448,7 @@ int get_clocks(void) #endif gd->arch.csb_clk = csb_clk; -#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) || \ +#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) gd->arch.tsec1_clk = tsec1_clk; gd->arch.tsec2_clk = tsec2_clk; @@ -459,7 +459,7 @@ int get_clocks(void) #if defined(CONFIG_MPC834x) gd->arch.usbmph_clk = usbmph_clk; #endif -#if defined(CONFIG_MPC8315) +#if defined(CONFIG_ARCH_MPC8315) gd->arch.tdm_clk = tdm_clk; #endif #if defined(CONFIG_FSL_ESDHC) @@ -483,12 +483,12 @@ int get_clocks(void) gd->arch.qe_clk = qe_clk; gd->arch.brg_clk = brg_clk; #endif -#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) || \ +#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ defined(CONFIG_MPC837x) gd->arch.pciexp1_clk = pciexp1_clk; gd->arch.pciexp2_clk = pciexp2_clk; #endif -#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315) +#if defined(CONFIG_MPC837x) || defined(CONFIG_ARCH_MPC8315) gd->arch.sata_clk = sata_clk; #endif gd->pci_clk = pci_sync_in; @@ -550,7 +550,7 @@ static int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf(" I2C2: %-4s MHz\n", strmhz(buf, gd->arch.i2c2_clk)); #endif -#if defined(CONFIG_MPC8315) +#if defined(CONFIG_ARCH_MPC8315) printf(" TDM: %-4s MHz\n", strmhz(buf, gd->arch.tdm_clk)); #endif @@ -558,7 +558,7 @@ static int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf(" SDHC: %-4s MHz\n", strmhz(buf, gd->arch.sdhc_clk)); #endif -#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) || \ +#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) printf(" TSEC1: %-4s MHz\n", strmhz(buf, gd->arch.tsec1_clk)); @@ -574,14 +574,14 @@ static int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf(" USB MPH: %-4s MHz\n", strmhz(buf, gd->arch.usbmph_clk)); #endif -#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) || \ +#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ defined(CONFIG_MPC837x) printf(" PCIEXP1: %-4s MHz\n", strmhz(buf, gd->arch.pciexp1_clk)); printf(" PCIEXP2: %-4s MHz\n", strmhz(buf, gd->arch.pciexp2_clk)); #endif -#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315) +#if defined(CONFIG_MPC837x) || defined(CONFIG_ARCH_MPC8315) printf(" SATA: %-4s MHz\n", strmhz(buf, gd->arch.sata_clk)); #endif diff --git a/arch/powerpc/include/asm/arch-mpc83xx/gpio.h b/arch/powerpc/include/asm/arch-mpc83xx/gpio.h index 4e5a352ac6..74ba91a469 100644 --- a/arch/powerpc/include/asm/arch-mpc83xx/gpio.h +++ b/arch/powerpc/include/asm/arch-mpc83xx/gpio.h @@ -6,8 +6,8 @@ /* * The MCP83xx's 1-2 GPIO controllers each with 32 bits. */ -#if defined(CONFIG_MPC8313) || defined(CONFIG_ARCH_MPC8308) || \ - defined(CONFIG_MPC8315) +#if defined(CONFIG_ARCH_MPC8313) || defined(CONFIG_ARCH_MPC8308) || \ + defined(CONFIG_ARCH_MPC8315) #define MPC83XX_GPIO_CTRLRS 1 #elif defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) #define MPC83XX_GPIO_CTRLRS 2 diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h index 700e2be0ee..0c3a4ade5c 100644 --- a/arch/powerpc/include/asm/global_data.h +++ b/arch/powerpc/include/asm/global_data.h @@ -35,7 +35,7 @@ struct arch_global_data { #else /* There are other clocks in the MPC83XX */ u32 csb_clk; -# if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) || \ +# if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) u32 tsec1_clk; u32 tsec2_clk; @@ -46,19 +46,19 @@ struct arch_global_data { # if defined(CONFIG_MPC834x) u32 usbmph_clk; # endif /* CONFIG_MPC834x */ -# if defined(CONFIG_MPC8315) +# if defined(CONFIG_ARCH_MPC8315) u32 tdm_clk; # endif u32 core_clk; u32 enc_clk; u32 lbiu_clk; u32 lclk_clk; -# if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) || \ +# if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ defined(CONFIG_MPC837x) u32 pciexp1_clk; u32 pciexp2_clk; # endif -# if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315) +# if defined(CONFIG_MPC837x) || defined(CONFIG_ARCH_MPC8315) u32 sata_clk; # endif # if defined(CONFIG_MPC8360) diff --git a/arch/powerpc/include/asm/immap_83xx.h b/arch/powerpc/include/asm/immap_83xx.h index b10feb546c..d22d887bab 100644 --- a/arch/powerpc/include/asm/immap_83xx.h +++ b/arch/powerpc/include/asm/immap_83xx.h @@ -679,7 +679,7 @@ typedef struct immap { #define CONFIG_SYS_MPC83xx_USB2_OFFSET 0x23000 #endif -#elif defined(CONFIG_MPC8313) +#elif defined(CONFIG_ARCH_MPC8313) typedef struct immap { sysconf83xx_t sysconf; /* System configuration */ wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */ @@ -714,7 +714,7 @@ typedef struct immap { u8 res7[0xC0000]; } immap_t; -#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC8315) +#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC8315) typedef struct immap { sysconf83xx_t sysconf; /* System configuration */ wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */ diff --git a/arch/powerpc/include/asm/mpc8xxx_spi.h b/arch/powerpc/include/asm/mpc8xxx_spi.h index 518d0c388a..3edd561007 100644 --- a/arch/powerpc/include/asm/mpc8xxx_spi.h +++ b/arch/powerpc/include/asm/mpc8xxx_spi.h @@ -11,8 +11,8 @@ #include #if defined(CONFIG_ARCH_MPC8308) || \ - defined(CONFIG_MPC8313) || \ - defined(CONFIG_MPC8315) || \ + defined(CONFIG_ARCH_MPC8313) || \ + defined(CONFIG_ARCH_MPC8315) || \ defined(CONFIG_MPC834x) || \ defined(CONFIG_MPC837x) diff --git a/drivers/ram/mpc83xx_sdram.c b/drivers/ram/mpc83xx_sdram.c index e352329981..58db7948c1 100644 --- a/drivers/ram/mpc83xx_sdram.c +++ b/drivers/ram/mpc83xx_sdram.c @@ -180,7 +180,7 @@ static int mpc83xx_sdram_static_init(ofnode node, u32 cs, u32 mapaddr, u32 size) case ODT_RD_ONLY_CURRENT: case ODT_RD_ONLY_OTHER_CS: if (!IS_ENABLED(CONFIG_ARCH_MPC830X) && - !IS_ENABLED(CONFIG_MPC831x) && + !IS_ENABLED(CONFIG_ARCH_MPC831X) && !IS_ENABLED(CONFIG_MPC8360) && !IS_ENABLED(CONFIG_MPC837x)) { debug("%s: odt_rd_cfg value %d invalid.\n", @@ -211,7 +211,7 @@ static int mpc83xx_sdram_static_init(ofnode node, u32 cs, u32 mapaddr, u32 size) case ODT_WR_ONLY_CURRENT: case ODT_WR_ONLY_OTHER_CS: if (!IS_ENABLED(CONFIG_ARCH_MPC830X) && - !IS_ENABLED(CONFIG_MPC831x) && + !IS_ENABLED(CONFIG_ARCH_MPC831X) && !IS_ENABLED(CONFIG_MPC8360) && !IS_ENABLED(CONFIG_MPC837x)) { debug("%s: odt_wr_cfg value %d invalid.\n", diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h index cfa5b56524..c5a8065d6a 100644 --- a/include/configs/MPC8313ERDB.h +++ b/include/configs/MPC8313ERDB.h @@ -13,8 +13,6 @@ * High Level Configuration Options */ #define CONFIG_E300 1 -#define CONFIG_MPC831x 1 -#define CONFIG_MPC8313 1 #define CONFIG_MPC8313ERDB 1 #ifdef CONFIG_NAND diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index 0ccf4acb82..b8506321af 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -22,8 +22,6 @@ * High Level Configuration Options */ #define CONFIG_E300 1 /* E300 family */ -#define CONFIG_MPC831x 1 /* MPC831x CPU family */ -#define CONFIG_MPC8315 1 /* MPC8315 CPU specific */ #define CONFIG_MPC8315ERDB 1 /* MPC8315ERDB board specific */ /* diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h index 7e4c497fe0..caa3dd1f1a 100644 --- a/include/configs/ids8313.h +++ b/include/configs/ids8313.h @@ -14,9 +14,6 @@ /* * High Level Configuration Options */ -#define CONFIG_MPC831x -#define CONFIG_MPC8313 - #define CONFIG_FSL_ELBC #define CONFIG_BOOT_RETRY_TIME 900 diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h index 85f678e5c4..791eac363b 100644 --- a/include/configs/ve8313.h +++ b/include/configs/ve8313.h @@ -16,8 +16,6 @@ * High Level Configuration Options */ #define CONFIG_E300 1 -#define CONFIG_MPC831x 1 -#define CONFIG_MPC8313 1 #define CONFIG_PCI_INDIRECT_BRIDGE 1 #define CONFIG_FSL_ELBC 1 diff --git a/include/mpc83xx.h b/include/mpc83xx.h index e93f50d0b3..0da271b2f3 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -129,7 +129,7 @@ #define SPCR_TSEC2EP 0x00000003 #define SPCR_TSEC2EP_SHIFT (31-31) -#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) || \ +#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ defined(CONFIG_MPC837x) /* SPCR bits - MPC8308, MPC831x and MPC837x specific */ /* TSEC data priority */ @@ -216,7 +216,7 @@ #define SICRL_URT_CTPR 0x06000000 #define SICRL_IRQ_CTPR 0x00C00000 -#elif defined(CONFIG_MPC8313) +#elif defined(CONFIG_ARCH_MPC8313) /* SICRL bits - MPC8313 specific */ #define SICRL_LBC 0x30000000 #define SICRL_UART 0x0C000000 @@ -248,7 +248,7 @@ #define SICRH_TSOBI1 0x00000002 #define SICRH_TSOBI2 0x00000001 -#elif defined(CONFIG_MPC8315) +#elif defined(CONFIG_ARCH_MPC8315) /* SICRL bits - MPC8315 specific */ #define SICRL_DMA_CH0 0xc0000000 #define SICRL_DMA_SPI 0x30000000 @@ -639,7 +639,7 @@ #define HRCWL_CE_TO_PLL_1X30 0x0000001E #define HRCWL_CE_TO_PLL_1X31 0x0000001F -#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC8315) +#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC8315) #define HRCWL_SVCOD 0x30000000 #define HRCWL_SVCOD_SHIFT 28 #define HRCWL_SVCOD_DIV_2 0x00000000 @@ -765,7 +765,7 @@ #define HRCWH_ROM_LOC_LOCAL_16BIT 0x00600000 #define HRCWH_ROM_LOC_LOCAL_32BIT 0x00700000 -#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) || \ +#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ defined(CONFIG_MPC837x) #define HRCWH_ROM_LOC_NAND_SP_8BIT 0x00100000 #define HRCWH_ROM_LOC_NAND_SP_16BIT 0x00200000 @@ -818,7 +818,7 @@ /* * RSR - Reset Status Register */ -#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) || \ +#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ defined(CONFIG_MPC837x) #define RSR_RSTSRC 0xF0000000 /* Reset source */ #define RSR_RSTSRC_SHIFT 28 @@ -965,7 +965,7 @@ #define SCCR_USBCM_2 0x00A00000 #define SCCR_USBCM_3 0x00F00000 -#elif defined(CONFIG_MPC8313) +#elif defined(CONFIG_ARCH_MPC8313) /* TSEC1 bits are for TSEC2 as well */ #define SCCR_TSEC1CM 0xc0000000 #define SCCR_TSEC1CM_SHIFT 30 @@ -986,7 +986,7 @@ #define SCCR_USBDRCM_2 0x00200000 #define SCCR_USBDRCM_3 0x00300000 -#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC8315) +#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC8315) /* SCCR bits - MPC8315/MPC8308 specific */ #define SCCR_TSEC1CM 0xc0000000 #define SCCR_TSEC1CM_SHIFT 30 @@ -1117,7 +1117,7 @@ */ #define CSCONFIG_EN 0x80000000 #define CSCONFIG_AP 0x00800000 -#if defined(CONFIG_ARCH_MPC830X) || defined(CONFIG_MPC831x) +#if defined(CONFIG_ARCH_MPC830X) || defined(CONFIG_ARCH_MPC831X) #define CSCONFIG_ODT_RD_NEVER 0x00000000 #define CSCONFIG_ODT_RD_ONLY_CURRENT 0x00100000 #define CSCONFIG_ODT_RD_ONLY_OTHER_CS 0x00200000 @@ -1239,7 +1239,7 @@ #define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000 #define SDRAM_CFG_SDRAM_TYPE_SHIFT 24 #define SDRAM_CFG_DYN_PWR 0x00200000 -#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) +#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) #define SDRAM_CFG_DBW_MASK 0x00180000 #define SDRAM_CFG_DBW_16 0x00100000 #define SDRAM_CFG_DBW_32 0x00080000 diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index d7d1b56359..d7bd37adf5 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -1220,11 +1220,8 @@ CONFIG_MMC_SPI_SPEED CONFIG_MMC_SUNXI_SLOT CONFIG_MMU CONFIG_MONITOR_IS_IN_RAM -CONFIG_MPC8313 CONFIG_MPC8313ERDB -CONFIG_MPC8315 CONFIG_MPC8315ERDB -CONFIG_MPC831x CONFIG_MPC832XEMDS CONFIG_MPC832x CONFIG_MPC8349 From bd3b867eb988b6796909765310cd2ae8b2b3cd94 Mon Sep 17 00:00:00 2001 From: Mario Six Date: Mon, 21 Jan 2019 09:17:26 +0100 Subject: [PATCH 03/86] mpc83xx: Introduce ARCH_MPC832* Replace CONFIG_MPC832* with proper CONFIG_ARCH_MPC832* Kconfig options. Signed-off-by: Mario Six --- arch/powerpc/cpu/mpc83xx/Kconfig | 7 +++++++ arch/powerpc/cpu/mpc83xx/speed.c | 10 +++++----- arch/powerpc/include/asm/immap_83xx.h | 2 +- include/configs/MPC8323ERDB.h | 1 - include/configs/MPC832XEMDS.h | 1 - include/configs/km/km8321-common.h | 1 - include/linux/immap_qe.h | 2 +- include/mpc83xx.h | 6 +++--- scripts/config_whitelist.txt | 1 - 9 files changed, 17 insertions(+), 14 deletions(-) diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index 20780ba68b..1b9402e024 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -40,9 +40,11 @@ config TARGET_MPC8315ERDB config TARGET_MPC8323ERDB bool "Support MPC8323ERDB" + select ARCH_MPC832X config TARGET_MPC832XEMDS bool "Support MPC832XEMDS" + select ARCH_MPC832X select BOARD_EARLY_INIT_F config TARGET_MPC8349EMDS @@ -82,11 +84,13 @@ config TARGET_SUVD3 bool "Support suvd3" select ARCH_MPC8309 if SYS_EXTRA_OPTIONS="KMTEGR1" select ARCH_MPC8309 if SYS_EXTRA_OPTIONS="KMVECT1" + select ARCH_MPC832X if SYS_EXTRA_OPTIONS="SUVD3" imply CMD_CRAMFS imply FS_CRAMFS config TARGET_TUXX1 bool "Support tuxx1" + select ARCH_MPC832X imply CMD_CRAMFS imply FS_CRAMFS @@ -128,6 +132,9 @@ config ARCH_MPC8315 bool select ARCH_MPC831X +config ARCH_MPC832X + bool + source "board/esd/vme8349/Kconfig" source "board/freescale/mpc8308rdb/Kconfig" source "board/freescale/mpc8313erdb/Kconfig" diff --git a/arch/powerpc/cpu/mpc83xx/speed.c b/arch/powerpc/cpu/mpc83xx/speed.c index 9f09d2955f..ab025af70d 100644 --- a/arch/powerpc/cpu/mpc83xx/speed.c +++ b/arch/powerpc/cpu/mpc83xx/speed.c @@ -98,7 +98,7 @@ int get_clocks(void) #endif u32 core_clk; u32 i2c1_clk; -#if !defined(CONFIG_MPC832x) +#if !defined(CONFIG_ARCH_MPC832X) u32 i2c2_clk; #endif #if defined(CONFIG_ARCH_MPC8315) @@ -315,7 +315,7 @@ int get_clocks(void) i2c1_clk = tsec2_clk; #elif defined(CONFIG_MPC8360) i2c1_clk = csb_clk; -#elif defined(CONFIG_MPC832x) +#elif defined(CONFIG_ARCH_MPC832X) i2c1_clk = enc_clk; #elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) i2c1_clk = enc_clk; @@ -326,7 +326,7 @@ int get_clocks(void) #elif defined(CONFIG_ARCH_MPC8309) i2c1_clk = csb_clk; #endif -#if !defined(CONFIG_MPC832x) +#if !defined(CONFIG_ARCH_MPC832X) i2c2_clk = csb_clk; /* i2c-2 clk is equal to csb clk */ #endif @@ -467,7 +467,7 @@ int get_clocks(void) #endif gd->arch.core_clk = core_clk; gd->arch.i2c1_clk = i2c1_clk; -#if !defined(CONFIG_MPC832x) +#if !defined(CONFIG_ARCH_MPC832X) gd->arch.i2c2_clk = i2c2_clk; #endif #if !defined(CONFIG_ARCH_MPC8309) @@ -546,7 +546,7 @@ static int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #endif printf(" I2C1: %-4s MHz\n", strmhz(buf, gd->arch.i2c1_clk)); -#if !defined(CONFIG_MPC832x) +#if !defined(CONFIG_ARCH_MPC832X) printf(" I2C2: %-4s MHz\n", strmhz(buf, gd->arch.i2c2_clk)); #endif diff --git a/arch/powerpc/include/asm/immap_83xx.h b/arch/powerpc/include/asm/immap_83xx.h index d22d887bab..318b79d0b8 100644 --- a/arch/powerpc/include/asm/immap_83xx.h +++ b/arch/powerpc/include/asm/immap_83xx.h @@ -843,7 +843,7 @@ typedef struct immap { u8 qe[0x100000]; /* QE block */ } immap_t; -#elif defined(CONFIG_MPC832x) +#elif defined(CONFIG_ARCH_MPC832X) typedef struct immap { sysconf83xx_t sysconf; /* System configuration */ wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */ diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index 578202f3be..bd1b1bb0a7 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -14,7 +14,6 @@ */ #define CONFIG_E300 1 /* E300 family */ #define CONFIG_QE 1 /* Has QE */ -#define CONFIG_MPC832x 1 /* MPC832x CPU specific */ /* * System Clock Setup diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index 8f11d9b3a4..0bb7db9bc3 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -11,7 +11,6 @@ */ #define CONFIG_E300 1 /* E300 family */ #define CONFIG_QE 1 /* Has QE */ -#define CONFIG_MPC832x 1 /* MPC832x CPU specific */ #define CONFIG_MPC832XEMDS 1 /* MPC832XEMDS board specific */ /* diff --git a/include/configs/km/km8321-common.h b/include/configs/km/km8321-common.h index 41b3ba2842..a121a445f7 100644 --- a/include/configs/km/km8321-common.h +++ b/include/configs/km/km8321-common.h @@ -26,7 +26,6 @@ * High Level Configuration Options */ #define CONFIG_QE /* Has QE */ -#define CONFIG_MPC832x /* MPC832x CPU specific */ #define CONFIG_KM8321 /* Keymile PBEC8321 board specific */ #define CONFIG_KM_DEF_ARCH "arch=ppc_8xx\0" diff --git a/include/linux/immap_qe.h b/include/linux/immap_qe.h index f7bc503ea3..6552d0e3c5 100644 --- a/include/linux/immap_qe.h +++ b/include/linux/immap_qe.h @@ -16,7 +16,7 @@ #define QE_MURAM_SIZE 0xc000UL #define MAX_QE_RISC 2 #define QE_NUM_OF_SNUM 28 -#elif defined(CONFIG_MPC832x) || defined(CONFIG_ARCH_MPC8309) +#elif defined(CONFIG_ARCH_MPC832X) || defined(CONFIG_ARCH_MPC8309) #define QE_MURAM_SIZE 0x4000UL #define MAX_QE_RISC 1 #define QE_NUM_OF_SNUM 28 diff --git a/include/mpc83xx.h b/include/mpc83xx.h index 0da271b2f3..0f4466ae89 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -208,7 +208,7 @@ #define SICRH_UC2E1OBI 0x00000002 #define SICRH_UC2E2OBI 0x00000001 -#elif defined(CONFIG_MPC832x) +#elif defined(CONFIG_ARCH_MPC832X) /* SICRL bits - MPC832x specific */ #define SICRL_LDP_LCS_A 0x80000000 #define SICRL_IRQ_CKS 0x20000000 @@ -593,7 +593,7 @@ #define HRCWL_CORE_TO_CSB_2_5X1 0x00050000 #define HRCWL_CORE_TO_CSB_3X1 0x00060000 -#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x) +#if defined(CONFIG_MPC8360) || defined(CONFIG_ARCH_MPC832X) #define HRCWL_CEVCOD 0x000000C0 #define HRCWL_CEVCOD_SHIFT 6 #define HRCWL_CE_PLL_VCO_DIV_4 0x00000000 @@ -1126,7 +1126,7 @@ #define CSCONFIG_ODT_WR_ONLY_CURRENT 0x00010000 #define CSCONFIG_ODT_WR_ONLY_OTHER_CS 0x00020000 #define CSCONFIG_ODT_WR_ALL 0x00040000 -#elif defined(CONFIG_MPC832x) +#elif defined(CONFIG_ARCH_MPC832X) #define CSCONFIG_ODT_RD_CFG 0x00400000 #define CSCONFIG_ODT_WR_CFG 0x00040000 #elif defined(CONFIG_MPC8360) || defined(CONFIG_MPC837x) diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index d7bd37adf5..481076e9d2 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -1223,7 +1223,6 @@ CONFIG_MONITOR_IS_IN_RAM CONFIG_MPC8313ERDB CONFIG_MPC8315ERDB CONFIG_MPC832XEMDS -CONFIG_MPC832x CONFIG_MPC8349 CONFIG_MPC8349ITX CONFIG_MPC834x From d5cfa4aa5d6422ad654bbc4032361c2367439de8 Mon Sep 17 00:00:00 2001 From: Mario Six Date: Mon, 21 Jan 2019 09:17:27 +0100 Subject: [PATCH 04/86] mpc83xx: Introduce ARCH_MPC834* Replace CONFIG_MPC834* with proper CONFIG_ARCH_MPC834* Kconfig options. Signed-off-by: Mario Six --- arch/powerpc/cpu/mpc83xx/Kconfig | 12 +++++++++++ arch/powerpc/cpu/mpc83xx/cpu_init.c | 2 +- arch/powerpc/cpu/mpc83xx/spd_sdram.c | 2 +- arch/powerpc/cpu/mpc83xx/speed.c | 22 ++++++++++---------- arch/powerpc/include/asm/arch-mpc83xx/gpio.h | 2 +- arch/powerpc/include/asm/fsl_lbc.h | 8 +++---- arch/powerpc/include/asm/global_data.h | 6 +++--- arch/powerpc/include/asm/immap_83xx.h | 6 +++--- arch/powerpc/include/asm/mpc8xxx_spi.h | 2 +- drivers/pci/pci_auto.c | 2 +- drivers/pci/pci_auto_old.c | 2 +- include/configs/MPC8349EMDS.h | 2 -- include/configs/MPC8349ITX.h | 3 --- include/configs/TQM834x.h | 2 -- include/configs/sbc8349.h | 2 -- include/configs/vme8349.h | 2 -- include/mpc83xx.h | 18 ++++++++-------- include/usb/ehci-ci.h | 2 +- scripts/config_whitelist.txt | 2 -- 19 files changed, 49 insertions(+), 50 deletions(-) diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index 1b9402e024..6cca45e402 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -14,6 +14,7 @@ config TARGET_MPC8308_P1M config TARGET_SBC8349 bool "Support sbc8349" + select ARCH_MPC8349 config TARGET_VE8313 bool "Support ve8313" @@ -21,6 +22,7 @@ config TARGET_VE8313 config TARGET_VME8349 bool "Support vme8349" + select ARCH_MPC8349 config TARGET_MPC8308RDB bool "Support MPC8308RDB" @@ -49,6 +51,7 @@ config TARGET_MPC832XEMDS config TARGET_MPC8349EMDS bool "Support MPC8349EMDS" + select ARCH_MPC8349 select BOARD_EARLY_INIT_F select SYS_FSL_DDR select SYS_FSL_DDR_BE @@ -56,6 +59,7 @@ config TARGET_MPC8349EMDS config TARGET_MPC8349ITX bool "Support MPC8349ITX" + select ARCH_MPC8349 imply CMD_IRQ config TARGET_MPC837XEMDS @@ -96,6 +100,7 @@ config TARGET_TUXX1 config TARGET_TQM834X bool "Support TQM834x" + select ARCH_MPC8349 config TARGET_HRCON bool "Support hrcon" @@ -135,6 +140,13 @@ config ARCH_MPC8315 config ARCH_MPC832X bool +config ARCH_MPC834X + bool + +config ARCH_MPC8349 + bool + select ARCH_MPC834X + source "board/esd/vme8349/Kconfig" source "board/freescale/mpc8308rdb/Kconfig" source "board/freescale/mpc8313erdb/Kconfig" diff --git a/arch/powerpc/cpu/mpc83xx/cpu_init.c b/arch/powerpc/cpu/mpc83xx/cpu_init.c index 7d8d5516b4..7c378671fe 100644 --- a/arch/powerpc/cpu/mpc83xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc83xx/cpu_init.c @@ -240,7 +240,7 @@ void cpu_init_f (volatile immap_t * im) /* System General Purpose Register */ #ifdef CONFIG_SYS_SICRH -#if defined(CONFIG_MPC834x) || defined(CONFIG_ARCH_MPC8313) +#if defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC8313) /* regarding to MPC34x manual rev.1 bits 28..29 must be preserved */ __raw_writel((im->sysconf.sicrh & 0x0000000C) | CONFIG_SYS_SICRH, &im->sysconf.sicrh); diff --git a/arch/powerpc/cpu/mpc83xx/spd_sdram.c b/arch/powerpc/cpu/mpc83xx/spd_sdram.c index 3f18aadf19..b3cbf9f882 100644 --- a/arch/powerpc/cpu/mpc83xx/spd_sdram.c +++ b/arch/powerpc/cpu/mpc83xx/spd_sdram.c @@ -426,7 +426,7 @@ long int spd_sdram() /* * Errata DDR6 work around: input enable 2 cycles earlier. - * including MPC834x Rev1.0/1.1 and MPC8360 Rev1.1/1.2. + * including MPC834X Rev1.0/1.1 and MPC8360 Rev1.1/1.2. */ if(PVR_MAJ(pvr) <= 1 && spd.mem_type == SPD_MEMTYPE_DDR){ if (caslat == 2) diff --git a/arch/powerpc/cpu/mpc83xx/speed.c b/arch/powerpc/cpu/mpc83xx/speed.c index ab025af70d..7cb6f3727d 100644 --- a/arch/powerpc/cpu/mpc83xx/speed.c +++ b/arch/powerpc/cpu/mpc83xx/speed.c @@ -86,14 +86,14 @@ int get_clocks(void) u32 csb_clk; #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ - defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) + defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_MPC837x) u32 tsec1_clk; u32 tsec2_clk; u32 usbdr_clk; #elif defined(CONFIG_ARCH_MPC8309) u32 usbdr_clk; #endif -#ifdef CONFIG_MPC834x +#ifdef CONFIG_ARCH_MPC834X u32 usbmph_clk; #endif u32 core_clk; @@ -156,7 +156,7 @@ int get_clocks(void) sccr = im->clk.sccr; #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ - defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) + defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_MPC837x) switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) { case 0: tsec1_clk = 0; @@ -177,7 +177,7 @@ int get_clocks(void) #endif #if defined(CONFIG_ARCH_MPC830X) || defined(CONFIG_ARCH_MPC831X) || \ - defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) + defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_MPC837x) switch ((sccr & SCCR_USBDRCM) >> SCCR_USBDRCM_SHIFT) { case 0: usbdr_clk = 0; @@ -198,7 +198,7 @@ int get_clocks(void) #endif #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC8315) || \ - defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) + defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_MPC837x) switch ((sccr & SCCR_TSEC2CM) >> SCCR_TSEC2CM_SHIFT) { case 0: tsec2_clk = 0; @@ -225,7 +225,7 @@ int get_clocks(void) tsec2_clk = 0; #endif -#if defined(CONFIG_MPC834x) +#if defined(CONFIG_ARCH_MPC834X) switch ((sccr & SCCR_USBMPHCM) >> SCCR_USBMPHCM_SHIFT) { case 0: usbmph_clk = 0; @@ -311,7 +311,7 @@ int get_clocks(void) } #endif -#if defined(CONFIG_MPC834x) +#if defined(CONFIG_ARCH_MPC834X) i2c1_clk = tsec2_clk; #elif defined(CONFIG_MPC8360) i2c1_clk = csb_clk; @@ -449,14 +449,14 @@ int get_clocks(void) gd->arch.csb_clk = csb_clk; #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ - defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) + defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_MPC837x) gd->arch.tsec1_clk = tsec1_clk; gd->arch.tsec2_clk = tsec2_clk; gd->arch.usbdr_clk = usbdr_clk; #elif defined(CONFIG_ARCH_MPC8309) gd->arch.usbdr_clk = usbdr_clk; #endif -#if defined(CONFIG_MPC834x) +#if defined(CONFIG_ARCH_MPC834X) gd->arch.usbmph_clk = usbmph_clk; #endif #if defined(CONFIG_ARCH_MPC8315) @@ -559,7 +559,7 @@ static int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) strmhz(buf, gd->arch.sdhc_clk)); #endif #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ - defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) + defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_MPC837x) printf(" TSEC1: %-4s MHz\n", strmhz(buf, gd->arch.tsec1_clk)); printf(" TSEC2: %-4s MHz\n", @@ -570,7 +570,7 @@ static int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf(" USB DR: %-4s MHz\n", strmhz(buf, gd->arch.usbdr_clk)); #endif -#if defined(CONFIG_MPC834x) +#if defined(CONFIG_ARCH_MPC834X) printf(" USB MPH: %-4s MHz\n", strmhz(buf, gd->arch.usbmph_clk)); #endif diff --git a/arch/powerpc/include/asm/arch-mpc83xx/gpio.h b/arch/powerpc/include/asm/arch-mpc83xx/gpio.h index 74ba91a469..16997316ff 100644 --- a/arch/powerpc/include/asm/arch-mpc83xx/gpio.h +++ b/arch/powerpc/include/asm/arch-mpc83xx/gpio.h @@ -9,7 +9,7 @@ #if defined(CONFIG_ARCH_MPC8313) || defined(CONFIG_ARCH_MPC8308) || \ defined(CONFIG_ARCH_MPC8315) #define MPC83XX_GPIO_CTRLRS 1 -#elif defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) +#elif defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_MPC837x) #define MPC83XX_GPIO_CTRLRS 2 #else #define MPC83XX_GPIO_CTRLRS 0 diff --git a/arch/powerpc/include/asm/fsl_lbc.h b/arch/powerpc/include/asm/fsl_lbc.h index cf89e186a6..0ea4456033 100644 --- a/arch/powerpc/include/asm/fsl_lbc.h +++ b/arch/powerpc/include/asm/fsl_lbc.h @@ -43,10 +43,10 @@ void lbc_sdram_init(void); #define BR_MSEL 0x000000E0 #define BR_MSEL_SHIFT 5 #define BR_MS_GPCM 0x00000000 /* GPCM */ -#if !defined(CONFIG_MPC834x) && !defined(CONFIG_MPC8360) +#if !defined(CONFIG_ARCH_MPC834X) && !defined(CONFIG_MPC8360) #define BR_MS_FCM 0x00000020 /* FCM */ #endif -#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC8360) +#if defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_MPC8360) #define BR_MS_SDRAM 0x00000060 /* SDRAM */ #elif defined(CONFIG_MPC85xx) #define BR_MS_SDRAM 0x00000000 /* SDRAM */ @@ -54,7 +54,7 @@ void lbc_sdram_init(void); #define BR_MS_UPMA 0x00000080 /* UPMA */ #define BR_MS_UPMB 0x000000A0 /* UPMB */ #define BR_MS_UPMC 0x000000C0 /* UPMC */ -#if !defined(CONFIG_MPC834x) +#if !defined(CONFIG_ARCH_MPC834X) #define BR_ATOM 0x0000000C #define BR_ATOM_SHIFT 2 #endif @@ -67,7 +67,7 @@ void lbc_sdram_init(void); #define UPMB 1 #define UPMC 2 -#if defined(CONFIG_MPC834x) +#if defined(CONFIG_ARCH_MPC834X) #define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_V) #else #define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_ATOM | BR_V) diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h index 0c3a4ade5c..cd0d76696d 100644 --- a/arch/powerpc/include/asm/global_data.h +++ b/arch/powerpc/include/asm/global_data.h @@ -36,16 +36,16 @@ struct arch_global_data { /* There are other clocks in the MPC83XX */ u32 csb_clk; # if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ - defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) + defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_MPC837x) u32 tsec1_clk; u32 tsec2_clk; u32 usbdr_clk; # elif defined(CONFIG_ARCH_MPC8309) u32 usbdr_clk; # endif -# if defined(CONFIG_MPC834x) +# if defined(CONFIG_ARCH_MPC834X) u32 usbmph_clk; -# endif /* CONFIG_MPC834x */ +# endif /* CONFIG_ARCH_MPC834X */ # if defined(CONFIG_ARCH_MPC8315) u32 tdm_clk; # endif diff --git a/arch/powerpc/include/asm/immap_83xx.h b/arch/powerpc/include/asm/immap_83xx.h index 318b79d0b8..bf7a4b9250 100644 --- a/arch/powerpc/include/asm/immap_83xx.h +++ b/arch/powerpc/include/asm/immap_83xx.h @@ -625,7 +625,7 @@ typedef struct tdmdmac83xx { u8 fixme[0x2000]; } tdmdmac83xx_t; -#if defined(CONFIG_MPC834x) +#if defined(CONFIG_ARCH_MPC834X) typedef struct immap { sysconf83xx_t sysconf; /* System configuration */ wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */ @@ -666,7 +666,7 @@ typedef struct immap { u8 res7[0xC0000]; } immap_t; -#ifndef CONFIG_MPC834x +#ifndef CONFIG_ARCH_MPC834X #ifdef CONFIG_HAS_FSL_MPH_USB #define CONFIG_SYS_MPC83xx_USB1_OFFSET 0x22000 /* use the MPH controller */ #define CONFIG_SYS_MPC83xx_USB2_OFFSET 0 @@ -946,7 +946,7 @@ typedef struct immap { #endif #define CONFIG_SYS_MPC83xx_USB1_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_USB1_OFFSET) -#if defined(CONFIG_MPC834x) +#if defined(CONFIG_ARCH_MPC834X) #define CONFIG_SYS_MPC83xx_USB2_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_USB2_OFFSET) #endif diff --git a/arch/powerpc/include/asm/mpc8xxx_spi.h b/arch/powerpc/include/asm/mpc8xxx_spi.h index 3edd561007..0c2bdb326b 100644 --- a/arch/powerpc/include/asm/mpc8xxx_spi.h +++ b/arch/powerpc/include/asm/mpc8xxx_spi.h @@ -13,7 +13,7 @@ #if defined(CONFIG_ARCH_MPC8308) || \ defined(CONFIG_ARCH_MPC8313) || \ defined(CONFIG_ARCH_MPC8315) || \ - defined(CONFIG_MPC834x) || \ + defined(CONFIG_ARCH_MPC834X) || \ defined(CONFIG_MPC837x) typedef struct spi8xxx { diff --git a/drivers/pci/pci_auto.c b/drivers/pci/pci_auto.c index d7237f6eee..a673d8ae13 100644 --- a/drivers/pci/pci_auto.c +++ b/drivers/pci/pci_auto.c @@ -359,7 +359,7 @@ int dm_pciauto_config_device(struct udevice *dev) PCI_DEV(dm_pci_get_bdf(dev))); break; #endif -#if defined(CONFIG_MPC834x) && !defined(CONFIG_VME8349) +#if defined(CONFIG_ARCH_MPC834X) && !defined(CONFIG_VME8349) case PCI_CLASS_BRIDGE_OTHER: /* * The host/PCI bridge 1 seems broken in 8349 - it presents diff --git a/drivers/pci/pci_auto_old.c b/drivers/pci/pci_auto_old.c index e705a3072e..90c22a08cb 100644 --- a/drivers/pci/pci_auto_old.c +++ b/drivers/pci/pci_auto_old.c @@ -376,7 +376,7 @@ int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev) PCI_DEV(dev)); break; #endif -#if defined(CONFIG_MPC834x) && !defined(CONFIG_VME8349) +#if defined(CONFIG_ARCH_MPC834X) && !defined(CONFIG_VME8349) case PCI_CLASS_BRIDGE_OTHER: /* * The host/PCI bridge 1 seems broken in 8349 - it presents diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index bda477cc16..93de2cc1c0 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -16,8 +16,6 @@ * High Level Configuration Options */ #define CONFIG_E300 1 /* E300 Family */ -#define CONFIG_MPC834x 1 /* MPC834x family */ -#define CONFIG_MPC8349 1 /* MPC8349 specific */ #define CONFIG_PCI_66M #ifdef CONFIG_PCI_66M diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index 111023b7be..496780d80c 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -46,9 +46,6 @@ /* * High Level Configuration Options */ -#define CONFIG_MPC834x /* MPC834x family (8343, 8347, 8349) */ -#define CONFIG_MPC8349 /* MPC8349 specific */ - #define CONFIG_SYS_IMMR 0xE0000000 /* The IMMR is relocated to here */ #define CONFIG_MISC_INIT_F diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index 0942b872ac..2b82bd82eb 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -15,8 +15,6 @@ * High Level Configuration Options */ #define CONFIG_E300 1 /* E300 Family */ -#define CONFIG_MPC834x 1 /* MPC834x specific */ -#define CONFIG_MPC8349 1 /* MPC8349 specific */ /* IMMR Base Address Register, use Freescale default: 0xff400000 */ #define CONFIG_SYS_IMMR 0xff400000 diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index 9074be80f1..6ae11185cb 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -18,8 +18,6 @@ * High Level Configuration Options */ #define CONFIG_E300 1 /* E300 Family */ -#define CONFIG_MPC834x 1 /* MPC834x family */ -#define CONFIG_MPC8349 1 /* MPC8349 specific */ /* Don't enable PCI2 on sbc834x - it doesn't exist physically. */ #undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */ diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h index 805f7d3df6..5695550130 100644 --- a/include/configs/vme8349.h +++ b/include/configs/vme8349.h @@ -28,8 +28,6 @@ * High Level Configuration Options */ #define CONFIG_E300 1 /* E300 Family */ -#define CONFIG_MPC834x 1 /* MPC834x family */ -#define CONFIG_MPC8349 1 /* MPC8349 specific */ #define CONFIG_VME8349 1 /* ESD VME8349 board specific */ /* Don't enable PCI2 on vme834x - it doesn't exist physically. */ diff --git a/include/mpc83xx.h b/include/mpc83xx.h index 0f4466ae89..feb8fef601 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -55,7 +55,7 @@ #define SPRIDR_PARTID 0xFFFF0000 /* Part Id */ #define SPRIDR_REVID 0x0000FFFF /* Revision Id */ -#if defined(CONFIG_MPC834x) +#if defined(CONFIG_ARCH_MPC834X) #define REVID_MAJOR(spridr) ((spridr & 0x0000FF00) >> 8) #define REVID_MINOR(spridr) (spridr & 0x000000FF) #else @@ -108,7 +108,7 @@ #define SPCR_COREPR 0x00300000 #define SPCR_COREPR_SHIFT (31-11) -#if defined(CONFIG_MPC834x) +#if defined(CONFIG_ARCH_MPC834X) /* SPCR bits - MPC8349 specific */ /* TSEC1 data priority */ #define SPCR_TSEC1DP 0x00003000 @@ -145,7 +145,7 @@ /* SICRL/H - System I/O Configuration Register Low/High */ -#if defined(CONFIG_MPC834x) +#if defined(CONFIG_ARCH_MPC834X) /* SICRL bits - MPC8349 specific */ #define SICRL_LDP_A 0x80000000 #define SICRL_USB1 0x40000000 @@ -720,7 +720,7 @@ #define HRCWH_PCI_HOST_SHIFT 31 #define HRCWH_PCI_AGENT 0x00000000 -#if defined(CONFIG_MPC834x) +#if defined(CONFIG_ARCH_MPC834X) #define HRCWH_32_BIT_PCI 0x00000000 #define HRCWH_64_BIT_PCI 0x40000000 #endif @@ -731,7 +731,7 @@ #define HRCWH_PCI_ARBITER_DISABLE 0x00000000 #define HRCWH_PCI_ARBITER_ENABLE 0x20000000 -#if defined(CONFIG_MPC834x) +#if defined(CONFIG_ARCH_MPC834X) #define HRCWH_PCI2_ARBITER_DISABLE 0x00000000 #define HRCWH_PCI2_ARBITER_ENABLE 0x10000000 @@ -755,7 +755,7 @@ #define HRCWH_ROM_LOC_DDR_SDRAM 0x00000000 #define HRCWH_ROM_LOC_PCI1 0x00100000 -#if defined(CONFIG_MPC834x) +#if defined(CONFIG_ARCH_MPC834X) #define HRCWH_ROM_LOC_PCI2 0x00200000 #endif #if defined(CONFIG_MPC837x) @@ -790,7 +790,7 @@ #define HRCWH_TSEC2M_IN_SGMII 0x00001800 #endif -#if defined(CONFIG_MPC834x) +#if defined(CONFIG_ARCH_MPC834X) #define HRCWH_TSEC1M_IN_RGMII 0x00000000 #define HRCWH_TSEC1M_IN_RTBI 0x00004000 #define HRCWH_TSEC1M_IN_GMII 0x00008000 @@ -937,8 +937,8 @@ #define SCCR_PCICM 0x00010000 #define SCCR_PCICM_SHIFT 16 -#if defined(CONFIG_MPC834x) -/* SCCR bits - MPC834x specific */ +#if defined(CONFIG_ARCH_MPC834X) +/* SCCR bits - MPC834X specific */ #define SCCR_TSEC1CM 0xc0000000 #define SCCR_TSEC1CM_SHIFT 30 #define SCCR_TSEC1CM_0 0x00000000 diff --git a/include/usb/ehci-ci.h b/include/usb/ehci-ci.h index e4579a5bec..efb2eec5ce 100644 --- a/include/usb/ehci-ci.h +++ b/include/usb/ehci-ci.h @@ -147,7 +147,7 @@ #if defined(CONFIG_MPC83xx) #define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_MPC83xx_USB1_ADDR -#if defined(CONFIG_MPC834x) +#if defined(CONFIG_ARCH_MPC834X) #define CONFIG_SYS_FSL_USB2_ADDR CONFIG_SYS_MPC83xx_USB2_ADDR #else #define CONFIG_SYS_FSL_USB2_ADDR 0 diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 481076e9d2..5cae6d81f2 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -1223,9 +1223,7 @@ CONFIG_MONITOR_IS_IN_RAM CONFIG_MPC8313ERDB CONFIG_MPC8315ERDB CONFIG_MPC832XEMDS -CONFIG_MPC8349 CONFIG_MPC8349ITX -CONFIG_MPC834x CONFIG_MPC8360 CONFIG_MPC837XEMDS CONFIG_MPC837XERDB From 61abced70fe5abf59b1a906d395b659ad918b8de Mon Sep 17 00:00:00 2001 From: Mario Six Date: Mon, 21 Jan 2019 09:17:28 +0100 Subject: [PATCH 05/86] mpc83xx: Introduce ARCH_MPC836* Replace CONFIG_MPC836* with proper CONFIG_ARCH_MPC836* Kconfig options. Signed-off-by: Mario Six --- arch/powerpc/cpu/mpc83xx/Kconfig | 4 ++++ arch/powerpc/cpu/mpc83xx/speed.c | 10 +++++----- arch/powerpc/include/asm/fsl_lbc.h | 4 ++-- arch/powerpc/include/asm/global_data.h | 4 ++-- arch/powerpc/include/asm/immap_83xx.h | 2 +- board/keymile/km83xx/km83xx.c | 4 ++-- drivers/ram/mpc83xx_sdram.c | 8 ++++---- include/configs/km8360.h | 1 - include/linux/immap_qe.h | 2 +- include/mpc83xx.h | 10 +++++----- include/post.h | 2 +- scripts/config_whitelist.txt | 1 - 12 files changed, 27 insertions(+), 25 deletions(-) diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index 6cca45e402..5f9d036e37 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -80,6 +80,7 @@ config TARGET_IDS8313 config TARGET_KM8360 bool "Support km8360" + select ARCH_MPC8360 imply CMD_CRAMFS imply CMD_DIAG imply FS_CRAMFS @@ -147,6 +148,9 @@ config ARCH_MPC8349 bool select ARCH_MPC834X +config ARCH_MPC8360 + bool + source "board/esd/vme8349/Kconfig" source "board/freescale/mpc8308rdb/Kconfig" source "board/freescale/mpc8313erdb/Kconfig" diff --git a/arch/powerpc/cpu/mpc83xx/speed.c b/arch/powerpc/cpu/mpc83xx/speed.c index 7cb6f3727d..ed77675a8e 100644 --- a/arch/powerpc/cpu/mpc83xx/speed.c +++ b/arch/powerpc/cpu/mpc83xx/speed.c @@ -113,7 +113,7 @@ int get_clocks(void) u32 lbiu_clk; u32 lclk_clk; u32 mem_clk; -#if defined(CONFIG_MPC8360) +#if defined(CONFIG_ARCH_MPC8360) u32 mem_sec_clk; #endif #if defined(CONFIG_QE) @@ -313,7 +313,7 @@ int get_clocks(void) #if defined(CONFIG_ARCH_MPC834X) i2c1_clk = tsec2_clk; -#elif defined(CONFIG_MPC8360) +#elif defined(CONFIG_ARCH_MPC8360) i2c1_clk = csb_clk; #elif defined(CONFIG_ARCH_MPC832X) i2c1_clk = enc_clk; @@ -407,7 +407,7 @@ int get_clocks(void) (1 + ((im->clk.spmr & SPMR_DDRCM) >> SPMR_DDRCM_SHIFT)); corepll = (im->clk.spmr & SPMR_COREPLL) >> SPMR_COREPLL_SHIFT; -#if defined(CONFIG_MPC8360) +#if defined(CONFIG_ARCH_MPC8360) mem_sec_clk = csb_clk * (1 + ((im->clk.spmr & SPMR_LBIUCM) >> SPMR_LBIUCM_SHIFT)); #endif @@ -476,7 +476,7 @@ int get_clocks(void) gd->arch.lbiu_clk = lbiu_clk; gd->arch.lclk_clk = lclk_clk; gd->mem_clk = mem_clk; -#if defined(CONFIG_MPC8360) +#if defined(CONFIG_ARCH_MPC8360) gd->arch.mem_sec_clk = mem_sec_clk; #endif #if defined(CONFIG_QE) @@ -536,7 +536,7 @@ static int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf(" Local Bus: %-4s MHz\n", strmhz(buf, gd->arch.lclk_clk)); printf(" DDR: %-4s MHz\n", strmhz(buf, gd->mem_clk)); -#if defined(CONFIG_MPC8360) +#if defined(CONFIG_ARCH_MPC8360) printf(" DDR Secondary: %-4s MHz\n", strmhz(buf, gd->arch.mem_sec_clk)); #endif diff --git a/arch/powerpc/include/asm/fsl_lbc.h b/arch/powerpc/include/asm/fsl_lbc.h index 0ea4456033..3528acd627 100644 --- a/arch/powerpc/include/asm/fsl_lbc.h +++ b/arch/powerpc/include/asm/fsl_lbc.h @@ -43,10 +43,10 @@ void lbc_sdram_init(void); #define BR_MSEL 0x000000E0 #define BR_MSEL_SHIFT 5 #define BR_MS_GPCM 0x00000000 /* GPCM */ -#if !defined(CONFIG_ARCH_MPC834X) && !defined(CONFIG_MPC8360) +#if !defined(CONFIG_ARCH_MPC834X) && !defined(CONFIG_ARCH_MPC8360) #define BR_MS_FCM 0x00000020 /* FCM */ #endif -#if defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_MPC8360) +#if defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC8360) #define BR_MS_SDRAM 0x00000060 /* SDRAM */ #elif defined(CONFIG_MPC85xx) #define BR_MS_SDRAM 0x00000000 /* SDRAM */ diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h index cd0d76696d..cf3ba58822 100644 --- a/arch/powerpc/include/asm/global_data.h +++ b/arch/powerpc/include/asm/global_data.h @@ -61,9 +61,9 @@ struct arch_global_data { # if defined(CONFIG_MPC837x) || defined(CONFIG_ARCH_MPC8315) u32 sata_clk; # endif -# if defined(CONFIG_MPC8360) +# if defined(CONFIG_ARCH_MPC8360) u32 mem_sec_clk; -# endif /* CONFIG_MPC8360 */ +# endif /* CONFIG_ARCH_MPC8360 */ #endif #endif #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) diff --git a/arch/powerpc/include/asm/immap_83xx.h b/arch/powerpc/include/asm/immap_83xx.h index bf7a4b9250..f6721e7b1d 100644 --- a/arch/powerpc/include/asm/immap_83xx.h +++ b/arch/powerpc/include/asm/immap_83xx.h @@ -803,7 +803,7 @@ typedef struct immap { rom83xx_t rom; /* On Chip ROM */ } immap_t; -#elif defined(CONFIG_MPC8360) +#elif defined(CONFIG_ARCH_MPC8360) typedef struct immap { sysconf83xx_t sysconf; /* System configuration */ wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */ diff --git a/board/keymile/km83xx/km83xx.c b/board/keymile/km83xx/km83xx.c index ce5126aae6..12044ee0d7 100644 --- a/board/keymile/km83xx/km83xx.c +++ b/board/keymile/km83xx/km83xx.c @@ -33,7 +33,7 @@ static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN]; const qe_iop_conf_t qe_iop_conf_tab[] = { /* port pin dir open_drain assign */ -#if defined(CONFIG_MPC8360) +#if defined(CONFIG_ARCH_MPC8360) /* MDIO */ {0, 1, 3, 0, 2}, /* MDIO */ {0, 2, 1, 0, 1}, /* MDC */ @@ -148,7 +148,7 @@ int board_early_init_r(void) u32 *mxmr = &lbc->mamr; #endif -#if defined(CONFIG_MPC8360) +#if defined(CONFIG_ARCH_MPC8360) unsigned short svid; /* * Because of errata in the UCCs, we have to write to the reserved diff --git a/drivers/ram/mpc83xx_sdram.c b/drivers/ram/mpc83xx_sdram.c index 58db7948c1..3e57b13118 100644 --- a/drivers/ram/mpc83xx_sdram.c +++ b/drivers/ram/mpc83xx_sdram.c @@ -169,7 +169,7 @@ static int mpc83xx_sdram_static_init(ofnode node, u32 cs, u32 mapaddr, u32 size) odt_rd_cfg = ofnode_read_u32_default(node, "odt_rd_cfg", 0); switch (odt_rd_cfg) { case ODT_RD_ONLY_OTHER_DIMM: - if (!IS_ENABLED(CONFIG_MPC8360) && + if (!IS_ENABLED(CONFIG_ARCH_MPC8360) && !IS_ENABLED(CONFIG_MPC837x)) { debug("%s: odt_rd_cfg value %d invalid.\n", ofnode_get_name(node), odt_rd_cfg); @@ -181,7 +181,7 @@ static int mpc83xx_sdram_static_init(ofnode node, u32 cs, u32 mapaddr, u32 size) case ODT_RD_ONLY_OTHER_CS: if (!IS_ENABLED(CONFIG_ARCH_MPC830X) && !IS_ENABLED(CONFIG_ARCH_MPC831X) && - !IS_ENABLED(CONFIG_MPC8360) && + !IS_ENABLED(CONFIG_ARCH_MPC8360) && !IS_ENABLED(CONFIG_MPC837x)) { debug("%s: odt_rd_cfg value %d invalid.\n", ofnode_get_name(node), odt_rd_cfg); @@ -200,7 +200,7 @@ static int mpc83xx_sdram_static_init(ofnode node, u32 cs, u32 mapaddr, u32 size) odt_wr_cfg = ofnode_read_u32_default(node, "odt_wr_cfg", 0); switch (odt_wr_cfg) { case ODT_WR_ONLY_OTHER_DIMM: - if (!IS_ENABLED(CONFIG_MPC8360) && + if (!IS_ENABLED(CONFIG_ARCH_MPC8360) && !IS_ENABLED(CONFIG_MPC837x)) { debug("%s: odt_wr_cfg value %d invalid.\n", ofnode_get_name(node), odt_wr_cfg); @@ -212,7 +212,7 @@ static int mpc83xx_sdram_static_init(ofnode node, u32 cs, u32 mapaddr, u32 size) case ODT_WR_ONLY_OTHER_CS: if (!IS_ENABLED(CONFIG_ARCH_MPC830X) && !IS_ENABLED(CONFIG_ARCH_MPC831X) && - !IS_ENABLED(CONFIG_MPC8360) && + !IS_ENABLED(CONFIG_ARCH_MPC8360) && !IS_ENABLED(CONFIG_MPC837x)) { debug("%s: odt_wr_cfg value %d invalid.\n", ofnode_get_name(node), odt_wr_cfg); diff --git a/include/configs/km8360.h b/include/configs/km8360.h index feb8a9a16d..7857b83055 100644 --- a/include/configs/km8360.h +++ b/include/configs/km8360.h @@ -36,7 +36,6 @@ * High Level Configuration Options */ #define CONFIG_QE /* Has QE */ -#define CONFIG_MPC8360 /* MPC8360 CPU specific */ /* include common defines/options for all 83xx Keymile boards */ #include "km/km83xx-common.h" diff --git a/include/linux/immap_qe.h b/include/linux/immap_qe.h index 6552d0e3c5..022771fff5 100644 --- a/include/linux/immap_qe.h +++ b/include/linux/immap_qe.h @@ -12,7 +12,7 @@ #define __IMMAP_QE_H__ #ifdef CONFIG_MPC83xx -#if defined(CONFIG_MPC8360) +#if defined(CONFIG_ARCH_MPC8360) #define QE_MURAM_SIZE 0xc000UL #define MAX_QE_RISC 2 #define QE_NUM_OF_SNUM 28 diff --git a/include/mpc83xx.h b/include/mpc83xx.h index feb8fef601..94b2816a82 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -191,7 +191,7 @@ #define SICRH_TSOBI1 0x00000002 #define SICRH_TSOBI2 0x00000001 -#elif defined(CONFIG_MPC8360) +#elif defined(CONFIG_ARCH_MPC8360) /* SICRL bits - MPC8360 specific */ #define SICRL_LDP_A 0xC0000000 #define SICRL_LCLK_1 0x10000000 @@ -593,7 +593,7 @@ #define HRCWL_CORE_TO_CSB_2_5X1 0x00050000 #define HRCWL_CORE_TO_CSB_3X1 0x00060000 -#if defined(CONFIG_MPC8360) || defined(CONFIG_ARCH_MPC832X) +#if defined(CONFIG_ARCH_MPC8360) || defined(CONFIG_ARCH_MPC832X) #define HRCWL_CEVCOD 0x000000C0 #define HRCWL_CEVCOD_SHIFT 6 #define HRCWL_CE_PLL_VCO_DIV_4 0x00000000 @@ -735,7 +735,7 @@ #define HRCWH_PCI2_ARBITER_DISABLE 0x00000000 #define HRCWH_PCI2_ARBITER_ENABLE 0x10000000 -#elif defined(CONFIG_MPC8360) +#elif defined(CONFIG_ARCH_MPC8360) #define HRCWH_PCICKDRV_DISABLE 0x00000000 #define HRCWH_PCICKDRV_ENABLE 0x10000000 #endif @@ -801,7 +801,7 @@ #define HRCWH_TSEC2M_IN_TBI 0x00003000 #endif -#if defined(CONFIG_MPC8360) +#if defined(CONFIG_ARCH_MPC8360) #define HRCWH_SECONDARY_DDR_DISABLE 0x00000000 #define HRCWH_SECONDARY_DDR_ENABLE 0x00000010 #endif @@ -1129,7 +1129,7 @@ #elif defined(CONFIG_ARCH_MPC832X) #define CSCONFIG_ODT_RD_CFG 0x00400000 #define CSCONFIG_ODT_WR_CFG 0x00040000 -#elif defined(CONFIG_MPC8360) || defined(CONFIG_MPC837x) +#elif defined(CONFIG_ARCH_MPC8360) || defined(CONFIG_MPC837x) #define CSCONFIG_ODT_RD_NEVER 0x00000000 #define CSCONFIG_ODT_RD_ONLY_CURRENT 0x00100000 #define CSCONFIG_ODT_RD_ONLY_OTHER_CS 0x00200000 diff --git a/include/post.h b/include/post.h index 08a771e405..eb218acde5 100644 --- a/include/post.h +++ b/include/post.h @@ -21,7 +21,7 @@ #define _POST_WORD_ADDR CONFIG_SYS_POST_WORD_ADDR #else -#if defined(CONFIG_MPC8360) +#if defined(CONFIG_ARCH_MPC8360) #include #define _POST_WORD_ADDR (CONFIG_SYS_IMMR + CPM_POST_WORD_ADDR) diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 5cae6d81f2..7b30903395 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -1224,7 +1224,6 @@ CONFIG_MPC8313ERDB CONFIG_MPC8315ERDB CONFIG_MPC832XEMDS CONFIG_MPC8349ITX -CONFIG_MPC8360 CONFIG_MPC837XEMDS CONFIG_MPC837XERDB CONFIG_MPC837x From 8439e99ddb54872f124b86f671d10d8a66cf9693 Mon Sep 17 00:00:00 2001 From: Mario Six Date: Mon, 21 Jan 2019 09:17:29 +0100 Subject: [PATCH 06/86] mpc83xx: Introduce ARCH_MPC837X Replace CONFIG_MPC837x with a proper CONFIG_ARCH_MPC837X Kconfig option. Signed-off-by: Mario Six --- arch/powerpc/cpu/mpc83xx/Kconfig | 5 ++++ arch/powerpc/cpu/mpc83xx/speed.c | 30 ++++++++++---------- arch/powerpc/include/asm/arch-mpc83xx/gpio.h | 2 +- arch/powerpc/include/asm/global_data.h | 6 ++-- arch/powerpc/include/asm/immap_83xx.h | 2 +- arch/powerpc/include/asm/mpc8xxx_spi.h | 2 +- drivers/ram/mpc83xx_sdram.c | 8 +++--- include/configs/MPC837XEMDS.h | 1 - include/configs/MPC837XERDB.h | 1 - include/mpc83xx.h | 24 ++++++++-------- scripts/config_whitelist.txt | 1 - 11 files changed, 42 insertions(+), 40 deletions(-) diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index 5f9d036e37..e41f4d1f9a 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -64,12 +64,14 @@ config TARGET_MPC8349ITX config TARGET_MPC837XEMDS bool "Support MPC837XEMDS" + select ARCH_MPC837X select BOARD_EARLY_INIT_F imply CMD_SATA imply FSL_SATA config TARGET_MPC837XERDB bool "Support MPC837XERDB" + select ARCH_MPC837X select BOARD_EARLY_INIT_F config TARGET_IDS8313 @@ -151,6 +153,9 @@ config ARCH_MPC8349 config ARCH_MPC8360 bool +config ARCH_MPC837X + bool + source "board/esd/vme8349/Kconfig" source "board/freescale/mpc8308rdb/Kconfig" source "board/freescale/mpc8313erdb/Kconfig" diff --git a/arch/powerpc/cpu/mpc83xx/speed.c b/arch/powerpc/cpu/mpc83xx/speed.c index ed77675a8e..668ed27862 100644 --- a/arch/powerpc/cpu/mpc83xx/speed.c +++ b/arch/powerpc/cpu/mpc83xx/speed.c @@ -86,7 +86,7 @@ int get_clocks(void) u32 csb_clk; #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ - defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_MPC837x) + defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X) u32 tsec1_clk; u32 tsec2_clk; u32 usbdr_clk; @@ -123,11 +123,11 @@ int get_clocks(void) u32 brg_clk; #endif #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ - defined(CONFIG_MPC837x) + defined(CONFIG_ARCH_MPC837X) u32 pciexp1_clk; u32 pciexp2_clk; #endif -#if defined(CONFIG_MPC837x) || defined(CONFIG_ARCH_MPC8315) +#if defined(CONFIG_ARCH_MPC837X) || defined(CONFIG_ARCH_MPC8315) u32 sata_clk; #endif @@ -156,7 +156,7 @@ int get_clocks(void) sccr = im->clk.sccr; #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ - defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_MPC837x) + defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X) switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) { case 0: tsec1_clk = 0; @@ -177,7 +177,7 @@ int get_clocks(void) #endif #if defined(CONFIG_ARCH_MPC830X) || defined(CONFIG_ARCH_MPC831X) || \ - defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_MPC837x) + defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X) switch ((sccr & SCCR_USBDRCM) >> SCCR_USBDRCM_SHIFT) { case 0: usbdr_clk = 0; @@ -198,7 +198,7 @@ int get_clocks(void) #endif #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC8315) || \ - defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_MPC837x) + defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X) switch ((sccr & SCCR_TSEC2CM) >> SCCR_TSEC2CM_SHIFT) { case 0: tsec2_clk = 0; @@ -321,7 +321,7 @@ int get_clocks(void) i2c1_clk = enc_clk; #elif defined(CONFIG_FSL_ESDHC) i2c1_clk = sdhc_clk; -#elif defined(CONFIG_MPC837x) +#elif defined(CONFIG_ARCH_MPC837X) i2c1_clk = enc_clk; #elif defined(CONFIG_ARCH_MPC8309) i2c1_clk = csb_clk; @@ -331,7 +331,7 @@ int get_clocks(void) #endif #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ - defined(CONFIG_MPC837x) + defined(CONFIG_ARCH_MPC837X) switch ((sccr & SCCR_PCIEXP1CM) >> SCCR_PCIEXP1CM_SHIFT) { case 0: pciexp1_clk = 0; @@ -369,7 +369,7 @@ int get_clocks(void) } #endif -#if defined(CONFIG_MPC837x) || defined(CONFIG_ARCH_MPC8315) +#if defined(CONFIG_ARCH_MPC837X) || defined(CONFIG_ARCH_MPC8315) switch ((sccr & SCCR_SATA1CM) >> SCCR_SATA1CM_SHIFT) { case 0: sata_clk = 0; @@ -449,7 +449,7 @@ int get_clocks(void) gd->arch.csb_clk = csb_clk; #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ - defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_MPC837x) + defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X) gd->arch.tsec1_clk = tsec1_clk; gd->arch.tsec2_clk = tsec2_clk; gd->arch.usbdr_clk = usbdr_clk; @@ -484,11 +484,11 @@ int get_clocks(void) gd->arch.brg_clk = brg_clk; #endif #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ - defined(CONFIG_MPC837x) + defined(CONFIG_ARCH_MPC837X) gd->arch.pciexp1_clk = pciexp1_clk; gd->arch.pciexp2_clk = pciexp2_clk; #endif -#if defined(CONFIG_MPC837x) || defined(CONFIG_ARCH_MPC8315) +#if defined(CONFIG_ARCH_MPC837X) || defined(CONFIG_ARCH_MPC8315) gd->arch.sata_clk = sata_clk; #endif gd->pci_clk = pci_sync_in; @@ -559,7 +559,7 @@ static int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) strmhz(buf, gd->arch.sdhc_clk)); #endif #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ - defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_MPC837x) + defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X) printf(" TSEC1: %-4s MHz\n", strmhz(buf, gd->arch.tsec1_clk)); printf(" TSEC2: %-4s MHz\n", @@ -575,13 +575,13 @@ static int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) strmhz(buf, gd->arch.usbmph_clk)); #endif #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ - defined(CONFIG_MPC837x) + defined(CONFIG_ARCH_MPC837X) printf(" PCIEXP1: %-4s MHz\n", strmhz(buf, gd->arch.pciexp1_clk)); printf(" PCIEXP2: %-4s MHz\n", strmhz(buf, gd->arch.pciexp2_clk)); #endif -#if defined(CONFIG_MPC837x) || defined(CONFIG_ARCH_MPC8315) +#if defined(CONFIG_ARCH_MPC837X) || defined(CONFIG_ARCH_MPC8315) printf(" SATA: %-4s MHz\n", strmhz(buf, gd->arch.sata_clk)); #endif diff --git a/arch/powerpc/include/asm/arch-mpc83xx/gpio.h b/arch/powerpc/include/asm/arch-mpc83xx/gpio.h index 16997316ff..b5ec50ba44 100644 --- a/arch/powerpc/include/asm/arch-mpc83xx/gpio.h +++ b/arch/powerpc/include/asm/arch-mpc83xx/gpio.h @@ -9,7 +9,7 @@ #if defined(CONFIG_ARCH_MPC8313) || defined(CONFIG_ARCH_MPC8308) || \ defined(CONFIG_ARCH_MPC8315) #define MPC83XX_GPIO_CTRLRS 1 -#elif defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_MPC837x) +#elif defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X) #define MPC83XX_GPIO_CTRLRS 2 #else #define MPC83XX_GPIO_CTRLRS 0 diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h index cf3ba58822..b6e4dd6c80 100644 --- a/arch/powerpc/include/asm/global_data.h +++ b/arch/powerpc/include/asm/global_data.h @@ -36,7 +36,7 @@ struct arch_global_data { /* There are other clocks in the MPC83XX */ u32 csb_clk; # if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ - defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_MPC837x) + defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X) u32 tsec1_clk; u32 tsec2_clk; u32 usbdr_clk; @@ -54,11 +54,11 @@ struct arch_global_data { u32 lbiu_clk; u32 lclk_clk; # if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ - defined(CONFIG_MPC837x) + defined(CONFIG_ARCH_MPC837X) u32 pciexp1_clk; u32 pciexp2_clk; # endif -# if defined(CONFIG_MPC837x) || defined(CONFIG_ARCH_MPC8315) +# if defined(CONFIG_ARCH_MPC837X) || defined(CONFIG_ARCH_MPC8315) u32 sata_clk; # endif # if defined(CONFIG_ARCH_MPC8360) diff --git a/arch/powerpc/include/asm/immap_83xx.h b/arch/powerpc/include/asm/immap_83xx.h index f6721e7b1d..30bbd5671b 100644 --- a/arch/powerpc/include/asm/immap_83xx.h +++ b/arch/powerpc/include/asm/immap_83xx.h @@ -759,7 +759,7 @@ typedef struct immap { u8 res12[0x1CF00]; } immap_t; -#elif defined(CONFIG_MPC837x) +#elif defined(CONFIG_ARCH_MPC837X) typedef struct immap { sysconf83xx_t sysconf; /* System configuration */ wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */ diff --git a/arch/powerpc/include/asm/mpc8xxx_spi.h b/arch/powerpc/include/asm/mpc8xxx_spi.h index 0c2bdb326b..b583a3269d 100644 --- a/arch/powerpc/include/asm/mpc8xxx_spi.h +++ b/arch/powerpc/include/asm/mpc8xxx_spi.h @@ -14,7 +14,7 @@ defined(CONFIG_ARCH_MPC8313) || \ defined(CONFIG_ARCH_MPC8315) || \ defined(CONFIG_ARCH_MPC834X) || \ - defined(CONFIG_MPC837x) + defined(CONFIG_ARCH_MPC837X) typedef struct spi8xxx { u8 res0[0x20]; /* 0x0-0x01f reserved */ diff --git a/drivers/ram/mpc83xx_sdram.c b/drivers/ram/mpc83xx_sdram.c index 3e57b13118..f03d0428b2 100644 --- a/drivers/ram/mpc83xx_sdram.c +++ b/drivers/ram/mpc83xx_sdram.c @@ -170,7 +170,7 @@ static int mpc83xx_sdram_static_init(ofnode node, u32 cs, u32 mapaddr, u32 size) switch (odt_rd_cfg) { case ODT_RD_ONLY_OTHER_DIMM: if (!IS_ENABLED(CONFIG_ARCH_MPC8360) && - !IS_ENABLED(CONFIG_MPC837x)) { + !IS_ENABLED(CONFIG_ARCH_MPC837X)) { debug("%s: odt_rd_cfg value %d invalid.\n", ofnode_get_name(node), odt_rd_cfg); return -EINVAL; @@ -182,7 +182,7 @@ static int mpc83xx_sdram_static_init(ofnode node, u32 cs, u32 mapaddr, u32 size) if (!IS_ENABLED(CONFIG_ARCH_MPC830X) && !IS_ENABLED(CONFIG_ARCH_MPC831X) && !IS_ENABLED(CONFIG_ARCH_MPC8360) && - !IS_ENABLED(CONFIG_MPC837x)) { + !IS_ENABLED(CONFIG_ARCH_MPC837X)) { debug("%s: odt_rd_cfg value %d invalid.\n", ofnode_get_name(node), odt_rd_cfg); return -EINVAL; @@ -201,7 +201,7 @@ static int mpc83xx_sdram_static_init(ofnode node, u32 cs, u32 mapaddr, u32 size) switch (odt_wr_cfg) { case ODT_WR_ONLY_OTHER_DIMM: if (!IS_ENABLED(CONFIG_ARCH_MPC8360) && - !IS_ENABLED(CONFIG_MPC837x)) { + !IS_ENABLED(CONFIG_ARCH_MPC837X)) { debug("%s: odt_wr_cfg value %d invalid.\n", ofnode_get_name(node), odt_wr_cfg); return -EINVAL; @@ -213,7 +213,7 @@ static int mpc83xx_sdram_static_init(ofnode node, u32 cs, u32 mapaddr, u32 size) if (!IS_ENABLED(CONFIG_ARCH_MPC830X) && !IS_ENABLED(CONFIG_ARCH_MPC831X) && !IS_ENABLED(CONFIG_ARCH_MPC8360) && - !IS_ENABLED(CONFIG_MPC837x)) { + !IS_ENABLED(CONFIG_ARCH_MPC837X)) { debug("%s: odt_wr_cfg value %d invalid.\n", ofnode_get_name(node), odt_wr_cfg); return -EINVAL; diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index 50f6df5844..82dcb85973 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -11,7 +11,6 @@ * High Level Configuration Options */ #define CONFIG_E300 1 /* E300 family */ -#define CONFIG_MPC837x 1 /* MPC837x CPU specific */ #define CONFIG_MPC837XEMDS 1 /* MPC837XEMDS board specific */ /* diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index 4ddd62ddbb..6029d0f21b 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -12,7 +12,6 @@ * High Level Configuration Options */ #define CONFIG_E300 1 /* E300 family */ -#define CONFIG_MPC837x 1 /* MPC837x CPU specific */ #define CONFIG_MPC837XERDB 1 #define CONFIG_HWCONFIG diff --git a/include/mpc83xx.h b/include/mpc83xx.h index 94b2816a82..c2a185321a 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -130,8 +130,8 @@ #define SPCR_TSEC2EP_SHIFT (31-31) #elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ - defined(CONFIG_MPC837x) -/* SPCR bits - MPC8308, MPC831x and MPC837x specific */ + defined(CONFIG_ARCH_MPC837X) +/* SPCR bits - MPC8308, MPC831x and MPC837X specific */ /* TSEC data priority */ #define SPCR_TSECDP 0x00003000 #define SPCR_TSECDP_SHIFT (31-19) @@ -283,8 +283,8 @@ #define SICRH_TSOBI1 0x00000002 #define SICRH_TSOBI2 0x00000001 -#elif defined(CONFIG_MPC837x) -/* SICRL bits - MPC837x specific */ +#elif defined(CONFIG_ARCH_MPC837X) +/* SICRL bits - MPC837X specific */ #define SICRL_USB_A 0xC0000000 #define SICRL_USB_B 0x30000000 #define SICRL_USB_B_SD 0x20000000 @@ -314,7 +314,7 @@ #define SICRL_LDP_A 0x00000002 #define SICRL_LDP_B 0x00000001 -/* SICRH bits - MPC837x specific */ +/* SICRH bits - MPC837X specific */ #define SICRH_DDR 0x80000000 #define SICRH_TSEC1_A 0x10000000 #define SICRH_TSEC1_B 0x08000000 @@ -647,7 +647,7 @@ #define HRCWL_SVCOD_DIV_8 0x20000000 #define HRCWL_SVCOD_DIV_1 0x30000000 -#elif defined(CONFIG_MPC837x) +#elif defined(CONFIG_ARCH_MPC837X) #define HRCWL_SVCOD 0x30000000 #define HRCWL_SVCOD_SHIFT 28 #define HRCWL_SVCOD_DIV_4 0x00000000 @@ -758,7 +758,7 @@ #if defined(CONFIG_ARCH_MPC834X) #define HRCWH_ROM_LOC_PCI2 0x00200000 #endif -#if defined(CONFIG_MPC837x) +#if defined(CONFIG_ARCH_MPC837X) #define HRCWH_ROM_LOC_ON_CHIP_ROM 0x00300000 #endif #define HRCWH_ROM_LOC_LOCAL_8BIT 0x00500000 @@ -766,7 +766,7 @@ #define HRCWH_ROM_LOC_LOCAL_32BIT 0x00700000 #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ - defined(CONFIG_MPC837x) + defined(CONFIG_ARCH_MPC837X) #define HRCWH_ROM_LOC_NAND_SP_8BIT 0x00100000 #define HRCWH_ROM_LOC_NAND_SP_16BIT 0x00200000 #define HRCWH_ROM_LOC_NAND_LP_8BIT 0x00500000 @@ -819,7 +819,7 @@ * RSR - Reset Status Register */ #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ - defined(CONFIG_MPC837x) + defined(CONFIG_ARCH_MPC837X) #define RSR_RSTSRC 0xF0000000 /* Reset source */ #define RSR_RSTSRC_SHIFT 28 #else @@ -1032,8 +1032,8 @@ #define SCCR_TDMCM_2 0x00000020 #define SCCR_TDMCM_3 0x00000030 -#elif defined(CONFIG_MPC837x) -/* SCCR bits - MPC837x specific */ +#elif defined(CONFIG_ARCH_MPC837X) +/* SCCR bits - MPC837X specific */ #define SCCR_TSEC1CM 0xc0000000 #define SCCR_TSEC1CM_SHIFT 30 #define SCCR_TSEC1CM_0 0x00000000 @@ -1129,7 +1129,7 @@ #elif defined(CONFIG_ARCH_MPC832X) #define CSCONFIG_ODT_RD_CFG 0x00400000 #define CSCONFIG_ODT_WR_CFG 0x00040000 -#elif defined(CONFIG_ARCH_MPC8360) || defined(CONFIG_MPC837x) +#elif defined(CONFIG_ARCH_MPC8360) || defined(CONFIG_ARCH_MPC837X) #define CSCONFIG_ODT_RD_NEVER 0x00000000 #define CSCONFIG_ODT_RD_ONLY_CURRENT 0x00100000 #define CSCONFIG_ODT_RD_ONLY_OTHER_CS 0x00200000 diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 7b30903395..761cdf6748 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -1226,7 +1226,6 @@ CONFIG_MPC832XEMDS CONFIG_MPC8349ITX CONFIG_MPC837XEMDS CONFIG_MPC837XERDB -CONFIG_MPC837x CONFIG_MPC83XX_GPIO CONFIG_MPC83XX_GPIO_0_INIT_DIRECTION CONFIG_MPC83XX_GPIO_0_INIT_OPEN_DRAIN From 0e0674fcab819e829929716aa5aa0f10d7feb75a Mon Sep 17 00:00:00 2001 From: Mario Six Date: Mon, 21 Jan 2019 09:17:30 +0100 Subject: [PATCH 07/86] keymile: Make distinct kmtegr1, kmvect1, suvd3 configs The kmtegr1, kmvect1, and suvd3 boards all use the same config include file with lots of #ifdefs in it. The Kconfig migation will become easier if we get rid of these #ifdefs first. Hence, create distinct config include files for these boards, and unwind the #ifdef logic in these config files to only include the options necessary for each board. Signed-off-by: Mario Six --- arch/powerpc/cpu/mpc83xx/Kconfig | 16 +++- board/keymile/km83xx/Kconfig | 26 ++++++ configs/kmtegr1_defconfig | 2 +- configs/kmvect1_defconfig | 2 +- include/configs/kmtegr1.h | 100 +++++++++++++++++++++++ include/configs/kmvect1.h | 133 +++++++++++++++++++++++++++++++ include/configs/suvd3.h | 94 ---------------------- 7 files changed, 274 insertions(+), 99 deletions(-) create mode 100644 include/configs/kmtegr1.h create mode 100644 include/configs/kmvect1.h diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index e41f4d1f9a..59e0c9a8d0 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -89,9 +89,19 @@ config TARGET_KM8360 config TARGET_SUVD3 bool "Support suvd3" - select ARCH_MPC8309 if SYS_EXTRA_OPTIONS="KMTEGR1" - select ARCH_MPC8309 if SYS_EXTRA_OPTIONS="KMVECT1" - select ARCH_MPC832X if SYS_EXTRA_OPTIONS="SUVD3" + select ARCH_MPC832X + imply CMD_CRAMFS + imply FS_CRAMFS + +config TARGET_KMVECT1 + bool "Support kmvect1" + select ARCH_MPC8309 + imply CMD_CRAMFS + imply FS_CRAMFS + +config TARGET_KMTEGR1 + bool "Support kmtegr1" + select ARCH_MPC8309 imply CMD_CRAMFS imply FS_CRAMFS diff --git a/board/keymile/km83xx/Kconfig b/board/keymile/km83xx/Kconfig index d6c594c96a..d52ee9117b 100644 --- a/board/keymile/km83xx/Kconfig +++ b/board/keymile/km83xx/Kconfig @@ -11,6 +11,32 @@ config SYS_CONFIG_NAME endif +if TARGET_KMVECT1 + +config SYS_BOARD + default "km83xx" + +config SYS_VENDOR + default "keymile" + +config SYS_CONFIG_NAME + default "kmvect1" + +endif + +if TARGET_KMTEGR1 + +config SYS_BOARD + default "km83xx" + +config SYS_VENDOR + default "keymile" + +config SYS_CONFIG_NAME + default "kmtegr1" + +endif + if TARGET_SUVD3 config SYS_BOARD diff --git a/configs/kmtegr1_defconfig b/configs/kmtegr1_defconfig index 40181758e9..38a861b861 100644 --- a/configs/kmtegr1_defconfig +++ b/configs/kmtegr1_defconfig @@ -1,7 +1,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xF0000000 CONFIG_MPC83xx=y -CONFIG_TARGET_SUVD3=y +CONFIG_TARGET_KMTEGR1=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="KMTEGR1" diff --git a/configs/kmvect1_defconfig b/configs/kmvect1_defconfig index 74b688fb5f..2f71ee7519 100644 --- a/configs/kmvect1_defconfig +++ b/configs/kmvect1_defconfig @@ -1,7 +1,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xF0000000 CONFIG_MPC83xx=y -CONFIG_TARGET_SUVD3=y +CONFIG_TARGET_KMVECT1=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="KMVECT1" diff --git a/include/configs/kmtegr1.h b/include/configs/kmtegr1.h new file mode 100644 index 0000000000..69397ae5ae --- /dev/null +++ b/include/configs/kmtegr1.h @@ -0,0 +1,100 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2006 Freescale Semiconductor, Inc. + * Dave Liu + * + * Copyright (C) 2007 Logic Product Development, Inc. + * Peter Barada + * + * Copyright (C) 2007 MontaVista Software, Inc. + * Anton Vorontsov + * + * (C) Copyright 2010 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ + +/* This needs to be set prior to including km/km83xx-common.h */ + +#define CONFIG_HOSTNAME "kmtegr1" +#define CONFIG_KM_BOARD_NAME "kmtegr1" +#define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0" +#define CONFIG_KM_UBI_PARTITION_NAME_APP "ubi1" + +#define CONFIG_ENV_ADDR 0xF0100000 +#define CONFIG_ENV_OFFSET 0x100000 + +#define CONFIG_NAND_ECC_BCH +#define CONFIG_NAND_KMETER1 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define NAND_MAX_CHIPS 1 + +/* include common defines/options for all 8309 Keymile boards */ +#include "km/km8309-common.h" +/* must be after the include because KMBEC_FPGA is otherwise undefined */ +#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */ + +#define CONFIG_SYS_APP1_BASE 0xA0000000 +#define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ +#define CONFIG_SYS_APP2_BASE 0xB0000000 +#define CONFIG_SYS_APP2_SIZE 256 /* Megabytes */ + +/* EEprom support */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 + +/* + * Init Local Bus Memory Controller: + * + * Bank Bus Machine PortSz Size Device + * ---- --- ------- ------ ----- ------ + * 2 Local UPMA 16 bit 256MB APP1 + * 3 Local GPCM 16 bit 256MB APP2 + * + */ + +#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_APP2_BASE | \ + BR_PS_16 | \ + BR_MS_GPCM | \ + BR_V) + +#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \ + OR_GPCM_SCY_5 | \ + OR_GPCM_TRLX_CLEAR | \ + OR_GPCM_EHTR_CLEAR) + +#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_APP2_BASE +#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) + +/* + * MMU Setup + */ +#define CONFIG_SYS_IBAT5L (0) +#define CONFIG_SYS_IBAT5U (0) +#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L +#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U +#define CONFIG_SYS_IBAT6L (CONFIG_SYS_APP2_BASE | BATL_PP_RW | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT6U (CONFIG_SYS_APP2_BASE | BATU_BL_256M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT6L (CONFIG_SYS_APP2_BASE | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U + +/* ethernet port connected to piggy (UEC2) */ +#define CONFIG_HAS_ETH1 +#define CONFIG_UEC_ETH2 +#define CONFIG_SYS_UEC2_UCC_NUM 2 /* UCC3 */ +#define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ +#define CONFIG_SYS_UEC2_TX_CLK QE_CLK12 +#define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH +#define CONFIG_SYS_UEC2_PHY_ADDR 0 +#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII +#define CONFIG_SYS_UEC2_INTERFACE_SPEED 100 + +#endif /* __CONFIG_H */ diff --git a/include/configs/kmvect1.h b/include/configs/kmvect1.h new file mode 100644 index 0000000000..178e769976 --- /dev/null +++ b/include/configs/kmvect1.h @@ -0,0 +1,133 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2006 Freescale Semiconductor, Inc. + * Dave Liu + * + * Copyright (C) 2007 Logic Product Development, Inc. + * Peter Barada + * + * Copyright (C) 2007 MontaVista Software, Inc. + * Anton Vorontsov + * + * (C) Copyright 2010 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ + +/* This needs to be set prior to including km/km83xx-common.h */ + +#define CONFIG_HOSTNAME "kmvect1" +#define CONFIG_KM_BOARD_NAME "kmvect1" +/* at end of uboot partition, before env */ +#define CONFIG_SYS_QE_FW_ADDR 0xF00B0000 +/* include common defines/options for all 8309 Keymile boards */ +#include "km/km8309-common.h" + +#define CONFIG_SYS_APP1_BASE 0xA0000000 +#define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ +#define CONFIG_SYS_APP2_BASE 0xB0000000 +#define CONFIG_SYS_APP2_SIZE 256 /* Megabytes */ + +/* EEprom support */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 + +/* + * Init Local Bus Memory Controller: + * + * Bank Bus Machine PortSz Size Device + * ---- --- ------- ------ ----- ------ + * 2 Local UPMA 16 bit 256MB APP1 + * 3 Local GPCM 16 bit 256MB APP2 + * + */ + +/* + * APP1 on the local bus CS2 + */ +#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_APP1_BASE +#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) + +#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_APP1_BASE | \ + BR_PS_16 | \ + BR_MS_UPMA | \ + BR_V) +#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_APP1_SIZE)) + +#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_APP2_BASE | \ + BR_PS_16 | \ + BR_V) + +#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \ + OR_GPCM_CSNT | \ + OR_GPCM_ACS_DIV4 | \ + OR_GPCM_SCY_3 | \ + OR_GPCM_TRLX_SET) + +#define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \ + 0x0000c000 | \ + MxMR_WLFx_2X) + +#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_APP2_BASE +#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) + +/* + * MMU Setup + */ +/* APP1: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT5L (CONFIG_SYS_APP1_BASE | BATL_PP_RW | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT5U (CONFIG_SYS_APP1_BASE | BATU_BL_256M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT5L (CONFIG_SYS_APP1_BASE | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U +#define CONFIG_SYS_IBAT6L (CONFIG_SYS_APP2_BASE | BATL_PP_RW | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT6U (CONFIG_SYS_APP2_BASE | BATU_BL_256M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT6L (CONFIG_SYS_APP2_BASE | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U + +/* + * QE UEC ethernet configuration + */ +#define CONFIG_MV88E6352_SWITCH +#define CONFIG_KM_MVEXTSW_ADDR 0x10 + +/* ethernet port connected to simple switch 88e6122 (UEC0) */ +#define CONFIG_UEC_ETH1 +#define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ +#define CONFIG_SYS_UEC1_RX_CLK QE_CLK9 +#define CONFIG_SYS_UEC1_TX_CLK QE_CLK10 + +#define CONFIG_FIXED_PHY 0xFFFFFFFF +#define CONFIG_SYS_FIXED_PHY_ADDR 0x1E /* unused address */ +#define CONFIG_SYS_FIXED_PHY_PORT(devnum, speed, duplex) \ + {devnum, speed, duplex} +#define CONFIG_SYS_FIXED_PHY_PORTS \ + CONFIG_SYS_FIXED_PHY_PORT("UEC0", SPEED_100, DUPLEX_FULL) + +#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH +#define CONFIG_SYS_UEC1_PHY_ADDR CONFIG_SYS_FIXED_PHY_ADDR +#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII +#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 + +/* ethernet port connected to piggy (UEC2) */ +#define CONFIG_HAS_ETH1 +#define CONFIG_UEC_ETH2 +#define CONFIG_SYS_UEC2_UCC_NUM 2 /* UCC3 */ +#define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ +#define CONFIG_SYS_UEC2_TX_CLK QE_CLK12 +#define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH +#define CONFIG_SYS_UEC2_PHY_ADDR 0 +#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII +#define CONFIG_SYS_UEC2_INTERFACE_SPEED 100 + +#endif /* __CONFIG_H */ diff --git a/include/configs/suvd3.h b/include/configs/suvd3.h index 3e88c9000c..2a3f7ff526 100644 --- a/include/configs/suvd3.h +++ b/include/configs/suvd3.h @@ -22,43 +22,11 @@ /* This needs to be set prior to including km/km83xx-common.h */ -#if defined(CONFIG_SUVD3) /* SUVD3 board specific */ #define CONFIG_HOSTNAME "suvd3" #define CONFIG_KM_BOARD_NAME "suvd3" /* include common defines/options for all 8321 Keymile boards */ #include "km/km8321-common.h" -#elif defined(CONFIG_KMVECT1) /* VECT1 board specific */ -#define CONFIG_HOSTNAME "kmvect1" -#define CONFIG_KM_BOARD_NAME "kmvect1" -/* at end of uboot partition, before env */ -#define CONFIG_SYS_QE_FW_ADDR 0xF00B0000 -/* include common defines/options for all 8309 Keymile boards */ -#include "km/km8309-common.h" - -#elif defined(CONFIG_KMTEGR1) /* TEGR1 board specific */ -#define CONFIG_HOSTNAME "kmtegr1" -#define CONFIG_KM_BOARD_NAME "kmtegr1" -#define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0" -#define CONFIG_KM_UBI_PARTITION_NAME_APP "ubi1" - -#define CONFIG_ENV_ADDR 0xF0100000 -#define CONFIG_ENV_OFFSET 0x100000 - -#define CONFIG_NAND_ECC_BCH -#define CONFIG_NAND_KMETER1 -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define NAND_MAX_CHIPS 1 - -/* include common defines/options for all 8309 Keymile boards */ -#include "km/km8309-common.h" -/* must be after the include because KMBEC_FPGA is otherwise undefined */ -#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */ - -#else -#error Supported boards are: SUVD3, KMVECT1, KMTEGR1 -#endif - #define CONFIG_SYS_APP1_BASE 0xA0000000 #define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ #define CONFIG_SYS_APP2_BASE 0xB0000000 @@ -77,7 +45,6 @@ * */ -#if defined(CONFIG_SUVD3) || defined(CONFIG_KMVECT1) /* * APP1 on the local bus CS2 */ @@ -104,26 +71,12 @@ 0x0000c000 | \ MxMR_WLFx_2X) -#elif defined(CONFIG_KMTEGR1) -#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_APP2_BASE | \ - BR_PS_16 | \ - BR_MS_GPCM | \ - BR_V) - -#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \ - OR_GPCM_SCY_5 | \ - OR_GPCM_TRLX_CLEAR | \ - OR_GPCM_EHTR_CLEAR) - -#endif /* CONFIG_KMTEGR1 */ - #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_APP2_BASE #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) /* * MMU Setup */ -#if defined(CONFIG_SUVD3) || defined(CONFIG_KMVECT1) /* APP1: icache cacheable, but dcache-inhibit and guarded */ #define CONFIG_SYS_IBAT5L (CONFIG_SYS_APP1_BASE | BATL_PP_RW | \ BATL_MEMCOHERENCE) @@ -132,14 +85,6 @@ #define CONFIG_SYS_DBAT5L (CONFIG_SYS_APP1_BASE | BATL_PP_RW | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U - -#elif defined(CONFIG_KMTEGR1) -#define CONFIG_SYS_IBAT5L (0) -#define CONFIG_SYS_IBAT5U (0) -#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L -#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U -#endif /* CONFIG_KMTEGR1 */ - #define CONFIG_SYS_IBAT6L (CONFIG_SYS_APP2_BASE | BATL_PP_RW | \ BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT6U (CONFIG_SYS_APP2_BASE | BATU_BL_256M | \ @@ -148,43 +93,4 @@ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U -/* - * QE UEC ethernet configuration - */ -#if defined(CONFIG_KMVECT1) -#define CONFIG_MV88E6352_SWITCH -#define CONFIG_KM_MVEXTSW_ADDR 0x10 - -/* ethernet port connected to simple switch 88e6122 (UEC0) */ -#define CONFIG_UEC_ETH1 -#define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ -#define CONFIG_SYS_UEC1_RX_CLK QE_CLK9 -#define CONFIG_SYS_UEC1_TX_CLK QE_CLK10 - -#define CONFIG_FIXED_PHY 0xFFFFFFFF -#define CONFIG_SYS_FIXED_PHY_ADDR 0x1E /* unused address */ -#define CONFIG_SYS_FIXED_PHY_PORT(devnum, speed, duplex) \ - {devnum, speed, duplex} -#define CONFIG_SYS_FIXED_PHY_PORTS \ - CONFIG_SYS_FIXED_PHY_PORT("UEC0", SPEED_100, DUPLEX_FULL) - -#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH -#define CONFIG_SYS_UEC1_PHY_ADDR CONFIG_SYS_FIXED_PHY_ADDR -#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII -#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 -#endif /* CONFIG_KMVECT1 */ - -#if defined(CONFIG_KMVECT1) || defined(CONFIG_KMTEGR1) -/* ethernet port connected to piggy (UEC2) */ -#define CONFIG_HAS_ETH1 -#define CONFIG_UEC_ETH2 -#define CONFIG_SYS_UEC2_UCC_NUM 2 /* UCC3 */ -#define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ -#define CONFIG_SYS_UEC2_TX_CLK QE_CLK12 -#define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH -#define CONFIG_SYS_UEC2_PHY_ADDR 0 -#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII -#define CONFIG_SYS_UEC2_INTERFACE_SPEED 100 -#endif /* CONFIG_KMVECT1 || CONFIG_KMTEGR1 */ - #endif /* __CONFIG_H */ From 0921ea2b00bb15ee630a23ee9ad52b78695bf161 Mon Sep 17 00:00:00 2001 From: Mario Six Date: Mon, 21 Jan 2019 09:17:31 +0100 Subject: [PATCH 08/86] keymile: Move config files We want to unroll several include files, while keeping include statements consistent. To make it easier to not break the include statements, move the include files to the main configs directory. All three include files moved will be unrolled, so they won't pollute the directory for long. Signed-off-by: Mario Six --- include/configs/{km => }/km8309-common.h | 0 include/configs/{km => }/km8321-common.h | 0 include/configs/km8360.h | 2 +- include/configs/{km => }/km83xx-common.h | 4 ++-- include/configs/kmtegr1.h | 4 ++-- include/configs/kmvect1.h | 4 ++-- include/configs/suvd3.h | 4 ++-- include/configs/tuxx1.h | 2 +- 8 files changed, 10 insertions(+), 10 deletions(-) rename include/configs/{km => }/km8309-common.h (100%) rename include/configs/{km => }/km8321-common.h (100%) rename include/configs/{km => }/km83xx-common.h (99%) diff --git a/include/configs/km/km8309-common.h b/include/configs/km8309-common.h similarity index 100% rename from include/configs/km/km8309-common.h rename to include/configs/km8309-common.h diff --git a/include/configs/km/km8321-common.h b/include/configs/km8321-common.h similarity index 100% rename from include/configs/km/km8321-common.h rename to include/configs/km8321-common.h diff --git a/include/configs/km8360.h b/include/configs/km8360.h index 7857b83055..08d2ae0cbc 100644 --- a/include/configs/km8360.h +++ b/include/configs/km8360.h @@ -38,7 +38,7 @@ #define CONFIG_QE /* Has QE */ /* include common defines/options for all 83xx Keymile boards */ -#include "km/km83xx-common.h" +#include "km83xx-common.h" /* * System IO Setup diff --git a/include/configs/km/km83xx-common.h b/include/configs/km83xx-common.h similarity index 99% rename from include/configs/km/km83xx-common.h rename to include/configs/km83xx-common.h index fb2a1cb39a..c80169c9b6 100644 --- a/include/configs/km/km83xx-common.h +++ b/include/configs/km83xx-common.h @@ -8,8 +8,8 @@ #define __CONFIG_KM83XX_H /* include common defines/options for all Keymile boards */ -#include "keymile-common.h" -#include "km-powerpc.h" +#include "km/keymile-common.h" +#include "km/km-powerpc.h" /* * System Clock Setup diff --git a/include/configs/kmtegr1.h b/include/configs/kmtegr1.h index 69397ae5ae..95a131892d 100644 --- a/include/configs/kmtegr1.h +++ b/include/configs/kmtegr1.h @@ -20,7 +20,7 @@ * High Level Configuration Options */ -/* This needs to be set prior to including km/km83xx-common.h */ +/* This needs to be set prior to including km83xx-common.h */ #define CONFIG_HOSTNAME "kmtegr1" #define CONFIG_KM_BOARD_NAME "kmtegr1" @@ -36,7 +36,7 @@ #define NAND_MAX_CHIPS 1 /* include common defines/options for all 8309 Keymile boards */ -#include "km/km8309-common.h" +#include "km8309-common.h" /* must be after the include because KMBEC_FPGA is otherwise undefined */ #define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */ diff --git a/include/configs/kmvect1.h b/include/configs/kmvect1.h index 178e769976..0bbf541aec 100644 --- a/include/configs/kmvect1.h +++ b/include/configs/kmvect1.h @@ -20,14 +20,14 @@ * High Level Configuration Options */ -/* This needs to be set prior to including km/km83xx-common.h */ +/* This needs to be set prior to including km83xx-common.h */ #define CONFIG_HOSTNAME "kmvect1" #define CONFIG_KM_BOARD_NAME "kmvect1" /* at end of uboot partition, before env */ #define CONFIG_SYS_QE_FW_ADDR 0xF00B0000 /* include common defines/options for all 8309 Keymile boards */ -#include "km/km8309-common.h" +#include "km8309-common.h" #define CONFIG_SYS_APP1_BASE 0xA0000000 #define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ diff --git a/include/configs/suvd3.h b/include/configs/suvd3.h index 2a3f7ff526..98137392ed 100644 --- a/include/configs/suvd3.h +++ b/include/configs/suvd3.h @@ -20,12 +20,12 @@ * High Level Configuration Options */ -/* This needs to be set prior to including km/km83xx-common.h */ +/* This needs to be set prior to including km83xx-common.h */ #define CONFIG_HOSTNAME "suvd3" #define CONFIG_KM_BOARD_NAME "suvd3" /* include common defines/options for all 8321 Keymile boards */ -#include "km/km8321-common.h" +#include "km8321-common.h" #define CONFIG_SYS_APP1_BASE 0xA0000000 #define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ diff --git a/include/configs/tuxx1.h b/include/configs/tuxx1.h index f22d73b8d3..0b17084b05 100644 --- a/include/configs/tuxx1.h +++ b/include/configs/tuxx1.h @@ -43,7 +43,7 @@ #endif /* include common defines/options for all 8321 Keymile boards */ -#include "km/km8321-common.h" +#include "km8321-common.h" #define CONFIG_SYS_APP1_BASE 0xA0000000 /* PAXG */ #define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ From 0e890d4c2b4e850ba0cba7fadfaba2305f76eb99 Mon Sep 17 00:00:00 2001 From: Mario Six Date: Mon, 21 Jan 2019 09:17:32 +0100 Subject: [PATCH 09/86] keymile: Unroll includes To further simplify config include files, unroll the km/km8309-common.h and km/km8321-common.h include files. Signed-off-by: Mario Six --- include/configs/km8309-common.h | 174 -------------------------------- include/configs/km8321-common.h | 139 ------------------------- include/configs/kmtegr1.h | 164 +++++++++++++++++++++++++++++- include/configs/kmvect1.h | 164 +++++++++++++++++++++++++++++- include/configs/suvd3.h | 116 ++++++++++++++++++++- include/configs/tuxx1.h | 115 ++++++++++++++++++++- 6 files changed, 551 insertions(+), 321 deletions(-) delete mode 100644 include/configs/km8309-common.h delete mode 100644 include/configs/km8321-common.h diff --git a/include/configs/km8309-common.h b/include/configs/km8309-common.h deleted file mode 100644 index 3bd334c515..0000000000 --- a/include/configs/km8309-common.h +++ /dev/null @@ -1,174 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2012 Keymile AG - * Gerlando Falauto - * - * Based on km8321-common.h, see respective copyright notice for credits - */ - -#ifndef __CONFIG_KM8309_COMMON_H -#define __CONFIG_KM8309_COMMON_H - -/* - * High Level Configuration Options - */ -#define CONFIG_E300 1 /* E300 family */ -#define CONFIG_QE 1 /* Has QE */ - -#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" - -/* include common defines/options for all 83xx Keymile boards */ -#include "km83xx-common.h" - -/* QE microcode/firmware address */ -#define CONFIG_SYS_QE_FMAN_FW_IN_NOR -/* between the u-boot partition and env */ -#ifndef CONFIG_SYS_QE_FW_ADDR -#define CONFIG_SYS_QE_FW_ADDR 0xF00C0000 -#endif - -/* - * System IO Config - */ -/* 0x14000180 SICR_1 */ -#define CONFIG_SYS_SICRL (0 \ - | SICR_1_UART1_UART1RTS \ - | SICR_1_I2C_CKSTOP \ - | SICR_1_IRQ_A_IRQ \ - | SICR_1_IRQ_B_IRQ \ - | SICR_1_GPIO_A_GPIO \ - | SICR_1_GPIO_B_GPIO \ - | SICR_1_GPIO_C_GPIO \ - | SICR_1_GPIO_D_GPIO \ - | SICR_1_GPIO_E_GPIO \ - | SICR_1_GPIO_F_GPIO \ - | SICR_1_USB_A_UART2S \ - | SICR_1_USB_B_UART2RTS \ - | SICR_1_FEC1_FEC1 \ - | SICR_1_FEC2_FEC2 \ - ) - -/* 0x00080400 SICR_2 */ -#define CONFIG_SYS_SICRH (0 \ - | SICR_2_FEC3_FEC3 \ - | SICR_2_HDLC1_A_HDLC1 \ - | SICR_2_ELBC_A_LA \ - | SICR_2_ELBC_B_LCLK \ - | SICR_2_HDLC2_A_HDLC2 \ - | SICR_2_USB_D_GPIO \ - | SICR_2_PCI_PCI \ - | SICR_2_HDLC1_B_HDLC1 \ - | SICR_2_HDLC1_C_HDLC1 \ - | SICR_2_HDLC2_B_GPIO \ - | SICR_2_HDLC2_C_HDLC2 \ - | SICR_2_QUIESCE_B \ - ) - -/* GPR_1 */ -#define CONFIG_SYS_GPR1 0x50008060 - -#define CONFIG_SYS_GP1DIR 0x00000000 -#define CONFIG_SYS_GP1ODR 0x00000000 -#define CONFIG_SYS_GP2DIR 0xFF000000 -#define CONFIG_SYS_GP2ODR 0x00000000 - -/* - * Hardware Reset Configuration Word - */ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \ - HRCWL_DDR_TO_SCB_CLK_2X1 | \ - HRCWL_CSB_TO_CLKIN_2X1 | \ - HRCWL_CORE_TO_CSB_2X1 | \ - HRCWL_CE_PLL_VCO_DIV_2 | \ - HRCWL_CE_TO_PLL_1X3) - -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_AGENT | \ - HRCWH_PCI_ARBITER_DISABLE | \ - HRCWH_CORE_ENABLE | \ - HRCWH_FROM_0X00000100 | \ - HRCWH_BOOTSEQ_DISABLE | \ - HRCWH_SW_WATCHDOG_DISABLE | \ - HRCWH_ROM_LOC_LOCAL_16BIT | \ - HRCWH_BIG_ENDIAN | \ - HRCWH_LALE_NORMAL) - -#define CONFIG_SYS_DDRCDR (\ - DDRCDR_EN | \ - DDRCDR_PZ_MAXZ | \ - DDRCDR_NZ_MAXZ | \ - DDRCDR_M_ODR) - -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f -#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ - SDRAM_CFG_32_BE | \ - SDRAM_CFG_SREN | \ - SDRAM_CFG_HSE) - -#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 -#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) -#define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ - (0x200 << SDRAM_INTERVAL_REFINT_SHIFT)) - -#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ - CSCONFIG_ODT_RD_NEVER | \ - CSCONFIG_ODT_WR_ONLY_CURRENT | \ - CSCONFIG_ROW_BIT_13 | \ - CSCONFIG_COL_BIT_10) - -#define CONFIG_SYS_DDR_MODE 0x47860242 -#define CONFIG_SYS_DDR_MODE2 0x8080c000 - -#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ - (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ - (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ - (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ - (0 << TIMING_CFG0_WWT_SHIFT) | \ - (0 << TIMING_CFG0_RRT_SHIFT) | \ - (0 << TIMING_CFG0_WRT_SHIFT) | \ - (0 << TIMING_CFG0_RWT_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \ - (2 << TIMING_CFG1_WRTORD_SHIFT) | \ - (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ - (3 << TIMING_CFG1_WRREC_SHIFT) | \ - (7 << TIMING_CFG1_REFREC_SHIFT) | \ - (3 << TIMING_CFG1_ACTTORW_SHIFT) | \ - (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ - (3 << TIMING_CFG1_PRETOACT_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ - (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ - (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ - (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ - (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ - (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \ - (5 << TIMING_CFG2_CPO_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_3 0x00000000 - -#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000 -#define CONFIG_SYS_KMBEC_FPGA_SIZE 128 - -/* EEprom support */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 - -/* - * Local Bus Configuration & Clock Setup - */ -#define CONFIG_SYS_LCRR_DBYP 0x80000000 -#define CONFIG_SYS_LCRR_EADC 0x00010000 -#define CONFIG_SYS_LCRR_CLKDIV 0x00000002 - -#define CONFIG_SYS_LBC_LBCR 0x00000000 - -/* - * MMU Setup - */ -#define CONFIG_SYS_IBAT7L (0) -#define CONFIG_SYS_IBAT7U (0) -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U - -#endif /* __CONFIG_KM8309_COMMON_H */ diff --git a/include/configs/km8321-common.h b/include/configs/km8321-common.h deleted file mode 100644 index a121a445f7..0000000000 --- a/include/configs/km8321-common.h +++ /dev/null @@ -1,139 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2006 Freescale Semiconductor, Inc. - * Dave Liu - * - * Copyright (C) 2007 Logic Product Development, Inc. - * Peter Barada - * - * Copyright (C) 2007 MontaVista Software, Inc. - * Anton Vorontsov - * - * (C) Copyright 2008 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * (C) Copyright 2010 - * Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com - * - * (C) Copyright 2010-2011 - * Thomas Reufer, KEYMILE Ltd, thomas.reufer@keymile.com - */ - -#ifndef __CONFIG_KM8321_COMMON_H -#define __CONFIG_KM8321_COMMON_H - -/* - * High Level Configuration Options - */ -#define CONFIG_QE /* Has QE */ -#define CONFIG_KM8321 /* Keymile PBEC8321 board specific */ - -#define CONFIG_KM_DEF_ARCH "arch=ppc_8xx\0" - -/* include common defines/options for all 83xx Keymile boards */ -#include "km83xx-common.h" - -/* - * System IO Config - */ -#define CONFIG_SYS_SICRL SICRL_IRQ_CKS - -/* - * Hardware Reset Configuration Word - */ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \ - HRCWL_DDR_TO_SCB_CLK_2X1 | \ - HRCWL_CSB_TO_CLKIN_2X1 | \ - HRCWL_CORE_TO_CSB_2_5X1 | \ - HRCWL_CE_PLL_VCO_DIV_2 | \ - HRCWL_CE_TO_PLL_1X3) - -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_AGENT | \ - HRCWH_PCI_ARBITER_DISABLE | \ - HRCWH_CORE_ENABLE | \ - HRCWH_FROM_0X00000100 | \ - HRCWH_BOOTSEQ_DISABLE | \ - HRCWH_SW_WATCHDOG_DISABLE | \ - HRCWH_ROM_LOC_LOCAL_16BIT | \ - HRCWH_BIG_ENDIAN | \ - HRCWH_LALE_NORMAL) - -#define CONFIG_SYS_DDRCDR (\ - DDRCDR_EN | \ - DDRCDR_PZ_MAXZ | \ - DDRCDR_NZ_MAXZ | \ - DDRCDR_M_ODR) - -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f -#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ - SDRAM_CFG_32_BE | \ - SDRAM_CFG_SREN | \ - SDRAM_CFG_HSE) - -#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 -#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) -#define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ - (0x200 << SDRAM_INTERVAL_REFINT_SHIFT)) - -#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ - CSCONFIG_ODT_WR_CFG | \ - CSCONFIG_ROW_BIT_13 | \ - CSCONFIG_COL_BIT_10) - -#define CONFIG_SYS_DDR_MODE 0x47860242 -#define CONFIG_SYS_DDR_MODE2 0x8080c000 - -#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ - (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ - (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ - (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ - (0 << TIMING_CFG0_WWT_SHIFT) | \ - (0 << TIMING_CFG0_RRT_SHIFT) | \ - (0 << TIMING_CFG0_WRT_SHIFT) | \ - (0 << TIMING_CFG0_RWT_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \ - (2 << TIMING_CFG1_WRTORD_SHIFT) | \ - (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ - (3 << TIMING_CFG1_WRREC_SHIFT) | \ - (7 << TIMING_CFG1_REFREC_SHIFT) | \ - (3 << TIMING_CFG1_ACTTORW_SHIFT) | \ - (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ - (3 << TIMING_CFG1_PRETOACT_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ - (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ - (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ - (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ - (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ - (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \ - (5 << TIMING_CFG2_CPO_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_3 0x00000000 - -#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000 -#define CONFIG_SYS_KMBEC_FPGA_SIZE 128 - -/* EEprom support */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 - -/* - * Local Bus Configuration & Clock Setup - */ -#define CONFIG_SYS_LCRR_DBYP 0x80000000 -#define CONFIG_SYS_LCRR_EADC 0x00010000 -#define CONFIG_SYS_LCRR_CLKDIV 0x00000002 - -#define CONFIG_SYS_LBC_LBCR 0x00000000 - -/* - * MMU Setup - */ -#define CONFIG_SYS_IBAT7L (0) -#define CONFIG_SYS_IBAT7U (0) -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U - -#endif /* __CONFIG_KM8321_COMMON_H */ diff --git a/include/configs/kmtegr1.h b/include/configs/kmtegr1.h index 95a131892d..27e3905c2b 100644 --- a/include/configs/kmtegr1.h +++ b/include/configs/kmtegr1.h @@ -35,8 +35,168 @@ #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define NAND_MAX_CHIPS 1 -/* include common defines/options for all 8309 Keymile boards */ -#include "km8309-common.h" +/* + * High Level Configuration Options + */ +#define CONFIG_E300 1 /* E300 family */ +#define CONFIG_QE 1 /* Has QE */ + +#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" + +/* include common defines/options for all 83xx Keymile boards */ +#include "km83xx-common.h" + +/* QE microcode/firmware address */ +#define CONFIG_SYS_QE_FMAN_FW_IN_NOR +/* between the u-boot partition and env */ +#ifndef CONFIG_SYS_QE_FW_ADDR +#define CONFIG_SYS_QE_FW_ADDR 0xF00C0000 +#endif + +/* + * System IO Config + */ +/* 0x14000180 SICR_1 */ +#define CONFIG_SYS_SICRL (0 \ + | SICR_1_UART1_UART1RTS \ + | SICR_1_I2C_CKSTOP \ + | SICR_1_IRQ_A_IRQ \ + | SICR_1_IRQ_B_IRQ \ + | SICR_1_GPIO_A_GPIO \ + | SICR_1_GPIO_B_GPIO \ + | SICR_1_GPIO_C_GPIO \ + | SICR_1_GPIO_D_GPIO \ + | SICR_1_GPIO_E_GPIO \ + | SICR_1_GPIO_F_GPIO \ + | SICR_1_USB_A_UART2S \ + | SICR_1_USB_B_UART2RTS \ + | SICR_1_FEC1_FEC1 \ + | SICR_1_FEC2_FEC2 \ + ) + +/* 0x00080400 SICR_2 */ +#define CONFIG_SYS_SICRH (0 \ + | SICR_2_FEC3_FEC3 \ + | SICR_2_HDLC1_A_HDLC1 \ + | SICR_2_ELBC_A_LA \ + | SICR_2_ELBC_B_LCLK \ + | SICR_2_HDLC2_A_HDLC2 \ + | SICR_2_USB_D_GPIO \ + | SICR_2_PCI_PCI \ + | SICR_2_HDLC1_B_HDLC1 \ + | SICR_2_HDLC1_C_HDLC1 \ + | SICR_2_HDLC2_B_GPIO \ + | SICR_2_HDLC2_C_HDLC2 \ + | SICR_2_QUIESCE_B \ + ) + +/* GPR_1 */ +#define CONFIG_SYS_GPR1 0x50008060 + +#define CONFIG_SYS_GP1DIR 0x00000000 +#define CONFIG_SYS_GP1ODR 0x00000000 +#define CONFIG_SYS_GP2DIR 0xFF000000 +#define CONFIG_SYS_GP2ODR 0x00000000 + +/* + * Hardware Reset Configuration Word + */ +#define CONFIG_SYS_HRCW_LOW (\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \ + HRCWL_DDR_TO_SCB_CLK_2X1 | \ + HRCWL_CSB_TO_CLKIN_2X1 | \ + HRCWL_CORE_TO_CSB_2X1 | \ + HRCWL_CE_PLL_VCO_DIV_2 | \ + HRCWL_CE_TO_PLL_1X3) + +#define CONFIG_SYS_HRCW_HIGH (\ + HRCWH_PCI_AGENT | \ + HRCWH_PCI_ARBITER_DISABLE | \ + HRCWH_CORE_ENABLE | \ + HRCWH_FROM_0X00000100 | \ + HRCWH_BOOTSEQ_DISABLE | \ + HRCWH_SW_WATCHDOG_DISABLE | \ + HRCWH_ROM_LOC_LOCAL_16BIT | \ + HRCWH_BIG_ENDIAN | \ + HRCWH_LALE_NORMAL) + +#define CONFIG_SYS_DDRCDR (\ + DDRCDR_EN | \ + DDRCDR_PZ_MAXZ | \ + DDRCDR_NZ_MAXZ | \ + DDRCDR_M_ODR) + +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f +#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ + SDRAM_CFG_32_BE | \ + SDRAM_CFG_SREN | \ + SDRAM_CFG_HSE) + +#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 +#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) +#define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ + (0x200 << SDRAM_INTERVAL_REFINT_SHIFT)) + +#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ + CSCONFIG_ODT_RD_NEVER | \ + CSCONFIG_ODT_WR_ONLY_CURRENT | \ + CSCONFIG_ROW_BIT_13 | \ + CSCONFIG_COL_BIT_10) + +#define CONFIG_SYS_DDR_MODE 0x47860242 +#define CONFIG_SYS_DDR_MODE2 0x8080c000 + +#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ + (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ + (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ + (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ + (0 << TIMING_CFG0_WWT_SHIFT) | \ + (0 << TIMING_CFG0_RRT_SHIFT) | \ + (0 << TIMING_CFG0_WRT_SHIFT) | \ + (0 << TIMING_CFG0_RWT_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \ + (2 << TIMING_CFG1_WRTORD_SHIFT) | \ + (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ + (3 << TIMING_CFG1_WRREC_SHIFT) | \ + (7 << TIMING_CFG1_REFREC_SHIFT) | \ + (3 << TIMING_CFG1_ACTTORW_SHIFT) | \ + (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ + (3 << TIMING_CFG1_PRETOACT_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ + (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ + (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ + (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ + (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ + (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \ + (5 << TIMING_CFG2_CPO_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_3 0x00000000 + +#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000 +#define CONFIG_SYS_KMBEC_FPGA_SIZE 128 + +/* EEprom support */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 + +/* + * Local Bus Configuration & Clock Setup + */ +#define CONFIG_SYS_LCRR_DBYP 0x80000000 +#define CONFIG_SYS_LCRR_EADC 0x00010000 +#define CONFIG_SYS_LCRR_CLKDIV 0x00000002 + +#define CONFIG_SYS_LBC_LBCR 0x00000000 + +/* + * MMU Setup + */ +#define CONFIG_SYS_IBAT7L (0) +#define CONFIG_SYS_IBAT7U (0) +#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L +#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U + /* must be after the include because KMBEC_FPGA is otherwise undefined */ #define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */ diff --git a/include/configs/kmvect1.h b/include/configs/kmvect1.h index 0bbf541aec..5a0fbccade 100644 --- a/include/configs/kmvect1.h +++ b/include/configs/kmvect1.h @@ -26,8 +26,168 @@ #define CONFIG_KM_BOARD_NAME "kmvect1" /* at end of uboot partition, before env */ #define CONFIG_SYS_QE_FW_ADDR 0xF00B0000 -/* include common defines/options for all 8309 Keymile boards */ -#include "km8309-common.h" + +/* + * High Level Configuration Options + */ +#define CONFIG_E300 1 /* E300 family */ +#define CONFIG_QE 1 /* Has QE */ + +#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" + +/* include common defines/options for all 83xx Keymile boards */ +#include "km83xx-common.h" + +/* QE microcode/firmware address */ +#define CONFIG_SYS_QE_FMAN_FW_IN_NOR +/* between the u-boot partition and env */ +#ifndef CONFIG_SYS_QE_FW_ADDR +#define CONFIG_SYS_QE_FW_ADDR 0xF00C0000 +#endif + +/* + * System IO Config + */ +/* 0x14000180 SICR_1 */ +#define CONFIG_SYS_SICRL (0 \ + | SICR_1_UART1_UART1RTS \ + | SICR_1_I2C_CKSTOP \ + | SICR_1_IRQ_A_IRQ \ + | SICR_1_IRQ_B_IRQ \ + | SICR_1_GPIO_A_GPIO \ + | SICR_1_GPIO_B_GPIO \ + | SICR_1_GPIO_C_GPIO \ + | SICR_1_GPIO_D_GPIO \ + | SICR_1_GPIO_E_GPIO \ + | SICR_1_GPIO_F_GPIO \ + | SICR_1_USB_A_UART2S \ + | SICR_1_USB_B_UART2RTS \ + | SICR_1_FEC1_FEC1 \ + | SICR_1_FEC2_FEC2 \ + ) + +/* 0x00080400 SICR_2 */ +#define CONFIG_SYS_SICRH (0 \ + | SICR_2_FEC3_FEC3 \ + | SICR_2_HDLC1_A_HDLC1 \ + | SICR_2_ELBC_A_LA \ + | SICR_2_ELBC_B_LCLK \ + | SICR_2_HDLC2_A_HDLC2 \ + | SICR_2_USB_D_GPIO \ + | SICR_2_PCI_PCI \ + | SICR_2_HDLC1_B_HDLC1 \ + | SICR_2_HDLC1_C_HDLC1 \ + | SICR_2_HDLC2_B_GPIO \ + | SICR_2_HDLC2_C_HDLC2 \ + | SICR_2_QUIESCE_B \ + ) + +/* GPR_1 */ +#define CONFIG_SYS_GPR1 0x50008060 + +#define CONFIG_SYS_GP1DIR 0x00000000 +#define CONFIG_SYS_GP1ODR 0x00000000 +#define CONFIG_SYS_GP2DIR 0xFF000000 +#define CONFIG_SYS_GP2ODR 0x00000000 + +/* + * Hardware Reset Configuration Word + */ +#define CONFIG_SYS_HRCW_LOW (\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \ + HRCWL_DDR_TO_SCB_CLK_2X1 | \ + HRCWL_CSB_TO_CLKIN_2X1 | \ + HRCWL_CORE_TO_CSB_2X1 | \ + HRCWL_CE_PLL_VCO_DIV_2 | \ + HRCWL_CE_TO_PLL_1X3) + +#define CONFIG_SYS_HRCW_HIGH (\ + HRCWH_PCI_AGENT | \ + HRCWH_PCI_ARBITER_DISABLE | \ + HRCWH_CORE_ENABLE | \ + HRCWH_FROM_0X00000100 | \ + HRCWH_BOOTSEQ_DISABLE | \ + HRCWH_SW_WATCHDOG_DISABLE | \ + HRCWH_ROM_LOC_LOCAL_16BIT | \ + HRCWH_BIG_ENDIAN | \ + HRCWH_LALE_NORMAL) + +#define CONFIG_SYS_DDRCDR (\ + DDRCDR_EN | \ + DDRCDR_PZ_MAXZ | \ + DDRCDR_NZ_MAXZ | \ + DDRCDR_M_ODR) + +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f +#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ + SDRAM_CFG_32_BE | \ + SDRAM_CFG_SREN | \ + SDRAM_CFG_HSE) + +#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 +#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) +#define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ + (0x200 << SDRAM_INTERVAL_REFINT_SHIFT)) + +#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ + CSCONFIG_ODT_RD_NEVER | \ + CSCONFIG_ODT_WR_ONLY_CURRENT | \ + CSCONFIG_ROW_BIT_13 | \ + CSCONFIG_COL_BIT_10) + +#define CONFIG_SYS_DDR_MODE 0x47860242 +#define CONFIG_SYS_DDR_MODE2 0x8080c000 + +#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ + (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ + (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ + (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ + (0 << TIMING_CFG0_WWT_SHIFT) | \ + (0 << TIMING_CFG0_RRT_SHIFT) | \ + (0 << TIMING_CFG0_WRT_SHIFT) | \ + (0 << TIMING_CFG0_RWT_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \ + (2 << TIMING_CFG1_WRTORD_SHIFT) | \ + (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ + (3 << TIMING_CFG1_WRREC_SHIFT) | \ + (7 << TIMING_CFG1_REFREC_SHIFT) | \ + (3 << TIMING_CFG1_ACTTORW_SHIFT) | \ + (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ + (3 << TIMING_CFG1_PRETOACT_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ + (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ + (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ + (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ + (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ + (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \ + (5 << TIMING_CFG2_CPO_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_3 0x00000000 + +#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000 +#define CONFIG_SYS_KMBEC_FPGA_SIZE 128 + +/* EEprom support */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 + +/* + * Local Bus Configuration & Clock Setup + */ +#define CONFIG_SYS_LCRR_DBYP 0x80000000 +#define CONFIG_SYS_LCRR_EADC 0x00010000 +#define CONFIG_SYS_LCRR_CLKDIV 0x00000002 + +#define CONFIG_SYS_LBC_LBCR 0x00000000 + +/* + * MMU Setup + */ +#define CONFIG_SYS_IBAT7L (0) +#define CONFIG_SYS_IBAT7U (0) +#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L +#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U #define CONFIG_SYS_APP1_BASE 0xA0000000 #define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ diff --git a/include/configs/suvd3.h b/include/configs/suvd3.h index 98137392ed..5fe5f3cc23 100644 --- a/include/configs/suvd3.h +++ b/include/configs/suvd3.h @@ -24,8 +24,120 @@ #define CONFIG_HOSTNAME "suvd3" #define CONFIG_KM_BOARD_NAME "suvd3" -/* include common defines/options for all 8321 Keymile boards */ -#include "km8321-common.h" + +/* + * High Level Configuration Options + */ +#define CONFIG_QE /* Has QE */ +#define CONFIG_KM8321 /* Keymile PBEC8321 board specific */ + +#define CONFIG_KM_DEF_ARCH "arch=ppc_8xx\0" + +/* include common defines/options for all 83xx Keymile boards */ +#include "km83xx-common.h" + +/* + * System IO Config + */ +#define CONFIG_SYS_SICRL SICRL_IRQ_CKS + +/* + * Hardware Reset Configuration Word + */ +#define CONFIG_SYS_HRCW_LOW (\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \ + HRCWL_DDR_TO_SCB_CLK_2X1 | \ + HRCWL_CSB_TO_CLKIN_2X1 | \ + HRCWL_CORE_TO_CSB_2_5X1 | \ + HRCWL_CE_PLL_VCO_DIV_2 | \ + HRCWL_CE_TO_PLL_1X3) + +#define CONFIG_SYS_HRCW_HIGH (\ + HRCWH_PCI_AGENT | \ + HRCWH_PCI_ARBITER_DISABLE | \ + HRCWH_CORE_ENABLE | \ + HRCWH_FROM_0X00000100 | \ + HRCWH_BOOTSEQ_DISABLE | \ + HRCWH_SW_WATCHDOG_DISABLE | \ + HRCWH_ROM_LOC_LOCAL_16BIT | \ + HRCWH_BIG_ENDIAN | \ + HRCWH_LALE_NORMAL) + +#define CONFIG_SYS_DDRCDR (\ + DDRCDR_EN | \ + DDRCDR_PZ_MAXZ | \ + DDRCDR_NZ_MAXZ | \ + DDRCDR_M_ODR) + +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f +#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ + SDRAM_CFG_32_BE | \ + SDRAM_CFG_SREN | \ + SDRAM_CFG_HSE) + +#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 +#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) +#define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ + (0x200 << SDRAM_INTERVAL_REFINT_SHIFT)) + +#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ + CSCONFIG_ODT_WR_CFG | \ + CSCONFIG_ROW_BIT_13 | \ + CSCONFIG_COL_BIT_10) + +#define CONFIG_SYS_DDR_MODE 0x47860242 +#define CONFIG_SYS_DDR_MODE2 0x8080c000 + +#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ + (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ + (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ + (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ + (0 << TIMING_CFG0_WWT_SHIFT) | \ + (0 << TIMING_CFG0_RRT_SHIFT) | \ + (0 << TIMING_CFG0_WRT_SHIFT) | \ + (0 << TIMING_CFG0_RWT_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \ + (2 << TIMING_CFG1_WRTORD_SHIFT) | \ + (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ + (3 << TIMING_CFG1_WRREC_SHIFT) | \ + (7 << TIMING_CFG1_REFREC_SHIFT) | \ + (3 << TIMING_CFG1_ACTTORW_SHIFT) | \ + (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ + (3 << TIMING_CFG1_PRETOACT_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ + (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ + (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ + (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ + (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ + (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \ + (5 << TIMING_CFG2_CPO_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_3 0x00000000 + +#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000 +#define CONFIG_SYS_KMBEC_FPGA_SIZE 128 + +/* EEprom support */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 + +/* + * Local Bus Configuration & Clock Setup + */ +#define CONFIG_SYS_LCRR_DBYP 0x80000000 +#define CONFIG_SYS_LCRR_EADC 0x00010000 +#define CONFIG_SYS_LCRR_CLKDIV 0x00000002 + +#define CONFIG_SYS_LBC_LBCR 0x00000000 + +/* + * MMU Setup + */ +#define CONFIG_SYS_IBAT7L (0) +#define CONFIG_SYS_IBAT7U (0) +#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L +#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U #define CONFIG_SYS_APP1_BASE 0xA0000000 #define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ diff --git a/include/configs/tuxx1.h b/include/configs/tuxx1.h index 0b17084b05..c031661830 100644 --- a/include/configs/tuxx1.h +++ b/include/configs/tuxx1.h @@ -42,8 +42,119 @@ #error ("Board not supported") #endif -/* include common defines/options for all 8321 Keymile boards */ -#include "km8321-common.h" +/* + * High Level Configuration Options + */ +#define CONFIG_QE /* Has QE */ +#define CONFIG_KM8321 /* Keymile PBEC8321 board specific */ + +#define CONFIG_KM_DEF_ARCH "arch=ppc_8xx\0" + +/* include common defines/options for all 83xx Keymile boards */ +#include "km83xx-common.h" + +/* + * System IO Config + */ +#define CONFIG_SYS_SICRL SICRL_IRQ_CKS + +/* + * Hardware Reset Configuration Word + */ +#define CONFIG_SYS_HRCW_LOW (\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \ + HRCWL_DDR_TO_SCB_CLK_2X1 | \ + HRCWL_CSB_TO_CLKIN_2X1 | \ + HRCWL_CORE_TO_CSB_2_5X1 | \ + HRCWL_CE_PLL_VCO_DIV_2 | \ + HRCWL_CE_TO_PLL_1X3) + +#define CONFIG_SYS_HRCW_HIGH (\ + HRCWH_PCI_AGENT | \ + HRCWH_PCI_ARBITER_DISABLE | \ + HRCWH_CORE_ENABLE | \ + HRCWH_FROM_0X00000100 | \ + HRCWH_BOOTSEQ_DISABLE | \ + HRCWH_SW_WATCHDOG_DISABLE | \ + HRCWH_ROM_LOC_LOCAL_16BIT | \ + HRCWH_BIG_ENDIAN | \ + HRCWH_LALE_NORMAL) + +#define CONFIG_SYS_DDRCDR (\ + DDRCDR_EN | \ + DDRCDR_PZ_MAXZ | \ + DDRCDR_NZ_MAXZ | \ + DDRCDR_M_ODR) + +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f +#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ + SDRAM_CFG_32_BE | \ + SDRAM_CFG_SREN | \ + SDRAM_CFG_HSE) + +#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 +#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) +#define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ + (0x200 << SDRAM_INTERVAL_REFINT_SHIFT)) + +#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ + CSCONFIG_ODT_WR_CFG | \ + CSCONFIG_ROW_BIT_13 | \ + CSCONFIG_COL_BIT_10) + +#define CONFIG_SYS_DDR_MODE 0x47860242 +#define CONFIG_SYS_DDR_MODE2 0x8080c000 + +#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ + (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ + (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ + (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ + (0 << TIMING_CFG0_WWT_SHIFT) | \ + (0 << TIMING_CFG0_RRT_SHIFT) | \ + (0 << TIMING_CFG0_WRT_SHIFT) | \ + (0 << TIMING_CFG0_RWT_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \ + (2 << TIMING_CFG1_WRTORD_SHIFT) | \ + (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ + (3 << TIMING_CFG1_WRREC_SHIFT) | \ + (7 << TIMING_CFG1_REFREC_SHIFT) | \ + (3 << TIMING_CFG1_ACTTORW_SHIFT) | \ + (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ + (3 << TIMING_CFG1_PRETOACT_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ + (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ + (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ + (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ + (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ + (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \ + (5 << TIMING_CFG2_CPO_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_3 0x00000000 + +#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000 +#define CONFIG_SYS_KMBEC_FPGA_SIZE 128 + +/* EEprom support */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 + +/* + * Local Bus Configuration & Clock Setup + */ +#define CONFIG_SYS_LCRR_DBYP 0x80000000 +#define CONFIG_SYS_LCRR_EADC 0x00010000 +#define CONFIG_SYS_LCRR_CLKDIV 0x00000002 + +#define CONFIG_SYS_LBC_LBCR 0x00000000 + +/* + * MMU Setup + */ +#define CONFIG_SYS_IBAT7L (0) +#define CONFIG_SYS_IBAT7U (0) +#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L +#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U #define CONFIG_SYS_APP1_BASE 0xA0000000 /* PAXG */ #define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ From 71c790097be0c5e7e99b1ca83e27e1232c12fc02 Mon Sep 17 00:00:00 2001 From: Mario Six Date: Mon, 21 Jan 2019 09:17:33 +0100 Subject: [PATCH 10/86] keymile: Make distinct kmsupx5, tuge1, kmopti2, and kmtepr2 configs The kmsupx5, tuge1, kmopti2, and kmtepr2 boards all build from the same include config file with lots of #ifdef logic. To ease Kconfig migration, create new config include files for these boards, and resolve the #ifdef logic as needed. Signed-off-by: Mario Six --- arch/powerpc/cpu/mpc83xx/Kconfig | 24 ++++ board/keymile/km83xx/Kconfig | 52 +++++++ configs/kmopti2_defconfig | 3 +- configs/kmsupx5_defconfig | 3 +- configs/kmtepr2_defconfig | 3 +- configs/tuge1_defconfig | 3 +- configs/tuxx1_defconfig | 1 - include/configs/kmopti2.h | 234 ++++++++++++++++++++++++++++++ include/configs/kmsupx5.h | 210 +++++++++++++++++++++++++++ include/configs/kmtepr2.h | 235 +++++++++++++++++++++++++++++++ include/configs/tuge1.h | 210 +++++++++++++++++++++++++++ include/configs/tuxx1.h | 62 -------- 12 files changed, 969 insertions(+), 71 deletions(-) create mode 100644 include/configs/kmopti2.h create mode 100644 include/configs/kmsupx5.h create mode 100644 include/configs/kmtepr2.h create mode 100644 include/configs/tuge1.h diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index 59e0c9a8d0..1ebb092f0b 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -111,6 +111,30 @@ config TARGET_TUXX1 imply CMD_CRAMFS imply FS_CRAMFS +config TARGET_KMSUPX5 + bool "Support kmsupx5" + select ARCH_MPC832X + imply CMD_CRAMFS + imply FS_CRAMFS + +config TARGET_TUGE1 + bool "Support tuge1" + select ARCH_MPC832X + imply CMD_CRAMFS + imply FS_CRAMFS + +config TARGET_KMOPTI2 + bool "Support kmopti2" + select ARCH_MPC832X + imply CMD_CRAMFS + imply FS_CRAMFS + +config TARGET_KMTEPR2 + bool "Support kmtepr2" + select ARCH_MPC832X + imply CMD_CRAMFS + imply FS_CRAMFS + config TARGET_TQM834X bool "Support TQM834x" select ARCH_MPC8349 diff --git a/board/keymile/km83xx/Kconfig b/board/keymile/km83xx/Kconfig index d52ee9117b..0c4fa0b7fd 100644 --- a/board/keymile/km83xx/Kconfig +++ b/board/keymile/km83xx/Kconfig @@ -62,3 +62,55 @@ config SYS_CONFIG_NAME default "tuxx1" endif + +if TARGET_KMSUPX5 + +config SYS_BOARD + default "km83xx" + +config SYS_VENDOR + default "keymile" + +config SYS_CONFIG_NAME + default "kmsupx5" + +endif + +if TARGET_TUGE1 + +config SYS_BOARD + default "km83xx" + +config SYS_VENDOR + default "keymile" + +config SYS_CONFIG_NAME + default "tuge1" + +endif + +if TARGET_KMOPTI2 + +config SYS_BOARD + default "km83xx" + +config SYS_VENDOR + default "keymile" + +config SYS_CONFIG_NAME + default "kmopti2" + +endif + +if TARGET_KMTEPR2 + +config SYS_BOARD + default "km83xx" + +config SYS_VENDOR + default "keymile" + +config SYS_CONFIG_NAME + default "kmtepr2" + +endif diff --git a/configs/kmopti2_defconfig b/configs/kmopti2_defconfig index e8e821fb80..c0927dd478 100644 --- a/configs/kmopti2_defconfig +++ b/configs/kmopti2_defconfig @@ -1,10 +1,9 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xF0000000 CONFIG_MPC83xx=y -CONFIG_TARGET_TUXX1=y +CONFIG_TARGET_KMOPTI2=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="KMOPTI2" CONFIG_MISC_INIT_R=y CONFIG_VERSION_VARIABLE=y CONFIG_BOARD_EARLY_INIT_R=y diff --git a/configs/kmsupx5_defconfig b/configs/kmsupx5_defconfig index 86e2bd9237..7a00c85a84 100644 --- a/configs/kmsupx5_defconfig +++ b/configs/kmsupx5_defconfig @@ -1,10 +1,9 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xF0000000 CONFIG_MPC83xx=y -CONFIG_TARGET_TUXX1=y +CONFIG_TARGET_KMSUPX5=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="KMSUPX5" CONFIG_MISC_INIT_R=y CONFIG_VERSION_VARIABLE=y CONFIG_BOARD_EARLY_INIT_R=y diff --git a/configs/kmtepr2_defconfig b/configs/kmtepr2_defconfig index 6170dc3f16..310cf5ac66 100644 --- a/configs/kmtepr2_defconfig +++ b/configs/kmtepr2_defconfig @@ -1,10 +1,9 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xF0000000 CONFIG_MPC83xx=y -CONFIG_TARGET_TUXX1=y +CONFIG_TARGET_KMTEPR2=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="KMTEPR2" CONFIG_MISC_INIT_R=y CONFIG_VERSION_VARIABLE=y CONFIG_BOARD_EARLY_INIT_R=y diff --git a/configs/tuge1_defconfig b/configs/tuge1_defconfig index e5826719b9..a3e04bc0f8 100644 --- a/configs/tuge1_defconfig +++ b/configs/tuge1_defconfig @@ -1,10 +1,9 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xF0000000 CONFIG_MPC83xx=y -CONFIG_TARGET_TUXX1=y +CONFIG_TARGET_TUGE1=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="TUGE1" CONFIG_MISC_INIT_R=y CONFIG_VERSION_VARIABLE=y CONFIG_BOARD_EARLY_INIT_R=y diff --git a/configs/tuxx1_defconfig b/configs/tuxx1_defconfig index 204d3e4f68..d1fc62697e 100644 --- a/configs/tuxx1_defconfig +++ b/configs/tuxx1_defconfig @@ -4,7 +4,6 @@ CONFIG_MPC83xx=y CONFIG_TARGET_TUXX1=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="TUXX1" CONFIG_MISC_INIT_R=y CONFIG_VERSION_VARIABLE=y CONFIG_BOARD_EARLY_INIT_R=y diff --git a/include/configs/kmopti2.h b/include/configs/kmopti2.h new file mode 100644 index 0000000000..0621be3928 --- /dev/null +++ b/include/configs/kmopti2.h @@ -0,0 +1,234 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2006 Freescale Semiconductor, Inc. + * Dave Liu + * + * Copyright (C) 2007 Logic Product Development, Inc. + * Peter Barada + * + * Copyright (C) 2007 MontaVista Software, Inc. + * Anton Vorontsov + * + * (C) Copyright 2008 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * (C) Copyright 2010-2013 + * Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com + * Holger Brunck, Keymile GmbH, holger.bruncl@keymile.com + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_KM_BOARD_NAME "kmopti2" +#define CONFIG_HOSTNAME "kmopti2" + +/* + * High Level Configuration Options + */ +#define CONFIG_QE /* Has QE */ +#define CONFIG_KM8321 /* Keymile PBEC8321 board specific */ + +#define CONFIG_KM_DEF_ARCH "arch=ppc_8xx\0" + +/* include common defines/options for all 83xx Keymile boards */ +#include "km83xx-common.h" + +/* + * System IO Config + */ +#define CONFIG_SYS_SICRL SICRL_IRQ_CKS + +/* + * Hardware Reset Configuration Word + */ +#define CONFIG_SYS_HRCW_LOW (\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \ + HRCWL_DDR_TO_SCB_CLK_2X1 | \ + HRCWL_CSB_TO_CLKIN_2X1 | \ + HRCWL_CORE_TO_CSB_2_5X1 | \ + HRCWL_CE_PLL_VCO_DIV_2 | \ + HRCWL_CE_TO_PLL_1X3) + +#define CONFIG_SYS_HRCW_HIGH (\ + HRCWH_PCI_AGENT | \ + HRCWH_PCI_ARBITER_DISABLE | \ + HRCWH_CORE_ENABLE | \ + HRCWH_FROM_0X00000100 | \ + HRCWH_BOOTSEQ_DISABLE | \ + HRCWH_SW_WATCHDOG_DISABLE | \ + HRCWH_ROM_LOC_LOCAL_16BIT | \ + HRCWH_BIG_ENDIAN | \ + HRCWH_LALE_NORMAL) + +#define CONFIG_SYS_DDRCDR (\ + DDRCDR_EN | \ + DDRCDR_PZ_MAXZ | \ + DDRCDR_NZ_MAXZ | \ + DDRCDR_M_ODR) + +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f +#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ + SDRAM_CFG_32_BE | \ + SDRAM_CFG_SREN | \ + SDRAM_CFG_HSE) + +#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 +#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) +#define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ + (0x200 << SDRAM_INTERVAL_REFINT_SHIFT)) + +#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ + CSCONFIG_ODT_WR_CFG | \ + CSCONFIG_ROW_BIT_13 | \ + CSCONFIG_COL_BIT_10) + +#define CONFIG_SYS_DDR_MODE 0x47860242 +#define CONFIG_SYS_DDR_MODE2 0x8080c000 + +#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ + (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ + (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ + (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ + (0 << TIMING_CFG0_WWT_SHIFT) | \ + (0 << TIMING_CFG0_RRT_SHIFT) | \ + (0 << TIMING_CFG0_WRT_SHIFT) | \ + (0 << TIMING_CFG0_RWT_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \ + (2 << TIMING_CFG1_WRTORD_SHIFT) | \ + (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ + (3 << TIMING_CFG1_WRREC_SHIFT) | \ + (7 << TIMING_CFG1_REFREC_SHIFT) | \ + (3 << TIMING_CFG1_ACTTORW_SHIFT) | \ + (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ + (3 << TIMING_CFG1_PRETOACT_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ + (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ + (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ + (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ + (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ + (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \ + (5 << TIMING_CFG2_CPO_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_3 0x00000000 + +#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000 +#define CONFIG_SYS_KMBEC_FPGA_SIZE 128 + +/* EEprom support */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 + +/* + * Local Bus Configuration & Clock Setup + */ +#define CONFIG_SYS_LCRR_DBYP 0x80000000 +#define CONFIG_SYS_LCRR_EADC 0x00010000 +#define CONFIG_SYS_LCRR_CLKDIV 0x00000002 + +#define CONFIG_SYS_LBC_LBCR 0x00000000 + +/* + * MMU Setup + */ +#define CONFIG_SYS_IBAT7L (0) +#define CONFIG_SYS_IBAT7U (0) +#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L +#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U + +#define CONFIG_SYS_APP1_BASE 0xA0000000 /* PAXG */ +#define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ +#define CONFIG_SYS_APP2_BASE 0xB0000000 /* PINC3 */ +#define CONFIG_SYS_APP2_SIZE 256 /* Megabytes */ + +/* + * Init Local Bus Memory Controller: + * Device on board + * Bank Bus Machine PortSz Size TUDA1 TUXA1 TUGE1 KMSUPX4 KMOPTI2 + * ----------------------------------------------------------------------------- + * 2 Local GPCM 8 bit 256MB PAXG LPXF PAXI LPXF PAXE + * 3 Local GPCM 8 bit 256MB PINC3 PINC2 unused unused OPI2(16 bit) + * + * Device on board (continued) + * Bank Bus Machine PortSz Size KMTEPR2 + * ----------------------------------------------------------------------------- + * 2 Local GPCM 8 bit 256MB NVRAM + * 3 Local GPCM 8 bit 256MB TEP2 (16 bit) + */ + +/* + * Configuration for C2 on the local bus + */ +/* Window base at flash base */ +#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_APP1_BASE +/* Window size: 256 MB */ +#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) + +#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_APP1_BASE | \ + BR_PS_8 | \ + BR_MS_GPCM | \ + BR_V) + +#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_APP1_SIZE) | \ + OR_GPCM_CSNT | \ + OR_GPCM_ACS_DIV4 | \ + OR_GPCM_SCY_2 | \ + OR_GPCM_TRLX_SET | \ + OR_GPCM_EHTR_CLEAR | \ + OR_GPCM_EAD) + +/* + * Configuration for C3 on the local bus + */ +#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_APP2_BASE +#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) +#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_APP2_BASE | \ + BR_PS_16 | \ + BR_MS_GPCM | \ + BR_V) +#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \ + OR_GPCM_SCY_4 | \ + OR_GPCM_TRLX_CLEAR | \ + OR_GPCM_EHTR_CLEAR) +/* + * MMU Setup + */ +/* APP1: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT5L (CONFIG_SYS_APP1_BASE | \ + BATL_PP_RW | \ + BATL_MEMCOHERENCE) +/* 512M should also include APP2... */ +#define CONFIG_SYS_IBAT5U (CONFIG_SYS_APP1_BASE | \ + BATU_BL_256M | \ + BATU_VS | \ + BATU_VP) +#define CONFIG_SYS_DBAT5L (CONFIG_SYS_APP1_BASE | \ + BATL_PP_RW | \ + BATL_CACHEINHIBIT | \ + BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U + +/* APP2: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT6L (CONFIG_SYS_APP2_BASE | \ + BATL_PP_RW | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT6U (CONFIG_SYS_APP2_BASE | \ + BATU_BL_256M | \ + BATU_VS | \ + BATU_VP) +#define CONFIG_SYS_DBAT6L (CONFIG_SYS_APP2_BASE | \ + BATL_PP_RW | \ + BATL_CACHEINHIBIT | \ + BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U + +#define CONFIG_SYS_IBAT7L (0) +#define CONFIG_SYS_IBAT7U (0) +#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L +#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U + +#endif /* __CONFIG_H */ diff --git a/include/configs/kmsupx5.h b/include/configs/kmsupx5.h new file mode 100644 index 0000000000..be93b7ce89 --- /dev/null +++ b/include/configs/kmsupx5.h @@ -0,0 +1,210 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2006 Freescale Semiconductor, Inc. + * Dave Liu + * + * Copyright (C) 2007 Logic Product Development, Inc. + * Peter Barada + * + * Copyright (C) 2007 MontaVista Software, Inc. + * Anton Vorontsov + * + * (C) Copyright 2008 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * (C) Copyright 2010-2013 + * Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com + * Holger Brunck, Keymile GmbH, holger.bruncl@keymile.com + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_KM_BOARD_NAME "kmsupx5" +#define CONFIG_HOSTNAME "kmsupx5" + +/* + * High Level Configuration Options + */ +#define CONFIG_QE /* Has QE */ +#define CONFIG_KM8321 /* Keymile PBEC8321 board specific */ + +#define CONFIG_KM_DEF_ARCH "arch=ppc_8xx\0" + +/* include common defines/options for all 83xx Keymile boards */ +#include "km83xx-common.h" + +/* + * System IO Config + */ +#define CONFIG_SYS_SICRL SICRL_IRQ_CKS + +/* + * Hardware Reset Configuration Word + */ +#define CONFIG_SYS_HRCW_LOW (\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \ + HRCWL_DDR_TO_SCB_CLK_2X1 | \ + HRCWL_CSB_TO_CLKIN_2X1 | \ + HRCWL_CORE_TO_CSB_2_5X1 | \ + HRCWL_CE_PLL_VCO_DIV_2 | \ + HRCWL_CE_TO_PLL_1X3) + +#define CONFIG_SYS_HRCW_HIGH (\ + HRCWH_PCI_AGENT | \ + HRCWH_PCI_ARBITER_DISABLE | \ + HRCWH_CORE_ENABLE | \ + HRCWH_FROM_0X00000100 | \ + HRCWH_BOOTSEQ_DISABLE | \ + HRCWH_SW_WATCHDOG_DISABLE | \ + HRCWH_ROM_LOC_LOCAL_16BIT | \ + HRCWH_BIG_ENDIAN | \ + HRCWH_LALE_NORMAL) + +#define CONFIG_SYS_DDRCDR (\ + DDRCDR_EN | \ + DDRCDR_PZ_MAXZ | \ + DDRCDR_NZ_MAXZ | \ + DDRCDR_M_ODR) + +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f +#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ + SDRAM_CFG_32_BE | \ + SDRAM_CFG_SREN | \ + SDRAM_CFG_HSE) + +#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 +#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) +#define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ + (0x200 << SDRAM_INTERVAL_REFINT_SHIFT)) + +#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ + CSCONFIG_ODT_WR_CFG | \ + CSCONFIG_ROW_BIT_13 | \ + CSCONFIG_COL_BIT_10) + +#define CONFIG_SYS_DDR_MODE 0x47860242 +#define CONFIG_SYS_DDR_MODE2 0x8080c000 + +#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ + (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ + (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ + (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ + (0 << TIMING_CFG0_WWT_SHIFT) | \ + (0 << TIMING_CFG0_RRT_SHIFT) | \ + (0 << TIMING_CFG0_WRT_SHIFT) | \ + (0 << TIMING_CFG0_RWT_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \ + (2 << TIMING_CFG1_WRTORD_SHIFT) | \ + (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ + (3 << TIMING_CFG1_WRREC_SHIFT) | \ + (7 << TIMING_CFG1_REFREC_SHIFT) | \ + (3 << TIMING_CFG1_ACTTORW_SHIFT) | \ + (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ + (3 << TIMING_CFG1_PRETOACT_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ + (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ + (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ + (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ + (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ + (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \ + (5 << TIMING_CFG2_CPO_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_3 0x00000000 + +#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000 +#define CONFIG_SYS_KMBEC_FPGA_SIZE 128 + +/* EEprom support */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 + +/* + * Local Bus Configuration & Clock Setup + */ +#define CONFIG_SYS_LCRR_DBYP 0x80000000 +#define CONFIG_SYS_LCRR_EADC 0x00010000 +#define CONFIG_SYS_LCRR_CLKDIV 0x00000002 + +#define CONFIG_SYS_LBC_LBCR 0x00000000 + +/* + * MMU Setup + */ +#define CONFIG_SYS_IBAT7L (0) +#define CONFIG_SYS_IBAT7U (0) +#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L +#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U + +#define CONFIG_SYS_APP1_BASE 0xA0000000 /* PAXG */ +#define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ + +/* + * Init Local Bus Memory Controller: + * Device on board + * Bank Bus Machine PortSz Size TUDA1 TUXA1 TUGE1 KMSUPX4 KMOPTI2 + * ----------------------------------------------------------------------------- + * 2 Local GPCM 8 bit 256MB PAXG LPXF PAXI LPXF PAXE + * 3 Local GPCM 8 bit 256MB PINC3 PINC2 unused unused OPI2(16 bit) + * + * Device on board (continued) + * Bank Bus Machine PortSz Size KMTEPR2 + * ----------------------------------------------------------------------------- + * 2 Local GPCM 8 bit 256MB NVRAM + * 3 Local GPCM 8 bit 256MB TEP2 (16 bit) + */ + +/* + * Configuration for C2 on the local bus + */ +/* Window base at flash base */ +#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_APP1_BASE +/* Window size: 256 MB */ +#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) + +#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_APP1_BASE | \ + BR_PS_8 | \ + BR_MS_GPCM | \ + BR_V) + +#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_APP1_SIZE) | \ + OR_GPCM_CSNT | \ + OR_GPCM_ACS_DIV4 | \ + OR_GPCM_SCY_2 | \ + OR_GPCM_TRLX_SET | \ + OR_GPCM_EHTR_CLEAR | \ + OR_GPCM_EAD) + +/* + * MMU Setup + */ +/* APP1: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT5L (CONFIG_SYS_APP1_BASE | \ + BATL_PP_RW | \ + BATL_MEMCOHERENCE) +/* 512M should also include APP2... */ +#define CONFIG_SYS_IBAT5U (CONFIG_SYS_APP1_BASE | \ + BATU_BL_256M | \ + BATU_VS | \ + BATU_VP) +#define CONFIG_SYS_DBAT5L (CONFIG_SYS_APP1_BASE | \ + BATL_PP_RW | \ + BATL_CACHEINHIBIT | \ + BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U + +#define CONFIG_SYS_IBAT6L (0) +#define CONFIG_SYS_IBAT6U (0) +#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L +#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U + +#define CONFIG_SYS_IBAT7L (0) +#define CONFIG_SYS_IBAT7U (0) +#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L +#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U + +#endif /* __CONFIG_H */ diff --git a/include/configs/kmtepr2.h b/include/configs/kmtepr2.h new file mode 100644 index 0000000000..f3504e5a81 --- /dev/null +++ b/include/configs/kmtepr2.h @@ -0,0 +1,235 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2006 Freescale Semiconductor, Inc. + * Dave Liu + * + * Copyright (C) 2007 Logic Product Development, Inc. + * Peter Barada + * + * Copyright (C) 2007 MontaVista Software, Inc. + * Anton Vorontsov + * + * (C) Copyright 2008 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * (C) Copyright 2010-2013 + * Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com + * Holger Brunck, Keymile GmbH, holger.bruncl@keymile.com + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_KM_BOARD_NAME "kmtepr2" +#define CONFIG_HOSTNAME "kmtepr2" + +/* + * High Level Configuration Options + */ +#define CONFIG_QE /* Has QE */ +#define CONFIG_KM8321 /* Keymile PBEC8321 board specific */ + +#define CONFIG_KM_DEF_ARCH "arch=ppc_8xx\0" + +/* include common defines/options for all 83xx Keymile boards */ +#include "km83xx-common.h" + +/* + * System IO Config + */ +#define CONFIG_SYS_SICRL SICRL_IRQ_CKS + +/* + * Hardware Reset Configuration Word + */ +#define CONFIG_SYS_HRCW_LOW (\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \ + HRCWL_DDR_TO_SCB_CLK_2X1 | \ + HRCWL_CSB_TO_CLKIN_2X1 | \ + HRCWL_CORE_TO_CSB_2_5X1 | \ + HRCWL_CE_PLL_VCO_DIV_2 | \ + HRCWL_CE_TO_PLL_1X3) + +#define CONFIG_SYS_HRCW_HIGH (\ + HRCWH_PCI_AGENT | \ + HRCWH_PCI_ARBITER_DISABLE | \ + HRCWH_CORE_ENABLE | \ + HRCWH_FROM_0X00000100 | \ + HRCWH_BOOTSEQ_DISABLE | \ + HRCWH_SW_WATCHDOG_DISABLE | \ + HRCWH_ROM_LOC_LOCAL_16BIT | \ + HRCWH_BIG_ENDIAN | \ + HRCWH_LALE_NORMAL) + +#define CONFIG_SYS_DDRCDR (\ + DDRCDR_EN | \ + DDRCDR_PZ_MAXZ | \ + DDRCDR_NZ_MAXZ | \ + DDRCDR_M_ODR) + +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f +#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ + SDRAM_CFG_32_BE | \ + SDRAM_CFG_SREN | \ + SDRAM_CFG_HSE) + +#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 +#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) +#define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ + (0x200 << SDRAM_INTERVAL_REFINT_SHIFT)) + +#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ + CSCONFIG_ODT_WR_CFG | \ + CSCONFIG_ROW_BIT_13 | \ + CSCONFIG_COL_BIT_10) + +#define CONFIG_SYS_DDR_MODE 0x47860242 +#define CONFIG_SYS_DDR_MODE2 0x8080c000 + +#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ + (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ + (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ + (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ + (0 << TIMING_CFG0_WWT_SHIFT) | \ + (0 << TIMING_CFG0_RRT_SHIFT) | \ + (0 << TIMING_CFG0_WRT_SHIFT) | \ + (0 << TIMING_CFG0_RWT_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \ + (2 << TIMING_CFG1_WRTORD_SHIFT) | \ + (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ + (3 << TIMING_CFG1_WRREC_SHIFT) | \ + (7 << TIMING_CFG1_REFREC_SHIFT) | \ + (3 << TIMING_CFG1_ACTTORW_SHIFT) | \ + (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ + (3 << TIMING_CFG1_PRETOACT_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ + (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ + (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ + (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ + (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ + (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \ + (5 << TIMING_CFG2_CPO_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_3 0x00000000 + +#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000 +#define CONFIG_SYS_KMBEC_FPGA_SIZE 128 + +/* EEprom support */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 + +/* + * Local Bus Configuration & Clock Setup + */ +#define CONFIG_SYS_LCRR_DBYP 0x80000000 +#define CONFIG_SYS_LCRR_EADC 0x00010000 +#define CONFIG_SYS_LCRR_CLKDIV 0x00000002 + +#define CONFIG_SYS_LBC_LBCR 0x00000000 + +/* + * MMU Setup + */ +#define CONFIG_SYS_IBAT7L (0) +#define CONFIG_SYS_IBAT7U (0) +#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L +#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U + +#define CONFIG_SYS_APP1_BASE 0xA0000000 /* PAXG */ +#define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ +#define CONFIG_SYS_APP2_BASE 0xB0000000 /* PINC3 */ +#define CONFIG_SYS_APP2_SIZE 256 /* Megabytes */ + +/* + * Init Local Bus Memory Controller: + * Device on board + * Bank Bus Machine PortSz Size TUDA1 TUXA1 TUGE1 KMSUPX4 KMOPTI2 + * ----------------------------------------------------------------------------- + * 2 Local GPCM 8 bit 256MB PAXG LPXF PAXI LPXF PAXE + * 3 Local GPCM 8 bit 256MB PINC3 PINC2 unused unused OPI2(16 bit) + * + * Device on board (continued) + * Bank Bus Machine PortSz Size KMTEPR2 + * ----------------------------------------------------------------------------- + * 2 Local GPCM 8 bit 256MB NVRAM + * 3 Local GPCM 8 bit 256MB TEP2 (16 bit) + */ + +/* + * Configuration for C2 on the local bus + */ +/* Window base at flash base */ +#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_APP1_BASE +/* Window size: 256 MB */ +#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) + +#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_APP1_BASE | \ + BR_PS_8 | \ + BR_MS_GPCM | \ + BR_V) + +#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_APP1_SIZE) | \ + OR_GPCM_CSNT | \ + OR_GPCM_ACS_DIV4 | \ + OR_GPCM_SCY_2 | \ + OR_GPCM_TRLX_SET | \ + OR_GPCM_EHTR_CLEAR | \ + OR_GPCM_EAD) + +/* + * Configuration for C3 on the local bus + */ +#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_APP2_BASE +#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) +#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_APP2_BASE | \ + BR_PS_16 | \ + BR_MS_GPCM | \ + BR_V) +#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \ + OR_GPCM_SCY_4 | \ + OR_GPCM_TRLX_CLEAR | \ + OR_GPCM_EHTR_CLEAR) + +/* + * MMU Setup + */ +/* APP1: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT5L (CONFIG_SYS_APP1_BASE | \ + BATL_PP_RW | \ + BATL_MEMCOHERENCE) +/* 512M should also include APP2... */ +#define CONFIG_SYS_IBAT5U (CONFIG_SYS_APP1_BASE | \ + BATU_BL_256M | \ + BATU_VS | \ + BATU_VP) +#define CONFIG_SYS_DBAT5L (CONFIG_SYS_APP1_BASE | \ + BATL_PP_RW | \ + BATL_CACHEINHIBIT | \ + BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U + +/* APP2: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT6L (CONFIG_SYS_APP2_BASE | \ + BATL_PP_RW | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT6U (CONFIG_SYS_APP2_BASE | \ + BATU_BL_256M | \ + BATU_VS | \ + BATU_VP) +#define CONFIG_SYS_DBAT6L (CONFIG_SYS_APP2_BASE | \ + BATL_PP_RW | \ + BATL_CACHEINHIBIT | \ + BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U + +#define CONFIG_SYS_IBAT7L (0) +#define CONFIG_SYS_IBAT7U (0) +#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L +#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U + +#endif /* __CONFIG_H */ diff --git a/include/configs/tuge1.h b/include/configs/tuge1.h new file mode 100644 index 0000000000..85f8e9cd30 --- /dev/null +++ b/include/configs/tuge1.h @@ -0,0 +1,210 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2006 Freescale Semiconductor, Inc. + * Dave Liu + * + * Copyright (C) 2007 Logic Product Development, Inc. + * Peter Barada + * + * Copyright (C) 2007 MontaVista Software, Inc. + * Anton Vorontsov + * + * (C) Copyright 2008 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * (C) Copyright 2010-2013 + * Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com + * Holger Brunck, Keymile GmbH, holger.bruncl@keymile.com + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_KM_BOARD_NAME "tuge1" +#define CONFIG_HOSTNAME "tuge1" + +/* + * High Level Configuration Options + */ +#define CONFIG_QE /* Has QE */ +#define CONFIG_KM8321 /* Keymile PBEC8321 board specific */ + +#define CONFIG_KM_DEF_ARCH "arch=ppc_8xx\0" + +/* include common defines/options for all 83xx Keymile boards */ +#include "km83xx-common.h" + +/* + * System IO Config + */ +#define CONFIG_SYS_SICRL SICRL_IRQ_CKS + +/* + * Hardware Reset Configuration Word + */ +#define CONFIG_SYS_HRCW_LOW (\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \ + HRCWL_DDR_TO_SCB_CLK_2X1 | \ + HRCWL_CSB_TO_CLKIN_2X1 | \ + HRCWL_CORE_TO_CSB_2_5X1 | \ + HRCWL_CE_PLL_VCO_DIV_2 | \ + HRCWL_CE_TO_PLL_1X3) + +#define CONFIG_SYS_HRCW_HIGH (\ + HRCWH_PCI_AGENT | \ + HRCWH_PCI_ARBITER_DISABLE | \ + HRCWH_CORE_ENABLE | \ + HRCWH_FROM_0X00000100 | \ + HRCWH_BOOTSEQ_DISABLE | \ + HRCWH_SW_WATCHDOG_DISABLE | \ + HRCWH_ROM_LOC_LOCAL_16BIT | \ + HRCWH_BIG_ENDIAN | \ + HRCWH_LALE_NORMAL) + +#define CONFIG_SYS_DDRCDR (\ + DDRCDR_EN | \ + DDRCDR_PZ_MAXZ | \ + DDRCDR_NZ_MAXZ | \ + DDRCDR_M_ODR) + +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f +#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ + SDRAM_CFG_32_BE | \ + SDRAM_CFG_SREN | \ + SDRAM_CFG_HSE) + +#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 +#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) +#define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ + (0x200 << SDRAM_INTERVAL_REFINT_SHIFT)) + +#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ + CSCONFIG_ODT_WR_CFG | \ + CSCONFIG_ROW_BIT_13 | \ + CSCONFIG_COL_BIT_10) + +#define CONFIG_SYS_DDR_MODE 0x47860242 +#define CONFIG_SYS_DDR_MODE2 0x8080c000 + +#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ + (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ + (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ + (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ + (0 << TIMING_CFG0_WWT_SHIFT) | \ + (0 << TIMING_CFG0_RRT_SHIFT) | \ + (0 << TIMING_CFG0_WRT_SHIFT) | \ + (0 << TIMING_CFG0_RWT_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \ + (2 << TIMING_CFG1_WRTORD_SHIFT) | \ + (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ + (3 << TIMING_CFG1_WRREC_SHIFT) | \ + (7 << TIMING_CFG1_REFREC_SHIFT) | \ + (3 << TIMING_CFG1_ACTTORW_SHIFT) | \ + (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ + (3 << TIMING_CFG1_PRETOACT_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ + (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ + (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ + (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ + (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ + (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \ + (5 << TIMING_CFG2_CPO_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_3 0x00000000 + +#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000 +#define CONFIG_SYS_KMBEC_FPGA_SIZE 128 + +/* EEprom support */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 + +/* + * Local Bus Configuration & Clock Setup + */ +#define CONFIG_SYS_LCRR_DBYP 0x80000000 +#define CONFIG_SYS_LCRR_EADC 0x00010000 +#define CONFIG_SYS_LCRR_CLKDIV 0x00000002 + +#define CONFIG_SYS_LBC_LBCR 0x00000000 + +/* + * MMU Setup + */ +#define CONFIG_SYS_IBAT7L (0) +#define CONFIG_SYS_IBAT7U (0) +#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L +#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U + +#define CONFIG_SYS_APP1_BASE 0xA0000000 /* PAXG */ +#define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ + +/* + * Init Local Bus Memory Controller: + * Device on board + * Bank Bus Machine PortSz Size TUDA1 TUXA1 TUGE1 KMSUPX4 KMOPTI2 + * ----------------------------------------------------------------------------- + * 2 Local GPCM 8 bit 256MB PAXG LPXF PAXI LPXF PAXE + * 3 Local GPCM 8 bit 256MB PINC3 PINC2 unused unused OPI2(16 bit) + * + * Device on board (continued) + * Bank Bus Machine PortSz Size KMTEPR2 + * ----------------------------------------------------------------------------- + * 2 Local GPCM 8 bit 256MB NVRAM + * 3 Local GPCM 8 bit 256MB TEP2 (16 bit) + */ + +/* + * Configuration for C2 on the local bus + */ +/* Window base at flash base */ +#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_APP1_BASE +/* Window size: 256 MB */ +#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) + +#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_APP1_BASE | \ + BR_PS_8 | \ + BR_MS_GPCM | \ + BR_V) + +#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_APP1_SIZE) | \ + OR_GPCM_CSNT | \ + OR_GPCM_ACS_DIV4 | \ + OR_GPCM_SCY_2 | \ + OR_GPCM_TRLX_SET | \ + OR_GPCM_EHTR_CLEAR | \ + OR_GPCM_EAD) + +/* + * MMU Setup + */ +/* APP1: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT5L (CONFIG_SYS_APP1_BASE | \ + BATL_PP_RW | \ + BATL_MEMCOHERENCE) +/* 512M should also include APP2... */ +#define CONFIG_SYS_IBAT5U (CONFIG_SYS_APP1_BASE | \ + BATU_BL_256M | \ + BATU_VS | \ + BATU_VP) +#define CONFIG_SYS_DBAT5L (CONFIG_SYS_APP1_BASE | \ + BATL_PP_RW | \ + BATL_CACHEINHIBIT | \ + BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U + +#define CONFIG_SYS_IBAT6L (0) +#define CONFIG_SYS_IBAT6U (0) +#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L +#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U + +#define CONFIG_SYS_IBAT7L (0) +#define CONFIG_SYS_IBAT7U (0) +#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L +#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U + +#endif /* __CONFIG_H */ diff --git a/include/configs/tuxx1.h b/include/configs/tuxx1.h index c031661830..b42221a430 100644 --- a/include/configs/tuxx1.h +++ b/include/configs/tuxx1.h @@ -23,24 +23,8 @@ /* * High Level Configuration Options */ -#if defined(CONFIG_KMSUPX5) -#define CONFIG_KM_BOARD_NAME "kmsupx5" -#define CONFIG_HOSTNAME "kmsupx5" -#elif defined(CONFIG_TUGE1) -#define CONFIG_KM_BOARD_NAME "tuge1" -#define CONFIG_HOSTNAME "tuge1" -#elif defined(CONFIG_TUXX1) /* TUXX1 board (tuxa1/tuda1) specific */ #define CONFIG_KM_BOARD_NAME "tuxx1" #define CONFIG_HOSTNAME "tuxx1" -#elif defined(CONFIG_KMOPTI2) -#define CONFIG_KM_BOARD_NAME "kmopti2" -#define CONFIG_HOSTNAME "kmopti2" -#elif defined(CONFIG_KMTEPR2) -#define CONFIG_KM_BOARD_NAME "kmtepr2" -#define CONFIG_HOSTNAME "kmtepr2" -#else -#error ("Board not supported") -#endif /* * High Level Configuration Options @@ -158,10 +142,8 @@ #define CONFIG_SYS_APP1_BASE 0xA0000000 /* PAXG */ #define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ -#if defined(CONFIG_TUXX1) || defined(CONFIG_KMOPTI2) || defined(CONFIG_KMTEPR2) #define CONFIG_SYS_APP2_BASE 0xB0000000 /* PINC3 */ #define CONFIG_SYS_APP2_SIZE 256 /* Megabytes */ -#endif /* * Init Local Bus Memory Controller: @@ -178,25 +160,6 @@ * 3 Local GPCM 8 bit 256MB TEP2 (16 bit) */ -#if defined(CONFIG_KMTEPRO2) -/* - * Configuration for C2 (NVRAM) on the local bus - */ -#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_APP1_BASE -#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) -#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_APP1_BASE | \ - BR_PS_8 | \ - BR_MS_GPCM | \ - BR_V) -#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_APP1_SIZE) | \ - OR_GPCM_CSNT | \ - OR_GPCM_ACS_DIV2 | \ - OR_GPCM_XACS | \ - OR_GPCM_SCY_2 | \ - OR_GPCM_TRLX_SET | \ - OR_GPCM_EHTR_SET | \ - OR_GPCM_EAD) -#else /* * Configuration for C2 on the local bus */ @@ -217,9 +180,7 @@ OR_GPCM_TRLX_SET | \ OR_GPCM_EHTR_CLEAR | \ OR_GPCM_EAD) -#endif -#if defined(CONFIG_TUXX1) /* * Configuration for C3 on the local bus */ @@ -243,23 +204,6 @@ #define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \ 0x0000c000 | \ MxMR_WLFx_2X) -#endif - -#if defined(CONFIG_KMOPTI2) || defined(CONFIG_KMTEPR2) -/* - * Configuration for C3 on the local bus - */ -#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_APP2_BASE -#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) -#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_APP2_BASE | \ - BR_PS_16 | \ - BR_MS_GPCM | \ - BR_V) -#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \ - OR_GPCM_SCY_4 | \ - OR_GPCM_TRLX_CLEAR | \ - OR_GPCM_EHTR_CLEAR) -#endif /* * MMU Setup @@ -279,11 +223,6 @@ BATL_GUARDEDSTORAGE) #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U -#if defined(CONFIG_TUGE1) || defined(CONFIG_KMSUPX5) -#define CONFIG_SYS_IBAT6L (0) -#define CONFIG_SYS_IBAT6U (0) -#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L -#else /* APP2: icache cacheable, but dcache-inhibit and guarded */ #define CONFIG_SYS_IBAT6L (CONFIG_SYS_APP2_BASE | \ BATL_PP_RW | \ @@ -296,7 +235,6 @@ BATL_PP_RW | \ BATL_CACHEINHIBIT | \ BATL_GUARDEDSTORAGE) -#endif #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U #define CONFIG_SYS_IBAT7L (0) From fb1b099f109826532f589a152c7cdf418090e5f8 Mon Sep 17 00:00:00 2001 From: Mario Six Date: Mon, 21 Jan 2019 09:17:34 +0100 Subject: [PATCH 11/86] keymile: Unroll km/km83xx-common.h Simplify the keymile config files once more by unrolling the km/km83xx-common.h, and resolve the #ifdef logic as needed. Signed-off-by: Mario Six --- include/configs/km8360.h | 287 ++++++++++++++++++++++++++++++- include/configs/km83xx-common.h | 296 -------------------------------- include/configs/kmopti2.h | 285 +++++++++++++++++++++++++++++- include/configs/kmsupx5.h | 285 +++++++++++++++++++++++++++++- include/configs/kmtegr1.h | 284 +++++++++++++++++++++++++++++- include/configs/kmtepr2.h | 285 +++++++++++++++++++++++++++++- include/configs/kmvect1.h | 284 +++++++++++++++++++++++++++++- include/configs/suvd3.h | 287 ++++++++++++++++++++++++++++++- include/configs/tuge1.h | 285 +++++++++++++++++++++++++++++- include/configs/tuxx1.h | 285 +++++++++++++++++++++++++++++- 10 files changed, 2543 insertions(+), 320 deletions(-) delete mode 100644 include/configs/km83xx-common.h diff --git a/include/configs/km8360.h b/include/configs/km8360.h index 08d2ae0cbc..3e25b3988b 100644 --- a/include/configs/km8360.h +++ b/include/configs/km8360.h @@ -37,8 +37,291 @@ */ #define CONFIG_QE /* Has QE */ -/* include common defines/options for all 83xx Keymile boards */ -#include "km83xx-common.h" +/* include common defines/options for all Keymile boards */ +#include "km/keymile-common.h" +#include "km/km-powerpc.h" + +/* + * System Clock Setup + */ +#define CONFIG_83XX_CLKIN 66000000 +#define CONFIG_SYS_CLK_FREQ 66000000 +#define CONFIG_83XX_PCICLK 66000000 + +/* + * IMMR new address + */ +#define CONFIG_SYS_IMMR 0xE0000000 + +/* + * Bus Arbitration Configuration Register (ACR) + */ +#define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */ +#define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */ +#define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */ +#define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */ + +/* + * DDR Setup + */ +#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */ + +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ + DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) + +#define CFG_83XX_DDR_USES_CS0 + +/* + * Manually set up DDR parameters + */ +#define CONFIG_DDR_II +#define CONFIG_SYS_DDR_SIZE 2048 /* MB */ + +/* + * The reserved memory + */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#define CONFIG_SYS_FLASH_BASE 0xF0000000 + +#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) +#define CONFIG_SYS_RAMBOOT +#endif + +/* Reserve 768 kB for Mon */ +#define CONFIG_SYS_MONITOR_LEN (768 * 1024) + +/* + * Initial RAM Base Address Setup + */ +#define CONFIG_SYS_INIT_RAM_LOCK +#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) + +/* + * Init Local Bus Memory Controller: + * + * Bank Bus Machine PortSz Size Device + * ---- --- ------- ------ ----- ------ + * 0 Local GPCM 16 bit 256MB FLASH + * 1 Local GPCM 8 bit 128MB GPIO/PIGGY + * + */ +/* + * FLASH on the Local Bus + */ +#define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ + +#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) + +#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ + BR_PS_16 | /* 16 bit port size */ \ + BR_MS_GPCM | /* MSEL = GPCM */ \ + BR_V) + +#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \ + OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ + OR_GPCM_SCY_5 | \ + OR_GPCM_TRLX_SET | OR_GPCM_EAD) + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } + +/* + * PRIO1/PIGGY on the local bus CS1 + */ +/* Window base at flash base */ +#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_KMBEC_FPGA_BASE +#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128MB) + +#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_KMBEC_FPGA_BASE | \ + BR_PS_8 | /* 8 bit port size */ \ + BR_MS_GPCM | /* MSEL = GPCM */ \ + BR_V) +#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \ + OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ + OR_GPCM_SCY_2 | \ + OR_GPCM_TRLX_SET | OR_GPCM_EAD) + +/* + * Serial Port + */ +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) + +/* + * QE UEC ethernet configuration + */ +#define CONFIG_UEC_ETH +#define CONFIG_ETHPRIME "UEC0" + +#if !defined(CONFIG_ARCH_MPC8309) +#define CONFIG_UEC_ETH1 /* GETH1 */ +#define UEC_VERBOSE_DEBUG 1 +#endif + +#ifdef CONFIG_UEC_ETH1 +#define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */ +#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ +#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17 +#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH +#define CONFIG_SYS_UEC1_PHY_ADDR 0 +#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII +#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 +#endif + +/* + * Environment + */ + +#ifndef CONFIG_SYS_RAMBOOT +#ifndef CONFIG_ENV_ADDR +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ + CONFIG_SYS_MONITOR_LEN) +#endif +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ +#ifndef CONFIG_ENV_OFFSET +#define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN) +#endif + +/* Address and size of Redundant Environment Sector */ +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ + CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) + +#else /* CFG_SYS_RAMBOOT */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) +#define CONFIG_ENV_SIZE 0x2000 +#endif /* CFG_SYS_RAMBOOT */ + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_NUM_I2C_BUSES 4 +#define CONFIG_SYS_I2C_MAX_HOPS 1 +#define CONFIG_SYS_I2C_FSL +#define CONFIG_SYS_FSL_I2C_SPEED 200000 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C_OFFSET 0x3000 +#define CONFIG_SYS_FSL_I2C2_SPEED 200000 +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 +#define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \ + {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \ + {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \ + {1, {I2C_NULL_HOP} } } + +#define CONFIG_KM_IVM_BUS 2 /* I2C2 (Mux-Port 1)*/ + +#if defined(CONFIG_CMD_NAND) +#define CONFIG_NAND_KMETER1 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE +#endif + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) + +/* + * Core HID Setup + */ +#define CONFIG_SYS_HID0_INIT 0x000000000 +#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ + HID0_ENABLE_INSTRUCTION_CACHE) +#define CONFIG_SYS_HID2 HID2_HBE + +/* + * MMU Setup + */ + +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + +/* DDR: cache cacheable */ +#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L +#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U + +/* IMMRBAR & PCI IO: cache-inhibit and guarded */ +#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS \ + | BATU_VP) +#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L +#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U + +/* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT2U (CONFIG_SYS_KMBEC_FPGA_BASE | BATU_BL_128M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U + +/* FLASH: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U + +/* Stack in dcache: cacheable, no memory coherence */ +#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) +#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L +#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U + +/* + * Internal Definitions + */ +#define BOOTFLASH_START 0xF0000000 + +#define CONFIG_KM_CONSOLE_TTY "ttyS0" + +/* + * Environment Configuration + */ +#define CONFIG_ENV_OVERWRITE +#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ +#define CONFIG_KM_DEF_ENV "km-common=empty\0" +#endif + +#ifndef CONFIG_KM_DEF_ARCH +#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_KM_DEF_ENV \ + CONFIG_KM_DEF_ARCH \ + "newenv=" \ + "prot off "__stringify(CONFIG_ENV_ADDR)" +0x40000 && " \ + "era "__stringify(CONFIG_ENV_ADDR)" +0x40000\0" \ + "unlock=yes\0" \ + "" + +#if defined(CONFIG_UEC_ETH) +#define CONFIG_HAS_ETH0 +#endif /* * System IO Setup diff --git a/include/configs/km83xx-common.h b/include/configs/km83xx-common.h deleted file mode 100644 index c80169c9b6..0000000000 --- a/include/configs/km83xx-common.h +++ /dev/null @@ -1,296 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - */ - -#ifndef __CONFIG_KM83XX_H -#define __CONFIG_KM83XX_H - -/* include common defines/options for all Keymile boards */ -#include "km/keymile-common.h" -#include "km/km-powerpc.h" - -/* - * System Clock Setup - */ -#define CONFIG_83XX_CLKIN 66000000 -#define CONFIG_SYS_CLK_FREQ 66000000 -#define CONFIG_83XX_PCICLK 66000000 - -/* - * IMMR new address - */ -#define CONFIG_SYS_IMMR 0xE0000000 - -/* - * Bus Arbitration Configuration Register (ACR) - */ -#define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */ -#define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */ -#define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */ -#define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */ - -/* - * DDR Setup - */ -#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */ - -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ - DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) - -#define CFG_83XX_DDR_USES_CS0 - -/* - * Manually set up DDR parameters - */ -#define CONFIG_DDR_II -#define CONFIG_SYS_DDR_SIZE 2048 /* MB */ - -/* - * The reserved memory - */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ -#define CONFIG_SYS_FLASH_BASE 0xF0000000 - -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT -#endif - -/* Reserve 768 kB for Mon */ -#define CONFIG_SYS_MONITOR_LEN (768 * 1024) - -/* - * Initial RAM Base Address Setup - */ -#define CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) - -/* - * Init Local Bus Memory Controller: - * - * Bank Bus Machine PortSz Size Device - * ---- --- ------- ------ ----- ------ - * 0 Local GPCM 16 bit 256MB FLASH - * 1 Local GPCM 8 bit 128MB GPIO/PIGGY - * - */ -/* - * FLASH on the Local Bus - */ -#define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ - -#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) - -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ - BR_PS_16 | /* 16 bit port size */ \ - BR_MS_GPCM | /* MSEL = GPCM */ \ - BR_V) - -#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \ - OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ - OR_GPCM_SCY_5 | \ - OR_GPCM_TRLX_SET | OR_GPCM_EAD) - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } - -/* - * PRIO1/PIGGY on the local bus CS1 - */ -/* Window base at flash base */ -#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_KMBEC_FPGA_BASE -#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128MB) - -#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_KMBEC_FPGA_BASE | \ - BR_PS_8 | /* 8 bit port size */ \ - BR_MS_GPCM | /* MSEL = GPCM */ \ - BR_V) -#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \ - OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ - OR_GPCM_SCY_2 | \ - OR_GPCM_TRLX_SET | OR_GPCM_EAD) - -/* - * Serial Port - */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) - -/* - * QE UEC ethernet configuration - */ -#define CONFIG_UEC_ETH -#define CONFIG_ETHPRIME "UEC0" - -#if !defined(CONFIG_ARCH_MPC8309) -#define CONFIG_UEC_ETH1 /* GETH1 */ -#define UEC_VERBOSE_DEBUG 1 -#endif - -#ifdef CONFIG_UEC_ETH1 -#define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */ -#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ -#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17 -#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH -#define CONFIG_SYS_UEC1_PHY_ADDR 0 -#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII -#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 -#endif - -/* - * Environment - */ - -#ifndef CONFIG_SYS_RAMBOOT -#ifndef CONFIG_ENV_ADDR -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ - CONFIG_SYS_MONITOR_LEN) -#endif -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ -#ifndef CONFIG_ENV_OFFSET -#define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN) -#endif - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#else /* CFG_SYS_RAMBOOT */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) -#define CONFIG_ENV_SIZE 0x2000 -#endif /* CFG_SYS_RAMBOOT */ - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_NUM_I2C_BUSES 4 -#define CONFIG_SYS_I2C_MAX_HOPS 1 -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 200000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_I2C_OFFSET 0x3000 -#define CONFIG_SYS_FSL_I2C2_SPEED 200000 -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 -#define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \ - {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \ - {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \ - {1, {I2C_NULL_HOP} } } - -#define CONFIG_KM_IVM_BUS 2 /* I2C2 (Mux-Port 1)*/ - -#if defined(CONFIG_CMD_NAND) -#define CONFIG_NAND_KMETER1 -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE -#endif - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) - -/* - * Core HID Setup - */ -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ - HID0_ENABLE_INSTRUCTION_CACHE) -#define CONFIG_SYS_HID2 HID2_HBE - -/* - * MMU Setup - */ - -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - -/* DDR: cache cacheable */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U - -/* IMMRBAR & PCI IO: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U - -/* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_KMBEC_FPGA_BASE | BATU_BL_128M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U - -/* FLASH: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -/* Stack in dcache: cacheable, no memory coherence */ -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) -#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L -#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U - -/* - * Internal Definitions - */ -#define BOOTFLASH_START 0xF0000000 - -#define CONFIG_KM_CONSOLE_TTY "ttyS0" - -/* - * Environment Configuration - */ -#define CONFIG_ENV_OVERWRITE -#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ -#define CONFIG_KM_DEF_ENV "km-common=empty\0" -#endif - -#ifndef CONFIG_KM_DEF_ARCH -#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" -#endif - -#define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_KM_DEF_ENV \ - CONFIG_KM_DEF_ARCH \ - "newenv=" \ - "prot off "__stringify(CONFIG_ENV_ADDR)" +0x40000 && " \ - "era "__stringify(CONFIG_ENV_ADDR)" +0x40000\0" \ - "unlock=yes\0" \ - "" - -#if defined(CONFIG_UEC_ETH) -#define CONFIG_HAS_ETH0 -#endif - -#endif /* __CONFIG_KM83XX_H */ diff --git a/include/configs/kmopti2.h b/include/configs/kmopti2.h index 0621be3928..fa12d41080 100644 --- a/include/configs/kmopti2.h +++ b/include/configs/kmopti2.h @@ -34,8 +34,289 @@ #define CONFIG_KM_DEF_ARCH "arch=ppc_8xx\0" -/* include common defines/options for all 83xx Keymile boards */ -#include "km83xx-common.h" +/* include common defines/options for all Keymile boards */ +#include "km/keymile-common.h" +#include "km/km-powerpc.h" + +/* + * System Clock Setup + */ +#define CONFIG_83XX_CLKIN 66000000 +#define CONFIG_SYS_CLK_FREQ 66000000 +#define CONFIG_83XX_PCICLK 66000000 + +/* + * IMMR new address + */ +#define CONFIG_SYS_IMMR 0xE0000000 + +/* + * Bus Arbitration Configuration Register (ACR) + */ +#define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */ +#define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */ +#define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */ +#define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */ + +/* + * DDR Setup + */ +#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */ + +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ + DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) + +#define CFG_83XX_DDR_USES_CS0 + +/* + * Manually set up DDR parameters + */ +#define CONFIG_DDR_II +#define CONFIG_SYS_DDR_SIZE 2048 /* MB */ + +/* + * The reserved memory + */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#define CONFIG_SYS_FLASH_BASE 0xF0000000 + +#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) +#define CONFIG_SYS_RAMBOOT +#endif + +/* Reserve 768 kB for Mon */ +#define CONFIG_SYS_MONITOR_LEN (768 * 1024) + +/* + * Initial RAM Base Address Setup + */ +#define CONFIG_SYS_INIT_RAM_LOCK +#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) + +/* + * Init Local Bus Memory Controller: + * + * Bank Bus Machine PortSz Size Device + * ---- --- ------- ------ ----- ------ + * 0 Local GPCM 16 bit 256MB FLASH + * 1 Local GPCM 8 bit 128MB GPIO/PIGGY + * + */ +/* + * FLASH on the Local Bus + */ +#define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ + +#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) + +#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ + BR_PS_16 | /* 16 bit port size */ \ + BR_MS_GPCM | /* MSEL = GPCM */ \ + BR_V) + +#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \ + OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ + OR_GPCM_SCY_5 | \ + OR_GPCM_TRLX_SET | OR_GPCM_EAD) + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } + +/* + * PRIO1/PIGGY on the local bus CS1 + */ +/* Window base at flash base */ +#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_KMBEC_FPGA_BASE +#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128MB) + +#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_KMBEC_FPGA_BASE | \ + BR_PS_8 | /* 8 bit port size */ \ + BR_MS_GPCM | /* MSEL = GPCM */ \ + BR_V) +#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \ + OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ + OR_GPCM_SCY_2 | \ + OR_GPCM_TRLX_SET | OR_GPCM_EAD) + +/* + * Serial Port + */ +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) + +/* + * QE UEC ethernet configuration + */ +#define CONFIG_UEC_ETH +#define CONFIG_ETHPRIME "UEC0" + +#define CONFIG_UEC_ETH1 /* GETH1 */ +#define UEC_VERBOSE_DEBUG 1 + +#ifdef CONFIG_UEC_ETH1 +#define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */ +#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ +#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17 +#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH +#define CONFIG_SYS_UEC1_PHY_ADDR 0 +#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII +#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 +#endif + +/* + * Environment + */ + +#ifndef CONFIG_SYS_RAMBOOT +#ifndef CONFIG_ENV_ADDR +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ + CONFIG_SYS_MONITOR_LEN) +#endif +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ +#ifndef CONFIG_ENV_OFFSET +#define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN) +#endif + +/* Address and size of Redundant Environment Sector */ +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ + CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) + +#else /* CFG_SYS_RAMBOOT */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) +#define CONFIG_ENV_SIZE 0x2000 +#endif /* CFG_SYS_RAMBOOT */ + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_NUM_I2C_BUSES 4 +#define CONFIG_SYS_I2C_MAX_HOPS 1 +#define CONFIG_SYS_I2C_FSL +#define CONFIG_SYS_FSL_I2C_SPEED 200000 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C_OFFSET 0x3000 +#define CONFIG_SYS_FSL_I2C2_SPEED 200000 +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 +#define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \ + {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \ + {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \ + {1, {I2C_NULL_HOP} } } + +#define CONFIG_KM_IVM_BUS 2 /* I2C2 (Mux-Port 1)*/ + +#if defined(CONFIG_CMD_NAND) +#define CONFIG_NAND_KMETER1 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE +#endif + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) + +/* + * Core HID Setup + */ +#define CONFIG_SYS_HID0_INIT 0x000000000 +#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ + HID0_ENABLE_INSTRUCTION_CACHE) +#define CONFIG_SYS_HID2 HID2_HBE + +/* + * MMU Setup + */ + +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + +/* DDR: cache cacheable */ +#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L +#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U + +/* IMMRBAR & PCI IO: cache-inhibit and guarded */ +#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS \ + | BATU_VP) +#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L +#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U + +/* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT2U (CONFIG_SYS_KMBEC_FPGA_BASE | BATU_BL_128M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U + +/* FLASH: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U + +/* Stack in dcache: cacheable, no memory coherence */ +#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) +#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L +#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U + +/* + * Internal Definitions + */ +#define BOOTFLASH_START 0xF0000000 + +#define CONFIG_KM_CONSOLE_TTY "ttyS0" + +/* + * Environment Configuration + */ +#define CONFIG_ENV_OVERWRITE +#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ +#define CONFIG_KM_DEF_ENV "km-common=empty\0" +#endif + +#ifndef CONFIG_KM_DEF_ARCH +#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_KM_DEF_ENV \ + CONFIG_KM_DEF_ARCH \ + "newenv=" \ + "prot off "__stringify(CONFIG_ENV_ADDR)" +0x40000 && " \ + "era "__stringify(CONFIG_ENV_ADDR)" +0x40000\0" \ + "unlock=yes\0" \ + "" + +#if defined(CONFIG_UEC_ETH) +#define CONFIG_HAS_ETH0 +#endif /* * System IO Config diff --git a/include/configs/kmsupx5.h b/include/configs/kmsupx5.h index be93b7ce89..30898c0b75 100644 --- a/include/configs/kmsupx5.h +++ b/include/configs/kmsupx5.h @@ -34,8 +34,289 @@ #define CONFIG_KM_DEF_ARCH "arch=ppc_8xx\0" -/* include common defines/options for all 83xx Keymile boards */ -#include "km83xx-common.h" +/* include common defines/options for all Keymile boards */ +#include "km/keymile-common.h" +#include "km/km-powerpc.h" + +/* + * System Clock Setup + */ +#define CONFIG_83XX_CLKIN 66000000 +#define CONFIG_SYS_CLK_FREQ 66000000 +#define CONFIG_83XX_PCICLK 66000000 + +/* + * IMMR new address + */ +#define CONFIG_SYS_IMMR 0xE0000000 + +/* + * Bus Arbitration Configuration Register (ACR) + */ +#define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */ +#define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */ +#define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */ +#define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */ + +/* + * DDR Setup + */ +#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */ + +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ + DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) + +#define CFG_83XX_DDR_USES_CS0 + +/* + * Manually set up DDR parameters + */ +#define CONFIG_DDR_II +#define CONFIG_SYS_DDR_SIZE 2048 /* MB */ + +/* + * The reserved memory + */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#define CONFIG_SYS_FLASH_BASE 0xF0000000 + +#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) +#define CONFIG_SYS_RAMBOOT +#endif + +/* Reserve 768 kB for Mon */ +#define CONFIG_SYS_MONITOR_LEN (768 * 1024) + +/* + * Initial RAM Base Address Setup + */ +#define CONFIG_SYS_INIT_RAM_LOCK +#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) + +/* + * Init Local Bus Memory Controller: + * + * Bank Bus Machine PortSz Size Device + * ---- --- ------- ------ ----- ------ + * 0 Local GPCM 16 bit 256MB FLASH + * 1 Local GPCM 8 bit 128MB GPIO/PIGGY + * + */ +/* + * FLASH on the Local Bus + */ +#define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ + +#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) + +#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ + BR_PS_16 | /* 16 bit port size */ \ + BR_MS_GPCM | /* MSEL = GPCM */ \ + BR_V) + +#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \ + OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ + OR_GPCM_SCY_5 | \ + OR_GPCM_TRLX_SET | OR_GPCM_EAD) + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } + +/* + * PRIO1/PIGGY on the local bus CS1 + */ +/* Window base at flash base */ +#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_KMBEC_FPGA_BASE +#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128MB) + +#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_KMBEC_FPGA_BASE | \ + BR_PS_8 | /* 8 bit port size */ \ + BR_MS_GPCM | /* MSEL = GPCM */ \ + BR_V) +#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \ + OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ + OR_GPCM_SCY_2 | \ + OR_GPCM_TRLX_SET | OR_GPCM_EAD) + +/* + * Serial Port + */ +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) + +/* + * QE UEC ethernet configuration + */ +#define CONFIG_UEC_ETH +#define CONFIG_ETHPRIME "UEC0" + +#define CONFIG_UEC_ETH1 /* GETH1 */ +#define UEC_VERBOSE_DEBUG 1 + +#ifdef CONFIG_UEC_ETH1 +#define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */ +#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ +#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17 +#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH +#define CONFIG_SYS_UEC1_PHY_ADDR 0 +#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII +#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 +#endif + +/* + * Environment + */ + +#ifndef CONFIG_SYS_RAMBOOT +#ifndef CONFIG_ENV_ADDR +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ + CONFIG_SYS_MONITOR_LEN) +#endif +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ +#ifndef CONFIG_ENV_OFFSET +#define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN) +#endif + +/* Address and size of Redundant Environment Sector */ +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ + CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) + +#else /* CFG_SYS_RAMBOOT */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) +#define CONFIG_ENV_SIZE 0x2000 +#endif /* CFG_SYS_RAMBOOT */ + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_NUM_I2C_BUSES 4 +#define CONFIG_SYS_I2C_MAX_HOPS 1 +#define CONFIG_SYS_I2C_FSL +#define CONFIG_SYS_FSL_I2C_SPEED 200000 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C_OFFSET 0x3000 +#define CONFIG_SYS_FSL_I2C2_SPEED 200000 +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 +#define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \ + {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \ + {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \ + {1, {I2C_NULL_HOP} } } + +#define CONFIG_KM_IVM_BUS 2 /* I2C2 (Mux-Port 1)*/ + +#if defined(CONFIG_CMD_NAND) +#define CONFIG_NAND_KMETER1 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE +#endif + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) + +/* + * Core HID Setup + */ +#define CONFIG_SYS_HID0_INIT 0x000000000 +#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ + HID0_ENABLE_INSTRUCTION_CACHE) +#define CONFIG_SYS_HID2 HID2_HBE + +/* + * MMU Setup + */ + +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + +/* DDR: cache cacheable */ +#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L +#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U + +/* IMMRBAR & PCI IO: cache-inhibit and guarded */ +#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS \ + | BATU_VP) +#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L +#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U + +/* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT2U (CONFIG_SYS_KMBEC_FPGA_BASE | BATU_BL_128M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U + +/* FLASH: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U + +/* Stack in dcache: cacheable, no memory coherence */ +#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) +#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L +#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U + +/* + * Internal Definitions + */ +#define BOOTFLASH_START 0xF0000000 + +#define CONFIG_KM_CONSOLE_TTY "ttyS0" + +/* + * Environment Configuration + */ +#define CONFIG_ENV_OVERWRITE +#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ +#define CONFIG_KM_DEF_ENV "km-common=empty\0" +#endif + +#ifndef CONFIG_KM_DEF_ARCH +#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_KM_DEF_ENV \ + CONFIG_KM_DEF_ARCH \ + "newenv=" \ + "prot off "__stringify(CONFIG_ENV_ADDR)" +0x40000 && " \ + "era "__stringify(CONFIG_ENV_ADDR)" +0x40000\0" \ + "unlock=yes\0" \ + "" + +#if defined(CONFIG_UEC_ETH) +#define CONFIG_HAS_ETH0 +#endif /* * System IO Config diff --git a/include/configs/kmtegr1.h b/include/configs/kmtegr1.h index 27e3905c2b..329a5cfe0f 100644 --- a/include/configs/kmtegr1.h +++ b/include/configs/kmtegr1.h @@ -20,8 +20,6 @@ * High Level Configuration Options */ -/* This needs to be set prior to including km83xx-common.h */ - #define CONFIG_HOSTNAME "kmtegr1" #define CONFIG_KM_BOARD_NAME "kmtegr1" #define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0" @@ -43,8 +41,286 @@ #define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" -/* include common defines/options for all 83xx Keymile boards */ -#include "km83xx-common.h" +/* include common defines/options for all Keymile boards */ +#include "km/keymile-common.h" +#include "km/km-powerpc.h" + +/* + * System Clock Setup + */ +#define CONFIG_83XX_CLKIN 66000000 +#define CONFIG_SYS_CLK_FREQ 66000000 +#define CONFIG_83XX_PCICLK 66000000 + +/* + * IMMR new address + */ +#define CONFIG_SYS_IMMR 0xE0000000 + +/* + * Bus Arbitration Configuration Register (ACR) + */ +#define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */ +#define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */ +#define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */ +#define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */ + +/* + * DDR Setup + */ +#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */ + +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ + DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) + +#define CFG_83XX_DDR_USES_CS0 + +/* + * Manually set up DDR parameters + */ +#define CONFIG_DDR_II +#define CONFIG_SYS_DDR_SIZE 2048 /* MB */ + +/* + * The reserved memory + */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#define CONFIG_SYS_FLASH_BASE 0xF0000000 + +#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) +#define CONFIG_SYS_RAMBOOT +#endif + +/* Reserve 768 kB for Mon */ +#define CONFIG_SYS_MONITOR_LEN (768 * 1024) + +/* + * Initial RAM Base Address Setup + */ +#define CONFIG_SYS_INIT_RAM_LOCK +#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) + +/* + * Init Local Bus Memory Controller: + * + * Bank Bus Machine PortSz Size Device + * ---- --- ------- ------ ----- ------ + * 0 Local GPCM 16 bit 256MB FLASH + * 1 Local GPCM 8 bit 128MB GPIO/PIGGY + * + */ +/* + * FLASH on the Local Bus + */ +#define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ + +#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) + +#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ + BR_PS_16 | /* 16 bit port size */ \ + BR_MS_GPCM | /* MSEL = GPCM */ \ + BR_V) + +#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \ + OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ + OR_GPCM_SCY_5 | \ + OR_GPCM_TRLX_SET | OR_GPCM_EAD) + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } + +/* + * PRIO1/PIGGY on the local bus CS1 + */ +/* Window base at flash base */ +#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_KMBEC_FPGA_BASE +#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128MB) + +#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_KMBEC_FPGA_BASE | \ + BR_PS_8 | /* 8 bit port size */ \ + BR_MS_GPCM | /* MSEL = GPCM */ \ + BR_V) +#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \ + OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ + OR_GPCM_SCY_2 | \ + OR_GPCM_TRLX_SET | OR_GPCM_EAD) + +/* + * Serial Port + */ +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) + +/* + * QE UEC ethernet configuration + */ +#define CONFIG_UEC_ETH +#define CONFIG_ETHPRIME "UEC0" + +#ifdef CONFIG_UEC_ETH1 +#define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */ +#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ +#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17 +#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH +#define CONFIG_SYS_UEC1_PHY_ADDR 0 +#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII +#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 +#endif + +/* + * Environment + */ + +#ifndef CONFIG_SYS_RAMBOOT +#ifndef CONFIG_ENV_ADDR +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ + CONFIG_SYS_MONITOR_LEN) +#endif +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ +#ifndef CONFIG_ENV_OFFSET +#define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN) +#endif + +/* Address and size of Redundant Environment Sector */ +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ + CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) + +#else /* CFG_SYS_RAMBOOT */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) +#define CONFIG_ENV_SIZE 0x2000 +#endif /* CFG_SYS_RAMBOOT */ + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_NUM_I2C_BUSES 4 +#define CONFIG_SYS_I2C_MAX_HOPS 1 +#define CONFIG_SYS_I2C_FSL +#define CONFIG_SYS_FSL_I2C_SPEED 200000 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C_OFFSET 0x3000 +#define CONFIG_SYS_FSL_I2C2_SPEED 200000 +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 +#define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \ + {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \ + {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \ + {1, {I2C_NULL_HOP} } } + +#define CONFIG_KM_IVM_BUS 2 /* I2C2 (Mux-Port 1)*/ + +#if defined(CONFIG_CMD_NAND) +#define CONFIG_NAND_KMETER1 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE +#endif + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) + +/* + * Core HID Setup + */ +#define CONFIG_SYS_HID0_INIT 0x000000000 +#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ + HID0_ENABLE_INSTRUCTION_CACHE) +#define CONFIG_SYS_HID2 HID2_HBE + +/* + * MMU Setup + */ + +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + +/* DDR: cache cacheable */ +#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L +#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U + +/* IMMRBAR & PCI IO: cache-inhibit and guarded */ +#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS \ + | BATU_VP) +#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L +#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U + +/* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT2U (CONFIG_SYS_KMBEC_FPGA_BASE | BATU_BL_128M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U + +/* FLASH: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U + +/* Stack in dcache: cacheable, no memory coherence */ +#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) +#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L +#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U + +/* + * Internal Definitions + */ +#define BOOTFLASH_START 0xF0000000 + +#define CONFIG_KM_CONSOLE_TTY "ttyS0" + +/* + * Environment Configuration + */ +#define CONFIG_ENV_OVERWRITE +#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ +#define CONFIG_KM_DEF_ENV "km-common=empty\0" +#endif + +#ifndef CONFIG_KM_DEF_ARCH +#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_KM_DEF_ENV \ + CONFIG_KM_DEF_ARCH \ + "newenv=" \ + "prot off "__stringify(CONFIG_ENV_ADDR)" +0x40000 && " \ + "era "__stringify(CONFIG_ENV_ADDR)" +0x40000\0" \ + "unlock=yes\0" \ + "" + +#if defined(CONFIG_UEC_ETH) +#define CONFIG_HAS_ETH0 +#endif /* QE microcode/firmware address */ #define CONFIG_SYS_QE_FMAN_FW_IN_NOR diff --git a/include/configs/kmtepr2.h b/include/configs/kmtepr2.h index f3504e5a81..02b72c874e 100644 --- a/include/configs/kmtepr2.h +++ b/include/configs/kmtepr2.h @@ -34,8 +34,289 @@ #define CONFIG_KM_DEF_ARCH "arch=ppc_8xx\0" -/* include common defines/options for all 83xx Keymile boards */ -#include "km83xx-common.h" +/* include common defines/options for all Keymile boards */ +#include "km/keymile-common.h" +#include "km/km-powerpc.h" + +/* + * System Clock Setup + */ +#define CONFIG_83XX_CLKIN 66000000 +#define CONFIG_SYS_CLK_FREQ 66000000 +#define CONFIG_83XX_PCICLK 66000000 + +/* + * IMMR new address + */ +#define CONFIG_SYS_IMMR 0xE0000000 + +/* + * Bus Arbitration Configuration Register (ACR) + */ +#define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */ +#define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */ +#define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */ +#define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */ + +/* + * DDR Setup + */ +#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */ + +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ + DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) + +#define CFG_83XX_DDR_USES_CS0 + +/* + * Manually set up DDR parameters + */ +#define CONFIG_DDR_II +#define CONFIG_SYS_DDR_SIZE 2048 /* MB */ + +/* + * The reserved memory + */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#define CONFIG_SYS_FLASH_BASE 0xF0000000 + +#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) +#define CONFIG_SYS_RAMBOOT +#endif + +/* Reserve 768 kB for Mon */ +#define CONFIG_SYS_MONITOR_LEN (768 * 1024) + +/* + * Initial RAM Base Address Setup + */ +#define CONFIG_SYS_INIT_RAM_LOCK +#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) + +/* + * Init Local Bus Memory Controller: + * + * Bank Bus Machine PortSz Size Device + * ---- --- ------- ------ ----- ------ + * 0 Local GPCM 16 bit 256MB FLASH + * 1 Local GPCM 8 bit 128MB GPIO/PIGGY + * + */ +/* + * FLASH on the Local Bus + */ +#define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ + +#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) + +#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ + BR_PS_16 | /* 16 bit port size */ \ + BR_MS_GPCM | /* MSEL = GPCM */ \ + BR_V) + +#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \ + OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ + OR_GPCM_SCY_5 | \ + OR_GPCM_TRLX_SET | OR_GPCM_EAD) + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } + +/* + * PRIO1/PIGGY on the local bus CS1 + */ +/* Window base at flash base */ +#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_KMBEC_FPGA_BASE +#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128MB) + +#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_KMBEC_FPGA_BASE | \ + BR_PS_8 | /* 8 bit port size */ \ + BR_MS_GPCM | /* MSEL = GPCM */ \ + BR_V) +#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \ + OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ + OR_GPCM_SCY_2 | \ + OR_GPCM_TRLX_SET | OR_GPCM_EAD) + +/* + * Serial Port + */ +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) + +/* + * QE UEC ethernet configuration + */ +#define CONFIG_UEC_ETH +#define CONFIG_ETHPRIME "UEC0" + +#define CONFIG_UEC_ETH1 /* GETH1 */ +#define UEC_VERBOSE_DEBUG 1 + +#ifdef CONFIG_UEC_ETH1 +#define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */ +#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ +#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17 +#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH +#define CONFIG_SYS_UEC1_PHY_ADDR 0 +#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII +#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 +#endif + +/* + * Environment + */ + +#ifndef CONFIG_SYS_RAMBOOT +#ifndef CONFIG_ENV_ADDR +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ + CONFIG_SYS_MONITOR_LEN) +#endif +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ +#ifndef CONFIG_ENV_OFFSET +#define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN) +#endif + +/* Address and size of Redundant Environment Sector */ +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ + CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) + +#else /* CFG_SYS_RAMBOOT */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) +#define CONFIG_ENV_SIZE 0x2000 +#endif /* CFG_SYS_RAMBOOT */ + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_NUM_I2C_BUSES 4 +#define CONFIG_SYS_I2C_MAX_HOPS 1 +#define CONFIG_SYS_I2C_FSL +#define CONFIG_SYS_FSL_I2C_SPEED 200000 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C_OFFSET 0x3000 +#define CONFIG_SYS_FSL_I2C2_SPEED 200000 +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 +#define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \ + {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \ + {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \ + {1, {I2C_NULL_HOP} } } + +#define CONFIG_KM_IVM_BUS 2 /* I2C2 (Mux-Port 1)*/ + +#if defined(CONFIG_CMD_NAND) +#define CONFIG_NAND_KMETER1 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE +#endif + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) + +/* + * Core HID Setup + */ +#define CONFIG_SYS_HID0_INIT 0x000000000 +#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ + HID0_ENABLE_INSTRUCTION_CACHE) +#define CONFIG_SYS_HID2 HID2_HBE + +/* + * MMU Setup + */ + +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + +/* DDR: cache cacheable */ +#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L +#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U + +/* IMMRBAR & PCI IO: cache-inhibit and guarded */ +#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS \ + | BATU_VP) +#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L +#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U + +/* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT2U (CONFIG_SYS_KMBEC_FPGA_BASE | BATU_BL_128M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U + +/* FLASH: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U + +/* Stack in dcache: cacheable, no memory coherence */ +#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) +#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L +#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U + +/* + * Internal Definitions + */ +#define BOOTFLASH_START 0xF0000000 + +#define CONFIG_KM_CONSOLE_TTY "ttyS0" + +/* + * Environment Configuration + */ +#define CONFIG_ENV_OVERWRITE +#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ +#define CONFIG_KM_DEF_ENV "km-common=empty\0" +#endif + +#ifndef CONFIG_KM_DEF_ARCH +#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_KM_DEF_ENV \ + CONFIG_KM_DEF_ARCH \ + "newenv=" \ + "prot off "__stringify(CONFIG_ENV_ADDR)" +0x40000 && " \ + "era "__stringify(CONFIG_ENV_ADDR)" +0x40000\0" \ + "unlock=yes\0" \ + "" + +#if defined(CONFIG_UEC_ETH) +#define CONFIG_HAS_ETH0 +#endif /* * System IO Config diff --git a/include/configs/kmvect1.h b/include/configs/kmvect1.h index 5a0fbccade..c21b9ba38f 100644 --- a/include/configs/kmvect1.h +++ b/include/configs/kmvect1.h @@ -20,8 +20,6 @@ * High Level Configuration Options */ -/* This needs to be set prior to including km83xx-common.h */ - #define CONFIG_HOSTNAME "kmvect1" #define CONFIG_KM_BOARD_NAME "kmvect1" /* at end of uboot partition, before env */ @@ -35,8 +33,286 @@ #define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" -/* include common defines/options for all 83xx Keymile boards */ -#include "km83xx-common.h" +/* include common defines/options for all Keymile boards */ +#include "km/keymile-common.h" +#include "km/km-powerpc.h" + +/* + * System Clock Setup + */ +#define CONFIG_83XX_CLKIN 66000000 +#define CONFIG_SYS_CLK_FREQ 66000000 +#define CONFIG_83XX_PCICLK 66000000 + +/* + * IMMR new address + */ +#define CONFIG_SYS_IMMR 0xE0000000 + +/* + * Bus Arbitration Configuration Register (ACR) + */ +#define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */ +#define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */ +#define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */ +#define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */ + +/* + * DDR Setup + */ +#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */ + +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ + DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) + +#define CFG_83XX_DDR_USES_CS0 + +/* + * Manually set up DDR parameters + */ +#define CONFIG_DDR_II +#define CONFIG_SYS_DDR_SIZE 2048 /* MB */ + +/* + * The reserved memory + */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#define CONFIG_SYS_FLASH_BASE 0xF0000000 + +#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) +#define CONFIG_SYS_RAMBOOT +#endif + +/* Reserve 768 kB for Mon */ +#define CONFIG_SYS_MONITOR_LEN (768 * 1024) + +/* + * Initial RAM Base Address Setup + */ +#define CONFIG_SYS_INIT_RAM_LOCK +#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) + +/* + * Init Local Bus Memory Controller: + * + * Bank Bus Machine PortSz Size Device + * ---- --- ------- ------ ----- ------ + * 0 Local GPCM 16 bit 256MB FLASH + * 1 Local GPCM 8 bit 128MB GPIO/PIGGY + * + */ +/* + * FLASH on the Local Bus + */ +#define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ + +#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) + +#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ + BR_PS_16 | /* 16 bit port size */ \ + BR_MS_GPCM | /* MSEL = GPCM */ \ + BR_V) + +#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \ + OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ + OR_GPCM_SCY_5 | \ + OR_GPCM_TRLX_SET | OR_GPCM_EAD) + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } + +/* + * PRIO1/PIGGY on the local bus CS1 + */ +/* Window base at flash base */ +#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_KMBEC_FPGA_BASE +#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128MB) + +#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_KMBEC_FPGA_BASE | \ + BR_PS_8 | /* 8 bit port size */ \ + BR_MS_GPCM | /* MSEL = GPCM */ \ + BR_V) +#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \ + OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ + OR_GPCM_SCY_2 | \ + OR_GPCM_TRLX_SET | OR_GPCM_EAD) + +/* + * Serial Port + */ +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) + +/* + * QE UEC ethernet configuration + */ +#define CONFIG_UEC_ETH +#define CONFIG_ETHPRIME "UEC0" + +#ifdef CONFIG_UEC_ETH1 +#define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */ +#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ +#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17 +#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH +#define CONFIG_SYS_UEC1_PHY_ADDR 0 +#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII +#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 +#endif + +/* + * Environment + */ + +#ifndef CONFIG_SYS_RAMBOOT +#ifndef CONFIG_ENV_ADDR +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ + CONFIG_SYS_MONITOR_LEN) +#endif +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ +#ifndef CONFIG_ENV_OFFSET +#define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN) +#endif + +/* Address and size of Redundant Environment Sector */ +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ + CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) + +#else /* CFG_SYS_RAMBOOT */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) +#define CONFIG_ENV_SIZE 0x2000 +#endif /* CFG_SYS_RAMBOOT */ + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_NUM_I2C_BUSES 4 +#define CONFIG_SYS_I2C_MAX_HOPS 1 +#define CONFIG_SYS_I2C_FSL +#define CONFIG_SYS_FSL_I2C_SPEED 200000 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C_OFFSET 0x3000 +#define CONFIG_SYS_FSL_I2C2_SPEED 200000 +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 +#define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \ + {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \ + {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \ + {1, {I2C_NULL_HOP} } } + +#define CONFIG_KM_IVM_BUS 2 /* I2C2 (Mux-Port 1)*/ + +#if defined(CONFIG_CMD_NAND) +#define CONFIG_NAND_KMETER1 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE +#endif + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) + +/* + * Core HID Setup + */ +#define CONFIG_SYS_HID0_INIT 0x000000000 +#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ + HID0_ENABLE_INSTRUCTION_CACHE) +#define CONFIG_SYS_HID2 HID2_HBE + +/* + * MMU Setup + */ + +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + +/* DDR: cache cacheable */ +#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L +#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U + +/* IMMRBAR & PCI IO: cache-inhibit and guarded */ +#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS \ + | BATU_VP) +#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L +#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U + +/* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT2U (CONFIG_SYS_KMBEC_FPGA_BASE | BATU_BL_128M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U + +/* FLASH: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U + +/* Stack in dcache: cacheable, no memory coherence */ +#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) +#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L +#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U + +/* + * Internal Definitions + */ +#define BOOTFLASH_START 0xF0000000 + +#define CONFIG_KM_CONSOLE_TTY "ttyS0" + +/* + * Environment Configuration + */ +#define CONFIG_ENV_OVERWRITE +#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ +#define CONFIG_KM_DEF_ENV "km-common=empty\0" +#endif + +#ifndef CONFIG_KM_DEF_ARCH +#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_KM_DEF_ENV \ + CONFIG_KM_DEF_ARCH \ + "newenv=" \ + "prot off "__stringify(CONFIG_ENV_ADDR)" +0x40000 && " \ + "era "__stringify(CONFIG_ENV_ADDR)" +0x40000\0" \ + "unlock=yes\0" \ + "" + +#if defined(CONFIG_UEC_ETH) +#define CONFIG_HAS_ETH0 +#endif /* QE microcode/firmware address */ #define CONFIG_SYS_QE_FMAN_FW_IN_NOR diff --git a/include/configs/suvd3.h b/include/configs/suvd3.h index 5fe5f3cc23..87f7390bcc 100644 --- a/include/configs/suvd3.h +++ b/include/configs/suvd3.h @@ -20,8 +20,6 @@ * High Level Configuration Options */ -/* This needs to be set prior to including km83xx-common.h */ - #define CONFIG_HOSTNAME "suvd3" #define CONFIG_KM_BOARD_NAME "suvd3" @@ -33,8 +31,289 @@ #define CONFIG_KM_DEF_ARCH "arch=ppc_8xx\0" -/* include common defines/options for all 83xx Keymile boards */ -#include "km83xx-common.h" +/* include common defines/options for all Keymile boards */ +#include "km/keymile-common.h" +#include "km/km-powerpc.h" + +/* + * System Clock Setup + */ +#define CONFIG_83XX_CLKIN 66000000 +#define CONFIG_SYS_CLK_FREQ 66000000 +#define CONFIG_83XX_PCICLK 66000000 + +/* + * IMMR new address + */ +#define CONFIG_SYS_IMMR 0xE0000000 + +/* + * Bus Arbitration Configuration Register (ACR) + */ +#define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */ +#define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */ +#define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */ +#define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */ + +/* + * DDR Setup + */ +#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */ + +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ + DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) + +#define CFG_83XX_DDR_USES_CS0 + +/* + * Manually set up DDR parameters + */ +#define CONFIG_DDR_II +#define CONFIG_SYS_DDR_SIZE 2048 /* MB */ + +/* + * The reserved memory + */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#define CONFIG_SYS_FLASH_BASE 0xF0000000 + +#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) +#define CONFIG_SYS_RAMBOOT +#endif + +/* Reserve 768 kB for Mon */ +#define CONFIG_SYS_MONITOR_LEN (768 * 1024) + +/* + * Initial RAM Base Address Setup + */ +#define CONFIG_SYS_INIT_RAM_LOCK +#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) + +/* + * Init Local Bus Memory Controller: + * + * Bank Bus Machine PortSz Size Device + * ---- --- ------- ------ ----- ------ + * 0 Local GPCM 16 bit 256MB FLASH + * 1 Local GPCM 8 bit 128MB GPIO/PIGGY + * + */ +/* + * FLASH on the Local Bus + */ +#define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ + +#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) + +#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ + BR_PS_16 | /* 16 bit port size */ \ + BR_MS_GPCM | /* MSEL = GPCM */ \ + BR_V) + +#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \ + OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ + OR_GPCM_SCY_5 | \ + OR_GPCM_TRLX_SET | OR_GPCM_EAD) + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } + +/* + * PRIO1/PIGGY on the local bus CS1 + */ +/* Window base at flash base */ +#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_KMBEC_FPGA_BASE +#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128MB) + +#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_KMBEC_FPGA_BASE | \ + BR_PS_8 | /* 8 bit port size */ \ + BR_MS_GPCM | /* MSEL = GPCM */ \ + BR_V) +#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \ + OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ + OR_GPCM_SCY_2 | \ + OR_GPCM_TRLX_SET | OR_GPCM_EAD) + +/* + * Serial Port + */ +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) + +/* + * QE UEC ethernet configuration + */ +#define CONFIG_UEC_ETH +#define CONFIG_ETHPRIME "UEC0" + +#define CONFIG_UEC_ETH1 /* GETH1 */ +#define UEC_VERBOSE_DEBUG 1 + +#ifdef CONFIG_UEC_ETH1 +#define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */ +#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ +#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17 +#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH +#define CONFIG_SYS_UEC1_PHY_ADDR 0 +#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII +#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 +#endif + +/* + * Environment + */ + +#ifndef CONFIG_SYS_RAMBOOT +#ifndef CONFIG_ENV_ADDR +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ + CONFIG_SYS_MONITOR_LEN) +#endif +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ +#ifndef CONFIG_ENV_OFFSET +#define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN) +#endif + +/* Address and size of Redundant Environment Sector */ +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ + CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) + +#else /* CFG_SYS_RAMBOOT */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) +#define CONFIG_ENV_SIZE 0x2000 +#endif /* CFG_SYS_RAMBOOT */ + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_NUM_I2C_BUSES 4 +#define CONFIG_SYS_I2C_MAX_HOPS 1 +#define CONFIG_SYS_I2C_FSL +#define CONFIG_SYS_FSL_I2C_SPEED 200000 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C_OFFSET 0x3000 +#define CONFIG_SYS_FSL_I2C2_SPEED 200000 +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 +#define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \ + {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \ + {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \ + {1, {I2C_NULL_HOP} } } + +#define CONFIG_KM_IVM_BUS 2 /* I2C2 (Mux-Port 1)*/ + +#if defined(CONFIG_CMD_NAND) +#define CONFIG_NAND_KMETER1 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE +#endif + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) + +/* + * Core HID Setup + */ +#define CONFIG_SYS_HID0_INIT 0x000000000 +#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ + HID0_ENABLE_INSTRUCTION_CACHE) +#define CONFIG_SYS_HID2 HID2_HBE + +/* + * MMU Setup + */ + +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + +/* DDR: cache cacheable */ +#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L +#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U + +/* IMMRBAR & PCI IO: cache-inhibit and guarded */ +#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS \ + | BATU_VP) +#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L +#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U + +/* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT2U (CONFIG_SYS_KMBEC_FPGA_BASE | BATU_BL_128M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U + +/* FLASH: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U + +/* Stack in dcache: cacheable, no memory coherence */ +#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) +#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L +#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U + +/* + * Internal Definitions + */ +#define BOOTFLASH_START 0xF0000000 + +#define CONFIG_KM_CONSOLE_TTY "ttyS0" + +/* + * Environment Configuration + */ +#define CONFIG_ENV_OVERWRITE +#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ +#define CONFIG_KM_DEF_ENV "km-common=empty\0" +#endif + +#ifndef CONFIG_KM_DEF_ARCH +#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_KM_DEF_ENV \ + CONFIG_KM_DEF_ARCH \ + "newenv=" \ + "prot off "__stringify(CONFIG_ENV_ADDR)" +0x40000 && " \ + "era "__stringify(CONFIG_ENV_ADDR)" +0x40000\0" \ + "unlock=yes\0" \ + "" + +#if defined(CONFIG_UEC_ETH) +#define CONFIG_HAS_ETH0 +#endif /* * System IO Config diff --git a/include/configs/tuge1.h b/include/configs/tuge1.h index 85f8e9cd30..1cd0985dc2 100644 --- a/include/configs/tuge1.h +++ b/include/configs/tuge1.h @@ -34,8 +34,289 @@ #define CONFIG_KM_DEF_ARCH "arch=ppc_8xx\0" -/* include common defines/options for all 83xx Keymile boards */ -#include "km83xx-common.h" +/* include common defines/options for all Keymile boards */ +#include "km/keymile-common.h" +#include "km/km-powerpc.h" + +/* + * System Clock Setup + */ +#define CONFIG_83XX_CLKIN 66000000 +#define CONFIG_SYS_CLK_FREQ 66000000 +#define CONFIG_83XX_PCICLK 66000000 + +/* + * IMMR new address + */ +#define CONFIG_SYS_IMMR 0xE0000000 + +/* + * Bus Arbitration Configuration Register (ACR) + */ +#define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */ +#define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */ +#define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */ +#define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */ + +/* + * DDR Setup + */ +#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */ + +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ + DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) + +#define CFG_83XX_DDR_USES_CS0 + +/* + * Manually set up DDR parameters + */ +#define CONFIG_DDR_II +#define CONFIG_SYS_DDR_SIZE 2048 /* MB */ + +/* + * The reserved memory + */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#define CONFIG_SYS_FLASH_BASE 0xF0000000 + +#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) +#define CONFIG_SYS_RAMBOOT +#endif + +/* Reserve 768 kB for Mon */ +#define CONFIG_SYS_MONITOR_LEN (768 * 1024) + +/* + * Initial RAM Base Address Setup + */ +#define CONFIG_SYS_INIT_RAM_LOCK +#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) + +/* + * Init Local Bus Memory Controller: + * + * Bank Bus Machine PortSz Size Device + * ---- --- ------- ------ ----- ------ + * 0 Local GPCM 16 bit 256MB FLASH + * 1 Local GPCM 8 bit 128MB GPIO/PIGGY + * + */ +/* + * FLASH on the Local Bus + */ +#define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ + +#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) + +#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ + BR_PS_16 | /* 16 bit port size */ \ + BR_MS_GPCM | /* MSEL = GPCM */ \ + BR_V) + +#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \ + OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ + OR_GPCM_SCY_5 | \ + OR_GPCM_TRLX_SET | OR_GPCM_EAD) + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } + +/* + * PRIO1/PIGGY on the local bus CS1 + */ +/* Window base at flash base */ +#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_KMBEC_FPGA_BASE +#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128MB) + +#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_KMBEC_FPGA_BASE | \ + BR_PS_8 | /* 8 bit port size */ \ + BR_MS_GPCM | /* MSEL = GPCM */ \ + BR_V) +#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \ + OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ + OR_GPCM_SCY_2 | \ + OR_GPCM_TRLX_SET | OR_GPCM_EAD) + +/* + * Serial Port + */ +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) + +/* + * QE UEC ethernet configuration + */ +#define CONFIG_UEC_ETH +#define CONFIG_ETHPRIME "UEC0" + +#define CONFIG_UEC_ETH1 /* GETH1 */ +#define UEC_VERBOSE_DEBUG 1 + +#ifdef CONFIG_UEC_ETH1 +#define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */ +#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ +#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17 +#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH +#define CONFIG_SYS_UEC1_PHY_ADDR 0 +#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII +#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 +#endif + +/* + * Environment + */ + +#ifndef CONFIG_SYS_RAMBOOT +#ifndef CONFIG_ENV_ADDR +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ + CONFIG_SYS_MONITOR_LEN) +#endif +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ +#ifndef CONFIG_ENV_OFFSET +#define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN) +#endif + +/* Address and size of Redundant Environment Sector */ +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ + CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) + +#else /* CFG_SYS_RAMBOOT */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) +#define CONFIG_ENV_SIZE 0x2000 +#endif /* CFG_SYS_RAMBOOT */ + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_NUM_I2C_BUSES 4 +#define CONFIG_SYS_I2C_MAX_HOPS 1 +#define CONFIG_SYS_I2C_FSL +#define CONFIG_SYS_FSL_I2C_SPEED 200000 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C_OFFSET 0x3000 +#define CONFIG_SYS_FSL_I2C2_SPEED 200000 +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 +#define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \ + {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \ + {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \ + {1, {I2C_NULL_HOP} } } + +#define CONFIG_KM_IVM_BUS 2 /* I2C2 (Mux-Port 1)*/ + +#if defined(CONFIG_CMD_NAND) +#define CONFIG_NAND_KMETER1 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE +#endif + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) + +/* + * Core HID Setup + */ +#define CONFIG_SYS_HID0_INIT 0x000000000 +#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ + HID0_ENABLE_INSTRUCTION_CACHE) +#define CONFIG_SYS_HID2 HID2_HBE + +/* + * MMU Setup + */ + +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + +/* DDR: cache cacheable */ +#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L +#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U + +/* IMMRBAR & PCI IO: cache-inhibit and guarded */ +#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS \ + | BATU_VP) +#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L +#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U + +/* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT2U (CONFIG_SYS_KMBEC_FPGA_BASE | BATU_BL_128M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U + +/* FLASH: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U + +/* Stack in dcache: cacheable, no memory coherence */ +#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) +#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L +#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U + +/* + * Internal Definitions + */ +#define BOOTFLASH_START 0xF0000000 + +#define CONFIG_KM_CONSOLE_TTY "ttyS0" + +/* + * Environment Configuration + */ +#define CONFIG_ENV_OVERWRITE +#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ +#define CONFIG_KM_DEF_ENV "km-common=empty\0" +#endif + +#ifndef CONFIG_KM_DEF_ARCH +#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_KM_DEF_ENV \ + CONFIG_KM_DEF_ARCH \ + "newenv=" \ + "prot off "__stringify(CONFIG_ENV_ADDR)" +0x40000 && " \ + "era "__stringify(CONFIG_ENV_ADDR)" +0x40000\0" \ + "unlock=yes\0" \ + "" + +#if defined(CONFIG_UEC_ETH) +#define CONFIG_HAS_ETH0 +#endif /* * System IO Config diff --git a/include/configs/tuxx1.h b/include/configs/tuxx1.h index b42221a430..d476a75e3e 100644 --- a/include/configs/tuxx1.h +++ b/include/configs/tuxx1.h @@ -34,8 +34,289 @@ #define CONFIG_KM_DEF_ARCH "arch=ppc_8xx\0" -/* include common defines/options for all 83xx Keymile boards */ -#include "km83xx-common.h" +/* include common defines/options for all Keymile boards */ +#include "km/keymile-common.h" +#include "km/km-powerpc.h" + +/* + * System Clock Setup + */ +#define CONFIG_83XX_CLKIN 66000000 +#define CONFIG_SYS_CLK_FREQ 66000000 +#define CONFIG_83XX_PCICLK 66000000 + +/* + * IMMR new address + */ +#define CONFIG_SYS_IMMR 0xE0000000 + +/* + * Bus Arbitration Configuration Register (ACR) + */ +#define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */ +#define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */ +#define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */ +#define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */ + +/* + * DDR Setup + */ +#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */ + +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ + DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) + +#define CFG_83XX_DDR_USES_CS0 + +/* + * Manually set up DDR parameters + */ +#define CONFIG_DDR_II +#define CONFIG_SYS_DDR_SIZE 2048 /* MB */ + +/* + * The reserved memory + */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#define CONFIG_SYS_FLASH_BASE 0xF0000000 + +#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) +#define CONFIG_SYS_RAMBOOT +#endif + +/* Reserve 768 kB for Mon */ +#define CONFIG_SYS_MONITOR_LEN (768 * 1024) + +/* + * Initial RAM Base Address Setup + */ +#define CONFIG_SYS_INIT_RAM_LOCK +#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) + +/* + * Init Local Bus Memory Controller: + * + * Bank Bus Machine PortSz Size Device + * ---- --- ------- ------ ----- ------ + * 0 Local GPCM 16 bit 256MB FLASH + * 1 Local GPCM 8 bit 128MB GPIO/PIGGY + * + */ +/* + * FLASH on the Local Bus + */ +#define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ + +#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) + +#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ + BR_PS_16 | /* 16 bit port size */ \ + BR_MS_GPCM | /* MSEL = GPCM */ \ + BR_V) + +#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \ + OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ + OR_GPCM_SCY_5 | \ + OR_GPCM_TRLX_SET | OR_GPCM_EAD) + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } + +/* + * PRIO1/PIGGY on the local bus CS1 + */ +/* Window base at flash base */ +#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_KMBEC_FPGA_BASE +#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128MB) + +#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_KMBEC_FPGA_BASE | \ + BR_PS_8 | /* 8 bit port size */ \ + BR_MS_GPCM | /* MSEL = GPCM */ \ + BR_V) +#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \ + OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ + OR_GPCM_SCY_2 | \ + OR_GPCM_TRLX_SET | OR_GPCM_EAD) + +/* + * Serial Port + */ +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) + +/* + * QE UEC ethernet configuration + */ +#define CONFIG_UEC_ETH +#define CONFIG_ETHPRIME "UEC0" + +#define CONFIG_UEC_ETH1 /* GETH1 */ +#define UEC_VERBOSE_DEBUG 1 + +#ifdef CONFIG_UEC_ETH1 +#define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */ +#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ +#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17 +#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH +#define CONFIG_SYS_UEC1_PHY_ADDR 0 +#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII +#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 +#endif + +/* + * Environment + */ + +#ifndef CONFIG_SYS_RAMBOOT +#ifndef CONFIG_ENV_ADDR +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ + CONFIG_SYS_MONITOR_LEN) +#endif +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ +#ifndef CONFIG_ENV_OFFSET +#define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN) +#endif + +/* Address and size of Redundant Environment Sector */ +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ + CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) + +#else /* CFG_SYS_RAMBOOT */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) +#define CONFIG_ENV_SIZE 0x2000 +#endif /* CFG_SYS_RAMBOOT */ + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_NUM_I2C_BUSES 4 +#define CONFIG_SYS_I2C_MAX_HOPS 1 +#define CONFIG_SYS_I2C_FSL +#define CONFIG_SYS_FSL_I2C_SPEED 200000 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C_OFFSET 0x3000 +#define CONFIG_SYS_FSL_I2C2_SPEED 200000 +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 +#define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \ + {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \ + {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \ + {1, {I2C_NULL_HOP} } } + +#define CONFIG_KM_IVM_BUS 2 /* I2C2 (Mux-Port 1)*/ + +#if defined(CONFIG_CMD_NAND) +#define CONFIG_NAND_KMETER1 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE +#endif + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) + +/* + * Core HID Setup + */ +#define CONFIG_SYS_HID0_INIT 0x000000000 +#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ + HID0_ENABLE_INSTRUCTION_CACHE) +#define CONFIG_SYS_HID2 HID2_HBE + +/* + * MMU Setup + */ + +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + +/* DDR: cache cacheable */ +#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L +#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U + +/* IMMRBAR & PCI IO: cache-inhibit and guarded */ +#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS \ + | BATU_VP) +#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L +#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U + +/* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT2U (CONFIG_SYS_KMBEC_FPGA_BASE | BATU_BL_128M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U + +/* FLASH: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U + +/* Stack in dcache: cacheable, no memory coherence */ +#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) +#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L +#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U + +/* + * Internal Definitions + */ +#define BOOTFLASH_START 0xF0000000 + +#define CONFIG_KM_CONSOLE_TTY "ttyS0" + +/* + * Environment Configuration + */ +#define CONFIG_ENV_OVERWRITE +#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ +#define CONFIG_KM_DEF_ENV "km-common=empty\0" +#endif + +#ifndef CONFIG_KM_DEF_ARCH +#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_KM_DEF_ENV \ + CONFIG_KM_DEF_ARCH \ + "newenv=" \ + "prot off "__stringify(CONFIG_ENV_ADDR)" +0x40000 && " \ + "era "__stringify(CONFIG_ENV_ADDR)" +0x40000\0" \ + "unlock=yes\0" \ + "" + +#if defined(CONFIG_UEC_ETH) +#define CONFIG_HAS_ETH0 +#endif /* * System IO Config From 009c87a2ab7bf39b2c46a415516a2142b76ed23a Mon Sep 17 00:00:00 2001 From: Mario Six Date: Mon, 21 Jan 2019 09:17:35 +0100 Subject: [PATCH 12/86] keymile: Make distinct kmeter1, and kmcoge5ne configs The kmeter1, and kmcoge5ne boards also build from the same config file with #ifdef logic. Create a separate include config for each board with the #ifdef logic resolved as needed. Signed-off-by: Mario Six --- arch/powerpc/cpu/mpc83xx/Kconfig | 11 +- board/keymile/km83xx/Kconfig | 17 +- board/keymile/km83xx/km83xx.c | 2 +- configs/kmcoge5ne_defconfig | 3 +- configs/kmeter1_defconfig | 3 +- include/configs/{km8360.h => kmcoge5ne.h} | 29 -- include/configs/kmeter1.h | 458 ++++++++++++++++++++++ 7 files changed, 485 insertions(+), 38 deletions(-) rename include/configs/{km8360.h => kmcoge5ne.h} (95%) create mode 100644 include/configs/kmeter1.h diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index 1ebb092f0b..29d84f363d 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -80,8 +80,15 @@ config TARGET_IDS8313 select DM imply CMD_DM -config TARGET_KM8360 - bool "Support km8360" +config TARGET_KMETER1 + bool "Support kmeter1" + select ARCH_MPC8360 + imply CMD_CRAMFS + imply CMD_DIAG + imply FS_CRAMFS + +config TARGET_KMCOGE5NE + bool "Support kmcoge5ne" select ARCH_MPC8360 imply CMD_CRAMFS imply CMD_DIAG diff --git a/board/keymile/km83xx/Kconfig b/board/keymile/km83xx/Kconfig index 0c4fa0b7fd..fbbbb17034 100644 --- a/board/keymile/km83xx/Kconfig +++ b/board/keymile/km83xx/Kconfig @@ -1,4 +1,4 @@ -if TARGET_KM8360 +if TARGET_KMETER1 config SYS_BOARD default "km83xx" @@ -7,7 +7,20 @@ config SYS_VENDOR default "keymile" config SYS_CONFIG_NAME - default "km8360" + default "kmeter1" + +endif + +if TARGET_KMCOGE5NE + +config SYS_BOARD + default "km83xx" + +config SYS_VENDOR + default "keymile" + +config SYS_CONFIG_NAME + default "kmcoge5ne" endif diff --git a/board/keymile/km83xx/km83xx.c b/board/keymile/km83xx/km83xx.c index 12044ee0d7..1fd6f91901 100644 --- a/board/keymile/km83xx/km83xx.c +++ b/board/keymile/km83xx/km83xx.c @@ -271,7 +271,7 @@ int last_stage_init(void) } #endif -#if defined(CONFIG_KMCOGE5NE) +#if defined(CONFIG_TARGET_KMCOGE5NE) struct bfticu_iomap *base = (struct bfticu_iomap *)CONFIG_SYS_BFTIC3_BASE; u8 dip_switch = in_8((u8 *)&(base->mswitch)) & BFTICU_DIPSWITCH_MASK; diff --git a/configs/kmcoge5ne_defconfig b/configs/kmcoge5ne_defconfig index cb47b0b7fd..b7c42fa9cb 100644 --- a/configs/kmcoge5ne_defconfig +++ b/configs/kmcoge5ne_defconfig @@ -1,10 +1,9 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xF0000000 CONFIG_MPC83xx=y -CONFIG_TARGET_KM8360=y +CONFIG_TARGET_KMCOGE5NE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="KMCOGE5NE" CONFIG_MISC_INIT_R=y CONFIG_VERSION_VARIABLE=y CONFIG_BOARD_EARLY_INIT_R=y diff --git a/configs/kmeter1_defconfig b/configs/kmeter1_defconfig index 0c3fadfcf8..1773f74358 100644 --- a/configs/kmeter1_defconfig +++ b/configs/kmeter1_defconfig @@ -1,10 +1,9 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xF0000000 CONFIG_MPC83xx=y -CONFIG_TARGET_KM8360=y +CONFIG_TARGET_KMETER1=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="KMETER1" CONFIG_MISC_INIT_R=y CONFIG_VERSION_VARIABLE=y CONFIG_BOARD_EARLY_INIT_R=y diff --git a/include/configs/km8360.h b/include/configs/kmcoge5ne.h similarity index 95% rename from include/configs/km8360.h rename to include/configs/kmcoge5ne.h index 3e25b3988b..ec65a4208b 100644 --- a/include/configs/km8360.h +++ b/include/configs/kmcoge5ne.h @@ -12,11 +12,6 @@ #define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000 #define CONFIG_SYS_KMBEC_FPGA_SIZE 64 -#if defined CONFIG_KMETER1 -#define CONFIG_HOSTNAME "kmeter1" -#define CONFIG_KM_BOARD_NAME "kmeter1" -#define CONFIG_KM_DEF_NETDEV "netdev=eth2\0" -#elif defined CONFIG_KMCOGE5NE #define CONFIG_HOSTNAME "kmcoge5ne" #define CONFIG_KM_BOARD_NAME "kmcoge5ne" #define CONFIG_KM_DEF_NETDEV "netdev=eth1\0" @@ -28,9 +23,6 @@ #define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0" #define CONFIG_KM_UBI_PARTITION_NAME_APP "ubi1" -#else -#error ("Board not supported") -#endif /* * High Level Configuration Options @@ -165,10 +157,8 @@ #define CONFIG_UEC_ETH #define CONFIG_ETHPRIME "UEC0" -#if !defined(CONFIG_ARCH_MPC8309) #define CONFIG_UEC_ETH1 /* GETH1 */ #define UEC_VERBOSE_DEBUG 1 -#endif #ifdef CONFIG_UEC_ETH1 #define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */ @@ -357,7 +347,6 @@ #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 -#ifdef CONFIG_KMCOGE5NE /** * KMCOGE5NE has 512 MB RAM */ @@ -368,12 +357,6 @@ CSCONFIG_BANK_BIT_3 | \ CSCONFIG_ROW_BIT_13 | \ CSCONFIG_COL_BIT_10) -#else -#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ - CSCONFIG_ROW_BIT_13 | \ - CSCONFIG_COL_BIT_10 | \ - CSCONFIG_ODT_WR_ONLY_CURRENT) -#endif #define CONFIG_SYS_DDR_CLK_CNTL (\ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) @@ -453,7 +436,6 @@ OR_GPCM_TRLX | \ OR_GPCM_EAD) -#ifdef CONFIG_KMCOGE5NE /* * BFTIC3 on the local bus CS4 */ @@ -472,7 +454,6 @@ OR_GPCM_SCY_2 |\ OR_GPCM_TRLX |\ OR_GPCM_EAD) -#endif /* * MMU Setup @@ -498,7 +479,6 @@ #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U -#ifdef CONFIG_KMCOGE5NE /* BFTIC3: icache cacheable, but dcache-inhibit and guarded */ #define CONFIG_SYS_IBAT6L (\ CONFIG_SYS_BFTIC3_BASE | \ @@ -538,15 +518,6 @@ #define CONFIG_TESTPIN_REG gprt3 /* for kmcoge5ne */ #define CONFIG_TESTPIN_MASK 0x20 /* for kmcoge5ne */ -#else -#define CONFIG_SYS_IBAT6L (0) -#define CONFIG_SYS_IBAT6U (0) -#define CONFIG_SYS_IBAT7L (0) -#define CONFIG_SYS_IBAT7U (0) -#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U -#endif - #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h new file mode 100644 index 0000000000..976255f578 --- /dev/null +++ b/include/configs/kmeter1.h @@ -0,0 +1,458 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2012 + * Holger Brunck, Keymile GmbH Hannover, + * Christian Herzig, Keymile AG Switzerland, + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* KMBEC FPGA (PRIO) */ +#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000 +#define CONFIG_SYS_KMBEC_FPGA_SIZE 64 + +#define CONFIG_HOSTNAME "kmeter1" +#define CONFIG_KM_BOARD_NAME "kmeter1" +#define CONFIG_KM_DEF_NETDEV "netdev=eth2\0" + +/* + * High Level Configuration Options + */ +#define CONFIG_QE /* Has QE */ + +/* include common defines/options for all Keymile boards */ +#include "km/keymile-common.h" +#include "km/km-powerpc.h" + +/* + * System Clock Setup + */ +#define CONFIG_83XX_CLKIN 66000000 +#define CONFIG_SYS_CLK_FREQ 66000000 +#define CONFIG_83XX_PCICLK 66000000 + +/* + * IMMR new address + */ +#define CONFIG_SYS_IMMR 0xE0000000 + +/* + * Bus Arbitration Configuration Register (ACR) + */ +#define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */ +#define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */ +#define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */ +#define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */ + +/* + * DDR Setup + */ +#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */ + +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ + DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) + +#define CFG_83XX_DDR_USES_CS0 + +/* + * Manually set up DDR parameters + */ +#define CONFIG_DDR_II +#define CONFIG_SYS_DDR_SIZE 2048 /* MB */ + +/* + * The reserved memory + */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#define CONFIG_SYS_FLASH_BASE 0xF0000000 + +#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) +#define CONFIG_SYS_RAMBOOT +#endif + +/* Reserve 768 kB for Mon */ +#define CONFIG_SYS_MONITOR_LEN (768 * 1024) + +/* + * Initial RAM Base Address Setup + */ +#define CONFIG_SYS_INIT_RAM_LOCK +#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) + +/* + * Init Local Bus Memory Controller: + * + * Bank Bus Machine PortSz Size Device + * ---- --- ------- ------ ----- ------ + * 0 Local GPCM 16 bit 256MB FLASH + * 1 Local GPCM 8 bit 128MB GPIO/PIGGY + * + */ +/* + * FLASH on the Local Bus + */ +#define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ + +#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) + +#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ + BR_PS_16 | /* 16 bit port size */ \ + BR_MS_GPCM | /* MSEL = GPCM */ \ + BR_V) + +#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \ + OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ + OR_GPCM_SCY_5 | \ + OR_GPCM_TRLX_SET | OR_GPCM_EAD) + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } + +/* + * PRIO1/PIGGY on the local bus CS1 + */ +/* Window base at flash base */ +#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_KMBEC_FPGA_BASE +#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128MB) + +#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_KMBEC_FPGA_BASE | \ + BR_PS_8 | /* 8 bit port size */ \ + BR_MS_GPCM | /* MSEL = GPCM */ \ + BR_V) +#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \ + OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ + OR_GPCM_SCY_2 | \ + OR_GPCM_TRLX_SET | OR_GPCM_EAD) + +/* + * Serial Port + */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) + +/* + * QE UEC ethernet configuration + */ +#define CONFIG_UEC_ETH +#define CONFIG_ETHPRIME "UEC0" + +#define CONFIG_UEC_ETH1 /* GETH1 */ +#define UEC_VERBOSE_DEBUG 1 + +#ifdef CONFIG_UEC_ETH1 +#define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */ +#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ +#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17 +#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH +#define CONFIG_SYS_UEC1_PHY_ADDR 0 +#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII +#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 +#endif + +/* + * Environment + */ + +#ifndef CONFIG_SYS_RAMBOOT +#ifndef CONFIG_ENV_ADDR +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ + CONFIG_SYS_MONITOR_LEN) +#endif +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ +#ifndef CONFIG_ENV_OFFSET +#define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN) +#endif + +/* Address and size of Redundant Environment Sector */ +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ + CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) + +#else /* CFG_SYS_RAMBOOT */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) +#define CONFIG_ENV_SIZE 0x2000 +#endif /* CFG_SYS_RAMBOOT */ + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_NUM_I2C_BUSES 4 +#define CONFIG_SYS_I2C_MAX_HOPS 1 +#define CONFIG_SYS_I2C_FSL +#define CONFIG_SYS_FSL_I2C_SPEED 200000 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C_OFFSET 0x3000 +#define CONFIG_SYS_FSL_I2C2_SPEED 200000 +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 +#define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \ + {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \ + {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \ + {1, {I2C_NULL_HOP} } } + +#define CONFIG_KM_IVM_BUS 2 /* I2C2 (Mux-Port 1)*/ + +#if defined(CONFIG_CMD_NAND) +#define CONFIG_NAND_KMETER1 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE +#endif + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) + +/* + * Core HID Setup + */ +#define CONFIG_SYS_HID0_INIT 0x000000000 +#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ + HID0_ENABLE_INSTRUCTION_CACHE) +#define CONFIG_SYS_HID2 HID2_HBE + +/* + * MMU Setup + */ + +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + +/* DDR: cache cacheable */ +#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L +#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U + +/* IMMRBAR & PCI IO: cache-inhibit and guarded */ +#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS \ + | BATU_VP) +#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L +#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U + +/* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT2U (CONFIG_SYS_KMBEC_FPGA_BASE | BATU_BL_128M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U + +/* FLASH: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U + +/* Stack in dcache: cacheable, no memory coherence */ +#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) +#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L +#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U + +/* + * Internal Definitions + */ +#define BOOTFLASH_START 0xF0000000 + +#define CONFIG_KM_CONSOLE_TTY "ttyS0" + +/* + * Environment Configuration + */ +#define CONFIG_ENV_OVERWRITE +#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ +#define CONFIG_KM_DEF_ENV "km-common=empty\0" +#endif + +#ifndef CONFIG_KM_DEF_ARCH +#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_KM_DEF_ENV \ + CONFIG_KM_DEF_ARCH \ + "newenv=" \ + "prot off "__stringify(CONFIG_ENV_ADDR)" +0x40000 && " \ + "era "__stringify(CONFIG_ENV_ADDR)" +0x40000\0" \ + "unlock=yes\0" \ + "" + +#if defined(CONFIG_UEC_ETH) +#define CONFIG_HAS_ETH0 +#endif + +/* + * System IO Setup + */ +#define CONFIG_SYS_SICRH (SICRH_UC1EOBI | SICRH_UC2E1OBI) + +/* + * Hardware Reset Configuration Word + */ +#define CONFIG_SYS_HRCW_LOW (\ + HRCWL_CSB_TO_CLKIN_4X1 | \ + HRCWL_CORE_TO_CSB_2X1 | \ + HRCWL_CE_PLL_VCO_DIV_2 | \ + HRCWL_CE_TO_PLL_1X6) + +#define CONFIG_SYS_HRCW_HIGH (\ + HRCWH_CORE_ENABLE | \ + HRCWH_FROM_0X00000100 | \ + HRCWH_BOOTSEQ_DISABLE | \ + HRCWH_SW_WATCHDOG_DISABLE | \ + HRCWH_ROM_LOC_LOCAL_16BIT | \ + HRCWH_BIG_ENDIAN | \ + HRCWH_LALE_EARLY | \ + HRCWH_LDP_CLEAR) + +/** + * DDR RAM settings + */ +#define CONFIG_SYS_DDR_SDRAM_CFG (\ + SDRAM_CFG_SDRAM_TYPE_DDR2 | \ + SDRAM_CFG_SREN | \ + SDRAM_CFG_HSE) + +#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 + +#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ + CSCONFIG_ROW_BIT_13 | \ + CSCONFIG_COL_BIT_10 | \ + CSCONFIG_ODT_WR_ONLY_CURRENT) + +#define CONFIG_SYS_DDR_CLK_CNTL (\ + DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) + +#define CONFIG_SYS_DDR_INTERVAL (\ + (0x080 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ + (0x203 << SDRAM_INTERVAL_REFINT_SHIFT)) + +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f + +#define CONFIG_SYS_DDRCDR (\ + DDRCDR_EN | \ + DDRCDR_Q_DRN) +#define CONFIG_SYS_DDR_MODE 0x47860452 +#define CONFIG_SYS_DDR_MODE2 0x8080c000 + +#define CONFIG_SYS_DDR_TIMING_0 (\ + (2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ + (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ + (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ + (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ + (0 << TIMING_CFG0_WWT_SHIFT) | \ + (0 << TIMING_CFG0_RRT_SHIFT) | \ + (0 << TIMING_CFG0_WRT_SHIFT) | \ + (0 << TIMING_CFG0_RWT_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \ + (2 << TIMING_CFG1_WRTORD_SHIFT) | \ + (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ + (3 << TIMING_CFG1_WRREC_SHIFT) | \ + (7 << TIMING_CFG1_REFREC_SHIFT) | \ + (3 << TIMING_CFG1_ACTTORW_SHIFT) | \ + (8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ + (3 << TIMING_CFG1_PRETOACT_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_2 (\ + (0xa << TIMING_CFG2_FOUR_ACT_SHIFT) | \ + (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ + (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ + (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ + (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ + (5 << TIMING_CFG2_CPO_SHIFT) | \ + (0 << TIMING_CFG2_ADD_LAT_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_3 0x00000000 + +/* EEprom support */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 + +/* + * Local Bus Configuration & Clock Setup + */ +#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP +#define CONFIG_SYS_LCRR_EADC LCRR_EADC_2 +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 + +/* + * PAXE on the local bus CS3 + */ +#define CONFIG_SYS_PAXE_BASE 0xA0000000 +#define CONFIG_SYS_PAXE_SIZE 256 + +#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_PAXE_BASE + +#define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000001C /* 512MB window size */ + +#define CONFIG_SYS_BR3_PRELIM (\ + CONFIG_SYS_PAXE_BASE | \ + (1 << BR_PS_SHIFT) | \ + BR_V) + +#define CONFIG_SYS_OR3_PRELIM (\ + MEG_TO_AM(CONFIG_SYS_PAXE_SIZE) | \ + OR_GPCM_CSNT | \ + OR_GPCM_ACS_DIV2 | \ + OR_GPCM_SCY_2 | \ + OR_GPCM_TRLX | \ + OR_GPCM_EAD) + +/* + * MMU Setup + */ + +/* PAXE: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT5L (\ + CONFIG_SYS_PAXE_BASE | \ + BATL_PP_10 | \ + BATL_MEMCOHERENCE) + +#define CONFIG_SYS_IBAT5U (\ + CONFIG_SYS_PAXE_BASE | \ + BATU_BL_256M | \ + BATU_VS | \ + BATU_VP) + +#define CONFIG_SYS_DBAT5L (\ + CONFIG_SYS_PAXE_BASE | \ + BATL_PP_10 | \ + BATL_CACHEINHIBIT | \ + BATL_GUARDEDSTORAGE) + +#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U +#define CONFIG_SYS_IBAT6L (0) +#define CONFIG_SYS_IBAT6U (0) +#define CONFIG_SYS_IBAT7L (0) +#define CONFIG_SYS_IBAT7U (0) +#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L +#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U +#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L +#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U + +#endif /* CONFIG */ From 16aaca214e5799bf246c502360fca05ee8d223ed Mon Sep 17 00:00:00 2001 From: Mario Six Date: Mon, 21 Jan 2019 09:17:36 +0100 Subject: [PATCH 13/86] mpc83xx: Make distinct MPC8313ERDB targets MPC8313ERDB has the option of either enabling NOR or NAND boot in its config file (by commenting out certain #ifdefs). To keep this ability after migrating options to Kconfig, we introduce two MPC8313ERDB configs: one for NOR, and one for NAND. Signed-off-by: Mario Six --- arch/powerpc/cpu/mpc83xx/Kconfig | 10 +- board/freescale/mpc8313erdb/Kconfig | 17 +- configs/MPC8313ERDB_33_defconfig | 2 +- configs/MPC8313ERDB_66_defconfig | 2 +- configs/MPC8313ERDB_NAND_33_defconfig | 2 +- configs/MPC8313ERDB_NAND_66_defconfig | 2 +- .../{MPC8313ERDB.h => MPC8313ERDB_NAND.h} | 61 +- include/configs/MPC8313ERDB_NOR.h | 591 ++++++++++++++++++ 8 files changed, 633 insertions(+), 54 deletions(-) rename include/configs/{MPC8313ERDB.h => MPC8313ERDB_NAND.h} (90%) create mode 100644 include/configs/MPC8313ERDB_NOR.h diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index 29d84f363d..ede98c70da 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -29,8 +29,14 @@ config TARGET_MPC8308RDB select ARCH_MPC8308 select SYS_FSL_ERRATUM_ESDHC111 -config TARGET_MPC8313ERDB - bool "Support MPC8313ERDB" +config TARGET_MPC8313ERDB_NOR + bool "Support MPC8313ERDB_NOR" + select ARCH_MPC8313 + select BOARD_EARLY_INIT_F + select SUPPORT_SPL + +config TARGET_MPC8313ERDB_NAND + bool "Support MPC8313ERDB_NAND" select ARCH_MPC8313 select BOARD_EARLY_INIT_F select SUPPORT_SPL diff --git a/board/freescale/mpc8313erdb/Kconfig b/board/freescale/mpc8313erdb/Kconfig index 145608feab..b6332a1368 100644 --- a/board/freescale/mpc8313erdb/Kconfig +++ b/board/freescale/mpc8313erdb/Kconfig @@ -1,4 +1,4 @@ -if TARGET_MPC8313ERDB +if TARGET_MPC8313ERDB_NOR config SYS_BOARD default "mpc8313erdb" @@ -7,6 +7,19 @@ config SYS_VENDOR default "freescale" config SYS_CONFIG_NAME - default "MPC8313ERDB" + default "MPC8313ERDB_NOR" + +endif + +if TARGET_MPC8313ERDB_NAND + +config SYS_BOARD + default "mpc8313erdb" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "MPC8313ERDB_NAND" endif diff --git a/configs/MPC8313ERDB_33_defconfig b/configs/MPC8313ERDB_33_defconfig index 3bb680c217..cacb5ba077 100644 --- a/configs/MPC8313ERDB_33_defconfig +++ b/configs/MPC8313ERDB_33_defconfig @@ -1,7 +1,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_MPC83xx=y -CONFIG_TARGET_MPC8313ERDB=y +CONFIG_TARGET_MPC8313ERDB_NOR=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SYS_33MHZ" diff --git a/configs/MPC8313ERDB_66_defconfig b/configs/MPC8313ERDB_66_defconfig index bb26a9e381..6b29c2e5c9 100644 --- a/configs/MPC8313ERDB_66_defconfig +++ b/configs/MPC8313ERDB_66_defconfig @@ -1,7 +1,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_MPC83xx=y -CONFIG_TARGET_MPC8313ERDB=y +CONFIG_TARGET_MPC8313ERDB_NOR=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SYS_66MHZ" diff --git a/configs/MPC8313ERDB_NAND_33_defconfig b/configs/MPC8313ERDB_NAND_33_defconfig index 44865711c2..bcb83b1308 100644 --- a/configs/MPC8313ERDB_NAND_33_defconfig +++ b/configs/MPC8313ERDB_NAND_33_defconfig @@ -3,7 +3,7 @@ CONFIG_SYS_TEXT_BASE=0x00100000 CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL=y CONFIG_MPC83xx=y -CONFIG_TARGET_MPC8313ERDB=y +CONFIG_TARGET_MPC8313ERDB_NAND=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SYS_33MHZ" diff --git a/configs/MPC8313ERDB_NAND_66_defconfig b/configs/MPC8313ERDB_NAND_66_defconfig index 83f0f6d01b..746ea27dc5 100644 --- a/configs/MPC8313ERDB_NAND_66_defconfig +++ b/configs/MPC8313ERDB_NAND_66_defconfig @@ -3,7 +3,7 @@ CONFIG_SYS_TEXT_BASE=0x00100000 CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL=y CONFIG_MPC83xx=y -CONFIG_TARGET_MPC8313ERDB=y +CONFIG_TARGET_MPC8313ERDB_NAND=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SYS_66MHZ" diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB_NAND.h similarity index 90% rename from include/configs/MPC8313ERDB.h rename to include/configs/MPC8313ERDB_NAND.h index c5a8065d6a..976b6854e4 100644 --- a/include/configs/MPC8313ERDB.h +++ b/include/configs/MPC8313ERDB_NAND.h @@ -15,7 +15,6 @@ #define CONFIG_E300 1 #define CONFIG_MPC8313ERDB 1 -#ifdef CONFIG_NAND #define CONFIG_SPL_INIT_MINIMAL #define CONFIG_SPL_FLUSH_IMAGE #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" @@ -40,8 +39,6 @@ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ #endif -#endif /* CONFIG_NAND */ - #ifndef CONFIG_SYS_MONITOR_BASE #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ #endif @@ -70,7 +67,7 @@ #define CONFIG_SYS_IMMR 0xE0000000 -#if defined(CONFIG_NAND) && !defined(CONFIG_SPL_BUILD) +#if !defined(CONFIG_SPL_BUILD) #define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR #endif @@ -184,11 +181,11 @@ #define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */ #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */ -#define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \ +#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE \ | BR_PS_16 /* 16 bit port */ \ | BR_MS_GPCM /* MSEL = GPCM */ \ | BR_V) /* valid */ -#define CONFIG_SYS_NOR_OR_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ +#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ | OR_GPCM_XACS \ | OR_GPCM_SCY_9 \ | OR_GPCM_EHTR \ @@ -235,7 +232,7 @@ #define CONFIG_SYS_LBC_MRTPR 0x20000000 /*TODO */ /* drivers/mtd/nand/raw/nand.c */ -#if defined(CONFIG_NAND) && defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_SPL_BUILD) #define CONFIG_SYS_NAND_BASE 0xFFF00000 #else #define CONFIG_SYS_NAND_BASE 0xE2800000 @@ -248,12 +245,12 @@ #define CONFIG_SYS_NAND_BLOCK_SIZE 16384 #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) -#define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \ +#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_NAND_BASE \ | BR_DECC_CHK_GEN /* Use HW ECC */ \ | BR_PS_8 /* 8 bit port */ \ | BR_MS_FCM /* MSEL = FCM */ \ | BR_V) /* valid */ -#define CONFIG_SYS_NAND_OR_PRELIM \ +#define CONFIG_SYS_OR0_PRELIM \ (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \ | OR_FCM_CSCT \ | OR_FCM_CST \ @@ -263,17 +260,9 @@ | OR_FCM_EHTR) /* 0xFFFF8396 */ -#ifdef CONFIG_NAND -#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM -#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM -#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NOR_BR_PRELIM -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NOR_OR_PRELIM -#else -#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM -#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM -#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM -#endif +/* Still needed for spl_minimal.c */ +#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR0_PRELIM +#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR0_PRELIM #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) @@ -407,25 +396,12 @@ /* * Environment */ -#if defined(CONFIG_NAND) - #define CONFIG_ENV_OFFSET (512 * 1024) - #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE - #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE - #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE - #define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4) - #define CONFIG_ENV_OFFSET_REDUND \ - (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE) -#elif !defined(CONFIG_SYS_RAMBOOT) - #define CONFIG_ENV_ADDR \ - (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) - #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ - #define CONFIG_ENV_SIZE 0x2000 - -/* Address and size of Redundant Environment Sector */ -#else - #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) - #define CONFIG_ENV_SIZE 0x2000 -#endif +#define CONFIG_ENV_OFFSET (512 * 1024) +#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE +#define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4) +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE) #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ @@ -499,17 +475,10 @@ HRCWH_TSEC2M_IN_RGMII |\ HRCWH_BIG_ENDIAN) -#ifdef CONFIG_NAND #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ HRCWH_FROM_0XFFF00100 |\ HRCWH_ROM_LOC_NAND_SP_8BIT |\ HRCWH_RL_EXT_NAND) -#else -#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ - HRCWH_FROM_0X00000100 |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_RL_EXT_LEGACY) -#endif /* System IO Config */ #define CONFIG_SYS_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */ diff --git a/include/configs/MPC8313ERDB_NOR.h b/include/configs/MPC8313ERDB_NOR.h new file mode 100644 index 0000000000..81e92fb939 --- /dev/null +++ b/include/configs/MPC8313ERDB_NOR.h @@ -0,0 +1,591 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) Freescale Semiconductor, Inc. 2006, 2010. + */ +/* + * mpc8313epb board configuration file + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_E300 1 +#define CONFIG_MPC8313ERDB 1 + +#ifndef CONFIG_SYS_MONITOR_BASE +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#endif + +#define CONFIG_PCI_INDIRECT_BRIDGE +#define CONFIG_FSL_ELBC 1 + +/* + * On-board devices + * + * TSEC1 is VSC switch + * TSEC2 is SoC TSEC + */ +#define CONFIG_VSC7385_ENET +#define CONFIG_TSEC2 + +#ifdef CONFIG_SYS_66MHZ +#define CONFIG_83XX_CLKIN 66666667 /* in Hz */ +#elif defined(CONFIG_SYS_33MHZ) +#define CONFIG_83XX_CLKIN 33333333 /* in Hz */ +#else +#error Unknown oscillator frequency. +#endif + +#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN + +#define CONFIG_SYS_IMMR 0xE0000000 + +#define CONFIG_SYS_MEMTEST_START 0x00001000 +#define CONFIG_SYS_MEMTEST_END 0x07f00000 + +/* Early revs of this board will lock up hard when attempting + * to access the PMC registers, unless a JTAG debugger is + * connected, or some resistor modifications are made. + */ +#define CONFIG_SYS_8313ERDB_BROKEN_PMC 1 + +#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ +#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ + +/* + * Device configurations + */ + +/* Vitesse 7385 */ + +#ifdef CONFIG_VSC7385_ENET + +#define CONFIG_TSEC1 + +/* The flash address and size of the VSC7385 firmware image */ +#define CONFIG_VSC7385_IMAGE 0xFE7FE000 +#define CONFIG_VSC7385_IMAGE_SIZE 8192 + +#endif + +/* + * DDR Setup + */ +#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE + +/* + * Manually set up DDR parameters, as this board does not + * seem to have the SPD connected to I2C. + */ +#define CONFIG_SYS_DDR_SIZE 128 /* MB */ +#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ + | CSCONFIG_ODT_RD_NEVER \ + | CSCONFIG_ODT_WR_ONLY_CURRENT \ + | CSCONFIG_ROW_BIT_13 \ + | CSCONFIG_COL_BIT_10) + /* 0x80010102 */ + +#define CONFIG_SYS_DDR_TIMING_3 0x00000000 +#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ + | (0 << TIMING_CFG0_WRT_SHIFT) \ + | (0 << TIMING_CFG0_RRT_SHIFT) \ + | (0 << TIMING_CFG0_WWT_SHIFT) \ + | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ + | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ + | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ + | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) + /* 0x00220802 */ +#define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \ + | (8 << TIMING_CFG1_ACTTOPRE_SHIFT) \ + | (3 << TIMING_CFG1_ACTTORW_SHIFT) \ + | (5 << TIMING_CFG1_CASLAT_SHIFT) \ + | (10 << TIMING_CFG1_REFREC_SHIFT) \ + | (3 << TIMING_CFG1_WRREC_SHIFT) \ + | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ + | (2 << TIMING_CFG1_WRTORD_SHIFT)) + /* 0x3835a322 */ +#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ + | (5 << TIMING_CFG2_CPO_SHIFT) \ + | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ + | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ + | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ + | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ + | (6 << TIMING_CFG2_FOUR_ACT_SHIFT)) + /* 0x129048c6 */ /* P9-45,may need tuning */ +#define CONFIG_SYS_DDR_INTERVAL ((1296 << SDRAM_INTERVAL_REFINT_SHIFT) \ + | (1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) + /* 0x05100500 */ +#if defined(CONFIG_DDR_2T_TIMING) +#define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \ + | SDRAM_CFG_SDRAM_TYPE_DDR2 \ + | SDRAM_CFG_DBW_32 \ + | SDRAM_CFG_2T_EN) + /* 0x43088000 */ +#else +#define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \ + | SDRAM_CFG_SDRAM_TYPE_DDR2 \ + | SDRAM_CFG_DBW_32) + /* 0x43080000 */ +#endif +#define CONFIG_SYS_SDRAM_CFG2 0x00401000 +/* set burst length to 8 for 32-bit data path */ +#define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \ + | (0x0632 << SDRAM_MODE_SD_SHIFT)) + /* 0x44480632 */ +#define CONFIG_SYS_DDR_MODE_2 0x8000C000 + +#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 + /*0x02000000*/ +#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ + | DDRCDR_PZ_NOMZ \ + | DDRCDR_NZ_NOMZ \ + | DDRCDR_M_ODR) + +/* + * FLASH on the Local Bus + */ +#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ +#define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */ +#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ +#define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */ + +#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ + | BR_PS_16 /* 16 bit port */ \ + | BR_MS_GPCM /* MSEL = GPCM */ \ + | BR_V) /* valid */ +#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ + | OR_GPCM_XACS \ + | OR_GPCM_SCY_9 \ + | OR_GPCM_EHTR \ + | OR_GPCM_EAD) + /* 0xFF006FF7 TODO SLOW 16 MB flash size */ + /* window base at flash base */ +#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE + /* 16 MB window size */ +#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_16MB) + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 135 /* sectors per device */ + +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && \ + !defined(CONFIG_SPL_BUILD) +#define CONFIG_SYS_RAMBOOT +#endif + +#define CONFIG_SYS_INIT_RAM_LOCK 1 +#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ + +#define CONFIG_SYS_GBL_DATA_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ +#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ + +/* + * Local Bus LCRR and LBCR regs + */ +#define CONFIG_SYS_LCRR_EADC LCRR_EADC_1 +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 +#define CONFIG_SYS_LBC_LBCR (0x00040000 /* TODO */ \ + | (0xFF << LBCR_BMT_SHIFT) \ + | 0xF) /* 0x0004ff0f */ + + /* LB refresh timer prescal, 266MHz/32 */ +#define CONFIG_SYS_LBC_MRTPR 0x20000000 /*TODO */ + +/* drivers/mtd/nand/nand.c */ +#define CONFIG_SYS_NAND_BASE 0xE2800000 + +#define CONFIG_MTD_PARTITION + +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_NAND_FSL_ELBC 1 +#define CONFIG_SYS_NAND_BLOCK_SIZE 16384 +#define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) + +#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \ + | BR_DECC_CHK_GEN /* Use HW ECC */ \ + | BR_PS_8 /* 8 bit port */ \ + | BR_MS_FCM /* MSEL = FCM */ \ + | BR_V) /* valid */ +#define CONFIG_SYS_OR1_PRELIM \ + (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \ + | OR_FCM_CSCT \ + | OR_FCM_CST \ + | OR_FCM_CHT \ + | OR_FCM_SCY_1 \ + | OR_FCM_TRLX \ + | OR_FCM_EHTR) + /* 0xFFFF8396 */ + +/* Still needed for spl_minimal.c */ +#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM +#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM + +#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE +#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) + +#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM +#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM + +/* local bus write LED / read status buffer (BCSR) mapping */ +#define CONFIG_SYS_BCSR_ADDR 0xFA000000 +#define CONFIG_SYS_BCSR_SIZE (32 * 1024) /* 0x00008000 */ + /* map at 0xFA000000 on LCS3 */ +#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_BCSR_ADDR \ + | BR_PS_8 /* 8 bit port */ \ + | BR_MS_GPCM /* MSEL = GPCM */ \ + | BR_V) /* valid */ + /* 0xFA000801 */ +#define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(CONFIG_SYS_BCSR_SIZE) \ + | OR_GPCM_CSNT \ + | OR_GPCM_ACS_DIV2 \ + | OR_GPCM_XACS \ + | OR_GPCM_SCY_15 \ + | OR_GPCM_TRLX_SET \ + | OR_GPCM_EHTR_SET \ + | OR_GPCM_EAD) + /* 0xFFFF8FF7 */ +#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_BCSR_ADDR +#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) + +/* Vitesse 7385 */ + +#ifdef CONFIG_VSC7385_ENET + + /* VSC7385 Base address on LCS2 */ +#define CONFIG_SYS_VSC7385_BASE 0xF0000000 +#define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */ + +#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE \ + | BR_PS_8 /* 8 bit port */ \ + | BR_MS_GPCM /* MSEL = GPCM */ \ + | BR_V) /* valid */ +#define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \ + | OR_GPCM_CSNT \ + | OR_GPCM_XACS \ + | OR_GPCM_SCY_15 \ + | OR_GPCM_SETA \ + | OR_GPCM_TRLX_SET \ + | OR_GPCM_EHTR_SET \ + | OR_GPCM_EAD) + /* 0xFFFE09FF */ + + /* Access window base at VSC7385 base */ +#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE +#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) + +#endif + +#define CONFIG_MPC83XX_GPIO 1 + +/* + * Serial Port + */ +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_FSL +#define CONFIG_SYS_FSL_I2C_SPEED 400000 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_FSL_I2C2_SPEED 400000 +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 +#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } + +/* + * General PCI + * Addresses are mapped 1-1. + */ +#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 +#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE +#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 +#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE +#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCI1_IO_BASE 0x00000000 +#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 +#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ + +#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ + +/* + * TSEC + */ + +#define CONFIG_GMII /* MII PHY management */ + +#ifdef CONFIG_TSEC1 +#define CONFIG_HAS_ETH0 +#define CONFIG_TSEC1_NAME "TSEC0" +#define CONFIG_SYS_TSEC1_OFFSET 0x24000 +#define TSEC1_PHY_ADDR 0x1c +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC1_PHYIDX 0 +#endif + +#ifdef CONFIG_TSEC2 +#define CONFIG_HAS_ETH1 +#define CONFIG_TSEC2_NAME "TSEC1" +#define CONFIG_SYS_TSEC2_OFFSET 0x25000 +#define TSEC2_PHY_ADDR 4 +#define TSEC2_FLAGS TSEC_GIGABIT +#define TSEC2_PHYIDX 0 +#endif + +/* Options are: TSEC[0-1] */ +#define CONFIG_ETHPRIME "TSEC1" + +/* + * Configure on-board RTC + */ +#define CONFIG_RTC_DS1337 +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 + +/* + * Environment + */ +#if !defined(CONFIG_SYS_RAMBOOT) + #define CONFIG_ENV_ADDR \ + (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) + #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ + #define CONFIG_ENV_SIZE 0x2000 + +/* Address and size of Redundant Environment Sector */ +#else + #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) + #define CONFIG_ENV_SIZE 0x2000 +#endif + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE + +/* + * Command line configuration. + */ + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ + + /* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +/* + * For booting Linux, the board info and command line data + * have to be in the first 256 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ + /* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ + +#ifdef CONFIG_SYS_66MHZ + +/* 66MHz IN, 133MHz CSB, 266 DDR, 266 CORE */ +/* 0x62040000 */ +#define CONFIG_SYS_HRCW_LOW (\ + 0x20000000 /* reserved, must be set */ |\ + HRCWL_DDRCM |\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ + HRCWL_DDR_TO_SCB_CLK_2X1 |\ + HRCWL_CSB_TO_CLKIN_2X1 |\ + HRCWL_CORE_TO_CSB_2X1) + +#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2) + +#elif defined(CONFIG_SYS_33MHZ) + +/* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */ +/* 0x65040000 */ +#define CONFIG_SYS_HRCW_LOW (\ + 0x20000000 /* reserved, must be set */ |\ + HRCWL_DDRCM |\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ + HRCWL_DDR_TO_SCB_CLK_2X1 |\ + HRCWL_CSB_TO_CLKIN_5X1 |\ + HRCWL_CORE_TO_CSB_2X1) + +#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 5) + +#endif + +#define CONFIG_SYS_HRCW_HIGH_BASE (\ + HRCWH_PCI_HOST |\ + HRCWH_PCI1_ARBITER_ENABLE |\ + HRCWH_CORE_ENABLE |\ + HRCWH_BOOTSEQ_DISABLE |\ + HRCWH_SW_WATCHDOG_DISABLE |\ + HRCWH_TSEC1M_IN_RGMII |\ + HRCWH_TSEC2M_IN_RGMII |\ + HRCWH_BIG_ENDIAN) + +#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ + HRCWH_FROM_0X00000100 |\ + HRCWH_ROM_LOC_LOCAL_16BIT |\ + HRCWH_RL_EXT_LEGACY) + +/* System IO Config */ +#define CONFIG_SYS_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */ + /* Enable Internal USB Phy and GPIO on LCD Connector */ +#define CONFIG_SYS_SICRL (SICRL_USBDR_10 | SICRL_LBC) + +#define CONFIG_SYS_HID0_INIT 0x000000000 +#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ + HID0_ENABLE_INSTRUCTION_CACHE | \ + HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) + +#define CONFIG_SYS_HID2 HID2_HBE + +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + +/* DDR @ 0x00000000 */ +#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW) +#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ + | BATU_BL_256M \ + | BATU_VS \ + | BATU_VP) + +/* PCI @ 0x80000000 */ +#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW) +#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ + | BATU_BL_256M \ + | BATU_VS \ + | BATU_VP) +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ + | BATL_PP_RW \ + | BATL_CACHEINHIBIT \ + | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ + | BATU_BL_256M \ + | BATU_VS \ + | BATU_VP) + +/* PCI2 not supported on 8313 */ +#define CONFIG_SYS_IBAT3L (0) +#define CONFIG_SYS_IBAT3U (0) +#define CONFIG_SYS_IBAT4L (0) +#define CONFIG_SYS_IBAT4U (0) + +/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ +#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ + | BATL_PP_RW \ + | BATL_CACHEINHIBIT \ + | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ + | BATU_BL_256M \ + | BATU_VS \ + | BATU_VP) + +/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ +#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) + +#define CONFIG_SYS_IBAT7L (0) +#define CONFIG_SYS_IBAT7U (0) + +#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L +#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U +#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L +#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U +#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L +#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U +#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L +#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U +#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L +#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U +#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L +#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U +#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L +#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U +#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L +#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U + +/* + * Environment Configuration + */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_NETDEV "eth1" + +#define CONFIG_HOSTNAME "mpc8313erdb" +#define CONFIG_ROOTPATH "/nfs/root/path" +#define CONFIG_BOOTFILE "uImage" + /* U-Boot image on TFTP server */ +#define CONFIG_UBOOTPATH "u-boot.bin" +#define CONFIG_FDTFILE "mpc8313erdb.dtb" + + /* default location for tftp and bootm */ +#define CONFIG_LOADADDR 800000 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=" CONFIG_NETDEV "\0" \ + "ethprime=TSEC1\0" \ + "uboot=" CONFIG_UBOOTPATH "\0" \ + "tftpflash=tftpboot $loadaddr $uboot; " \ + "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ + " +$filesize; " \ + "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ + " +$filesize; " \ + "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ + " $filesize; " \ + "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ + " +$filesize; " \ + "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ + " $filesize\0" \ + "fdtaddr=780000\0" \ + "fdtfile=" CONFIG_FDTFILE "\0" \ + "console=ttyS0\0" \ + "setbootargs=setenv bootargs " \ + "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \ + "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\ + "$netdev:off " \ + "root=$rootdev rw console=$console,$baudrate $othbootargs\0" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv rootdev /dev/nfs;" \ + "run setbootargs;" \ + "run setipargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv rootdev /dev/ram;" \ + "run setbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#endif /* __CONFIG_H */ From c2a446048e7682296b8054ed81e12639099d5a56 Mon Sep 17 00:00:00 2001 From: Mario Six Date: Mon, 21 Jan 2019 09:17:37 +0100 Subject: [PATCH 14/86] vme8349: Migrate to CONFIG_TARGET_VME8349 CONFIG_TARGET_VME8349 can replace CONFIG_VME8349. Hence, replace CONFIG_VME8349 with CONFIG_TARGET_VME8349, and remove CONFIG_VME8349. Signed-off-by: Mario Six --- drivers/pci/pci_auto.c | 2 +- drivers/pci/pci_auto_old.c | 2 +- include/configs/vme8349.h | 1 - 3 files changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/pci/pci_auto.c b/drivers/pci/pci_auto.c index a673d8ae13..f5e46842bf 100644 --- a/drivers/pci/pci_auto.c +++ b/drivers/pci/pci_auto.c @@ -359,7 +359,7 @@ int dm_pciauto_config_device(struct udevice *dev) PCI_DEV(dm_pci_get_bdf(dev))); break; #endif -#if defined(CONFIG_ARCH_MPC834X) && !defined(CONFIG_VME8349) +#if defined(CONFIG_ARCH_MPC834X) && !defined(CONFIG_TARGET_VME8349) case PCI_CLASS_BRIDGE_OTHER: /* * The host/PCI bridge 1 seems broken in 8349 - it presents diff --git a/drivers/pci/pci_auto_old.c b/drivers/pci/pci_auto_old.c index 90c22a08cb..6ab1b3b43f 100644 --- a/drivers/pci/pci_auto_old.c +++ b/drivers/pci/pci_auto_old.c @@ -376,7 +376,7 @@ int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev) PCI_DEV(dev)); break; #endif -#if defined(CONFIG_ARCH_MPC834X) && !defined(CONFIG_VME8349) +#if defined(CONFIG_ARCH_MPC834X) && !defined(CONFIG_TARGET_VME8349) case PCI_CLASS_BRIDGE_OTHER: /* * The host/PCI bridge 1 seems broken in 8349 - it presents diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h index 5695550130..fe570abf8f 100644 --- a/include/configs/vme8349.h +++ b/include/configs/vme8349.h @@ -28,7 +28,6 @@ * High Level Configuration Options */ #define CONFIG_E300 1 /* E300 Family */ -#define CONFIG_VME8349 1 /* ESD VME8349 board specific */ /* Don't enable PCI2 on vme834x - it doesn't exist physically. */ #undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */ From 904c47fc7d09c33fb4e43f30ddf2039fa7a0a168 Mon Sep 17 00:00:00 2001 From: Mario Six Date: Mon, 21 Jan 2019 09:17:38 +0100 Subject: [PATCH 15/86] mpc83xx: Make distinct caddy2 config vme8349.h contains two separate boards: The vme8349 itself, and the caddy2 board. The caddy2 board is chosen by setting certain config variables. Create a proper config file for the caddy2 board to make Kconfig migration easier. Furthermore, simplify the vme8349 and caddy2 configs by keeping only the options necessary for each board. Signed-off-by: Mario Six --- arch/powerpc/cpu/mpc83xx/Kconfig | 4 + board/esd/vme8349/Kconfig | 13 + board/esd/vme8349/vme8349.c | 8 +- configs/caddy2_defconfig | 3 +- drivers/pci/pci_auto.c | 3 +- drivers/pci/pci_auto_old.c | 3 +- include/configs/caddy2.h | 512 +++++++++++++++++++++++++++++++ include/configs/vme8349.h | 29 -- 8 files changed, 538 insertions(+), 37 deletions(-) create mode 100644 include/configs/caddy2.h diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index ede98c70da..65f4583ffe 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -24,6 +24,10 @@ config TARGET_VME8349 bool "Support vme8349" select ARCH_MPC8349 +config TARGET_CADDY2 + bool "Support caddy2" + select ARCH_MPC8349 + config TARGET_MPC8308RDB bool "Support MPC8308RDB" select ARCH_MPC8308 diff --git a/board/esd/vme8349/Kconfig b/board/esd/vme8349/Kconfig index b8d9432dcc..ef2af40f7e 100644 --- a/board/esd/vme8349/Kconfig +++ b/board/esd/vme8349/Kconfig @@ -10,3 +10,16 @@ config SYS_CONFIG_NAME default "vme8349" endif + +if TARGET_CADDY2 + +config SYS_BOARD + default "vme8349" + +config SYS_VENDOR + default "esd" + +config SYS_CONFIG_NAME + default "caddy2" + +endif diff --git a/board/esd/vme8349/vme8349.c b/board/esd/vme8349/vme8349.c index 45ad3a83ee..a46d0b6da6 100644 --- a/board/esd/vme8349/vme8349.c +++ b/board/esd/vme8349/vme8349.c @@ -60,7 +60,7 @@ int dram_init(void) int checkboard(void) { -#ifdef VME_CADDY2 +#ifdef CONFIG_TARGET_CADDY2 puts("Board: esd VME-CADDY/2\n"); #else puts("Board: esd VME-CPU/8349\n"); @@ -69,7 +69,7 @@ int checkboard(void) return 0; } -#ifdef VME_CADDY2 +#ifdef CONFIG_TARGET_CADDY2 int board_eth_init(bd_t *bis) { return pci_eth_init(bis); @@ -102,7 +102,7 @@ int misc_init_r() * Provide SPD values for spd_sdram(). Both boards (VME-CADDY/2 * and VME-CADDY/2) have different SDRAM configurations. */ -#ifdef VME_CADDY2 +#ifdef CONFIG_TARGET_CADDY2 #define SMALL_RAM 0xff #define LARGE_RAM 0x00 #else @@ -165,7 +165,7 @@ static spd_eeprom_t default_spd_eeprom = { SPD_VAL(0x7e, 0x1d), /* 63 */ { 'e', 's', 'd', '-', 'g', 'm', 'b', 'h' }, SPD_VAL(0x00, 0x00), /* 72 */ -#ifdef VME_CADDY2 +#ifdef CONFIG_TARGET_CADDY2 { "vme-caddy/2 ram " } #else { "vme-cpu/2 ram " } diff --git a/configs/caddy2_defconfig b/configs/caddy2_defconfig index 5fec4f8d49..fe0c34fc61 100644 --- a/configs/caddy2_defconfig +++ b/configs/caddy2_defconfig @@ -1,10 +1,9 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFFF00000 CONFIG_MPC83xx=y -CONFIG_TARGET_VME8349=y +CONFIG_TARGET_CADDY2=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="CADDY2" CONFIG_BOOTDELAY=6 CONFIG_MISC_INIT_R=y CONFIG_HUSH_PARSER=y diff --git a/drivers/pci/pci_auto.c b/drivers/pci/pci_auto.c index f5e46842bf..1a3bf70834 100644 --- a/drivers/pci/pci_auto.c +++ b/drivers/pci/pci_auto.c @@ -359,7 +359,8 @@ int dm_pciauto_config_device(struct udevice *dev) PCI_DEV(dm_pci_get_bdf(dev))); break; #endif -#if defined(CONFIG_ARCH_MPC834X) && !defined(CONFIG_TARGET_VME8349) +#if defined(CONFIG_ARCH_MPC834X) && !defined(CONFIG_TARGET_VME8349) && \ + !defined(CONFIG_TARGET_CADDY2) case PCI_CLASS_BRIDGE_OTHER: /* * The host/PCI bridge 1 seems broken in 8349 - it presents diff --git a/drivers/pci/pci_auto_old.c b/drivers/pci/pci_auto_old.c index 6ab1b3b43f..b566705c9d 100644 --- a/drivers/pci/pci_auto_old.c +++ b/drivers/pci/pci_auto_old.c @@ -376,7 +376,8 @@ int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev) PCI_DEV(dev)); break; #endif -#if defined(CONFIG_ARCH_MPC834X) && !defined(CONFIG_TARGET_VME8349) +#if defined(CONFIG_ARCH_MPC834X) && !defined(CONFIG_TARGET_VME8349) && \ + !defined(CONFIG_TARGET_CADDY2) case PCI_CLASS_BRIDGE_OTHER: /* * The host/PCI bridge 1 seems broken in 8349 - it presents diff --git a/include/configs/caddy2.h b/include/configs/caddy2.h new file mode 100644 index 0000000000..a7bbbbdd0b --- /dev/null +++ b/include/configs/caddy2.h @@ -0,0 +1,512 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * esd vme8349 U-Boot configuration file + * Copyright (c) 2008, 2009 esd gmbh Hannover Germany + * + * (C) Copyright 2006-2010 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * reinhard.arlt@esd-electronics.de + * Based on the MPC8349EMDS config. + */ + +/* + * vme8349 board configuration file. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_E300 1 /* E300 Family */ + +/* Don't enable PCI2 on vme834x - it doesn't exist physically. */ +#undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */ + +#define CONFIG_PCI_66M +#ifdef CONFIG_PCI_66M +#define CONFIG_83XX_CLKIN 66000000 /* in Hz */ +#else +#define CONFIG_83XX_CLKIN 33000000 /* in Hz */ +#endif + +#ifndef CONFIG_SYS_CLK_FREQ +#ifdef CONFIG_PCI_66M +#define CONFIG_SYS_CLK_FREQ 66000000 +#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1 +#else +#define CONFIG_SYS_CLK_FREQ 33000000 +#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1 +#endif +#endif + +#define CONFIG_SYS_IMMR 0xE0000000 + +#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ +#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ +#define CONFIG_SYS_MEMTEST_END 0x00100000 + +/* + * DDR Setup + */ +#define CONFIG_DDR_ECC /* only for ECC DDR module */ +#define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ +#define CONFIG_SPD_EEPROM +#define SPD_EEPROM_ADDRESS 0x54 +#define CONFIG_SYS_READ_SPD vme8349_read_spd +#define CONFIG_SYS_83XX_DDR_USES_CS0 /* esd; Fsl board uses CS2/CS3 */ + +/* + * 32-bit data path mode. + * + * Please note that using this mode for devices with the real density of 64-bit + * effectively reduces the amount of available memory due to the effect of + * wrapping around while translating address to row/columns, for example in the + * 256MB module the upper 128MB get aliased with contents of the lower + * 128MB); normally this define should be used for devices with real 32-bit + * data path. + */ +#undef CONFIG_DDR_32BIT + +#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is sys memory*/ +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ + | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) +#define CONFIG_DDR_2T_TIMING +#define CONFIG_SYS_DDRCDR (DDRCDR_DHC_EN \ + | DDRCDR_ODT \ + | DDRCDR_Q_DRN) + /* 0x80080001 */ + +/* + * FLASH on the Local Bus + */ +#define CONFIG_SYS_FLASH_BASE 0xffc00000 /* start of FLASH */ +#define CONFIG_SYS_FLASH_SIZE 4 /* flash size in MB */ +#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ + BR_PS_16 | /* 16bit */ \ + BR_MS_GPCM | /* MSEL = GPCM */ \ + BR_V) /* valid */ + +#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ + | OR_GPCM_XAM \ + | OR_GPCM_CSNT \ + | OR_GPCM_ACS_DIV2 \ + | OR_GPCM_XACS \ + | OR_GPCM_SCY_15 \ + | OR_GPCM_TRLX_SET \ + | OR_GPCM_EHTR_SET \ + | OR_GPCM_EAD) + /* 0xffc06ff7 */ +#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_4MB) + +#define CONFIG_SYS_WINDOW1_BASE 0xf0000000 +#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_WINDOW1_BASE \ + | BR_PS_32 \ + | BR_MS_GPCM \ + | BR_V) + /* 0xF0001801 */ +#define CONFIG_SYS_OR1_PRELIM (OR_AM_256KB \ + | OR_GPCM_SETA) + /* 0xfffc0208 */ +#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_WINDOW1_BASE +#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_256KB) + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device*/ + +#undef CONFIG_SYS_FLASH_CHECKSUM +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase TO (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write TO (ms) */ + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ + +#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) +#define CONFIG_SYS_RAMBOOT +#else +#undef CONFIG_SYS_RAMBOOT +#endif + +#define CONFIG_SYS_INIT_RAM_LOCK 1 +#define CONFIG_SYS_INIT_RAM_ADDR 0xF7000000 /* Initial RAM addr */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* size */ + +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB */ +#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Malloc size */ + +/* + * Local Bus LCRR and LBCR regs + * LCRR: no DLL bypass, Clock divider is 4 + * External Local Bus rate is + * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV + */ +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 +#define CONFIG_SYS_LBC_LBCR 0x00000000 + +#undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */ + +/* + * Serial Port + */ +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_FSL +#define CONFIG_SYS_FSL_I2C_SPEED 400000 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_FSL_I2C2_SPEED 400000 +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 +#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } +/* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */ + +#define CONFIG_SYS_I2C_8574_ADDR2 0x20 /* I2C1, PCF8574 */ + +/* TSEC */ +#define CONFIG_SYS_TSEC1_OFFSET 0x24000 +#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) +#define CONFIG_SYS_TSEC2_OFFSET 0x25000 +#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET) + +/* + * General PCI + * Addresses are mapped 1-1. + */ +#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 +#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE +#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 +#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE +#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCI1_IO_BASE 0x00000000 +#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 +#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ + +#define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000 +#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE +#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000 +#define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE +#define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCI2_IO_BASE 0x00000000 +#define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000 +#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ + +#if defined(CONFIG_PCI) + +#define PCI_64BIT +#define PCI_ONE_PCI1 +#if defined(PCI_64BIT) +#undef PCI_ALL_PCI1 +#undef PCI_TWO_PCI1 +#undef PCI_ONE_PCI1 +#endif + +#undef CONFIG_EEPRO100 +#undef CONFIG_TULIP + +#if !defined(CONFIG_PCI_PNP) + #define PCI_ENET0_IOADDR 0xFIXME + #define PCI_ENET0_MEMADDR 0xFIXME + #define PCI_IDSEL_NUMBER 0xFIXME +#endif + +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ + +#endif /* CONFIG_PCI */ + +/* + * TSEC configuration + */ + +#if defined(CONFIG_TSEC_ENET) + +#define CONFIG_GMII /* MII PHY management */ +#define CONFIG_TSEC1 +#define CONFIG_TSEC1_NAME "TSEC0" +#define CONFIG_TSEC2 +#define CONFIG_TSEC2_NAME "TSEC1" +#define CONFIG_PHY_M88E1111 +#define TSEC1_PHY_ADDR 0x08 +#define TSEC2_PHY_ADDR 0x10 +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC2_FLAGS TSEC_GIGABIT + +/* Options are: TSEC[0-1] */ +#define CONFIG_ETHPRIME "TSEC0" + +#endif /* CONFIG_TSEC_ENET */ + +/* + * Environment + */ +#ifndef CONFIG_SYS_RAMBOOT + #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0xc0000) + #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ + #define CONFIG_ENV_SIZE 0x2000 + +/* Address and size of Redundant Environment Sector */ +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) + +#else + #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) + #define CONFIG_ENV_SIZE 0x2000 +#endif + +#define CONFIG_LOADS_ECHO /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE + +/* + * Command line configuration. + */ +#define CONFIG_SYS_RTC_BUS_NUM 0x01 +#define CONFIG_SYS_I2C_RTC_ADDR 0x32 +#define CONFIG_RTC_RX8025 + +/* Pass Ethernet MAC to VxWorks */ +#define CONFIG_SYS_VXWORKS_MAC_PTR 0x000043f0 + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 256 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Init Memory map for Linux*/ + +#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ + +#define CONFIG_SYS_HRCW_LOW (\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ + HRCWL_DDR_TO_SCB_CLK_1X1 |\ + HRCWL_CSB_TO_CLKIN |\ + HRCWL_VCO_1X2 |\ + HRCWL_CORE_TO_CSB_2X1) + +#if defined(PCI_64BIT) +#define CONFIG_SYS_HRCW_HIGH (\ + HRCWH_PCI_HOST |\ + HRCWH_64_BIT_PCI |\ + HRCWH_PCI1_ARBITER_ENABLE |\ + HRCWH_PCI2_ARBITER_DISABLE |\ + HRCWH_CORE_ENABLE |\ + HRCWH_FROM_0X00000100 |\ + HRCWH_BOOTSEQ_DISABLE |\ + HRCWH_SW_WATCHDOG_DISABLE |\ + HRCWH_ROM_LOC_LOCAL_16BIT |\ + HRCWH_TSEC1M_IN_GMII |\ + HRCWH_TSEC2M_IN_GMII) +#else +#define CONFIG_SYS_HRCW_HIGH (\ + HRCWH_PCI_HOST |\ + HRCWH_32_BIT_PCI |\ + HRCWH_PCI1_ARBITER_ENABLE |\ + HRCWH_PCI2_ARBITER_ENABLE |\ + HRCWH_CORE_ENABLE |\ + HRCWH_FROM_0X00000100 |\ + HRCWH_BOOTSEQ_DISABLE |\ + HRCWH_SW_WATCHDOG_DISABLE |\ + HRCWH_ROM_LOC_LOCAL_16BIT |\ + HRCWH_TSEC1M_IN_GMII |\ + HRCWH_TSEC2M_IN_GMII) +#endif + +/* System IO Config */ +#define CONFIG_SYS_SICRH 0 +#define CONFIG_SYS_SICRL SICRL_LDP_A + +#define CONFIG_SYS_HID0_INIT 0x000000000 +#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ + HID0_ENABLE_INSTRUCTION_CACHE) + +#define CONFIG_SYS_HID2 HID2_HBE + +#define CONFIG_SYS_GPIO1_PRELIM +#define CONFIG_SYS_GPIO1_DIR 0x00100000 +#define CONFIG_SYS_GPIO1_DAT 0x00100000 + +#define CONFIG_SYS_GPIO2_PRELIM +#define CONFIG_SYS_GPIO2_DIR 0x78900000 +#define CONFIG_SYS_GPIO2_DAT 0x70100000 + +#define CONFIG_HIGH_BATS /* High BATs supported */ + +/* DDR @ 0x00000000 */ +#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \ + BATU_VS | BATU_VP) + +/* PCI @ 0x80000000 */ +#ifdef CONFIG_PCI +#define CONFIG_PCI_INDIRECT_BRIDGE +#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | \ + BATU_VS | BATU_VP) +#else +#define CONFIG_SYS_IBAT1L (0) +#define CONFIG_SYS_IBAT1U (0) +#define CONFIG_SYS_IBAT2L (0) +#define CONFIG_SYS_IBAT2U (0) +#endif + +#ifdef CONFIG_MPC83XX_PCI2 +#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_RW | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | \ + BATU_VS | BATU_VP) +#else +#define CONFIG_SYS_IBAT3L (0) +#define CONFIG_SYS_IBAT3U (0) +#define CONFIG_SYS_IBAT4L (0) +#define CONFIG_SYS_IBAT4U (0) +#endif + +/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */ +#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | \ + BATU_VS | BATU_VP) + +#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) + +#if (CONFIG_SYS_DDR_SIZE == 512) +#define CONFIG_SYS_IBAT7L (CONFIG_SYS_SDRAM_BASE+0x10000000 | \ + BATL_PP_RW | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT7U (CONFIG_SYS_SDRAM_BASE+0x10000000 | \ + BATU_BL_256M | BATU_VS | BATU_VP) +#else +#define CONFIG_SYS_IBAT7L (0) +#define CONFIG_SYS_IBAT7U (0) +#endif + +#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L +#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U +#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L +#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U +#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L +#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U +#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L +#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U +#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L +#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U +#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L +#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U +#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L +#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U +#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L +#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ +#endif + +/* + * Environment Configuration + */ +#define CONFIG_ENV_OVERWRITE + +#if defined(CONFIG_TSEC_ENET) +#define CONFIG_HAS_ETH0 +#define CONFIG_HAS_ETH1 +#endif + +#define CONFIG_HOSTNAME "VME8349" +#define CONFIG_ROOTPATH "/tftpboot/rootfs" +#define CONFIG_BOOTFILE "uImage" + +#define CONFIG_LOADADDR 800000 /* def location for tftp and bootm */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "hostname=vme8349\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ + "flash_nfs=run nfsargs addip addtty;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip addtty;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ + "bootm\0" \ + "load=tftp 100000 /tftpboot/bdi2000/vme8349.bin\0" \ + "update=protect off fff00000 fff3ffff; " \ + "era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \ + "upd=run load update\0" \ + "fdtaddr=780000\0" \ + "fdtfile=vme8349.dtb\0" \ + "" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ + "$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_BOOTCOMMAND "run flash_self" + +#ifndef __ASSEMBLY__ +int vme8349_read_spd(unsigned char chip, unsigned int addr, int alen, + unsigned char *buffer, int len); +#endif + +#endif /* __CONFIG_H */ diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h index fe570abf8f..6c3ad76e52 100644 --- a/include/configs/vme8349.h +++ b/include/configs/vme8349.h @@ -17,13 +17,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -/* - * Top level Makefile configuration choices - */ -#ifdef CONFIG_CADDY2 -#define VME_CADDY2 -#endif - /* * High Level Configuration Options */ @@ -91,27 +84,6 @@ /* * FLASH on the Local Bus */ -#ifdef VME_CADDY2 -#define CONFIG_SYS_FLASH_BASE 0xffc00000 /* start of FLASH */ -#define CONFIG_SYS_FLASH_SIZE 4 /* flash size in MB */ -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ - BR_PS_16 | /* 16bit */ \ - BR_MS_GPCM | /* MSEL = GPCM */ \ - BR_V) /* valid */ - -#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ - | OR_GPCM_XAM \ - | OR_GPCM_CSNT \ - | OR_GPCM_ACS_DIV2 \ - | OR_GPCM_XACS \ - | OR_GPCM_SCY_15 \ - | OR_GPCM_TRLX_SET \ - | OR_GPCM_EHTR_SET \ - | OR_GPCM_EAD) - /* 0xffc06ff7 */ -#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_4MB) -#else #define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH */ #define CONFIG_SYS_FLASH_SIZE 128 /* flash size in MB */ #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ @@ -131,7 +103,6 @@ /* 0xf8006ff7 */ #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_128MB) -#endif #define CONFIG_SYS_WINDOW1_BASE 0xf0000000 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_WINDOW1_BASE \ From 10590363b55658029616aa79694880a30a9764c3 Mon Sep 17 00:00:00 2001 From: Mario Six Date: Mon, 21 Jan 2019 09:17:39 +0100 Subject: [PATCH 16/86] powerpc: Add LSDMR config values The LSDMR_* macros are used to configure the system bus on MPC83xx. A few of the possible LSDMR_* macros were never defined in the respective include files. This renders the SDRAM support on the MPC8349EMDS unusable, because it uses these undefined macros. To make the SDRAM option work, introduce these macros into the proper config file. Signed-off-by: Mario Six --- arch/powerpc/include/asm/fsl_lbc.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/powerpc/include/asm/fsl_lbc.h b/arch/powerpc/include/asm/fsl_lbc.h index 3528acd627..bf352d9a56 100644 --- a/arch/powerpc/include/asm/fsl_lbc.h +++ b/arch/powerpc/include/asm/fsl_lbc.h @@ -428,14 +428,17 @@ void lbc_sdram_init(void); #define LSDMR_BSMA1516 (3 << (31 - 10)) #define LSDMR_BSMA1617 (4 << (31 - 10)) #define LSDMR_RFCR5 (3 << (31 - 16)) +#define LSDMR_RFCR8 (5 << (31 - 16)) #define LSDMR_RFCR16 (7 << (31 - 16)) #define LSDMR_PRETOACT3 (3 << (31 - 19)) +#define LSDMR_PRETOACT6 (5 << (31 - 19)) #define LSDMR_PRETOACT7 (7 << (31 - 19)) #define LSDMR_ACTTORW3 (3 << (31 - 22)) #define LSDMR_ACTTORW7 (7 << (31 - 22)) #define LSDMR_ACTTORW6 (6 << (31 - 22)) #define LSDMR_BL8 (1 << (31 - 23)) #define LSDMR_WRC2 (2 << (31 - 27)) +#define LSDMR_WRC3 (3 << (31 - 27)) #define LSDMR_WRC4 (0 << (31 - 27)) #define LSDMR_BUFCMD (1 << (31 - 29)) #define LSDMR_CL3 (3 << (31 - 31)) From ddc935fc093ffacd9aeeb8fe12cd7ebeeefc87dd Mon Sep 17 00:00:00 2001 From: Mario Six Date: Mon, 21 Jan 2019 09:17:40 +0100 Subject: [PATCH 17/86] mpc83xx: Make distinct MPC8349EMDS_SDRAM board The MPC8349EMDS config file contains config options to enable SDRAM support. To keep this ability after the Kconfig migration, create a new MPC8349EMDS_SDRAM board that enables the SDRAM support and remove the SDRAM support from the original board. Signed-off-by: Mario Six --- arch/powerpc/cpu/mpc83xx/Kconfig | 8 + board/freescale/mpc8349emds/Kconfig | 13 + board/freescale/mpc8349emds/MAINTAINERS | 1 + configs/MPC8349EMDS_SDRAM_defconfig | 27 + include/configs/MPC8349EMDS.h | 76 --- include/configs/MPC8349EMDS_SDRAM.h | 731 ++++++++++++++++++++++++ 6 files changed, 780 insertions(+), 76 deletions(-) create mode 100644 configs/MPC8349EMDS_SDRAM_defconfig create mode 100644 include/configs/MPC8349EMDS_SDRAM.h diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index 65f4583ffe..0ce1aad6d0 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -67,6 +67,14 @@ config TARGET_MPC8349EMDS select SYS_FSL_DDR_BE select SYS_FSL_HAS_DDR2 +config TARGET_MPC8349EMDS_SDRAM + bool "Support MPC8349EMDS_SDRAM" + select ARCH_MPC8349 + select BOARD_EARLY_INIT_F + select SYS_FSL_DDR + select SYS_FSL_DDR_BE + select SYS_FSL_HAS_DDR2 + config TARGET_MPC8349ITX bool "Support MPC8349ITX" select ARCH_MPC8349 diff --git a/board/freescale/mpc8349emds/Kconfig b/board/freescale/mpc8349emds/Kconfig index 51f0b34f39..d154118079 100644 --- a/board/freescale/mpc8349emds/Kconfig +++ b/board/freescale/mpc8349emds/Kconfig @@ -10,3 +10,16 @@ config SYS_CONFIG_NAME default "MPC8349EMDS" endif + +if TARGET_MPC8349EMDS_SDRAM + +config SYS_BOARD + default "mpc8349emds" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "MPC8349EMDS_SDRAM" + +endif diff --git a/board/freescale/mpc8349emds/MAINTAINERS b/board/freescale/mpc8349emds/MAINTAINERS index e6648d66a0..b676c07492 100644 --- a/board/freescale/mpc8349emds/MAINTAINERS +++ b/board/freescale/mpc8349emds/MAINTAINERS @@ -4,3 +4,4 @@ S: Orphan (since 2018-05) F: board/freescale/mpc8349emds/ F: include/configs/MPC8349EMDS.h F: configs/MPC8349EMDS_defconfig +F: configs/MPC8349EMDS_SDRAM_defconfig diff --git a/configs/MPC8349EMDS_SDRAM_defconfig b/configs/MPC8349EMDS_SDRAM_defconfig new file mode 100644 index 0000000000..2607dfa4f3 --- /dev/null +++ b/configs/MPC8349EMDS_SDRAM_defconfig @@ -0,0 +1,27 @@ +CONFIG_PPC=y +CONFIG_SYS_TEXT_BASE=0xFE000000 +CONFIG_MPC83xx=y +CONFIG_TARGET_MPC8349EMDS_SDRAM=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_BOOTDELAY=6 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_IMLS=y +CONFIG_CMD_I2C=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_DATE=y +# CONFIG_MMC is not set +CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_CFI_DRIVER=y +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y +CONFIG_SYS_FLASH_CFI=y +CONFIG_PHY_MARVELL=y +CONFIG_NETDEVICES=y +CONFIG_TSEC_ENET=y +# CONFIG_PCI is not set +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_MPC8XXX_SPI=y +CONFIG_OF_LIBFDT=y diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 93de2cc1c0..fe2b81b905 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -218,82 +218,6 @@ #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 #define CONFIG_SYS_LBC_LBCR 0x00000000 -/* - * The MPC834xEA MDS for 834xE rev3.1 may not be assembled SDRAM memory. - * if board has SRDAM on local bus, you can define CONFIG_SYS_LB_SDRAM - */ -#undef CONFIG_SYS_LB_SDRAM - -#ifdef CONFIG_SYS_LB_SDRAM -/* Local bus BR2, OR2 definition for SDRAM if soldered on the MDS board */ -/* - * Base Register 2 and Option Register 2 configure SDRAM. - * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. - * - * For BR2, need: - * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 - * port-size = 32-bits = BR2[19:20] = 11 - * no parity checking = BR2[21:22] = 00 - * SDRAM for MSEL = BR2[24:26] = 011 - * Valid = BR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861 - */ - -#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LBC_SDRAM_BASE \ - | BR_PS_32 /* 32-bit port */ \ - | BR_MS_SDRAM /* MSEL = SDRAM */ \ - | BR_V) /* Valid */ - /* 0xF0001861 */ -#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LBC_SDRAM_BASE -#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_64MB) - -/* - * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. - * - * For OR2, need: - * 64MB mask for AM, OR2[0:7] = 1111 1100 - * XAM, OR2[17:18] = 11 - * 9 columns OR2[19-21] = 010 - * 13 rows OR2[23-25] = 100 - * EAD set for extra time OR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901 - */ - -#define CONFIG_SYS_OR2_PRELIM (OR_AM_64MB \ - | OR_SDRAM_XAM \ - | ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \ - | ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \ - | OR_SDRAM_EAD) - /* 0xFC006901 */ - - /* LB sdram refresh timer, about 6us */ -#define CONFIG_SYS_LBC_LSRT 0x32000000 - /* LB refresh timer prescal, 266MHz/32 */ -#define CONFIG_SYS_LBC_MRTPR 0x20000000 - -#define CONFIG_SYS_LBC_LSDMR_COMMON (LSDMR_RFEN \ - | LSDMR_BSMA1516 \ - | LSDMR_RFCR8 \ - | LSDMR_PRETOACT6 \ - | LSDMR_ACTTORW3 \ - | LSDMR_BL8 \ - | LSDMR_WRC3 \ - | LSDMR_CL3) - -/* - * SDRAM Controller configuration sequence. - */ -#define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) -#define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) -#define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) -#define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) -#define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL) -#endif - /* * Serial Port */ diff --git a/include/configs/MPC8349EMDS_SDRAM.h b/include/configs/MPC8349EMDS_SDRAM.h new file mode 100644 index 0000000000..b610b555a7 --- /dev/null +++ b/include/configs/MPC8349EMDS_SDRAM.h @@ -0,0 +1,731 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2006-2010 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + */ + +/* + * mpc8349emds board configuration file + * + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_E300 1 /* E300 Family */ + +#define CONFIG_PCI_66M +#ifdef CONFIG_PCI_66M +#define CONFIG_83XX_CLKIN 66000000 /* in Hz */ +#else +#define CONFIG_83XX_CLKIN 33000000 /* in Hz */ +#endif + +#ifdef CONFIG_PCISLAVE +#define CONFIG_83XX_PCICLK 66666666 /* in Hz */ +#endif /* CONFIG_PCISLAVE */ + +#ifndef CONFIG_SYS_CLK_FREQ +#ifdef CONFIG_PCI_66M +#define CONFIG_SYS_CLK_FREQ 66000000 +#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1 +#else +#define CONFIG_SYS_CLK_FREQ 33000000 +#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1 +#endif +#endif + +#define CONFIG_SYS_IMMR 0xE0000000 + +#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ +#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ +#define CONFIG_SYS_MEMTEST_END 0x00100000 + +/* + * DDR Setup + */ +#define CONFIG_DDR_ECC /* support DDR ECC function */ +#define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ +#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ + +/* + * SYS_FSL_DDR2 is selected in Kconfig to use unified DDR driver + * unselect it to use old spd_sdram.c + */ +#define CONFIG_SYS_SPD_BUS_NUM 0 +#define SPD_EEPROM_ADDRESS1 0x52 +#define SPD_EEPROM_ADDRESS2 0x51 +#define CONFIG_DIMM_SLOTS_PER_CTLR 2 +#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER +#define CONFIG_MEM_INIT_VALUE 0xDeadBeef + +/* + * 32-bit data path mode. + * + * Please note that using this mode for devices with the real density of 64-bit + * effectively reduces the amount of available memory due to the effect of + * wrapping around while translating address to row/columns, for example in the + * 256MB module the upper 128MB get aliased with contents of the lower + * 128MB); normally this define should be used for devices with real 32-bit + * data path. + */ +#undef CONFIG_DDR_32BIT + +#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ + | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) +#undef CONFIG_DDR_2T_TIMING + +/* + * DDRCDR - DDR Control Driver Register + */ +#define CONFIG_SYS_DDRCDR_VALUE 0x80080001 + +#if defined(CONFIG_SPD_EEPROM) +/* + * Determine DDR configuration from I2C interface. + */ +#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ +#else +/* + * Manually set up DDR parameters + */ +#define CONFIG_SYS_DDR_SIZE 256 /* MB */ +#if defined(CONFIG_DDR_II) +#define CONFIG_SYS_DDRCDR 0x80080001 +#define CONFIG_SYS_DDR_CS2_BNDS 0x0000000f +#define CONFIG_SYS_DDR_CS2_CONFIG 0x80330102 +#define CONFIG_SYS_DDR_TIMING_0 0x00220802 +#define CONFIG_SYS_DDR_TIMING_1 0x38357322 +#define CONFIG_SYS_DDR_TIMING_2 0x2f9048c8 +#define CONFIG_SYS_DDR_TIMING_3 0x00000000 +#define CONFIG_SYS_DDR_CLK_CNTL 0x02000000 +#define CONFIG_SYS_DDR_MODE 0x47d00432 +#define CONFIG_SYS_DDR_MODE2 0x8000c000 +#define CONFIG_SYS_DDR_INTERVAL 0x03cf0080 +#define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000 +#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 +#else +#define CONFIG_SYS_DDR_CS2_CONFIG (CSCONFIG_EN \ + | CSCONFIG_ROW_BIT_13 \ + | CSCONFIG_COL_BIT_10) +#define CONFIG_SYS_DDR_TIMING_1 0x36332321 +#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ +#define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ +#define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */ + +#if defined(CONFIG_DDR_32BIT) +/* set burst length to 8 for 32-bit data path */ + /* DLL,normal,seq,4/2.5, 8 burst len */ +#define CONFIG_SYS_DDR_MODE 0x00000023 +#else +/* the default burst length is 4 - for 64-bit data path */ + /* DLL,normal,seq,4/2.5, 4 burst len */ +#define CONFIG_SYS_DDR_MODE 0x00000022 +#endif +#endif +#endif + +/* + * SDRAM on the Local Bus + */ +#define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */ +#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ + +/* + * FLASH on the Local Bus + */ +#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ +#define CONFIG_SYS_FLASH_SIZE 32 /* max flash size in MB */ + +#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ + | BR_PS_16 /* 16 bit port */ \ + | BR_MS_GPCM /* MSEL = GPCM */ \ + | BR_V) /* valid */ +#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ + | OR_UPM_XAM \ + | OR_GPCM_CSNT \ + | OR_GPCM_ACS_DIV2 \ + | OR_GPCM_XACS \ + | OR_GPCM_SCY_15 \ + | OR_GPCM_TRLX_SET \ + | OR_GPCM_EHTR_SET \ + | OR_GPCM_EAD) + + /* window base at flash base */ +#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB) + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ + +#undef CONFIG_SYS_FLASH_CHECKSUM +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ + +#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) +#define CONFIG_SYS_RAMBOOT +#else +#undef CONFIG_SYS_RAMBOOT +#endif + +/* + * BCSR register on local bus 32KB, 8-bit wide for MDS config reg + */ +#define CONFIG_SYS_BCSR 0xE2400000 + /* Access window base at BCSR base */ +#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR +#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) +#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \ + | BR_PS_8 \ + | BR_MS_GPCM \ + | BR_V) + /* 0x00000801 */ +#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \ + | OR_GPCM_XAM \ + | OR_GPCM_CSNT \ + | OR_GPCM_SCY_15 \ + | OR_GPCM_TRLX_CLEAR \ + | OR_GPCM_EHTR_CLEAR) + /* 0xFFFFE8F0 */ + +#define CONFIG_SYS_INIT_RAM_LOCK 1 +#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ + +#define CONFIG_SYS_GBL_DATA_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ +#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ + +/* + * Local Bus LCRR and LBCR regs + * LCRR: DLL bypass, Clock divider is 4 + * External Local Bus rate is + * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV + */ +#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 +#define CONFIG_SYS_LBC_LBCR 0x00000000 + +/* + * The MPC834xEA MDS for 834xE rev3.1 may not be assembled SDRAM memory. + */ + +/* Local bus BR2, OR2 definition for SDRAM if soldered on the MDS board */ +/* + * Base Register 2 and Option Register 2 configure SDRAM. + * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. + * + * For BR2, need: + * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 + * port-size = 32-bits = BR2[19:20] = 11 + * no parity checking = BR2[21:22] = 00 + * SDRAM for MSEL = BR2[24:26] = 011 + * Valid = BR[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861 + */ + +#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LBC_SDRAM_BASE \ + | BR_PS_32 /* 32-bit port */ \ + | BR_MS_SDRAM /* MSEL = SDRAM */ \ + | BR_V) /* Valid */ + /* 0xF0001861 */ +#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LBC_SDRAM_BASE +#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_64MB) + +/* + * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. + * + * For OR2, need: + * 64MB mask for AM, OR2[0:7] = 1111 1100 + * XAM, OR2[17:18] = 11 + * 9 columns OR2[19-21] = 010 + * 13 rows OR2[23-25] = 100 + * EAD set for extra time OR[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901 + */ + +#define CONFIG_SYS_OR2_PRELIM (OR_AM_64MB \ + | OR_SDRAM_XAM \ + | ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \ + | ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \ + | OR_SDRAM_EAD) + /* 0xFC006901 */ + + /* LB sdram refresh timer, about 6us */ +#define CONFIG_SYS_LBC_LSRT 0x32000000 + /* LB refresh timer prescal, 266MHz/32 */ +#define CONFIG_SYS_LBC_MRTPR 0x20000000 + +#define CONFIG_SYS_LBC_LSDMR_COMMON (LSDMR_RFEN \ + | LSDMR_BSMA1516 \ + | LSDMR_RFCR8 \ + | LSDMR_PRETOACT6 \ + | LSDMR_ACTTORW3 \ + | LSDMR_BL8 \ + | LSDMR_WRC3 \ + | LSDMR_CL3) + +/* + * SDRAM Controller configuration sequence. + */ +#define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) +#define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) +#define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) +#define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) +#define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL) + +/* + * Serial Port + */ +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_FSL +#define CONFIG_SYS_FSL_I2C_SPEED 400000 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_FSL_I2C2_SPEED 400000 +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 +#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } + +/* SPI */ +#undef CONFIG_SOFT_SPI /* SPI bit-banged */ + +/* GPIOs. Used as SPI chip selects */ +#define CONFIG_SYS_GPIO1_PRELIM +#define CONFIG_SYS_GPIO1_DIR 0xC0000000 /* SPI CS on 0, LED on 1 */ +#define CONFIG_SYS_GPIO1_DAT 0xC0000000 /* Both are active LOW */ + +/* TSEC */ +#define CONFIG_SYS_TSEC1_OFFSET 0x24000 +#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) +#define CONFIG_SYS_TSEC2_OFFSET 0x25000 +#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) + +/* USB */ +#define CONFIG_SYS_USE_MPC834XSYS_USB_PHY 1 /* Use SYS board PHY */ + +/* + * General PCI + * Addresses are mapped 1-1. + */ +#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 +#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE +#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 +#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE +#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCI1_IO_BASE 0x00000000 +#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 +#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ + +#define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000 +#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE +#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000 +#define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE +#define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCI2_IO_BASE 0x00000000 +#define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000 +#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ + +#if defined(CONFIG_PCI) + +#define PCI_ONE_PCI1 +#if defined(PCI_64BIT) +#undef PCI_ALL_PCI1 +#undef PCI_TWO_PCI1 +#undef PCI_ONE_PCI1 +#endif + +#define CONFIG_83XX_PCI_STREAMING + +#undef CONFIG_EEPRO100 +#undef CONFIG_TULIP + +#if !defined(CONFIG_PCI_PNP) + #define PCI_ENET0_IOADDR 0xFIXME + #define PCI_ENET0_MEMADDR 0xFIXME + #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ +#endif + +#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ + +#endif /* CONFIG_PCI */ + +/* + * TSEC configuration + */ + +#if defined(CONFIG_TSEC_ENET) + +#define CONFIG_GMII 1 /* MII PHY management */ +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "TSEC0" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "TSEC1" +#define TSEC1_PHY_ADDR 0 +#define TSEC2_PHY_ADDR 1 +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC2_FLAGS TSEC_GIGABIT + +/* Options are: TSEC[0-1] */ +#define CONFIG_ETHPRIME "TSEC0" + +#endif /* CONFIG_TSEC_ENET */ + +/* + * Configure on-board RTC + */ +#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ + +/* + * Environment + */ +#ifndef CONFIG_SYS_RAMBOOT + #define CONFIG_ENV_ADDR \ + (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) + #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ + #define CONFIG_ENV_SIZE 0x2000 + +/* Address and size of Redundant Environment Sector */ +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) + +#else + #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) + #define CONFIG_ENV_SIZE 0x2000 +#endif + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE + +/* + * Command line configuration. + */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 256 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ + /* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ + +#if 1 /*528/264*/ +#define CONFIG_SYS_HRCW_LOW (\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ + HRCWL_DDR_TO_SCB_CLK_1X1 |\ + HRCWL_CSB_TO_CLKIN |\ + HRCWL_VCO_1X2 |\ + HRCWL_CORE_TO_CSB_2X1) +#elif 0 /*396/132*/ +#define CONFIG_SYS_HRCW_LOW (\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ + HRCWL_DDR_TO_SCB_CLK_1X1 |\ + HRCWL_CSB_TO_CLKIN |\ + HRCWL_VCO_1X4 |\ + HRCWL_CORE_TO_CSB_3X1) +#elif 0 /*264/132*/ +#define CONFIG_SYS_HRCW_LOW (\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ + HRCWL_DDR_TO_SCB_CLK_1X1 |\ + HRCWL_CSB_TO_CLKIN |\ + HRCWL_VCO_1X4 |\ + HRCWL_CORE_TO_CSB_2X1) +#elif 0 /*132/132*/ +#define CONFIG_SYS_HRCW_LOW (\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ + HRCWL_DDR_TO_SCB_CLK_1X1 |\ + HRCWL_CSB_TO_CLKIN |\ + HRCWL_VCO_1X4 |\ + HRCWL_CORE_TO_CSB_1X1) +#elif 0 /*264/264 */ +#define CONFIG_SYS_HRCW_LOW (\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ + HRCWL_DDR_TO_SCB_CLK_1X1 |\ + HRCWL_CSB_TO_CLKIN |\ + HRCWL_VCO_1X4 |\ + HRCWL_CORE_TO_CSB_1X1) +#endif + +#ifdef CONFIG_PCISLAVE +#define CONFIG_SYS_HRCW_HIGH (\ + HRCWH_PCI_AGENT |\ + HRCWH_64_BIT_PCI |\ + HRCWH_PCI1_ARBITER_DISABLE |\ + HRCWH_PCI2_ARBITER_DISABLE |\ + HRCWH_CORE_ENABLE |\ + HRCWH_FROM_0X00000100 |\ + HRCWH_BOOTSEQ_DISABLE |\ + HRCWH_SW_WATCHDOG_DISABLE |\ + HRCWH_ROM_LOC_LOCAL_16BIT |\ + HRCWH_TSEC1M_IN_GMII |\ + HRCWH_TSEC2M_IN_GMII) +#else +#if defined(PCI_64BIT) +#define CONFIG_SYS_HRCW_HIGH (\ + HRCWH_PCI_HOST |\ + HRCWH_64_BIT_PCI |\ + HRCWH_PCI1_ARBITER_ENABLE |\ + HRCWH_PCI2_ARBITER_DISABLE |\ + HRCWH_CORE_ENABLE |\ + HRCWH_FROM_0X00000100 |\ + HRCWH_BOOTSEQ_DISABLE |\ + HRCWH_SW_WATCHDOG_DISABLE |\ + HRCWH_ROM_LOC_LOCAL_16BIT |\ + HRCWH_TSEC1M_IN_GMII |\ + HRCWH_TSEC2M_IN_GMII) +#else +#define CONFIG_SYS_HRCW_HIGH (\ + HRCWH_PCI_HOST |\ + HRCWH_32_BIT_PCI |\ + HRCWH_PCI1_ARBITER_ENABLE |\ + HRCWH_PCI2_ARBITER_ENABLE |\ + HRCWH_CORE_ENABLE |\ + HRCWH_FROM_0X00000100 |\ + HRCWH_BOOTSEQ_DISABLE |\ + HRCWH_SW_WATCHDOG_DISABLE |\ + HRCWH_ROM_LOC_LOCAL_16BIT |\ + HRCWH_TSEC1M_IN_GMII |\ + HRCWH_TSEC2M_IN_GMII) +#endif /* PCI_64BIT */ +#endif /* CONFIG_PCISLAVE */ + +/* + * System performance + */ +#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ +#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ +#define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */ +#define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */ +#define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */ +#define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */ + +/* System IO Config */ +#define CONFIG_SYS_SICRH 0 +#define CONFIG_SYS_SICRL SICRL_LDP_A + +#define CONFIG_SYS_HID0_INIT 0x000000000 +#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \ + | HID0_ENABLE_INSTRUCTION_CACHE) + +/* #define CONFIG_SYS_HID0_FINAL (\ + HID0_ENABLE_INSTRUCTION_CACHE |\ + HID0_ENABLE_M_BIT |\ + HID0_ENABLE_ADDRESS_BROADCAST) */ + +#define CONFIG_SYS_HID2 HID2_HBE +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + +/* DDR @ 0x00000000 */ +#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ + | BATL_PP_RW \ + | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ + | BATU_BL_256M \ + | BATU_VS \ + | BATU_VP) + +/* PCI @ 0x80000000 */ +#ifdef CONFIG_PCI +#define CONFIG_PCI_INDIRECT_BRIDGE +#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \ + | BATL_PP_RW \ + | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ + | BATU_BL_256M \ + | BATU_VS \ + | BATU_VP) +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ + | BATL_PP_RW \ + | BATL_CACHEINHIBIT \ + | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ + | BATU_BL_256M \ + | BATU_VS \ + | BATU_VP) +#else +#define CONFIG_SYS_IBAT1L (0) +#define CONFIG_SYS_IBAT1U (0) +#define CONFIG_SYS_IBAT2L (0) +#define CONFIG_SYS_IBAT2U (0) +#endif + +#ifdef CONFIG_MPC83XX_PCI2 +#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \ + | BATL_PP_RW \ + | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \ + | BATU_BL_256M \ + | BATU_VS \ + | BATU_VP) +#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \ + | BATL_PP_RW \ + | BATL_CACHEINHIBIT \ + | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \ + | BATU_BL_256M \ + | BATU_VS \ + | BATU_VP) +#else +#define CONFIG_SYS_IBAT3L (0) +#define CONFIG_SYS_IBAT3U (0) +#define CONFIG_SYS_IBAT4L (0) +#define CONFIG_SYS_IBAT4U (0) +#endif + +/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ +#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ + | BATL_PP_RW \ + | BATL_CACHEINHIBIT \ + | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ + | BATU_BL_256M \ + | BATU_VS \ + | BATU_VP) + +/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ +#define CONFIG_SYS_IBAT6L (0xF0000000 \ + | BATL_PP_RW \ + | BATL_MEMCOHERENCE \ + | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT6U (0xF0000000 \ + | BATU_BL_256M \ + | BATU_VS \ + | BATU_VP) + +#define CONFIG_SYS_IBAT7L (0) +#define CONFIG_SYS_IBAT7U (0) + +#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L +#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U +#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L +#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U +#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L +#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U +#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L +#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U +#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L +#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U +#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L +#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U +#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L +#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U +#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L +#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ +#endif + +/* + * Environment Configuration + */ +#define CONFIG_ENV_OVERWRITE + +#if defined(CONFIG_TSEC_ENET) +#define CONFIG_HAS_ETH1 +#define CONFIG_HAS_ETH0 +#endif + +#define CONFIG_HOSTNAME "mpc8349emds" +#define CONFIG_ROOTPATH "/nfsroot/rootfs" +#define CONFIG_BOOTFILE "uImage" + +#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ + "echo" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "hostname=mpc8349emds\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ + "flash_nfs=run nfsargs addip addtty;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip addtty;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ + "bootm\0" \ + "load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0" \ + "update=protect off fe000000 fe03ffff; " \ + "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0"\ + "upd=run load update\0" \ + "fdtaddr=780000\0" \ + "fdtfile=mpc834x_mds.dtb\0" \ + "" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ + "$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_BOOTCOMMAND "run flash_self" + +#endif /* __CONFIG_H */ From 7577cb19fc229ebd2a20e1cb8a94a2b423d4f0cf Mon Sep 17 00:00:00 2001 From: Mario Six Date: Mon, 21 Jan 2019 09:17:41 +0100 Subject: [PATCH 18/86] mpc8315erdb: Merge BR/OR settings The mpc8315erdb has the option of either configuring the eLBC (enhanced local system bus) such that * NOR flash is the first memory bank, and NAND flash is the second memory bank, or * NAND flash is the first memory bank, and NOR flash is the second memory bank, by using CONFIG_SYS_NOR_{BR,OR}_PRELIM and CONFIG_SYS_NAND_{BR,OR}_PRELIM for defining CONFIG_SYS_{BR,OR}{0,1}_PRELIM. After Kconfig migration, replacing some lines in the defconfig will have the same effect. Hence, we will not create distinct ve8313_{NOR,NAND} configs for such a small change. Instead, fix the current default (NOR first, NAND second), and unroll the CONFIG_SYS_NAND_{BR,OR}_PRELIM options. This will ease the Kconfig migration. Signed-off-by: Mario Six --- include/configs/MPC8315ERDB.h | 40 +++++++++++++++++------------------ 1 file changed, 19 insertions(+), 21 deletions(-) diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index b8506321af..a2b5b07ea9 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -191,20 +191,6 @@ #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB) -#define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \ - | BR_PS_16 /* 16 bit port */ \ - | BR_MS_GPCM /* MSEL = GPCM */ \ - | BR_V) /* valid */ -#define CONFIG_SYS_NOR_OR_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ - | OR_UPM_XAM \ - | OR_GPCM_CSNT \ - | OR_GPCM_ACS_DIV2 \ - | OR_GPCM_XACS \ - | OR_GPCM_SCY_15 \ - | OR_GPCM_TRLX_SET \ - | OR_GPCM_EHTR_SET \ - | OR_GPCM_EAD) - #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ /* 127 64KB sectors and 8 8KB top sectors per device */ #define CONFIG_SYS_MAX_FLASH_SECT 135 @@ -236,13 +222,26 @@ #define CONFIG_SYS_NAND_U_BOOT_OFFS 16384 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000 -#define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \ +#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ + | BR_PS_16 /* 16 bit port */ \ + | BR_MS_GPCM /* MSEL = GPCM */ \ + | BR_V) /* valid */ +#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB \ + | OR_UPM_XAM \ + | OR_GPCM_CSNT \ + | OR_GPCM_ACS_DIV2 \ + | OR_GPCM_XACS \ + | OR_GPCM_SCY_15 \ + | OR_GPCM_TRLX_SET \ + | OR_GPCM_EHTR_SET \ + | OR_GPCM_EAD) +#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \ | BR_DECC_CHK_GEN /* Use HW ECC */ \ | BR_PS_8 /* 8 bit port */ \ | BR_MS_FCM /* MSEL = FCM */ \ | BR_V) /* valid */ -#define CONFIG_SYS_NAND_OR_PRELIM \ - (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \ +#define CONFIG_SYS_OR1_PRELIM \ + (OR_AM_32KB \ | OR_FCM_CSCT \ | OR_FCM_CST \ | OR_FCM_CHT \ @@ -251,10 +250,9 @@ | OR_FCM_EHTR) /* 0xFFFF8396 */ -#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM -#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM -#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM +/* Still needed for spl_minimal.c */ +#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM +#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) From 1e35d425d14b2ceb5136aea9fe1b53cdebd66a75 Mon Sep 17 00:00:00 2001 From: Mario Six Date: Mon, 21 Jan 2019 09:17:42 +0100 Subject: [PATCH 19/86] ve8313: Merge BR/OR settings The ve8313 has the option of either configuring the eLBC (enhanced local system bus) such that * NOR flash is the first memory bank, and NAND flash is the second memory bank, or * NAND flash is the first memory bank, and NOR flash is the second memory bank, by using CONFIG_SYS_NOR_{BR,OR}_PRELIM and CONFIG_SYS_NAND_{BR,OR}_PRELIM for defining CONFIG_SYS_{BR,OR}{0,1}_PRELIM. After Kconfig migration, replacing some lines in the defconfig will have the same effect. Hence, we will not create distinct ve8313_{NOR,NAND} configs for such a small change. Instead, fix the current default (NOR first, NAND second), and unroll the CONFIG_SYS_NAND_{BR,OR}_PRELIM options. This will ease the Kconfig migration Signed-off-by: Mario Six --- include/configs/ve8313.h | 39 +++++++++++++++++++-------------------- 1 file changed, 19 insertions(+), 20 deletions(-) diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h index 791eac363b..87fbe36640 100644 --- a/include/configs/ve8313.h +++ b/include/configs/ve8313.h @@ -115,18 +115,6 @@ #define CONFIG_SYS_FLASH_SIZE 32 /* size in MB */ #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */ -#define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \ - | BR_PS_16 /* 16 bit */ \ - | BR_MS_GPCM /* MSEL = GPCM */ \ - | BR_V) /* valid */ -#define CONFIG_SYS_NOR_OR_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ - | OR_GPCM_CSNT \ - | OR_GPCM_ACS_DIV4 \ - | OR_GPCM_SCY_5 \ - | OR_GPCM_TRLX_SET \ - | OR_GPCM_EAD) - /* 0xfe000c55 */ - #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB) @@ -172,24 +160,35 @@ #define CONFIG_NAND_FSL_ELBC 1 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384 -#define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \ + +#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ + | BR_PS_16 /* 16 bit */ \ + | BR_MS_GPCM /* MSEL = GPCM */ \ + | BR_V) /* valid */ +#define CONFIG_SYS_OR0_PRELIM (OR_AM_32MB \ + | OR_GPCM_CSNT \ + | OR_GPCM_ACS_DIV4 \ + | OR_GPCM_SCY_5 \ + | OR_GPCM_TRLX_SET \ + | OR_GPCM_EAD) + /* 0xfe000c55 */ + +#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \ | BR_PS_8 \ | BR_DECC_CHK_GEN \ | BR_MS_FCM \ | BR_V) /* valid */ /* 0x61000c21 */ -#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \ +#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \ | OR_FCM_BCTLD \ | OR_FCM_CHT \ | OR_FCM_SCY_2 \ | OR_FCM_RST \ - | OR_FCM_TRLX) - /* 0xffff90ac */ + | OR_FCM_TRLX) /* 0xffff90ac */ -#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM -#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM -#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM +/* Still needed for spl_minimal.c */ +#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM +#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) From 8014c162019ffb199467adb937217800b4614a8f Mon Sep 17 00:00:00 2001 From: Mario Six Date: Mon, 21 Jan 2019 09:17:43 +0100 Subject: [PATCH 20/86] MPC832XEMDS: Migrate to CONFIG_TARGET_MPC832XEMDS Use the proper CONFIG_TARGET_MPC832XEMDS Kconfig option to replace the CONFIG_MPC832XEMDS ad-hoc config option. Signed-off-by: Mario Six --- board/freescale/common/pq-mds-pib.c | 6 +++--- include/configs/MPC832XEMDS.h | 1 - scripts/config_whitelist.txt | 1 - 3 files changed, 3 insertions(+), 5 deletions(-) diff --git a/board/freescale/common/pq-mds-pib.c b/board/freescale/common/pq-mds-pib.c index d152a7821f..ae66039857 100644 --- a/board/freescale/common/pq-mds-pib.c +++ b/board/freescale/common/pq-mds-pib.c @@ -36,7 +36,7 @@ int pib_init(void) i2c_write(0x26, 0x6, 1, &val8, 1); val8 = 0x34; i2c_write(0x26, 0x7, 1, &val8, 1); -#if defined(CONFIG_MPC832XEMDS) +#if defined(CONFIG_TARGET_MPC832XEMDS) val8 = 0xf9; /* PMC2, PMC3 slot to PCI bus */ #else val8 = 0xf3; /* PMC1, PMC2, PMC3 slot to PCI bus */ @@ -55,7 +55,7 @@ int pib_init(void) eieio(); -#if defined(CONFIG_MPC832XEMDS) +#if defined(CONFIG_TARGET_MPC832XEMDS) printf("PCI 32bit bus on PMC2 &PMC3\n"); #else printf("PCI 32bit bus on PMC1 & PMC2 &PMC3\n"); @@ -76,7 +76,7 @@ int pib_init(void) eieio(); printf("QOC3 ATM card on PMC0\n"); -#elif defined(CONFIG_MPC832XEMDS) +#elif defined(CONFIG_TARGET_MPC832XEMDS) val8 = 0; i2c_write(0x26, 0x7, 1, &val8, 1); val8 = 0xf7; diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index 0bb7db9bc3..4cb595bb8e 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -11,7 +11,6 @@ */ #define CONFIG_E300 1 /* E300 family */ #define CONFIG_QE 1 /* Has QE */ -#define CONFIG_MPC832XEMDS 1 /* MPC832XEMDS board specific */ /* * System Clock Setup diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 761cdf6748..b426f2a777 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -1222,7 +1222,6 @@ CONFIG_MMU CONFIG_MONITOR_IS_IN_RAM CONFIG_MPC8313ERDB CONFIG_MPC8315ERDB -CONFIG_MPC832XEMDS CONFIG_MPC8349ITX CONFIG_MPC837XEMDS CONFIG_MPC837XERDB From 4cb06d3edff9e39a1e0b0bbfd110b9e219158412 Mon Sep 17 00:00:00 2001 From: Mario Six Date: Mon, 21 Jan 2019 09:17:44 +0100 Subject: [PATCH 21/86] MPC8349ITX: Migrate to CONFIG_TARGET_MPC8349ITX Use the proper CONFIG_TARGET_MPC8349ITX Kconfig option to replace the CONFIG_MPC8349ITX ad-hoc config option. Signed-off-by: Mario Six --- board/freescale/mpc8349itx/mpc8349itx.c | 2 +- configs/MPC8349ITX_LOWBOOT_defconfig | 1 - configs/MPC8349ITX_defconfig | 1 - include/configs/MPC8349ITX.h | 4 ++-- scripts/config_whitelist.txt | 1 - 5 files changed, 3 insertions(+), 6 deletions(-) diff --git a/board/freescale/mpc8349itx/mpc8349itx.c b/board/freescale/mpc8349itx/mpc8349itx.c index 3bdec1c400..d90553384f 100644 --- a/board/freescale/mpc8349itx/mpc8349itx.c +++ b/board/freescale/mpc8349itx/mpc8349itx.c @@ -152,7 +152,7 @@ int dram_init(void) int checkboard(void) { -#ifdef CONFIG_MPC8349ITX +#ifdef CONFIG_TARGET_MPC8349ITX puts("Board: Freescale MPC8349E-mITX\n"); #else puts("Board: Freescale MPC8349E-mITX-GP\n"); diff --git a/configs/MPC8349ITX_LOWBOOT_defconfig b/configs/MPC8349ITX_LOWBOOT_defconfig index 5166723548..22225e3ad6 100644 --- a/configs/MPC8349ITX_LOWBOOT_defconfig +++ b/configs/MPC8349ITX_LOWBOOT_defconfig @@ -4,7 +4,6 @@ CONFIG_MPC83xx=y CONFIG_TARGET_MPC8349ITX=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="MPC8349ITX" CONFIG_BOOTDELAY=6 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=:/nfsroot/rootfs ip=::::mpc8349emitx:eth0:off console=ttyS0,115200" diff --git a/configs/MPC8349ITX_defconfig b/configs/MPC8349ITX_defconfig index 55e593c115..7f9b9cb283 100644 --- a/configs/MPC8349ITX_defconfig +++ b/configs/MPC8349ITX_defconfig @@ -4,7 +4,6 @@ CONFIG_MPC83xx=y CONFIG_TARGET_MPC8349ITX=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="MPC8349ITX" CONFIG_BOOTDELAY=6 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=:/nfsroot/rootfs ip=::::mpc8349emitx:eth0:off console=ttyS0,115200" diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index 496780d80c..5877279ada 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -54,7 +54,7 @@ * On-board devices */ -#ifdef CONFIG_MPC8349ITX +#ifdef CONFIG_TARGET_MPC8349ITX /* The CF card interface on the back of the board */ #define CONFIG_COMPACT_FLASH #define CONFIG_VSC7385_ENET /* VSC7385 ethernet support */ @@ -642,7 +642,7 @@ boards, we say we have two, but don't display a message if we find only one. */ /* U-Boot image on TFTP server */ #define CONFIG_UBOOTPATH "u-boot.bin" -#ifdef CONFIG_MPC8349ITX +#ifdef CONFIG_TARGET_MPC8349ITX #define CONFIG_FDTFILE "mpc8349emitx.dtb" #else #define CONFIG_FDTFILE "mpc8349emitxgp.dtb" diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index b426f2a777..4c3842bdc3 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -1222,7 +1222,6 @@ CONFIG_MMU CONFIG_MONITOR_IS_IN_RAM CONFIG_MPC8313ERDB CONFIG_MPC8315ERDB -CONFIG_MPC8349ITX CONFIG_MPC837XEMDS CONFIG_MPC837XERDB CONFIG_MPC83XX_GPIO From d6918816fb88ab648016284d80e88cc0db2a33ae Mon Sep 17 00:00:00 2001 From: Mario Six Date: Mon, 21 Jan 2019 09:17:45 +0100 Subject: [PATCH 22/86] hrcon: Migrate to CONFIG_TARGET_HRCON Use the proper CONFIG_TARGET_HRCON Kconfig option to replace the CONFIG_HRCON ad-hoc config option. Signed-off-by: Mario Six --- board/gdsys/common/Makefile | 2 +- board/gdsys/mpc8308/Makefile | 2 +- include/configs/hrcon.h | 1 - include/gdsys_fpga.h | 2 +- scripts/config_whitelist.txt | 1 - 5 files changed, 3 insertions(+), 5 deletions(-) diff --git a/board/gdsys/common/Makefile b/board/gdsys/common/Makefile index af9058a5d7..67d2b310b3 100644 --- a/board/gdsys/common/Makefile +++ b/board/gdsys/common/Makefile @@ -10,7 +10,7 @@ obj-$(CONFIG_IO64) += miiphybb.o obj-$(CONFIG_IOCON) += osd.o mclink.o dp501.o phy.o ch7301.o obj-$(CONFIG_DLVISION_10G) += osd.o dp501.o obj-$(CONFIG_CONTROLCENTERD) += dp501.o -obj-$(CONFIG_HRCON) += osd.o mclink.o dp501.o phy.o ioep-fpga.o fanctrl.o +obj-$(CONFIG_TARGET_HRCON) += osd.o mclink.o dp501.o phy.o ioep-fpga.o fanctrl.o obj-$(CONFIG_STRIDER) += mclink.o dp501.o phy.o ioep-fpga.o adv7611.o ch7301.o obj-$(CONFIG_STRIDER) += fanctrl.o obj-$(CONFIG_STRIDER_CON) += osd.o diff --git a/board/gdsys/mpc8308/Makefile b/board/gdsys/mpc8308/Makefile index 60d2232573..f29376fc9e 100644 --- a/board/gdsys/mpc8308/Makefile +++ b/board/gdsys/mpc8308/Makefile @@ -4,5 +4,5 @@ # Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc obj-y := mpc8308.o sdram.o -obj-$(CONFIG_HRCON) += hrcon.o +obj-$(CONFIG_TARGET_HRCON) += hrcon.o obj-$(CONFIG_STRIDER) += strider.o diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h index 23ed4e54c7..cd5e883b7a 100644 --- a/include/configs/hrcon.h +++ b/include/configs/hrcon.h @@ -13,7 +13,6 @@ */ #define CONFIG_E300 1 /* E300 family */ #define CONFIG_MPC83xx 1 /* MPC83xx family */ -#define CONFIG_HRCON 1 /* HRCON board specific */ #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR diff --git a/include/gdsys_fpga.h b/include/gdsys_fpga.h index db4424d3f8..e9fb4b88b5 100644 --- a/include/gdsys_fpga.h +++ b/include/gdsys_fpga.h @@ -161,7 +161,7 @@ struct ihs_fpga { }; #endif -#if defined(CONFIG_HRCON) || defined(CONFIG_STRIDER_CON_DP) +#if defined(CONFIG_TARGET_HRCON) || defined(CONFIG_STRIDER_CON_DP) struct ihs_fpga { u16 reflection_low; /* 0x0000 */ u16 versions; /* 0x0002 */ diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 4c3842bdc3..35197779ea 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -881,7 +881,6 @@ CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP -CONFIG_HRCON CONFIG_HRCON_DH CONFIG_HRCON_FANS CONFIG_HSMMC2_8BIT From 0e93bb13aad82821abfbd27e0ea0998e54c50fea Mon Sep 17 00:00:00 2001 From: Mario Six Date: Mon, 21 Jan 2019 09:17:46 +0100 Subject: [PATCH 23/86] strider: Migrate to CONFIG_TARGET_STRIDER Use the proper CONFIG_TARGET_STRIDER Kconfig option to replace the CONFIG_STRIDER ad-hoc config option. Signed-off-by: Mario Six --- board/gdsys/common/Makefile | 4 ++-- board/gdsys/mpc8308/Makefile | 2 +- include/configs/strider.h | 1 - scripts/config_whitelist.txt | 1 - 4 files changed, 3 insertions(+), 5 deletions(-) diff --git a/board/gdsys/common/Makefile b/board/gdsys/common/Makefile index 67d2b310b3..9090933e34 100644 --- a/board/gdsys/common/Makefile +++ b/board/gdsys/common/Makefile @@ -11,8 +11,8 @@ obj-$(CONFIG_IOCON) += osd.o mclink.o dp501.o phy.o ch7301.o obj-$(CONFIG_DLVISION_10G) += osd.o dp501.o obj-$(CONFIG_CONTROLCENTERD) += dp501.o obj-$(CONFIG_TARGET_HRCON) += osd.o mclink.o dp501.o phy.o ioep-fpga.o fanctrl.o -obj-$(CONFIG_STRIDER) += mclink.o dp501.o phy.o ioep-fpga.o adv7611.o ch7301.o -obj-$(CONFIG_STRIDER) += fanctrl.o +obj-$(CONFIG_TARGET_STRIDER) += mclink.o dp501.o phy.o ioep-fpga.o adv7611.o ch7301.o +obj-$(CONFIG_TARGET_STRIDER) += fanctrl.o obj-$(CONFIG_STRIDER_CON) += osd.o obj-$(CONFIG_STRIDER_CON_DP) += osd.o diff --git a/board/gdsys/mpc8308/Makefile b/board/gdsys/mpc8308/Makefile index f29376fc9e..dc579479f9 100644 --- a/board/gdsys/mpc8308/Makefile +++ b/board/gdsys/mpc8308/Makefile @@ -5,4 +5,4 @@ obj-y := mpc8308.o sdram.o obj-$(CONFIG_TARGET_HRCON) += hrcon.o -obj-$(CONFIG_STRIDER) += strider.o +obj-$(CONFIG_TARGET_STRIDER) += strider.o diff --git a/include/configs/strider.h b/include/configs/strider.h index 89e0610871..c42fe8c3ec 100644 --- a/include/configs/strider.h +++ b/include/configs/strider.h @@ -13,7 +13,6 @@ */ #define CONFIG_E300 1 /* E300 family */ #define CONFIG_MPC83xx 1 /* MPC83xx family */ -#define CONFIG_STRIDER 1 /* STRIDER board specific */ #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 35197779ea..7c3256a5cb 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -1899,7 +1899,6 @@ CONFIG_STANDALONE_LOAD_ADDR CONFIG_STATIC_BOARD_REV CONFIG_STD_DEVICES_SETTINGS CONFIG_STM32_FLASH -CONFIG_STRIDER CONFIG_STRIDER_CON CONFIG_STRIDER_CON_DP CONFIG_STRIDER_CPU From 67185d19e2d2fe7ee6e15b06e06d8ebf282982ef Mon Sep 17 00:00:00 2001 From: Mario Six Date: Mon, 21 Jan 2019 09:17:47 +0100 Subject: [PATCH 24/86] MPC8313ERDB: Remove CONFIG_MPC8313ERDB CONFIG_MPC8313ERDB is unused, and TARGET_MPC8313ERDB_NAND/TARGET_MPC8313ERDB_NOR Kconfig could replace it. Hence, get rid of CONFIG_MPC8313ERDB. Signed-off-by: Mario Six --- include/configs/MPC8313ERDB_NAND.h | 1 - include/configs/MPC8313ERDB_NOR.h | 1 - scripts/config_whitelist.txt | 1 - 3 files changed, 3 deletions(-) diff --git a/include/configs/MPC8313ERDB_NAND.h b/include/configs/MPC8313ERDB_NAND.h index 976b6854e4..31c2900180 100644 --- a/include/configs/MPC8313ERDB_NAND.h +++ b/include/configs/MPC8313ERDB_NAND.h @@ -13,7 +13,6 @@ * High Level Configuration Options */ #define CONFIG_E300 1 -#define CONFIG_MPC8313ERDB 1 #define CONFIG_SPL_INIT_MINIMAL #define CONFIG_SPL_FLUSH_IMAGE diff --git a/include/configs/MPC8313ERDB_NOR.h b/include/configs/MPC8313ERDB_NOR.h index 81e92fb939..afb0586c4b 100644 --- a/include/configs/MPC8313ERDB_NOR.h +++ b/include/configs/MPC8313ERDB_NOR.h @@ -13,7 +13,6 @@ * High Level Configuration Options */ #define CONFIG_E300 1 -#define CONFIG_MPC8313ERDB 1 #ifndef CONFIG_SYS_MONITOR_BASE #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 7c3256a5cb..d70b9ff6b1 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -1219,7 +1219,6 @@ CONFIG_MMC_SPI_SPEED CONFIG_MMC_SUNXI_SLOT CONFIG_MMU CONFIG_MONITOR_IS_IN_RAM -CONFIG_MPC8313ERDB CONFIG_MPC8315ERDB CONFIG_MPC837XEMDS CONFIG_MPC837XERDB From d6a77954008cbf5f2182d5e317c46bfab600e917 Mon Sep 17 00:00:00 2001 From: Mario Six Date: Mon, 21 Jan 2019 09:17:48 +0100 Subject: [PATCH 25/86] MPC8315ERDB: Remove CONFIG_MPC8315ERDB CONFIG_MPC8315ERDB is unused, and TARGET_MPC8315ERDB could replace it. Hence, get rid of CONFIG_MPC8315ERDB. Signed-off-by: Mario Six --- include/configs/MPC8315ERDB.h | 1 - scripts/config_whitelist.txt | 1 - 2 files changed, 2 deletions(-) diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index a2b5b07ea9..c373a0ab4c 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -22,7 +22,6 @@ * High Level Configuration Options */ #define CONFIG_E300 1 /* E300 family */ -#define CONFIG_MPC8315ERDB 1 /* MPC8315ERDB board specific */ /* * System Clock Setup diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index d70b9ff6b1..ef7835faf6 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -1219,7 +1219,6 @@ CONFIG_MMC_SPI_SPEED CONFIG_MMC_SUNXI_SLOT CONFIG_MMU CONFIG_MONITOR_IS_IN_RAM -CONFIG_MPC8315ERDB CONFIG_MPC837XEMDS CONFIG_MPC837XERDB CONFIG_MPC83XX_GPIO From 897c82ae91c9f31479332aecc0e9fc4832b0823c Mon Sep 17 00:00:00 2001 From: Mario Six Date: Mon, 21 Jan 2019 09:17:49 +0100 Subject: [PATCH 26/86] MPC837XEMDS: Remove CONFIG_MPC837XEMDS CONFIG_MPC837XEMDS is unused, and TARGET_MPC837XEMDS could replace it. Hence, get rid of CONFIG_MPC837XEMDS. Signed-off-by: Mario Six --- include/configs/MPC837XEMDS.h | 1 - scripts/config_whitelist.txt | 1 - 2 files changed, 2 deletions(-) diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index 82dcb85973..577f7ec0b2 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -11,7 +11,6 @@ * High Level Configuration Options */ #define CONFIG_E300 1 /* E300 family */ -#define CONFIG_MPC837XEMDS 1 /* MPC837XEMDS board specific */ /* * System Clock Setup diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index ef7835faf6..5cb04571f9 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -1219,7 +1219,6 @@ CONFIG_MMC_SPI_SPEED CONFIG_MMC_SUNXI_SLOT CONFIG_MMU CONFIG_MONITOR_IS_IN_RAM -CONFIG_MPC837XEMDS CONFIG_MPC837XERDB CONFIG_MPC83XX_GPIO CONFIG_MPC83XX_GPIO_0_INIT_DIRECTION From 47a1b3f446de751ce9cacf57d43681ea43402ea4 Mon Sep 17 00:00:00 2001 From: Mario Six Date: Mon, 21 Jan 2019 09:17:50 +0100 Subject: [PATCH 27/86] MPC837XERDB: Remove CONFIG_MPC837XERDB CONFIG_MPC837XERDB is unused, and TARGET_MPC837XERDB could replace it. Hence, get rid of CONFIG_MPC837XERDB. Signed-off-by: Mario Six --- include/configs/MPC837XERDB.h | 1 - scripts/config_whitelist.txt | 1 - 2 files changed, 2 deletions(-) diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index 6029d0f21b..a8f5b013b2 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -12,7 +12,6 @@ * High Level Configuration Options */ #define CONFIG_E300 1 /* E300 family */ -#define CONFIG_MPC837XERDB 1 #define CONFIG_HWCONFIG diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 5cb04571f9..7b5f76670e 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -1219,7 +1219,6 @@ CONFIG_MMC_SPI_SPEED CONFIG_MMC_SUNXI_SLOT CONFIG_MMU CONFIG_MONITOR_IS_IN_RAM -CONFIG_MPC837XERDB CONFIG_MPC83XX_GPIO CONFIG_MPC83XX_GPIO_0_INIT_DIRECTION CONFIG_MPC83XX_GPIO_0_INIT_OPEN_DRAIN From 1cbc10c8158d22d65bb5ccc7550186036bb9f17a Mon Sep 17 00:00:00 2001 From: Mario Six Date: Mon, 21 Jan 2019 09:17:51 +0100 Subject: [PATCH 28/86] mpc83xx: Migrate legacy PCI options to Kconfig The MPC83xx include files contain some settings of the PCI subsystem. Migrate these to Kconfig until a proper DM PCI driver exists. Signed-off-by: Mario Six --- arch/powerpc/cpu/mpc83xx/Kconfig | 26 ++++++++++++++++++++++++++ board/freescale/mpc8349emds/pci.c | 12 ++++++------ configs/MPC8349EMDS_SDRAM_defconfig | 1 + configs/MPC8349EMDS_defconfig | 1 + configs/sbc8349_PCI_33_defconfig | 1 + configs/sbc8349_PCI_66_defconfig | 1 + configs/vme8349_defconfig | 1 + include/configs/MPC8349EMDS.h | 11 ++--------- include/configs/MPC8349EMDS_SDRAM.h | 11 ++--------- include/configs/TQM834x.h | 2 +- include/configs/caddy2.h | 8 -------- include/configs/sbc8349.h | 10 +--------- include/configs/vme8349.h | 10 +--------- 13 files changed, 44 insertions(+), 51 deletions(-) diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index 0ce1aad6d0..bd4e5c14a9 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -215,6 +215,32 @@ config ARCH_MPC8360 config ARCH_MPC837X bool +menu "Legacy options" + +if ARCH_MPC8349 + +#TODO(mario.six@gdsys.cc): Remove when mpc83xx PCI has been converted to DM/DT +choice + prompt "PMC slot configuration" + +config PCI_ALL_PCI1 + bool "All PMC slots on PCI1" + +config PCI_ONE_PCI1 + bool "First PMC1 on PCI1" + +config PCI_TWO_PCI1 + bool "First two PMC1 on PCI1" + +endchoice + +config PCI_64BIT + bool "PMC2 is 64bit" + +endif + +endmenu + source "board/esd/vme8349/Kconfig" source "board/freescale/mpc8308rdb/Kconfig" source "board/freescale/mpc8313erdb/Kconfig" diff --git a/board/freescale/mpc8349emds/pci.c b/board/freescale/mpc8349emds/pci.c index a2feda855f..005190ed87 100644 --- a/board/freescale/mpc8349emds/pci.c +++ b/board/freescale/mpc8349emds/pci.c @@ -77,11 +77,11 @@ void pib_init(void) i2c_write(0x26, 0x6, 1, &val8, 1); val8 = 0x34; i2c_write(0x26, 0x7, 1, &val8, 1); -#if defined(PCI_64BIT) +#if defined(CONFIG_PCI_64BIT) val8 = 0xf4; /* PMC2:PCI1/64-bit */ -#elif defined(PCI_ALL_PCI1) +#elif defined(CONFIG_PCI_ALL_PCI1) val8 = 0xf3; /* PMC1:PCI1 PMC2:PCI1 PMC3:PCI1 */ -#elif defined(PCI_ONE_PCI1) +#elif defined(CONFIG_PCI_ONE_PCI1) val8 = 0xf9; /* PMC1:PCI1 PMC2:PCI2 PMC3:PCI2 */ #else val8 = 0xf5; /* PMC1:PCI1 PMC2:PCI1 PMC3:PCI2 */ @@ -98,11 +98,11 @@ void pib_init(void) i2c_write(0x27, 0x3, 1, &val8, 1); asm("eieio"); -#if defined(PCI_64BIT) +#if defined(CONFIG_PCI_64BIT) printf("PCI1: 64-bit on PMC2\n"); -#elif defined(PCI_ALL_PCI1) +#elif defined(CONFIG_PCI_ALL_PCI1) printf("PCI1: 32-bit on PMC1, PMC2, PMC3\n"); -#elif defined(PCI_ONE_PCI1) +#elif defined(CONFIG_PCI_ONE_PCI1) printf("PCI1: 32-bit on PMC1\n"); printf("PCI2: 32-bit on PMC2, PMC3\n"); #else diff --git a/configs/MPC8349EMDS_SDRAM_defconfig b/configs/MPC8349EMDS_SDRAM_defconfig index 2607dfa4f3..a98cc74027 100644 --- a/configs/MPC8349EMDS_SDRAM_defconfig +++ b/configs/MPC8349EMDS_SDRAM_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_MPC83xx=y CONFIG_TARGET_MPC8349EMDS_SDRAM=y +CONFIG_PCI_ONE_PCI1=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC8349EMDS_defconfig b/configs/MPC8349EMDS_defconfig index 41a1d9609b..bd8ff625e1 100644 --- a/configs/MPC8349EMDS_defconfig +++ b/configs/MPC8349EMDS_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_MPC83xx=y CONFIG_TARGET_MPC8349EMDS=y +CONFIG_PCI_ONE_PCI1=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/sbc8349_PCI_33_defconfig b/configs/sbc8349_PCI_33_defconfig index 02d5185124..5c2720aef1 100644 --- a/configs/sbc8349_PCI_33_defconfig +++ b/configs/sbc8349_PCI_33_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFF800000 CONFIG_MPC83xx=y CONFIG_TARGET_SBC8349=y +CONFIG_PCI_64BIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PCI_33M" diff --git a/configs/sbc8349_PCI_66_defconfig b/configs/sbc8349_PCI_66_defconfig index 945c5229b9..e6535dafcf 100644 --- a/configs/sbc8349_PCI_66_defconfig +++ b/configs/sbc8349_PCI_66_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFF800000 CONFIG_MPC83xx=y CONFIG_TARGET_SBC8349=y +CONFIG_PCI_64BIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PCI_66M" diff --git a/configs/vme8349_defconfig b/configs/vme8349_defconfig index a7d81a3a0f..90c29b7fed 100644 --- a/configs/vme8349_defconfig +++ b/configs/vme8349_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFFF00000 CONFIG_MPC83xx=y CONFIG_TARGET_VME8349=y +CONFIG_PCI_64BIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index fe2b81b905..40e5c1997d 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -285,13 +285,6 @@ #if defined(CONFIG_PCI) -#define PCI_ONE_PCI1 -#if defined(PCI_64BIT) -#undef PCI_ALL_PCI1 -#undef PCI_TWO_PCI1 -#undef PCI_ONE_PCI1 -#endif - #define CONFIG_83XX_PCI_STREAMING #undef CONFIG_EEPRO100 @@ -436,7 +429,7 @@ HRCWH_TSEC1M_IN_GMII |\ HRCWH_TSEC2M_IN_GMII) #else -#if defined(PCI_64BIT) +#if defined(CONFIG_PCI_64BIT) #define CONFIG_SYS_HRCW_HIGH (\ HRCWH_PCI_HOST |\ HRCWH_64_BIT_PCI |\ @@ -462,7 +455,7 @@ HRCWH_ROM_LOC_LOCAL_16BIT |\ HRCWH_TSEC1M_IN_GMII |\ HRCWH_TSEC2M_IN_GMII) -#endif /* PCI_64BIT */ +#endif /* CONFIG_PCI_64BIT */ #endif /* CONFIG_PCISLAVE */ /* diff --git a/include/configs/MPC8349EMDS_SDRAM.h b/include/configs/MPC8349EMDS_SDRAM.h index b610b555a7..15f10492a5 100644 --- a/include/configs/MPC8349EMDS_SDRAM.h +++ b/include/configs/MPC8349EMDS_SDRAM.h @@ -357,13 +357,6 @@ #if defined(CONFIG_PCI) -#define PCI_ONE_PCI1 -#if defined(PCI_64BIT) -#undef PCI_ALL_PCI1 -#undef PCI_TWO_PCI1 -#undef PCI_ONE_PCI1 -#endif - #define CONFIG_83XX_PCI_STREAMING #undef CONFIG_EEPRO100 @@ -508,7 +501,7 @@ HRCWH_TSEC1M_IN_GMII |\ HRCWH_TSEC2M_IN_GMII) #else -#if defined(PCI_64BIT) +#if defined(CONFIG_PCI_64BIT) #define CONFIG_SYS_HRCW_HIGH (\ HRCWH_PCI_HOST |\ HRCWH_64_BIT_PCI |\ @@ -534,7 +527,7 @@ HRCWH_ROM_LOC_LOCAL_16BIT |\ HRCWH_TSEC1M_IN_GMII |\ HRCWH_TSEC2M_IN_GMII) -#endif /* PCI_64BIT */ +#endif /* CONFIG_PCI_64BIT */ #endif /* CONFIG_PCISLAVE */ /* diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index 2b82bd82eb..949e370150 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -270,7 +270,7 @@ HRCWL_VCO_1X2 |\ HRCWL_CORE_TO_CSB_2X1) -#if defined(PCI_64BIT) +#if defined(CONFIG_PCI_64BIT) #define CONFIG_SYS_HRCW_HIGH (\ HRCWH_PCI_HOST |\ HRCWH_64_BIT_PCI |\ diff --git a/include/configs/caddy2.h b/include/configs/caddy2.h index a7bbbbdd0b..a8f692d5ea 100644 --- a/include/configs/caddy2.h +++ b/include/configs/caddy2.h @@ -212,14 +212,6 @@ #if defined(CONFIG_PCI) -#define PCI_64BIT -#define PCI_ONE_PCI1 -#if defined(PCI_64BIT) -#undef PCI_ALL_PCI1 -#undef PCI_TWO_PCI1 -#undef PCI_ONE_PCI1 -#endif - #undef CONFIG_EEPRO100 #undef CONFIG_TULIP diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index 6ae11185cb..60eb2cf831 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -307,14 +307,6 @@ #if defined(CONFIG_PCI) -#define PCI_64BIT -#define PCI_ONE_PCI1 -#if defined(PCI_64BIT) -#undef PCI_ALL_PCI1 -#undef PCI_TWO_PCI1 -#undef PCI_ONE_PCI1 -#endif - #undef CONFIG_EEPRO100 #undef CONFIG_TULIP @@ -435,7 +427,7 @@ HRCWL_CORE_TO_CSB_1X1) #endif -#if defined(PCI_64BIT) +#if defined(CONFIG_PCI_64BIT) #define CONFIG_SYS_HRCW_HIGH (\ HRCWH_PCI_HOST |\ HRCWH_64_BIT_PCI |\ diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h index 6c3ad76e52..ea08058752 100644 --- a/include/configs/vme8349.h +++ b/include/configs/vme8349.h @@ -212,14 +212,6 @@ #if defined(CONFIG_PCI) -#define PCI_64BIT -#define PCI_ONE_PCI1 -#if defined(PCI_64BIT) -#undef PCI_ALL_PCI1 -#undef PCI_TWO_PCI1 -#undef PCI_ONE_PCI1 -#endif - #undef CONFIG_EEPRO100 #undef CONFIG_TULIP @@ -316,7 +308,7 @@ HRCWL_VCO_1X2 |\ HRCWL_CORE_TO_CSB_2X1) -#if defined(PCI_64BIT) +#if defined(CONFIG_PCI_64BIT) #define CONFIG_SYS_HRCW_HIGH (\ HRCWH_PCI_HOST |\ HRCWH_64_BIT_PCI |\ From 0f06f57c280eaec528c76ebfca9b22aa181ca8be Mon Sep 17 00:00:00 2001 From: Mario Six Date: Mon, 21 Jan 2019 09:17:52 +0100 Subject: [PATCH 29/86] mpc83xx: Replace CONFIG_83XX_CLKIN in calculations CONFIG_SYS_CLK_FREQ is the standard way to set the system clock frequency. On MPC83xx, CONFIG_83XX_CLKIN is used for this purpose. Hence, the obvious way is to replace CONFIG_83XX_CLKIN with CONFIG_SYS_CLK_FREQ. A few MPC83xx boards use the CONFIG_83XX_CLKIN variable for computing CONFIG_SYS_NS16550_CLK. This makes it harder to replace CONFIG_83XX_CLKIN. But the value of the multiplicator can be read from the SPMR register. Hence, replace the static calculations with a call to a new get_bus_freq function, as other architectures do. Signed-off-by: Mario Six --- arch/powerpc/cpu/mpc83xx/spl_minimal.c | 8 ++++++++ include/configs/MPC8315ERDB.h | 2 +- include/configs/ids8313.h | 2 +- 3 files changed, 10 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/cpu/mpc83xx/spl_minimal.c b/arch/powerpc/cpu/mpc83xx/spl_minimal.c index 746f1febba..3315ee05e1 100644 --- a/arch/powerpc/cpu/mpc83xx/spl_minimal.c +++ b/arch/powerpc/cpu/mpc83xx/spl_minimal.c @@ -89,3 +89,11 @@ void puts(const char *str) while (*str) putc(*str++); } + +ulong get_bus_freq(ulong dummy) +{ + volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; + u8 spmf = (im->clk.spmr & SPMR_SPMF) >> SPMR_SPMF_SHIFT; + + return CONFIG_83XX_CLKIN * spmf; +} diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index c373a0ab4c..adb2bb6c2d 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -271,7 +271,7 @@ */ #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2) +#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)) #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h index caa3dd1f1a..4b0ec273fb 100644 --- a/include/configs/ids8313.h +++ b/include/configs/ids8313.h @@ -301,7 +301,7 @@ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) -#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2) +#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)) #define CONFIG_HAS_FSL_DR_USB #define CONFIG_SYS_SCCR_USBDRCM 3 From ff3bb0c435e0d10ccb61a8fd2dada3ae72f1f97e Mon Sep 17 00:00:00 2001 From: Mario Six Date: Mon, 21 Jan 2019 09:17:53 +0100 Subject: [PATCH 30/86] mpc83xx: Get rid of CONFIG_83XX_CLKIN MPC83xx uses CONFIG_83XX_CLKIN instead of CONFIG_SYS_CLK_FREQ to set the system clock. To migrate the architecture, we can replace CONFIG_83XX_CLKIN with CONFIG_SYS_CLK_FREQ. To do this * replace all occurrences of CONFIG_83XX_CLKIN with CONFIG_SYS_CLK_FREQ * set CONFIG_SYS_CLK_FREQ to the old value of CONFIG_83XX_CLKIN in all MPC83xx config files Signed-off-by: Mario Six --- Kconfig | 2 +- arch/powerpc/cpu/mpc83xx/speed.c | 4 +-- arch/powerpc/cpu/mpc83xx/spl_minimal.c | 2 +- board/freescale/mpc8349emds/MAINTAINERS | 1 + board/freescale/mpc837xerdb/MAINTAINERS | 1 + board/tqc/tqm834x/pci.c | 2 +- configs/MPC8308RDB_defconfig | 1 + configs/MPC8313ERDB_33_defconfig | 1 + configs/MPC8313ERDB_66_defconfig | 1 + configs/MPC8313ERDB_NAND_33_defconfig | 1 + configs/MPC8313ERDB_NAND_66_defconfig | 1 + configs/MPC8315ERDB_defconfig | 1 + configs/MPC8323ERDB_defconfig | 1 + configs/MPC832XEMDS_ATM_defconfig | 1 + configs/MPC832XEMDS_HOST_33_defconfig | 1 + configs/MPC832XEMDS_HOST_66_defconfig | 1 + configs/MPC832XEMDS_SLAVE_defconfig | 1 + configs/MPC832XEMDS_defconfig | 1 + configs/MPC8349EMDS_SDRAM_defconfig | 1 + configs/MPC8349EMDS_SLAVE_defconfig | 25 ++++++++++++++++++ configs/MPC8349EMDS_defconfig | 1 + configs/MPC8349ITXGP_defconfig | 2 ++ configs/MPC8349ITX_LOWBOOT_defconfig | 1 + configs/MPC8349ITX_defconfig | 1 + configs/MPC837XEMDS_HOST_defconfig | 1 + configs/MPC837XEMDS_defconfig | 1 + configs/MPC837XERDB_SLAVE_defconfig | 34 +++++++++++++++++++++++++ configs/MPC837XERDB_defconfig | 2 ++ configs/TQM834x_defconfig | 1 + configs/caddy2_defconfig | 1 + configs/hrcon_defconfig | 1 + configs/hrcon_dh_defconfig | 1 + configs/ids8313_defconfig | 1 + configs/kmcoge5ne_defconfig | 1 + configs/kmeter1_defconfig | 1 + configs/kmopti2_defconfig | 1 + configs/kmsupx5_defconfig | 1 + configs/kmtegr1_defconfig | 1 + configs/kmtepr2_defconfig | 1 + configs/kmvect1_defconfig | 1 + configs/mpc8308_p1m_defconfig | 1 + configs/sbc8349_PCI_33_defconfig | 1 + configs/sbc8349_PCI_66_defconfig | 1 + configs/sbc8349_defconfig | 1 + configs/strider_con_defconfig | 1 + configs/strider_con_dp_defconfig | 1 + configs/strider_cpu_defconfig | 1 + configs/strider_cpu_dp_defconfig | 1 + configs/suvd3_defconfig | 1 + configs/tuge1_defconfig | 1 + configs/tuxx1_defconfig | 1 + configs/ve8313_defconfig | 1 + configs/vme8349_defconfig | 1 + include/configs/MPC8308RDB.h | 6 ----- include/configs/MPC8313ERDB_NAND.h | 17 +------------ include/configs/MPC8313ERDB_NOR.h | 15 +---------- include/configs/MPC8315ERDB.h | 6 ----- include/configs/MPC8323ERDB.h | 9 ------- include/configs/MPC832XEMDS.h | 13 ---------- include/configs/MPC8349EMDS.h | 19 ++------------ include/configs/MPC8349EMDS_SDRAM.h | 19 ++------------ include/configs/MPC8349ITX.h | 7 ----- include/configs/MPC837XEMDS.h | 13 ---------- include/configs/MPC837XERDB.h | 14 ---------- include/configs/TQM834x.h | 3 --- include/configs/caddy2.h | 11 -------- include/configs/hrcon.h | 6 ----- include/configs/ids8313.h | 3 --- include/configs/kmeter1.h | 7 ----- include/configs/mpc8308_p1m.h | 6 ----- include/configs/sbc8349.h | 16 ------------ include/configs/strider.h | 6 ----- include/configs/ve8313.h | 4 --- include/configs/vme8349.h | 9 ------- 74 files changed, 119 insertions(+), 208 deletions(-) create mode 100644 configs/MPC8349EMDS_SLAVE_defconfig create mode 100644 configs/MPC837XERDB_SLAVE_defconfig diff --git a/Kconfig b/Kconfig index da208d65a3..5f5c5ccfd6 100644 --- a/Kconfig +++ b/Kconfig @@ -512,7 +512,7 @@ config SYS_TEXT_BASE config SYS_CLK_FREQ - depends on ARC || ARCH_SUNXI + depends on ARC || ARCH_SUNXI || MPC83xx int "CPU clock frequency" help TODO: Move CONFIG_SYS_CLK_FREQ for all the architecture diff --git a/arch/powerpc/cpu/mpc83xx/speed.c b/arch/powerpc/cpu/mpc83xx/speed.c index 668ed27862..e870a23103 100644 --- a/arch/powerpc/cpu/mpc83xx/speed.c +++ b/arch/powerpc/cpu/mpc83xx/speed.c @@ -137,8 +137,8 @@ int get_clocks(void) clkin_div = ((im->clk.spmr & SPMR_CKID) >> SPMR_CKID_SHIFT); if (im->reset.rcwh & HRCWH_PCI_HOST) { -#if defined(CONFIG_83XX_CLKIN) - pci_sync_in = CONFIG_83XX_CLKIN / (1 + clkin_div); +#if defined(CONFIG_SYS_CLK_FREQ) + pci_sync_in = CONFIG_SYS_CLK_FREQ / (1 + clkin_div); #else pci_sync_in = 0xDEADBEEF; #endif diff --git a/arch/powerpc/cpu/mpc83xx/spl_minimal.c b/arch/powerpc/cpu/mpc83xx/spl_minimal.c index 3315ee05e1..2d6ba12e2d 100644 --- a/arch/powerpc/cpu/mpc83xx/spl_minimal.c +++ b/arch/powerpc/cpu/mpc83xx/spl_minimal.c @@ -95,5 +95,5 @@ ulong get_bus_freq(ulong dummy) volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; u8 spmf = (im->clk.spmr & SPMR_SPMF) >> SPMR_SPMF_SHIFT; - return CONFIG_83XX_CLKIN * spmf; + return CONFIG_SYS_CLK_FREQ * spmf; } diff --git a/board/freescale/mpc8349emds/MAINTAINERS b/board/freescale/mpc8349emds/MAINTAINERS index b676c07492..0719225671 100644 --- a/board/freescale/mpc8349emds/MAINTAINERS +++ b/board/freescale/mpc8349emds/MAINTAINERS @@ -5,3 +5,4 @@ F: board/freescale/mpc8349emds/ F: include/configs/MPC8349EMDS.h F: configs/MPC8349EMDS_defconfig F: configs/MPC8349EMDS_SDRAM_defconfig +F: configs/MPC8349EMDS_SLAVE_defconfig diff --git a/board/freescale/mpc837xerdb/MAINTAINERS b/board/freescale/mpc837xerdb/MAINTAINERS index 81b4eed5ed..9f44a37a0d 100644 --- a/board/freescale/mpc837xerdb/MAINTAINERS +++ b/board/freescale/mpc837xerdb/MAINTAINERS @@ -4,3 +4,4 @@ S: Maintained F: board/freescale/mpc837xerdb/ F: include/configs/MPC837XERDB.h F: configs/MPC837XERDB_defconfig +F: configs/MPC837XERDB_SLAVE_defconfig diff --git a/board/tqc/tqm834x/pci.c b/board/tqc/tqm834x/pci.c index 34c68ac463..c9b05e44c2 100644 --- a/board/tqc/tqm834x/pci.c +++ b/board/tqc/tqm834x/pci.c @@ -71,7 +71,7 @@ pci_init_board(void) reg32 = 0xff000000; #endif if (clk->spmr & SPMR_CKID) { - /* PCI Clock is half CONFIG_83XX_CLKIN so need to set up OCCR + /* PCI Clock is half CONFIG_SYS_CLK_FREQ so need to set up OCCR * fields accordingly */ reg32 |= (OCCR_PCI1CR | OCCR_PCI2CR); diff --git a/configs/MPC8308RDB_defconfig b/configs/MPC8308RDB_defconfig index 06657b2bfe..59dde136f2 100644 --- a/configs/MPC8308RDB_defconfig +++ b/configs/MPC8308RDB_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 +CONFIG_SYS_CLK_FREQ=33333333 CONFIG_MPC83xx=y CONFIG_TARGET_MPC8308RDB=y CONFIG_FIT=y diff --git a/configs/MPC8313ERDB_33_defconfig b/configs/MPC8313ERDB_33_defconfig index cacb5ba077..4851611cf5 100644 --- a/configs/MPC8313ERDB_33_defconfig +++ b/configs/MPC8313ERDB_33_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 +CONFIG_SYS_CLK_FREQ=33333333 CONFIG_MPC83xx=y CONFIG_TARGET_MPC8313ERDB_NOR=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/MPC8313ERDB_66_defconfig b/configs/MPC8313ERDB_66_defconfig index 6b29c2e5c9..fb4fddec46 100644 --- a/configs/MPC8313ERDB_66_defconfig +++ b/configs/MPC8313ERDB_66_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 +CONFIG_SYS_CLK_FREQ=66666667 CONFIG_MPC83xx=y CONFIG_TARGET_MPC8313ERDB_NOR=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/MPC8313ERDB_NAND_33_defconfig b/configs/MPC8313ERDB_NAND_33_defconfig index bcb83b1308..80ed52b2e1 100644 --- a/configs/MPC8313ERDB_NAND_33_defconfig +++ b/configs/MPC8313ERDB_NAND_33_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0x00100000 CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL=y +CONFIG_SYS_CLK_FREQ=33333333 CONFIG_MPC83xx=y CONFIG_TARGET_MPC8313ERDB_NAND=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/MPC8313ERDB_NAND_66_defconfig b/configs/MPC8313ERDB_NAND_66_defconfig index 746ea27dc5..d0d84d429d 100644 --- a/configs/MPC8313ERDB_NAND_66_defconfig +++ b/configs/MPC8313ERDB_NAND_66_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0x00100000 CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL=y +CONFIG_SYS_CLK_FREQ=66666667 CONFIG_MPC83xx=y CONFIG_TARGET_MPC8313ERDB_NAND=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/MPC8315ERDB_defconfig b/configs/MPC8315ERDB_defconfig index b45369e626..15dbbe35dd 100644 --- a/configs/MPC8315ERDB_defconfig +++ b/configs/MPC8315ERDB_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 +CONFIG_SYS_CLK_FREQ=66666667 CONFIG_MPC83xx=y CONFIG_TARGET_MPC8315ERDB=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/MPC8323ERDB_defconfig b/configs/MPC8323ERDB_defconfig index a1227bfdad..c43ae8c992 100644 --- a/configs/MPC8323ERDB_defconfig +++ b/configs/MPC8323ERDB_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 +CONFIG_SYS_CLK_FREQ=66666667 CONFIG_MPC83xx=y CONFIG_TARGET_MPC8323ERDB=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/MPC832XEMDS_ATM_defconfig b/configs/MPC832XEMDS_ATM_defconfig index e4c44d90a9..a40f16d49b 100644 --- a/configs/MPC832XEMDS_ATM_defconfig +++ b/configs/MPC832XEMDS_ATM_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 +CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_MPC832XEMDS=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/MPC832XEMDS_HOST_33_defconfig b/configs/MPC832XEMDS_HOST_33_defconfig index 2b03a56245..1031dd655a 100644 --- a/configs/MPC832XEMDS_HOST_33_defconfig +++ b/configs/MPC832XEMDS_HOST_33_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 +CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_MPC832XEMDS=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/MPC832XEMDS_HOST_66_defconfig b/configs/MPC832XEMDS_HOST_66_defconfig index 4aa34dc331..416e0e9aea 100644 --- a/configs/MPC832XEMDS_HOST_66_defconfig +++ b/configs/MPC832XEMDS_HOST_66_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 +CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_MPC832XEMDS=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/MPC832XEMDS_SLAVE_defconfig b/configs/MPC832XEMDS_SLAVE_defconfig index 332088934a..29b8f1a988 100644 --- a/configs/MPC832XEMDS_SLAVE_defconfig +++ b/configs/MPC832XEMDS_SLAVE_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 +CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_MPC832XEMDS=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/MPC832XEMDS_defconfig b/configs/MPC832XEMDS_defconfig index f3ec967b3c..2a15e5c18e 100644 --- a/configs/MPC832XEMDS_defconfig +++ b/configs/MPC832XEMDS_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 +CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_MPC832XEMDS=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/MPC8349EMDS_SDRAM_defconfig b/configs/MPC8349EMDS_SDRAM_defconfig index a98cc74027..d4f6587bb3 100644 --- a/configs/MPC8349EMDS_SDRAM_defconfig +++ b/configs/MPC8349EMDS_SDRAM_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 +CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_MPC8349EMDS_SDRAM=y CONFIG_PCI_ONE_PCI1=y diff --git a/configs/MPC8349EMDS_SLAVE_defconfig b/configs/MPC8349EMDS_SLAVE_defconfig new file mode 100644 index 0000000000..11e3b144b7 --- /dev/null +++ b/configs/MPC8349EMDS_SLAVE_defconfig @@ -0,0 +1,25 @@ +CONFIG_PPC=y +CONFIG_SYS_TEXT_BASE=0xFE000000 +CONFIG_SYS_CLK_FREQ=66666666 +CONFIG_MPC83xx=y +CONFIG_TARGET_MPC8349EMDS=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_SYS_EXTRA_OPTIONS="PCISLAVE" +CONFIG_BOOTDELAY=6 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_IMLS=y +CONFIG_CMD_I2C=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_DATE=y +# CONFIG_MMC is not set +CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_CFI_DRIVER=y +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y +CONFIG_SYS_FLASH_CFI=y +CONFIG_PHYLIB=y +# CONFIG_PCI is not set +CONFIG_SYS_NS16550=y +CONFIG_OF_LIBFDT=y diff --git a/configs/MPC8349EMDS_defconfig b/configs/MPC8349EMDS_defconfig index bd8ff625e1..9a6eebf746 100644 --- a/configs/MPC8349EMDS_defconfig +++ b/configs/MPC8349EMDS_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 +CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_MPC8349EMDS=y CONFIG_PCI_ONE_PCI1=y diff --git a/configs/MPC8349ITXGP_defconfig b/configs/MPC8349ITXGP_defconfig index 95d807bac0..c7f465e409 100644 --- a/configs/MPC8349ITXGP_defconfig +++ b/configs/MPC8349ITXGP_defconfig @@ -1,9 +1,11 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 +CONFIG_SYS_CLK_FREQ=66666666 CONFIG_MPC83xx=y CONFIG_TARGET_MPC8349ITX=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFE000000" CONFIG_BOOTDELAY=6 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=:/nfsroot/rootfs ip=::::mpc8349emitxgp:eth0:off console=ttyS0,115200" diff --git a/configs/MPC8349ITX_LOWBOOT_defconfig b/configs/MPC8349ITX_LOWBOOT_defconfig index 22225e3ad6..7dbde3222b 100644 --- a/configs/MPC8349ITX_LOWBOOT_defconfig +++ b/configs/MPC8349ITX_LOWBOOT_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 +CONFIG_SYS_CLK_FREQ=66666666 CONFIG_MPC83xx=y CONFIG_TARGET_MPC8349ITX=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/MPC8349ITX_defconfig b/configs/MPC8349ITX_defconfig index 7f9b9cb283..d3ab1eafeb 100644 --- a/configs/MPC8349ITX_defconfig +++ b/configs/MPC8349ITX_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFEF00000 +CONFIG_SYS_CLK_FREQ=66666666 CONFIG_MPC83xx=y CONFIG_TARGET_MPC8349ITX=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/MPC837XEMDS_HOST_defconfig b/configs/MPC837XEMDS_HOST_defconfig index 4ac95735b2..15d60a2ccd 100644 --- a/configs/MPC837XEMDS_HOST_defconfig +++ b/configs/MPC837XEMDS_HOST_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 +CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_MPC837XEMDS=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/MPC837XEMDS_defconfig b/configs/MPC837XEMDS_defconfig index 9ee8c7d880..d5d42ab12f 100644 --- a/configs/MPC837XEMDS_defconfig +++ b/configs/MPC837XEMDS_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 +CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_MPC837XEMDS=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/MPC837XERDB_SLAVE_defconfig b/configs/MPC837XERDB_SLAVE_defconfig new file mode 100644 index 0000000000..8c2389c698 --- /dev/null +++ b/configs/MPC837XERDB_SLAVE_defconfig @@ -0,0 +1,34 @@ +CONFIG_PPC=y +CONFIG_SYS_TEXT_BASE=0xFE000000 +CONFIG_SYS_CLK_FREQ=66666667 +CONFIG_MPC83xx=y +CONFIG_TARGET_MPC837XERDB=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_SYS_EXTRA_OPTIONS="PCISLAVE,PCIE" +CONFIG_BOOTDELAY=6 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_IMLS=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_SATA=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_DATE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_FAT=y +CONFIG_FSL_SATA=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_FLASH_CFI_DRIVER=y +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y +CONFIG_SYS_FLASH_CFI=y +CONFIG_TSEC_ENET=y +CONFIG_SYS_NS16550=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_STORAGE=y +CONFIG_OF_LIBFDT=y diff --git a/configs/MPC837XERDB_defconfig b/configs/MPC837XERDB_defconfig index 45b68e9092..090b9e5152 100644 --- a/configs/MPC837XERDB_defconfig +++ b/configs/MPC837XERDB_defconfig @@ -1,9 +1,11 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 +CONFIG_SYS_CLK_FREQ=66666667 CONFIG_MPC83xx=y CONFIG_TARGET_MPC837XERDB=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_SYS_EXTRA_OPTIONS="PCIE" CONFIG_BOOTDELAY=6 CONFIG_MISC_INIT_R=y CONFIG_HUSH_PARSER=y diff --git a/configs/TQM834x_defconfig b/configs/TQM834x_defconfig index e1a7a06306..8f68804a48 100644 --- a/configs/TQM834x_defconfig +++ b/configs/TQM834x_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0x80000000 +CONFIG_SYS_CLK_FREQ=66666000 CONFIG_MPC83xx=y CONFIG_TARGET_TQM834X=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/caddy2_defconfig b/configs/caddy2_defconfig index fe0c34fc61..2d2d64d103 100644 --- a/configs/caddy2_defconfig +++ b/configs/caddy2_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFFF00000 +CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_CADDY2=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/hrcon_defconfig b/configs/hrcon_defconfig index 7605c56619..2a7b932b1e 100644 --- a/configs/hrcon_defconfig +++ b/configs/hrcon_defconfig @@ -1,6 +1,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_IDENT_STRING=" hrcon 0.01" +CONFIG_SYS_CLK_FREQ=33333333 CONFIG_MPC83xx=y CONFIG_TARGET_HRCON=y CONFIG_CMD_IOLOOP=y diff --git a/configs/hrcon_dh_defconfig b/configs/hrcon_dh_defconfig index bc51a5d02a..3b1fbca268 100644 --- a/configs/hrcon_dh_defconfig +++ b/configs/hrcon_dh_defconfig @@ -1,6 +1,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_IDENT_STRING=" hrcon dh 0.01" +CONFIG_SYS_CLK_FREQ=33333333 CONFIG_MPC83xx=y CONFIG_TARGET_HRCON=y CONFIG_CMD_IOLOOP=y diff --git a/configs/ids8313_defconfig b/configs/ids8313_defconfig index 0d055e395d..7223af1f55 100644 --- a/configs/ids8313_defconfig +++ b/configs/ids8313_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFFF00000 +CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_IDS8313=y CONFIG_FIT=y diff --git a/configs/kmcoge5ne_defconfig b/configs/kmcoge5ne_defconfig index b7c42fa9cb..beac453ce5 100644 --- a/configs/kmcoge5ne_defconfig +++ b/configs/kmcoge5ne_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xF0000000 +CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_KMCOGE5NE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/kmeter1_defconfig b/configs/kmeter1_defconfig index 1773f74358..2bf2c40a63 100644 --- a/configs/kmeter1_defconfig +++ b/configs/kmeter1_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xF0000000 +CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_KMETER1=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/kmopti2_defconfig b/configs/kmopti2_defconfig index c0927dd478..1b63b427f0 100644 --- a/configs/kmopti2_defconfig +++ b/configs/kmopti2_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xF0000000 +CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_KMOPTI2=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/kmsupx5_defconfig b/configs/kmsupx5_defconfig index 7a00c85a84..df1bfaef18 100644 --- a/configs/kmsupx5_defconfig +++ b/configs/kmsupx5_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xF0000000 +CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_KMSUPX5=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/kmtegr1_defconfig b/configs/kmtegr1_defconfig index 38a861b861..7187af7786 100644 --- a/configs/kmtegr1_defconfig +++ b/configs/kmtegr1_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xF0000000 +CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_KMTEGR1=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/kmtepr2_defconfig b/configs/kmtepr2_defconfig index 310cf5ac66..bbd13b8bfa 100644 --- a/configs/kmtepr2_defconfig +++ b/configs/kmtepr2_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xF0000000 +CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_KMTEPR2=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/kmvect1_defconfig b/configs/kmvect1_defconfig index 2f71ee7519..98dd9e2b37 100644 --- a/configs/kmvect1_defconfig +++ b/configs/kmvect1_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xF0000000 +CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_KMVECT1=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/mpc8308_p1m_defconfig b/configs/mpc8308_p1m_defconfig index 114ffeeddb..1e50782f7c 100644 --- a/configs/mpc8308_p1m_defconfig +++ b/configs/mpc8308_p1m_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFC000000 +CONFIG_SYS_CLK_FREQ=33333333 CONFIG_MPC83xx=y CONFIG_TARGET_MPC8308_P1M=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/sbc8349_PCI_33_defconfig b/configs/sbc8349_PCI_33_defconfig index 5c2720aef1..eca22bec3a 100644 --- a/configs/sbc8349_PCI_33_defconfig +++ b/configs/sbc8349_PCI_33_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFF800000 +CONFIG_SYS_CLK_FREQ=33000000 CONFIG_MPC83xx=y CONFIG_TARGET_SBC8349=y CONFIG_PCI_64BIT=y diff --git a/configs/sbc8349_PCI_66_defconfig b/configs/sbc8349_PCI_66_defconfig index e6535dafcf..fa1ec519c5 100644 --- a/configs/sbc8349_PCI_66_defconfig +++ b/configs/sbc8349_PCI_66_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFF800000 +CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_SBC8349=y CONFIG_PCI_64BIT=y diff --git a/configs/sbc8349_defconfig b/configs/sbc8349_defconfig index 82379e67d2..d70332c785 100644 --- a/configs/sbc8349_defconfig +++ b/configs/sbc8349_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFF800000 +CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_SBC8349=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/strider_con_defconfig b/configs/strider_con_defconfig index 24c793dfc5..194cebdb67 100644 --- a/configs/strider_con_defconfig +++ b/configs/strider_con_defconfig @@ -1,6 +1,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_IDENT_STRING=" strider con 0.01" +CONFIG_SYS_CLK_FREQ=33333333 CONFIG_MPC83xx=y CONFIG_TARGET_STRIDER=y CONFIG_CMD_IOLOOP=y diff --git a/configs/strider_con_dp_defconfig b/configs/strider_con_dp_defconfig index c70d99a7e6..4e72582d2f 100644 --- a/configs/strider_con_dp_defconfig +++ b/configs/strider_con_dp_defconfig @@ -1,6 +1,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_IDENT_STRING=" strider con dp 0.01" +CONFIG_SYS_CLK_FREQ=33333333 CONFIG_MPC83xx=y CONFIG_TARGET_STRIDER=y CONFIG_CMD_IOLOOP=y diff --git a/configs/strider_cpu_defconfig b/configs/strider_cpu_defconfig index fef58848af..c633e030e3 100644 --- a/configs/strider_cpu_defconfig +++ b/configs/strider_cpu_defconfig @@ -1,6 +1,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_IDENT_STRING=" strider cpu 0.01" +CONFIG_SYS_CLK_FREQ=33333333 CONFIG_MPC83xx=y CONFIG_TARGET_STRIDER=y CONFIG_CMD_IOLOOP=y diff --git a/configs/strider_cpu_dp_defconfig b/configs/strider_cpu_dp_defconfig index fc8f39eb54..e1d08e782d 100644 --- a/configs/strider_cpu_dp_defconfig +++ b/configs/strider_cpu_dp_defconfig @@ -1,6 +1,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_IDENT_STRING=" strider cpu dp 0.01" +CONFIG_SYS_CLK_FREQ=33333333 CONFIG_MPC83xx=y CONFIG_TARGET_STRIDER=y CONFIG_CMD_IOLOOP=y diff --git a/configs/suvd3_defconfig b/configs/suvd3_defconfig index e6b97b866d..4744122e4e 100644 --- a/configs/suvd3_defconfig +++ b/configs/suvd3_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xF0000000 +CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_SUVD3=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/tuge1_defconfig b/configs/tuge1_defconfig index a3e04bc0f8..349b1d0009 100644 --- a/configs/tuge1_defconfig +++ b/configs/tuge1_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xF0000000 +CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_TUGE1=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/tuxx1_defconfig b/configs/tuxx1_defconfig index d1fc62697e..a6654c9025 100644 --- a/configs/tuxx1_defconfig +++ b/configs/tuxx1_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xF0000000 +CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_TUXX1=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/ve8313_defconfig b/configs/ve8313_defconfig index 584aafb08f..084b1bdeaf 100644 --- a/configs/ve8313_defconfig +++ b/configs/ve8313_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 +CONFIG_SYS_CLK_FREQ=32000000 CONFIG_MPC83xx=y CONFIG_TARGET_VE8313=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/vme8349_defconfig b/configs/vme8349_defconfig index 90c29b7fed..aae2214192 100644 --- a/configs/vme8349_defconfig +++ b/configs/vme8349_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFFF00000 +CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_VME8349=y CONFIG_PCI_64BIT=y diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h index 7bf91524c8..77c30093bf 100644 --- a/include/configs/MPC8308RDB.h +++ b/include/configs/MPC8308RDB.h @@ -27,12 +27,6 @@ #define CONFIG_TSEC1 #define CONFIG_VSC7385_ENET -/* - * System Clock Setup - */ -#define CONFIG_83XX_CLKIN 33333333 /* in Hz */ -#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN - /* * Hardware Reset Configuration Word * if CLKIN is 66.66MHz, then diff --git a/include/configs/MPC8313ERDB_NAND.h b/include/configs/MPC8313ERDB_NAND.h index 31c2900180..103ace2d3a 100644 --- a/include/configs/MPC8313ERDB_NAND.h +++ b/include/configs/MPC8313ERDB_NAND.h @@ -54,16 +54,6 @@ #define CONFIG_VSC7385_ENET #define CONFIG_TSEC2 -#ifdef CONFIG_SYS_66MHZ -#define CONFIG_83XX_CLKIN 66666667 /* in Hz */ -#elif defined(CONFIG_SYS_33MHZ) -#define CONFIG_83XX_CLKIN 33333333 /* in Hz */ -#else -#error Unknown oscillator frequency. -#endif - -#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN - #define CONFIG_SYS_IMMR 0xE0000000 #if !defined(CONFIG_SPL_BUILD) @@ -445,9 +435,6 @@ HRCWL_DDR_TO_SCB_CLK_2X1 |\ HRCWL_CSB_TO_CLKIN_2X1 |\ HRCWL_CORE_TO_CSB_2X1) - -#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2) - #elif defined(CONFIG_SYS_33MHZ) /* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */ @@ -459,9 +446,6 @@ HRCWL_DDR_TO_SCB_CLK_2X1 |\ HRCWL_CSB_TO_CLKIN_5X1 |\ HRCWL_CORE_TO_CSB_2X1) - -#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 5) - #endif #define CONFIG_SYS_HRCW_HIGH_BASE (\ @@ -478,6 +462,7 @@ HRCWH_FROM_0XFFF00100 |\ HRCWH_ROM_LOC_NAND_SP_8BIT |\ HRCWH_RL_EXT_NAND) +#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)) /* System IO Config */ #define CONFIG_SYS_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */ diff --git a/include/configs/MPC8313ERDB_NOR.h b/include/configs/MPC8313ERDB_NOR.h index afb0586c4b..64b289adce 100644 --- a/include/configs/MPC8313ERDB_NOR.h +++ b/include/configs/MPC8313ERDB_NOR.h @@ -30,16 +30,6 @@ #define CONFIG_VSC7385_ENET #define CONFIG_TSEC2 -#ifdef CONFIG_SYS_66MHZ -#define CONFIG_83XX_CLKIN 66666667 /* in Hz */ -#elif defined(CONFIG_SYS_33MHZ) -#define CONFIG_83XX_CLKIN 33333333 /* in Hz */ -#else -#error Unknown oscillator frequency. -#endif - -#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN - #define CONFIG_SYS_IMMR 0xE0000000 #define CONFIG_SYS_MEMTEST_START 0x00001000 @@ -420,8 +410,6 @@ HRCWL_CSB_TO_CLKIN_2X1 |\ HRCWL_CORE_TO_CSB_2X1) -#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2) - #elif defined(CONFIG_SYS_33MHZ) /* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */ @@ -434,8 +422,6 @@ HRCWL_CSB_TO_CLKIN_5X1 |\ HRCWL_CORE_TO_CSB_2X1) -#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 5) - #endif #define CONFIG_SYS_HRCW_HIGH_BASE (\ @@ -452,6 +438,7 @@ HRCWH_FROM_0X00000100 |\ HRCWH_ROM_LOC_LOCAL_16BIT |\ HRCWH_RL_EXT_LEGACY) +#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)) /* System IO Config */ #define CONFIG_SYS_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */ diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index adb2bb6c2d..53a02f415f 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -23,12 +23,6 @@ */ #define CONFIG_E300 1 /* E300 family */ -/* - * System Clock Setup - */ -#define CONFIG_83XX_CLKIN 66666667 /* in Hz */ -#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN - /* * Hardware Reset Configuration Word * if CLKIN is 66.66MHz, then diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index bd1b1bb0a7..ee4eeec885 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -15,15 +15,6 @@ #define CONFIG_E300 1 /* E300 family */ #define CONFIG_QE 1 /* Has QE */ -/* - * System Clock Setup - */ -#define CONFIG_83XX_CLKIN 66666667 /* in Hz */ - -#ifndef CONFIG_SYS_CLK_FREQ -#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN -#endif - /* * Hardware Reset Configuration Word */ diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index 4cb595bb8e..0ba6477254 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -12,19 +12,6 @@ #define CONFIG_E300 1 /* E300 family */ #define CONFIG_QE 1 /* Has QE */ -/* - * System Clock Setup - */ -#ifdef CONFIG_PCISLAVE -#define CONFIG_83XX_PCICLK 66000000 /* in HZ */ -#else -#define CONFIG_83XX_CLKIN 66000000 /* in Hz */ -#endif - -#ifndef CONFIG_SYS_CLK_FREQ -#define CONFIG_SYS_CLK_FREQ 66000000 -#endif - /* * Hardware Reset Configuration Word */ diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 40e5c1997d..4c9ee76815 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -17,26 +17,11 @@ */ #define CONFIG_E300 1 /* E300 Family */ -#define CONFIG_PCI_66M -#ifdef CONFIG_PCI_66M -#define CONFIG_83XX_CLKIN 66000000 /* in Hz */ -#else -#define CONFIG_83XX_CLKIN 33000000 /* in Hz */ -#endif - -#ifdef CONFIG_PCISLAVE -#define CONFIG_83XX_PCICLK 66666666 /* in Hz */ -#endif /* CONFIG_PCISLAVE */ - -#ifndef CONFIG_SYS_CLK_FREQ -#ifdef CONFIG_PCI_66M -#define CONFIG_SYS_CLK_FREQ 66000000 +#if CONFIG_SYS_CLK_FREQ == 66000000 || CONFIG_SYS_CLK_FREQ == 66666666 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1 -#else -#define CONFIG_SYS_CLK_FREQ 33000000 +#elif CONFIG_SYS_CLK_FREQ == 33000000 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1 #endif -#endif #define CONFIG_SYS_IMMR 0xE0000000 diff --git a/include/configs/MPC8349EMDS_SDRAM.h b/include/configs/MPC8349EMDS_SDRAM.h index 15f10492a5..b9710b6588 100644 --- a/include/configs/MPC8349EMDS_SDRAM.h +++ b/include/configs/MPC8349EMDS_SDRAM.h @@ -17,26 +17,11 @@ */ #define CONFIG_E300 1 /* E300 Family */ -#define CONFIG_PCI_66M -#ifdef CONFIG_PCI_66M -#define CONFIG_83XX_CLKIN 66000000 /* in Hz */ -#else -#define CONFIG_83XX_CLKIN 33000000 /* in Hz */ -#endif - -#ifdef CONFIG_PCISLAVE -#define CONFIG_83XX_PCICLK 66666666 /* in Hz */ -#endif /* CONFIG_PCISLAVE */ - -#ifndef CONFIG_SYS_CLK_FREQ -#ifdef CONFIG_PCI_66M -#define CONFIG_SYS_CLK_FREQ 66000000 +#if CONFIG_SYS_CLK_FREQ == 66000000 || CONFIG_SYS_CLK_FREQ == 66666666 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1 -#else -#define CONFIG_SYS_CLK_FREQ 33000000 +#elif CONFIG_SYS_CLK_FREQ == 33000000 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1 #endif -#endif #define CONFIG_SYS_IMMR 0xE0000000 diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index 5877279ada..e170271c40 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -391,13 +391,6 @@ boards, we say we have two, but don't display a message if we find only one. */ #endif -#define CONFIG_PCI_66M -#ifdef CONFIG_PCI_66M -#define CONFIG_83XX_CLKIN 66666666 /* in Hz */ -#else -#define CONFIG_83XX_CLKIN 33333333 /* in Hz */ -#endif - /* TSEC */ #ifdef CONFIG_TSEC_ENET diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index 577f7ec0b2..33c485aab7 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -12,19 +12,6 @@ */ #define CONFIG_E300 1 /* E300 family */ -/* - * System Clock Setup - */ -#ifdef CONFIG_PCISLAVE -#define CONFIG_83XX_PCICLK 66000000 /* in HZ */ -#else -#define CONFIG_83XX_CLKIN 66000000 /* in Hz */ -#endif - -#ifndef CONFIG_SYS_CLK_FREQ -#define CONFIG_SYS_CLK_FREQ 66000000 -#endif - /* * Hardware Reset Configuration Word * if CLKIN is 66MHz, then diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index a8f5b013b2..806b0f32e5 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -20,20 +20,6 @@ */ #define CONFIG_VSC7385_ENET -/* - * System Clock Setup - */ -#ifdef CONFIG_PCISLAVE -#define CONFIG_83XX_PCICLK 66666667 /* in HZ */ -#else -#define CONFIG_83XX_CLKIN 66666667 /* in Hz */ -#define CONFIG_PCIE -#endif - -#ifndef CONFIG_SYS_CLK_FREQ -#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN -#endif - /* * Hardware Reset Configuration Word */ diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index 949e370150..58c301553e 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -19,9 +19,6 @@ /* IMMR Base Address Register, use Freescale default: 0xff400000 */ #define CONFIG_SYS_IMMR 0xff400000 -/* System clock. Primary input clock when in PCI host mode */ -#define CONFIG_83XX_CLKIN 66666000 /* 66,666 MHz */ - /* * Local Bus LCRR * LCRR: DLL bypass, Clock divider is 8 diff --git a/include/configs/caddy2.h b/include/configs/caddy2.h index a8f692d5ea..68fb989856 100644 --- a/include/configs/caddy2.h +++ b/include/configs/caddy2.h @@ -25,22 +25,11 @@ /* Don't enable PCI2 on vme834x - it doesn't exist physically. */ #undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */ -#define CONFIG_PCI_66M #ifdef CONFIG_PCI_66M -#define CONFIG_83XX_CLKIN 66000000 /* in Hz */ -#else -#define CONFIG_83XX_CLKIN 33000000 /* in Hz */ -#endif - -#ifndef CONFIG_SYS_CLK_FREQ -#ifdef CONFIG_PCI_66M -#define CONFIG_SYS_CLK_FREQ 66000000 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1 #else -#define CONFIG_SYS_CLK_FREQ 33000000 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1 #endif -#endif #define CONFIG_SYS_IMMR 0xE0000000 diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h index cd5e883b7a..8eb12b7670 100644 --- a/include/configs/hrcon.h +++ b/include/configs/hrcon.h @@ -16,12 +16,6 @@ #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR -/* - * System Clock Setup - */ -#define CONFIG_83XX_CLKIN 33333333 /* in Hz */ -#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN - /* * Hardware Reset Configuration Word * if CLKIN is 66.66MHz, then diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h index 4b0ec273fb..eff0addd51 100644 --- a/include/configs/ids8313.h +++ b/include/configs/ids8313.h @@ -20,9 +20,6 @@ #define CONFIG_BOOT_RETRY_MIN 30 #define CONFIG_RESET_TO_RETRY -#define CONFIG_83XX_CLKIN 66000000 /* in Hz */ -#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN - #define CONFIG_SYS_IMMR 0xF0000000 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h index 976255f578..2280f007f2 100644 --- a/include/configs/kmeter1.h +++ b/include/configs/kmeter1.h @@ -25,13 +25,6 @@ #include "km/keymile-common.h" #include "km/km-powerpc.h" -/* - * System Clock Setup - */ -#define CONFIG_83XX_CLKIN 66000000 -#define CONFIG_SYS_CLK_FREQ 66000000 -#define CONFIG_83XX_PCICLK 66000000 - /* * IMMR new address */ diff --git a/include/configs/mpc8308_p1m.h b/include/configs/mpc8308_p1m.h index c007877276..fd59471370 100644 --- a/include/configs/mpc8308_p1m.h +++ b/include/configs/mpc8308_p1m.h @@ -21,12 +21,6 @@ #define CONFIG_TSEC1 #define CONFIG_TSEC2 -/* - * System Clock Setup - */ -#define CONFIG_83XX_CLKIN 33333333 /* in Hz */ -#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN - /* * Hardware Reset Configuration Word * if CLKIN is 66.66MHz, then diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index 60eb2cf831..2520a77dd3 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -22,27 +22,11 @@ /* Don't enable PCI2 on sbc834x - it doesn't exist physically. */ #undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */ -/* - * The default if PCI isn't enabled, or if no PCI clk setting is given - * is 66MHz; this is what the board defaults to when the PCI slot is - * physically empty. The board will automatically (i.e w/o jumpers) - * clock down to 33MHz if you insert a 33MHz PCI card. - */ #ifdef CONFIG_PCI_33M -#define CONFIG_83XX_CLKIN 33000000 /* in Hz */ -#else /* 66M */ -#define CONFIG_83XX_CLKIN 66000000 /* in Hz */ -#endif - -#ifndef CONFIG_SYS_CLK_FREQ -#ifdef CONFIG_PCI_33M -#define CONFIG_SYS_CLK_FREQ 33000000 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1 #else /* 66M */ -#define CONFIG_SYS_CLK_FREQ 66000000 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1 #endif -#endif #define CONFIG_SYS_IMMR 0xE0000000 diff --git a/include/configs/strider.h b/include/configs/strider.h index c42fe8c3ec..8c9acfba8d 100644 --- a/include/configs/strider.h +++ b/include/configs/strider.h @@ -16,12 +16,6 @@ #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR -/* - * System Clock Setup - */ -#define CONFIG_83XX_CLKIN 33333333 /* in Hz */ -#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN - /* * Hardware Reset Configuration Word * if CLKIN is 66.66MHz, then diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h index 87fbe36640..2ef6f88bdf 100644 --- a/include/configs/ve8313.h +++ b/include/configs/ve8313.h @@ -24,10 +24,6 @@ * On-board devices * */ -#define CONFIG_83XX_CLKIN 32000000 /* in Hz */ - -#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN - #define CONFIG_SYS_IMMR 0xE0000000 #define CONFIG_SYS_MEMTEST_START 0x00001000 diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h index ea08058752..c5086958ff 100644 --- a/include/configs/vme8349.h +++ b/include/configs/vme8349.h @@ -26,21 +26,12 @@ #undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */ #define CONFIG_PCI_66M -#ifdef CONFIG_PCI_66M -#define CONFIG_83XX_CLKIN 66000000 /* in Hz */ -#else -#define CONFIG_83XX_CLKIN 33000000 /* in Hz */ -#endif -#ifndef CONFIG_SYS_CLK_FREQ #ifdef CONFIG_PCI_66M -#define CONFIG_SYS_CLK_FREQ 66000000 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1 #else -#define CONFIG_SYS_CLK_FREQ 33000000 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1 #endif -#endif #define CONFIG_SYS_IMMR 0xE0000000 From 21c1502a4a81904706b9883f523ec4a94aba880f Mon Sep 17 00:00:00 2001 From: Mario Six Date: Mon, 21 Jan 2019 09:17:54 +0100 Subject: [PATCH 31/86] mpc83xx: Kconfig: Migrate HRCW to Kconfig The HRCW (hardware reset configuration word) is a constant that must be hard-coded into the boot loader image. So, it must be available at compile time, and cannot be migrated to the DT mechanism, but has to be kept in Kconfig. Configuration of this crucial variable should still be somewhat comfortable. Hence, make its fields configurable in Kconfig, and assemble the final value from these. Signed-off-by: Mario Six --- arch/powerpc/cpu/mpc83xx/Kconfig | 69 ++ arch/powerpc/cpu/mpc83xx/hrcw/Kconfig | 816 ++++++++++++++++++++++++ arch/powerpc/cpu/mpc83xx/hrcw/hrcw.h | 37 ++ arch/powerpc/cpu/mpc83xx/start.S | 2 + board/freescale/mpc8315erdb/MAINTAINERS | 1 + board/freescale/mpc8349emds/MAINTAINERS | 1 + board/freescale/mpc8349itx/mpc8349itx.c | 2 + board/freescale/mpc837xemds/MAINTAINERS | 1 + configs/MPC8308RDB_defconfig | 7 + configs/MPC8313ERDB_33_defconfig | 8 + configs/MPC8313ERDB_66_defconfig | 7 + configs/MPC8313ERDB_NAND_33_defconfig | 7 + configs/MPC8313ERDB_NAND_66_defconfig | 6 + configs/MPC8315ERDB_defconfig | 8 + configs/MPC8323ERDB_defconfig | 6 + configs/MPC832XEMDS_ATM_defconfig | 6 + configs/MPC832XEMDS_HOST_33_defconfig | 6 + configs/MPC832XEMDS_HOST_66_defconfig | 6 + configs/MPC832XEMDS_SLAVE_defconfig | 3 + configs/MPC832XEMDS_defconfig | 6 + configs/MPC8349EMDS_PCI64_defconfig | 35 + configs/MPC8349EMDS_SDRAM_defconfig | 10 + configs/MPC8349EMDS_SLAVE_defconfig | 12 +- configs/MPC8349EMDS_defconfig | 10 + configs/MPC8349ITXGP_defconfig | 10 + configs/MPC8349ITX_LOWBOOT_defconfig | 10 + configs/MPC8349ITX_defconfig | 9 + configs/MPC837XEMDS_HOST_defconfig | 10 + configs/MPC837XEMDS_SLAVE_defconfig | 35 + configs/MPC837XEMDS_defconfig | 10 + configs/MPC837XERDB_SLAVE_defconfig | 7 + configs/MPC837XERDB_defconfig | 10 + configs/TQM834x_defconfig | 9 + configs/caddy2_defconfig | 10 + configs/hrcon_defconfig | 6 + configs/hrcon_dh_defconfig | 6 + configs/ids8313_defconfig | 3 + configs/kmcoge5ne_defconfig | 9 + configs/kmeter1_defconfig | 9 + configs/kmopti2_defconfig | 4 + configs/kmsupx5_defconfig | 4 + configs/kmtegr1_defconfig | 5 + configs/kmtepr2_defconfig | 4 + configs/kmvect1_defconfig | 5 + configs/mpc8308_p1m_defconfig | 5 + configs/sbc8349_PCI_33_defconfig | 10 + configs/sbc8349_PCI_66_defconfig | 10 + configs/sbc8349_defconfig | 10 + configs/strider_con_defconfig | 5 + configs/strider_con_dp_defconfig | 5 + configs/strider_cpu_defconfig | 5 + configs/strider_cpu_dp_defconfig | 5 + configs/suvd3_defconfig | 4 + configs/tuge1_defconfig | 4 + configs/tuxx1_defconfig | 4 + configs/ve8313_defconfig | 7 + configs/vme8349_defconfig | 10 + include/configs/MPC8308RDB.h | 32 - include/configs/MPC8313ERDB_NAND.h | 38 -- include/configs/MPC8313ERDB_NOR.h | 40 -- include/configs/MPC8315ERDB.h | 34 - include/configs/MPC8323ERDB.h | 24 - include/configs/MPC832XEMDS.h | 37 -- include/configs/MPC8349EMDS.h | 86 --- include/configs/MPC8349EMDS_SDRAM.h | 86 --- include/configs/MPC8349ITX.h | 39 -- include/configs/MPC837XEMDS.h | 42 -- include/configs/MPC837XERDB.h | 40 -- include/configs/TQM834x.h | 35 - include/configs/caddy2.h | 41 -- include/configs/hrcon.h | 32 - include/configs/ids8313.h | 21 - include/configs/kmcoge5ne.h | 19 - include/configs/kmeter1.h | 19 - include/configs/kmopti2.h | 22 - include/configs/kmsupx5.h | 22 - include/configs/kmtegr1.h | 22 - include/configs/kmtepr2.h | 22 - include/configs/kmvect1.h | 22 - include/configs/mpc8308_p1m.h | 32 - include/configs/sbc8349.h | 71 --- include/configs/strider.h | 32 - include/configs/suvd3.h | 22 - include/configs/tuge1.h | 22 - include/configs/tuxx1.h | 22 - include/configs/ve8313.h | 19 - include/configs/vme8349.h | 43 -- 87 files changed, 1330 insertions(+), 1039 deletions(-) create mode 100644 arch/powerpc/cpu/mpc83xx/hrcw/Kconfig create mode 100644 arch/powerpc/cpu/mpc83xx/hrcw/hrcw.h create mode 100644 configs/MPC8349EMDS_PCI64_defconfig create mode 100644 configs/MPC837XEMDS_SLAVE_defconfig diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index bd4e5c14a9..1206c687cc 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -177,30 +177,79 @@ config TARGET_STRIDER endchoice +config MPC83XX_QUICC_ENGINE + bool + +# TODO: Imply MPC83xx PCI driver +config MPC83XX_PCI_SUPPORT + bool + +# TODO: Imply TSEC driver +config MPC83XX_TSEC1_SUPPORT + bool + +config MPC83XX_TSEC2_SUPPORT + bool + +config MPC83XX_PCIE1_SUPPORT + bool + +config MPC83XX_PCIE2_SUPPORT + bool + +config MPC83XX_SDHC_SUPPORT + bool + +config MPC83XX_SATA_SUPPORT + bool + +config MPC83XX_SECOND_I2C_SUPPORT + bool + +config MPC83XX_LDP_PIN + bool + config ARCH_MPC830X bool + select MPC83XX_SDHC_SUPPORT config ARCH_MPC8308 bool select ARCH_MPC830X + select MPC83XX_TSEC1_SUPPORT + select MPC83XX_TSEC2_SUPPORT + select MPC83XX_PCIE1_SUPPORT + select MPC83XX_SECOND_I2C_SUPPORT config ARCH_MPC8309 bool select ARCH_MPC830X + select MPC83XX_QUICC_ENGINE + select MPC83XX_PCI_SUPPORT + select MPC83XX_SECOND_I2C_SUPPORT config ARCH_MPC831X bool + select MPC83XX_PCI_SUPPORT + select MPC83XX_TSEC1_SUPPORT + select MPC83XX_TSEC2_SUPPORT config ARCH_MPC8313 bool select ARCH_MPC831X + select MPC83XX_SECOND_I2C_SUPPORT config ARCH_MPC8315 bool select ARCH_MPC831X + select MPC83XX_PCIE1_SUPPORT + select MPC83XX_PCIE2_SUPPORT + select MPC83XX_SATA_SUPPORT config ARCH_MPC832X bool + select MPC83XX_QUICC_ENGINE + select MPC83XX_PCI_SUPPORT config ARCH_MPC834X bool @@ -208,12 +257,32 @@ config ARCH_MPC834X config ARCH_MPC8349 bool select ARCH_MPC834X + select MPC83XX_PCI_SUPPORT + select MPC83XX_TSEC1_SUPPORT + select MPC83XX_TSEC2_SUPPORT + select MPC83XX_LDP_PIN + select MPC83XX_SECOND_I2C_SUPPORT config ARCH_MPC8360 bool + select MPC83XX_QUICC_ENGINE + select MPC83XX_PCI_SUPPORT + select MPC83XX_LDP_PIN + select MPC83XX_SECOND_I2C_SUPPORT config ARCH_MPC837X bool + select MPC83XX_PCI_SUPPORT + select MPC83XX_TSEC1_SUPPORT + select MPC83XX_TSEC2_SUPPORT + select MPC83XX_PCIE1_SUPPORT + select MPC83XX_PCIE2_SUPPORT + select MPC83XX_SDHC_SUPPORT + select MPC83XX_SATA_SUPPORT + select MPC83XX_LDP_PIN + select MPC83XX_SECOND_I2C_SUPPORT + +source "arch/powerpc/cpu/mpc83xx/hrcw/Kconfig" menu "Legacy options" diff --git a/arch/powerpc/cpu/mpc83xx/hrcw/Kconfig b/arch/powerpc/cpu/mpc83xx/hrcw/Kconfig new file mode 100644 index 0000000000..c657a47b11 --- /dev/null +++ b/arch/powerpc/cpu/mpc83xx/hrcw/Kconfig @@ -0,0 +1,816 @@ +menu "Reset Configuration Word" + +choice + prompt "Local bus memory controller clock mode" + +config LBMC_CLOCK_MODE_1_1 + bool "1 : 1" + +config LBMC_CLOCK_MODE_1_2 + depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC837X + bool "1 : 2" + +endchoice + +choice + prompt "DDR SDRAM memory controller clock mode" + +config DDR_MC_CLOCK_MODE_1_2 + bool "1 : 2" + +config DDR_MC_CLOCK_MODE_1_1 + depends on ARCH_MPC8315 || ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC837X + bool "1 : 1" + +endchoice + +if !ARCH_MPC8313 && !ARCH_MPC832X && !ARCH_MPC8349 + +choice + prompt "System PLL VCO division" + +config SYSTEM_PLL_VCO_DIV_1 + depends on !ARCH_MPC837X + bool "1" + +config SYSTEM_PLL_VCO_DIV_2 + bool "2" + +config SYSTEM_PLL_VCO_DIV_4 + depends on !ARCH_MPC831X + bool "4" + +config SYSTEM_PLL_VCO_DIV_8 + depends on !ARCH_MPC831X + bool "8" + +endchoice + +endif + +choice + prompt "System PLL multiplication factor" + +config SYSTEM_PLL_FACTOR_2_1 + bool "2 : 1" + +config SYSTEM_PLL_FACTOR_3_1 + bool "3 : 1" + +config SYSTEM_PLL_FACTOR_4_1 + bool "4 : 1" + +config SYSTEM_PLL_FACTOR_5_1 + bool "5 : 1" + +config SYSTEM_PLL_FACTOR_6_1 + bool "6 : 1" + +config SYSTEM_PLL_FACTOR_7_1 + depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X + bool "7 : 1" + +config SYSTEM_PLL_FACTOR_8_1 + depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X + bool "8 : 1" + +config SYSTEM_PLL_FACTOR_9_1 + depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X + bool "9 : 1" + +config SYSTEM_PLL_FACTOR_10_1 + depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X + bool "10 : 1" + +config SYSTEM_PLL_FACTOR_11_1 + depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X + bool "11 : 1" + +config SYSTEM_PLL_FACTOR_12_1 + depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X + bool "12 : 1" + +config SYSTEM_PLL_FACTOR_13_1 + depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X + bool "13 : 1" + +config SYSTEM_PLL_FACTOR_14_1 + depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X + bool "14 : 1" + +config SYSTEM_PLL_FACTOR_15_1 + depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X + bool "15 : 1" + +config SYSTEM_PLL_FACTOR_16_1 + depends on ARCH_MPC8349 || ARCH_MPV8360 + bool "16 : 1" + +endchoice + +config CORE_PLL_BYPASS + bool "Core PLL bypassed" + +if !CORE_PLL_BYPASS + +choice + prompt "Core PLL Ratio" + +config CORE_PLL_RATIO_1_1 + bool "1 : 1" + +config CORE_PLL_RATIO_15_1 + bool "1.5 : 1" + +config CORE_PLL_RATIO_2_1 + bool "2 : 1" + +config CORE_PLL_RATIO_25_1 + bool "2.5 : 1" + +config CORE_PLL_RATIO_3_1 + bool "3 : 1" + +endchoice + +choice + prompt "Core PLL VCO Divider" + +config CORE_PLL_VCO_DIVIDER_2 + bool "2" + +config CORE_PLL_VCO_DIVIDER_4 + bool "4" + +config CORE_PLL_VCO_DIVIDER_8 + depends on !ARCH_MPC8315 + bool "8" + +endchoice + +endif + +if MPC83XX_QUICC_ENGINE + +choice + prompt "QUICC Engine PLL VCO Divider" + +config QUICC_VCO_DIVIDER_2 + bool "2" + +config QUICC_VCO_DIVIDER_4 + bool "4" + +config QUICC_VCO_DIVIDER_8 + depends on ARCH_MPC8309 + bool "8" + +endchoice + +choice + prompt "QUICC Engine PLL division factor" + +config QUICC_DIV_FACTOR_1 + bool "1" + +config QUICC_DIV_FACTOR_2 + bool "2" + +endchoice + +choice + prompt "QUICC Engine PLL multiplication factor" + +config QUICC_MULT_FACTOR_2 + bool "2" + +config QUICC_MULT_FACTOR_3 + bool "3" + +config QUICC_MULT_FACTOR_4 + bool "4" + +config QUICC_MULT_FACTOR_5 + bool "5" + +config QUICC_MULT_FACTOR_6 + bool "6" + +config QUICC_MULT_FACTOR_7 + bool "7" + +config QUICC_MULT_FACTOR_8 + bool "8" + +config QUICC_MULT_FACTOR_9 + depends on ARCH_MPC8360 + bool "9" + +config QUICC_MULT_FACTOR_10 + depends on ARCH_MPC8360 + bool "10" + +config QUICC_MULT_FACTOR_11 + depends on ARCH_MPC8360 + bool "11" + +config QUICC_MULT_FACTOR_12 + depends on ARCH_MPC8360 + bool "12" + +config QUICC_MULT_FACTOR_13 + depends on ARCH_MPC8360 + bool "13" + +config QUICC_MULT_FACTOR_14 + depends on ARCH_MPC8360 + bool "14" + +config QUICC_MULT_FACTOR_15 + depends on ARCH_MPC8360 + bool "15" + +config QUICC_MULT_FACTOR_16 + depends on ARCH_MPC8360 + bool "16" + +config QUICC_MULT_FACTOR_17 + depends on ARCH_MPC8360 + bool "17" + +config QUICC_MULT_FACTOR_18 + depends on ARCH_MPC8360 + bool "18" + +config QUICC_MULT_FACTOR_19 + depends on ARCH_MPC8360 + bool "19" + +config QUICC_MULT_FACTOR_20 + depends on ARCH_MPC8360 + bool "20" + +config QUICC_MULT_FACTOR_21 + depends on ARCH_MPC8360 + bool "21" + +config QUICC_MULT_FACTOR_22 + depends on ARCH_MPC8360 + bool "22" + +config QUICC_MULT_FACTOR_23 + depends on ARCH_MPC8360 + bool "23" + +config QUICC_MULT_FACTOR_24 + depends on ARCH_MPC8360 + bool "24" + +config QUICC_MULT_FACTOR_25 + depends on ARCH_MPC8360 + bool "25" + +config QUICC_MULT_FACTOR_26 + depends on ARCH_MPC8360 + bool "26" + +config QUICC_MULT_FACTOR_27 + depends on ARCH_MPC8360 + bool "27" + +config QUICC_MULT_FACTOR_28 + depends on ARCH_MPC8360 + bool "28" + +config QUICC_MULT_FACTOR_29 + depends on ARCH_MPC8360 + bool "29" + +config QUICC_MULT_FACTOR_30 + depends on ARCH_MPC8360 + bool "30" + +config QUICC_MULT_FACTOR_31 + depends on ARCH_MPC8360 + bool "31" + +endchoice + +endif + +if MPC83XX_PCI_SUPPORT + +choice + prompt "PCI host mode" + +config PCI_HOST_MODE_DISABLE + bool "Disabled" + +config PCI_HOST_MODE_ENABLE + bool "Enabled" + +endchoice + +if ARCH_MPC8349 + +choice + prompt "PCI 64-bit mode" + +config PCI_64BIT_MODE_DISABLE + bool "Disabled" + +config PCI_64BIT_MODE_ENABLE + bool "Enabled" + +endchoice + +endif + +choice + prompt "PCI internal arbiter 1 mode" + +config PCI_INT_ARBITER1_DISABLE + bool "Disabled" + +config PCI_INT_ARBITER1_ENABLE + bool "Enabled" + +endchoice + +if ARCH_MPC8349 + +choice + prompt "PCI internal arbiter 2 mode" + +config PCI_INT_ARBITER2_DISABLE + bool "Disabled" + +config PCI_INT_ARBITER2_ENABLE + bool "Enabled" + +endchoice + +endif + +if ARCH_MPC8360 + +choice + prompt "PCI clock output drive" + +config PCI_CLOCK_OUTPUT_DRIVE_DISABLE + bool "Disabled" + +config PCI_CLOCK_OUTPUT_DRIVE_ENABLE + bool "Enabled" + +endchoice + +endif + +endif + +choice + prompt "Core disable mode" + +config CORE_DISABLE_MODE_OFF + bool "Off" + +config CORE_DISABLE_MODE_ON + bool "On" + +endchoice + +choice + prompt "Boot Memory Space" + +config BOOT_MEMORY_SPACE_HIGH + bool "High" + +config BOOT_MEMORY_SPACE_LOW + bool "Low" + +endchoice + +choice + prompt "Boot Sequencer Configuration" + +config BOOT_SEQUENCER_DISABLED + bool "Disabled" + +config BOOT_SEQUENCER_NORMAL_I2C + bool "Normal I2C" + +config BOOT_SEQUENCER_EXTENDED_I2C + bool "Extended I2C" + +endchoice + +choice + prompt "Software Watchdog" + +config SOFTWARE_WATCHDOG_DISABLED + bool "Disabled" + +config SOFTWARE_WATCHDOG_ENABLED + bool "Enabled" + +endchoice + +choice + prompt "Boot ROM interface location" + +config BOOT_ROM_INTERFACE_DDR_SDRAM + bool "DDR_SDRAM" + +config BOOT_ROM_INTERFACE_PCI1 + depends on MPC83XX_PCI_SUPPORT + bool "PCI1" + +config BOOT_ROM_INTERFACE_PCI2 + depends on MPC83XX_PCI_SUPPORT && ARCH_MPC8349 + bool "PCI2" + +config BOOT_ROM_INTERFACE_ON_CHIP_BOOT_ROM + depends on ARCH_MPC837X + bool "PCI2" + +config BOOT_ROM_INTERFACE_ESDHC + depends on ARCH_MPC8309 + bool "eSDHC" + +config BOOT_ROM_INTERFACE_SPI + depends on ARCH_MPC8309 + bool "SPI" + +config BOOT_ROM_INTERFACE_GPCM_8BIT + bool "Local bus GPCM - 8-bit ROM" + +config BOOT_ROM_INTERFACE_GPCM_16BIT + bool "Local bus GPCM - 16-bit ROM" + +config BOOT_ROM_INTERFACE_GPCM_32BIT + depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC837X + bool "Local bus GPCM - 32-bit ROM" + +config BOOT_ROM_INTERFACE_NAND_FLASH_8BIT_SMALL + depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360 + bool "Local bus NAND Flash- 8-bit small page ROM" + +config BOOT_ROM_INTERFACE_NAND_FLASH_8BIT_LARGE + depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360 + bool "Local bus NAND Flash- 8-bit large page ROM" + +endchoice + +if MPC83XX_TSEC1_SUPPORT + +choice + prompt "TSEC1 mode" + +config TSEC1_MODE_MII + depends on !ARCH_MPC8349 + bool "MII" + +config TSEC1_MODE_RMII + depends on ARCH_MPC831X && !ARCH_MPC8349 + bool "RMII" + +config TSEC1_MODE_RGMII + bool "RGMII" + +config TSEC1_MODE_RTBI + depends on ARCH_MPC831X || ARCH_MPC837X + bool "RTBI" + +config TSEC1_MODE_GMII + depends on ARCH_MPC8349 + bool "GMII" + +config TSEC1_MODE_TBI + depends on ARCH_MPC8349 + bool "TBI" + +config TSEC1_MODE_SGMII + depends on ARCH_MPC831X || ARCH_MPC837X + bool "SGMII" + +endchoice + +endif + +if MPC83XX_TSEC2_SUPPORT + +choice + prompt "TSEC2 mode" + +config TSEC2_MODE_MII + depends on !ARCH_MPC8349 + bool "MII" + +config TSEC2_MODE_RMII + depends on ARCH_MPC831X && !ARCH_MPC8349 + bool "RMII" + +config TSEC2_MODE_RGMII + bool "RGMII" + +config TSEC2_MODE_RTBI + depends on ARCH_MPC831X || ARCH_MPC837X + bool "RTBI" + +config TSEC2_MODE_GMII + depends on ARCH_MPC8349 + bool "GMII" + +config TSEC2_MODE_TBI + depends on ARCH_MPC8349 + bool "TBI" + +config TSEC2_MODE_SGMII + depends on ARCH_MPC831X || ARCH_MPC837X + bool "SGMII" + +endchoice + +endif + +choice + prompt "True litle-endian mode" + +config TRUE_LITTLE_ENDIAN_BIG_ENDIAN + bool "Big-endian" + +config TRUE_LITTLE_ENDIAN_LITTLE_ENDIAN + bool "Little-endian" + +endchoice + +if ARCH_MPC8360 + +choice + prompt "Secondary DDR IO" + +config SECONDARY_DDR_IO_DISABLE + bool "Disable" + +config SECONDARY_DDR_IO_ENABLE + bool "Enable" + +endchoice + +endif + +if ARCH_MPC831X || ARCH_MPC832X || ARCH_MPC8349 || ARCH_MPC8360 + +choice + prompt "LALE timing" + +config LALE_TIMING_NORMAL + bool "Normal" + +config LALE_TIMING_EARLIER + bool "Earlier" + +endchoice + +endif + +if MPC83XX_LDP_PIN + +choice + prompt "LDP pin mux state" + +config LDP_PIN_MUX_STATE_1 + bool "Inital value 1" + +config LDP_PIN_MUX_STATE_0 + bool "Inital value 0" + +endchoice + +endif + +endmenu + +config LBMC_CLOCK_MODE + int + default 0 if LBMC_CLOCK_MODE_1_1 + default 1 if LBMC_CLOCK_MODE_1_2 + +config DDR_MC_CLOCK_MODE + int + default 1 if DDR_MC_CLOCK_MODE_1_2 + default 0 if DDR_MC_CLOCK_MODE_1_1 + +config SYSTEM_PLL_VCO_DIV + int + default 0 if ARCH_MPC8349 || ARCH_MPC832X + default 2 if ARCH_MPC8313 + default 0 if SYSTEM_PLL_VCO_DIV_2 && !ARCH_MPC8360 && !ARCH_MPC837X + default 1 if SYSTEM_PLL_VCO_DIV_4 && !ARCH_MPC8360 && !ARCH_MPC837X + default 2 if SYSTEM_PLL_VCO_DIV_8 && !ARCH_MPC8360 && !ARCH_MPC837X + default 0 if SYSTEM_PLL_VCO_DIV_4 && (ARCH_MPC8360 || ARCH_MPC837X) + default 1 if SYSTEM_PLL_VCO_DIV_8 && (ARCH_MPC8360 || ARCH_MPC837X) + default 2 if SYSTEM_PLL_VCO_DIV_2 && (ARCH_MPC8360 || ARCH_MPC837X) + default 3 if SYSTEM_PLL_VCO_DIV_1 + +config SYSTEM_PLL_FACTOR + int + default 2 if SYSTEM_PLL_FACTOR_2_1 + default 3 if SYSTEM_PLL_FACTOR_3_1 + default 4 if SYSTEM_PLL_FACTOR_4_1 + default 5 if SYSTEM_PLL_FACTOR_5_1 + default 6 if SYSTEM_PLL_FACTOR_6_1 + default 7 if SYSTEM_PLL_FACTOR_7_1 + default 8 if SYSTEM_PLL_FACTOR_8_1 + default 9 if SYSTEM_PLL_FACTOR_9_1 + default 10 if SYSTEM_PLL_FACTOR_10_1 + default 11 if SYSTEM_PLL_FACTOR_11_1 + default 12 if SYSTEM_PLL_FACTOR_12_1 + default 13 if SYSTEM_PLL_FACTOR_13_1 + default 14 if SYSTEM_PLL_FACTOR_14_1 + default 15 if SYSTEM_PLL_FACTOR_15_1 + default 0 if SYSTEM_PLL_FACTOR_16_1 + +config CORE_PLL_RATIO + hex + default 0x0 if CORE_PLL_BYPASS + default 0x02 if CORE_PLL_RATIO_1_1 && CORE_PLL_VCO_DIVIDER_2 + default 0x22 if CORE_PLL_RATIO_1_1 && CORE_PLL_VCO_DIVIDER_4 + default 0x42 if CORE_PLL_RATIO_1_1 && CORE_PLL_VCO_DIVIDER_8 + default 0x03 if CORE_PLL_RATIO_15_1 && CORE_PLL_VCO_DIVIDER_2 + default 0x23 if CORE_PLL_RATIO_15_1 && CORE_PLL_VCO_DIVIDER_4 + default 0x43 if CORE_PLL_RATIO_15_1 && CORE_PLL_VCO_DIVIDER_8 + default 0x04 if CORE_PLL_RATIO_2_1 && CORE_PLL_VCO_DIVIDER_2 + default 0x24 if CORE_PLL_RATIO_2_1 && CORE_PLL_VCO_DIVIDER_4 + default 0x44 if CORE_PLL_RATIO_2_1 && CORE_PLL_VCO_DIVIDER_8 + default 0x05 if CORE_PLL_RATIO_25_1 && CORE_PLL_VCO_DIVIDER_2 + default 0x25 if CORE_PLL_RATIO_25_1 && CORE_PLL_VCO_DIVIDER_4 + default 0x45 if CORE_PLL_RATIO_25_1 && CORE_PLL_VCO_DIVIDER_8 + default 0x06 if CORE_PLL_RATIO_3_1 && CORE_PLL_VCO_DIVIDER_2 + default 0x26 if CORE_PLL_RATIO_3_1 && CORE_PLL_VCO_DIVIDER_4 + default 0x46 if CORE_PLL_RATIO_3_1 && CORE_PLL_VCO_DIVIDER_8 + +config CORE_DISABLE_MODE + int + default 0 if CORE_DISABLE_MODE_OFF + default 1 if CORE_DISABLE_MODE_ON + +config BOOT_MEMORY_SPACE + int + default 0 if BOOT_MEMORY_SPACE_LOW + default 1 if BOOT_MEMORY_SPACE_HIGH + +config BOOT_SEQUENCER + int + default 0 if BOOT_SEQUENCER_DISABLED + default 1 if BOOT_SEQUENCER_NORMAL_I2C + default 2 if BOOT_SEQUENCER_EXTENDED_I2C + +config SOFTWARE_WATCHDOG + int + default 0 if SOFTWARE_WATCHDOG_DISABLED + default 1 if SOFTWARE_WATCHDOG_ENABLED + +config BOOT_ROM_INTERFACE + hex + default 0x0 if BOOT_ROM_INTERFACE_DDR_SDRAM + default 0x4 if BOOT_ROM_INTERFACE_PCI1 + default 0x8 if BOOT_ROM_INTERFACE_PCI2 + default 0x8 if BOOT_ROM_INTERFACE_ESDHC + default 0xc if BOOT_ROM_INTERFACE_SPI + default 0xc if BOOT_ROM_INTERFACE_ON_CHIP_BOOT_ROM + default 0x14 if BOOT_ROM_INTERFACE_GPCM_8BIT + default 0x18 if BOOT_ROM_INTERFACE_GPCM_16BIT + default 0x1c if BOOT_ROM_INTERFACE_GPCM_32BIT + default 0x5 if BOOT_ROM_INTERFACE_NAND_FLASH_8BIT_SMALL + default 0x15 if BOOT_ROM_INTERFACE_NAND_FLASH_8BIT_LARGE + +config TSEC1_MODE + hex + default 0x0 if !MPC83XX_TSEC1_SUPPORT + default 0x0 if TSEC1_MODE_MII + default 0x1 if TSEC1_MODE_RMII + default 0x3 if TSEC1_MODE_RGMII && !ARCH_MPC8349 + default 0x5 if TSEC1_MODE_RTBI && !ARCH_MPC8349 + default 0x6 if TSEC1_MODE_SGMII + default 0x0 if TSEC1_MODE_RGMII && ARCH_MPC8349 + default 0x1 if TSEC1_MODE_RTBI && ARCH_MPC8349 + default 0x2 if TSEC1_MODE_GMII + default 0x3 if TSEC1_MODE_TBI + +config TSEC2_MODE + hex + default 0x0 if !MPC83XX_TSEC2_SUPPORT + default 0x0 if TSEC2_MODE_MII + default 0x1 if TSEC2_MODE_RMII + default 0x3 if TSEC2_MODE_RGMII && !ARCH_MPC8349 + default 0x5 if TSEC2_MODE_RTBI && !ARCH_MPC8349 + default 0x6 if TSEC2_MODE_SGMII + default 0x0 if TSEC2_MODE_RGMII && ARCH_MPC8349 + default 0x1 if TSEC2_MODE_RTBI && ARCH_MPC8349 + default 0x2 if TSEC2_MODE_GMII + default 0x3 if TSEC2_MODE_TBI + +config SECONDARY_DDR_IO + int + default 0 if !ARCH_MPC8360 + default 0 if SECONDARY_DDR_IO_DISABLE + default 1 if SECONDARY_DDR_IO_ENABLE + +config TRUE_LITTLE_ENDIAN + int + default 0 if TRUE_LITTLE_ENDIAN_BIG_ENDIAN + default 1 if TRUE_LITTLE_ENDIAN_LITTLE_ENDIAN + +config LALE_TIMING + int + default 0 if ARCH_MPC830X || ARCH_MPC837X + default 0 if LALE_TIMING_NORMAL + default 1 if LALE_TIMING_EARLIER + +config LDP_PIN_MUX_STATE + int + default 0 if !MPC83XX_LDP_PIN + default 0 if LDP_PIN_MUX_STATE_1 + default 1 if LDP_PIN_MUX_STATE_0 + +config QUICC_VCO_DIVIDER + int + default 0 if !MPC83XX_QUICC_ENGINE + default 0 if QUICC_VCO_DIVIDER_2 && ARCH_MPC8309 + default 1 if QUICC_VCO_DIVIDER_4 && ARCH_MPC8309 + default 2 if QUICC_VCO_DIVIDER_8 && ARCH_MPC8309 + default 2 if QUICC_VCO_DIVIDER_2 && (ARCH_MPC832X || ARCH_MPC8360) + default 0 if QUICC_VCO_DIVIDER_4 && (ARCH_MPC832X || ARCH_MPC8360) + default 1 if QUICC_VCO_DIVIDER_8 && ARCH_MPC8360 + +config QUICC_DIV_FACTOR + int + default 0 if !MPC83XX_QUICC_ENGINE + default 0 if QUICC_DIV_FACTOR_1 + default 1 if QUICC_DIV_FACTOR_2 + +config QUICC_MULT_FACTOR + int + default 0 if !MPC83XX_QUICC_ENGINE + default 2 if QUICC_MULT_FACTOR_2 + default 3 if QUICC_MULT_FACTOR_3 + default 4 if QUICC_MULT_FACTOR_4 + default 5 if QUICC_MULT_FACTOR_5 + default 6 if QUICC_MULT_FACTOR_6 + default 7 if QUICC_MULT_FACTOR_7 + default 8 if QUICC_MULT_FACTOR_8 + default 9 if QUICC_MULT_FACTOR_9 + default 10 if QUICC_MULT_FACTOR_10 + default 11 if QUICC_MULT_FACTOR_11 + default 12 if QUICC_MULT_FACTOR_12 + default 13 if QUICC_MULT_FACTOR_13 + default 14 if QUICC_MULT_FACTOR_14 + default 15 if QUICC_MULT_FACTOR_15 + default 16 if QUICC_MULT_FACTOR_16 + default 17 if QUICC_MULT_FACTOR_17 + default 18 if QUICC_MULT_FACTOR_18 + default 19 if QUICC_MULT_FACTOR_19 + default 20 if QUICC_MULT_FACTOR_20 + default 21 if QUICC_MULT_FACTOR_21 + default 22 if QUICC_MULT_FACTOR_22 + default 23 if QUICC_MULT_FACTOR_23 + default 24 if QUICC_MULT_FACTOR_24 + default 25 if QUICC_MULT_FACTOR_25 + default 26 if QUICC_MULT_FACTOR_26 + default 27 if QUICC_MULT_FACTOR_27 + default 28 if QUICC_MULT_FACTOR_28 + default 29 if QUICC_MULT_FACTOR_29 + default 30 if QUICC_MULT_FACTOR_30 + default 31 if QUICC_MULT_FACTOR_31 + +config PCI_HOST_MODE + int + default 0 if !MPC83XX_PCI_SUPPORT && !ARCH_MPC8308 + default 0 if PCI_HOST_MODE_DISABLE + default 1 if PCI_HOST_MODE_ENABLE || ARCH_MPC8308 # MPC8308 needs this bit set regardless + +config PCI_64BIT_MODE + int + default 0 if !ARCH_MPC8349 + default 0 if PCI_64BIT_MODE_DISABLE + default 1 if PCI_64BIT_MODE_ENABLE + +config PCI_INT_ARBITER1 + int + default 0 if !MPC83XX_PCI_SUPPORT && !ARCH_MPC8308 + default 0 if PCI_INT_ARBITER1_DISABLE + default 1 if PCI_INT_ARBITER1_ENABLE || ARCH_MPC8308 # MPC8308 needs this bit set regardless + +config PCI_INT_ARBITER2 + int + default 0 if !ARCH_MPC8349 + default 0 if PCI_INT_ARBITER2_DISABLE + default 1 if PCI_INT_ARBITER2_ENABLE + +config PCI_CLOCK_OUTPUT_DRIVE + int + default 0 if !ARCH_MPC8360 + default 0 if PCI_CLOCK_OUTPUT_DRIVE_DISABLE + default 1 if PCI_CLOCK_OUTPUT_DRIVE_ENABLE diff --git a/arch/powerpc/cpu/mpc83xx/hrcw/hrcw.h b/arch/powerpc/cpu/mpc83xx/hrcw/hrcw.h new file mode 100644 index 0000000000..7d66ba726b --- /dev/null +++ b/arch/powerpc/cpu/mpc83xx/hrcw/hrcw.h @@ -0,0 +1,37 @@ +#ifdef CONFIG_ARCH_MPC8349 +#define TSEC1_MODE_SHIFT 17 +#define TSEC2_MODE_SHIFT 19 +#else +#define TSEC1_MODE_SHIFT 18 +#define TSEC2_MODE_SHIFT 21 +#endif + +#define CONFIG_SYS_HRCW_LOW (\ + (CONFIG_LBMC_CLOCK_MODE << (31 - 0)) |\ + (CONFIG_DDR_MC_CLOCK_MODE << (31 - 1)) |\ + (CONFIG_SYSTEM_PLL_VCO_DIV << (31 - 3)) |\ + (CONFIG_SYSTEM_PLL_FACTOR << (31 - 7)) |\ + (CONFIG_CORE_PLL_RATIO << (31 - 15)) |\ + (CONFIG_QUICC_VCO_DIVIDER << (31 - 25)) |\ + (CONFIG_QUICC_DIV_FACTOR << (31 - 26)) |\ + (CONFIG_QUICC_MULT_FACTOR << (31 - 31)) \ + ) + +#define CONFIG_SYS_HRCW_HIGH (\ + (CONFIG_PCI_HOST_MODE << (31 - 0)) |\ + (CONFIG_PCI_64BIT_MODE << (31 - 1)) |\ + (CONFIG_PCI_INT_ARBITER1 << (31 - 2)) |\ + (CONFIG_PCI_INT_ARBITER2 << (31 - 3)) |\ + (CONFIG_PCI_CLOCK_OUTPUT_DRIVE << (31 - 3)) |\ + (CONFIG_CORE_DISABLE_MODE << (31 - 4)) |\ + (CONFIG_BOOT_MEMORY_SPACE << (31 - 5)) |\ + (CONFIG_BOOT_SEQUENCER << (31 - 7)) |\ + (CONFIG_SOFTWARE_WATCHDOG << (31 - 8)) |\ + (CONFIG_BOOT_ROM_INTERFACE << (31 - 13)) |\ + (CONFIG_TSEC1_MODE << (31 - TSEC1_MODE_SHIFT)) |\ + (CONFIG_TSEC2_MODE << (31 - TSEC2_MODE_SHIFT)) |\ + (CONFIG_SECONDARY_DDR_IO << (31 - 27)) |\ + (CONFIG_TRUE_LITTLE_ENDIAN << (31 - 28)) |\ + (CONFIG_LALE_TIMING << (31 - 29)) |\ + (CONFIG_LDP_PIN_MUX_STATE << (31 - 30)) \ + ) diff --git a/arch/powerpc/cpu/mpc83xx/start.S b/arch/powerpc/cpu/mpc83xx/start.S index c00bb31363..77170a7424 100644 --- a/arch/powerpc/cpu/mpc83xx/start.S +++ b/arch/powerpc/cpu/mpc83xx/start.S @@ -24,6 +24,8 @@ #include #include +#include "hrcw/hrcw.h" + /* We don't want the MMU yet. */ #undef MSR_KERNEL diff --git a/board/freescale/mpc8315erdb/MAINTAINERS b/board/freescale/mpc8315erdb/MAINTAINERS index 5a67b40993..cdac1ac2ee 100644 --- a/board/freescale/mpc8315erdb/MAINTAINERS +++ b/board/freescale/mpc8315erdb/MAINTAINERS @@ -4,3 +4,4 @@ S: Orphan (since 2018-05) F: board/freescale/mpc8315erdb/ F: include/configs/MPC8315ERDB.h F: configs/MPC8315ERDB_defconfig +F: configs/MPC8315ERDB_NANDSPL_defconfig diff --git a/board/freescale/mpc8349emds/MAINTAINERS b/board/freescale/mpc8349emds/MAINTAINERS index 0719225671..a8f26a9a31 100644 --- a/board/freescale/mpc8349emds/MAINTAINERS +++ b/board/freescale/mpc8349emds/MAINTAINERS @@ -5,4 +5,5 @@ F: board/freescale/mpc8349emds/ F: include/configs/MPC8349EMDS.h F: configs/MPC8349EMDS_defconfig F: configs/MPC8349EMDS_SDRAM_defconfig +F: configs/MPC8349EMDS_PCI64_defconfig F: configs/MPC8349EMDS_SLAVE_defconfig diff --git a/board/freescale/mpc8349itx/mpc8349itx.c b/board/freescale/mpc8349itx/mpc8349itx.c index d90553384f..c4bec090be 100644 --- a/board/freescale/mpc8349itx/mpc8349itx.c +++ b/board/freescale/mpc8349itx/mpc8349itx.c @@ -19,6 +19,8 @@ #include #endif +#include "../../../arch/powerpc/cpu/mpc83xx/hrcw/hrcw.h" + DECLARE_GLOBAL_DATA_PTR; #ifndef CONFIG_SPD_EEPROM diff --git a/board/freescale/mpc837xemds/MAINTAINERS b/board/freescale/mpc837xemds/MAINTAINERS index 8386aa7297..ce9c446f2d 100644 --- a/board/freescale/mpc837xemds/MAINTAINERS +++ b/board/freescale/mpc837xemds/MAINTAINERS @@ -4,4 +4,5 @@ S: Orphan (since 2018-05) F: board/freescale/mpc837xemds/ F: include/configs/MPC837XEMDS.h F: configs/MPC837XEMDS_defconfig +F: configs/MPC837XEMDS_SLAVE_defconfig F: configs/MPC837XEMDS_HOST_defconfig diff --git a/configs/MPC8308RDB_defconfig b/configs/MPC8308RDB_defconfig index 59dde136f2..042f6aa010 100644 --- a/configs/MPC8308RDB_defconfig +++ b/configs/MPC8308RDB_defconfig @@ -3,6 +3,13 @@ CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_CLK_FREQ=33333333 CONFIG_MPC83xx=y CONFIG_TARGET_MPC8308RDB=y +CONFIG_SYSTEM_PLL_VCO_DIV_2=y +CONFIG_SYSTEM_PLL_FACTOR_4_1=y +CONFIG_CORE_PLL_RATIO_3_1=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_TSEC1_MODE_RGMII=y +CONFIG_TSEC2_MODE_RGMII=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/MPC8313ERDB_33_defconfig b/configs/MPC8313ERDB_33_defconfig index 4851611cf5..c99d739996 100644 --- a/configs/MPC8313ERDB_33_defconfig +++ b/configs/MPC8313ERDB_33_defconfig @@ -3,6 +3,14 @@ CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_CLK_FREQ=33333333 CONFIG_MPC83xx=y CONFIG_TARGET_MPC8313ERDB_NOR=y +CONFIG_SYSTEM_PLL_FACTOR_5_1=y +CONFIG_CORE_PLL_RATIO_2_1=y +CONFIG_PCI_HOST_MODE_ENABLE=y +CONFIG_PCI_INT_ARBITER1_ENABLE=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_TSEC1_MODE_RGMII=y +CONFIG_TSEC2_MODE_RGMII=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SYS_33MHZ" diff --git a/configs/MPC8313ERDB_66_defconfig b/configs/MPC8313ERDB_66_defconfig index fb4fddec46..c1eb49af7b 100644 --- a/configs/MPC8313ERDB_66_defconfig +++ b/configs/MPC8313ERDB_66_defconfig @@ -3,6 +3,13 @@ CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_CLK_FREQ=66666667 CONFIG_MPC83xx=y CONFIG_TARGET_MPC8313ERDB_NOR=y +CONFIG_CORE_PLL_RATIO_2_1=y +CONFIG_PCI_HOST_MODE_ENABLE=y +CONFIG_PCI_INT_ARBITER1_ENABLE=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_TSEC1_MODE_RGMII=y +CONFIG_TSEC2_MODE_RGMII=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SYS_66MHZ" diff --git a/configs/MPC8313ERDB_NAND_33_defconfig b/configs/MPC8313ERDB_NAND_33_defconfig index 80ed52b2e1..adec951b72 100644 --- a/configs/MPC8313ERDB_NAND_33_defconfig +++ b/configs/MPC8313ERDB_NAND_33_defconfig @@ -5,6 +5,13 @@ CONFIG_SPL=y CONFIG_SYS_CLK_FREQ=33333333 CONFIG_MPC83xx=y CONFIG_TARGET_MPC8313ERDB_NAND=y +CONFIG_SYSTEM_PLL_FACTOR_5_1=y +CONFIG_CORE_PLL_RATIO_2_1=y +CONFIG_PCI_HOST_MODE_ENABLE=y +CONFIG_PCI_INT_ARBITER1_ENABLE=y +CONFIG_BOOT_ROM_INTERFACE_NAND_FLASH_8BIT_SMALL=y +CONFIG_TSEC1_MODE_RGMII=y +CONFIG_TSEC2_MODE_RGMII=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SYS_33MHZ" diff --git a/configs/MPC8313ERDB_NAND_66_defconfig b/configs/MPC8313ERDB_NAND_66_defconfig index d0d84d429d..6c75faacb0 100644 --- a/configs/MPC8313ERDB_NAND_66_defconfig +++ b/configs/MPC8313ERDB_NAND_66_defconfig @@ -5,6 +5,12 @@ CONFIG_SPL=y CONFIG_SYS_CLK_FREQ=66666667 CONFIG_MPC83xx=y CONFIG_TARGET_MPC8313ERDB_NAND=y +CONFIG_CORE_PLL_RATIO_2_1=y +CONFIG_PCI_HOST_MODE_ENABLE=y +CONFIG_PCI_INT_ARBITER1_ENABLE=y +CONFIG_BOOT_ROM_INTERFACE_NAND_FLASH_8BIT_SMALL=y +CONFIG_TSEC1_MODE_RGMII=y +CONFIG_TSEC2_MODE_RGMII=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SYS_66MHZ" diff --git a/configs/MPC8315ERDB_defconfig b/configs/MPC8315ERDB_defconfig index 15dbbe35dd..cb3f206038 100644 --- a/configs/MPC8315ERDB_defconfig +++ b/configs/MPC8315ERDB_defconfig @@ -3,6 +3,14 @@ CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_CLK_FREQ=66666667 CONFIG_MPC83xx=y CONFIG_TARGET_MPC8315ERDB=y +CONFIG_SYSTEM_PLL_VCO_DIV_2=y +CONFIG_CORE_PLL_RATIO_3_1=y +CONFIG_PCI_HOST_MODE_ENABLE=y +CONFIG_PCI_INT_ARBITER1_ENABLE=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_TSEC1_MODE_RGMII=y +CONFIG_TSEC2_MODE_RGMII=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC8323ERDB_defconfig b/configs/MPC8323ERDB_defconfig index c43ae8c992..cdc559a581 100644 --- a/configs/MPC8323ERDB_defconfig +++ b/configs/MPC8323ERDB_defconfig @@ -3,6 +3,12 @@ CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_CLK_FREQ=66666667 CONFIG_MPC83xx=y CONFIG_TARGET_MPC8323ERDB=y +CONFIG_CORE_PLL_RATIO_25_1=y +CONFIG_QUICC_MULT_FACTOR_3=y +CONFIG_PCI_HOST_MODE_ENABLE=y +CONFIG_PCI_INT_ARBITER1_ENABLE=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC832XEMDS_ATM_defconfig b/configs/MPC832XEMDS_ATM_defconfig index a40f16d49b..5f14da422d 100644 --- a/configs/MPC832XEMDS_ATM_defconfig +++ b/configs/MPC832XEMDS_ATM_defconfig @@ -3,6 +3,12 @@ CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_MPC832XEMDS=y +CONFIG_CORE_PLL_RATIO_2_1=y +CONFIG_QUICC_MULT_FACTOR_3=y +CONFIG_PCI_HOST_MODE_ENABLE=y +CONFIG_PCI_INT_ARBITER1_ENABLE=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PQ_MDS_PIB=1,PQ_MDS_PIB_ATM=1" diff --git a/configs/MPC832XEMDS_HOST_33_defconfig b/configs/MPC832XEMDS_HOST_33_defconfig index 1031dd655a..41245a3fc9 100644 --- a/configs/MPC832XEMDS_HOST_33_defconfig +++ b/configs/MPC832XEMDS_HOST_33_defconfig @@ -3,6 +3,12 @@ CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_MPC832XEMDS=y +CONFIG_CORE_PLL_RATIO_2_1=y +CONFIG_QUICC_MULT_FACTOR_3=y +CONFIG_PCI_HOST_MODE_ENABLE=y +CONFIG_PCI_INT_ARBITER1_ENABLE=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PCI_33M,PQ_MDS_PIB=1" diff --git a/configs/MPC832XEMDS_HOST_66_defconfig b/configs/MPC832XEMDS_HOST_66_defconfig index 416e0e9aea..ea90bea77d 100644 --- a/configs/MPC832XEMDS_HOST_66_defconfig +++ b/configs/MPC832XEMDS_HOST_66_defconfig @@ -3,6 +3,12 @@ CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_MPC832XEMDS=y +CONFIG_CORE_PLL_RATIO_2_1=y +CONFIG_QUICC_MULT_FACTOR_3=y +CONFIG_PCI_HOST_MODE_ENABLE=y +CONFIG_PCI_INT_ARBITER1_ENABLE=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PCI_66M,PQ_MDS_PIB=1" diff --git a/configs/MPC832XEMDS_SLAVE_defconfig b/configs/MPC832XEMDS_SLAVE_defconfig index 29b8f1a988..4944694048 100644 --- a/configs/MPC832XEMDS_SLAVE_defconfig +++ b/configs/MPC832XEMDS_SLAVE_defconfig @@ -3,6 +3,9 @@ CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_MPC832XEMDS=y +CONFIG_CORE_PLL_RATIO_2_1=y +CONFIG_QUICC_MULT_FACTOR_3=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PCISLAVE" diff --git a/configs/MPC832XEMDS_defconfig b/configs/MPC832XEMDS_defconfig index 2a15e5c18e..d04292a388 100644 --- a/configs/MPC832XEMDS_defconfig +++ b/configs/MPC832XEMDS_defconfig @@ -3,6 +3,12 @@ CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_MPC832XEMDS=y +CONFIG_CORE_PLL_RATIO_2_1=y +CONFIG_QUICC_MULT_FACTOR_3=y +CONFIG_PCI_HOST_MODE_ENABLE=y +CONFIG_PCI_INT_ARBITER1_ENABLE=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC8349EMDS_PCI64_defconfig b/configs/MPC8349EMDS_PCI64_defconfig new file mode 100644 index 0000000000..db0698237b --- /dev/null +++ b/configs/MPC8349EMDS_PCI64_defconfig @@ -0,0 +1,35 @@ +CONFIG_PPC=y +CONFIG_SYS_TEXT_BASE=0xFE000000 +CONFIG_SYS_CLK_FREQ=66000000 +CONFIG_MPC83xx=y +CONFIG_TARGET_MPC8349EMDS=y +CONFIG_DDR_MC_CLOCK_MODE_1_1=y +CONFIG_SYSTEM_PLL_FACTOR_4_1=y +CONFIG_CORE_PLL_RATIO_2_1=y +CONFIG_PCI_HOST_MODE_ENABLE=y +CONFIG_PCI_64BIT_MODE_ENABLE=y +CONFIG_PCI_INT_ARBITER1_ENABLE=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_TSEC1_MODE_GMII=y +CONFIG_TSEC2_MODE_GMII=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_BOOTDELAY=6 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_IMLS=y +CONFIG_CMD_I2C=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_DATE=y +# CONFIG_MMC is not set +CONFIG_MTD_NOR_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_FLASH_CFI_DRIVER=y +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y +CONFIG_SYS_FLASH_CFI=y +CONFIG_TSEC_ENET=y +# CONFIG_PCI is not set +CONFIG_SYS_NS16550=y +CONFIG_OF_LIBFDT=y diff --git a/configs/MPC8349EMDS_SDRAM_defconfig b/configs/MPC8349EMDS_SDRAM_defconfig index d4f6587bb3..8465cc6800 100644 --- a/configs/MPC8349EMDS_SDRAM_defconfig +++ b/configs/MPC8349EMDS_SDRAM_defconfig @@ -3,6 +3,16 @@ CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_MPC8349EMDS_SDRAM=y +CONFIG_DDR_MC_CLOCK_MODE_1_1=y +CONFIG_SYSTEM_PLL_FACTOR_4_1=y +CONFIG_CORE_PLL_RATIO_2_1=y +CONFIG_PCI_HOST_MODE_ENABLE=y +CONFIG_PCI_INT_ARBITER1_ENABLE=y +CONFIG_PCI_INT_ARBITER2_ENABLE=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_TSEC1_MODE_GMII=y +CONFIG_TSEC2_MODE_GMII=y CONFIG_PCI_ONE_PCI1=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/configs/MPC8349EMDS_SLAVE_defconfig b/configs/MPC8349EMDS_SLAVE_defconfig index 11e3b144b7..b0cb93bf7f 100644 --- a/configs/MPC8349EMDS_SLAVE_defconfig +++ b/configs/MPC8349EMDS_SLAVE_defconfig @@ -3,6 +3,15 @@ CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_CLK_FREQ=66666666 CONFIG_MPC83xx=y CONFIG_TARGET_MPC8349EMDS=y +CONFIG_DDR_MC_CLOCK_MODE_1_1=y +CONFIG_SYSTEM_PLL_FACTOR_4_1=y +CONFIG_CORE_PLL_RATIO_2_1=y +CONFIG_PCI_64BIT_MODE_ENABLE=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_TSEC1_MODE_GMII=y +CONFIG_TSEC2_MODE_GMII=y +CONFIG_PCI_ONE_PCI1=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PCISLAVE" @@ -19,7 +28,8 @@ CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y -CONFIG_PHYLIB=y +CONFIG_NETDEVICES=y +CONFIG_TSEC_ENET=y # CONFIG_PCI is not set CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y diff --git a/configs/MPC8349EMDS_defconfig b/configs/MPC8349EMDS_defconfig index 9a6eebf746..ecded68c05 100644 --- a/configs/MPC8349EMDS_defconfig +++ b/configs/MPC8349EMDS_defconfig @@ -3,6 +3,16 @@ CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_MPC8349EMDS=y +CONFIG_DDR_MC_CLOCK_MODE_1_1=y +CONFIG_SYSTEM_PLL_FACTOR_4_1=y +CONFIG_CORE_PLL_RATIO_2_1=y +CONFIG_PCI_HOST_MODE_ENABLE=y +CONFIG_PCI_INT_ARBITER1_ENABLE=y +CONFIG_PCI_INT_ARBITER2_ENABLE=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_TSEC1_MODE_GMII=y +CONFIG_TSEC2_MODE_GMII=y CONFIG_PCI_ONE_PCI1=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/configs/MPC8349ITXGP_defconfig b/configs/MPC8349ITXGP_defconfig index c7f465e409..13312e04aa 100644 --- a/configs/MPC8349ITXGP_defconfig +++ b/configs/MPC8349ITXGP_defconfig @@ -3,6 +3,16 @@ CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_CLK_FREQ=66666666 CONFIG_MPC83xx=y CONFIG_TARGET_MPC8349ITX=y +CONFIG_DDR_MC_CLOCK_MODE_1_1=y +CONFIG_SYSTEM_PLL_FACTOR_4_1=y +CONFIG_CORE_PLL_RATIO_2_1=y +CONFIG_PCI_HOST_MODE_ENABLE=y +CONFIG_PCI_INT_ARBITER1_ENABLE=y +CONFIG_PCI_INT_ARBITER2_ENABLE=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_TSEC1_MODE_GMII=y +CONFIG_TSEC2_MODE_GMII=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFE000000" diff --git a/configs/MPC8349ITX_LOWBOOT_defconfig b/configs/MPC8349ITX_LOWBOOT_defconfig index 7dbde3222b..221edf9116 100644 --- a/configs/MPC8349ITX_LOWBOOT_defconfig +++ b/configs/MPC8349ITX_LOWBOOT_defconfig @@ -3,6 +3,16 @@ CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_CLK_FREQ=66666666 CONFIG_MPC83xx=y CONFIG_TARGET_MPC8349ITX=y +CONFIG_DDR_MC_CLOCK_MODE_1_1=y +CONFIG_SYSTEM_PLL_FACTOR_4_1=y +CONFIG_CORE_PLL_RATIO_2_1=y +CONFIG_PCI_HOST_MODE_ENABLE=y +CONFIG_PCI_INT_ARBITER1_ENABLE=y +CONFIG_PCI_INT_ARBITER2_ENABLE=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_TSEC1_MODE_GMII=y +CONFIG_TSEC2_MODE_GMII=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC8349ITX_defconfig b/configs/MPC8349ITX_defconfig index d3ab1eafeb..46c9085852 100644 --- a/configs/MPC8349ITX_defconfig +++ b/configs/MPC8349ITX_defconfig @@ -3,6 +3,15 @@ CONFIG_SYS_TEXT_BASE=0xFEF00000 CONFIG_SYS_CLK_FREQ=66666666 CONFIG_MPC83xx=y CONFIG_TARGET_MPC8349ITX=y +CONFIG_DDR_MC_CLOCK_MODE_1_1=y +CONFIG_SYSTEM_PLL_FACTOR_4_1=y +CONFIG_CORE_PLL_RATIO_2_1=y +CONFIG_PCI_HOST_MODE_ENABLE=y +CONFIG_PCI_INT_ARBITER1_ENABLE=y +CONFIG_PCI_INT_ARBITER2_ENABLE=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_TSEC1_MODE_GMII=y +CONFIG_TSEC2_MODE_GMII=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC837XEMDS_HOST_defconfig b/configs/MPC837XEMDS_HOST_defconfig index 15d60a2ccd..1b88b599f4 100644 --- a/configs/MPC837XEMDS_HOST_defconfig +++ b/configs/MPC837XEMDS_HOST_defconfig @@ -3,6 +3,16 @@ CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_MPC837XEMDS=y +CONFIG_DDR_MC_CLOCK_MODE_1_1=y +CONFIG_SYSTEM_PLL_FACTOR_6_1=y +CONFIG_CORE_PLL_RATIO_15_1=y +CONFIG_PCI_HOST_MODE_ENABLE=y +CONFIG_PCI_INT_ARBITER1_ENABLE=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_TSEC1_MODE_RGMII=y +CONFIG_TSEC2_MODE_RGMII=y +CONFIG_LDP_PIN_MUX_STATE_0=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC837XEMDS_SLAVE_defconfig b/configs/MPC837XEMDS_SLAVE_defconfig new file mode 100644 index 0000000000..8a50ff16d0 --- /dev/null +++ b/configs/MPC837XEMDS_SLAVE_defconfig @@ -0,0 +1,35 @@ +CONFIG_PPC=y +CONFIG_SYS_TEXT_BASE=0xFE000000 +CONFIG_SYS_CLK_FREQ=66000000 +CONFIG_MPC83xx=y +CONFIG_TARGET_MPC837XEMDS=y +CONFIG_DDR_MC_CLOCK_MODE_1_1=y +CONFIG_SYSTEM_PLL_FACTOR_6_1=y +CONFIG_CORE_PLL_RATIO_15_1=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_TSEC1_MODE_RGMII=y +CONFIG_TSEC2_MODE_RGMII=y +CONFIG_LDP_PIN_MUX_STATE_0=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_SYS_EXTRA_OPTIONS="PCISLAVE" +CONFIG_BOOTDELAY=6 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_IMLS=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_NAND=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_DATE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_FAT=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_CFI_DRIVER=y +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y +CONFIG_SYS_FLASH_CFI=y +CONFIG_TSEC_ENET=y +# CONFIG_PCI is not set +CONFIG_SYS_NS16550=y +CONFIG_OF_LIBFDT=y diff --git a/configs/MPC837XEMDS_defconfig b/configs/MPC837XEMDS_defconfig index d5d42ab12f..da908c762f 100644 --- a/configs/MPC837XEMDS_defconfig +++ b/configs/MPC837XEMDS_defconfig @@ -3,6 +3,16 @@ CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_MPC837XEMDS=y +CONFIG_DDR_MC_CLOCK_MODE_1_1=y +CONFIG_SYSTEM_PLL_FACTOR_6_1=y +CONFIG_CORE_PLL_RATIO_15_1=y +CONFIG_PCI_HOST_MODE_ENABLE=y +CONFIG_PCI_INT_ARBITER1_ENABLE=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_TSEC1_MODE_RGMII=y +CONFIG_TSEC2_MODE_RGMII=y +CONFIG_LDP_PIN_MUX_STATE_0=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC837XERDB_SLAVE_defconfig b/configs/MPC837XERDB_SLAVE_defconfig index 8c2389c698..e145504ded 100644 --- a/configs/MPC837XERDB_SLAVE_defconfig +++ b/configs/MPC837XERDB_SLAVE_defconfig @@ -3,6 +3,13 @@ CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_CLK_FREQ=66666667 CONFIG_MPC83xx=y CONFIG_TARGET_MPC837XERDB=y +CONFIG_DDR_MC_CLOCK_MODE_1_1=y +CONFIG_SYSTEM_PLL_FACTOR_5_1=y +CONFIG_CORE_PLL_RATIO_2_1=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_TSEC1_MODE_RGMII=y +CONFIG_TSEC2_MODE_RGMII=y +CONFIG_LDP_PIN_MUX_STATE_0=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PCISLAVE,PCIE" diff --git a/configs/MPC837XERDB_defconfig b/configs/MPC837XERDB_defconfig index 090b9e5152..4b9a7deb94 100644 --- a/configs/MPC837XERDB_defconfig +++ b/configs/MPC837XERDB_defconfig @@ -3,6 +3,16 @@ CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_CLK_FREQ=66666667 CONFIG_MPC83xx=y CONFIG_TARGET_MPC837XERDB=y +CONFIG_DDR_MC_CLOCK_MODE_1_1=y +CONFIG_SYSTEM_PLL_FACTOR_5_1=y +CONFIG_CORE_PLL_RATIO_2_1=y +CONFIG_PCI_HOST_MODE_ENABLE=y +CONFIG_PCI_INT_ARBITER1_ENABLE=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_TSEC1_MODE_RGMII=y +CONFIG_TSEC2_MODE_RGMII=y +CONFIG_LDP_PIN_MUX_STATE_0=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PCIE" diff --git a/configs/TQM834x_defconfig b/configs/TQM834x_defconfig index 8f68804a48..1e873c3e01 100644 --- a/configs/TQM834x_defconfig +++ b/configs/TQM834x_defconfig @@ -3,6 +3,15 @@ CONFIG_SYS_TEXT_BASE=0x80000000 CONFIG_SYS_CLK_FREQ=66666000 CONFIG_MPC83xx=y CONFIG_TARGET_TQM834X=y +CONFIG_DDR_MC_CLOCK_MODE_1_1=y +CONFIG_SYSTEM_PLL_FACTOR_4_1=y +CONFIG_CORE_PLL_RATIO_2_1=y +CONFIG_PCI_HOST_MODE_ENABLE=y +CONFIG_PCI_INT_ARBITER1_ENABLE=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_TSEC1_MODE_GMII=y +CONFIG_TSEC2_MODE_GMII=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/caddy2_defconfig b/configs/caddy2_defconfig index 2d2d64d103..29ec5e0afc 100644 --- a/configs/caddy2_defconfig +++ b/configs/caddy2_defconfig @@ -3,6 +3,16 @@ CONFIG_SYS_TEXT_BASE=0xFFF00000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_CADDY2=y +CONFIG_DDR_MC_CLOCK_MODE_1_1=y +CONFIG_SYSTEM_PLL_FACTOR_4_1=y +CONFIG_CORE_PLL_RATIO_2_1=y +CONFIG_PCI_HOST_MODE_ENABLE=y +CONFIG_PCI_INT_ARBITER1_ENABLE=y +CONFIG_PCI_INT_ARBITER2_ENABLE=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_TSEC1_MODE_GMII=y +CONFIG_TSEC2_MODE_GMII=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/hrcon_defconfig b/configs/hrcon_defconfig index 2a7b932b1e..97fe0e06fe 100644 --- a/configs/hrcon_defconfig +++ b/configs/hrcon_defconfig @@ -4,6 +4,12 @@ CONFIG_IDENT_STRING=" hrcon 0.01" CONFIG_SYS_CLK_FREQ=33333333 CONFIG_MPC83xx=y CONFIG_TARGET_HRCON=y +CONFIG_SYSTEM_PLL_VCO_DIV_2=y +CONFIG_SYSTEM_PLL_FACTOR_4_1=y +CONFIG_CORE_PLL_RATIO_3_1=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_TSEC1_MODE_RGMII=y +CONFIG_TSEC2_MODE_RGMII=y CONFIG_CMD_IOLOOP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/hrcon_dh_defconfig b/configs/hrcon_dh_defconfig index 3b1fbca268..83dd6bf3a9 100644 --- a/configs/hrcon_dh_defconfig +++ b/configs/hrcon_dh_defconfig @@ -4,6 +4,12 @@ CONFIG_IDENT_STRING=" hrcon dh 0.01" CONFIG_SYS_CLK_FREQ=33333333 CONFIG_MPC83xx=y CONFIG_TARGET_HRCON=y +CONFIG_SYSTEM_PLL_VCO_DIV_2=y +CONFIG_SYSTEM_PLL_FACTOR_4_1=y +CONFIG_CORE_PLL_RATIO_3_1=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_TSEC1_MODE_RGMII=y +CONFIG_TSEC2_MODE_RGMII=y CONFIG_CMD_IOLOOP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/ids8313_defconfig b/configs/ids8313_defconfig index 7223af1f55..482b51ef87 100644 --- a/configs/ids8313_defconfig +++ b/configs/ids8313_defconfig @@ -3,6 +3,9 @@ CONFIG_SYS_TEXT_BASE=0xFFF00000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_IDS8313=y +CONFIG_CORE_PLL_RATIO_2_1=y +CONFIG_PCI_HOST_MODE_ENABLE=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_8BIT=y CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_IMAGE_FORMAT_LEGACY=y diff --git a/configs/kmcoge5ne_defconfig b/configs/kmcoge5ne_defconfig index beac453ce5..7f22fa3b15 100644 --- a/configs/kmcoge5ne_defconfig +++ b/configs/kmcoge5ne_defconfig @@ -3,6 +3,15 @@ CONFIG_SYS_TEXT_BASE=0xF0000000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_KMCOGE5NE=y +CONFIG_DDR_MC_CLOCK_MODE_1_1=y +CONFIG_SYSTEM_PLL_VCO_DIV_4=y +CONFIG_SYSTEM_PLL_FACTOR_4_1=y +CONFIG_CORE_PLL_RATIO_2_1=y +CONFIG_QUICC_MULT_FACTOR_6=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_LALE_TIMING_EARLIER=y +CONFIG_LDP_PIN_MUX_STATE_0=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_MISC_INIT_R=y diff --git a/configs/kmeter1_defconfig b/configs/kmeter1_defconfig index 2bf2c40a63..600a1ad1dc 100644 --- a/configs/kmeter1_defconfig +++ b/configs/kmeter1_defconfig @@ -3,6 +3,15 @@ CONFIG_SYS_TEXT_BASE=0xF0000000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_KMETER1=y +CONFIG_DDR_MC_CLOCK_MODE_1_1=y +CONFIG_SYSTEM_PLL_VCO_DIV_4=y +CONFIG_SYSTEM_PLL_FACTOR_4_1=y +CONFIG_CORE_PLL_RATIO_2_1=y +CONFIG_QUICC_MULT_FACTOR_6=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_LALE_TIMING_EARLIER=y +CONFIG_LDP_PIN_MUX_STATE_0=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_MISC_INIT_R=y diff --git a/configs/kmopti2_defconfig b/configs/kmopti2_defconfig index 1b63b427f0..6486c6a59c 100644 --- a/configs/kmopti2_defconfig +++ b/configs/kmopti2_defconfig @@ -3,6 +3,10 @@ CONFIG_SYS_TEXT_BASE=0xF0000000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_KMOPTI2=y +CONFIG_CORE_PLL_RATIO_25_1=y +CONFIG_QUICC_MULT_FACTOR_3=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_MISC_INIT_R=y diff --git a/configs/kmsupx5_defconfig b/configs/kmsupx5_defconfig index df1bfaef18..20df9f3fa4 100644 --- a/configs/kmsupx5_defconfig +++ b/configs/kmsupx5_defconfig @@ -3,6 +3,10 @@ CONFIG_SYS_TEXT_BASE=0xF0000000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_KMSUPX5=y +CONFIG_CORE_PLL_RATIO_25_1=y +CONFIG_QUICC_MULT_FACTOR_3=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_MISC_INIT_R=y diff --git a/configs/kmtegr1_defconfig b/configs/kmtegr1_defconfig index 7187af7786..c1d30cdde8 100644 --- a/configs/kmtegr1_defconfig +++ b/configs/kmtegr1_defconfig @@ -3,6 +3,11 @@ CONFIG_SYS_TEXT_BASE=0xF0000000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_KMTEGR1=y +CONFIG_SYSTEM_PLL_VCO_DIV_2=y +CONFIG_CORE_PLL_RATIO_2_1=y +CONFIG_QUICC_MULT_FACTOR_3=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="KMTEGR1" diff --git a/configs/kmtepr2_defconfig b/configs/kmtepr2_defconfig index bbd13b8bfa..ed8bc32d65 100644 --- a/configs/kmtepr2_defconfig +++ b/configs/kmtepr2_defconfig @@ -3,6 +3,10 @@ CONFIG_SYS_TEXT_BASE=0xF0000000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_KMTEPR2=y +CONFIG_CORE_PLL_RATIO_25_1=y +CONFIG_QUICC_MULT_FACTOR_3=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_MISC_INIT_R=y diff --git a/configs/kmvect1_defconfig b/configs/kmvect1_defconfig index 98dd9e2b37..66b3cd39b5 100644 --- a/configs/kmvect1_defconfig +++ b/configs/kmvect1_defconfig @@ -3,6 +3,11 @@ CONFIG_SYS_TEXT_BASE=0xF0000000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_KMVECT1=y +CONFIG_SYSTEM_PLL_VCO_DIV_2=y +CONFIG_CORE_PLL_RATIO_2_1=y +CONFIG_QUICC_MULT_FACTOR_3=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="KMVECT1" diff --git a/configs/mpc8308_p1m_defconfig b/configs/mpc8308_p1m_defconfig index 1e50782f7c..cb24c97f04 100644 --- a/configs/mpc8308_p1m_defconfig +++ b/configs/mpc8308_p1m_defconfig @@ -3,6 +3,11 @@ CONFIG_SYS_TEXT_BASE=0xFC000000 CONFIG_SYS_CLK_FREQ=33333333 CONFIG_MPC83xx=y CONFIG_TARGET_MPC8308_P1M=y +CONFIG_SYSTEM_PLL_VCO_DIV_2=y +CONFIG_SYSTEM_PLL_FACTOR_4_1=y +CONFIG_CORE_PLL_RATIO_3_1=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=5 diff --git a/configs/sbc8349_PCI_33_defconfig b/configs/sbc8349_PCI_33_defconfig index eca22bec3a..7fc0edde70 100644 --- a/configs/sbc8349_PCI_33_defconfig +++ b/configs/sbc8349_PCI_33_defconfig @@ -3,6 +3,16 @@ CONFIG_SYS_TEXT_BASE=0xFF800000 CONFIG_SYS_CLK_FREQ=33000000 CONFIG_MPC83xx=y CONFIG_TARGET_SBC8349=y +CONFIG_DDR_MC_CLOCK_MODE_1_1=y +CONFIG_SYSTEM_PLL_FACTOR_8_1=y +CONFIG_CORE_PLL_RATIO_2_1=y +CONFIG_PCI_HOST_MODE_ENABLE=y +CONFIG_PCI_64BIT_MODE_ENABLE=y +CONFIG_PCI_INT_ARBITER1_ENABLE=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_TSEC1_MODE_GMII=y +CONFIG_TSEC2_MODE_GMII=y CONFIG_PCI_64BIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/configs/sbc8349_PCI_66_defconfig b/configs/sbc8349_PCI_66_defconfig index fa1ec519c5..80cdd644f7 100644 --- a/configs/sbc8349_PCI_66_defconfig +++ b/configs/sbc8349_PCI_66_defconfig @@ -3,6 +3,16 @@ CONFIG_SYS_TEXT_BASE=0xFF800000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_SBC8349=y +CONFIG_DDR_MC_CLOCK_MODE_1_1=y +CONFIG_SYSTEM_PLL_FACTOR_4_1=y +CONFIG_CORE_PLL_RATIO_2_1=y +CONFIG_PCI_HOST_MODE_ENABLE=y +CONFIG_PCI_64BIT_MODE_ENABLE=y +CONFIG_PCI_INT_ARBITER1_ENABLE=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_TSEC1_MODE_GMII=y +CONFIG_TSEC2_MODE_GMII=y CONFIG_PCI_64BIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/configs/sbc8349_defconfig b/configs/sbc8349_defconfig index d70332c785..1141b791e7 100644 --- a/configs/sbc8349_defconfig +++ b/configs/sbc8349_defconfig @@ -3,6 +3,16 @@ CONFIG_SYS_TEXT_BASE=0xFF800000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_SBC8349=y +CONFIG_DDR_MC_CLOCK_MODE_1_1=y +CONFIG_SYSTEM_PLL_FACTOR_4_1=y +CONFIG_CORE_PLL_RATIO_2_1=y +CONFIG_PCI_HOST_MODE_ENABLE=y +CONFIG_PCI_INT_ARBITER1_ENABLE=y +CONFIG_PCI_INT_ARBITER2_ENABLE=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_TSEC1_MODE_GMII=y +CONFIG_TSEC2_MODE_GMII=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/strider_con_defconfig b/configs/strider_con_defconfig index 194cebdb67..c2faf3855e 100644 --- a/configs/strider_con_defconfig +++ b/configs/strider_con_defconfig @@ -4,6 +4,11 @@ CONFIG_IDENT_STRING=" strider con 0.01" CONFIG_SYS_CLK_FREQ=33333333 CONFIG_MPC83xx=y CONFIG_TARGET_STRIDER=y +CONFIG_SYSTEM_PLL_VCO_DIV_2=y +CONFIG_SYSTEM_PLL_FACTOR_4_1=y +CONFIG_CORE_PLL_RATIO_3_1=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_TSEC2_MODE_RGMII=y CONFIG_CMD_IOLOOP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/strider_con_dp_defconfig b/configs/strider_con_dp_defconfig index 4e72582d2f..cff81f41f5 100644 --- a/configs/strider_con_dp_defconfig +++ b/configs/strider_con_dp_defconfig @@ -4,6 +4,11 @@ CONFIG_IDENT_STRING=" strider con dp 0.01" CONFIG_SYS_CLK_FREQ=33333333 CONFIG_MPC83xx=y CONFIG_TARGET_STRIDER=y +CONFIG_SYSTEM_PLL_VCO_DIV_2=y +CONFIG_SYSTEM_PLL_FACTOR_4_1=y +CONFIG_CORE_PLL_RATIO_3_1=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_TSEC2_MODE_RGMII=y CONFIG_CMD_IOLOOP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/strider_cpu_defconfig b/configs/strider_cpu_defconfig index c633e030e3..f72bec439b 100644 --- a/configs/strider_cpu_defconfig +++ b/configs/strider_cpu_defconfig @@ -4,6 +4,11 @@ CONFIG_IDENT_STRING=" strider cpu 0.01" CONFIG_SYS_CLK_FREQ=33333333 CONFIG_MPC83xx=y CONFIG_TARGET_STRIDER=y +CONFIG_SYSTEM_PLL_VCO_DIV_2=y +CONFIG_SYSTEM_PLL_FACTOR_4_1=y +CONFIG_CORE_PLL_RATIO_3_1=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_TSEC2_MODE_RGMII=y CONFIG_CMD_IOLOOP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/strider_cpu_dp_defconfig b/configs/strider_cpu_dp_defconfig index e1d08e782d..0e43049663 100644 --- a/configs/strider_cpu_dp_defconfig +++ b/configs/strider_cpu_dp_defconfig @@ -4,6 +4,11 @@ CONFIG_IDENT_STRING=" strider cpu dp 0.01" CONFIG_SYS_CLK_FREQ=33333333 CONFIG_MPC83xx=y CONFIG_TARGET_STRIDER=y +CONFIG_SYSTEM_PLL_VCO_DIV_2=y +CONFIG_SYSTEM_PLL_FACTOR_4_1=y +CONFIG_CORE_PLL_RATIO_3_1=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_TSEC2_MODE_RGMII=y CONFIG_CMD_IOLOOP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/suvd3_defconfig b/configs/suvd3_defconfig index 4744122e4e..9b36aa0fa4 100644 --- a/configs/suvd3_defconfig +++ b/configs/suvd3_defconfig @@ -3,6 +3,10 @@ CONFIG_SYS_TEXT_BASE=0xF0000000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_SUVD3=y +CONFIG_CORE_PLL_RATIO_25_1=y +CONFIG_QUICC_MULT_FACTOR_3=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SUVD3" diff --git a/configs/tuge1_defconfig b/configs/tuge1_defconfig index 349b1d0009..3467b7ebd9 100644 --- a/configs/tuge1_defconfig +++ b/configs/tuge1_defconfig @@ -3,6 +3,10 @@ CONFIG_SYS_TEXT_BASE=0xF0000000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_TUGE1=y +CONFIG_CORE_PLL_RATIO_25_1=y +CONFIG_QUICC_MULT_FACTOR_3=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_MISC_INIT_R=y diff --git a/configs/tuxx1_defconfig b/configs/tuxx1_defconfig index a6654c9025..f67e3b8728 100644 --- a/configs/tuxx1_defconfig +++ b/configs/tuxx1_defconfig @@ -3,6 +3,10 @@ CONFIG_SYS_TEXT_BASE=0xF0000000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_TUXX1=y +CONFIG_CORE_PLL_RATIO_25_1=y +CONFIG_QUICC_MULT_FACTOR_3=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_MISC_INIT_R=y diff --git a/configs/ve8313_defconfig b/configs/ve8313_defconfig index 084b1bdeaf..f09c83d856 100644 --- a/configs/ve8313_defconfig +++ b/configs/ve8313_defconfig @@ -3,6 +3,13 @@ CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_CLK_FREQ=32000000 CONFIG_MPC83xx=y CONFIG_TARGET_VE8313=y +CONFIG_SYSTEM_PLL_FACTOR_4_1=y +CONFIG_CORE_PLL_RATIO_25_1=y +CONFIG_PCI_HOST_MODE_ENABLE=y +CONFIG_PCI_INT_ARBITER1_ENABLE=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_LALE_TIMING_EARLIER=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/vme8349_defconfig b/configs/vme8349_defconfig index aae2214192..271e690535 100644 --- a/configs/vme8349_defconfig +++ b/configs/vme8349_defconfig @@ -3,6 +3,16 @@ CONFIG_SYS_TEXT_BASE=0xFFF00000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_VME8349=y +CONFIG_DDR_MC_CLOCK_MODE_1_1=y +CONFIG_SYSTEM_PLL_FACTOR_4_1=y +CONFIG_CORE_PLL_RATIO_2_1=y +CONFIG_PCI_HOST_MODE_ENABLE=y +CONFIG_PCI_64BIT_MODE_ENABLE=y +CONFIG_PCI_INT_ARBITER1_ENABLE=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_TSEC1_MODE_GMII=y +CONFIG_TSEC2_MODE_GMII=y CONFIG_PCI_64BIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h index 77c30093bf..db283578b9 100644 --- a/include/configs/MPC8308RDB.h +++ b/include/configs/MPC8308RDB.h @@ -27,38 +27,6 @@ #define CONFIG_TSEC1 #define CONFIG_VSC7385_ENET -/* - * Hardware Reset Configuration Word - * if CLKIN is 66.66MHz, then - * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz - * We choose the A type silicon as default, so the core is 400Mhz. - */ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_2X1 |\ - HRCWL_SVCOD_DIV_2 |\ - HRCWL_CSB_TO_CLKIN_4X1 |\ - HRCWL_CORE_TO_CSB_3X1) -/* - * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits - * in 8308's HRCWH according to the manual, but original Freescale's - * code has them and I've expirienced some problems using the board - * with BDI3000 attached when I've tried to set these bits to zero - * (UART doesn't work after the 'reset run' command). - */ -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_HOST |\ - HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0X00000100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_RL_EXT_LEGACY |\ - HRCWH_TSEC1M_IN_RGMII |\ - HRCWH_TSEC2M_IN_RGMII |\ - HRCWH_BIG_ENDIAN) - /* * System IO Config */ diff --git a/include/configs/MPC8313ERDB_NAND.h b/include/configs/MPC8313ERDB_NAND.h index 103ace2d3a..e14652a626 100644 --- a/include/configs/MPC8313ERDB_NAND.h +++ b/include/configs/MPC8313ERDB_NAND.h @@ -424,44 +424,6 @@ #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ -#ifdef CONFIG_SYS_66MHZ - -/* 66MHz IN, 133MHz CSB, 266 DDR, 266 CORE */ -/* 0x62040000 */ -#define CONFIG_SYS_HRCW_LOW (\ - 0x20000000 /* reserved, must be set */ |\ - HRCWL_DDRCM |\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_2X1 |\ - HRCWL_CSB_TO_CLKIN_2X1 |\ - HRCWL_CORE_TO_CSB_2X1) -#elif defined(CONFIG_SYS_33MHZ) - -/* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */ -/* 0x65040000 */ -#define CONFIG_SYS_HRCW_LOW (\ - 0x20000000 /* reserved, must be set */ |\ - HRCWL_DDRCM |\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_2X1 |\ - HRCWL_CSB_TO_CLKIN_5X1 |\ - HRCWL_CORE_TO_CSB_2X1) -#endif - -#define CONFIG_SYS_HRCW_HIGH_BASE (\ - HRCWH_PCI_HOST |\ - HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_TSEC1M_IN_RGMII |\ - HRCWH_TSEC2M_IN_RGMII |\ - HRCWH_BIG_ENDIAN) - -#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ - HRCWH_FROM_0XFFF00100 |\ - HRCWH_ROM_LOC_NAND_SP_8BIT |\ - HRCWH_RL_EXT_NAND) #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)) /* System IO Config */ diff --git a/include/configs/MPC8313ERDB_NOR.h b/include/configs/MPC8313ERDB_NOR.h index 64b289adce..b550a8daf8 100644 --- a/include/configs/MPC8313ERDB_NOR.h +++ b/include/configs/MPC8313ERDB_NOR.h @@ -398,46 +398,6 @@ #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ -#ifdef CONFIG_SYS_66MHZ - -/* 66MHz IN, 133MHz CSB, 266 DDR, 266 CORE */ -/* 0x62040000 */ -#define CONFIG_SYS_HRCW_LOW (\ - 0x20000000 /* reserved, must be set */ |\ - HRCWL_DDRCM |\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_2X1 |\ - HRCWL_CSB_TO_CLKIN_2X1 |\ - HRCWL_CORE_TO_CSB_2X1) - -#elif defined(CONFIG_SYS_33MHZ) - -/* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */ -/* 0x65040000 */ -#define CONFIG_SYS_HRCW_LOW (\ - 0x20000000 /* reserved, must be set */ |\ - HRCWL_DDRCM |\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_2X1 |\ - HRCWL_CSB_TO_CLKIN_5X1 |\ - HRCWL_CORE_TO_CSB_2X1) - -#endif - -#define CONFIG_SYS_HRCW_HIGH_BASE (\ - HRCWH_PCI_HOST |\ - HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_TSEC1M_IN_RGMII |\ - HRCWH_TSEC2M_IN_RGMII |\ - HRCWH_BIG_ENDIAN) - -#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ - HRCWH_FROM_0X00000100 |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_RL_EXT_LEGACY) #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)) /* System IO Config */ diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index 53a02f415f..446c98bad1 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -23,40 +23,6 @@ */ #define CONFIG_E300 1 /* E300 family */ -/* - * Hardware Reset Configuration Word - * if CLKIN is 66.66MHz, then - * CSB = 133MHz, CORE = 400MHz, DDRC = 266MHz, LBC = 133MHz - */ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_2X1 |\ - HRCWL_SVCOD_DIV_2 |\ - HRCWL_CSB_TO_CLKIN_2X1 |\ - HRCWL_CORE_TO_CSB_3X1) -#define CONFIG_SYS_HRCW_HIGH_BASE (\ - HRCWH_PCI_HOST |\ - HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_TSEC1M_IN_RGMII |\ - HRCWH_TSEC2M_IN_RGMII |\ - HRCWH_BIG_ENDIAN |\ - HRCWH_LALE_NORMAL) - -#ifdef CONFIG_NAND_SPL -#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ - HRCWH_FROM_0XFFF00100 |\ - HRCWH_ROM_LOC_NAND_SP_8BIT |\ - HRCWH_RL_EXT_NAND) -#else -#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ - HRCWH_FROM_0X00000100 |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_RL_EXT_LEGACY) -#endif - /* * System IO Config */ diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index ee4eeec885..7dbbb4e0fb 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -15,30 +15,6 @@ #define CONFIG_E300 1 /* E300 family */ #define CONFIG_QE 1 /* Has QE */ -/* - * Hardware Reset Configuration Word - */ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_2X1 |\ - HRCWL_VCO_1X2 |\ - HRCWL_CSB_TO_CLKIN_2X1 |\ - HRCWL_CORE_TO_CSB_2_5X1 |\ - HRCWL_CE_PLL_VCO_DIV_2 |\ - HRCWL_CE_PLL_DIV_1X1 |\ - HRCWL_CE_TO_PLL_1X3) - -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_HOST |\ - HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0X00000100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_BIG_ENDIAN |\ - HRCWH_LALE_NORMAL) - /* * System IO Config */ diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index 0ba6477254..dad8407f67 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -12,43 +12,6 @@ #define CONFIG_E300 1 /* E300 family */ #define CONFIG_QE 1 /* Has QE */ -/* - * Hardware Reset Configuration Word - */ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_2X1 |\ - HRCWL_VCO_1X2 |\ - HRCWL_CSB_TO_CLKIN_2X1 |\ - HRCWL_CORE_TO_CSB_2X1 |\ - HRCWL_CE_PLL_VCO_DIV_2 |\ - HRCWL_CE_PLL_DIV_1X1 |\ - HRCWL_CE_TO_PLL_1X3) - -#ifdef CONFIG_PCISLAVE -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_AGENT |\ - HRCWH_PCI1_ARBITER_DISABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0XFFF00100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_BIG_ENDIAN |\ - HRCWH_LALE_NORMAL) -#else -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_HOST |\ - HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0X00000100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_BIG_ENDIAN |\ - HRCWH_LALE_NORMAL) -#endif - /* * System IO Config */ diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 4c9ee76815..2159454061 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -17,12 +17,6 @@ */ #define CONFIG_E300 1 /* E300 Family */ -#if CONFIG_SYS_CLK_FREQ == 66000000 || CONFIG_SYS_CLK_FREQ == 66666666 -#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1 -#elif CONFIG_SYS_CLK_FREQ == 33000000 -#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1 -#endif - #define CONFIG_SYS_IMMR 0xE0000000 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ @@ -363,86 +357,6 @@ #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ -#if 1 /*528/264*/ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_1X1 |\ - HRCWL_CSB_TO_CLKIN |\ - HRCWL_VCO_1X2 |\ - HRCWL_CORE_TO_CSB_2X1) -#elif 0 /*396/132*/ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_1X1 |\ - HRCWL_CSB_TO_CLKIN |\ - HRCWL_VCO_1X4 |\ - HRCWL_CORE_TO_CSB_3X1) -#elif 0 /*264/132*/ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_1X1 |\ - HRCWL_CSB_TO_CLKIN |\ - HRCWL_VCO_1X4 |\ - HRCWL_CORE_TO_CSB_2X1) -#elif 0 /*132/132*/ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_1X1 |\ - HRCWL_CSB_TO_CLKIN |\ - HRCWL_VCO_1X4 |\ - HRCWL_CORE_TO_CSB_1X1) -#elif 0 /*264/264 */ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_1X1 |\ - HRCWL_CSB_TO_CLKIN |\ - HRCWL_VCO_1X4 |\ - HRCWL_CORE_TO_CSB_1X1) -#endif - -#ifdef CONFIG_PCISLAVE -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_AGENT |\ - HRCWH_64_BIT_PCI |\ - HRCWH_PCI1_ARBITER_DISABLE |\ - HRCWH_PCI2_ARBITER_DISABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0X00000100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_TSEC1M_IN_GMII |\ - HRCWH_TSEC2M_IN_GMII) -#else -#if defined(CONFIG_PCI_64BIT) -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_HOST |\ - HRCWH_64_BIT_PCI |\ - HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_PCI2_ARBITER_DISABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0X00000100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_TSEC1M_IN_GMII |\ - HRCWH_TSEC2M_IN_GMII) -#else -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_HOST |\ - HRCWH_32_BIT_PCI |\ - HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_PCI2_ARBITER_ENABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0X00000100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_TSEC1M_IN_GMII |\ - HRCWH_TSEC2M_IN_GMII) -#endif /* CONFIG_PCI_64BIT */ -#endif /* CONFIG_PCISLAVE */ - /* * System performance */ diff --git a/include/configs/MPC8349EMDS_SDRAM.h b/include/configs/MPC8349EMDS_SDRAM.h index b9710b6588..a19e732d8a 100644 --- a/include/configs/MPC8349EMDS_SDRAM.h +++ b/include/configs/MPC8349EMDS_SDRAM.h @@ -17,12 +17,6 @@ */ #define CONFIG_E300 1 /* E300 Family */ -#if CONFIG_SYS_CLK_FREQ == 66000000 || CONFIG_SYS_CLK_FREQ == 66666666 -#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1 -#elif CONFIG_SYS_CLK_FREQ == 33000000 -#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1 -#endif - #define CONFIG_SYS_IMMR 0xE0000000 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ @@ -435,86 +429,6 @@ #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ -#if 1 /*528/264*/ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_1X1 |\ - HRCWL_CSB_TO_CLKIN |\ - HRCWL_VCO_1X2 |\ - HRCWL_CORE_TO_CSB_2X1) -#elif 0 /*396/132*/ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_1X1 |\ - HRCWL_CSB_TO_CLKIN |\ - HRCWL_VCO_1X4 |\ - HRCWL_CORE_TO_CSB_3X1) -#elif 0 /*264/132*/ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_1X1 |\ - HRCWL_CSB_TO_CLKIN |\ - HRCWL_VCO_1X4 |\ - HRCWL_CORE_TO_CSB_2X1) -#elif 0 /*132/132*/ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_1X1 |\ - HRCWL_CSB_TO_CLKIN |\ - HRCWL_VCO_1X4 |\ - HRCWL_CORE_TO_CSB_1X1) -#elif 0 /*264/264 */ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_1X1 |\ - HRCWL_CSB_TO_CLKIN |\ - HRCWL_VCO_1X4 |\ - HRCWL_CORE_TO_CSB_1X1) -#endif - -#ifdef CONFIG_PCISLAVE -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_AGENT |\ - HRCWH_64_BIT_PCI |\ - HRCWH_PCI1_ARBITER_DISABLE |\ - HRCWH_PCI2_ARBITER_DISABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0X00000100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_TSEC1M_IN_GMII |\ - HRCWH_TSEC2M_IN_GMII) -#else -#if defined(CONFIG_PCI_64BIT) -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_HOST |\ - HRCWH_64_BIT_PCI |\ - HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_PCI2_ARBITER_DISABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0X00000100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_TSEC1M_IN_GMII |\ - HRCWH_TSEC2M_IN_GMII) -#else -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_HOST |\ - HRCWH_32_BIT_PCI |\ - HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_PCI2_ARBITER_ENABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0X00000100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_TSEC1M_IN_GMII |\ - HRCWH_TSEC2M_IN_GMII) -#endif /* CONFIG_PCI_64BIT */ -#endif /* CONFIG_PCISLAVE */ - /* * System performance */ diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index e170271c40..6860c72794 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -39,10 +39,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#if (CONFIG_SYS_TEXT_BASE == 0xFE000000) -#define CONFIG_SYS_LOWBOOT -#endif - /* * High Level Configuration Options */ @@ -461,41 +457,6 @@ boards, we say we have two, but don't display a message if we find only one. */ #define CONFIG_SYS_BOOTMAPSZ (256 << 20) #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_1X1 |\ - HRCWL_CSB_TO_CLKIN_4X1 |\ - HRCWL_VCO_1X2 |\ - HRCWL_CORE_TO_CSB_2X1) - -#ifdef CONFIG_SYS_LOWBOOT -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_HOST |\ - HRCWH_32_BIT_PCI |\ - HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_PCI2_ARBITER_ENABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0X00000100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_TSEC1M_IN_GMII |\ - HRCWH_TSEC2M_IN_GMII) -#else -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_HOST |\ - HRCWH_32_BIT_PCI |\ - HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_PCI2_ARBITER_ENABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0XFFF00100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_TSEC1M_IN_GMII |\ - HRCWH_TSEC2M_IN_GMII) -#endif - /* * System performance */ diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index 33c485aab7..8c562fde2e 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -12,48 +12,6 @@ */ #define CONFIG_E300 1 /* E300 family */ -/* - * Hardware Reset Configuration Word - * if CLKIN is 66MHz, then - * CSB = 396MHz, CORE = 594MHz, DDRC = 396MHz, LBC = 396MHz - */ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_1X1 |\ - HRCWL_SVCOD_DIV_2 |\ - HRCWL_CSB_TO_CLKIN_6X1 |\ - HRCWL_CORE_TO_CSB_1_5X1) - -#ifdef CONFIG_PCISLAVE -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_AGENT |\ - HRCWH_PCI1_ARBITER_DISABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0XFFF00100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_RL_EXT_LEGACY |\ - HRCWH_TSEC1M_IN_RGMII |\ - HRCWH_TSEC2M_IN_RGMII |\ - HRCWH_BIG_ENDIAN |\ - HRCWH_LDP_CLEAR) -#else -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_HOST |\ - HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0X00000100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_RL_EXT_LEGACY |\ - HRCWH_TSEC1M_IN_RGMII |\ - HRCWH_TSEC2M_IN_RGMII |\ - HRCWH_BIG_ENDIAN |\ - HRCWH_LDP_CLEAR) -#endif - /* Arbiter Configuration Register */ #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */ #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */ diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index 806b0f32e5..055a30e24f 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -20,46 +20,6 @@ */ #define CONFIG_VSC7385_ENET -/* - * Hardware Reset Configuration Word - */ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_1X1 |\ - HRCWL_SVCOD_DIV_2 |\ - HRCWL_CSB_TO_CLKIN_5X1 |\ - HRCWL_CORE_TO_CSB_2X1) - -#ifdef CONFIG_PCISLAVE -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_AGENT |\ - HRCWH_PCI1_ARBITER_DISABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0XFFF00100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_RL_EXT_LEGACY |\ - HRCWH_TSEC1M_IN_RGMII |\ - HRCWH_TSEC2M_IN_RGMII |\ - HRCWH_BIG_ENDIAN |\ - HRCWH_LDP_CLEAR) -#else -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_HOST |\ - HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0X00000100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_RL_EXT_LEGACY |\ - HRCWH_TSEC1M_IN_RGMII |\ - HRCWH_TSEC2M_IN_RGMII |\ - HRCWH_BIG_ENDIAN |\ - HRCWH_LDP_CLEAR) -#endif - /* System performance - define the value i.e. CONFIG_SYS_XXX */ diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index 58c301553e..be1c2893f1 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -260,41 +260,6 @@ /* Initial Memory map for Linux */ #define CONFIG_SYS_BOOTMAPSZ (256 << 20) -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_1X1 |\ - HRCWL_CSB_TO_CLKIN_4X1 |\ - HRCWL_VCO_1X2 |\ - HRCWL_CORE_TO_CSB_2X1) - -#if defined(CONFIG_PCI_64BIT) -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_HOST |\ - HRCWH_64_BIT_PCI |\ - HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_PCI2_ARBITER_DISABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0X00000100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_TSEC1M_IN_GMII |\ - HRCWH_TSEC2M_IN_GMII) -#else -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_HOST |\ - HRCWH_32_BIT_PCI |\ - HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_PCI2_ARBITER_DISABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0X00000100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_TSEC1M_IN_GMII |\ - HRCWH_TSEC2M_IN_GMII) -#endif - /* System IO Config */ #define CONFIG_SYS_SICRH 0 #define CONFIG_SYS_SICRL SICRL_LDP_A diff --git a/include/configs/caddy2.h b/include/configs/caddy2.h index 68fb989856..5e88bd7eda 100644 --- a/include/configs/caddy2.h +++ b/include/configs/caddy2.h @@ -25,12 +25,6 @@ /* Don't enable PCI2 on vme834x - it doesn't exist physically. */ #undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */ -#ifdef CONFIG_PCI_66M -#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1 -#else -#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1 -#endif - #define CONFIG_SYS_IMMR 0xE0000000 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ @@ -290,41 +284,6 @@ #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_1X1 |\ - HRCWL_CSB_TO_CLKIN |\ - HRCWL_VCO_1X2 |\ - HRCWL_CORE_TO_CSB_2X1) - -#if defined(PCI_64BIT) -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_HOST |\ - HRCWH_64_BIT_PCI |\ - HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_PCI2_ARBITER_DISABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0X00000100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_TSEC1M_IN_GMII |\ - HRCWH_TSEC2M_IN_GMII) -#else -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_HOST |\ - HRCWH_32_BIT_PCI |\ - HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_PCI2_ARBITER_ENABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0X00000100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_TSEC1M_IN_GMII |\ - HRCWH_TSEC2M_IN_GMII) -#endif - /* System IO Config */ #define CONFIG_SYS_SICRH 0 #define CONFIG_SYS_SICRL SICRL_LDP_A diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h index 8eb12b7670..c1fe6b45bd 100644 --- a/include/configs/hrcon.h +++ b/include/configs/hrcon.h @@ -16,38 +16,6 @@ #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR -/* - * Hardware Reset Configuration Word - * if CLKIN is 66.66MHz, then - * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz - * We choose the A type silicon as default, so the core is 400Mhz. - */ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_2X1 |\ - HRCWL_SVCOD_DIV_2 |\ - HRCWL_CSB_TO_CLKIN_4X1 |\ - HRCWL_CORE_TO_CSB_3X1) -/* - * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits - * in 8308's HRCWH according to the manual, but original Freescale's - * code has them and I've expirienced some problems using the board - * with BDI3000 attached when I've tried to set these bits to zero - * (UART doesn't work after the 'reset run' command). - */ -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_HOST |\ - HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0XFFF00100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_RL_EXT_LEGACY |\ - HRCWH_TSEC1M_IN_RGMII |\ - HRCWH_TSEC2M_IN_RGMII |\ - HRCWH_BIG_ENDIAN) - /* * System IO Config */ diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h index eff0addd51..4e5927ed70 100644 --- a/include/configs/ids8313.h +++ b/include/configs/ids8313.h @@ -25,27 +25,6 @@ #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ -/* - * Hardware Reset Configuration Word - * if CLKIN is 66.000MHz, then - * CSB = 132MHz, CORE = 264MHz, DDRC = 264MHz, LBC = 132MHz - */ -#define CONFIG_SYS_HRCW_LOW (0x20000000 /* reserved, must be set */ |\ - HRCWL_DDR_TO_SCB_CLK_2X1 |\ - HRCWL_CSB_TO_CLKIN_2X1 |\ - HRCWL_CORE_TO_CSB_2X1) - -#define CONFIG_SYS_HRCW_HIGH (HRCWH_PCI_HOST |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0XFFF00100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_8BIT |\ - HRCWH_RL_EXT_LEGACY |\ - HRCWH_TSEC1M_IN_MII |\ - HRCWH_TSEC2M_IN_MII |\ - HRCWH_BIG_ENDIAN) - #define CONFIG_SYS_SICRH 0x00000000 #define CONFIG_SYS_SICRL (SICRL_LBC | SICRL_SPI_D) diff --git a/include/configs/kmcoge5ne.h b/include/configs/kmcoge5ne.h index ec65a4208b..7e579db6ae 100644 --- a/include/configs/kmcoge5ne.h +++ b/include/configs/kmcoge5ne.h @@ -318,25 +318,6 @@ */ #define CONFIG_SYS_SICRH (SICRH_UC1EOBI | SICRH_UC2E1OBI) -/* - * Hardware Reset Configuration Word - */ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_CSB_TO_CLKIN_4X1 | \ - HRCWL_CORE_TO_CSB_2X1 | \ - HRCWL_CE_PLL_VCO_DIV_2 | \ - HRCWL_CE_TO_PLL_1X6) - -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_CORE_ENABLE | \ - HRCWH_FROM_0X00000100 | \ - HRCWH_BOOTSEQ_DISABLE | \ - HRCWH_SW_WATCHDOG_DISABLE | \ - HRCWH_ROM_LOC_LOCAL_16BIT | \ - HRCWH_BIG_ENDIAN | \ - HRCWH_LALE_EARLY | \ - HRCWH_LDP_CLEAR) - /** * DDR RAM settings */ diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h index 2280f007f2..3a98f9497b 100644 --- a/include/configs/kmeter1.h +++ b/include/configs/kmeter1.h @@ -304,25 +304,6 @@ */ #define CONFIG_SYS_SICRH (SICRH_UC1EOBI | SICRH_UC2E1OBI) -/* - * Hardware Reset Configuration Word - */ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_CSB_TO_CLKIN_4X1 | \ - HRCWL_CORE_TO_CSB_2X1 | \ - HRCWL_CE_PLL_VCO_DIV_2 | \ - HRCWL_CE_TO_PLL_1X6) - -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_CORE_ENABLE | \ - HRCWH_FROM_0X00000100 | \ - HRCWH_BOOTSEQ_DISABLE | \ - HRCWH_SW_WATCHDOG_DISABLE | \ - HRCWH_ROM_LOC_LOCAL_16BIT | \ - HRCWH_BIG_ENDIAN | \ - HRCWH_LALE_EARLY | \ - HRCWH_LDP_CLEAR) - /** * DDR RAM settings */ diff --git a/include/configs/kmopti2.h b/include/configs/kmopti2.h index fa12d41080..4494475486 100644 --- a/include/configs/kmopti2.h +++ b/include/configs/kmopti2.h @@ -323,28 +323,6 @@ */ #define CONFIG_SYS_SICRL SICRL_IRQ_CKS -/* - * Hardware Reset Configuration Word - */ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \ - HRCWL_DDR_TO_SCB_CLK_2X1 | \ - HRCWL_CSB_TO_CLKIN_2X1 | \ - HRCWL_CORE_TO_CSB_2_5X1 | \ - HRCWL_CE_PLL_VCO_DIV_2 | \ - HRCWL_CE_TO_PLL_1X3) - -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_AGENT | \ - HRCWH_PCI_ARBITER_DISABLE | \ - HRCWH_CORE_ENABLE | \ - HRCWH_FROM_0X00000100 | \ - HRCWH_BOOTSEQ_DISABLE | \ - HRCWH_SW_WATCHDOG_DISABLE | \ - HRCWH_ROM_LOC_LOCAL_16BIT | \ - HRCWH_BIG_ENDIAN | \ - HRCWH_LALE_NORMAL) - #define CONFIG_SYS_DDRCDR (\ DDRCDR_EN | \ DDRCDR_PZ_MAXZ | \ diff --git a/include/configs/kmsupx5.h b/include/configs/kmsupx5.h index 30898c0b75..7c008f8516 100644 --- a/include/configs/kmsupx5.h +++ b/include/configs/kmsupx5.h @@ -323,28 +323,6 @@ */ #define CONFIG_SYS_SICRL SICRL_IRQ_CKS -/* - * Hardware Reset Configuration Word - */ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \ - HRCWL_DDR_TO_SCB_CLK_2X1 | \ - HRCWL_CSB_TO_CLKIN_2X1 | \ - HRCWL_CORE_TO_CSB_2_5X1 | \ - HRCWL_CE_PLL_VCO_DIV_2 | \ - HRCWL_CE_TO_PLL_1X3) - -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_AGENT | \ - HRCWH_PCI_ARBITER_DISABLE | \ - HRCWH_CORE_ENABLE | \ - HRCWH_FROM_0X00000100 | \ - HRCWH_BOOTSEQ_DISABLE | \ - HRCWH_SW_WATCHDOG_DISABLE | \ - HRCWH_ROM_LOC_LOCAL_16BIT | \ - HRCWH_BIG_ENDIAN | \ - HRCWH_LALE_NORMAL) - #define CONFIG_SYS_DDRCDR (\ DDRCDR_EN | \ DDRCDR_PZ_MAXZ | \ diff --git a/include/configs/kmtegr1.h b/include/configs/kmtegr1.h index 329a5cfe0f..95b16ca585 100644 --- a/include/configs/kmtegr1.h +++ b/include/configs/kmtegr1.h @@ -374,28 +374,6 @@ #define CONFIG_SYS_GP2DIR 0xFF000000 #define CONFIG_SYS_GP2ODR 0x00000000 -/* - * Hardware Reset Configuration Word - */ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \ - HRCWL_DDR_TO_SCB_CLK_2X1 | \ - HRCWL_CSB_TO_CLKIN_2X1 | \ - HRCWL_CORE_TO_CSB_2X1 | \ - HRCWL_CE_PLL_VCO_DIV_2 | \ - HRCWL_CE_TO_PLL_1X3) - -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_AGENT | \ - HRCWH_PCI_ARBITER_DISABLE | \ - HRCWH_CORE_ENABLE | \ - HRCWH_FROM_0X00000100 | \ - HRCWH_BOOTSEQ_DISABLE | \ - HRCWH_SW_WATCHDOG_DISABLE | \ - HRCWH_ROM_LOC_LOCAL_16BIT | \ - HRCWH_BIG_ENDIAN | \ - HRCWH_LALE_NORMAL) - #define CONFIG_SYS_DDRCDR (\ DDRCDR_EN | \ DDRCDR_PZ_MAXZ | \ diff --git a/include/configs/kmtepr2.h b/include/configs/kmtepr2.h index 02b72c874e..5191f2c4b0 100644 --- a/include/configs/kmtepr2.h +++ b/include/configs/kmtepr2.h @@ -323,28 +323,6 @@ */ #define CONFIG_SYS_SICRL SICRL_IRQ_CKS -/* - * Hardware Reset Configuration Word - */ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \ - HRCWL_DDR_TO_SCB_CLK_2X1 | \ - HRCWL_CSB_TO_CLKIN_2X1 | \ - HRCWL_CORE_TO_CSB_2_5X1 | \ - HRCWL_CE_PLL_VCO_DIV_2 | \ - HRCWL_CE_TO_PLL_1X3) - -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_AGENT | \ - HRCWH_PCI_ARBITER_DISABLE | \ - HRCWH_CORE_ENABLE | \ - HRCWH_FROM_0X00000100 | \ - HRCWH_BOOTSEQ_DISABLE | \ - HRCWH_SW_WATCHDOG_DISABLE | \ - HRCWH_ROM_LOC_LOCAL_16BIT | \ - HRCWH_BIG_ENDIAN | \ - HRCWH_LALE_NORMAL) - #define CONFIG_SYS_DDRCDR (\ DDRCDR_EN | \ DDRCDR_PZ_MAXZ | \ diff --git a/include/configs/kmvect1.h b/include/configs/kmvect1.h index c21b9ba38f..cc88f071ec 100644 --- a/include/configs/kmvect1.h +++ b/include/configs/kmvect1.h @@ -366,28 +366,6 @@ #define CONFIG_SYS_GP2DIR 0xFF000000 #define CONFIG_SYS_GP2ODR 0x00000000 -/* - * Hardware Reset Configuration Word - */ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \ - HRCWL_DDR_TO_SCB_CLK_2X1 | \ - HRCWL_CSB_TO_CLKIN_2X1 | \ - HRCWL_CORE_TO_CSB_2X1 | \ - HRCWL_CE_PLL_VCO_DIV_2 | \ - HRCWL_CE_TO_PLL_1X3) - -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_AGENT | \ - HRCWH_PCI_ARBITER_DISABLE | \ - HRCWH_CORE_ENABLE | \ - HRCWH_FROM_0X00000100 | \ - HRCWH_BOOTSEQ_DISABLE | \ - HRCWH_SW_WATCHDOG_DISABLE | \ - HRCWH_ROM_LOC_LOCAL_16BIT | \ - HRCWH_BIG_ENDIAN | \ - HRCWH_LALE_NORMAL) - #define CONFIG_SYS_DDRCDR (\ DDRCDR_EN | \ DDRCDR_PZ_MAXZ | \ diff --git a/include/configs/mpc8308_p1m.h b/include/configs/mpc8308_p1m.h index fd59471370..2822aa3b9d 100644 --- a/include/configs/mpc8308_p1m.h +++ b/include/configs/mpc8308_p1m.h @@ -21,38 +21,6 @@ #define CONFIG_TSEC1 #define CONFIG_TSEC2 -/* - * Hardware Reset Configuration Word - * if CLKIN is 66.66MHz, then - * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz - * We choose the A type silicon as default, so the core is 400Mhz. - */ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_2X1 |\ - HRCWL_SVCOD_DIV_2 |\ - HRCWL_CSB_TO_CLKIN_4X1 |\ - HRCWL_CORE_TO_CSB_3X1) -/* - * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits - * in 8308's HRCWH according to the manual, but original Freescale's - * code has them and I've expirienced some problems using the board - * with BDI3000 attached when I've tried to set these bits to zero - * (UART doesn't work after the 'reset run' command). - */ -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_HOST |\ - HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0X00000100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_RL_EXT_LEGACY |\ - HRCWH_TSEC1M_IN_MII |\ - HRCWH_TSEC2M_IN_MII |\ - HRCWH_BIG_ENDIAN) - /* * System IO Config */ diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index 2520a77dd3..fd67aca207 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -22,12 +22,6 @@ /* Don't enable PCI2 on sbc834x - it doesn't exist physically. */ #undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */ -#ifdef CONFIG_PCI_33M -#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1 -#else /* 66M */ -#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1 -#endif - #define CONFIG_SYS_IMMR 0xE0000000 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ @@ -374,71 +368,6 @@ #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ -#if 1 /*528/264*/ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_1X1 |\ - HRCWL_CSB_TO_CLKIN |\ - HRCWL_VCO_1X2 |\ - HRCWL_CORE_TO_CSB_2X1) -#elif 0 /*396/132*/ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_1X1 |\ - HRCWL_CSB_TO_CLKIN |\ - HRCWL_VCO_1X4 |\ - HRCWL_CORE_TO_CSB_3X1) -#elif 0 /*264/132*/ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_1X1 |\ - HRCWL_CSB_TO_CLKIN |\ - HRCWL_VCO_1X4 |\ - HRCWL_CORE_TO_CSB_2X1) -#elif 0 /*132/132*/ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_1X1 |\ - HRCWL_CSB_TO_CLKIN |\ - HRCWL_VCO_1X4 |\ - HRCWL_CORE_TO_CSB_1X1) -#elif 0 /*264/264 */ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_1X1 |\ - HRCWL_CSB_TO_CLKIN |\ - HRCWL_VCO_1X4 |\ - HRCWL_CORE_TO_CSB_1X1) -#endif - -#if defined(CONFIG_PCI_64BIT) -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_HOST |\ - HRCWH_64_BIT_PCI |\ - HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_PCI2_ARBITER_DISABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0X00000100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_TSEC1M_IN_GMII |\ - HRCWH_TSEC2M_IN_GMII) -#else -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_HOST |\ - HRCWH_32_BIT_PCI |\ - HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_PCI2_ARBITER_ENABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0X00000100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_TSEC1M_IN_GMII |\ - HRCWH_TSEC2M_IN_GMII) -#endif - /* System IO Config */ #define CONFIG_SYS_SICRH 0 #define CONFIG_SYS_SICRL SICRL_LDP_A diff --git a/include/configs/strider.h b/include/configs/strider.h index 8c9acfba8d..ef33eaef9b 100644 --- a/include/configs/strider.h +++ b/include/configs/strider.h @@ -16,38 +16,6 @@ #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR -/* - * Hardware Reset Configuration Word - * if CLKIN is 66.66MHz, then - * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz - * We choose the A type silicon as default, so the core is 400Mhz. - */ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_2X1 |\ - HRCWL_SVCOD_DIV_2 |\ - HRCWL_CSB_TO_CLKIN_4X1 |\ - HRCWL_CORE_TO_CSB_3X1) -/* - * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits - * in 8308's HRCWH according to the manual, but original Freescale's - * code has them and I've expirienced some problems using the board - * with BDI3000 attached when I've tried to set these bits to zero - * (UART doesn't work after the 'reset run' command). - */ -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_HOST |\ - HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0XFFF00100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_RL_EXT_LEGACY |\ - HRCWH_TSEC1M_IN_MII |\ - HRCWH_TSEC2M_IN_RGMII |\ - HRCWH_BIG_ENDIAN) - /* * System IO Config */ diff --git a/include/configs/suvd3.h b/include/configs/suvd3.h index 87f7390bcc..c84c7c0f6e 100644 --- a/include/configs/suvd3.h +++ b/include/configs/suvd3.h @@ -320,28 +320,6 @@ */ #define CONFIG_SYS_SICRL SICRL_IRQ_CKS -/* - * Hardware Reset Configuration Word - */ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \ - HRCWL_DDR_TO_SCB_CLK_2X1 | \ - HRCWL_CSB_TO_CLKIN_2X1 | \ - HRCWL_CORE_TO_CSB_2_5X1 | \ - HRCWL_CE_PLL_VCO_DIV_2 | \ - HRCWL_CE_TO_PLL_1X3) - -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_AGENT | \ - HRCWH_PCI_ARBITER_DISABLE | \ - HRCWH_CORE_ENABLE | \ - HRCWH_FROM_0X00000100 | \ - HRCWH_BOOTSEQ_DISABLE | \ - HRCWH_SW_WATCHDOG_DISABLE | \ - HRCWH_ROM_LOC_LOCAL_16BIT | \ - HRCWH_BIG_ENDIAN | \ - HRCWH_LALE_NORMAL) - #define CONFIG_SYS_DDRCDR (\ DDRCDR_EN | \ DDRCDR_PZ_MAXZ | \ diff --git a/include/configs/tuge1.h b/include/configs/tuge1.h index 1cd0985dc2..8f60db3055 100644 --- a/include/configs/tuge1.h +++ b/include/configs/tuge1.h @@ -323,28 +323,6 @@ */ #define CONFIG_SYS_SICRL SICRL_IRQ_CKS -/* - * Hardware Reset Configuration Word - */ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \ - HRCWL_DDR_TO_SCB_CLK_2X1 | \ - HRCWL_CSB_TO_CLKIN_2X1 | \ - HRCWL_CORE_TO_CSB_2_5X1 | \ - HRCWL_CE_PLL_VCO_DIV_2 | \ - HRCWL_CE_TO_PLL_1X3) - -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_AGENT | \ - HRCWH_PCI_ARBITER_DISABLE | \ - HRCWH_CORE_ENABLE | \ - HRCWH_FROM_0X00000100 | \ - HRCWH_BOOTSEQ_DISABLE | \ - HRCWH_SW_WATCHDOG_DISABLE | \ - HRCWH_ROM_LOC_LOCAL_16BIT | \ - HRCWH_BIG_ENDIAN | \ - HRCWH_LALE_NORMAL) - #define CONFIG_SYS_DDRCDR (\ DDRCDR_EN | \ DDRCDR_PZ_MAXZ | \ diff --git a/include/configs/tuxx1.h b/include/configs/tuxx1.h index d476a75e3e..58c6089bec 100644 --- a/include/configs/tuxx1.h +++ b/include/configs/tuxx1.h @@ -323,28 +323,6 @@ */ #define CONFIG_SYS_SICRL SICRL_IRQ_CKS -/* - * Hardware Reset Configuration Word - */ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \ - HRCWL_DDR_TO_SCB_CLK_2X1 | \ - HRCWL_CSB_TO_CLKIN_2X1 | \ - HRCWL_CORE_TO_CSB_2_5X1 | \ - HRCWL_CE_PLL_VCO_DIV_2 | \ - HRCWL_CE_TO_PLL_1X3) - -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_AGENT | \ - HRCWH_PCI_ARBITER_DISABLE | \ - HRCWH_CORE_ENABLE | \ - HRCWH_FROM_0X00000100 | \ - HRCWH_BOOTSEQ_DISABLE | \ - HRCWH_SW_WATCHDOG_DISABLE | \ - HRCWH_ROM_LOC_LOCAL_16BIT | \ - HRCWH_BIG_ENDIAN | \ - HRCWH_LALE_NORMAL) - #define CONFIG_SYS_DDRCDR (\ DDRCDR_EN | \ DDRCDR_PZ_MAXZ | \ diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h index 2ef6f88bdf..c4bdfe574a 100644 --- a/include/configs/ve8313.h +++ b/include/configs/ve8313.h @@ -308,25 +308,6 @@ /* Initial Memory map for Linux*/ #define CONFIG_SYS_BOOTMAPSZ (256 << 20) -/* 0x64050000 */ -#define CONFIG_SYS_HRCW_LOW (\ - 0x20000000 /* reserved, must be set */ |\ - HRCWL_DDRCM |\ - HRCWL_CSB_TO_CLKIN_4X1 | \ - HRCWL_CORE_TO_CSB_2_5X1) - -/* 0xa0600004 */ -#define CONFIG_SYS_HRCW_HIGH (HRCWH_PCI_HOST | \ - HRCWH_PCI_ARBITER_ENABLE | \ - HRCWH_CORE_ENABLE | \ - HRCWH_FROM_0X00000100 | \ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT | \ - HRCWH_TSEC1M_IN_MII | \ - HRCWH_BIG_ENDIAN | \ - HRCWH_LALE_EARLY) - /* System IO Config */ #define CONFIG_SYS_SICRH (0x01000000 | \ SICRH_ETSEC2_B | \ diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h index c5086958ff..ca6233a26e 100644 --- a/include/configs/vme8349.h +++ b/include/configs/vme8349.h @@ -25,14 +25,6 @@ /* Don't enable PCI2 on vme834x - it doesn't exist physically. */ #undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */ -#define CONFIG_PCI_66M - -#ifdef CONFIG_PCI_66M -#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1 -#else -#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1 -#endif - #define CONFIG_SYS_IMMR 0xE0000000 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ @@ -292,41 +284,6 @@ #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_1X1 |\ - HRCWL_CSB_TO_CLKIN |\ - HRCWL_VCO_1X2 |\ - HRCWL_CORE_TO_CSB_2X1) - -#if defined(CONFIG_PCI_64BIT) -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_HOST |\ - HRCWH_64_BIT_PCI |\ - HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_PCI2_ARBITER_DISABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0X00000100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_TSEC1M_IN_GMII |\ - HRCWH_TSEC2M_IN_GMII) -#else -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_HOST |\ - HRCWH_32_BIT_PCI |\ - HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_PCI2_ARBITER_ENABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0X00000100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_TSEC1M_IN_GMII |\ - HRCWH_TSEC2M_IN_GMII) -#endif - /* System IO Config */ #define CONFIG_SYS_SICRH 0 #define CONFIG_SYS_SICRL SICRL_LDP_A From d0c625728bbf769dc17472ac6072fc353be327e8 Mon Sep 17 00:00:00 2001 From: Mario Six Date: Mon, 21 Jan 2019 09:17:55 +0100 Subject: [PATCH 32/86] mpc83xx: pcie: Read the clock from registers The MPC83xx DM timer driver disables arch.pciexp*_clk, and uses clk_get_rate instead. But the legacy MPC83xx PCIe driver still uses arch.pciexp*_clk for the clock. Hence, read the PCIe clock from the registers in the legacy MPC83xx PCIe driver. Signed-off-by: Mario Six --- arch/powerpc/cpu/mpc83xx/pcie.c | 39 ++++++++++++++++++++++++++++++--- 1 file changed, 36 insertions(+), 3 deletions(-) diff --git a/arch/powerpc/cpu/mpc83xx/pcie.c b/arch/powerpc/cpu/mpc83xx/pcie.c index d3f979f3c4..b500ddd3f3 100644 --- a/arch/powerpc/cpu/mpc83xx/pcie.c +++ b/arch/powerpc/cpu/mpc83xx/pcie.c @@ -174,6 +174,41 @@ static void mpc83xx_pcie_register_hose(int bus, struct pci_region *reg, #endif /* CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES */ +int get_pcie_clk(int index) +{ + volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; + u32 pci_sync_in; + u8 spmf; + u8 clkin_div; + u32 sccr; + u32 csb_clk; + u32 testval; + + clkin_div = ((im->clk.spmr & SPMR_CKID) >> SPMR_CKID_SHIFT); + sccr = im->clk.sccr; + pci_sync_in = CONFIG_SYS_CLK_FREQ / (1 + clkin_div); + spmf = (im->clk.spmr & SPMR_SPMF) >> SPMR_SPMF_SHIFT; + csb_clk = pci_sync_in * (1 + clkin_div) * spmf; + + if (index) + testval = (sccr & SCCR_PCIEXP2CM) >> SCCR_PCIEXP2CM_SHIFT; + else + testval = (sccr & SCCR_PCIEXP1CM) >> SCCR_PCIEXP1CM_SHIFT; + + switch (testval) { + case 0: + return 0; + case 1: + return csb_clk; + case 2: + return csb_clk / 2; + case 3: + return csb_clk / 3; + } + + return 0; +} + static void mpc83xx_pcie_init_bus(int bus, struct pci_region *reg) { immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; @@ -269,11 +304,9 @@ static void mpc83xx_pcie_init_bus(int bus, struct pci_region *reg) /* Hose configure header is memory-mapped */ hose_cfg_base = (void *)pex; - get_clocks(); /* Configure the PCIE controller core clock ratio */ out_le32(hose_cfg_base + PEX_GCLK_RATIO, - (((bus ? gd->arch.pciexp2_clk : gd->arch.pciexp1_clk) - / 1000000) * 16) / 333); + ((get_pcie_clk(bus) / 1000000) * 16) / 333); udelay(1000000); /* Do Type 1 bridge configuration */ From 93de25308dac01dd1a6ff5891e13ea849041a88a Mon Sep 17 00:00:00 2001 From: Mario Six Date: Mon, 21 Jan 2019 09:17:56 +0100 Subject: [PATCH 33/86] powerpc: Migrate HIGH_BATS to Kconfig Migrate the CONFIG_HIGH_BATS variable to Kconfig. Signed-off-by: Mario Six --- arch/powerpc/Kconfig | 6 ++++++ configs/MPC8313ERDB_33_defconfig | 1 + configs/MPC8313ERDB_66_defconfig | 1 + configs/MPC8313ERDB_NAND_33_defconfig | 1 + configs/MPC8313ERDB_NAND_66_defconfig | 1 + configs/MPC8315ERDB_defconfig | 1 + configs/MPC8323ERDB_defconfig | 1 + configs/MPC832XEMDS_ATM_defconfig | 1 + configs/MPC832XEMDS_HOST_33_defconfig | 1 + configs/MPC832XEMDS_HOST_66_defconfig | 1 + configs/MPC832XEMDS_SLAVE_defconfig | 1 + configs/MPC832XEMDS_defconfig | 1 + configs/MPC8349EMDS_PCI64_defconfig | 1 + configs/MPC8349EMDS_SDRAM_defconfig | 1 + configs/MPC8349EMDS_SLAVE_defconfig | 1 + configs/MPC8349EMDS_defconfig | 1 + configs/MPC8349ITXGP_defconfig | 1 + configs/MPC8349ITX_LOWBOOT_defconfig | 1 + configs/MPC8349ITX_defconfig | 1 + configs/MPC837XEMDS_HOST_defconfig | 1 + configs/MPC837XEMDS_defconfig | 1 + configs/MPC837XERDB_defconfig | 1 + configs/MPC8610HPCD_defconfig | 1 + configs/MPC8641HPCN_36BIT_defconfig | 1 + configs/MPC8641HPCN_defconfig | 1 + configs/TQM834x_defconfig | 1 + configs/caddy2_defconfig | 1 + configs/ids8313_defconfig | 1 + configs/kmcoge5ne_defconfig | 1 + configs/kmopti2_defconfig | 1 + configs/kmsupx5_defconfig | 1 + configs/kmtegr1_defconfig | 1 + configs/kmtepr2_defconfig | 1 + configs/kmvect1_defconfig | 1 + configs/sbc8349_PCI_33_defconfig | 1 + configs/sbc8349_PCI_66_defconfig | 1 + configs/sbc8349_defconfig | 1 + configs/sbc8641d_defconfig | 1 + configs/suvd3_defconfig | 1 + configs/tuge1_defconfig | 1 + configs/tuxx1_defconfig | 1 + configs/ve8313_defconfig | 1 + configs/vme8349_defconfig | 1 + configs/xpedite517x_defconfig | 1 + include/configs/MPC8313ERDB_NAND.h | 2 -- include/configs/MPC8313ERDB_NOR.h | 2 -- include/configs/MPC8315ERDB.h | 1 - include/configs/MPC8323ERDB.h | 1 - include/configs/MPC832XEMDS.h | 2 -- include/configs/MPC8349EMDS.h | 1 - include/configs/MPC8349EMDS_SDRAM.h | 1 - include/configs/MPC8349ITX.h | 1 - include/configs/MPC837XEMDS.h | 1 - include/configs/MPC837XERDB.h | 2 -- include/configs/MPC8610HPCD.h | 1 - include/configs/MPC8641HPCN.h | 1 - include/configs/TQM834x.h | 2 -- include/configs/caddy2.h | 2 -- include/configs/ids8313.h | 1 - include/configs/kmcoge5ne.h | 2 -- include/configs/kmeter1.h | 2 -- include/configs/kmopti2.h | 2 -- include/configs/kmsupx5.h | 2 -- include/configs/kmtegr1.h | 2 -- include/configs/kmtepr2.h | 2 -- include/configs/kmvect1.h | 2 -- include/configs/sbc8349.h | 2 -- include/configs/sbc8641d.h | 1 - include/configs/suvd3.h | 2 -- include/configs/tuge1.h | 2 -- include/configs/tuxx1.h | 2 -- include/configs/ve8313.h | 2 -- include/configs/vme8349.h | 2 -- include/configs/xpedite517x.h | 1 - scripts/config_whitelist.txt | 1 - 75 files changed, 49 insertions(+), 50 deletions(-) diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index 0b1629ba62..c2c577f60c 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig @@ -39,6 +39,12 @@ config MPC8xx endchoice +config HIGH_BATS + bool "Enable high BAT registers" + help + Enable BATs (block address translation registers) 4-7 on machines + that support them. + source "arch/powerpc/cpu/mpc83xx/Kconfig" source "arch/powerpc/cpu/mpc85xx/Kconfig" source "arch/powerpc/cpu/mpc86xx/Kconfig" diff --git a/configs/MPC8313ERDB_33_defconfig b/configs/MPC8313ERDB_33_defconfig index c99d739996..641c6c8545 100644 --- a/configs/MPC8313ERDB_33_defconfig +++ b/configs/MPC8313ERDB_33_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_CLK_FREQ=33333333 CONFIG_MPC83xx=y +CONFIG_HIGH_BATS=y CONFIG_TARGET_MPC8313ERDB_NOR=y CONFIG_SYSTEM_PLL_FACTOR_5_1=y CONFIG_CORE_PLL_RATIO_2_1=y diff --git a/configs/MPC8313ERDB_66_defconfig b/configs/MPC8313ERDB_66_defconfig index c1eb49af7b..b1a4bcbc53 100644 --- a/configs/MPC8313ERDB_66_defconfig +++ b/configs/MPC8313ERDB_66_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_CLK_FREQ=66666667 CONFIG_MPC83xx=y +CONFIG_HIGH_BATS=y CONFIG_TARGET_MPC8313ERDB_NOR=y CONFIG_CORE_PLL_RATIO_2_1=y CONFIG_PCI_HOST_MODE_ENABLE=y diff --git a/configs/MPC8313ERDB_NAND_33_defconfig b/configs/MPC8313ERDB_NAND_33_defconfig index adec951b72..306f4cc80c 100644 --- a/configs/MPC8313ERDB_NAND_33_defconfig +++ b/configs/MPC8313ERDB_NAND_33_defconfig @@ -4,6 +4,7 @@ CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL=y CONFIG_SYS_CLK_FREQ=33333333 CONFIG_MPC83xx=y +CONFIG_HIGH_BATS=y CONFIG_TARGET_MPC8313ERDB_NAND=y CONFIG_SYSTEM_PLL_FACTOR_5_1=y CONFIG_CORE_PLL_RATIO_2_1=y diff --git a/configs/MPC8313ERDB_NAND_66_defconfig b/configs/MPC8313ERDB_NAND_66_defconfig index 6c75faacb0..951ef72445 100644 --- a/configs/MPC8313ERDB_NAND_66_defconfig +++ b/configs/MPC8313ERDB_NAND_66_defconfig @@ -4,6 +4,7 @@ CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL=y CONFIG_SYS_CLK_FREQ=66666667 CONFIG_MPC83xx=y +CONFIG_HIGH_BATS=y CONFIG_TARGET_MPC8313ERDB_NAND=y CONFIG_CORE_PLL_RATIO_2_1=y CONFIG_PCI_HOST_MODE_ENABLE=y diff --git a/configs/MPC8315ERDB_defconfig b/configs/MPC8315ERDB_defconfig index cb3f206038..149e71c310 100644 --- a/configs/MPC8315ERDB_defconfig +++ b/configs/MPC8315ERDB_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_CLK_FREQ=66666667 CONFIG_MPC83xx=y +CONFIG_HIGH_BATS=y CONFIG_TARGET_MPC8315ERDB=y CONFIG_SYSTEM_PLL_VCO_DIV_2=y CONFIG_CORE_PLL_RATIO_3_1=y diff --git a/configs/MPC8323ERDB_defconfig b/configs/MPC8323ERDB_defconfig index cdc559a581..49e690e88b 100644 --- a/configs/MPC8323ERDB_defconfig +++ b/configs/MPC8323ERDB_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_CLK_FREQ=66666667 CONFIG_MPC83xx=y +CONFIG_HIGH_BATS=y CONFIG_TARGET_MPC8323ERDB=y CONFIG_CORE_PLL_RATIO_25_1=y CONFIG_QUICC_MULT_FACTOR_3=y diff --git a/configs/MPC832XEMDS_ATM_defconfig b/configs/MPC832XEMDS_ATM_defconfig index 5f14da422d..323b368f9e 100644 --- a/configs/MPC832XEMDS_ATM_defconfig +++ b/configs/MPC832XEMDS_ATM_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y +CONFIG_HIGH_BATS=y CONFIG_TARGET_MPC832XEMDS=y CONFIG_CORE_PLL_RATIO_2_1=y CONFIG_QUICC_MULT_FACTOR_3=y diff --git a/configs/MPC832XEMDS_HOST_33_defconfig b/configs/MPC832XEMDS_HOST_33_defconfig index 41245a3fc9..a13dcfb91d 100644 --- a/configs/MPC832XEMDS_HOST_33_defconfig +++ b/configs/MPC832XEMDS_HOST_33_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y +CONFIG_HIGH_BATS=y CONFIG_TARGET_MPC832XEMDS=y CONFIG_CORE_PLL_RATIO_2_1=y CONFIG_QUICC_MULT_FACTOR_3=y diff --git a/configs/MPC832XEMDS_HOST_66_defconfig b/configs/MPC832XEMDS_HOST_66_defconfig index ea90bea77d..2a4ff9a3e1 100644 --- a/configs/MPC832XEMDS_HOST_66_defconfig +++ b/configs/MPC832XEMDS_HOST_66_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y +CONFIG_HIGH_BATS=y CONFIG_TARGET_MPC832XEMDS=y CONFIG_CORE_PLL_RATIO_2_1=y CONFIG_QUICC_MULT_FACTOR_3=y diff --git a/configs/MPC832XEMDS_SLAVE_defconfig b/configs/MPC832XEMDS_SLAVE_defconfig index 4944694048..e7ea39a236 100644 --- a/configs/MPC832XEMDS_SLAVE_defconfig +++ b/configs/MPC832XEMDS_SLAVE_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y +CONFIG_HIGH_BATS=y CONFIG_TARGET_MPC832XEMDS=y CONFIG_CORE_PLL_RATIO_2_1=y CONFIG_QUICC_MULT_FACTOR_3=y diff --git a/configs/MPC832XEMDS_defconfig b/configs/MPC832XEMDS_defconfig index d04292a388..bffc55b917 100644 --- a/configs/MPC832XEMDS_defconfig +++ b/configs/MPC832XEMDS_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y +CONFIG_HIGH_BATS=y CONFIG_TARGET_MPC832XEMDS=y CONFIG_CORE_PLL_RATIO_2_1=y CONFIG_QUICC_MULT_FACTOR_3=y diff --git a/configs/MPC8349EMDS_PCI64_defconfig b/configs/MPC8349EMDS_PCI64_defconfig index db0698237b..11bce06a09 100644 --- a/configs/MPC8349EMDS_PCI64_defconfig +++ b/configs/MPC8349EMDS_PCI64_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y +CONFIG_HIGH_BATS=y CONFIG_TARGET_MPC8349EMDS=y CONFIG_DDR_MC_CLOCK_MODE_1_1=y CONFIG_SYSTEM_PLL_FACTOR_4_1=y diff --git a/configs/MPC8349EMDS_SDRAM_defconfig b/configs/MPC8349EMDS_SDRAM_defconfig index 8465cc6800..6b571b0368 100644 --- a/configs/MPC8349EMDS_SDRAM_defconfig +++ b/configs/MPC8349EMDS_SDRAM_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y +CONFIG_HIGH_BATS=y CONFIG_TARGET_MPC8349EMDS_SDRAM=y CONFIG_DDR_MC_CLOCK_MODE_1_1=y CONFIG_SYSTEM_PLL_FACTOR_4_1=y diff --git a/configs/MPC8349EMDS_SLAVE_defconfig b/configs/MPC8349EMDS_SLAVE_defconfig index b0cb93bf7f..87892c3d67 100644 --- a/configs/MPC8349EMDS_SLAVE_defconfig +++ b/configs/MPC8349EMDS_SLAVE_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_CLK_FREQ=66666666 CONFIG_MPC83xx=y +CONFIG_HIGH_BATS=y CONFIG_TARGET_MPC8349EMDS=y CONFIG_DDR_MC_CLOCK_MODE_1_1=y CONFIG_SYSTEM_PLL_FACTOR_4_1=y diff --git a/configs/MPC8349EMDS_defconfig b/configs/MPC8349EMDS_defconfig index ecded68c05..40633d19be 100644 --- a/configs/MPC8349EMDS_defconfig +++ b/configs/MPC8349EMDS_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y +CONFIG_HIGH_BATS=y CONFIG_TARGET_MPC8349EMDS=y CONFIG_DDR_MC_CLOCK_MODE_1_1=y CONFIG_SYSTEM_PLL_FACTOR_4_1=y diff --git a/configs/MPC8349ITXGP_defconfig b/configs/MPC8349ITXGP_defconfig index 13312e04aa..9e466b1bd1 100644 --- a/configs/MPC8349ITXGP_defconfig +++ b/configs/MPC8349ITXGP_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_CLK_FREQ=66666666 CONFIG_MPC83xx=y +CONFIG_HIGH_BATS=y CONFIG_TARGET_MPC8349ITX=y CONFIG_DDR_MC_CLOCK_MODE_1_1=y CONFIG_SYSTEM_PLL_FACTOR_4_1=y diff --git a/configs/MPC8349ITX_LOWBOOT_defconfig b/configs/MPC8349ITX_LOWBOOT_defconfig index 221edf9116..3a61235736 100644 --- a/configs/MPC8349ITX_LOWBOOT_defconfig +++ b/configs/MPC8349ITX_LOWBOOT_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_CLK_FREQ=66666666 CONFIG_MPC83xx=y +CONFIG_HIGH_BATS=y CONFIG_TARGET_MPC8349ITX=y CONFIG_DDR_MC_CLOCK_MODE_1_1=y CONFIG_SYSTEM_PLL_FACTOR_4_1=y diff --git a/configs/MPC8349ITX_defconfig b/configs/MPC8349ITX_defconfig index 46c9085852..ed9bd83302 100644 --- a/configs/MPC8349ITX_defconfig +++ b/configs/MPC8349ITX_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFEF00000 CONFIG_SYS_CLK_FREQ=66666666 CONFIG_MPC83xx=y +CONFIG_HIGH_BATS=y CONFIG_TARGET_MPC8349ITX=y CONFIG_DDR_MC_CLOCK_MODE_1_1=y CONFIG_SYSTEM_PLL_FACTOR_4_1=y diff --git a/configs/MPC837XEMDS_HOST_defconfig b/configs/MPC837XEMDS_HOST_defconfig index 1b88b599f4..73ba7dc632 100644 --- a/configs/MPC837XEMDS_HOST_defconfig +++ b/configs/MPC837XEMDS_HOST_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y +CONFIG_HIGH_BATS=y CONFIG_TARGET_MPC837XEMDS=y CONFIG_DDR_MC_CLOCK_MODE_1_1=y CONFIG_SYSTEM_PLL_FACTOR_6_1=y diff --git a/configs/MPC837XEMDS_defconfig b/configs/MPC837XEMDS_defconfig index da908c762f..cf0694f3b5 100644 --- a/configs/MPC837XEMDS_defconfig +++ b/configs/MPC837XEMDS_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y +CONFIG_HIGH_BATS=y CONFIG_TARGET_MPC837XEMDS=y CONFIG_DDR_MC_CLOCK_MODE_1_1=y CONFIG_SYSTEM_PLL_FACTOR_6_1=y diff --git a/configs/MPC837XERDB_defconfig b/configs/MPC837XERDB_defconfig index 4b9a7deb94..03fd7b70ba 100644 --- a/configs/MPC837XERDB_defconfig +++ b/configs/MPC837XERDB_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_CLK_FREQ=66666667 CONFIG_MPC83xx=y +CONFIG_HIGH_BATS=y CONFIG_TARGET_MPC837XERDB=y CONFIG_DDR_MC_CLOCK_MODE_1_1=y CONFIG_SYSTEM_PLL_FACTOR_5_1=y diff --git a/configs/MPC8610HPCD_defconfig b/configs/MPC8610HPCD_defconfig index cfdfa9011f..80ea441aa3 100644 --- a/configs/MPC8610HPCD_defconfig +++ b/configs/MPC8610HPCD_defconfig @@ -1,6 +1,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xfff00000 CONFIG_MPC86xx=y +CONFIG_HIGH_BATS=y CONFIG_TARGET_MPC8610HPCD=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/configs/MPC8641HPCN_36BIT_defconfig b/configs/MPC8641HPCN_36BIT_defconfig index 4b924c08b3..81901f7a28 100644 --- a/configs/MPC8641HPCN_36BIT_defconfig +++ b/configs/MPC8641HPCN_36BIT_defconfig @@ -1,6 +1,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xeff00000 CONFIG_MPC86xx=y +CONFIG_HIGH_BATS=y CONFIG_TARGET_MPC8641HPCN=y CONFIG_PHYS_64BIT=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/MPC8641HPCN_defconfig b/configs/MPC8641HPCN_defconfig index 52fba9750d..497d398c83 100644 --- a/configs/MPC8641HPCN_defconfig +++ b/configs/MPC8641HPCN_defconfig @@ -1,6 +1,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xeff00000 CONFIG_MPC86xx=y +CONFIG_HIGH_BATS=y CONFIG_TARGET_MPC8641HPCN=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/configs/TQM834x_defconfig b/configs/TQM834x_defconfig index 1e873c3e01..c746afd1fd 100644 --- a/configs/TQM834x_defconfig +++ b/configs/TQM834x_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0x80000000 CONFIG_SYS_CLK_FREQ=66666000 CONFIG_MPC83xx=y +CONFIG_HIGH_BATS=y CONFIG_TARGET_TQM834X=y CONFIG_DDR_MC_CLOCK_MODE_1_1=y CONFIG_SYSTEM_PLL_FACTOR_4_1=y diff --git a/configs/caddy2_defconfig b/configs/caddy2_defconfig index 29ec5e0afc..b52ea881ce 100644 --- a/configs/caddy2_defconfig +++ b/configs/caddy2_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFFF00000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y +CONFIG_HIGH_BATS=y CONFIG_TARGET_CADDY2=y CONFIG_DDR_MC_CLOCK_MODE_1_1=y CONFIG_SYSTEM_PLL_FACTOR_4_1=y diff --git a/configs/ids8313_defconfig b/configs/ids8313_defconfig index 482b51ef87..a8619ef621 100644 --- a/configs/ids8313_defconfig +++ b/configs/ids8313_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFFF00000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y +CONFIG_HIGH_BATS=y CONFIG_TARGET_IDS8313=y CONFIG_CORE_PLL_RATIO_2_1=y CONFIG_PCI_HOST_MODE_ENABLE=y diff --git a/configs/kmcoge5ne_defconfig b/configs/kmcoge5ne_defconfig index 7f22fa3b15..03437f7cb8 100644 --- a/configs/kmcoge5ne_defconfig +++ b/configs/kmcoge5ne_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xF0000000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y +CONFIG_HIGH_BATS=y CONFIG_TARGET_KMCOGE5NE=y CONFIG_DDR_MC_CLOCK_MODE_1_1=y CONFIG_SYSTEM_PLL_VCO_DIV_4=y diff --git a/configs/kmopti2_defconfig b/configs/kmopti2_defconfig index 6486c6a59c..ba489eeb6a 100644 --- a/configs/kmopti2_defconfig +++ b/configs/kmopti2_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xF0000000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y +CONFIG_HIGH_BATS=y CONFIG_TARGET_KMOPTI2=y CONFIG_CORE_PLL_RATIO_25_1=y CONFIG_QUICC_MULT_FACTOR_3=y diff --git a/configs/kmsupx5_defconfig b/configs/kmsupx5_defconfig index 20df9f3fa4..f39bca4fbd 100644 --- a/configs/kmsupx5_defconfig +++ b/configs/kmsupx5_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xF0000000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y +CONFIG_HIGH_BATS=y CONFIG_TARGET_KMSUPX5=y CONFIG_CORE_PLL_RATIO_25_1=y CONFIG_QUICC_MULT_FACTOR_3=y diff --git a/configs/kmtegr1_defconfig b/configs/kmtegr1_defconfig index c1d30cdde8..3e7b2f73fd 100644 --- a/configs/kmtegr1_defconfig +++ b/configs/kmtegr1_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xF0000000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y +CONFIG_HIGH_BATS=y CONFIG_TARGET_KMTEGR1=y CONFIG_SYSTEM_PLL_VCO_DIV_2=y CONFIG_CORE_PLL_RATIO_2_1=y diff --git a/configs/kmtepr2_defconfig b/configs/kmtepr2_defconfig index ed8bc32d65..0f32283e9d 100644 --- a/configs/kmtepr2_defconfig +++ b/configs/kmtepr2_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xF0000000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y +CONFIG_HIGH_BATS=y CONFIG_TARGET_KMTEPR2=y CONFIG_CORE_PLL_RATIO_25_1=y CONFIG_QUICC_MULT_FACTOR_3=y diff --git a/configs/kmvect1_defconfig b/configs/kmvect1_defconfig index 66b3cd39b5..ec3ff28793 100644 --- a/configs/kmvect1_defconfig +++ b/configs/kmvect1_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xF0000000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y +CONFIG_HIGH_BATS=y CONFIG_TARGET_KMVECT1=y CONFIG_SYSTEM_PLL_VCO_DIV_2=y CONFIG_CORE_PLL_RATIO_2_1=y diff --git a/configs/sbc8349_PCI_33_defconfig b/configs/sbc8349_PCI_33_defconfig index 7fc0edde70..47feb5ae36 100644 --- a/configs/sbc8349_PCI_33_defconfig +++ b/configs/sbc8349_PCI_33_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFF800000 CONFIG_SYS_CLK_FREQ=33000000 CONFIG_MPC83xx=y +CONFIG_HIGH_BATS=y CONFIG_TARGET_SBC8349=y CONFIG_DDR_MC_CLOCK_MODE_1_1=y CONFIG_SYSTEM_PLL_FACTOR_8_1=y diff --git a/configs/sbc8349_PCI_66_defconfig b/configs/sbc8349_PCI_66_defconfig index 80cdd644f7..019341691f 100644 --- a/configs/sbc8349_PCI_66_defconfig +++ b/configs/sbc8349_PCI_66_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFF800000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y +CONFIG_HIGH_BATS=y CONFIG_TARGET_SBC8349=y CONFIG_DDR_MC_CLOCK_MODE_1_1=y CONFIG_SYSTEM_PLL_FACTOR_4_1=y diff --git a/configs/sbc8349_defconfig b/configs/sbc8349_defconfig index 1141b791e7..f7c3de8e9e 100644 --- a/configs/sbc8349_defconfig +++ b/configs/sbc8349_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFF800000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y +CONFIG_HIGH_BATS=y CONFIG_TARGET_SBC8349=y CONFIG_DDR_MC_CLOCK_MODE_1_1=y CONFIG_SYSTEM_PLL_FACTOR_4_1=y diff --git a/configs/sbc8641d_defconfig b/configs/sbc8641d_defconfig index d1ffea5afb..47cec18a95 100644 --- a/configs/sbc8641d_defconfig +++ b/configs/sbc8641d_defconfig @@ -1,6 +1,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xfff00000 CONFIG_MPC86xx=y +CONFIG_HIGH_BATS=y CONFIG_TARGET_SBC8641D=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/configs/suvd3_defconfig b/configs/suvd3_defconfig index 9b36aa0fa4..b6f17d2f29 100644 --- a/configs/suvd3_defconfig +++ b/configs/suvd3_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xF0000000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y +CONFIG_HIGH_BATS=y CONFIG_TARGET_SUVD3=y CONFIG_CORE_PLL_RATIO_25_1=y CONFIG_QUICC_MULT_FACTOR_3=y diff --git a/configs/tuge1_defconfig b/configs/tuge1_defconfig index 3467b7ebd9..445b89d483 100644 --- a/configs/tuge1_defconfig +++ b/configs/tuge1_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xF0000000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y +CONFIG_HIGH_BATS=y CONFIG_TARGET_TUGE1=y CONFIG_CORE_PLL_RATIO_25_1=y CONFIG_QUICC_MULT_FACTOR_3=y diff --git a/configs/tuxx1_defconfig b/configs/tuxx1_defconfig index f67e3b8728..d7b0a94ada 100644 --- a/configs/tuxx1_defconfig +++ b/configs/tuxx1_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xF0000000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y +CONFIG_HIGH_BATS=y CONFIG_TARGET_TUXX1=y CONFIG_CORE_PLL_RATIO_25_1=y CONFIG_QUICC_MULT_FACTOR_3=y diff --git a/configs/ve8313_defconfig b/configs/ve8313_defconfig index f09c83d856..52a51cc5bb 100644 --- a/configs/ve8313_defconfig +++ b/configs/ve8313_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_CLK_FREQ=32000000 CONFIG_MPC83xx=y +CONFIG_HIGH_BATS=y CONFIG_TARGET_VE8313=y CONFIG_SYSTEM_PLL_FACTOR_4_1=y CONFIG_CORE_PLL_RATIO_25_1=y diff --git a/configs/vme8349_defconfig b/configs/vme8349_defconfig index 271e690535..3f1f5c069b 100644 --- a/configs/vme8349_defconfig +++ b/configs/vme8349_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFFF00000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y +CONFIG_HIGH_BATS=y CONFIG_TARGET_VME8349=y CONFIG_DDR_MC_CLOCK_MODE_1_1=y CONFIG_SYSTEM_PLL_FACTOR_4_1=y diff --git a/configs/xpedite517x_defconfig b/configs/xpedite517x_defconfig index d2d8313da6..cad95d338e 100644 --- a/configs/xpedite517x_defconfig +++ b/configs/xpedite517x_defconfig @@ -1,6 +1,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xfff00000 CONFIG_MPC86xx=y +CONFIG_HIGH_BATS=y CONFIG_TARGET_XPEDITE517X=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/include/configs/MPC8313ERDB_NAND.h b/include/configs/MPC8313ERDB_NAND.h index e14652a626..e3bcc63e13 100644 --- a/include/configs/MPC8313ERDB_NAND.h +++ b/include/configs/MPC8313ERDB_NAND.h @@ -438,8 +438,6 @@ #define CONFIG_SYS_HID2 HID2_HBE -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - /* DDR @ 0x00000000 */ #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW) #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ diff --git a/include/configs/MPC8313ERDB_NOR.h b/include/configs/MPC8313ERDB_NOR.h index b550a8daf8..af2432b12d 100644 --- a/include/configs/MPC8313ERDB_NOR.h +++ b/include/configs/MPC8313ERDB_NOR.h @@ -412,8 +412,6 @@ #define CONFIG_SYS_HID2 HID2_HBE -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - /* DDR @ 0x00000000 */ #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW) #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index 446c98bad1..d2f9309cd6 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -404,7 +404,6 @@ /* * MMU Setup */ -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ /* DDR: cache cacheable */ #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index 7dbbb4e0fb..37f173ef74 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -300,7 +300,6 @@ /* * MMU Setup */ -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ /* DDR: cache cacheable */ #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index dad8407f67..d8cadde0e0 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -364,8 +364,6 @@ * MMU Setup */ -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - /* DDR: cache cacheable */ #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ | BATL_PP_RW \ diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 2159454061..d70e477f80 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -381,7 +381,6 @@ HID0_ENABLE_ADDRESS_BROADCAST) */ #define CONFIG_SYS_HID2 HID2_HBE -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ /* DDR @ 0x00000000 */ #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ diff --git a/include/configs/MPC8349EMDS_SDRAM.h b/include/configs/MPC8349EMDS_SDRAM.h index a19e732d8a..286654066c 100644 --- a/include/configs/MPC8349EMDS_SDRAM.h +++ b/include/configs/MPC8349EMDS_SDRAM.h @@ -453,7 +453,6 @@ HID0_ENABLE_ADDRESS_BROADCAST) */ #define CONFIG_SYS_HID2 HID2_HBE -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ /* DDR @ 0x00000000 */ #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index 6860c72794..e7031e94fd 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -481,7 +481,6 @@ boards, we say we have two, but don't display a message if we find only one. */ #define CONFIG_SYS_HID0_FINAL HID0_ENABLE_INSTRUCTION_CACHE #define CONFIG_SYS_HID2 HID2_HBE -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ /* DDR */ #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index 8c562fde2e..3473ca6102 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -423,7 +423,6 @@ extern int board_pci_host_broken(void); /* * MMU Setup */ -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ /* DDR: cache cacheable */ #define CONFIG_SYS_SDRAM_LOWER CONFIG_SYS_SDRAM_BASE diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index 055a30e24f..9ddd2af0d9 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -439,8 +439,6 @@ * MMU Setup */ -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - /* DDR: cache cacheable */ #define CONFIG_SYS_SDRAM_LOWER CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_SDRAM_UPPER (CONFIG_SYS_SDRAM_BASE + 0x10000000) diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h index b534d4758b..04f55e3990 100644 --- a/include/configs/MPC8610HPCD.h +++ b/include/configs/MPC8610HPCD.h @@ -43,7 +43,6 @@ #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ #define CONFIG_BAT_RW 1 /* Use common BAT rw code */ -#define CONFIG_HIGH_BATS 1 /* High BATs supported & enabled */ #define CONFIG_ALTIVEC 1 /* diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index 9318b190ae..8c01891e26 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -45,7 +45,6 @@ #define CONFIG_ENV_OVERWRITE #define CONFIG_BAT_RW 1 /* Use common BAT rw code */ -#define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */ #define CONFIG_SYS_NUM_ADDR_MAP 8 /* Number of addr map slots = 8 dbats */ #define CONFIG_ALTIVEC 1 diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index be1c2893f1..c27a04ace9 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -270,8 +270,6 @@ HID0_ENABLE_INSTRUCTION_CACHE) #define CONFIG_SYS_HID2 HID2_HBE -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - /* DDR 0 - 512M */ #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ | BATL_PP_RW \ diff --git a/include/configs/caddy2.h b/include/configs/caddy2.h index 5e88bd7eda..007ded0299 100644 --- a/include/configs/caddy2.h +++ b/include/configs/caddy2.h @@ -302,8 +302,6 @@ #define CONFIG_SYS_GPIO2_DIR 0x78900000 #define CONFIG_SYS_GPIO2_DAT 0x70100000 -#define CONFIG_HIGH_BATS /* High BATs supported */ - /* DDR @ 0x00000000 */ #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ BATL_MEMCOHERENCE) diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h index 4e5927ed70..ac151dccba 100644 --- a/include/configs/ids8313.h +++ b/include/configs/ids8313.h @@ -285,7 +285,6 @@ /* * BAT's */ -#define CONFIG_HIGH_BATS /* DDR @ 0x00000000 */ #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE |\ diff --git a/include/configs/kmcoge5ne.h b/include/configs/kmcoge5ne.h index 7e579db6ae..a45ea521ac 100644 --- a/include/configs/kmcoge5ne.h +++ b/include/configs/kmcoge5ne.h @@ -238,8 +238,6 @@ * MMU Setup */ -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - /* DDR: cache cacheable */ #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h index 3a98f9497b..2d7b3106dd 100644 --- a/include/configs/kmeter1.h +++ b/include/configs/kmeter1.h @@ -224,8 +224,6 @@ * MMU Setup */ -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - /* DDR: cache cacheable */ #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) diff --git a/include/configs/kmopti2.h b/include/configs/kmopti2.h index 4494475486..2f19b2e9ef 100644 --- a/include/configs/kmopti2.h +++ b/include/configs/kmopti2.h @@ -243,8 +243,6 @@ * MMU Setup */ -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - /* DDR: cache cacheable */ #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) diff --git a/include/configs/kmsupx5.h b/include/configs/kmsupx5.h index 7c008f8516..ae997a71f6 100644 --- a/include/configs/kmsupx5.h +++ b/include/configs/kmsupx5.h @@ -243,8 +243,6 @@ * MMU Setup */ -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - /* DDR: cache cacheable */ #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) diff --git a/include/configs/kmtegr1.h b/include/configs/kmtegr1.h index 95b16ca585..2e4e2a3b5f 100644 --- a/include/configs/kmtegr1.h +++ b/include/configs/kmtegr1.h @@ -247,8 +247,6 @@ * MMU Setup */ -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - /* DDR: cache cacheable */ #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) diff --git a/include/configs/kmtepr2.h b/include/configs/kmtepr2.h index 5191f2c4b0..f998b95f93 100644 --- a/include/configs/kmtepr2.h +++ b/include/configs/kmtepr2.h @@ -243,8 +243,6 @@ * MMU Setup */ -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - /* DDR: cache cacheable */ #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) diff --git a/include/configs/kmvect1.h b/include/configs/kmvect1.h index cc88f071ec..f4da14a616 100644 --- a/include/configs/kmvect1.h +++ b/include/configs/kmvect1.h @@ -239,8 +239,6 @@ * MMU Setup */ -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - /* DDR: cache cacheable */ #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index fd67aca207..d6f2813e50 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -383,8 +383,6 @@ #define CONFIG_SYS_HID2 HID2_HBE -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - /* DDR @ 0x00000000 */ #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ | BATL_PP_RW \ diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h index e9e264b40b..d1535b6fac 100644 --- a/include/configs/sbc8641d.h +++ b/include/configs/sbc8641d.h @@ -45,7 +45,6 @@ #define CONFIG_ENV_OVERWRITE #define CONFIG_BAT_RW 1 /* Use common BAT rw code */ -#define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */ #undef CONFIG_SPD_EEPROM /* Do not use SPD EEPROM for DDR setup*/ #undef CONFIG_DDR_ECC /* only for ECC DDR module */ diff --git a/include/configs/suvd3.h b/include/configs/suvd3.h index c84c7c0f6e..4cc9f13d37 100644 --- a/include/configs/suvd3.h +++ b/include/configs/suvd3.h @@ -240,8 +240,6 @@ * MMU Setup */ -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - /* DDR: cache cacheable */ #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) diff --git a/include/configs/tuge1.h b/include/configs/tuge1.h index 8f60db3055..8d254689cf 100644 --- a/include/configs/tuge1.h +++ b/include/configs/tuge1.h @@ -243,8 +243,6 @@ * MMU Setup */ -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - /* DDR: cache cacheable */ #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) diff --git a/include/configs/tuxx1.h b/include/configs/tuxx1.h index 58c6089bec..63fbf1b45c 100644 --- a/include/configs/tuxx1.h +++ b/include/configs/tuxx1.h @@ -243,8 +243,6 @@ * MMU Setup */ -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - /* DDR: cache cacheable */ #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h index c4bdfe574a..b15cd218f2 100644 --- a/include/configs/ve8313.h +++ b/include/configs/ve8313.h @@ -333,8 +333,6 @@ #define CONFIG_SYS_HID2 HID2_HBE -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - /* DDR @ 0x00000000 */ #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW) #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h index ca6233a26e..d73265e064 100644 --- a/include/configs/vme8349.h +++ b/include/configs/vme8349.h @@ -302,8 +302,6 @@ #define CONFIG_SYS_GPIO2_DIR 0x78900000 #define CONFIG_SYS_GPIO2_DAT 0x70100000 -#define CONFIG_HIGH_BATS /* High BATs supported */ - /* DDR @ 0x00000000 */ #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ BATL_MEMCOHERENCE) diff --git a/include/configs/xpedite517x.h b/include/configs/xpedite517x.h index 2d2a87a719..1ef803b020 100644 --- a/include/configs/xpedite517x.h +++ b/include/configs/xpedite517x.h @@ -17,7 +17,6 @@ #define CONFIG_SYS_FORM_3U_VPX 1 #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ #define CONFIG_BAT_RW 1 /* Use common BAT rw code */ -#define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */ #define CONFIG_ALTIVEC 1 #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 7b5f76670e..4f0e9f75d5 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -733,7 +733,6 @@ CONFIG_HDBOOT CONFIG_HDMI_ENCODER_I2C_ADDR CONFIG_HETROGENOUS_CLUSTERS CONFIG_HIDE_LOGO_VERSION -CONFIG_HIGH_BATS CONFIG_HIKEY_GPIO CONFIG_HITACHI_SX14 CONFIG_HOSTNAME From 30915ab95d9a95328623010390d94da1325529f9 Mon Sep 17 00:00:00 2001 From: Mario Six Date: Mon, 21 Jan 2019 09:17:57 +0100 Subject: [PATCH 34/86] mpc83xx: Migrate BATS config to Kconfig The BATs (block address translation registers) determine the initial memory window mappings. Hence, they must be known at compile time and cannot be implemented in the DT mechanism. Configuration of this crucial variable should still be somewhat comfortable. Hence, make its fields configurable in Kconfig, and assemble the final value from these. Signed-off-by: Mario Six --- arch/powerpc/cpu/mpc83xx/Kconfig | 1 + arch/powerpc/cpu/mpc83xx/bats/Kconfig | 1311 +++++++++++++++++++++++++ arch/powerpc/cpu/mpc83xx/bats/bats.h | 223 +++++ arch/powerpc/cpu/mpc83xx/start.S | 1 + configs/MPC8308RDB_defconfig | 36 + configs/MPC8313ERDB_33_defconfig | 45 + configs/MPC8313ERDB_66_defconfig | 45 + configs/MPC8313ERDB_NAND_33_defconfig | 45 + configs/MPC8313ERDB_NAND_66_defconfig | 45 + configs/MPC8315ERDB_defconfig | 56 ++ configs/MPC8323ERDB_defconfig | 56 ++ configs/MPC832XEMDS_ATM_defconfig | 46 + configs/MPC832XEMDS_HOST_33_defconfig | 66 ++ configs/MPC832XEMDS_HOST_66_defconfig | 66 ++ configs/MPC832XEMDS_SLAVE_defconfig | 66 ++ configs/MPC832XEMDS_defconfig | 46 + configs/MPC8349EMDS_PCI64_defconfig | 31 + configs/MPC8349EMDS_SDRAM_defconfig | 31 + configs/MPC8349EMDS_SLAVE_defconfig | 31 + configs/MPC8349EMDS_defconfig | 31 + configs/MPC8349ITXGP_defconfig | 71 ++ configs/MPC8349ITX_LOWBOOT_defconfig | 71 ++ configs/MPC8349ITX_defconfig | 71 ++ configs/MPC837XEMDS_HOST_defconfig | 75 ++ configs/MPC837XEMDS_SLAVE_defconfig | 39 + configs/MPC837XEMDS_defconfig | 55 ++ configs/MPC837XERDB_SLAVE_defconfig | 39 + configs/MPC837XERDB_defconfig | 75 ++ configs/TQM834x_defconfig | 79 ++ configs/caddy2_defconfig | 49 + configs/hrcon_defconfig | 36 + configs/hrcon_dh_defconfig | 36 + configs/ids8313_defconfig | 46 + configs/kmcoge5ne_defconfig | 79 ++ configs/kmeter1_defconfig | 53 + configs/kmopti2_defconfig | 68 ++ configs/kmsupx5_defconfig | 58 ++ configs/kmtegr1_defconfig | 58 ++ configs/kmtepr2_defconfig | 68 ++ configs/kmvect1_defconfig | 68 ++ configs/mpc8308_p1m_defconfig | 36 + configs/sbc8349_PCI_33_defconfig | 51 + configs/sbc8349_PCI_66_defconfig | 51 + configs/sbc8349_defconfig | 31 + configs/strider_con_defconfig | 36 + configs/strider_con_dp_defconfig | 36 + configs/strider_cpu_defconfig | 36 + configs/strider_cpu_dp_defconfig | 36 + configs/suvd3_defconfig | 68 ++ configs/tuge1_defconfig | 58 ++ configs/tuxx1_defconfig | 68 ++ configs/ve8313_defconfig | 54 + configs/vme8349_defconfig | 49 + include/configs/MPC8308RDB.h | 37 - include/configs/MPC8313ERDB_NAND.h | 62 -- include/configs/MPC8313ERDB_NOR.h | 62 -- include/configs/MPC8315ERDB.h | 79 -- include/configs/MPC8323ERDB.h | 94 -- include/configs/MPC832XEMDS.h | 100 -- include/configs/MPC8349EMDS.h | 93 -- include/configs/MPC8349EMDS_SDRAM.h | 93 -- include/configs/MPC8349ITX.h | 96 -- include/configs/MPC837XEMDS.h | 108 -- include/configs/MPC837XERDB.h | 108 -- include/configs/TQM834x.h | 92 -- include/configs/caddy2.h | 72 -- include/configs/hrcon.h | 37 - include/configs/ids8313.h | 77 -- include/configs/kmcoge5ne.h | 104 -- include/configs/kmeter1.h | 77 -- include/configs/kmopti2.h | 89 -- include/configs/kmsupx5.h | 81 -- include/configs/kmtegr1.h | 68 -- include/configs/kmtepr2.h | 90 -- include/configs/kmvect1.h | 72 -- include/configs/mpc8308_p1m.h | 37 - include/configs/sbc8349.h | 93 -- include/configs/strider.h | 37 - include/configs/suvd3.h | 72 -- include/configs/tuge1.h | 81 -- include/configs/tuxx1.h | 90 -- include/configs/ve8313.h | 70 -- include/configs/vme8349.h | 72 -- 83 files changed, 4082 insertions(+), 2343 deletions(-) create mode 100644 arch/powerpc/cpu/mpc83xx/bats/Kconfig create mode 100644 arch/powerpc/cpu/mpc83xx/bats/bats.h diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index 1206c687cc..f7f625aea1 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -283,6 +283,7 @@ config ARCH_MPC837X select MPC83XX_SECOND_I2C_SUPPORT source "arch/powerpc/cpu/mpc83xx/hrcw/Kconfig" +source "arch/powerpc/cpu/mpc83xx/bats/Kconfig" menu "Legacy options" diff --git a/arch/powerpc/cpu/mpc83xx/bats/Kconfig b/arch/powerpc/cpu/mpc83xx/bats/Kconfig new file mode 100644 index 0000000000..218920cfc9 --- /dev/null +++ b/arch/powerpc/cpu/mpc83xx/bats/Kconfig @@ -0,0 +1,1311 @@ +menu "BATS setup" + +menuconfig BAT0 + bool "BAT0" + +if BAT0 + +config BAT0_NAME + string "Identifier" + +config BAT0_BASE + hex "Base" + +choice + prompt "Block length" + +config BAT0_LENGTH_128_KBYTES + bool "128 kb" + +config BAT0_LENGTH_256_KBYTES + bool "256 kb" + +config BAT0_LENGTH_512_KBYTES + bool "512 kb" + +config BAT0_LENGTH_1_MBYTES + bool "1 mb" + +config BAT0_LENGTH_2_MBYTES + bool "2 mb" + +config BAT0_LENGTH_4_MBYTES + bool "4 mb" + +config BAT0_LENGTH_8_MBYTES + bool "8 mb" + +config BAT0_LENGTH_16_MBYTES + bool "16 mb" + +config BAT0_LENGTH_32_MBYTES + bool "32 mb" + +config BAT0_LENGTH_64_MBYTES + bool "64 mb" + +config BAT0_LENGTH_128_MBYTES + bool "128 mb" + +config BAT0_LENGTH_256_MBYTES + bool "256 mb" +endchoice + +choice + prompt "Protection mode" + +config BAT0_ACCESS_NONE + bool "No access" + +config BAT0_ACCESS_RO + bool "Read-only" + +config BAT0_ACCESS_RW + bool "Read-write" + +endchoice + +config BAT0_ICACHE_WRITETHROUGH + bool "I-cache Write-through" + +config BAT0_ICACHE_INHIBITED + bool "I-cache Inhibited" + +config BAT0_ICACHE_MEMORYCOHERENCE + bool "I-cache Memory coherence" + +config BAT0_ICACHE_GUARDED + bool "I-cache Guarded" + +config BAT0_DCACHE_WRITETHROUGH + bool "D-cache Write-through" + +config BAT0_DCACHE_INHIBITED + bool "D-cache Inhibited" + +config BAT0_DCACHE_MEMORYCOHERENCE + bool "D-cache Memory coherence" + +config BAT0_DCACHE_GUARDED + bool "D-cache Guarded" + +config BAT0_USER_MODE_VALID + bool "User mode valid" + +config BAT0_SUPERVISOR_MODE_VALID + bool "Supervisor mode valid" + +endif + +config BAT0_LENGTH + hex + default 0x00000000 if BAT0_LENGTH_128_KBYTES + default 0x00000004 if BAT0_LENGTH_256_KBYTES + default 0x0000000c if BAT0_LENGTH_512_KBYTES + default 0x0000001c if BAT0_LENGTH_1_MBYTES + default 0x0000003c if BAT0_LENGTH_2_MBYTES + default 0x0000007c if BAT0_LENGTH_4_MBYTES + default 0x000000fc if BAT0_LENGTH_8_MBYTES + default 0x000001fc if BAT0_LENGTH_16_MBYTES + default 0x000003fc if BAT0_LENGTH_32_MBYTES + default 0x000007fc if BAT0_LENGTH_64_MBYTES + default 0x00000ffc if BAT0_LENGTH_128_MBYTES + default 0x00001ffc if BAT0_LENGTH_256_MBYTES + +config BAT0_PAGE_PROTECTION + hex + default 0x0 if BAT0_ACCESS_NONE + default 0x1 if BAT0_ACCESS_RO + default 0x2 if BAT0_ACCESS_RW + +config BAT0_WIMG_ICACHE + hex + default 0x0 if !BAT0_ICACHE_WRITETHROUGH && !BAT0_ICACHE_INHIBITED && !BAT0_ICACHE_MEMORYCOHERENCE && !BAT0_ICACHE_GUARDED + default 0x8 if !BAT0_ICACHE_WRITETHROUGH && !BAT0_ICACHE_INHIBITED && !BAT0_ICACHE_MEMORYCOHERENCE && BAT0_ICACHE_GUARDED + default 0x10 if !BAT0_ICACHE_WRITETHROUGH && !BAT0_ICACHE_INHIBITED && BAT0_ICACHE_MEMORYCOHERENCE && !BAT0_ICACHE_GUARDED + default 0x18 if !BAT0_ICACHE_WRITETHROUGH && !BAT0_ICACHE_INHIBITED && BAT0_ICACHE_MEMORYCOHERENCE && BAT0_ICACHE_GUARDED + default 0x20 if !BAT0_ICACHE_WRITETHROUGH && BAT0_ICACHE_INHIBITED && !BAT0_ICACHE_MEMORYCOHERENCE && !BAT0_ICACHE_GUARDED + default 0x28 if !BAT0_ICACHE_WRITETHROUGH && BAT0_ICACHE_INHIBITED && !BAT0_ICACHE_MEMORYCOHERENCE && BAT0_ICACHE_GUARDED + default 0x30 if !BAT0_ICACHE_WRITETHROUGH && BAT0_ICACHE_INHIBITED && BAT0_ICACHE_MEMORYCOHERENCE && !BAT0_ICACHE_GUARDED + default 0x38 if !BAT0_ICACHE_WRITETHROUGH && BAT0_ICACHE_INHIBITED && BAT0_ICACHE_MEMORYCOHERENCE && BAT0_ICACHE_GUARDED + default 0x40 if BAT0_ICACHE_WRITETHROUGH && !BAT0_ICACHE_INHIBITED && !BAT0_ICACHE_MEMORYCOHERENCE && !BAT0_ICACHE_GUARDED + default 0x48 if BAT0_ICACHE_WRITETHROUGH && !BAT0_ICACHE_INHIBITED && !BAT0_ICACHE_MEMORYCOHERENCE && BAT0_ICACHE_GUARDED + default 0x50 if BAT0_ICACHE_WRITETHROUGH && !BAT0_ICACHE_INHIBITED && BAT0_ICACHE_MEMORYCOHERENCE && !BAT0_ICACHE_GUARDED + default 0x58 if BAT0_ICACHE_WRITETHROUGH && !BAT0_ICACHE_INHIBITED && BAT0_ICACHE_MEMORYCOHERENCE && BAT0_ICACHE_GUARDED + default 0x60 if BAT0_ICACHE_WRITETHROUGH && BAT0_ICACHE_INHIBITED && !BAT0_ICACHE_MEMORYCOHERENCE && !BAT0_ICACHE_GUARDED + default 0x68 if BAT0_ICACHE_WRITETHROUGH && BAT0_ICACHE_INHIBITED && !BAT0_ICACHE_MEMORYCOHERENCE && BAT0_ICACHE_GUARDED + default 0x70 if BAT0_ICACHE_WRITETHROUGH && BAT0_ICACHE_INHIBITED && BAT0_ICACHE_MEMORYCOHERENCE && !BAT0_ICACHE_GUARDED + default 0x78 if BAT0_ICACHE_WRITETHROUGH && BAT0_ICACHE_INHIBITED && BAT0_ICACHE_MEMORYCOHERENCE && BAT0_ICACHE_GUARDED + +config BAT0_WIMG_DCACHE + hex + default 0x0 if !BAT0_DCACHE_WRITETHROUGH && !BAT0_DCACHE_INHIBITED && !BAT0_DCACHE_MEMORYCOHERENCE && !BAT0_DCACHE_GUARDED + default 0x8 if !BAT0_DCACHE_WRITETHROUGH && !BAT0_DCACHE_INHIBITED && !BAT0_DCACHE_MEMORYCOHERENCE && BAT0_DCACHE_GUARDED + default 0x10 if !BAT0_DCACHE_WRITETHROUGH && !BAT0_DCACHE_INHIBITED && BAT0_DCACHE_MEMORYCOHERENCE && !BAT0_DCACHE_GUARDED + default 0x18 if !BAT0_DCACHE_WRITETHROUGH && !BAT0_DCACHE_INHIBITED && BAT0_DCACHE_MEMORYCOHERENCE && BAT0_DCACHE_GUARDED + default 0x20 if !BAT0_DCACHE_WRITETHROUGH && BAT0_DCACHE_INHIBITED && !BAT0_DCACHE_MEMORYCOHERENCE && !BAT0_DCACHE_GUARDED + default 0x28 if !BAT0_DCACHE_WRITETHROUGH && BAT0_DCACHE_INHIBITED && !BAT0_DCACHE_MEMORYCOHERENCE && BAT0_DCACHE_GUARDED + default 0x30 if !BAT0_DCACHE_WRITETHROUGH && BAT0_DCACHE_INHIBITED && BAT0_DCACHE_MEMORYCOHERENCE && !BAT0_DCACHE_GUARDED + default 0x38 if !BAT0_DCACHE_WRITETHROUGH && BAT0_DCACHE_INHIBITED && BAT0_DCACHE_MEMORYCOHERENCE && BAT0_DCACHE_GUARDED + default 0x40 if BAT0_DCACHE_WRITETHROUGH && !BAT0_DCACHE_INHIBITED && !BAT0_DCACHE_MEMORYCOHERENCE && !BAT0_DCACHE_GUARDED + default 0x48 if BAT0_DCACHE_WRITETHROUGH && !BAT0_DCACHE_INHIBITED && !BAT0_DCACHE_MEMORYCOHERENCE && BAT0_DCACHE_GUARDED + default 0x50 if BAT0_DCACHE_WRITETHROUGH && !BAT0_DCACHE_INHIBITED && BAT0_DCACHE_MEMORYCOHERENCE && !BAT0_DCACHE_GUARDED + default 0x58 if BAT0_DCACHE_WRITETHROUGH && !BAT0_DCACHE_INHIBITED && BAT0_DCACHE_MEMORYCOHERENCE && BAT0_DCACHE_GUARDED + default 0x60 if BAT0_DCACHE_WRITETHROUGH && BAT0_DCACHE_INHIBITED && !BAT0_DCACHE_MEMORYCOHERENCE && !BAT0_DCACHE_GUARDED + default 0x68 if BAT0_DCACHE_WRITETHROUGH && BAT0_DCACHE_INHIBITED && !BAT0_DCACHE_MEMORYCOHERENCE && BAT0_DCACHE_GUARDED + default 0x70 if BAT0_DCACHE_WRITETHROUGH && BAT0_DCACHE_INHIBITED && BAT0_DCACHE_MEMORYCOHERENCE && !BAT0_DCACHE_GUARDED + default 0x78 if BAT0_DCACHE_WRITETHROUGH && BAT0_DCACHE_INHIBITED && BAT0_DCACHE_MEMORYCOHERENCE && BAT0_DCACHE_GUARDED + +config BAT0_VALID_BITS + hex + default 0x0 if !BAT0_SUPERVISOR_MODE_VALID && !BAT0_USER_MODE_VALID + default 0x1 if !BAT0_SUPERVISOR_MODE_VALID && BAT0_USER_MODE_VALID + default 0x2 if BAT0_SUPERVISOR_MODE_VALID && !BAT0_USER_MODE_VALID + default 0x3 if BAT0_SUPERVISOR_MODE_VALID && BAT0_USER_MODE_VALID + +menuconfig BAT1 + bool "BAT1" + +if BAT1 + +config BAT1_NAME + string "Identifier" + +config BAT1_BASE + hex "Base" + +choice + prompt "Block length" + +config BAT1_LENGTH_128_KBYTES + bool "128 kb" + +config BAT1_LENGTH_256_KBYTES + bool "256 kb" + +config BAT1_LENGTH_512_KBYTES + bool "512 kb" + +config BAT1_LENGTH_1_MBYTES + bool "1 mb" + +config BAT1_LENGTH_2_MBYTES + bool "2 mb" + +config BAT1_LENGTH_4_MBYTES + bool "4 mb" + +config BAT1_LENGTH_8_MBYTES + bool "8 mb" + +config BAT1_LENGTH_16_MBYTES + bool "16 mb" + +config BAT1_LENGTH_32_MBYTES + bool "32 mb" + +config BAT1_LENGTH_64_MBYTES + bool "64 mb" + +config BAT1_LENGTH_128_MBYTES + bool "128 mb" + +config BAT1_LENGTH_256_MBYTES + bool "256 mb" +endchoice + +choice + prompt "Protection mode" + +config BAT1_ACCESS_NONE + bool "No access" + +config BAT1_ACCESS_RO + bool "Read-only" + +config BAT1_ACCESS_RW + bool "Read-write" + +endchoice + +config BAT1_ICACHE_WRITETHROUGH + bool "I-cache Write-through" + +config BAT1_ICACHE_INHIBITED + bool "I-cache Inhibited" + +config BAT1_ICACHE_MEMORYCOHERENCE + bool "I-cache Memory coherence" + +config BAT1_ICACHE_GUARDED + bool "I-cache Guarded" + +config BAT1_DCACHE_WRITETHROUGH + bool "D-cache Write-through" + +config BAT1_DCACHE_INHIBITED + bool "D-cache Inhibited" + +config BAT1_DCACHE_MEMORYCOHERENCE + bool "D-cache Memory coherence" + +config BAT1_DCACHE_GUARDED + bool "D-cache Guarded" + +config BAT1_USER_MODE_VALID + bool "User mode valid" + +config BAT1_SUPERVISOR_MODE_VALID + bool "Supervisor mode valid" + +endif + +config BAT1_LENGTH + hex + default 0x00000000 if BAT1_LENGTH_128_KBYTES + default 0x00000004 if BAT1_LENGTH_256_KBYTES + default 0x0000000c if BAT1_LENGTH_512_KBYTES + default 0x0000001c if BAT1_LENGTH_1_MBYTES + default 0x0000003c if BAT1_LENGTH_2_MBYTES + default 0x0000007c if BAT1_LENGTH_4_MBYTES + default 0x000000fc if BAT1_LENGTH_8_MBYTES + default 0x000001fc if BAT1_LENGTH_16_MBYTES + default 0x000003fc if BAT1_LENGTH_32_MBYTES + default 0x000007fc if BAT1_LENGTH_64_MBYTES + default 0x00000ffc if BAT1_LENGTH_128_MBYTES + default 0x00001ffc if BAT1_LENGTH_256_MBYTES + +config BAT1_PAGE_PROTECTION + hex + default 0x0 if BAT1_ACCESS_NONE + default 0x1 if BAT1_ACCESS_RO + default 0x2 if BAT1_ACCESS_RW + +config BAT1_WIMG_ICACHE + hex + default 0x0 if !BAT1_ICACHE_WRITETHROUGH && !BAT1_ICACHE_INHIBITED && !BAT1_ICACHE_MEMORYCOHERENCE && !BAT1_ICACHE_GUARDED + default 0x8 if !BAT1_ICACHE_WRITETHROUGH && !BAT1_ICACHE_INHIBITED && !BAT1_ICACHE_MEMORYCOHERENCE && BAT1_ICACHE_GUARDED + default 0x10 if !BAT1_ICACHE_WRITETHROUGH && !BAT1_ICACHE_INHIBITED && BAT1_ICACHE_MEMORYCOHERENCE && !BAT1_ICACHE_GUARDED + default 0x18 if !BAT1_ICACHE_WRITETHROUGH && !BAT1_ICACHE_INHIBITED && BAT1_ICACHE_MEMORYCOHERENCE && BAT1_ICACHE_GUARDED + default 0x20 if !BAT1_ICACHE_WRITETHROUGH && BAT1_ICACHE_INHIBITED && !BAT1_ICACHE_MEMORYCOHERENCE && !BAT1_ICACHE_GUARDED + default 0x28 if !BAT1_ICACHE_WRITETHROUGH && BAT1_ICACHE_INHIBITED && !BAT1_ICACHE_MEMORYCOHERENCE && BAT1_ICACHE_GUARDED + default 0x30 if !BAT1_ICACHE_WRITETHROUGH && BAT1_ICACHE_INHIBITED && BAT1_ICACHE_MEMORYCOHERENCE && !BAT1_ICACHE_GUARDED + default 0x38 if !BAT1_ICACHE_WRITETHROUGH && BAT1_ICACHE_INHIBITED && BAT1_ICACHE_MEMORYCOHERENCE && BAT1_ICACHE_GUARDED + default 0x40 if BAT1_ICACHE_WRITETHROUGH && !BAT1_ICACHE_INHIBITED && !BAT1_ICACHE_MEMORYCOHERENCE && !BAT1_ICACHE_GUARDED + default 0x48 if BAT1_ICACHE_WRITETHROUGH && !BAT1_ICACHE_INHIBITED && !BAT1_ICACHE_MEMORYCOHERENCE && BAT1_ICACHE_GUARDED + default 0x50 if BAT1_ICACHE_WRITETHROUGH && !BAT1_ICACHE_INHIBITED && BAT1_ICACHE_MEMORYCOHERENCE && !BAT1_ICACHE_GUARDED + default 0x58 if BAT1_ICACHE_WRITETHROUGH && !BAT1_ICACHE_INHIBITED && BAT1_ICACHE_MEMORYCOHERENCE && BAT1_ICACHE_GUARDED + default 0x60 if BAT1_ICACHE_WRITETHROUGH && BAT1_ICACHE_INHIBITED && !BAT1_ICACHE_MEMORYCOHERENCE && !BAT1_ICACHE_GUARDED + default 0x68 if BAT1_ICACHE_WRITETHROUGH && BAT1_ICACHE_INHIBITED && !BAT1_ICACHE_MEMORYCOHERENCE && BAT1_ICACHE_GUARDED + default 0x70 if BAT1_ICACHE_WRITETHROUGH && BAT1_ICACHE_INHIBITED && BAT1_ICACHE_MEMORYCOHERENCE && !BAT1_ICACHE_GUARDED + default 0x78 if BAT1_ICACHE_WRITETHROUGH && BAT1_ICACHE_INHIBITED && BAT1_ICACHE_MEMORYCOHERENCE && BAT1_ICACHE_GUARDED + +config BAT1_WIMG_DCACHE + hex + default 0x0 if !BAT1_DCACHE_WRITETHROUGH && !BAT1_DCACHE_INHIBITED && !BAT1_DCACHE_MEMORYCOHERENCE && !BAT1_DCACHE_GUARDED + default 0x8 if !BAT1_DCACHE_WRITETHROUGH && !BAT1_DCACHE_INHIBITED && !BAT1_DCACHE_MEMORYCOHERENCE && BAT1_DCACHE_GUARDED + default 0x10 if !BAT1_DCACHE_WRITETHROUGH && !BAT1_DCACHE_INHIBITED && BAT1_DCACHE_MEMORYCOHERENCE && !BAT1_DCACHE_GUARDED + default 0x18 if !BAT1_DCACHE_WRITETHROUGH && !BAT1_DCACHE_INHIBITED && BAT1_DCACHE_MEMORYCOHERENCE && BAT1_DCACHE_GUARDED + default 0x20 if !BAT1_DCACHE_WRITETHROUGH && BAT1_DCACHE_INHIBITED && !BAT1_DCACHE_MEMORYCOHERENCE && !BAT1_DCACHE_GUARDED + default 0x28 if !BAT1_DCACHE_WRITETHROUGH && BAT1_DCACHE_INHIBITED && !BAT1_DCACHE_MEMORYCOHERENCE && BAT1_DCACHE_GUARDED + default 0x30 if !BAT1_DCACHE_WRITETHROUGH && BAT1_DCACHE_INHIBITED && BAT1_DCACHE_MEMORYCOHERENCE && !BAT1_DCACHE_GUARDED + default 0x38 if !BAT1_DCACHE_WRITETHROUGH && BAT1_DCACHE_INHIBITED && BAT1_DCACHE_MEMORYCOHERENCE && BAT1_DCACHE_GUARDED + default 0x40 if BAT1_DCACHE_WRITETHROUGH && !BAT1_DCACHE_INHIBITED && !BAT1_DCACHE_MEMORYCOHERENCE && !BAT1_DCACHE_GUARDED + default 0x48 if BAT1_DCACHE_WRITETHROUGH && !BAT1_DCACHE_INHIBITED && !BAT1_DCACHE_MEMORYCOHERENCE && BAT1_DCACHE_GUARDED + default 0x50 if BAT1_DCACHE_WRITETHROUGH && !BAT1_DCACHE_INHIBITED && BAT1_DCACHE_MEMORYCOHERENCE && !BAT1_DCACHE_GUARDED + default 0x58 if BAT1_DCACHE_WRITETHROUGH && !BAT1_DCACHE_INHIBITED && BAT1_DCACHE_MEMORYCOHERENCE && BAT1_DCACHE_GUARDED + default 0x60 if BAT1_DCACHE_WRITETHROUGH && BAT1_DCACHE_INHIBITED && !BAT1_DCACHE_MEMORYCOHERENCE && !BAT1_DCACHE_GUARDED + default 0x68 if BAT1_DCACHE_WRITETHROUGH && BAT1_DCACHE_INHIBITED && !BAT1_DCACHE_MEMORYCOHERENCE && BAT1_DCACHE_GUARDED + default 0x70 if BAT1_DCACHE_WRITETHROUGH && BAT1_DCACHE_INHIBITED && BAT1_DCACHE_MEMORYCOHERENCE && !BAT1_DCACHE_GUARDED + default 0x78 if BAT1_DCACHE_WRITETHROUGH && BAT1_DCACHE_INHIBITED && BAT1_DCACHE_MEMORYCOHERENCE && BAT1_DCACHE_GUARDED + +config BAT1_VALID_BITS + hex + default 0x0 if !BAT1_SUPERVISOR_MODE_VALID && !BAT1_USER_MODE_VALID + default 0x1 if !BAT1_SUPERVISOR_MODE_VALID && BAT1_USER_MODE_VALID + default 0x2 if BAT1_SUPERVISOR_MODE_VALID && !BAT1_USER_MODE_VALID + default 0x3 if BAT1_SUPERVISOR_MODE_VALID && BAT1_USER_MODE_VALID + +menuconfig BAT2 + bool "BAT2" + +if BAT2 + +config BAT2_NAME + string "Identifier" + +config BAT2_BASE + hex "Base" + +choice + prompt "Block length" + +config BAT2_LENGTH_128_KBYTES + bool "128 kb" + +config BAT2_LENGTH_256_KBYTES + bool "256 kb" + +config BAT2_LENGTH_512_KBYTES + bool "512 kb" + +config BAT2_LENGTH_1_MBYTES + bool "1 mb" + +config BAT2_LENGTH_2_MBYTES + bool "2 mb" + +config BAT2_LENGTH_4_MBYTES + bool "4 mb" + +config BAT2_LENGTH_8_MBYTES + bool "8 mb" + +config BAT2_LENGTH_16_MBYTES + bool "16 mb" + +config BAT2_LENGTH_32_MBYTES + bool "32 mb" + +config BAT2_LENGTH_64_MBYTES + bool "64 mb" + +config BAT2_LENGTH_128_MBYTES + bool "128 mb" + +config BAT2_LENGTH_256_MBYTES + bool "256 mb" +endchoice + +choice + prompt "Protection mode" + +config BAT2_ACCESS_NONE + bool "No access" + +config BAT2_ACCESS_RO + bool "Read-only" + +config BAT2_ACCESS_RW + bool "Read-write" + +endchoice + +config BAT2_ICACHE_WRITETHROUGH + bool "I-cache Write-through" + +config BAT2_ICACHE_INHIBITED + bool "I-cache Inhibited" + +config BAT2_ICACHE_MEMORYCOHERENCE + bool "I-cache Memory coherence" + +config BAT2_ICACHE_GUARDED + bool "I-cache Guarded" + +config BAT2_DCACHE_WRITETHROUGH + bool "D-cache Write-through" + +config BAT2_DCACHE_INHIBITED + bool "D-cache Inhibited" + +config BAT2_DCACHE_MEMORYCOHERENCE + bool "D-cache Memory coherence" + +config BAT2_DCACHE_GUARDED + bool "D-cache Guarded" + +config BAT2_USER_MODE_VALID + bool "User mode valid" + +config BAT2_SUPERVISOR_MODE_VALID + bool "Supervisor mode valid" + +endif + +config BAT2_LENGTH + hex + default 0x00000000 if BAT2_LENGTH_128_KBYTES + default 0x00000004 if BAT2_LENGTH_256_KBYTES + default 0x0000000c if BAT2_LENGTH_512_KBYTES + default 0x0000001c if BAT2_LENGTH_1_MBYTES + default 0x0000003c if BAT2_LENGTH_2_MBYTES + default 0x0000007c if BAT2_LENGTH_4_MBYTES + default 0x000000fc if BAT2_LENGTH_8_MBYTES + default 0x000001fc if BAT2_LENGTH_16_MBYTES + default 0x000003fc if BAT2_LENGTH_32_MBYTES + default 0x000007fc if BAT2_LENGTH_64_MBYTES + default 0x00000ffc if BAT2_LENGTH_128_MBYTES + default 0x00001ffc if BAT2_LENGTH_256_MBYTES + +config BAT2_PAGE_PROTECTION + hex + default 0x0 if BAT2_ACCESS_NONE + default 0x1 if BAT2_ACCESS_RO + default 0x2 if BAT2_ACCESS_RW + +config BAT2_WIMG_ICACHE + hex + default 0x0 if !BAT2_ICACHE_WRITETHROUGH && !BAT2_ICACHE_INHIBITED && !BAT2_ICACHE_MEMORYCOHERENCE && !BAT2_ICACHE_GUARDED + default 0x8 if !BAT2_ICACHE_WRITETHROUGH && !BAT2_ICACHE_INHIBITED && !BAT2_ICACHE_MEMORYCOHERENCE && BAT2_ICACHE_GUARDED + default 0x10 if !BAT2_ICACHE_WRITETHROUGH && !BAT2_ICACHE_INHIBITED && BAT2_ICACHE_MEMORYCOHERENCE && !BAT2_ICACHE_GUARDED + default 0x18 if !BAT2_ICACHE_WRITETHROUGH && !BAT2_ICACHE_INHIBITED && BAT2_ICACHE_MEMORYCOHERENCE && BAT2_ICACHE_GUARDED + default 0x20 if !BAT2_ICACHE_WRITETHROUGH && BAT2_ICACHE_INHIBITED && !BAT2_ICACHE_MEMORYCOHERENCE && !BAT2_ICACHE_GUARDED + default 0x28 if !BAT2_ICACHE_WRITETHROUGH && BAT2_ICACHE_INHIBITED && !BAT2_ICACHE_MEMORYCOHERENCE && BAT2_ICACHE_GUARDED + default 0x30 if !BAT2_ICACHE_WRITETHROUGH && BAT2_ICACHE_INHIBITED && BAT2_ICACHE_MEMORYCOHERENCE && !BAT2_ICACHE_GUARDED + default 0x38 if !BAT2_ICACHE_WRITETHROUGH && BAT2_ICACHE_INHIBITED && BAT2_ICACHE_MEMORYCOHERENCE && BAT2_ICACHE_GUARDED + default 0x40 if BAT2_ICACHE_WRITETHROUGH && !BAT2_ICACHE_INHIBITED && !BAT2_ICACHE_MEMORYCOHERENCE && !BAT2_ICACHE_GUARDED + default 0x48 if BAT2_ICACHE_WRITETHROUGH && !BAT2_ICACHE_INHIBITED && !BAT2_ICACHE_MEMORYCOHERENCE && BAT2_ICACHE_GUARDED + default 0x50 if BAT2_ICACHE_WRITETHROUGH && !BAT2_ICACHE_INHIBITED && BAT2_ICACHE_MEMORYCOHERENCE && !BAT2_ICACHE_GUARDED + default 0x58 if BAT2_ICACHE_WRITETHROUGH && !BAT2_ICACHE_INHIBITED && BAT2_ICACHE_MEMORYCOHERENCE && BAT2_ICACHE_GUARDED + default 0x60 if BAT2_ICACHE_WRITETHROUGH && BAT2_ICACHE_INHIBITED && !BAT2_ICACHE_MEMORYCOHERENCE && !BAT2_ICACHE_GUARDED + default 0x68 if BAT2_ICACHE_WRITETHROUGH && BAT2_ICACHE_INHIBITED && !BAT2_ICACHE_MEMORYCOHERENCE && BAT2_ICACHE_GUARDED + default 0x70 if BAT2_ICACHE_WRITETHROUGH && BAT2_ICACHE_INHIBITED && BAT2_ICACHE_MEMORYCOHERENCE && !BAT2_ICACHE_GUARDED + default 0x78 if BAT2_ICACHE_WRITETHROUGH && BAT2_ICACHE_INHIBITED && BAT2_ICACHE_MEMORYCOHERENCE && BAT2_ICACHE_GUARDED + +config BAT2_WIMG_DCACHE + hex + default 0x0 if !BAT2_DCACHE_WRITETHROUGH && !BAT2_DCACHE_INHIBITED && !BAT2_DCACHE_MEMORYCOHERENCE && !BAT2_DCACHE_GUARDED + default 0x8 if !BAT2_DCACHE_WRITETHROUGH && !BAT2_DCACHE_INHIBITED && !BAT2_DCACHE_MEMORYCOHERENCE && BAT2_DCACHE_GUARDED + default 0x10 if !BAT2_DCACHE_WRITETHROUGH && !BAT2_DCACHE_INHIBITED && BAT2_DCACHE_MEMORYCOHERENCE && !BAT2_DCACHE_GUARDED + default 0x18 if !BAT2_DCACHE_WRITETHROUGH && !BAT2_DCACHE_INHIBITED && BAT2_DCACHE_MEMORYCOHERENCE && BAT2_DCACHE_GUARDED + default 0x20 if !BAT2_DCACHE_WRITETHROUGH && BAT2_DCACHE_INHIBITED && !BAT2_DCACHE_MEMORYCOHERENCE && !BAT2_DCACHE_GUARDED + default 0x28 if !BAT2_DCACHE_WRITETHROUGH && BAT2_DCACHE_INHIBITED && !BAT2_DCACHE_MEMORYCOHERENCE && BAT2_DCACHE_GUARDED + default 0x30 if !BAT2_DCACHE_WRITETHROUGH && BAT2_DCACHE_INHIBITED && BAT2_DCACHE_MEMORYCOHERENCE && !BAT2_DCACHE_GUARDED + default 0x38 if !BAT2_DCACHE_WRITETHROUGH && BAT2_DCACHE_INHIBITED && BAT2_DCACHE_MEMORYCOHERENCE && BAT2_DCACHE_GUARDED + default 0x40 if BAT2_DCACHE_WRITETHROUGH && !BAT2_DCACHE_INHIBITED && !BAT2_DCACHE_MEMORYCOHERENCE && !BAT2_DCACHE_GUARDED + default 0x48 if BAT2_DCACHE_WRITETHROUGH && !BAT2_DCACHE_INHIBITED && !BAT2_DCACHE_MEMORYCOHERENCE && BAT2_DCACHE_GUARDED + default 0x50 if BAT2_DCACHE_WRITETHROUGH && !BAT2_DCACHE_INHIBITED && BAT2_DCACHE_MEMORYCOHERENCE && !BAT2_DCACHE_GUARDED + default 0x58 if BAT2_DCACHE_WRITETHROUGH && !BAT2_DCACHE_INHIBITED && BAT2_DCACHE_MEMORYCOHERENCE && BAT2_DCACHE_GUARDED + default 0x60 if BAT2_DCACHE_WRITETHROUGH && BAT2_DCACHE_INHIBITED && !BAT2_DCACHE_MEMORYCOHERENCE && !BAT2_DCACHE_GUARDED + default 0x68 if BAT2_DCACHE_WRITETHROUGH && BAT2_DCACHE_INHIBITED && !BAT2_DCACHE_MEMORYCOHERENCE && BAT2_DCACHE_GUARDED + default 0x70 if BAT2_DCACHE_WRITETHROUGH && BAT2_DCACHE_INHIBITED && BAT2_DCACHE_MEMORYCOHERENCE && !BAT2_DCACHE_GUARDED + default 0x78 if BAT2_DCACHE_WRITETHROUGH && BAT2_DCACHE_INHIBITED && BAT2_DCACHE_MEMORYCOHERENCE && BAT2_DCACHE_GUARDED + +config BAT2_VALID_BITS + hex + default 0x0 if !BAT2_SUPERVISOR_MODE_VALID && !BAT2_USER_MODE_VALID + default 0x1 if !BAT2_SUPERVISOR_MODE_VALID && BAT2_USER_MODE_VALID + default 0x2 if BAT2_SUPERVISOR_MODE_VALID && !BAT2_USER_MODE_VALID + default 0x3 if BAT2_SUPERVISOR_MODE_VALID && BAT2_USER_MODE_VALID + +menuconfig BAT3 + bool "BAT3" + +if BAT3 + +config BAT3_NAME + string "Identifier" + +config BAT3_BASE + hex "Base" + +choice + prompt "Block length" + +config BAT3_LENGTH_128_KBYTES + bool "128 kb" + +config BAT3_LENGTH_256_KBYTES + bool "256 kb" + +config BAT3_LENGTH_512_KBYTES + bool "512 kb" + +config BAT3_LENGTH_1_MBYTES + bool "1 mb" + +config BAT3_LENGTH_2_MBYTES + bool "2 mb" + +config BAT3_LENGTH_4_MBYTES + bool "4 mb" + +config BAT3_LENGTH_8_MBYTES + bool "8 mb" + +config BAT3_LENGTH_16_MBYTES + bool "16 mb" + +config BAT3_LENGTH_32_MBYTES + bool "32 mb" + +config BAT3_LENGTH_64_MBYTES + bool "64 mb" + +config BAT3_LENGTH_128_MBYTES + bool "128 mb" + +config BAT3_LENGTH_256_MBYTES + bool "256 mb" +endchoice + +choice + prompt "Protection mode" + +config BAT3_ACCESS_NONE + bool "No access" + +config BAT3_ACCESS_RO + bool "Read-only" + +config BAT3_ACCESS_RW + bool "Read-write" + +endchoice + +config BAT3_ICACHE_WRITETHROUGH + bool "I-cache Write-through" + +config BAT3_ICACHE_INHIBITED + bool "I-cache Inhibited" + +config BAT3_ICACHE_MEMORYCOHERENCE + bool "I-cache Memory coherence" + +config BAT3_ICACHE_GUARDED + bool "I-cache Guarded" + +config BAT3_DCACHE_WRITETHROUGH + bool "D-cache Write-through" + +config BAT3_DCACHE_INHIBITED + bool "D-cache Inhibited" + +config BAT3_DCACHE_MEMORYCOHERENCE + bool "D-cache Memory coherence" + +config BAT3_DCACHE_GUARDED + bool "D-cache Guarded" + +config BAT3_USER_MODE_VALID + bool "User mode valid" + +config BAT3_SUPERVISOR_MODE_VALID + bool "Supervisor mode valid" + +endif + +config BAT3_LENGTH + hex + default 0x00000000 if BAT3_LENGTH_128_KBYTES + default 0x00000004 if BAT3_LENGTH_256_KBYTES + default 0x0000000c if BAT3_LENGTH_512_KBYTES + default 0x0000001c if BAT3_LENGTH_1_MBYTES + default 0x0000003c if BAT3_LENGTH_2_MBYTES + default 0x0000007c if BAT3_LENGTH_4_MBYTES + default 0x000000fc if BAT3_LENGTH_8_MBYTES + default 0x000001fc if BAT3_LENGTH_16_MBYTES + default 0x000003fc if BAT3_LENGTH_32_MBYTES + default 0x000007fc if BAT3_LENGTH_64_MBYTES + default 0x00000ffc if BAT3_LENGTH_128_MBYTES + default 0x00001ffc if BAT3_LENGTH_256_MBYTES + +config BAT3_PAGE_PROTECTION + hex + default 0x0 if BAT3_ACCESS_NONE + default 0x1 if BAT3_ACCESS_RO + default 0x2 if BAT3_ACCESS_RW + +config BAT3_WIMG_ICACHE + hex + default 0x0 if !BAT3_ICACHE_WRITETHROUGH && !BAT3_ICACHE_INHIBITED && !BAT3_ICACHE_MEMORYCOHERENCE && !BAT3_ICACHE_GUARDED + default 0x8 if !BAT3_ICACHE_WRITETHROUGH && !BAT3_ICACHE_INHIBITED && !BAT3_ICACHE_MEMORYCOHERENCE && BAT3_ICACHE_GUARDED + default 0x10 if !BAT3_ICACHE_WRITETHROUGH && !BAT3_ICACHE_INHIBITED && BAT3_ICACHE_MEMORYCOHERENCE && !BAT3_ICACHE_GUARDED + default 0x18 if !BAT3_ICACHE_WRITETHROUGH && !BAT3_ICACHE_INHIBITED && BAT3_ICACHE_MEMORYCOHERENCE && BAT3_ICACHE_GUARDED + default 0x20 if !BAT3_ICACHE_WRITETHROUGH && BAT3_ICACHE_INHIBITED && !BAT3_ICACHE_MEMORYCOHERENCE && !BAT3_ICACHE_GUARDED + default 0x28 if !BAT3_ICACHE_WRITETHROUGH && BAT3_ICACHE_INHIBITED && !BAT3_ICACHE_MEMORYCOHERENCE && BAT3_ICACHE_GUARDED + default 0x30 if !BAT3_ICACHE_WRITETHROUGH && BAT3_ICACHE_INHIBITED && BAT3_ICACHE_MEMORYCOHERENCE && !BAT3_ICACHE_GUARDED + default 0x38 if !BAT3_ICACHE_WRITETHROUGH && BAT3_ICACHE_INHIBITED && BAT3_ICACHE_MEMORYCOHERENCE && BAT3_ICACHE_GUARDED + default 0x40 if BAT3_ICACHE_WRITETHROUGH && !BAT3_ICACHE_INHIBITED && !BAT3_ICACHE_MEMORYCOHERENCE && !BAT3_ICACHE_GUARDED + default 0x48 if BAT3_ICACHE_WRITETHROUGH && !BAT3_ICACHE_INHIBITED && !BAT3_ICACHE_MEMORYCOHERENCE && BAT3_ICACHE_GUARDED + default 0x50 if BAT3_ICACHE_WRITETHROUGH && !BAT3_ICACHE_INHIBITED && BAT3_ICACHE_MEMORYCOHERENCE && !BAT3_ICACHE_GUARDED + default 0x58 if BAT3_ICACHE_WRITETHROUGH && !BAT3_ICACHE_INHIBITED && BAT3_ICACHE_MEMORYCOHERENCE && BAT3_ICACHE_GUARDED + default 0x60 if BAT3_ICACHE_WRITETHROUGH && BAT3_ICACHE_INHIBITED && !BAT3_ICACHE_MEMORYCOHERENCE && !BAT3_ICACHE_GUARDED + default 0x68 if BAT3_ICACHE_WRITETHROUGH && BAT3_ICACHE_INHIBITED && !BAT3_ICACHE_MEMORYCOHERENCE && BAT3_ICACHE_GUARDED + default 0x70 if BAT3_ICACHE_WRITETHROUGH && BAT3_ICACHE_INHIBITED && BAT3_ICACHE_MEMORYCOHERENCE && !BAT3_ICACHE_GUARDED + default 0x78 if BAT3_ICACHE_WRITETHROUGH && BAT3_ICACHE_INHIBITED && BAT3_ICACHE_MEMORYCOHERENCE && BAT3_ICACHE_GUARDED + +config BAT3_WIMG_DCACHE + hex + default 0x0 if !BAT3_DCACHE_WRITETHROUGH && !BAT3_DCACHE_INHIBITED && !BAT3_DCACHE_MEMORYCOHERENCE && !BAT3_DCACHE_GUARDED + default 0x8 if !BAT3_DCACHE_WRITETHROUGH && !BAT3_DCACHE_INHIBITED && !BAT3_DCACHE_MEMORYCOHERENCE && BAT3_DCACHE_GUARDED + default 0x10 if !BAT3_DCACHE_WRITETHROUGH && !BAT3_DCACHE_INHIBITED && BAT3_DCACHE_MEMORYCOHERENCE && !BAT3_DCACHE_GUARDED + default 0x18 if !BAT3_DCACHE_WRITETHROUGH && !BAT3_DCACHE_INHIBITED && BAT3_DCACHE_MEMORYCOHERENCE && BAT3_DCACHE_GUARDED + default 0x20 if !BAT3_DCACHE_WRITETHROUGH && BAT3_DCACHE_INHIBITED && !BAT3_DCACHE_MEMORYCOHERENCE && !BAT3_DCACHE_GUARDED + default 0x28 if !BAT3_DCACHE_WRITETHROUGH && BAT3_DCACHE_INHIBITED && !BAT3_DCACHE_MEMORYCOHERENCE && BAT3_DCACHE_GUARDED + default 0x30 if !BAT3_DCACHE_WRITETHROUGH && BAT3_DCACHE_INHIBITED && BAT3_DCACHE_MEMORYCOHERENCE && !BAT3_DCACHE_GUARDED + default 0x38 if !BAT3_DCACHE_WRITETHROUGH && BAT3_DCACHE_INHIBITED && BAT3_DCACHE_MEMORYCOHERENCE && BAT3_DCACHE_GUARDED + default 0x40 if BAT3_DCACHE_WRITETHROUGH && !BAT3_DCACHE_INHIBITED && !BAT3_DCACHE_MEMORYCOHERENCE && !BAT3_DCACHE_GUARDED + default 0x48 if BAT3_DCACHE_WRITETHROUGH && !BAT3_DCACHE_INHIBITED && !BAT3_DCACHE_MEMORYCOHERENCE && BAT3_DCACHE_GUARDED + default 0x50 if BAT3_DCACHE_WRITETHROUGH && !BAT3_DCACHE_INHIBITED && BAT3_DCACHE_MEMORYCOHERENCE && !BAT3_DCACHE_GUARDED + default 0x58 if BAT3_DCACHE_WRITETHROUGH && !BAT3_DCACHE_INHIBITED && BAT3_DCACHE_MEMORYCOHERENCE && BAT3_DCACHE_GUARDED + default 0x60 if BAT3_DCACHE_WRITETHROUGH && BAT3_DCACHE_INHIBITED && !BAT3_DCACHE_MEMORYCOHERENCE && !BAT3_DCACHE_GUARDED + default 0x68 if BAT3_DCACHE_WRITETHROUGH && BAT3_DCACHE_INHIBITED && !BAT3_DCACHE_MEMORYCOHERENCE && BAT3_DCACHE_GUARDED + default 0x70 if BAT3_DCACHE_WRITETHROUGH && BAT3_DCACHE_INHIBITED && BAT3_DCACHE_MEMORYCOHERENCE && !BAT3_DCACHE_GUARDED + default 0x78 if BAT3_DCACHE_WRITETHROUGH && BAT3_DCACHE_INHIBITED && BAT3_DCACHE_MEMORYCOHERENCE && BAT3_DCACHE_GUARDED + +config BAT3_VALID_BITS + hex + default 0x0 if !BAT3_SUPERVISOR_MODE_VALID && !BAT3_USER_MODE_VALID + default 0x1 if !BAT3_SUPERVISOR_MODE_VALID && BAT3_USER_MODE_VALID + default 0x2 if BAT3_SUPERVISOR_MODE_VALID && !BAT3_USER_MODE_VALID + default 0x3 if BAT3_SUPERVISOR_MODE_VALID && BAT3_USER_MODE_VALID + +if HIGH_BATS + +menuconfig BAT4 + bool "BAT4" + +if BAT4 + +config BAT4_NAME + string "Identifier" + +config BAT4_BASE + hex "Base" + +choice + prompt "Block length" + +config BAT4_LENGTH_128_KBYTES + bool "128 kb" + +config BAT4_LENGTH_256_KBYTES + bool "256 kb" + +config BAT4_LENGTH_512_KBYTES + bool "512 kb" + +config BAT4_LENGTH_1_MBYTES + bool "1 mb" + +config BAT4_LENGTH_2_MBYTES + bool "2 mb" + +config BAT4_LENGTH_4_MBYTES + bool "4 mb" + +config BAT4_LENGTH_8_MBYTES + bool "8 mb" + +config BAT4_LENGTH_16_MBYTES + bool "16 mb" + +config BAT4_LENGTH_32_MBYTES + bool "32 mb" + +config BAT4_LENGTH_64_MBYTES + bool "64 mb" + +config BAT4_LENGTH_128_MBYTES + bool "128 mb" + +config BAT4_LENGTH_256_MBYTES + bool "256 mb" +endchoice + +choice + prompt "Protection mode" + +config BAT4_ACCESS_NONE + bool "No access" + +config BAT4_ACCESS_RO + bool "Read-only" + +config BAT4_ACCESS_RW + bool "Read-write" + +endchoice + +config BAT4_ICACHE_WRITETHROUGH + bool "I-cache Write-through" + +config BAT4_ICACHE_INHIBITED + bool "I-cache Inhibited" + +config BAT4_ICACHE_MEMORYCOHERENCE + bool "I-cache Memory coherence" + +config BAT4_ICACHE_GUARDED + bool "I-cache Guarded" + +config BAT4_DCACHE_WRITETHROUGH + bool "D-cache Write-through" + +config BAT4_DCACHE_INHIBITED + bool "D-cache Inhibited" + +config BAT4_DCACHE_MEMORYCOHERENCE + bool "D-cache Memory coherence" + +config BAT4_DCACHE_GUARDED + bool "D-cache Guarded" + +config BAT4_USER_MODE_VALID + bool "User mode valid" + +config BAT4_SUPERVISOR_MODE_VALID + bool "Supervisor mode valid" + +endif + +config BAT4_LENGTH + hex + default 0x00000000 if BAT4_LENGTH_128_KBYTES + default 0x00000004 if BAT4_LENGTH_256_KBYTES + default 0x0000000c if BAT4_LENGTH_512_KBYTES + default 0x0000001c if BAT4_LENGTH_1_MBYTES + default 0x0000003c if BAT4_LENGTH_2_MBYTES + default 0x0000007c if BAT4_LENGTH_4_MBYTES + default 0x000000fc if BAT4_LENGTH_8_MBYTES + default 0x000001fc if BAT4_LENGTH_16_MBYTES + default 0x000003fc if BAT4_LENGTH_32_MBYTES + default 0x000007fc if BAT4_LENGTH_64_MBYTES + default 0x00000ffc if BAT4_LENGTH_128_MBYTES + default 0x00001ffc if BAT4_LENGTH_256_MBYTES + +config BAT4_PAGE_PROTECTION + hex + default 0x0 if BAT4_ACCESS_NONE + default 0x1 if BAT4_ACCESS_RO + default 0x2 if BAT4_ACCESS_RW + +config BAT4_WIMG_ICACHE + hex + default 0x0 if !BAT4_ICACHE_WRITETHROUGH && !BAT4_ICACHE_INHIBITED && !BAT4_ICACHE_MEMORYCOHERENCE && !BAT4_ICACHE_GUARDED + default 0x8 if !BAT4_ICACHE_WRITETHROUGH && !BAT4_ICACHE_INHIBITED && !BAT4_ICACHE_MEMORYCOHERENCE && BAT4_ICACHE_GUARDED + default 0x10 if !BAT4_ICACHE_WRITETHROUGH && !BAT4_ICACHE_INHIBITED && BAT4_ICACHE_MEMORYCOHERENCE && !BAT4_ICACHE_GUARDED + default 0x18 if !BAT4_ICACHE_WRITETHROUGH && !BAT4_ICACHE_INHIBITED && BAT4_ICACHE_MEMORYCOHERENCE && BAT4_ICACHE_GUARDED + default 0x20 if !BAT4_ICACHE_WRITETHROUGH && BAT4_ICACHE_INHIBITED && !BAT4_ICACHE_MEMORYCOHERENCE && !BAT4_ICACHE_GUARDED + default 0x28 if !BAT4_ICACHE_WRITETHROUGH && BAT4_ICACHE_INHIBITED && !BAT4_ICACHE_MEMORYCOHERENCE && BAT4_ICACHE_GUARDED + default 0x30 if !BAT4_ICACHE_WRITETHROUGH && BAT4_ICACHE_INHIBITED && BAT4_ICACHE_MEMORYCOHERENCE && !BAT4_ICACHE_GUARDED + default 0x38 if !BAT4_ICACHE_WRITETHROUGH && BAT4_ICACHE_INHIBITED && BAT4_ICACHE_MEMORYCOHERENCE && BAT4_ICACHE_GUARDED + default 0x40 if BAT4_ICACHE_WRITETHROUGH && !BAT4_ICACHE_INHIBITED && !BAT4_ICACHE_MEMORYCOHERENCE && !BAT4_ICACHE_GUARDED + default 0x48 if BAT4_ICACHE_WRITETHROUGH && !BAT4_ICACHE_INHIBITED && !BAT4_ICACHE_MEMORYCOHERENCE && BAT4_ICACHE_GUARDED + default 0x50 if BAT4_ICACHE_WRITETHROUGH && !BAT4_ICACHE_INHIBITED && BAT4_ICACHE_MEMORYCOHERENCE && !BAT4_ICACHE_GUARDED + default 0x58 if BAT4_ICACHE_WRITETHROUGH && !BAT4_ICACHE_INHIBITED && BAT4_ICACHE_MEMORYCOHERENCE && BAT4_ICACHE_GUARDED + default 0x60 if BAT4_ICACHE_WRITETHROUGH && BAT4_ICACHE_INHIBITED && !BAT4_ICACHE_MEMORYCOHERENCE && !BAT4_ICACHE_GUARDED + default 0x68 if BAT4_ICACHE_WRITETHROUGH && BAT4_ICACHE_INHIBITED && !BAT4_ICACHE_MEMORYCOHERENCE && BAT4_ICACHE_GUARDED + default 0x70 if BAT4_ICACHE_WRITETHROUGH && BAT4_ICACHE_INHIBITED && BAT4_ICACHE_MEMORYCOHERENCE && !BAT4_ICACHE_GUARDED + default 0x78 if BAT4_ICACHE_WRITETHROUGH && BAT4_ICACHE_INHIBITED && BAT4_ICACHE_MEMORYCOHERENCE && BAT4_ICACHE_GUARDED + +config BAT4_WIMG_DCACHE + hex + default 0x0 if !BAT4_DCACHE_WRITETHROUGH && !BAT4_DCACHE_INHIBITED && !BAT4_DCACHE_MEMORYCOHERENCE && !BAT4_DCACHE_GUARDED + default 0x8 if !BAT4_DCACHE_WRITETHROUGH && !BAT4_DCACHE_INHIBITED && !BAT4_DCACHE_MEMORYCOHERENCE && BAT4_DCACHE_GUARDED + default 0x10 if !BAT4_DCACHE_WRITETHROUGH && !BAT4_DCACHE_INHIBITED && BAT4_DCACHE_MEMORYCOHERENCE && !BAT4_DCACHE_GUARDED + default 0x18 if !BAT4_DCACHE_WRITETHROUGH && !BAT4_DCACHE_INHIBITED && BAT4_DCACHE_MEMORYCOHERENCE && BAT4_DCACHE_GUARDED + default 0x20 if !BAT4_DCACHE_WRITETHROUGH && BAT4_DCACHE_INHIBITED && !BAT4_DCACHE_MEMORYCOHERENCE && !BAT4_DCACHE_GUARDED + default 0x28 if !BAT4_DCACHE_WRITETHROUGH && BAT4_DCACHE_INHIBITED && !BAT4_DCACHE_MEMORYCOHERENCE && BAT4_DCACHE_GUARDED + default 0x30 if !BAT4_DCACHE_WRITETHROUGH && BAT4_DCACHE_INHIBITED && BAT4_DCACHE_MEMORYCOHERENCE && !BAT4_DCACHE_GUARDED + default 0x38 if !BAT4_DCACHE_WRITETHROUGH && BAT4_DCACHE_INHIBITED && BAT4_DCACHE_MEMORYCOHERENCE && BAT4_DCACHE_GUARDED + default 0x40 if BAT4_DCACHE_WRITETHROUGH && !BAT4_DCACHE_INHIBITED && !BAT4_DCACHE_MEMORYCOHERENCE && !BAT4_DCACHE_GUARDED + default 0x48 if BAT4_DCACHE_WRITETHROUGH && !BAT4_DCACHE_INHIBITED && !BAT4_DCACHE_MEMORYCOHERENCE && BAT4_DCACHE_GUARDED + default 0x50 if BAT4_DCACHE_WRITETHROUGH && !BAT4_DCACHE_INHIBITED && BAT4_DCACHE_MEMORYCOHERENCE && !BAT4_DCACHE_GUARDED + default 0x58 if BAT4_DCACHE_WRITETHROUGH && !BAT4_DCACHE_INHIBITED && BAT4_DCACHE_MEMORYCOHERENCE && BAT4_DCACHE_GUARDED + default 0x60 if BAT4_DCACHE_WRITETHROUGH && BAT4_DCACHE_INHIBITED && !BAT4_DCACHE_MEMORYCOHERENCE && !BAT4_DCACHE_GUARDED + default 0x68 if BAT4_DCACHE_WRITETHROUGH && BAT4_DCACHE_INHIBITED && !BAT4_DCACHE_MEMORYCOHERENCE && BAT4_DCACHE_GUARDED + default 0x70 if BAT4_DCACHE_WRITETHROUGH && BAT4_DCACHE_INHIBITED && BAT4_DCACHE_MEMORYCOHERENCE && !BAT4_DCACHE_GUARDED + default 0x78 if BAT4_DCACHE_WRITETHROUGH && BAT4_DCACHE_INHIBITED && BAT4_DCACHE_MEMORYCOHERENCE && BAT4_DCACHE_GUARDED + +config BAT4_VALID_BITS + hex + default 0x0 if !BAT4_SUPERVISOR_MODE_VALID && !BAT4_USER_MODE_VALID + default 0x1 if !BAT4_SUPERVISOR_MODE_VALID && BAT4_USER_MODE_VALID + default 0x2 if BAT4_SUPERVISOR_MODE_VALID && !BAT4_USER_MODE_VALID + default 0x3 if BAT4_SUPERVISOR_MODE_VALID && BAT4_USER_MODE_VALID + +menuconfig BAT5 + bool "BAT5" + +if BAT5 + +config BAT5_NAME + string "Identifier" + +config BAT5_BASE + hex "Base" + +choice + prompt "Block length" + +config BAT5_LENGTH_128_KBYTES + bool "128 kb" + +config BAT5_LENGTH_256_KBYTES + bool "256 kb" + +config BAT5_LENGTH_512_KBYTES + bool "512 kb" + +config BAT5_LENGTH_1_MBYTES + bool "1 mb" + +config BAT5_LENGTH_2_MBYTES + bool "2 mb" + +config BAT5_LENGTH_4_MBYTES + bool "4 mb" + +config BAT5_LENGTH_8_MBYTES + bool "8 mb" + +config BAT5_LENGTH_16_MBYTES + bool "16 mb" + +config BAT5_LENGTH_32_MBYTES + bool "32 mb" + +config BAT5_LENGTH_64_MBYTES + bool "64 mb" + +config BAT5_LENGTH_128_MBYTES + bool "128 mb" + +config BAT5_LENGTH_256_MBYTES + bool "256 mb" +endchoice + +choice + prompt "Protection mode" + +config BAT5_ACCESS_NONE + bool "No access" + +config BAT5_ACCESS_RO + bool "Read-only" + +config BAT5_ACCESS_RW + bool "Read-write" + +endchoice + +config BAT5_ICACHE_WRITETHROUGH + bool "I-cache Write-through" + +config BAT5_ICACHE_INHIBITED + bool "I-cache Inhibited" + +config BAT5_ICACHE_MEMORYCOHERENCE + bool "I-cache Memory coherence" + +config BAT5_ICACHE_GUARDED + bool "I-cache Guarded" + +config BAT5_DCACHE_WRITETHROUGH + bool "D-cache Write-through" + +config BAT5_DCACHE_INHIBITED + bool "D-cache Inhibited" + +config BAT5_DCACHE_MEMORYCOHERENCE + bool "D-cache Memory coherence" + +config BAT5_DCACHE_GUARDED + bool "D-cache Guarded" + +config BAT5_USER_MODE_VALID + bool "User mode valid" + +config BAT5_SUPERVISOR_MODE_VALID + bool "Supervisor mode valid" + +endif + +config BAT5_LENGTH + hex + default 0x00000000 if BAT5_LENGTH_128_KBYTES + default 0x00000004 if BAT5_LENGTH_256_KBYTES + default 0x0000000c if BAT5_LENGTH_512_KBYTES + default 0x0000001c if BAT5_LENGTH_1_MBYTES + default 0x0000003c if BAT5_LENGTH_2_MBYTES + default 0x0000007c if BAT5_LENGTH_4_MBYTES + default 0x000000fc if BAT5_LENGTH_8_MBYTES + default 0x000001fc if BAT5_LENGTH_16_MBYTES + default 0x000003fc if BAT5_LENGTH_32_MBYTES + default 0x000007fc if BAT5_LENGTH_64_MBYTES + default 0x00000ffc if BAT5_LENGTH_128_MBYTES + default 0x00001ffc if BAT5_LENGTH_256_MBYTES + +config BAT5_PAGE_PROTECTION + hex + default 0x0 if BAT5_ACCESS_NONE + default 0x1 if BAT5_ACCESS_RO + default 0x2 if BAT5_ACCESS_RW + +config BAT5_WIMG_ICACHE + hex + default 0x0 if !BAT5_ICACHE_WRITETHROUGH && !BAT5_ICACHE_INHIBITED && !BAT5_ICACHE_MEMORYCOHERENCE && !BAT5_ICACHE_GUARDED + default 0x8 if !BAT5_ICACHE_WRITETHROUGH && !BAT5_ICACHE_INHIBITED && !BAT5_ICACHE_MEMORYCOHERENCE && BAT5_ICACHE_GUARDED + default 0x10 if !BAT5_ICACHE_WRITETHROUGH && !BAT5_ICACHE_INHIBITED && BAT5_ICACHE_MEMORYCOHERENCE && !BAT5_ICACHE_GUARDED + default 0x18 if !BAT5_ICACHE_WRITETHROUGH && !BAT5_ICACHE_INHIBITED && BAT5_ICACHE_MEMORYCOHERENCE && BAT5_ICACHE_GUARDED + default 0x20 if !BAT5_ICACHE_WRITETHROUGH && BAT5_ICACHE_INHIBITED && !BAT5_ICACHE_MEMORYCOHERENCE && !BAT5_ICACHE_GUARDED + default 0x28 if !BAT5_ICACHE_WRITETHROUGH && BAT5_ICACHE_INHIBITED && !BAT5_ICACHE_MEMORYCOHERENCE && BAT5_ICACHE_GUARDED + default 0x30 if !BAT5_ICACHE_WRITETHROUGH && BAT5_ICACHE_INHIBITED && BAT5_ICACHE_MEMORYCOHERENCE && !BAT5_ICACHE_GUARDED + default 0x38 if !BAT5_ICACHE_WRITETHROUGH && BAT5_ICACHE_INHIBITED && BAT5_ICACHE_MEMORYCOHERENCE && BAT5_ICACHE_GUARDED + default 0x40 if BAT5_ICACHE_WRITETHROUGH && !BAT5_ICACHE_INHIBITED && !BAT5_ICACHE_MEMORYCOHERENCE && !BAT5_ICACHE_GUARDED + default 0x48 if BAT5_ICACHE_WRITETHROUGH && !BAT5_ICACHE_INHIBITED && !BAT5_ICACHE_MEMORYCOHERENCE && BAT5_ICACHE_GUARDED + default 0x50 if BAT5_ICACHE_WRITETHROUGH && !BAT5_ICACHE_INHIBITED && BAT5_ICACHE_MEMORYCOHERENCE && !BAT5_ICACHE_GUARDED + default 0x58 if BAT5_ICACHE_WRITETHROUGH && !BAT5_ICACHE_INHIBITED && BAT5_ICACHE_MEMORYCOHERENCE && BAT5_ICACHE_GUARDED + default 0x60 if BAT5_ICACHE_WRITETHROUGH && BAT5_ICACHE_INHIBITED && !BAT5_ICACHE_MEMORYCOHERENCE && !BAT5_ICACHE_GUARDED + default 0x68 if BAT5_ICACHE_WRITETHROUGH && BAT5_ICACHE_INHIBITED && !BAT5_ICACHE_MEMORYCOHERENCE && BAT5_ICACHE_GUARDED + default 0x70 if BAT5_ICACHE_WRITETHROUGH && BAT5_ICACHE_INHIBITED && BAT5_ICACHE_MEMORYCOHERENCE && !BAT5_ICACHE_GUARDED + default 0x78 if BAT5_ICACHE_WRITETHROUGH && BAT5_ICACHE_INHIBITED && BAT5_ICACHE_MEMORYCOHERENCE && BAT5_ICACHE_GUARDED + +config BAT5_WIMG_DCACHE + hex + default 0x0 if !BAT5_DCACHE_WRITETHROUGH && !BAT5_DCACHE_INHIBITED && !BAT5_DCACHE_MEMORYCOHERENCE && !BAT5_DCACHE_GUARDED + default 0x8 if !BAT5_DCACHE_WRITETHROUGH && !BAT5_DCACHE_INHIBITED && !BAT5_DCACHE_MEMORYCOHERENCE && BAT5_DCACHE_GUARDED + default 0x10 if !BAT5_DCACHE_WRITETHROUGH && !BAT5_DCACHE_INHIBITED && BAT5_DCACHE_MEMORYCOHERENCE && !BAT5_DCACHE_GUARDED + default 0x18 if !BAT5_DCACHE_WRITETHROUGH && !BAT5_DCACHE_INHIBITED && BAT5_DCACHE_MEMORYCOHERENCE && BAT5_DCACHE_GUARDED + default 0x20 if !BAT5_DCACHE_WRITETHROUGH && BAT5_DCACHE_INHIBITED && !BAT5_DCACHE_MEMORYCOHERENCE && !BAT5_DCACHE_GUARDED + default 0x28 if !BAT5_DCACHE_WRITETHROUGH && BAT5_DCACHE_INHIBITED && !BAT5_DCACHE_MEMORYCOHERENCE && BAT5_DCACHE_GUARDED + default 0x30 if !BAT5_DCACHE_WRITETHROUGH && BAT5_DCACHE_INHIBITED && BAT5_DCACHE_MEMORYCOHERENCE && !BAT5_DCACHE_GUARDED + default 0x38 if !BAT5_DCACHE_WRITETHROUGH && BAT5_DCACHE_INHIBITED && BAT5_DCACHE_MEMORYCOHERENCE && BAT5_DCACHE_GUARDED + default 0x40 if BAT5_DCACHE_WRITETHROUGH && !BAT5_DCACHE_INHIBITED && !BAT5_DCACHE_MEMORYCOHERENCE && !BAT5_DCACHE_GUARDED + default 0x48 if BAT5_DCACHE_WRITETHROUGH && !BAT5_DCACHE_INHIBITED && !BAT5_DCACHE_MEMORYCOHERENCE && BAT5_DCACHE_GUARDED + default 0x50 if BAT5_DCACHE_WRITETHROUGH && !BAT5_DCACHE_INHIBITED && BAT5_DCACHE_MEMORYCOHERENCE && !BAT5_DCACHE_GUARDED + default 0x58 if BAT5_DCACHE_WRITETHROUGH && !BAT5_DCACHE_INHIBITED && BAT5_DCACHE_MEMORYCOHERENCE && BAT5_DCACHE_GUARDED + default 0x60 if BAT5_DCACHE_WRITETHROUGH && BAT5_DCACHE_INHIBITED && !BAT5_DCACHE_MEMORYCOHERENCE && !BAT5_DCACHE_GUARDED + default 0x68 if BAT5_DCACHE_WRITETHROUGH && BAT5_DCACHE_INHIBITED && !BAT5_DCACHE_MEMORYCOHERENCE && BAT5_DCACHE_GUARDED + default 0x70 if BAT5_DCACHE_WRITETHROUGH && BAT5_DCACHE_INHIBITED && BAT5_DCACHE_MEMORYCOHERENCE && !BAT5_DCACHE_GUARDED + default 0x78 if BAT5_DCACHE_WRITETHROUGH && BAT5_DCACHE_INHIBITED && BAT5_DCACHE_MEMORYCOHERENCE && BAT5_DCACHE_GUARDED + +config BAT5_VALID_BITS + hex + default 0x0 if !BAT5_SUPERVISOR_MODE_VALID && !BAT5_USER_MODE_VALID + default 0x1 if !BAT5_SUPERVISOR_MODE_VALID && BAT5_USER_MODE_VALID + default 0x2 if BAT5_SUPERVISOR_MODE_VALID && !BAT5_USER_MODE_VALID + default 0x3 if BAT5_SUPERVISOR_MODE_VALID && BAT5_USER_MODE_VALID + +menuconfig BAT6 + bool "BAT6" + +if BAT6 + +config BAT6_NAME + string "Identifier" + +config BAT6_BASE + hex "Base" + +choice + prompt "Block length" + +config BAT6_LENGTH_128_KBYTES + bool "128 kb" + +config BAT6_LENGTH_256_KBYTES + bool "256 kb" + +config BAT6_LENGTH_512_KBYTES + bool "512 kb" + +config BAT6_LENGTH_1_MBYTES + bool "1 mb" + +config BAT6_LENGTH_2_MBYTES + bool "2 mb" + +config BAT6_LENGTH_4_MBYTES + bool "4 mb" + +config BAT6_LENGTH_8_MBYTES + bool "8 mb" + +config BAT6_LENGTH_16_MBYTES + bool "16 mb" + +config BAT6_LENGTH_32_MBYTES + bool "32 mb" + +config BAT6_LENGTH_64_MBYTES + bool "64 mb" + +config BAT6_LENGTH_128_MBYTES + bool "128 mb" + +config BAT6_LENGTH_256_MBYTES + bool "256 mb" +endchoice + +choice + prompt "Protection mode" + +config BAT6_ACCESS_NONE + bool "No access" + +config BAT6_ACCESS_RO + bool "Read-only" + +config BAT6_ACCESS_RW + bool "Read-write" + +endchoice + +config BAT6_ICACHE_WRITETHROUGH + bool "I-cache Write-through" + +config BAT6_ICACHE_INHIBITED + bool "I-cache Inhibited" + +config BAT6_ICACHE_MEMORYCOHERENCE + bool "I-cache Memory coherence" + +config BAT6_ICACHE_GUARDED + bool "I-cache Guarded" + +config BAT6_DCACHE_WRITETHROUGH + bool "D-cache Write-through" + +config BAT6_DCACHE_INHIBITED + bool "D-cache Inhibited" + +config BAT6_DCACHE_MEMORYCOHERENCE + bool "D-cache Memory coherence" + +config BAT6_DCACHE_GUARDED + bool "D-cache Guarded" + +config BAT6_USER_MODE_VALID + bool "User mode valid" + +config BAT6_SUPERVISOR_MODE_VALID + bool "Supervisor mode valid" + +endif + +config BAT6_LENGTH + hex + default 0x00000000 if BAT6_LENGTH_128_KBYTES + default 0x00000004 if BAT6_LENGTH_256_KBYTES + default 0x0000000c if BAT6_LENGTH_512_KBYTES + default 0x0000001c if BAT6_LENGTH_1_MBYTES + default 0x0000003c if BAT6_LENGTH_2_MBYTES + default 0x0000007c if BAT6_LENGTH_4_MBYTES + default 0x000000fc if BAT6_LENGTH_8_MBYTES + default 0x000001fc if BAT6_LENGTH_16_MBYTES + default 0x000003fc if BAT6_LENGTH_32_MBYTES + default 0x000007fc if BAT6_LENGTH_64_MBYTES + default 0x00000ffc if BAT6_LENGTH_128_MBYTES + default 0x00001ffc if BAT6_LENGTH_256_MBYTES + +config BAT6_PAGE_PROTECTION + hex + default 0x0 if BAT6_ACCESS_NONE + default 0x1 if BAT6_ACCESS_RO + default 0x2 if BAT6_ACCESS_RW + +config BAT6_WIMG_ICACHE + hex + default 0x0 if !BAT6_ICACHE_WRITETHROUGH && !BAT6_ICACHE_INHIBITED && !BAT6_ICACHE_MEMORYCOHERENCE && !BAT6_ICACHE_GUARDED + default 0x8 if !BAT6_ICACHE_WRITETHROUGH && !BAT6_ICACHE_INHIBITED && !BAT6_ICACHE_MEMORYCOHERENCE && BAT6_ICACHE_GUARDED + default 0x10 if !BAT6_ICACHE_WRITETHROUGH && !BAT6_ICACHE_INHIBITED && BAT6_ICACHE_MEMORYCOHERENCE && !BAT6_ICACHE_GUARDED + default 0x18 if !BAT6_ICACHE_WRITETHROUGH && !BAT6_ICACHE_INHIBITED && BAT6_ICACHE_MEMORYCOHERENCE && BAT6_ICACHE_GUARDED + default 0x20 if !BAT6_ICACHE_WRITETHROUGH && BAT6_ICACHE_INHIBITED && !BAT6_ICACHE_MEMORYCOHERENCE && !BAT6_ICACHE_GUARDED + default 0x28 if !BAT6_ICACHE_WRITETHROUGH && BAT6_ICACHE_INHIBITED && !BAT6_ICACHE_MEMORYCOHERENCE && BAT6_ICACHE_GUARDED + default 0x30 if !BAT6_ICACHE_WRITETHROUGH && BAT6_ICACHE_INHIBITED && BAT6_ICACHE_MEMORYCOHERENCE && !BAT6_ICACHE_GUARDED + default 0x38 if !BAT6_ICACHE_WRITETHROUGH && BAT6_ICACHE_INHIBITED && BAT6_ICACHE_MEMORYCOHERENCE && BAT6_ICACHE_GUARDED + default 0x40 if BAT6_ICACHE_WRITETHROUGH && !BAT6_ICACHE_INHIBITED && !BAT6_ICACHE_MEMORYCOHERENCE && !BAT6_ICACHE_GUARDED + default 0x48 if BAT6_ICACHE_WRITETHROUGH && !BAT6_ICACHE_INHIBITED && !BAT6_ICACHE_MEMORYCOHERENCE && BAT6_ICACHE_GUARDED + default 0x50 if BAT6_ICACHE_WRITETHROUGH && !BAT6_ICACHE_INHIBITED && BAT6_ICACHE_MEMORYCOHERENCE && !BAT6_ICACHE_GUARDED + default 0x58 if BAT6_ICACHE_WRITETHROUGH && !BAT6_ICACHE_INHIBITED && BAT6_ICACHE_MEMORYCOHERENCE && BAT6_ICACHE_GUARDED + default 0x60 if BAT6_ICACHE_WRITETHROUGH && BAT6_ICACHE_INHIBITED && !BAT6_ICACHE_MEMORYCOHERENCE && !BAT6_ICACHE_GUARDED + default 0x68 if BAT6_ICACHE_WRITETHROUGH && BAT6_ICACHE_INHIBITED && !BAT6_ICACHE_MEMORYCOHERENCE && BAT6_ICACHE_GUARDED + default 0x70 if BAT6_ICACHE_WRITETHROUGH && BAT6_ICACHE_INHIBITED && BAT6_ICACHE_MEMORYCOHERENCE && !BAT6_ICACHE_GUARDED + default 0x78 if BAT6_ICACHE_WRITETHROUGH && BAT6_ICACHE_INHIBITED && BAT6_ICACHE_MEMORYCOHERENCE && BAT6_ICACHE_GUARDED + +config BAT6_WIMG_DCACHE + hex + default 0x0 if !BAT6_DCACHE_WRITETHROUGH && !BAT6_DCACHE_INHIBITED && !BAT6_DCACHE_MEMORYCOHERENCE && !BAT6_DCACHE_GUARDED + default 0x8 if !BAT6_DCACHE_WRITETHROUGH && !BAT6_DCACHE_INHIBITED && !BAT6_DCACHE_MEMORYCOHERENCE && BAT6_DCACHE_GUARDED + default 0x10 if !BAT6_DCACHE_WRITETHROUGH && !BAT6_DCACHE_INHIBITED && BAT6_DCACHE_MEMORYCOHERENCE && !BAT6_DCACHE_GUARDED + default 0x18 if !BAT6_DCACHE_WRITETHROUGH && !BAT6_DCACHE_INHIBITED && BAT6_DCACHE_MEMORYCOHERENCE && BAT6_DCACHE_GUARDED + default 0x20 if !BAT6_DCACHE_WRITETHROUGH && BAT6_DCACHE_INHIBITED && !BAT6_DCACHE_MEMORYCOHERENCE && !BAT6_DCACHE_GUARDED + default 0x28 if !BAT6_DCACHE_WRITETHROUGH && BAT6_DCACHE_INHIBITED && !BAT6_DCACHE_MEMORYCOHERENCE && BAT6_DCACHE_GUARDED + default 0x30 if !BAT6_DCACHE_WRITETHROUGH && BAT6_DCACHE_INHIBITED && BAT6_DCACHE_MEMORYCOHERENCE && !BAT6_DCACHE_GUARDED + default 0x38 if !BAT6_DCACHE_WRITETHROUGH && BAT6_DCACHE_INHIBITED && BAT6_DCACHE_MEMORYCOHERENCE && BAT6_DCACHE_GUARDED + default 0x40 if BAT6_DCACHE_WRITETHROUGH && !BAT6_DCACHE_INHIBITED && !BAT6_DCACHE_MEMORYCOHERENCE && !BAT6_DCACHE_GUARDED + default 0x48 if BAT6_DCACHE_WRITETHROUGH && !BAT6_DCACHE_INHIBITED && !BAT6_DCACHE_MEMORYCOHERENCE && BAT6_DCACHE_GUARDED + default 0x50 if BAT6_DCACHE_WRITETHROUGH && !BAT6_DCACHE_INHIBITED && BAT6_DCACHE_MEMORYCOHERENCE && !BAT6_DCACHE_GUARDED + default 0x58 if BAT6_DCACHE_WRITETHROUGH && !BAT6_DCACHE_INHIBITED && BAT6_DCACHE_MEMORYCOHERENCE && BAT6_DCACHE_GUARDED + default 0x60 if BAT6_DCACHE_WRITETHROUGH && BAT6_DCACHE_INHIBITED && !BAT6_DCACHE_MEMORYCOHERENCE && !BAT6_DCACHE_GUARDED + default 0x68 if BAT6_DCACHE_WRITETHROUGH && BAT6_DCACHE_INHIBITED && !BAT6_DCACHE_MEMORYCOHERENCE && BAT6_DCACHE_GUARDED + default 0x70 if BAT6_DCACHE_WRITETHROUGH && BAT6_DCACHE_INHIBITED && BAT6_DCACHE_MEMORYCOHERENCE && !BAT6_DCACHE_GUARDED + default 0x78 if BAT6_DCACHE_WRITETHROUGH && BAT6_DCACHE_INHIBITED && BAT6_DCACHE_MEMORYCOHERENCE && BAT6_DCACHE_GUARDED + +config BAT6_VALID_BITS + hex + default 0x0 if !BAT6_SUPERVISOR_MODE_VALID && !BAT6_USER_MODE_VALID + default 0x1 if !BAT6_SUPERVISOR_MODE_VALID && BAT6_USER_MODE_VALID + default 0x2 if BAT6_SUPERVISOR_MODE_VALID && !BAT6_USER_MODE_VALID + default 0x3 if BAT6_SUPERVISOR_MODE_VALID && BAT6_USER_MODE_VALID + +menuconfig BAT7 + bool "BAT7" + +if BAT7 + +config BAT7_NAME + string "Identifier" + +config BAT7_BASE + hex "Base" + +choice + prompt "Block length" + +config BAT7_LENGTH_128_KBYTES + bool "128 kb" + +config BAT7_LENGTH_256_KBYTES + bool "256 kb" + +config BAT7_LENGTH_512_KBYTES + bool "512 kb" + +config BAT7_LENGTH_1_MBYTES + bool "1 mb" + +config BAT7_LENGTH_2_MBYTES + bool "2 mb" + +config BAT7_LENGTH_4_MBYTES + bool "4 mb" + +config BAT7_LENGTH_8_MBYTES + bool "8 mb" + +config BAT7_LENGTH_16_MBYTES + bool "16 mb" + +config BAT7_LENGTH_32_MBYTES + bool "32 mb" + +config BAT7_LENGTH_64_MBYTES + bool "64 mb" + +config BAT7_LENGTH_128_MBYTES + bool "128 mb" + +config BAT7_LENGTH_256_MBYTES + bool "256 mb" +endchoice + +choice + prompt "Protection mode" + +config BAT7_ACCESS_NONE + bool "No access" + +config BAT7_ACCESS_RO + bool "Read-only" + +config BAT7_ACCESS_RW + bool "Read-write" + +endchoice + +config BAT7_ICACHE_WRITETHROUGH + bool "I-cache Write-through" + +config BAT7_ICACHE_INHIBITED + bool "I-cache Inhibited" + +config BAT7_ICACHE_MEMORYCOHERENCE + bool "I-cache Memory coherence" + +config BAT7_ICACHE_GUARDED + bool "I-cache Guarded" + +config BAT7_DCACHE_WRITETHROUGH + bool "D-cache Write-through" + +config BAT7_DCACHE_INHIBITED + bool "D-cache Inhibited" + +config BAT7_DCACHE_MEMORYCOHERENCE + bool "D-cache Memory coherence" + +config BAT7_DCACHE_GUARDED + bool "D-cache Guarded" + +config BAT7_USER_MODE_VALID + bool "User mode valid" + +config BAT7_SUPERVISOR_MODE_VALID + bool "Supervisor mode valid" + +endif + +config BAT7_LENGTH + hex + default 0x00000000 if BAT7_LENGTH_128_KBYTES + default 0x00000004 if BAT7_LENGTH_256_KBYTES + default 0x0000000c if BAT7_LENGTH_512_KBYTES + default 0x0000001c if BAT7_LENGTH_1_MBYTES + default 0x0000003c if BAT7_LENGTH_2_MBYTES + default 0x0000007c if BAT7_LENGTH_4_MBYTES + default 0x000000fc if BAT7_LENGTH_8_MBYTES + default 0x000001fc if BAT7_LENGTH_16_MBYTES + default 0x000003fc if BAT7_LENGTH_32_MBYTES + default 0x000007fc if BAT7_LENGTH_64_MBYTES + default 0x00000ffc if BAT7_LENGTH_128_MBYTES + default 0x00001ffc if BAT7_LENGTH_256_MBYTES + +config BAT7_PAGE_PROTECTION + hex + default 0x0 if BAT7_ACCESS_NONE + default 0x1 if BAT7_ACCESS_RO + default 0x2 if BAT7_ACCESS_RW + +config BAT7_WIMG_ICACHE + hex + default 0x0 if !BAT7_ICACHE_WRITETHROUGH && !BAT7_ICACHE_INHIBITED && !BAT7_ICACHE_MEMORYCOHERENCE && !BAT7_ICACHE_GUARDED + default 0x8 if !BAT7_ICACHE_WRITETHROUGH && !BAT7_ICACHE_INHIBITED && !BAT7_ICACHE_MEMORYCOHERENCE && BAT7_ICACHE_GUARDED + default 0x10 if !BAT7_ICACHE_WRITETHROUGH && !BAT7_ICACHE_INHIBITED && BAT7_ICACHE_MEMORYCOHERENCE && !BAT7_ICACHE_GUARDED + default 0x18 if !BAT7_ICACHE_WRITETHROUGH && !BAT7_ICACHE_INHIBITED && BAT7_ICACHE_MEMORYCOHERENCE && BAT7_ICACHE_GUARDED + default 0x20 if !BAT7_ICACHE_WRITETHROUGH && BAT7_ICACHE_INHIBITED && !BAT7_ICACHE_MEMORYCOHERENCE && !BAT7_ICACHE_GUARDED + default 0x28 if !BAT7_ICACHE_WRITETHROUGH && BAT7_ICACHE_INHIBITED && !BAT7_ICACHE_MEMORYCOHERENCE && BAT7_ICACHE_GUARDED + default 0x30 if !BAT7_ICACHE_WRITETHROUGH && BAT7_ICACHE_INHIBITED && BAT7_ICACHE_MEMORYCOHERENCE && !BAT7_ICACHE_GUARDED + default 0x38 if !BAT7_ICACHE_WRITETHROUGH && BAT7_ICACHE_INHIBITED && BAT7_ICACHE_MEMORYCOHERENCE && BAT7_ICACHE_GUARDED + default 0x40 if BAT7_ICACHE_WRITETHROUGH && !BAT7_ICACHE_INHIBITED && !BAT7_ICACHE_MEMORYCOHERENCE && !BAT7_ICACHE_GUARDED + default 0x48 if BAT7_ICACHE_WRITETHROUGH && !BAT7_ICACHE_INHIBITED && !BAT7_ICACHE_MEMORYCOHERENCE && BAT7_ICACHE_GUARDED + default 0x50 if BAT7_ICACHE_WRITETHROUGH && !BAT7_ICACHE_INHIBITED && BAT7_ICACHE_MEMORYCOHERENCE && !BAT7_ICACHE_GUARDED + default 0x58 if BAT7_ICACHE_WRITETHROUGH && !BAT7_ICACHE_INHIBITED && BAT7_ICACHE_MEMORYCOHERENCE && BAT7_ICACHE_GUARDED + default 0x60 if BAT7_ICACHE_WRITETHROUGH && BAT7_ICACHE_INHIBITED && !BAT7_ICACHE_MEMORYCOHERENCE && !BAT7_ICACHE_GUARDED + default 0x68 if BAT7_ICACHE_WRITETHROUGH && BAT7_ICACHE_INHIBITED && !BAT7_ICACHE_MEMORYCOHERENCE && BAT7_ICACHE_GUARDED + default 0x70 if BAT7_ICACHE_WRITETHROUGH && BAT7_ICACHE_INHIBITED && BAT7_ICACHE_MEMORYCOHERENCE && !BAT7_ICACHE_GUARDED + default 0x78 if BAT7_ICACHE_WRITETHROUGH && BAT7_ICACHE_INHIBITED && BAT7_ICACHE_MEMORYCOHERENCE && BAT7_ICACHE_GUARDED + +config BAT7_WIMG_DCACHE + hex + default 0x0 if !BAT7_DCACHE_WRITETHROUGH && !BAT7_DCACHE_INHIBITED && !BAT7_DCACHE_MEMORYCOHERENCE && !BAT7_DCACHE_GUARDED + default 0x8 if !BAT7_DCACHE_WRITETHROUGH && !BAT7_DCACHE_INHIBITED && !BAT7_DCACHE_MEMORYCOHERENCE && BAT7_DCACHE_GUARDED + default 0x10 if !BAT7_DCACHE_WRITETHROUGH && !BAT7_DCACHE_INHIBITED && BAT7_DCACHE_MEMORYCOHERENCE && !BAT7_DCACHE_GUARDED + default 0x18 if !BAT7_DCACHE_WRITETHROUGH && !BAT7_DCACHE_INHIBITED && BAT7_DCACHE_MEMORYCOHERENCE && BAT7_DCACHE_GUARDED + default 0x20 if !BAT7_DCACHE_WRITETHROUGH && BAT7_DCACHE_INHIBITED && !BAT7_DCACHE_MEMORYCOHERENCE && !BAT7_DCACHE_GUARDED + default 0x28 if !BAT7_DCACHE_WRITETHROUGH && BAT7_DCACHE_INHIBITED && !BAT7_DCACHE_MEMORYCOHERENCE && BAT7_DCACHE_GUARDED + default 0x30 if !BAT7_DCACHE_WRITETHROUGH && BAT7_DCACHE_INHIBITED && BAT7_DCACHE_MEMORYCOHERENCE && !BAT7_DCACHE_GUARDED + default 0x38 if !BAT7_DCACHE_WRITETHROUGH && BAT7_DCACHE_INHIBITED && BAT7_DCACHE_MEMORYCOHERENCE && BAT7_DCACHE_GUARDED + default 0x40 if BAT7_DCACHE_WRITETHROUGH && !BAT7_DCACHE_INHIBITED && !BAT7_DCACHE_MEMORYCOHERENCE && !BAT7_DCACHE_GUARDED + default 0x48 if BAT7_DCACHE_WRITETHROUGH && !BAT7_DCACHE_INHIBITED && !BAT7_DCACHE_MEMORYCOHERENCE && BAT7_DCACHE_GUARDED + default 0x50 if BAT7_DCACHE_WRITETHROUGH && !BAT7_DCACHE_INHIBITED && BAT7_DCACHE_MEMORYCOHERENCE && !BAT7_DCACHE_GUARDED + default 0x58 if BAT7_DCACHE_WRITETHROUGH && !BAT7_DCACHE_INHIBITED && BAT7_DCACHE_MEMORYCOHERENCE && BAT7_DCACHE_GUARDED + default 0x60 if BAT7_DCACHE_WRITETHROUGH && BAT7_DCACHE_INHIBITED && !BAT7_DCACHE_MEMORYCOHERENCE && !BAT7_DCACHE_GUARDED + default 0x68 if BAT7_DCACHE_WRITETHROUGH && BAT7_DCACHE_INHIBITED && !BAT7_DCACHE_MEMORYCOHERENCE && BAT7_DCACHE_GUARDED + default 0x70 if BAT7_DCACHE_WRITETHROUGH && BAT7_DCACHE_INHIBITED && BAT7_DCACHE_MEMORYCOHERENCE && !BAT7_DCACHE_GUARDED + default 0x78 if BAT7_DCACHE_WRITETHROUGH && BAT7_DCACHE_INHIBITED && BAT7_DCACHE_MEMORYCOHERENCE && BAT7_DCACHE_GUARDED + +config BAT7_VALID_BITS + hex + default 0x0 if !BAT7_SUPERVISOR_MODE_VALID && !BAT7_USER_MODE_VALID + default 0x1 if !BAT7_SUPERVISOR_MODE_VALID && BAT7_USER_MODE_VALID + default 0x2 if BAT7_SUPERVISOR_MODE_VALID && !BAT7_USER_MODE_VALID + default 0x3 if BAT7_SUPERVISOR_MODE_VALID && BAT7_USER_MODE_VALID + +endif + +endmenu diff --git a/arch/powerpc/cpu/mpc83xx/bats/bats.h b/arch/powerpc/cpu/mpc83xx/bats/bats.h new file mode 100644 index 0000000000..f0754c2351 --- /dev/null +++ b/arch/powerpc/cpu/mpc83xx/bats/bats.h @@ -0,0 +1,223 @@ +#ifdef CONFIG_BAT0 +#define CONFIG_SYS_IBAT0L (\ + (CONFIG_BAT0_BASE) |\ + (CONFIG_BAT0_PAGE_PROTECTION) |\ + (CONFIG_BAT0_WIMG_ICACHE) \ + ) +#define CONFIG_SYS_IBAT0U (\ + (CONFIG_BAT0_BASE) |\ + (CONFIG_BAT0_LENGTH) |\ + (CONFIG_BAT0_VALID_BITS) \ + ) +#define CONFIG_SYS_DBAT0L (\ + (CONFIG_BAT0_BASE) |\ + (CONFIG_BAT0_PAGE_PROTECTION) |\ + (CONFIG_BAT0_WIMG_DCACHE) \ + ) +#define CONFIG_SYS_DBAT0U (\ + (CONFIG_BAT0_BASE) |\ + (CONFIG_BAT0_LENGTH) |\ + (CONFIG_BAT0_VALID_BITS) \ + ) +#else +#define CONFIG_SYS_IBAT0L (0) +#define CONFIG_SYS_IBAT0U (0) +#define CONFIG_SYS_DBAT0L (0) +#define CONFIG_SYS_DBAT0U (0) +#endif /* CONFIG_BAT0 */ + +#ifdef CONFIG_BAT1 +#define CONFIG_SYS_IBAT1L (\ + (CONFIG_BAT1_BASE) |\ + (CONFIG_BAT1_PAGE_PROTECTION) |\ + (CONFIG_BAT1_WIMG_ICACHE) \ + ) +#define CONFIG_SYS_IBAT1U (\ + (CONFIG_BAT1_BASE) |\ + (CONFIG_BAT1_LENGTH) |\ + (CONFIG_BAT1_VALID_BITS) \ + ) +#define CONFIG_SYS_DBAT1L (\ + (CONFIG_BAT1_BASE) |\ + (CONFIG_BAT1_PAGE_PROTECTION) |\ + (CONFIG_BAT1_WIMG_DCACHE) \ + ) +#define CONFIG_SYS_DBAT1U (\ + (CONFIG_BAT1_BASE) |\ + (CONFIG_BAT1_LENGTH) |\ + (CONFIG_BAT1_VALID_BITS) \ + ) +#else +#define CONFIG_SYS_IBAT1L (0) +#define CONFIG_SYS_IBAT1U (0) +#define CONFIG_SYS_DBAT1L (0) +#define CONFIG_SYS_DBAT1U (0) +#endif /* CONFIG_BAT1 */ + +#ifdef CONFIG_BAT2 +#define CONFIG_SYS_IBAT2L (\ + (CONFIG_BAT2_BASE) |\ + (CONFIG_BAT2_PAGE_PROTECTION) |\ + (CONFIG_BAT2_WIMG_ICACHE) \ + ) +#define CONFIG_SYS_IBAT2U (\ + (CONFIG_BAT2_BASE) |\ + (CONFIG_BAT2_LENGTH) |\ + (CONFIG_BAT2_VALID_BITS) \ + ) +#define CONFIG_SYS_DBAT2L (\ + (CONFIG_BAT2_BASE) |\ + (CONFIG_BAT2_PAGE_PROTECTION) |\ + (CONFIG_BAT2_WIMG_DCACHE) \ + ) +#define CONFIG_SYS_DBAT2U (\ + (CONFIG_BAT2_BASE) |\ + (CONFIG_BAT2_LENGTH) |\ + (CONFIG_BAT2_VALID_BITS) \ + ) +#else +#define CONFIG_SYS_IBAT2L (0) +#define CONFIG_SYS_IBAT2U (0) +#define CONFIG_SYS_DBAT2L (0) +#define CONFIG_SYS_DBAT2U (0) +#endif /* CONFIG_BAT2 */ + +#ifdef CONFIG_BAT3 +#define CONFIG_SYS_IBAT3L (\ + (CONFIG_BAT3_BASE) |\ + (CONFIG_BAT3_PAGE_PROTECTION) |\ + (CONFIG_BAT3_WIMG_ICACHE) \ + ) +#define CONFIG_SYS_IBAT3U (\ + (CONFIG_BAT3_BASE) |\ + (CONFIG_BAT3_LENGTH) |\ + (CONFIG_BAT3_VALID_BITS) \ + ) +#define CONFIG_SYS_DBAT3L (\ + (CONFIG_BAT3_BASE) |\ + (CONFIG_BAT3_PAGE_PROTECTION) |\ + (CONFIG_BAT3_WIMG_DCACHE) \ + ) +#define CONFIG_SYS_DBAT3U (\ + (CONFIG_BAT3_BASE) |\ + (CONFIG_BAT3_LENGTH) |\ + (CONFIG_BAT3_VALID_BITS) \ + ) +#else +#define CONFIG_SYS_IBAT3L (0) +#define CONFIG_SYS_IBAT3U (0) +#define CONFIG_SYS_DBAT3L (0) +#define CONFIG_SYS_DBAT3U (0) +#endif /* CONFIG_BAT3 */ + +#ifdef CONFIG_BAT4 +#define CONFIG_SYS_IBAT4L (\ + (CONFIG_BAT4_BASE) |\ + (CONFIG_BAT4_PAGE_PROTECTION) |\ + (CONFIG_BAT4_WIMG_ICACHE) \ + ) +#define CONFIG_SYS_IBAT4U (\ + (CONFIG_BAT4_BASE) |\ + (CONFIG_BAT4_LENGTH) |\ + (CONFIG_BAT4_VALID_BITS) \ + ) +#define CONFIG_SYS_DBAT4L (\ + (CONFIG_BAT4_BASE) |\ + (CONFIG_BAT4_PAGE_PROTECTION) |\ + (CONFIG_BAT4_WIMG_DCACHE) \ + ) +#define CONFIG_SYS_DBAT4U (\ + (CONFIG_BAT4_BASE) |\ + (CONFIG_BAT4_LENGTH) |\ + (CONFIG_BAT4_VALID_BITS) \ + ) +#else +#define CONFIG_SYS_IBAT4L (0) +#define CONFIG_SYS_IBAT4U (0) +#define CONFIG_SYS_DBAT4L (0) +#define CONFIG_SYS_DBAT4U (0) +#endif /* CONFIG_BAT4 */ + +#ifdef CONFIG_BAT5 +#define CONFIG_SYS_IBAT5L (\ + (CONFIG_BAT5_BASE) |\ + (CONFIG_BAT5_PAGE_PROTECTION) |\ + (CONFIG_BAT5_WIMG_ICACHE) \ + ) +#define CONFIG_SYS_IBAT5U (\ + (CONFIG_BAT5_BASE) |\ + (CONFIG_BAT5_LENGTH) |\ + (CONFIG_BAT5_VALID_BITS) \ + ) +#define CONFIG_SYS_DBAT5L (\ + (CONFIG_BAT5_BASE) |\ + (CONFIG_BAT5_PAGE_PROTECTION) |\ + (CONFIG_BAT5_WIMG_DCACHE) \ + ) +#define CONFIG_SYS_DBAT5U (\ + (CONFIG_BAT5_BASE) |\ + (CONFIG_BAT5_LENGTH) |\ + (CONFIG_BAT5_VALID_BITS) \ + ) +#else +#define CONFIG_SYS_IBAT5L (0) +#define CONFIG_SYS_IBAT5U (0) +#define CONFIG_SYS_DBAT5L (0) +#define CONFIG_SYS_DBAT5U (0) +#endif /* CONFIG_BAT5 */ + +#ifdef CONFIG_BAT6 +#define CONFIG_SYS_IBAT6L (\ + (CONFIG_BAT6_BASE) |\ + (CONFIG_BAT6_PAGE_PROTECTION) |\ + (CONFIG_BAT6_WIMG_ICACHE) \ + ) +#define CONFIG_SYS_IBAT6U (\ + (CONFIG_BAT6_BASE) |\ + (CONFIG_BAT6_LENGTH) |\ + (CONFIG_BAT6_VALID_BITS) \ + ) +#define CONFIG_SYS_DBAT6L (\ + (CONFIG_BAT6_BASE) |\ + (CONFIG_BAT6_PAGE_PROTECTION) |\ + (CONFIG_BAT6_WIMG_DCACHE) \ + ) +#define CONFIG_SYS_DBAT6U (\ + (CONFIG_BAT6_BASE) |\ + (CONFIG_BAT6_LENGTH) |\ + (CONFIG_BAT6_VALID_BITS) \ + ) +#else +#define CONFIG_SYS_IBAT6L (0) +#define CONFIG_SYS_IBAT6U (0) +#define CONFIG_SYS_DBAT6L (0) +#define CONFIG_SYS_DBAT6U (0) +#endif /* CONFIG_BAT6 */ + +#ifdef CONFIG_BAT7 +#define CONFIG_SYS_IBAT7L (\ + (CONFIG_BAT7_BASE) |\ + (CONFIG_BAT7_PAGE_PROTECTION) |\ + (CONFIG_BAT7_WIMG_ICACHE) \ + ) +#define CONFIG_SYS_IBAT7U (\ + (CONFIG_BAT7_BASE) |\ + (CONFIG_BAT7_LENGTH) |\ + (CONFIG_BAT7_VALID_BITS) \ + ) +#define CONFIG_SYS_DBAT7L (\ + (CONFIG_BAT7_BASE) |\ + (CONFIG_BAT7_PAGE_PROTECTION) |\ + (CONFIG_BAT7_WIMG_DCACHE) \ + ) +#define CONFIG_SYS_DBAT7U (\ + (CONFIG_BAT7_BASE) |\ + (CONFIG_BAT7_LENGTH) |\ + (CONFIG_BAT7_VALID_BITS) \ + ) +#else +#define CONFIG_SYS_IBAT7L (0) +#define CONFIG_SYS_IBAT7U (0) +#define CONFIG_SYS_DBAT7L (0) +#define CONFIG_SYS_DBAT7U (0) +#endif /* CONFIG_BAT7 */ diff --git a/arch/powerpc/cpu/mpc83xx/start.S b/arch/powerpc/cpu/mpc83xx/start.S index 77170a7424..f7fc922af0 100644 --- a/arch/powerpc/cpu/mpc83xx/start.S +++ b/arch/powerpc/cpu/mpc83xx/start.S @@ -25,6 +25,7 @@ #include #include "hrcw/hrcw.h" +#include "bats/bats.h" /* We don't want the MMU yet. */ diff --git a/configs/MPC8308RDB_defconfig b/configs/MPC8308RDB_defconfig index 042f6aa010..14136f6b67 100644 --- a/configs/MPC8308RDB_defconfig +++ b/configs/MPC8308RDB_defconfig @@ -10,6 +10,42 @@ CONFIG_BOOT_MEMORY_SPACE_LOW=y CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_TSEC1_MODE_RGMII=y CONFIG_TSEC2_MODE_RGMII=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="DDR" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_128_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT1=y +CONFIG_BAT1_NAME="IMMRBAR" +CONFIG_BAT1_BASE=0xE0000000 +CONFIG_BAT1_LENGTH_8_MBYTES=y +CONFIG_BAT1_ACCESS_RW=y +CONFIG_BAT1_ICACHE_INHIBITED=y +CONFIG_BAT1_ICACHE_GUARDED=y +CONFIG_BAT1_DCACHE_INHIBITED=y +CONFIG_BAT1_DCACHE_GUARDED=y +CONFIG_BAT1_USER_MODE_VALID=y +CONFIG_BAT1_SUPERVISOR_MODE_VALID=y +CONFIG_BAT2=y +CONFIG_BAT2_NAME="FLASH" +CONFIG_BAT2_BASE=0xFE000000 +CONFIG_BAT2_LENGTH_8_MBYTES=y +CONFIG_BAT2_ACCESS_RW=y +CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT2_DCACHE_INHIBITED=y +CONFIG_BAT2_DCACHE_GUARDED=y +CONFIG_BAT2_USER_MODE_VALID=y +CONFIG_BAT2_SUPERVISOR_MODE_VALID=y +CONFIG_BAT3=y +CONFIG_BAT3_NAME="STACK_IN_DCACHE" +CONFIG_BAT3_BASE=0xE6000000 +CONFIG_BAT3_ACCESS_RW=y +CONFIG_BAT3_USER_MODE_VALID=y +CONFIG_BAT3_SUPERVISOR_MODE_VALID=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/MPC8313ERDB_33_defconfig b/configs/MPC8313ERDB_33_defconfig index 641c6c8545..8e34ee2c2b 100644 --- a/configs/MPC8313ERDB_33_defconfig +++ b/configs/MPC8313ERDB_33_defconfig @@ -12,6 +12,51 @@ CONFIG_BOOT_MEMORY_SPACE_LOW=y CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_TSEC1_MODE_RGMII=y CONFIG_TSEC2_MODE_RGMII=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="DDR" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_256_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT1=y +CONFIG_BAT1_NAME="PCI1_MEM" +CONFIG_BAT1_BASE=0x80000000 +CONFIG_BAT1_LENGTH_256_MBYTES=y +CONFIG_BAT1_ACCESS_RW=y +CONFIG_BAT1_USER_MODE_VALID=y +CONFIG_BAT1_SUPERVISOR_MODE_VALID=y +CONFIG_BAT2=y +CONFIG_BAT2_NAME="PCI1_MMIO_BASE" +CONFIG_BAT2_BASE=0x90000000 +CONFIG_BAT2_LENGTH_256_MBYTES=y +CONFIG_BAT2_ACCESS_RW=y +CONFIG_BAT2_ICACHE_INHIBITED=y +CONFIG_BAT2_ICACHE_GUARDED=y +CONFIG_BAT2_DCACHE_INHIBITED=y +CONFIG_BAT2_DCACHE_GUARDED=y +CONFIG_BAT2_USER_MODE_VALID=y +CONFIG_BAT2_SUPERVISOR_MODE_VALID=y +CONFIG_BAT5=y +CONFIG_BAT5_NAME="IMMR" +CONFIG_BAT5_BASE=0xE0000000 +CONFIG_BAT5_LENGTH_256_MBYTES=y +CONFIG_BAT5_ACCESS_RW=y +CONFIG_BAT5_ICACHE_INHIBITED=y +CONFIG_BAT5_ICACHE_GUARDED=y +CONFIG_BAT5_DCACHE_INHIBITED=y +CONFIG_BAT5_DCACHE_GUARDED=y +CONFIG_BAT5_USER_MODE_VALID=y +CONFIG_BAT5_SUPERVISOR_MODE_VALID=y +CONFIG_BAT6=y +CONFIG_BAT6_NAME="STACK_IN_DCACHE" +CONFIG_BAT6_BASE=0xF0000000 +CONFIG_BAT6_LENGTH_256_MBYTES=y +CONFIG_BAT6_ACCESS_RW=y +CONFIG_BAT6_ICACHE_GUARDED=y +CONFIG_BAT6_DCACHE_GUARDED=y +CONFIG_BAT6_USER_MODE_VALID=y +CONFIG_BAT6_SUPERVISOR_MODE_VALID=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SYS_33MHZ" diff --git a/configs/MPC8313ERDB_66_defconfig b/configs/MPC8313ERDB_66_defconfig index b1a4bcbc53..a2f7eb5837 100644 --- a/configs/MPC8313ERDB_66_defconfig +++ b/configs/MPC8313ERDB_66_defconfig @@ -11,6 +11,51 @@ CONFIG_BOOT_MEMORY_SPACE_LOW=y CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_TSEC1_MODE_RGMII=y CONFIG_TSEC2_MODE_RGMII=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="DDR" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_256_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT1=y +CONFIG_BAT1_NAME="PCI1_MEM" +CONFIG_BAT1_BASE=0x80000000 +CONFIG_BAT1_LENGTH_256_MBYTES=y +CONFIG_BAT1_ACCESS_RW=y +CONFIG_BAT1_USER_MODE_VALID=y +CONFIG_BAT1_SUPERVISOR_MODE_VALID=y +CONFIG_BAT2=y +CONFIG_BAT2_NAME="PCI1_MMIO_BASE" +CONFIG_BAT2_BASE=0x90000000 +CONFIG_BAT2_LENGTH_256_MBYTES=y +CONFIG_BAT2_ACCESS_RW=y +CONFIG_BAT2_ICACHE_INHIBITED=y +CONFIG_BAT2_ICACHE_GUARDED=y +CONFIG_BAT2_DCACHE_INHIBITED=y +CONFIG_BAT2_DCACHE_GUARDED=y +CONFIG_BAT2_USER_MODE_VALID=y +CONFIG_BAT2_SUPERVISOR_MODE_VALID=y +CONFIG_BAT5=y +CONFIG_BAT5_NAME="IMMR" +CONFIG_BAT5_BASE=0xE0000000 +CONFIG_BAT5_LENGTH_256_MBYTES=y +CONFIG_BAT5_ACCESS_RW=y +CONFIG_BAT5_ICACHE_INHIBITED=y +CONFIG_BAT5_ICACHE_GUARDED=y +CONFIG_BAT5_DCACHE_INHIBITED=y +CONFIG_BAT5_DCACHE_GUARDED=y +CONFIG_BAT5_USER_MODE_VALID=y +CONFIG_BAT5_SUPERVISOR_MODE_VALID=y +CONFIG_BAT6=y +CONFIG_BAT6_NAME="STACK_IN_DCACHE" +CONFIG_BAT6_BASE=0xF0000000 +CONFIG_BAT6_LENGTH_256_MBYTES=y +CONFIG_BAT6_ACCESS_RW=y +CONFIG_BAT6_ICACHE_GUARDED=y +CONFIG_BAT6_DCACHE_GUARDED=y +CONFIG_BAT6_USER_MODE_VALID=y +CONFIG_BAT6_SUPERVISOR_MODE_VALID=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SYS_66MHZ" diff --git a/configs/MPC8313ERDB_NAND_33_defconfig b/configs/MPC8313ERDB_NAND_33_defconfig index 306f4cc80c..9946bf965e 100644 --- a/configs/MPC8313ERDB_NAND_33_defconfig +++ b/configs/MPC8313ERDB_NAND_33_defconfig @@ -13,6 +13,51 @@ CONFIG_PCI_INT_ARBITER1_ENABLE=y CONFIG_BOOT_ROM_INTERFACE_NAND_FLASH_8BIT_SMALL=y CONFIG_TSEC1_MODE_RGMII=y CONFIG_TSEC2_MODE_RGMII=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="DDR" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_256_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT1=y +CONFIG_BAT1_NAME="PCI1_MEM" +CONFIG_BAT1_BASE=0x80000000 +CONFIG_BAT1_LENGTH_256_MBYTES=y +CONFIG_BAT1_ACCESS_RW=y +CONFIG_BAT1_USER_MODE_VALID=y +CONFIG_BAT1_SUPERVISOR_MODE_VALID=y +CONFIG_BAT2=y +CONFIG_BAT2_NAME="PCI1_MMIO_BASE" +CONFIG_BAT2_BASE=0x90000000 +CONFIG_BAT2_LENGTH_256_MBYTES=y +CONFIG_BAT2_ACCESS_RW=y +CONFIG_BAT2_ICACHE_INHIBITED=y +CONFIG_BAT2_ICACHE_GUARDED=y +CONFIG_BAT2_DCACHE_INHIBITED=y +CONFIG_BAT2_DCACHE_GUARDED=y +CONFIG_BAT2_USER_MODE_VALID=y +CONFIG_BAT2_SUPERVISOR_MODE_VALID=y +CONFIG_BAT5=y +CONFIG_BAT5_NAME="IMMR" +CONFIG_BAT5_BASE=0xE0000000 +CONFIG_BAT5_LENGTH_256_MBYTES=y +CONFIG_BAT5_ACCESS_RW=y +CONFIG_BAT5_ICACHE_INHIBITED=y +CONFIG_BAT5_ICACHE_GUARDED=y +CONFIG_BAT5_DCACHE_INHIBITED=y +CONFIG_BAT5_DCACHE_GUARDED=y +CONFIG_BAT5_USER_MODE_VALID=y +CONFIG_BAT5_SUPERVISOR_MODE_VALID=y +CONFIG_BAT6=y +CONFIG_BAT6_NAME="STACK_IN_DCACHE" +CONFIG_BAT6_BASE=0xF0000000 +CONFIG_BAT6_LENGTH_256_MBYTES=y +CONFIG_BAT6_ACCESS_RW=y +CONFIG_BAT6_ICACHE_GUARDED=y +CONFIG_BAT6_DCACHE_GUARDED=y +CONFIG_BAT6_USER_MODE_VALID=y +CONFIG_BAT6_SUPERVISOR_MODE_VALID=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SYS_33MHZ" diff --git a/configs/MPC8313ERDB_NAND_66_defconfig b/configs/MPC8313ERDB_NAND_66_defconfig index 951ef72445..ffa22bfb83 100644 --- a/configs/MPC8313ERDB_NAND_66_defconfig +++ b/configs/MPC8313ERDB_NAND_66_defconfig @@ -12,6 +12,51 @@ CONFIG_PCI_INT_ARBITER1_ENABLE=y CONFIG_BOOT_ROM_INTERFACE_NAND_FLASH_8BIT_SMALL=y CONFIG_TSEC1_MODE_RGMII=y CONFIG_TSEC2_MODE_RGMII=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="DDR" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_256_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT1=y +CONFIG_BAT1_NAME="PCI1_MEM" +CONFIG_BAT1_BASE=0x80000000 +CONFIG_BAT1_LENGTH_256_MBYTES=y +CONFIG_BAT1_ACCESS_RW=y +CONFIG_BAT1_USER_MODE_VALID=y +CONFIG_BAT1_SUPERVISOR_MODE_VALID=y +CONFIG_BAT2=y +CONFIG_BAT2_NAME="PCI1_MMIO_BASE" +CONFIG_BAT2_BASE=0x90000000 +CONFIG_BAT2_LENGTH_256_MBYTES=y +CONFIG_BAT2_ACCESS_RW=y +CONFIG_BAT2_ICACHE_INHIBITED=y +CONFIG_BAT2_ICACHE_GUARDED=y +CONFIG_BAT2_DCACHE_INHIBITED=y +CONFIG_BAT2_DCACHE_GUARDED=y +CONFIG_BAT2_USER_MODE_VALID=y +CONFIG_BAT2_SUPERVISOR_MODE_VALID=y +CONFIG_BAT5=y +CONFIG_BAT5_NAME="IMMR" +CONFIG_BAT5_BASE=0xE0000000 +CONFIG_BAT5_LENGTH_256_MBYTES=y +CONFIG_BAT5_ACCESS_RW=y +CONFIG_BAT5_ICACHE_INHIBITED=y +CONFIG_BAT5_ICACHE_GUARDED=y +CONFIG_BAT5_DCACHE_INHIBITED=y +CONFIG_BAT5_DCACHE_GUARDED=y +CONFIG_BAT5_USER_MODE_VALID=y +CONFIG_BAT5_SUPERVISOR_MODE_VALID=y +CONFIG_BAT6=y +CONFIG_BAT6_NAME="STACK_IN_DCACHE" +CONFIG_BAT6_BASE=0xF0000000 +CONFIG_BAT6_LENGTH_256_MBYTES=y +CONFIG_BAT6_ACCESS_RW=y +CONFIG_BAT6_ICACHE_GUARDED=y +CONFIG_BAT6_DCACHE_GUARDED=y +CONFIG_BAT6_USER_MODE_VALID=y +CONFIG_BAT6_SUPERVISOR_MODE_VALID=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SYS_66MHZ" diff --git a/configs/MPC8315ERDB_defconfig b/configs/MPC8315ERDB_defconfig index 149e71c310..43daee1f19 100644 --- a/configs/MPC8315ERDB_defconfig +++ b/configs/MPC8315ERDB_defconfig @@ -12,6 +12,62 @@ CONFIG_BOOT_MEMORY_SPACE_LOW=y CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_TSEC1_MODE_RGMII=y CONFIG_TSEC2_MODE_RGMII=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="SDRAM" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_128_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT1=y +CONFIG_BAT1_NAME="IMMRBAR" +CONFIG_BAT1_BASE=0xE0000000 +CONFIG_BAT1_LENGTH_8_MBYTES=y +CONFIG_BAT1_ACCESS_RW=y +CONFIG_BAT1_ICACHE_INHIBITED=y +CONFIG_BAT1_ICACHE_GUARDED=y +CONFIG_BAT1_DCACHE_INHIBITED=y +CONFIG_BAT1_DCACHE_GUARDED=y +CONFIG_BAT1_USER_MODE_VALID=y +CONFIG_BAT1_SUPERVISOR_MODE_VALID=y +CONFIG_BAT2=y +CONFIG_BAT2_NAME="FLASH" +CONFIG_BAT2_BASE=0xFE000000 +CONFIG_BAT2_LENGTH_32_MBYTES=y +CONFIG_BAT2_ACCESS_RW=y +CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT2_DCACHE_INHIBITED=y +CONFIG_BAT2_DCACHE_GUARDED=y +CONFIG_BAT2_USER_MODE_VALID=y +CONFIG_BAT2_SUPERVISOR_MODE_VALID=y +CONFIG_BAT3=y +CONFIG_BAT3_NAME="STACK_IN_DCACHE" +CONFIG_BAT3_BASE=0xE6000000 +CONFIG_BAT3_ACCESS_RW=y +CONFIG_BAT3_USER_MODE_VALID=y +CONFIG_BAT3_SUPERVISOR_MODE_VALID=y +CONFIG_BAT4=y +CONFIG_BAT4_NAME="PCI_MEM_PHYS" +CONFIG_BAT4_BASE=0x80000000 +CONFIG_BAT4_LENGTH_256_MBYTES=y +CONFIG_BAT4_ACCESS_RW=y +CONFIG_BAT4_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT4_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT4_USER_MODE_VALID=y +CONFIG_BAT4_SUPERVISOR_MODE_VALID=y +CONFIG_BAT5=y +CONFIG_BAT5_NAME="PCI_MMIO_PHYS" +CONFIG_BAT5_BASE=0x90000000 +CONFIG_BAT5_LENGTH_256_MBYTES=y +CONFIG_BAT5_ACCESS_RW=y +CONFIG_BAT5_ICACHE_INHIBITED=y +CONFIG_BAT5_ICACHE_GUARDED=y +CONFIG_BAT5_DCACHE_INHIBITED=y +CONFIG_BAT5_DCACHE_GUARDED=y +CONFIG_BAT5_USER_MODE_VALID=y +CONFIG_BAT5_SUPERVISOR_MODE_VALID=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC8323ERDB_defconfig b/configs/MPC8323ERDB_defconfig index 49e690e88b..9039652d4b 100644 --- a/configs/MPC8323ERDB_defconfig +++ b/configs/MPC8323ERDB_defconfig @@ -10,6 +10,62 @@ CONFIG_PCI_HOST_MODE_ENABLE=y CONFIG_PCI_INT_ARBITER1_ENABLE=y CONFIG_BOOT_MEMORY_SPACE_LOW=y CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="SDRAM" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_256_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT1=y +CONFIG_BAT1_NAME="IMMR" +CONFIG_BAT1_BASE=0xE0000000 +CONFIG_BAT1_LENGTH_4_MBYTES=y +CONFIG_BAT1_ACCESS_RW=y +CONFIG_BAT1_ICACHE_INHIBITED=y +CONFIG_BAT1_ICACHE_GUARDED=y +CONFIG_BAT1_DCACHE_INHIBITED=y +CONFIG_BAT1_DCACHE_GUARDED=y +CONFIG_BAT1_USER_MODE_VALID=y +CONFIG_BAT1_SUPERVISOR_MODE_VALID=y +CONFIG_BAT2=y +CONFIG_BAT2_NAME="FLASH" +CONFIG_BAT2_BASE=0xFE000000 +CONFIG_BAT2_LENGTH_32_MBYTES=y +CONFIG_BAT2_ACCESS_RW=y +CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT2_DCACHE_INHIBITED=y +CONFIG_BAT2_DCACHE_GUARDED=y +CONFIG_BAT2_USER_MODE_VALID=y +CONFIG_BAT2_SUPERVISOR_MODE_VALID=y +CONFIG_BAT4=y +CONFIG_BAT4_NAME="STACK_IN_DCACHE" +CONFIG_BAT4_BASE=0xE6000000 +CONFIG_BAT4_ACCESS_RW=y +CONFIG_BAT4_USER_MODE_VALID=y +CONFIG_BAT4_SUPERVISOR_MODE_VALID=y +CONFIG_BAT5=y +CONFIG_BAT5_NAME="PCI_MEM_PHYS" +CONFIG_BAT5_BASE=0x80000000 +CONFIG_BAT5_LENGTH_256_MBYTES=y +CONFIG_BAT5_ACCESS_RW=y +CONFIG_BAT5_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT5_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT5_USER_MODE_VALID=y +CONFIG_BAT5_SUPERVISOR_MODE_VALID=y +CONFIG_BAT6=y +CONFIG_BAT6_NAME="PCI1_MMIO_PHYS" +CONFIG_BAT6_BASE=0x90000000 +CONFIG_BAT6_LENGTH_256_MBYTES=y +CONFIG_BAT6_ACCESS_RW=y +CONFIG_BAT6_ICACHE_INHIBITED=y +CONFIG_BAT6_ICACHE_GUARDED=y +CONFIG_BAT6_DCACHE_INHIBITED=y +CONFIG_BAT6_DCACHE_GUARDED=y +CONFIG_BAT6_USER_MODE_VALID=y +CONFIG_BAT6_SUPERVISOR_MODE_VALID=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC832XEMDS_ATM_defconfig b/configs/MPC832XEMDS_ATM_defconfig index 323b368f9e..aefb01f150 100644 --- a/configs/MPC832XEMDS_ATM_defconfig +++ b/configs/MPC832XEMDS_ATM_defconfig @@ -10,6 +10,52 @@ CONFIG_PCI_HOST_MODE_ENABLE=y CONFIG_PCI_INT_ARBITER1_ENABLE=y CONFIG_BOOT_MEMORY_SPACE_LOW=y CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="SDRAM" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_256_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT1=y +CONFIG_BAT1_NAME="IMMR" +CONFIG_BAT1_BASE=0xE0000000 +CONFIG_BAT1_LENGTH_4_MBYTES=y +CONFIG_BAT1_ACCESS_RW=y +CONFIG_BAT1_ICACHE_INHIBITED=y +CONFIG_BAT1_ICACHE_GUARDED=y +CONFIG_BAT1_DCACHE_INHIBITED=y +CONFIG_BAT1_DCACHE_GUARDED=y +CONFIG_BAT1_USER_MODE_VALID=y +CONFIG_BAT1_SUPERVISOR_MODE_VALID=y +CONFIG_BAT2=y +CONFIG_BAT2_NAME="BCSR" +CONFIG_BAT2_BASE=0xF8000000 +CONFIG_BAT2_ACCESS_RW=y +CONFIG_BAT2_ICACHE_INHIBITED=y +CONFIG_BAT2_ICACHE_GUARDED=y +CONFIG_BAT2_DCACHE_INHIBITED=y +CONFIG_BAT2_DCACHE_GUARDED=y +CONFIG_BAT2_USER_MODE_VALID=y +CONFIG_BAT2_SUPERVISOR_MODE_VALID=y +CONFIG_BAT3=y +CONFIG_BAT3_NAME="FLASH" +CONFIG_BAT3_BASE=0xFE000000 +CONFIG_BAT3_LENGTH_32_MBYTES=y +CONFIG_BAT3_ACCESS_RW=y +CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT3_DCACHE_INHIBITED=y +CONFIG_BAT3_DCACHE_GUARDED=y +CONFIG_BAT3_USER_MODE_VALID=y +CONFIG_BAT3_SUPERVISOR_MODE_VALID=y +CONFIG_BAT5=y +CONFIG_BAT5_NAME="STACK_IN_DCACHE" +CONFIG_BAT5_BASE=0xE6000000 +CONFIG_BAT5_ACCESS_RW=y +CONFIG_BAT5_USER_MODE_VALID=y +CONFIG_BAT5_SUPERVISOR_MODE_VALID=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PQ_MDS_PIB=1,PQ_MDS_PIB_ATM=1" diff --git a/configs/MPC832XEMDS_HOST_33_defconfig b/configs/MPC832XEMDS_HOST_33_defconfig index a13dcfb91d..f410f8dac0 100644 --- a/configs/MPC832XEMDS_HOST_33_defconfig +++ b/configs/MPC832XEMDS_HOST_33_defconfig @@ -10,6 +10,72 @@ CONFIG_PCI_HOST_MODE_ENABLE=y CONFIG_PCI_INT_ARBITER1_ENABLE=y CONFIG_BOOT_MEMORY_SPACE_LOW=y CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="SDRAM" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_256_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT1=y +CONFIG_BAT1_NAME="IMMR" +CONFIG_BAT1_BASE=0xE0000000 +CONFIG_BAT1_LENGTH_4_MBYTES=y +CONFIG_BAT1_ACCESS_RW=y +CONFIG_BAT1_ICACHE_INHIBITED=y +CONFIG_BAT1_ICACHE_GUARDED=y +CONFIG_BAT1_DCACHE_INHIBITED=y +CONFIG_BAT1_DCACHE_GUARDED=y +CONFIG_BAT1_USER_MODE_VALID=y +CONFIG_BAT1_SUPERVISOR_MODE_VALID=y +CONFIG_BAT2=y +CONFIG_BAT2_NAME="BCSR" +CONFIG_BAT2_BASE=0xF8000000 +CONFIG_BAT2_ACCESS_RW=y +CONFIG_BAT2_ICACHE_INHIBITED=y +CONFIG_BAT2_ICACHE_GUARDED=y +CONFIG_BAT2_DCACHE_INHIBITED=y +CONFIG_BAT2_DCACHE_GUARDED=y +CONFIG_BAT2_USER_MODE_VALID=y +CONFIG_BAT2_SUPERVISOR_MODE_VALID=y +CONFIG_BAT3=y +CONFIG_BAT3_NAME="FLASH" +CONFIG_BAT3_BASE=0xFE000000 +CONFIG_BAT3_LENGTH_32_MBYTES=y +CONFIG_BAT3_ACCESS_RW=y +CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT3_DCACHE_INHIBITED=y +CONFIG_BAT3_DCACHE_GUARDED=y +CONFIG_BAT3_USER_MODE_VALID=y +CONFIG_BAT3_SUPERVISOR_MODE_VALID=y +CONFIG_BAT5=y +CONFIG_BAT5_NAME="STACK_IN_DCACHE" +CONFIG_BAT5_BASE=0xE6000000 +CONFIG_BAT5_ACCESS_RW=y +CONFIG_BAT5_USER_MODE_VALID=y +CONFIG_BAT5_SUPERVISOR_MODE_VALID=y +CONFIG_BAT6=y +CONFIG_BAT6_NAME="PCI_MEM_PHYS" +CONFIG_BAT6_BASE=0x80000000 +CONFIG_BAT6_LENGTH_256_MBYTES=y +CONFIG_BAT6_ACCESS_RW=y +CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT6_USER_MODE_VALID=y +CONFIG_BAT6_SUPERVISOR_MODE_VALID=y +CONFIG_BAT7=y +CONFIG_BAT7_NAME="PCI1_MMIO_PHYS" +CONFIG_BAT7_BASE=0x90000000 +CONFIG_BAT7_LENGTH_256_MBYTES=y +CONFIG_BAT7_ACCESS_RW=y +CONFIG_BAT7_ICACHE_INHIBITED=y +CONFIG_BAT7_ICACHE_GUARDED=y +CONFIG_BAT7_DCACHE_INHIBITED=y +CONFIG_BAT7_DCACHE_GUARDED=y +CONFIG_BAT7_USER_MODE_VALID=y +CONFIG_BAT7_SUPERVISOR_MODE_VALID=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PCI_33M,PQ_MDS_PIB=1" diff --git a/configs/MPC832XEMDS_HOST_66_defconfig b/configs/MPC832XEMDS_HOST_66_defconfig index 2a4ff9a3e1..dac8f28a4d 100644 --- a/configs/MPC832XEMDS_HOST_66_defconfig +++ b/configs/MPC832XEMDS_HOST_66_defconfig @@ -10,6 +10,72 @@ CONFIG_PCI_HOST_MODE_ENABLE=y CONFIG_PCI_INT_ARBITER1_ENABLE=y CONFIG_BOOT_MEMORY_SPACE_LOW=y CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="SDRAM" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_256_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT1=y +CONFIG_BAT1_NAME="IMMR" +CONFIG_BAT1_BASE=0xE0000000 +CONFIG_BAT1_LENGTH_4_MBYTES=y +CONFIG_BAT1_ACCESS_RW=y +CONFIG_BAT1_ICACHE_INHIBITED=y +CONFIG_BAT1_ICACHE_GUARDED=y +CONFIG_BAT1_DCACHE_INHIBITED=y +CONFIG_BAT1_DCACHE_GUARDED=y +CONFIG_BAT1_USER_MODE_VALID=y +CONFIG_BAT1_SUPERVISOR_MODE_VALID=y +CONFIG_BAT2=y +CONFIG_BAT2_NAME="BCSR" +CONFIG_BAT2_BASE=0xF8000000 +CONFIG_BAT2_ACCESS_RW=y +CONFIG_BAT2_ICACHE_INHIBITED=y +CONFIG_BAT2_ICACHE_GUARDED=y +CONFIG_BAT2_DCACHE_INHIBITED=y +CONFIG_BAT2_DCACHE_GUARDED=y +CONFIG_BAT2_USER_MODE_VALID=y +CONFIG_BAT2_SUPERVISOR_MODE_VALID=y +CONFIG_BAT3=y +CONFIG_BAT3_NAME="FLASH" +CONFIG_BAT3_BASE=0xFE000000 +CONFIG_BAT3_LENGTH_32_MBYTES=y +CONFIG_BAT3_ACCESS_RW=y +CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT3_DCACHE_INHIBITED=y +CONFIG_BAT3_DCACHE_GUARDED=y +CONFIG_BAT3_USER_MODE_VALID=y +CONFIG_BAT3_SUPERVISOR_MODE_VALID=y +CONFIG_BAT5=y +CONFIG_BAT5_NAME="STACK_IN_DCACHE" +CONFIG_BAT5_BASE=0xE6000000 +CONFIG_BAT5_ACCESS_RW=y +CONFIG_BAT5_USER_MODE_VALID=y +CONFIG_BAT5_SUPERVISOR_MODE_VALID=y +CONFIG_BAT6=y +CONFIG_BAT6_NAME="PCI_MEM_PHYS" +CONFIG_BAT6_BASE=0x80000000 +CONFIG_BAT6_LENGTH_256_MBYTES=y +CONFIG_BAT6_ACCESS_RW=y +CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT6_USER_MODE_VALID=y +CONFIG_BAT6_SUPERVISOR_MODE_VALID=y +CONFIG_BAT7=y +CONFIG_BAT7_NAME="PCI1_MMIO_PHYS" +CONFIG_BAT7_BASE=0x90000000 +CONFIG_BAT7_LENGTH_256_MBYTES=y +CONFIG_BAT7_ACCESS_RW=y +CONFIG_BAT7_ICACHE_INHIBITED=y +CONFIG_BAT7_ICACHE_GUARDED=y +CONFIG_BAT7_DCACHE_INHIBITED=y +CONFIG_BAT7_DCACHE_GUARDED=y +CONFIG_BAT7_USER_MODE_VALID=y +CONFIG_BAT7_SUPERVISOR_MODE_VALID=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PCI_66M,PQ_MDS_PIB=1" diff --git a/configs/MPC832XEMDS_SLAVE_defconfig b/configs/MPC832XEMDS_SLAVE_defconfig index e7ea39a236..c1cb69ad93 100644 --- a/configs/MPC832XEMDS_SLAVE_defconfig +++ b/configs/MPC832XEMDS_SLAVE_defconfig @@ -7,6 +7,72 @@ CONFIG_TARGET_MPC832XEMDS=y CONFIG_CORE_PLL_RATIO_2_1=y CONFIG_QUICC_MULT_FACTOR_3=y CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="SDRAM" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_256_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT1=y +CONFIG_BAT1_NAME="IMMR" +CONFIG_BAT1_BASE=0xE0000000 +CONFIG_BAT1_LENGTH_4_MBYTES=y +CONFIG_BAT1_ACCESS_RW=y +CONFIG_BAT1_ICACHE_INHIBITED=y +CONFIG_BAT1_ICACHE_GUARDED=y +CONFIG_BAT1_DCACHE_INHIBITED=y +CONFIG_BAT1_DCACHE_GUARDED=y +CONFIG_BAT1_USER_MODE_VALID=y +CONFIG_BAT1_SUPERVISOR_MODE_VALID=y +CONFIG_BAT2=y +CONFIG_BAT2_NAME="BCSR" +CONFIG_BAT2_BASE=0xF8000000 +CONFIG_BAT2_ACCESS_RW=y +CONFIG_BAT2_ICACHE_INHIBITED=y +CONFIG_BAT2_ICACHE_GUARDED=y +CONFIG_BAT2_DCACHE_INHIBITED=y +CONFIG_BAT2_DCACHE_GUARDED=y +CONFIG_BAT2_USER_MODE_VALID=y +CONFIG_BAT2_SUPERVISOR_MODE_VALID=y +CONFIG_BAT3=y +CONFIG_BAT3_NAME="FLASH" +CONFIG_BAT3_BASE=0xFE000000 +CONFIG_BAT3_LENGTH_32_MBYTES=y +CONFIG_BAT3_ACCESS_RW=y +CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT3_DCACHE_INHIBITED=y +CONFIG_BAT3_DCACHE_GUARDED=y +CONFIG_BAT3_USER_MODE_VALID=y +CONFIG_BAT3_SUPERVISOR_MODE_VALID=y +CONFIG_BAT5=y +CONFIG_BAT5_NAME="STACK_IN_DCACHE" +CONFIG_BAT5_BASE=0xE6000000 +CONFIG_BAT5_ACCESS_RW=y +CONFIG_BAT5_USER_MODE_VALID=y +CONFIG_BAT5_SUPERVISOR_MODE_VALID=y +CONFIG_BAT6=y +CONFIG_BAT6_NAME="PCI_MEM_PHYS" +CONFIG_BAT6_BASE=0x80000000 +CONFIG_BAT6_LENGTH_256_MBYTES=y +CONFIG_BAT6_ACCESS_RW=y +CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT6_USER_MODE_VALID=y +CONFIG_BAT6_SUPERVISOR_MODE_VALID=y +CONFIG_BAT7=y +CONFIG_BAT7_NAME="PCI1_MMIO_PHYS" +CONFIG_BAT7_BASE=0x90000000 +CONFIG_BAT7_LENGTH_256_MBYTES=y +CONFIG_BAT7_ACCESS_RW=y +CONFIG_BAT7_ICACHE_INHIBITED=y +CONFIG_BAT7_ICACHE_GUARDED=y +CONFIG_BAT7_DCACHE_INHIBITED=y +CONFIG_BAT7_DCACHE_GUARDED=y +CONFIG_BAT7_USER_MODE_VALID=y +CONFIG_BAT7_SUPERVISOR_MODE_VALID=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PCISLAVE" diff --git a/configs/MPC832XEMDS_defconfig b/configs/MPC832XEMDS_defconfig index bffc55b917..38e0b7f6de 100644 --- a/configs/MPC832XEMDS_defconfig +++ b/configs/MPC832XEMDS_defconfig @@ -10,6 +10,52 @@ CONFIG_PCI_HOST_MODE_ENABLE=y CONFIG_PCI_INT_ARBITER1_ENABLE=y CONFIG_BOOT_MEMORY_SPACE_LOW=y CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="SDRAM" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_256_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT1=y +CONFIG_BAT1_NAME="IMMR" +CONFIG_BAT1_BASE=0xE0000000 +CONFIG_BAT1_LENGTH_4_MBYTES=y +CONFIG_BAT1_ACCESS_RW=y +CONFIG_BAT1_ICACHE_INHIBITED=y +CONFIG_BAT1_ICACHE_GUARDED=y +CONFIG_BAT1_DCACHE_INHIBITED=y +CONFIG_BAT1_DCACHE_GUARDED=y +CONFIG_BAT1_USER_MODE_VALID=y +CONFIG_BAT1_SUPERVISOR_MODE_VALID=y +CONFIG_BAT2=y +CONFIG_BAT2_NAME="BCSR" +CONFIG_BAT2_BASE=0xF8000000 +CONFIG_BAT2_ACCESS_RW=y +CONFIG_BAT2_ICACHE_INHIBITED=y +CONFIG_BAT2_ICACHE_GUARDED=y +CONFIG_BAT2_DCACHE_INHIBITED=y +CONFIG_BAT2_DCACHE_GUARDED=y +CONFIG_BAT2_USER_MODE_VALID=y +CONFIG_BAT2_SUPERVISOR_MODE_VALID=y +CONFIG_BAT3=y +CONFIG_BAT3_NAME="FLASH" +CONFIG_BAT3_BASE=0xFE000000 +CONFIG_BAT3_LENGTH_32_MBYTES=y +CONFIG_BAT3_ACCESS_RW=y +CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT3_DCACHE_INHIBITED=y +CONFIG_BAT3_DCACHE_GUARDED=y +CONFIG_BAT3_USER_MODE_VALID=y +CONFIG_BAT3_SUPERVISOR_MODE_VALID=y +CONFIG_BAT5=y +CONFIG_BAT5_NAME="STACK_IN_DCACHE" +CONFIG_BAT5_BASE=0xE6000000 +CONFIG_BAT5_ACCESS_RW=y +CONFIG_BAT5_USER_MODE_VALID=y +CONFIG_BAT5_SUPERVISOR_MODE_VALID=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC8349EMDS_PCI64_defconfig b/configs/MPC8349EMDS_PCI64_defconfig index 11bce06a09..6daab44b62 100644 --- a/configs/MPC8349EMDS_PCI64_defconfig +++ b/configs/MPC8349EMDS_PCI64_defconfig @@ -14,6 +14,37 @@ CONFIG_BOOT_MEMORY_SPACE_LOW=y CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_TSEC1_MODE_GMII=y CONFIG_TSEC2_MODE_GMII=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="SDRAM" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_256_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT5=y +CONFIG_BAT5_NAME="IMMR" +CONFIG_BAT5_BASE=0xE0000000 +CONFIG_BAT5_LENGTH_256_MBYTES=y +CONFIG_BAT5_ACCESS_RW=y +CONFIG_BAT5_ICACHE_INHIBITED=y +CONFIG_BAT5_ICACHE_GUARDED=y +CONFIG_BAT5_DCACHE_INHIBITED=y +CONFIG_BAT5_DCACHE_GUARDED=y +CONFIG_BAT5_USER_MODE_VALID=y +CONFIG_BAT5_SUPERVISOR_MODE_VALID=y +CONFIG_BAT6=y +CONFIG_BAT6_NAME="STACK_IN_DCACHE" +CONFIG_BAT6_BASE=0xF0000000 +CONFIG_BAT6_LENGTH_256_MBYTES=y +CONFIG_BAT6_ACCESS_RW=y +CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT6_ICACHE_GUARDED=y +CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT6_DCACHE_GUARDED=y +CONFIG_BAT6_USER_MODE_VALID=y +CONFIG_BAT6_SUPERVISOR_MODE_VALID=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC8349EMDS_SDRAM_defconfig b/configs/MPC8349EMDS_SDRAM_defconfig index 6b571b0368..d3f42f99e0 100644 --- a/configs/MPC8349EMDS_SDRAM_defconfig +++ b/configs/MPC8349EMDS_SDRAM_defconfig @@ -14,6 +14,37 @@ CONFIG_BOOT_MEMORY_SPACE_LOW=y CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_TSEC1_MODE_GMII=y CONFIG_TSEC2_MODE_GMII=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="SDRAM" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_256_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT5=y +CONFIG_BAT5_NAME="IMMR" +CONFIG_BAT5_BASE=0xE0000000 +CONFIG_BAT5_LENGTH_256_MBYTES=y +CONFIG_BAT5_ACCESS_RW=y +CONFIG_BAT5_ICACHE_INHIBITED=y +CONFIG_BAT5_ICACHE_GUARDED=y +CONFIG_BAT5_DCACHE_INHIBITED=y +CONFIG_BAT5_DCACHE_GUARDED=y +CONFIG_BAT5_USER_MODE_VALID=y +CONFIG_BAT5_SUPERVISOR_MODE_VALID=y +CONFIG_BAT6=y +CONFIG_BAT6_NAME="STACK_IN_DCACHE" +CONFIG_BAT6_BASE=0xF0000000 +CONFIG_BAT6_LENGTH_256_MBYTES=y +CONFIG_BAT6_ACCESS_RW=y +CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT6_ICACHE_GUARDED=y +CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT6_DCACHE_GUARDED=y +CONFIG_BAT6_USER_MODE_VALID=y +CONFIG_BAT6_SUPERVISOR_MODE_VALID=y CONFIG_PCI_ONE_PCI1=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/configs/MPC8349EMDS_SLAVE_defconfig b/configs/MPC8349EMDS_SLAVE_defconfig index 87892c3d67..c264f7b53d 100644 --- a/configs/MPC8349EMDS_SLAVE_defconfig +++ b/configs/MPC8349EMDS_SLAVE_defconfig @@ -12,6 +12,37 @@ CONFIG_BOOT_MEMORY_SPACE_LOW=y CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_TSEC1_MODE_GMII=y CONFIG_TSEC2_MODE_GMII=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="SDRAM" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_256_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT5=y +CONFIG_BAT5_NAME="IMMR" +CONFIG_BAT5_BASE=0xE0000000 +CONFIG_BAT5_LENGTH_256_MBYTES=y +CONFIG_BAT5_ACCESS_RW=y +CONFIG_BAT5_ICACHE_INHIBITED=y +CONFIG_BAT5_ICACHE_GUARDED=y +CONFIG_BAT5_DCACHE_INHIBITED=y +CONFIG_BAT5_DCACHE_GUARDED=y +CONFIG_BAT5_USER_MODE_VALID=y +CONFIG_BAT5_SUPERVISOR_MODE_VALID=y +CONFIG_BAT6=y +CONFIG_BAT6_NAME="STACK_IN_DCACHE" +CONFIG_BAT6_BASE=0xF0000000 +CONFIG_BAT6_LENGTH_256_MBYTES=y +CONFIG_BAT6_ACCESS_RW=y +CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT6_ICACHE_GUARDED=y +CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT6_DCACHE_GUARDED=y +CONFIG_BAT6_USER_MODE_VALID=y +CONFIG_BAT6_SUPERVISOR_MODE_VALID=y CONFIG_PCI_ONE_PCI1=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/configs/MPC8349EMDS_defconfig b/configs/MPC8349EMDS_defconfig index 40633d19be..4018d81825 100644 --- a/configs/MPC8349EMDS_defconfig +++ b/configs/MPC8349EMDS_defconfig @@ -14,6 +14,37 @@ CONFIG_BOOT_MEMORY_SPACE_LOW=y CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_TSEC1_MODE_GMII=y CONFIG_TSEC2_MODE_GMII=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="SDRAM" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_256_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT5=y +CONFIG_BAT5_NAME="IMMR" +CONFIG_BAT5_BASE=0xE0000000 +CONFIG_BAT5_LENGTH_256_MBYTES=y +CONFIG_BAT5_ACCESS_RW=y +CONFIG_BAT5_ICACHE_INHIBITED=y +CONFIG_BAT5_ICACHE_GUARDED=y +CONFIG_BAT5_DCACHE_INHIBITED=y +CONFIG_BAT5_DCACHE_GUARDED=y +CONFIG_BAT5_USER_MODE_VALID=y +CONFIG_BAT5_SUPERVISOR_MODE_VALID=y +CONFIG_BAT6=y +CONFIG_BAT6_NAME="STACK_IN_DCACHE" +CONFIG_BAT6_BASE=0xF0000000 +CONFIG_BAT6_LENGTH_256_MBYTES=y +CONFIG_BAT6_ACCESS_RW=y +CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT6_ICACHE_GUARDED=y +CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT6_DCACHE_GUARDED=y +CONFIG_BAT6_USER_MODE_VALID=y +CONFIG_BAT6_SUPERVISOR_MODE_VALID=y CONFIG_PCI_ONE_PCI1=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/configs/MPC8349ITXGP_defconfig b/configs/MPC8349ITXGP_defconfig index 9e466b1bd1..0434118419 100644 --- a/configs/MPC8349ITXGP_defconfig +++ b/configs/MPC8349ITXGP_defconfig @@ -14,6 +14,77 @@ CONFIG_BOOT_MEMORY_SPACE_LOW=y CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_TSEC1_MODE_GMII=y CONFIG_TSEC2_MODE_GMII=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="SDRAM" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_256_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT1=y +CONFIG_BAT1_NAME="PCI1_MEM" +CONFIG_BAT1_BASE=0x80000000 +CONFIG_BAT1_LENGTH_256_MBYTES=y +CONFIG_BAT1_ACCESS_RW=y +CONFIG_BAT1_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT1_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT1_USER_MODE_VALID=y +CONFIG_BAT1_SUPERVISOR_MODE_VALID=y +CONFIG_BAT2=y +CONFIG_BAT2_NAME="PCI1_MMIO" +CONFIG_BAT2_BASE=0x90000000 +CONFIG_BAT2_LENGTH_256_MBYTES=y +CONFIG_BAT2_ACCESS_RW=y +CONFIG_BAT2_ICACHE_INHIBITED=y +CONFIG_BAT2_ICACHE_GUARDED=y +CONFIG_BAT2_DCACHE_INHIBITED=y +CONFIG_BAT2_DCACHE_GUARDED=y +CONFIG_BAT2_USER_MODE_VALID=y +CONFIG_BAT2_SUPERVISOR_MODE_VALID=y +CONFIG_BAT3=y +CONFIG_BAT3_NAME="PCI2_MEM" +CONFIG_BAT3_BASE=0xA0000000 +CONFIG_BAT3_LENGTH_256_MBYTES=y +CONFIG_BAT3_ACCESS_RW=y +CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT3_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT3_USER_MODE_VALID=y +CONFIG_BAT3_SUPERVISOR_MODE_VALID=y +CONFIG_BAT4=y +CONFIG_BAT4_NAME="PCI2_MMIO" +CONFIG_BAT4_BASE=0xB0000000 +CONFIG_BAT4_LENGTH_256_MBYTES=y +CONFIG_BAT4_ACCESS_RW=y +CONFIG_BAT4_ICACHE_INHIBITED=y +CONFIG_BAT4_ICACHE_GUARDED=y +CONFIG_BAT4_DCACHE_INHIBITED=y +CONFIG_BAT4_DCACHE_GUARDED=y +CONFIG_BAT4_USER_MODE_VALID=y +CONFIG_BAT4_SUPERVISOR_MODE_VALID=y +CONFIG_BAT5=y +CONFIG_BAT5_NAME="IMMR" +CONFIG_BAT5_BASE=0xE0000000 +CONFIG_BAT5_LENGTH_256_MBYTES=y +CONFIG_BAT5_ACCESS_RW=y +CONFIG_BAT5_ICACHE_INHIBITED=y +CONFIG_BAT5_ICACHE_GUARDED=y +CONFIG_BAT5_DCACHE_INHIBITED=y +CONFIG_BAT5_DCACHE_GUARDED=y +CONFIG_BAT5_USER_MODE_VALID=y +CONFIG_BAT5_SUPERVISOR_MODE_VALID=y +CONFIG_BAT6=y +CONFIG_BAT6_NAME="STACK_IN_DCACHE" +CONFIG_BAT6_BASE=0xF0000000 +CONFIG_BAT6_LENGTH_256_MBYTES=y +CONFIG_BAT6_ACCESS_RW=y +CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT6_ICACHE_GUARDED=y +CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT6_DCACHE_GUARDED=y +CONFIG_BAT6_USER_MODE_VALID=y +CONFIG_BAT6_SUPERVISOR_MODE_VALID=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFE000000" diff --git a/configs/MPC8349ITX_LOWBOOT_defconfig b/configs/MPC8349ITX_LOWBOOT_defconfig index 3a61235736..de97bb15b2 100644 --- a/configs/MPC8349ITX_LOWBOOT_defconfig +++ b/configs/MPC8349ITX_LOWBOOT_defconfig @@ -14,6 +14,77 @@ CONFIG_BOOT_MEMORY_SPACE_LOW=y CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_TSEC1_MODE_GMII=y CONFIG_TSEC2_MODE_GMII=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="SDRAM" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_256_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT1=y +CONFIG_BAT1_NAME="PCI1_MEM" +CONFIG_BAT1_BASE=0x80000000 +CONFIG_BAT1_LENGTH_256_MBYTES=y +CONFIG_BAT1_ACCESS_RW=y +CONFIG_BAT1_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT1_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT1_USER_MODE_VALID=y +CONFIG_BAT1_SUPERVISOR_MODE_VALID=y +CONFIG_BAT2=y +CONFIG_BAT2_NAME="PCI1_MMIO" +CONFIG_BAT2_BASE=0x90000000 +CONFIG_BAT2_LENGTH_256_MBYTES=y +CONFIG_BAT2_ACCESS_RW=y +CONFIG_BAT2_ICACHE_INHIBITED=y +CONFIG_BAT2_ICACHE_GUARDED=y +CONFIG_BAT2_DCACHE_INHIBITED=y +CONFIG_BAT2_DCACHE_GUARDED=y +CONFIG_BAT2_USER_MODE_VALID=y +CONFIG_BAT2_SUPERVISOR_MODE_VALID=y +CONFIG_BAT3=y +CONFIG_BAT3_NAME="PCI2_MEM" +CONFIG_BAT3_BASE=0xA0000000 +CONFIG_BAT3_LENGTH_256_MBYTES=y +CONFIG_BAT3_ACCESS_RW=y +CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT3_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT3_USER_MODE_VALID=y +CONFIG_BAT3_SUPERVISOR_MODE_VALID=y +CONFIG_BAT4=y +CONFIG_BAT4_NAME="PCI2_MMIO" +CONFIG_BAT4_BASE=0xB0000000 +CONFIG_BAT4_LENGTH_256_MBYTES=y +CONFIG_BAT4_ACCESS_RW=y +CONFIG_BAT4_ICACHE_INHIBITED=y +CONFIG_BAT4_ICACHE_GUARDED=y +CONFIG_BAT4_DCACHE_INHIBITED=y +CONFIG_BAT4_DCACHE_GUARDED=y +CONFIG_BAT4_USER_MODE_VALID=y +CONFIG_BAT4_SUPERVISOR_MODE_VALID=y +CONFIG_BAT5=y +CONFIG_BAT5_NAME="IMMR" +CONFIG_BAT5_BASE=0xE0000000 +CONFIG_BAT5_LENGTH_256_MBYTES=y +CONFIG_BAT5_ACCESS_RW=y +CONFIG_BAT5_ICACHE_INHIBITED=y +CONFIG_BAT5_ICACHE_GUARDED=y +CONFIG_BAT5_DCACHE_INHIBITED=y +CONFIG_BAT5_DCACHE_GUARDED=y +CONFIG_BAT5_USER_MODE_VALID=y +CONFIG_BAT5_SUPERVISOR_MODE_VALID=y +CONFIG_BAT6=y +CONFIG_BAT6_NAME="STACK_IN_DCACHE" +CONFIG_BAT6_BASE=0xF0000000 +CONFIG_BAT6_LENGTH_256_MBYTES=y +CONFIG_BAT6_ACCESS_RW=y +CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT6_ICACHE_GUARDED=y +CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT6_DCACHE_GUARDED=y +CONFIG_BAT6_USER_MODE_VALID=y +CONFIG_BAT6_SUPERVISOR_MODE_VALID=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC8349ITX_defconfig b/configs/MPC8349ITX_defconfig index ed9bd83302..b1e687ceab 100644 --- a/configs/MPC8349ITX_defconfig +++ b/configs/MPC8349ITX_defconfig @@ -13,6 +13,77 @@ CONFIG_PCI_INT_ARBITER2_ENABLE=y CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_TSEC1_MODE_GMII=y CONFIG_TSEC2_MODE_GMII=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="SDRAM" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_256_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT1=y +CONFIG_BAT1_NAME="PCI1_MEM" +CONFIG_BAT1_BASE=0x80000000 +CONFIG_BAT1_LENGTH_256_MBYTES=y +CONFIG_BAT1_ACCESS_RW=y +CONFIG_BAT1_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT1_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT1_USER_MODE_VALID=y +CONFIG_BAT1_SUPERVISOR_MODE_VALID=y +CONFIG_BAT2=y +CONFIG_BAT2_NAME="PCI1_MMIO" +CONFIG_BAT2_BASE=0x90000000 +CONFIG_BAT2_LENGTH_256_MBYTES=y +CONFIG_BAT2_ACCESS_RW=y +CONFIG_BAT2_ICACHE_INHIBITED=y +CONFIG_BAT2_ICACHE_GUARDED=y +CONFIG_BAT2_DCACHE_INHIBITED=y +CONFIG_BAT2_DCACHE_GUARDED=y +CONFIG_BAT2_USER_MODE_VALID=y +CONFIG_BAT2_SUPERVISOR_MODE_VALID=y +CONFIG_BAT3=y +CONFIG_BAT3_NAME="PCI2_MEM" +CONFIG_BAT3_BASE=0xA0000000 +CONFIG_BAT3_LENGTH_256_MBYTES=y +CONFIG_BAT3_ACCESS_RW=y +CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT3_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT3_USER_MODE_VALID=y +CONFIG_BAT3_SUPERVISOR_MODE_VALID=y +CONFIG_BAT4=y +CONFIG_BAT4_NAME="PCI2_MMIO" +CONFIG_BAT4_BASE=0xB0000000 +CONFIG_BAT4_LENGTH_256_MBYTES=y +CONFIG_BAT4_ACCESS_RW=y +CONFIG_BAT4_ICACHE_INHIBITED=y +CONFIG_BAT4_ICACHE_GUARDED=y +CONFIG_BAT4_DCACHE_INHIBITED=y +CONFIG_BAT4_DCACHE_GUARDED=y +CONFIG_BAT4_USER_MODE_VALID=y +CONFIG_BAT4_SUPERVISOR_MODE_VALID=y +CONFIG_BAT5=y +CONFIG_BAT5_NAME="IMMR" +CONFIG_BAT5_BASE=0xE0000000 +CONFIG_BAT5_LENGTH_256_MBYTES=y +CONFIG_BAT5_ACCESS_RW=y +CONFIG_BAT5_ICACHE_INHIBITED=y +CONFIG_BAT5_ICACHE_GUARDED=y +CONFIG_BAT5_DCACHE_INHIBITED=y +CONFIG_BAT5_DCACHE_GUARDED=y +CONFIG_BAT5_USER_MODE_VALID=y +CONFIG_BAT5_SUPERVISOR_MODE_VALID=y +CONFIG_BAT6=y +CONFIG_BAT6_NAME="STACK_IN_DCACHE" +CONFIG_BAT6_BASE=0xF0000000 +CONFIG_BAT6_LENGTH_256_MBYTES=y +CONFIG_BAT6_ACCESS_RW=y +CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT6_ICACHE_GUARDED=y +CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT6_DCACHE_GUARDED=y +CONFIG_BAT6_USER_MODE_VALID=y +CONFIG_BAT6_SUPERVISOR_MODE_VALID=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC837XEMDS_HOST_defconfig b/configs/MPC837XEMDS_HOST_defconfig index 73ba7dc632..86b9f6071a 100644 --- a/configs/MPC837XEMDS_HOST_defconfig +++ b/configs/MPC837XEMDS_HOST_defconfig @@ -14,6 +14,81 @@ CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_TSEC1_MODE_RGMII=y CONFIG_TSEC2_MODE_RGMII=y CONFIG_LDP_PIN_MUX_STATE_0=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="SDRAM_LOWER" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_256_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT1=y +CONFIG_BAT1_NAME="SDRAM_UPPER" +CONFIG_BAT1_BASE=0x10000000 +CONFIG_BAT1_LENGTH_256_MBYTES=y +CONFIG_BAT1_ACCESS_RW=y +CONFIG_BAT1_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT1_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT1_USER_MODE_VALID=y +CONFIG_BAT1_SUPERVISOR_MODE_VALID=y +CONFIG_BAT2=y +CONFIG_BAT2_NAME="IMMR" +CONFIG_BAT2_BASE=0xE0000000 +CONFIG_BAT2_LENGTH_8_MBYTES=y +CONFIG_BAT2_ACCESS_RW=y +CONFIG_BAT2_ICACHE_INHIBITED=y +CONFIG_BAT2_ICACHE_GUARDED=y +CONFIG_BAT2_DCACHE_INHIBITED=y +CONFIG_BAT2_DCACHE_GUARDED=y +CONFIG_BAT2_USER_MODE_VALID=y +CONFIG_BAT2_SUPERVISOR_MODE_VALID=y +CONFIG_BAT3=y +CONFIG_BAT3_NAME="BCSR" +CONFIG_BAT3_BASE=0xF8000000 +CONFIG_BAT3_ACCESS_RW=y +CONFIG_BAT3_ICACHE_INHIBITED=y +CONFIG_BAT3_ICACHE_GUARDED=y +CONFIG_BAT3_DCACHE_INHIBITED=y +CONFIG_BAT3_DCACHE_GUARDED=y +CONFIG_BAT3_USER_MODE_VALID=y +CONFIG_BAT3_SUPERVISOR_MODE_VALID=y +CONFIG_BAT4=y +CONFIG_BAT4_NAME="FLASH" +CONFIG_BAT4_BASE=0xFE000000 +CONFIG_BAT4_LENGTH_32_MBYTES=y +CONFIG_BAT4_ACCESS_RW=y +CONFIG_BAT4_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT4_DCACHE_INHIBITED=y +CONFIG_BAT4_DCACHE_GUARDED=y +CONFIG_BAT4_USER_MODE_VALID=y +CONFIG_BAT4_SUPERVISOR_MODE_VALID=y +CONFIG_BAT5=y +CONFIG_BAT5_NAME="STACK_IN_DCACHE" +CONFIG_BAT5_BASE=0xE6000000 +CONFIG_BAT5_ACCESS_RW=y +CONFIG_BAT5_USER_MODE_VALID=y +CONFIG_BAT5_SUPERVISOR_MODE_VALID=y +CONFIG_BAT6=y +CONFIG_BAT6_NAME="PCI_MEM" +CONFIG_BAT6_BASE=0x80000000 +CONFIG_BAT6_LENGTH_256_MBYTES=y +CONFIG_BAT6_ACCESS_RW=y +CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT6_USER_MODE_VALID=y +CONFIG_BAT6_SUPERVISOR_MODE_VALID=y +CONFIG_BAT7=y +CONFIG_BAT7_NAME="PCI_MMIO" +CONFIG_BAT7_BASE=0x90000000 +CONFIG_BAT7_LENGTH_256_MBYTES=y +CONFIG_BAT7_ACCESS_RW=y +CONFIG_BAT7_ICACHE_INHIBITED=y +CONFIG_BAT7_ICACHE_GUARDED=y +CONFIG_BAT7_DCACHE_INHIBITED=y +CONFIG_BAT7_DCACHE_GUARDED=y +CONFIG_BAT7_USER_MODE_VALID=y +CONFIG_BAT7_SUPERVISOR_MODE_VALID=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC837XEMDS_SLAVE_defconfig b/configs/MPC837XEMDS_SLAVE_defconfig index 8a50ff16d0..44c23eade5 100644 --- a/configs/MPC837XEMDS_SLAVE_defconfig +++ b/configs/MPC837XEMDS_SLAVE_defconfig @@ -10,6 +10,45 @@ CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_TSEC1_MODE_RGMII=y CONFIG_TSEC2_MODE_RGMII=y CONFIG_LDP_PIN_MUX_STATE_0=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="SDRAM_LOWER" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_256_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT1=y +CONFIG_BAT1_NAME="SDRAM_UPPER" +CONFIG_BAT1_BASE=0x10000000 +CONFIG_BAT1_LENGTH_256_MBYTES=y +CONFIG_BAT1_ACCESS_RW=y +CONFIG_BAT1_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT1_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT1_USER_MODE_VALID=y +CONFIG_BAT1_SUPERVISOR_MODE_VALID=y +CONFIG_BAT2=y +CONFIG_BAT2_NAME="IMMR" +CONFIG_BAT2_BASE=0xE0000000 +CONFIG_BAT2_LENGTH_8_MBYTES=y +CONFIG_BAT2_ACCESS_RW=y +CONFIG_BAT2_ICACHE_INHIBITED=y +CONFIG_BAT2_ICACHE_GUARDED=y +CONFIG_BAT2_DCACHE_INHIBITED=y +CONFIG_BAT2_DCACHE_GUARDED=y +CONFIG_BAT2_USER_MODE_VALID=y +CONFIG_BAT2_SUPERVISOR_MODE_VALID=y +CONFIG_BAT3=y +CONFIG_BAT3_NAME="BCSR" +CONFIG_BAT3_BASE=0xF8000000 +CONFIG_BAT3_ACCESS_RW=y +CONFIG_BAT3_ICACHE_INHIBITED=y +CONFIG_BAT3_ICACHE_GUARDED=y +CONFIG_BAT3_DCACHE_INHIBITED=y +CONFIG_BAT3_DCACHE_GUARDED=y +CONFIG_BAT3_USER_MODE_VALID=y +CONFIG_BAT3_SUPERVISOR_MODE_VALID=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PCISLAVE" diff --git a/configs/MPC837XEMDS_defconfig b/configs/MPC837XEMDS_defconfig index cf0694f3b5..f21cdbd179 100644 --- a/configs/MPC837XEMDS_defconfig +++ b/configs/MPC837XEMDS_defconfig @@ -14,6 +14,61 @@ CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_TSEC1_MODE_RGMII=y CONFIG_TSEC2_MODE_RGMII=y CONFIG_LDP_PIN_MUX_STATE_0=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="SDRAM_LOWER" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_256_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT1=y +CONFIG_BAT1_NAME="SDRAM_UPPER" +CONFIG_BAT1_BASE=0x10000000 +CONFIG_BAT1_LENGTH_256_MBYTES=y +CONFIG_BAT1_ACCESS_RW=y +CONFIG_BAT1_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT1_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT1_USER_MODE_VALID=y +CONFIG_BAT1_SUPERVISOR_MODE_VALID=y +CONFIG_BAT2=y +CONFIG_BAT2_NAME="IMMR" +CONFIG_BAT2_BASE=0xE0000000 +CONFIG_BAT2_LENGTH_8_MBYTES=y +CONFIG_BAT2_ACCESS_RW=y +CONFIG_BAT2_ICACHE_INHIBITED=y +CONFIG_BAT2_ICACHE_GUARDED=y +CONFIG_BAT2_DCACHE_INHIBITED=y +CONFIG_BAT2_DCACHE_GUARDED=y +CONFIG_BAT2_USER_MODE_VALID=y +CONFIG_BAT2_SUPERVISOR_MODE_VALID=y +CONFIG_BAT3=y +CONFIG_BAT3_NAME="BCSR" +CONFIG_BAT3_BASE=0xF8000000 +CONFIG_BAT3_ACCESS_RW=y +CONFIG_BAT3_ICACHE_INHIBITED=y +CONFIG_BAT3_ICACHE_GUARDED=y +CONFIG_BAT3_DCACHE_INHIBITED=y +CONFIG_BAT3_DCACHE_GUARDED=y +CONFIG_BAT3_USER_MODE_VALID=y +CONFIG_BAT3_SUPERVISOR_MODE_VALID=y +CONFIG_BAT4=y +CONFIG_BAT4_NAME="FLASH" +CONFIG_BAT4_BASE=0xFE000000 +CONFIG_BAT4_LENGTH_32_MBYTES=y +CONFIG_BAT4_ACCESS_RW=y +CONFIG_BAT4_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT4_DCACHE_INHIBITED=y +CONFIG_BAT4_DCACHE_GUARDED=y +CONFIG_BAT4_USER_MODE_VALID=y +CONFIG_BAT4_SUPERVISOR_MODE_VALID=y +CONFIG_BAT5=y +CONFIG_BAT5_NAME="STACK_IN_DCACHE" +CONFIG_BAT5_BASE=0xE6000000 +CONFIG_BAT5_ACCESS_RW=y +CONFIG_BAT5_USER_MODE_VALID=y +CONFIG_BAT5_SUPERVISOR_MODE_VALID=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC837XERDB_SLAVE_defconfig b/configs/MPC837XERDB_SLAVE_defconfig index e145504ded..d1455b0e9d 100644 --- a/configs/MPC837XERDB_SLAVE_defconfig +++ b/configs/MPC837XERDB_SLAVE_defconfig @@ -10,6 +10,45 @@ CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_TSEC1_MODE_RGMII=y CONFIG_TSEC2_MODE_RGMII=y CONFIG_LDP_PIN_MUX_STATE_0=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="SDRAM_LOWER" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_256_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT1=y +CONFIG_BAT1_NAME="SDRAM_UPPER" +CONFIG_BAT1_BASE=0x10000000 +CONFIG_BAT1_LENGTH_256_MBYTES=y +CONFIG_BAT1_ACCESS_RW=y +CONFIG_BAT1_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT1_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT1_USER_MODE_VALID=y +CONFIG_BAT1_SUPERVISOR_MODE_VALID=y +CONFIG_BAT2=y +CONFIG_BAT2_NAME="IMMR" +CONFIG_BAT2_BASE=0xE0000000 +CONFIG_BAT2_LENGTH_8_MBYTES=y +CONFIG_BAT2_ACCESS_RW=y +CONFIG_BAT2_ICACHE_INHIBITED=y +CONFIG_BAT2_ICACHE_GUARDED=y +CONFIG_BAT2_DCACHE_INHIBITED=y +CONFIG_BAT2_DCACHE_GUARDED=y +CONFIG_BAT2_USER_MODE_VALID=y +CONFIG_BAT2_SUPERVISOR_MODE_VALID=y +CONFIG_BAT3=y +CONFIG_BAT3_NAME="L2_SWITCH" +CONFIG_BAT3_BASE=0xF0000000 +CONFIG_BAT3_ACCESS_RW=y +CONFIG_BAT3_ICACHE_INHIBITED=y +CONFIG_BAT3_ICACHE_GUARDED=y +CONFIG_BAT3_DCACHE_INHIBITED=y +CONFIG_BAT3_DCACHE_GUARDED=y +CONFIG_BAT3_USER_MODE_VALID=y +CONFIG_BAT3_SUPERVISOR_MODE_VALID=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PCISLAVE,PCIE" diff --git a/configs/MPC837XERDB_defconfig b/configs/MPC837XERDB_defconfig index 03fd7b70ba..e6138c06fc 100644 --- a/configs/MPC837XERDB_defconfig +++ b/configs/MPC837XERDB_defconfig @@ -14,6 +14,81 @@ CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_TSEC1_MODE_RGMII=y CONFIG_TSEC2_MODE_RGMII=y CONFIG_LDP_PIN_MUX_STATE_0=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="SDRAM_LOWER" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_256_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT1=y +CONFIG_BAT1_NAME="SDRAM_UPPER" +CONFIG_BAT1_BASE=0x10000000 +CONFIG_BAT1_LENGTH_256_MBYTES=y +CONFIG_BAT1_ACCESS_RW=y +CONFIG_BAT1_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT1_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT1_USER_MODE_VALID=y +CONFIG_BAT1_SUPERVISOR_MODE_VALID=y +CONFIG_BAT2=y +CONFIG_BAT2_NAME="IMMR" +CONFIG_BAT2_BASE=0xE0000000 +CONFIG_BAT2_LENGTH_8_MBYTES=y +CONFIG_BAT2_ACCESS_RW=y +CONFIG_BAT2_ICACHE_INHIBITED=y +CONFIG_BAT2_ICACHE_GUARDED=y +CONFIG_BAT2_DCACHE_INHIBITED=y +CONFIG_BAT2_DCACHE_GUARDED=y +CONFIG_BAT2_USER_MODE_VALID=y +CONFIG_BAT2_SUPERVISOR_MODE_VALID=y +CONFIG_BAT3=y +CONFIG_BAT3_NAME="L2_SWITCH" +CONFIG_BAT3_BASE=0xF0000000 +CONFIG_BAT3_ACCESS_RW=y +CONFIG_BAT3_ICACHE_INHIBITED=y +CONFIG_BAT3_ICACHE_GUARDED=y +CONFIG_BAT3_DCACHE_INHIBITED=y +CONFIG_BAT3_DCACHE_GUARDED=y +CONFIG_BAT3_USER_MODE_VALID=y +CONFIG_BAT3_SUPERVISOR_MODE_VALID=y +CONFIG_BAT4=y +CONFIG_BAT4_NAME="FLASH" +CONFIG_BAT4_BASE=0xFE000000 +CONFIG_BAT4_LENGTH_32_MBYTES=y +CONFIG_BAT4_ACCESS_RW=y +CONFIG_BAT4_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT4_DCACHE_INHIBITED=y +CONFIG_BAT4_DCACHE_GUARDED=y +CONFIG_BAT4_USER_MODE_VALID=y +CONFIG_BAT4_SUPERVISOR_MODE_VALID=y +CONFIG_BAT5=y +CONFIG_BAT5_NAME="STACH_IN_DCACHE" +CONFIG_BAT5_BASE=0xE6000000 +CONFIG_BAT5_ACCESS_RW=y +CONFIG_BAT5_USER_MODE_VALID=y +CONFIG_BAT5_SUPERVISOR_MODE_VALID=y +CONFIG_BAT6=y +CONFIG_BAT6_NAME="PCI_MEM" +CONFIG_BAT6_BASE=0x80000000 +CONFIG_BAT6_LENGTH_256_MBYTES=y +CONFIG_BAT6_ACCESS_RW=y +CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT6_USER_MODE_VALID=y +CONFIG_BAT6_SUPERVISOR_MODE_VALID=y +CONFIG_BAT7=y +CONFIG_BAT7_NAME="PCI_MMIO" +CONFIG_BAT7_BASE=0x90000000 +CONFIG_BAT7_LENGTH_256_MBYTES=y +CONFIG_BAT7_ACCESS_RW=y +CONFIG_BAT7_ICACHE_INHIBITED=y +CONFIG_BAT7_ICACHE_GUARDED=y +CONFIG_BAT7_DCACHE_INHIBITED=y +CONFIG_BAT7_DCACHE_GUARDED=y +CONFIG_BAT7_USER_MODE_VALID=y +CONFIG_BAT7_SUPERVISOR_MODE_VALID=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PCIE" diff --git a/configs/TQM834x_defconfig b/configs/TQM834x_defconfig index c746afd1fd..677f0513a3 100644 --- a/configs/TQM834x_defconfig +++ b/configs/TQM834x_defconfig @@ -13,6 +13,85 @@ CONFIG_BOOT_MEMORY_SPACE_LOW=y CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_TSEC1_MODE_GMII=y CONFIG_TSEC2_MODE_GMII=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="SDRAM_LOWER" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_256_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT1=y +CONFIG_BAT1_NAME="SDRAM_UPPER" +CONFIG_BAT1_BASE=0x10000000 +CONFIG_BAT1_LENGTH_256_MBYTES=y +CONFIG_BAT1_ACCESS_RW=y +CONFIG_BAT1_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT1_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT1_USER_MODE_VALID=y +CONFIG_BAT1_SUPERVISOR_MODE_VALID=y +CONFIG_BAT2=y +CONFIG_BAT2_NAME="STACK_IN_DCACHE" +CONFIG_BAT2_BASE=0x20000000 +CONFIG_BAT2_ACCESS_RW=y +CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT2_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT2_USER_MODE_VALID=y +CONFIG_BAT2_SUPERVISOR_MODE_VALID=y +CONFIG_BAT3=y +CONFIG_BAT3_NAME="PCI_MEM_BASE" +CONFIG_BAT3_BASE=0x90000000 +CONFIG_BAT3_LENGTH_256_MBYTES=y +CONFIG_BAT3_ACCESS_RW=y +CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT3_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT3_USER_MODE_VALID=y +CONFIG_BAT3_SUPERVISOR_MODE_VALID=y +CONFIG_BAT4=y +CONFIG_BAT4_NAME="PCI_MMIO" +CONFIG_BAT4_BASE=0xA0000000 +CONFIG_BAT4_LENGTH_256_MBYTES=y +CONFIG_BAT4_ACCESS_RW=y +CONFIG_BAT4_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT4_ICACHE_GUARDED=y +CONFIG_BAT4_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT4_DCACHE_GUARDED=y +CONFIG_BAT4_USER_MODE_VALID=y +CONFIG_BAT4_SUPERVISOR_MODE_VALID=y +CONFIG_BAT5=y +CONFIG_BAT5_NAME="PCI_IO" +CONFIG_BAT5_BASE=0xE2000000 +CONFIG_BAT5_LENGTH_16_MBYTES=y +CONFIG_BAT5_ACCESS_RW=y +CONFIG_BAT5_ICACHE_INHIBITED=y +CONFIG_BAT5_ICACHE_GUARDED=y +CONFIG_BAT5_DCACHE_INHIBITED=y +CONFIG_BAT5_DCACHE_GUARDED=y +CONFIG_BAT5_USER_MODE_VALID=y +CONFIG_BAT5_SUPERVISOR_MODE_VALID=y +CONFIG_BAT6=y +CONFIG_BAT6_NAME="IMMR" +CONFIG_BAT6_BASE=0xFF400000 +CONFIG_BAT6_LENGTH_1_MBYTES=y +CONFIG_BAT6_ACCESS_RW=y +CONFIG_BAT6_ICACHE_INHIBITED=y +CONFIG_BAT6_ICACHE_GUARDED=y +CONFIG_BAT6_DCACHE_INHIBITED=y +CONFIG_BAT6_DCACHE_GUARDED=y +CONFIG_BAT6_USER_MODE_VALID=y +CONFIG_BAT6_SUPERVISOR_MODE_VALID=y +CONFIG_BAT7=y +CONFIG_BAT7_NAME="FLASH" +CONFIG_BAT7_BASE=0x80000000 +CONFIG_BAT7_LENGTH_256_MBYTES=y +CONFIG_BAT7_ACCESS_RW=y +CONFIG_BAT7_ICACHE_INHIBITED=y +CONFIG_BAT7_ICACHE_GUARDED=y +CONFIG_BAT7_DCACHE_INHIBITED=y +CONFIG_BAT7_DCACHE_GUARDED=y +CONFIG_BAT7_USER_MODE_VALID=y +CONFIG_BAT7_SUPERVISOR_MODE_VALID=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/caddy2_defconfig b/configs/caddy2_defconfig index b52ea881ce..2665e72573 100644 --- a/configs/caddy2_defconfig +++ b/configs/caddy2_defconfig @@ -14,6 +14,55 @@ CONFIG_BOOT_MEMORY_SPACE_LOW=y CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_TSEC1_MODE_GMII=y CONFIG_TSEC2_MODE_GMII=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="SDRAM" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_256_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT1=y +CONFIG_BAT1_NAME="PCI1_MEM" +CONFIG_BAT1_BASE=0x80000000 +CONFIG_BAT1_LENGTH_256_MBYTES=y +CONFIG_BAT1_ACCESS_RW=y +CONFIG_BAT1_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT1_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT1_USER_MODE_VALID=y +CONFIG_BAT1_SUPERVISOR_MODE_VALID=y +CONFIG_BAT2=y +CONFIG_BAT2_NAME="PCI1_MMIO" +CONFIG_BAT2_BASE=0x90000000 +CONFIG_BAT2_LENGTH_256_MBYTES=y +CONFIG_BAT2_ACCESS_RW=y +CONFIG_BAT2_ICACHE_INHIBITED=y +CONFIG_BAT2_ICACHE_GUARDED=y +CONFIG_BAT2_DCACHE_INHIBITED=y +CONFIG_BAT2_DCACHE_GUARDED=y +CONFIG_BAT2_USER_MODE_VALID=y +CONFIG_BAT2_SUPERVISOR_MODE_VALID=y +CONFIG_BAT5=y +CONFIG_BAT5_NAME="IMMR_PCIIO" +CONFIG_BAT5_BASE=0xE0000000 +CONFIG_BAT5_LENGTH_256_MBYTES=y +CONFIG_BAT5_ACCESS_RW=y +CONFIG_BAT5_ICACHE_INHIBITED=y +CONFIG_BAT5_ICACHE_GUARDED=y +CONFIG_BAT5_DCACHE_INHIBITED=y +CONFIG_BAT5_DCACHE_GUARDED=y +CONFIG_BAT5_USER_MODE_VALID=y +CONFIG_BAT5_SUPERVISOR_MODE_VALID=y +CONFIG_BAT6=y +CONFIG_BAT6_NAME="UNKNOWN" +CONFIG_BAT6_BASE=0xF0000000 +CONFIG_BAT6_LENGTH_256_MBYTES=y +CONFIG_BAT6_ACCESS_RW=y +CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT6_USER_MODE_VALID=y +CONFIG_BAT6_SUPERVISOR_MODE_VALID=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/hrcon_defconfig b/configs/hrcon_defconfig index 97fe0e06fe..deed831c11 100644 --- a/configs/hrcon_defconfig +++ b/configs/hrcon_defconfig @@ -10,6 +10,42 @@ CONFIG_CORE_PLL_RATIO_3_1=y CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_TSEC1_MODE_RGMII=y CONFIG_TSEC2_MODE_RGMII=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="DDR" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_128_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT1=y +CONFIG_BAT1_NAME="IMMRBAR" +CONFIG_BAT1_BASE=0xE0000000 +CONFIG_BAT1_LENGTH_8_MBYTES=y +CONFIG_BAT1_ACCESS_RW=y +CONFIG_BAT1_ICACHE_INHIBITED=y +CONFIG_BAT1_ICACHE_GUARDED=y +CONFIG_BAT1_DCACHE_INHIBITED=y +CONFIG_BAT1_DCACHE_GUARDED=y +CONFIG_BAT1_USER_MODE_VALID=y +CONFIG_BAT1_SUPERVISOR_MODE_VALID=y +CONFIG_BAT2=y +CONFIG_BAT2_NAME="FLASH" +CONFIG_BAT2_BASE=0xFE000000 +CONFIG_BAT2_LENGTH_8_MBYTES=y +CONFIG_BAT2_ACCESS_RW=y +CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT2_DCACHE_INHIBITED=y +CONFIG_BAT2_DCACHE_GUARDED=y +CONFIG_BAT2_USER_MODE_VALID=y +CONFIG_BAT2_SUPERVISOR_MODE_VALID=y +CONFIG_BAT3=y +CONFIG_BAT3_NAME="STACK_IN_DCACHE" +CONFIG_BAT3_BASE=0xE6000000 +CONFIG_BAT3_ACCESS_RW=y +CONFIG_BAT3_USER_MODE_VALID=y +CONFIG_BAT3_SUPERVISOR_MODE_VALID=y CONFIG_CMD_IOLOOP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/hrcon_dh_defconfig b/configs/hrcon_dh_defconfig index 83dd6bf3a9..c113543472 100644 --- a/configs/hrcon_dh_defconfig +++ b/configs/hrcon_dh_defconfig @@ -10,6 +10,42 @@ CONFIG_CORE_PLL_RATIO_3_1=y CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_TSEC1_MODE_RGMII=y CONFIG_TSEC2_MODE_RGMII=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="DDR" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_128_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT1=y +CONFIG_BAT1_NAME="IMMRBAR" +CONFIG_BAT1_BASE=0xE0000000 +CONFIG_BAT1_LENGTH_8_MBYTES=y +CONFIG_BAT1_ACCESS_RW=y +CONFIG_BAT1_ICACHE_INHIBITED=y +CONFIG_BAT1_ICACHE_GUARDED=y +CONFIG_BAT1_DCACHE_INHIBITED=y +CONFIG_BAT1_DCACHE_GUARDED=y +CONFIG_BAT1_USER_MODE_VALID=y +CONFIG_BAT1_SUPERVISOR_MODE_VALID=y +CONFIG_BAT2=y +CONFIG_BAT2_NAME="FLASH" +CONFIG_BAT2_BASE=0xFE000000 +CONFIG_BAT2_LENGTH_8_MBYTES=y +CONFIG_BAT2_ACCESS_RW=y +CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT2_DCACHE_INHIBITED=y +CONFIG_BAT2_DCACHE_GUARDED=y +CONFIG_BAT2_USER_MODE_VALID=y +CONFIG_BAT2_SUPERVISOR_MODE_VALID=y +CONFIG_BAT3=y +CONFIG_BAT3_NAME="STACK_IN_DCACHE" +CONFIG_BAT3_BASE=0xE6000000 +CONFIG_BAT3_ACCESS_RW=y +CONFIG_BAT3_USER_MODE_VALID=y +CONFIG_BAT3_SUPERVISOR_MODE_VALID=y CONFIG_CMD_IOLOOP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/ids8313_defconfig b/configs/ids8313_defconfig index a8619ef621..4afed47033 100644 --- a/configs/ids8313_defconfig +++ b/configs/ids8313_defconfig @@ -7,6 +7,52 @@ CONFIG_TARGET_IDS8313=y CONFIG_CORE_PLL_RATIO_2_1=y CONFIG_PCI_HOST_MODE_ENABLE=y CONFIG_BOOT_ROM_INTERFACE_GPCM_8BIT=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="SDRAM" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_256_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT1=y +CONFIG_BAT1_NAME="INITRAM" +CONFIG_BAT1_BASE=0xFD000000 +CONFIG_BAT1_LENGTH_256_KBYTES=y +CONFIG_BAT1_ACCESS_RW=y +CONFIG_BAT1_ICACHE_GUARDED=y +CONFIG_BAT1_DCACHE_GUARDED=y +CONFIG_BAT1_USER_MODE_VALID=y +CONFIG_BAT1_SUPERVISOR_MODE_VALID=y +CONFIG_BAT2=y +CONFIG_BAT2_NAME="FLASH" +CONFIG_BAT2_BASE=0xFF800000 +CONFIG_BAT2_LENGTH_8_MBYTES=y +CONFIG_BAT2_ACCESS_RW=y +CONFIG_BAT2_ICACHE_GUARDED=y +CONFIG_BAT2_DCACHE_INHIBITED=y +CONFIG_BAT2_DCACHE_GUARDED=y +CONFIG_BAT2_USER_MODE_VALID=y +CONFIG_BAT2_SUPERVISOR_MODE_VALID=y +CONFIG_BAT5=y +CONFIG_BAT5_NAME="IMMR" +CONFIG_BAT5_BASE=0xF0000000 +CONFIG_BAT5_LENGTH_128_MBYTES=y +CONFIG_BAT5_ACCESS_RW=y +CONFIG_BAT5_ICACHE_INHIBITED=y +CONFIG_BAT5_ICACHE_GUARDED=y +CONFIG_BAT5_DCACHE_INHIBITED=y +CONFIG_BAT5_DCACHE_GUARDED=y +CONFIG_BAT5_USER_MODE_VALID=y +CONFIG_BAT5_SUPERVISOR_MODE_VALID=y +CONFIG_BAT6=y +CONFIG_BAT6_NAME="NAND_MRAM_CPLD" +CONFIG_BAT6_BASE=0xE0000000 +CONFIG_BAT6_LENGTH_256_MBYTES=y +CONFIG_BAT6_ACCESS_RW=y +CONFIG_BAT6_ICACHE_GUARDED=y +CONFIG_BAT6_DCACHE_GUARDED=y +CONFIG_BAT6_USER_MODE_VALID=y +CONFIG_BAT6_SUPERVISOR_MODE_VALID=y CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_IMAGE_FORMAT_LEGACY=y diff --git a/configs/kmcoge5ne_defconfig b/configs/kmcoge5ne_defconfig index 03437f7cb8..a358e28886 100644 --- a/configs/kmcoge5ne_defconfig +++ b/configs/kmcoge5ne_defconfig @@ -13,6 +13,85 @@ CONFIG_BOOT_MEMORY_SPACE_LOW=y CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_LALE_TIMING_EARLIER=y CONFIG_LDP_PIN_MUX_STATE_0=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="SDRAM_LOWER" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_256_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_ICACHE_INHIBITED=y +CONFIG_BAT0_ICACHE_GUARDED=y +CONFIG_BAT0_DCACHE_INHIBITED=y +CONFIG_BAT0_DCACHE_GUARDED=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT1=y +CONFIG_BAT1_NAME="IMMR" +CONFIG_BAT1_BASE=0xE0000000 +CONFIG_BAT1_LENGTH_4_MBYTES=y +CONFIG_BAT1_ACCESS_RW=y +CONFIG_BAT1_ICACHE_INHIBITED=y +CONFIG_BAT1_ICACHE_GUARDED=y +CONFIG_BAT1_DCACHE_INHIBITED=y +CONFIG_BAT1_DCACHE_GUARDED=y +CONFIG_BAT1_USER_MODE_VALID=y +CONFIG_BAT1_SUPERVISOR_MODE_VALID=y +CONFIG_BAT2=y +CONFIG_BAT2_NAME="KMBEC_FPGA" +CONFIG_BAT2_BASE=0xE8000000 +CONFIG_BAT2_LENGTH_128_MBYTES=y +CONFIG_BAT2_ACCESS_RW=y +CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT2_DCACHE_INHIBITED=y +CONFIG_BAT2_DCACHE_GUARDED=y +CONFIG_BAT2_USER_MODE_VALID=y +CONFIG_BAT2_SUPERVISOR_MODE_VALID=y +CONFIG_BAT3=y +CONFIG_BAT3_NAME="FLASH" +CONFIG_BAT3_BASE=0xF0000000 +CONFIG_BAT3_LENGTH_256_MBYTES=y +CONFIG_BAT3_ACCESS_RW=y +CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT3_DCACHE_INHIBITED=y +CONFIG_BAT3_DCACHE_GUARDED=y +CONFIG_BAT3_USER_MODE_VALID=y +CONFIG_BAT3_SUPERVISOR_MODE_VALID=y +CONFIG_BAT4=y +CONFIG_BAT4_NAME="STACK_IN_DCACHE" +CONFIG_BAT4_BASE=0xE6000000 +CONFIG_BAT4_ACCESS_RW=y +CONFIG_BAT4_USER_MODE_VALID=y +CONFIG_BAT4_SUPERVISOR_MODE_VALID=y +CONFIG_BAT5=y +CONFIG_BAT5_NAME="PAXE" +CONFIG_BAT5_BASE=0xA0000000 +CONFIG_BAT5_LENGTH_256_MBYTES=y +CONFIG_BAT5_ACCESS_RW=y +CONFIG_BAT5_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT5_DCACHE_INHIBITED=y +CONFIG_BAT5_DCACHE_GUARDED=y +CONFIG_BAT5_USER_MODE_VALID=y +CONFIG_BAT5_SUPERVISOR_MODE_VALID=y +CONFIG_BAT6=y +CONFIG_BAT6_NAME="BFTIC3" +CONFIG_BAT6_BASE=0xB0000000 +CONFIG_BAT6_LENGTH_256_MBYTES=y +CONFIG_BAT6_ACCESS_RW=y +CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT6_DCACHE_INHIBITED=y +CONFIG_BAT6_DCACHE_GUARDED=y +CONFIG_BAT6_USER_MODE_VALID=y +CONFIG_BAT6_SUPERVISOR_MODE_VALID=y +CONFIG_BAT7=y +CONFIG_BAT7_NAME="SDRAM_UPPER" +CONFIG_BAT7_BASE=0x10000000 +CONFIG_BAT7_LENGTH_256_MBYTES=y +CONFIG_BAT7_ACCESS_RW=y +CONFIG_BAT7_ICACHE_INHIBITED=y +CONFIG_BAT7_ICACHE_GUARDED=y +CONFIG_BAT7_DCACHE_INHIBITED=y +CONFIG_BAT7_DCACHE_GUARDED=y +CONFIG_BAT7_USER_MODE_VALID=y +CONFIG_BAT7_SUPERVISOR_MODE_VALID=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_MISC_INIT_R=y diff --git a/configs/kmeter1_defconfig b/configs/kmeter1_defconfig index 600a1ad1dc..10f7fdf110 100644 --- a/configs/kmeter1_defconfig +++ b/configs/kmeter1_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xF0000000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y +CONFIG_HIGH_BATS=y CONFIG_TARGET_KMETER1=y CONFIG_DDR_MC_CLOCK_MODE_1_1=y CONFIG_SYSTEM_PLL_VCO_DIV_4=y @@ -12,6 +13,58 @@ CONFIG_BOOT_MEMORY_SPACE_LOW=y CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_LALE_TIMING_EARLIER=y CONFIG_LDP_PIN_MUX_STATE_0=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="SDRAM" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_256_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_ICACHE_INHIBITED=y +CONFIG_BAT0_ICACHE_GUARDED=y +CONFIG_BAT0_DCACHE_INHIBITED=y +CONFIG_BAT0_DCACHE_GUARDED=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT1=y +CONFIG_BAT1_NAME="IMMR" +CONFIG_BAT1_BASE=0xE0000000 +CONFIG_BAT1_LENGTH_4_MBYTES=y +CONFIG_BAT1_ACCESS_RW=y +CONFIG_BAT1_ICACHE_INHIBITED=y +CONFIG_BAT1_ICACHE_GUARDED=y +CONFIG_BAT1_DCACHE_INHIBITED=y +CONFIG_BAT1_DCACHE_GUARDED=y +CONFIG_BAT1_USER_MODE_VALID=y +CONFIG_BAT1_SUPERVISOR_MODE_VALID=y +CONFIG_BAT2=y +CONFIG_BAT2_NAME="KMBEC_FPGA" +CONFIG_BAT2_BASE=0xE8000000 +CONFIG_BAT2_LENGTH_128_MBYTES=y +CONFIG_BAT2_ACCESS_RW=y +CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT2_DCACHE_INHIBITED=y +CONFIG_BAT2_DCACHE_GUARDED=y +CONFIG_BAT2_USER_MODE_VALID=y +CONFIG_BAT2_SUPERVISOR_MODE_VALID=y +CONFIG_BAT3=y +CONFIG_BAT3_NAME="FLASH" +CONFIG_BAT3_BASE=0xF0000000 +CONFIG_BAT3_LENGTH_256_MBYTES=y +CONFIG_BAT3_ACCESS_RW=y +CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT3_DCACHE_INHIBITED=y +CONFIG_BAT3_DCACHE_GUARDED=y +CONFIG_BAT3_USER_MODE_VALID=y +CONFIG_BAT3_SUPERVISOR_MODE_VALID=y +CONFIG_BAT5=y +CONFIG_BAT5_NAME="PAXE" +CONFIG_BAT5_BASE=0xA0000000 +CONFIG_BAT5_LENGTH_256_MBYTES=y +CONFIG_BAT5_ACCESS_RW=y +CONFIG_BAT5_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT5_DCACHE_INHIBITED=y +CONFIG_BAT5_DCACHE_GUARDED=y +CONFIG_BAT5_USER_MODE_VALID=y +CONFIG_BAT5_SUPERVISOR_MODE_VALID=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_MISC_INIT_R=y diff --git a/configs/kmopti2_defconfig b/configs/kmopti2_defconfig index ba489eeb6a..b32b39113f 100644 --- a/configs/kmopti2_defconfig +++ b/configs/kmopti2_defconfig @@ -8,6 +8,74 @@ CONFIG_CORE_PLL_RATIO_25_1=y CONFIG_QUICC_MULT_FACTOR_3=y CONFIG_BOOT_MEMORY_SPACE_LOW=y CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="SDRAM" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_256_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_ICACHE_INHIBITED=y +CONFIG_BAT0_ICACHE_GUARDED=y +CONFIG_BAT0_DCACHE_INHIBITED=y +CONFIG_BAT0_DCACHE_GUARDED=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT1=y +CONFIG_BAT1_NAME="IMMR" +CONFIG_BAT1_BASE=0xE0000000 +CONFIG_BAT1_LENGTH_4_MBYTES=y +CONFIG_BAT1_ACCESS_RW=y +CONFIG_BAT1_ICACHE_INHIBITED=y +CONFIG_BAT1_ICACHE_GUARDED=y +CONFIG_BAT1_DCACHE_INHIBITED=y +CONFIG_BAT1_DCACHE_GUARDED=y +CONFIG_BAT1_USER_MODE_VALID=y +CONFIG_BAT1_SUPERVISOR_MODE_VALID=y +CONFIG_BAT2=y +CONFIG_BAT2_NAME="KMBEC_FPGA" +CONFIG_BAT2_BASE=0xE8000000 +CONFIG_BAT2_LENGTH_128_MBYTES=y +CONFIG_BAT2_ACCESS_RW=y +CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT2_DCACHE_INHIBITED=y +CONFIG_BAT2_DCACHE_GUARDED=y +CONFIG_BAT2_USER_MODE_VALID=y +CONFIG_BAT2_SUPERVISOR_MODE_VALID=y +CONFIG_BAT3=y +CONFIG_BAT3_NAME="FLASH" +CONFIG_BAT3_BASE=0xF0000000 +CONFIG_BAT3_LENGTH_256_MBYTES=y +CONFIG_BAT3_ACCESS_RW=y +CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT3_DCACHE_INHIBITED=y +CONFIG_BAT3_DCACHE_GUARDED=y +CONFIG_BAT3_USER_MODE_VALID=y +CONFIG_BAT3_SUPERVISOR_MODE_VALID=y +CONFIG_BAT4=y +CONFIG_BAT4_NAME="STACK_IN_DCACHE" +CONFIG_BAT4_BASE=0xE6000000 +CONFIG_BAT4_ACCESS_RW=y +CONFIG_BAT4_USER_MODE_VALID=y +CONFIG_BAT4_SUPERVISOR_MODE_VALID=y +CONFIG_BAT5=y +CONFIG_BAT5_NAME="APP1" +CONFIG_BAT5_BASE=0xA0000000 +CONFIG_BAT5_LENGTH_256_MBYTES=y +CONFIG_BAT5_ACCESS_RW=y +CONFIG_BAT5_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT5_DCACHE_INHIBITED=y +CONFIG_BAT5_DCACHE_GUARDED=y +CONFIG_BAT5_USER_MODE_VALID=y +CONFIG_BAT5_SUPERVISOR_MODE_VALID=y +CONFIG_BAT6=y +CONFIG_BAT6_NAME="APP2" +CONFIG_BAT6_BASE=0xB0000000 +CONFIG_BAT6_LENGTH_256_MBYTES=y +CONFIG_BAT6_ACCESS_RW=y +CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT6_DCACHE_INHIBITED=y +CONFIG_BAT6_DCACHE_GUARDED=y +CONFIG_BAT6_USER_MODE_VALID=y +CONFIG_BAT6_SUPERVISOR_MODE_VALID=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_MISC_INIT_R=y diff --git a/configs/kmsupx5_defconfig b/configs/kmsupx5_defconfig index f39bca4fbd..cc94d174f0 100644 --- a/configs/kmsupx5_defconfig +++ b/configs/kmsupx5_defconfig @@ -8,6 +8,64 @@ CONFIG_CORE_PLL_RATIO_25_1=y CONFIG_QUICC_MULT_FACTOR_3=y CONFIG_BOOT_MEMORY_SPACE_LOW=y CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="SDRAM" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_256_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_ICACHE_INHIBITED=y +CONFIG_BAT0_ICACHE_GUARDED=y +CONFIG_BAT0_DCACHE_INHIBITED=y +CONFIG_BAT0_DCACHE_GUARDED=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT1=y +CONFIG_BAT1_NAME="IMMR" +CONFIG_BAT1_BASE=0xE0000000 +CONFIG_BAT1_LENGTH_4_MBYTES=y +CONFIG_BAT1_ACCESS_RW=y +CONFIG_BAT1_ICACHE_INHIBITED=y +CONFIG_BAT1_ICACHE_GUARDED=y +CONFIG_BAT1_DCACHE_INHIBITED=y +CONFIG_BAT1_DCACHE_GUARDED=y +CONFIG_BAT1_USER_MODE_VALID=y +CONFIG_BAT1_SUPERVISOR_MODE_VALID=y +CONFIG_BAT2=y +CONFIG_BAT2_NAME="KMBEC_FPGA" +CONFIG_BAT2_BASE=0xE8000000 +CONFIG_BAT2_LENGTH_128_MBYTES=y +CONFIG_BAT2_ACCESS_RW=y +CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT2_DCACHE_INHIBITED=y +CONFIG_BAT2_DCACHE_GUARDED=y +CONFIG_BAT2_USER_MODE_VALID=y +CONFIG_BAT2_SUPERVISOR_MODE_VALID=y +CONFIG_BAT3=y +CONFIG_BAT3_NAME="FLASH" +CONFIG_BAT3_BASE=0xF0000000 +CONFIG_BAT3_LENGTH_256_MBYTES=y +CONFIG_BAT3_ACCESS_RW=y +CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT3_DCACHE_INHIBITED=y +CONFIG_BAT3_DCACHE_GUARDED=y +CONFIG_BAT3_USER_MODE_VALID=y +CONFIG_BAT3_SUPERVISOR_MODE_VALID=y +CONFIG_BAT4=y +CONFIG_BAT4_NAME="STACK_IN_DCACHE" +CONFIG_BAT4_BASE=0xE6000000 +CONFIG_BAT4_ACCESS_RW=y +CONFIG_BAT4_USER_MODE_VALID=y +CONFIG_BAT4_SUPERVISOR_MODE_VALID=y +CONFIG_BAT5=y +CONFIG_BAT5_NAME="APP1" +CONFIG_BAT5_BASE=0xA0000000 +CONFIG_BAT5_LENGTH_256_MBYTES=y +CONFIG_BAT5_ACCESS_RW=y +CONFIG_BAT5_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT5_DCACHE_INHIBITED=y +CONFIG_BAT5_DCACHE_GUARDED=y +CONFIG_BAT5_USER_MODE_VALID=y +CONFIG_BAT5_SUPERVISOR_MODE_VALID=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_MISC_INIT_R=y diff --git a/configs/kmtegr1_defconfig b/configs/kmtegr1_defconfig index 3e7b2f73fd..994e1525f7 100644 --- a/configs/kmtegr1_defconfig +++ b/configs/kmtegr1_defconfig @@ -9,6 +9,64 @@ CONFIG_CORE_PLL_RATIO_2_1=y CONFIG_QUICC_MULT_FACTOR_3=y CONFIG_BOOT_MEMORY_SPACE_LOW=y CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="SDRAM" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_256_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_ICACHE_INHIBITED=y +CONFIG_BAT0_ICACHE_GUARDED=y +CONFIG_BAT0_DCACHE_INHIBITED=y +CONFIG_BAT0_DCACHE_GUARDED=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT1=y +CONFIG_BAT1_NAME="IMMR" +CONFIG_BAT1_BASE=0xE0000000 +CONFIG_BAT1_LENGTH_4_MBYTES=y +CONFIG_BAT1_ACCESS_RW=y +CONFIG_BAT1_ICACHE_INHIBITED=y +CONFIG_BAT1_ICACHE_GUARDED=y +CONFIG_BAT1_DCACHE_INHIBITED=y +CONFIG_BAT1_DCACHE_GUARDED=y +CONFIG_BAT1_USER_MODE_VALID=y +CONFIG_BAT1_SUPERVISOR_MODE_VALID=y +CONFIG_BAT2=y +CONFIG_BAT2_NAME="KMBEC_FPGA" +CONFIG_BAT2_BASE=0xE8000000 +CONFIG_BAT2_LENGTH_128_MBYTES=y +CONFIG_BAT2_ACCESS_RW=y +CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT2_DCACHE_INHIBITED=y +CONFIG_BAT2_DCACHE_GUARDED=y +CONFIG_BAT2_USER_MODE_VALID=y +CONFIG_BAT2_SUPERVISOR_MODE_VALID=y +CONFIG_BAT3=y +CONFIG_BAT3_NAME="FLASH" +CONFIG_BAT3_BASE=0xF0000000 +CONFIG_BAT3_LENGTH_256_MBYTES=y +CONFIG_BAT3_ACCESS_RW=y +CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT3_DCACHE_INHIBITED=y +CONFIG_BAT3_DCACHE_GUARDED=y +CONFIG_BAT3_USER_MODE_VALID=y +CONFIG_BAT3_SUPERVISOR_MODE_VALID=y +CONFIG_BAT4=y +CONFIG_BAT4_NAME="STACK_IN_DCACHE" +CONFIG_BAT4_BASE=0xE6000000 +CONFIG_BAT4_ACCESS_RW=y +CONFIG_BAT4_USER_MODE_VALID=y +CONFIG_BAT4_SUPERVISOR_MODE_VALID=y +CONFIG_BAT6=y +CONFIG_BAT6_NAME="APP2" +CONFIG_BAT6_BASE=0xB0000000 +CONFIG_BAT6_LENGTH_256_MBYTES=y +CONFIG_BAT6_ACCESS_RW=y +CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT6_DCACHE_INHIBITED=y +CONFIG_BAT6_DCACHE_GUARDED=y +CONFIG_BAT6_USER_MODE_VALID=y +CONFIG_BAT6_SUPERVISOR_MODE_VALID=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="KMTEGR1" diff --git a/configs/kmtepr2_defconfig b/configs/kmtepr2_defconfig index 0f32283e9d..bb23786057 100644 --- a/configs/kmtepr2_defconfig +++ b/configs/kmtepr2_defconfig @@ -8,6 +8,74 @@ CONFIG_CORE_PLL_RATIO_25_1=y CONFIG_QUICC_MULT_FACTOR_3=y CONFIG_BOOT_MEMORY_SPACE_LOW=y CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="SDRAM" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_256_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_ICACHE_INHIBITED=y +CONFIG_BAT0_ICACHE_GUARDED=y +CONFIG_BAT0_DCACHE_INHIBITED=y +CONFIG_BAT0_DCACHE_GUARDED=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT1=y +CONFIG_BAT1_NAME="IMMR" +CONFIG_BAT1_BASE=0xE0000000 +CONFIG_BAT1_LENGTH_4_MBYTES=y +CONFIG_BAT1_ACCESS_RW=y +CONFIG_BAT1_ICACHE_INHIBITED=y +CONFIG_BAT1_ICACHE_GUARDED=y +CONFIG_BAT1_DCACHE_INHIBITED=y +CONFIG_BAT1_DCACHE_GUARDED=y +CONFIG_BAT1_USER_MODE_VALID=y +CONFIG_BAT1_SUPERVISOR_MODE_VALID=y +CONFIG_BAT2=y +CONFIG_BAT2_NAME="KMBEC_FPGA" +CONFIG_BAT2_BASE=0xE8000000 +CONFIG_BAT2_LENGTH_128_MBYTES=y +CONFIG_BAT2_ACCESS_RW=y +CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT2_DCACHE_INHIBITED=y +CONFIG_BAT2_DCACHE_GUARDED=y +CONFIG_BAT2_USER_MODE_VALID=y +CONFIG_BAT2_SUPERVISOR_MODE_VALID=y +CONFIG_BAT3=y +CONFIG_BAT3_NAME="FLASH" +CONFIG_BAT3_BASE=0xF0000000 +CONFIG_BAT3_LENGTH_256_MBYTES=y +CONFIG_BAT3_ACCESS_RW=y +CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT3_DCACHE_INHIBITED=y +CONFIG_BAT3_DCACHE_GUARDED=y +CONFIG_BAT3_USER_MODE_VALID=y +CONFIG_BAT3_SUPERVISOR_MODE_VALID=y +CONFIG_BAT4=y +CONFIG_BAT4_NAME="STACK_IN_DCACHE" +CONFIG_BAT4_BASE=0xE6000000 +CONFIG_BAT4_ACCESS_RW=y +CONFIG_BAT4_USER_MODE_VALID=y +CONFIG_BAT4_SUPERVISOR_MODE_VALID=y +CONFIG_BAT5=y +CONFIG_BAT5_NAME="APP1" +CONFIG_BAT5_BASE=0xA0000000 +CONFIG_BAT5_LENGTH_256_MBYTES=y +CONFIG_BAT5_ACCESS_RW=y +CONFIG_BAT5_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT5_DCACHE_INHIBITED=y +CONFIG_BAT5_DCACHE_GUARDED=y +CONFIG_BAT5_USER_MODE_VALID=y +CONFIG_BAT5_SUPERVISOR_MODE_VALID=y +CONFIG_BAT6=y +CONFIG_BAT6_NAME="APP2" +CONFIG_BAT6_BASE=0xB0000000 +CONFIG_BAT6_LENGTH_256_MBYTES=y +CONFIG_BAT6_ACCESS_RW=y +CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT6_DCACHE_INHIBITED=y +CONFIG_BAT6_DCACHE_GUARDED=y +CONFIG_BAT6_USER_MODE_VALID=y +CONFIG_BAT6_SUPERVISOR_MODE_VALID=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_MISC_INIT_R=y diff --git a/configs/kmvect1_defconfig b/configs/kmvect1_defconfig index ec3ff28793..666dbf32cc 100644 --- a/configs/kmvect1_defconfig +++ b/configs/kmvect1_defconfig @@ -9,6 +9,74 @@ CONFIG_CORE_PLL_RATIO_2_1=y CONFIG_QUICC_MULT_FACTOR_3=y CONFIG_BOOT_MEMORY_SPACE_LOW=y CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="SDRAM" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_256_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_ICACHE_INHIBITED=y +CONFIG_BAT0_ICACHE_GUARDED=y +CONFIG_BAT0_DCACHE_INHIBITED=y +CONFIG_BAT0_DCACHE_GUARDED=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT1=y +CONFIG_BAT1_NAME="IMMR" +CONFIG_BAT1_BASE=0xE0000000 +CONFIG_BAT1_LENGTH_4_MBYTES=y +CONFIG_BAT1_ACCESS_RW=y +CONFIG_BAT1_ICACHE_INHIBITED=y +CONFIG_BAT1_ICACHE_GUARDED=y +CONFIG_BAT1_DCACHE_INHIBITED=y +CONFIG_BAT1_DCACHE_GUARDED=y +CONFIG_BAT1_USER_MODE_VALID=y +CONFIG_BAT1_SUPERVISOR_MODE_VALID=y +CONFIG_BAT2=y +CONFIG_BAT2_NAME="KMBEC_FPGA" +CONFIG_BAT2_BASE=0xE8000000 +CONFIG_BAT2_LENGTH_128_MBYTES=y +CONFIG_BAT2_ACCESS_RW=y +CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT2_DCACHE_INHIBITED=y +CONFIG_BAT2_DCACHE_GUARDED=y +CONFIG_BAT2_USER_MODE_VALID=y +CONFIG_BAT2_SUPERVISOR_MODE_VALID=y +CONFIG_BAT3=y +CONFIG_BAT3_NAME="FLASH" +CONFIG_BAT3_BASE=0xF0000000 +CONFIG_BAT3_LENGTH_256_MBYTES=y +CONFIG_BAT3_ACCESS_RW=y +CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT3_DCACHE_INHIBITED=y +CONFIG_BAT3_DCACHE_GUARDED=y +CONFIG_BAT3_USER_MODE_VALID=y +CONFIG_BAT3_SUPERVISOR_MODE_VALID=y +CONFIG_BAT4=y +CONFIG_BAT4_NAME="STACK_IN_DCACHE" +CONFIG_BAT4_BASE=0xE6000000 +CONFIG_BAT4_ACCESS_RW=y +CONFIG_BAT4_USER_MODE_VALID=y +CONFIG_BAT4_SUPERVISOR_MODE_VALID=y +CONFIG_BAT5=y +CONFIG_BAT5_NAME="APP1" +CONFIG_BAT5_BASE=0xA0000000 +CONFIG_BAT5_LENGTH_256_MBYTES=y +CONFIG_BAT5_ACCESS_RW=y +CONFIG_BAT5_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT5_DCACHE_INHIBITED=y +CONFIG_BAT5_DCACHE_GUARDED=y +CONFIG_BAT5_USER_MODE_VALID=y +CONFIG_BAT5_SUPERVISOR_MODE_VALID=y +CONFIG_BAT6=y +CONFIG_BAT6_NAME="APP2" +CONFIG_BAT6_BASE=0xB0000000 +CONFIG_BAT6_LENGTH_256_MBYTES=y +CONFIG_BAT6_ACCESS_RW=y +CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT6_DCACHE_INHIBITED=y +CONFIG_BAT6_DCACHE_GUARDED=y +CONFIG_BAT6_USER_MODE_VALID=y +CONFIG_BAT6_SUPERVISOR_MODE_VALID=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="KMVECT1" diff --git a/configs/mpc8308_p1m_defconfig b/configs/mpc8308_p1m_defconfig index cb24c97f04..f583fa922e 100644 --- a/configs/mpc8308_p1m_defconfig +++ b/configs/mpc8308_p1m_defconfig @@ -8,6 +8,42 @@ CONFIG_SYSTEM_PLL_FACTOR_4_1=y CONFIG_CORE_PLL_RATIO_3_1=y CONFIG_BOOT_MEMORY_SPACE_LOW=y CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="DDR" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_128_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT1=y +CONFIG_BAT1_NAME="IMMRBAR" +CONFIG_BAT1_BASE=0xE0000000 +CONFIG_BAT1_LENGTH_8_MBYTES=y +CONFIG_BAT1_ACCESS_RW=y +CONFIG_BAT1_ICACHE_INHIBITED=y +CONFIG_BAT1_ICACHE_GUARDED=y +CONFIG_BAT1_DCACHE_INHIBITED=y +CONFIG_BAT1_DCACHE_GUARDED=y +CONFIG_BAT1_USER_MODE_VALID=y +CONFIG_BAT1_SUPERVISOR_MODE_VALID=y +CONFIG_BAT2=y +CONFIG_BAT2_NAME="FLASH" +CONFIG_BAT2_BASE=0xFC000000 +CONFIG_BAT2_LENGTH_8_MBYTES=y +CONFIG_BAT2_ACCESS_RW=y +CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT2_DCACHE_INHIBITED=y +CONFIG_BAT2_DCACHE_GUARDED=y +CONFIG_BAT2_USER_MODE_VALID=y +CONFIG_BAT2_SUPERVISOR_MODE_VALID=y +CONFIG_BAT3=y +CONFIG_BAT3_NAME="STACKINDCACHE" +CONFIG_BAT3_BASE=0xE6000000 +CONFIG_BAT3_ACCESS_RW=y +CONFIG_BAT3_USER_MODE_VALID=y +CONFIG_BAT3_SUPERVISOR_MODE_VALID=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=5 diff --git a/configs/sbc8349_PCI_33_defconfig b/configs/sbc8349_PCI_33_defconfig index 47feb5ae36..f8ce309376 100644 --- a/configs/sbc8349_PCI_33_defconfig +++ b/configs/sbc8349_PCI_33_defconfig @@ -14,6 +14,57 @@ CONFIG_BOOT_MEMORY_SPACE_LOW=y CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_TSEC1_MODE_GMII=y CONFIG_TSEC2_MODE_GMII=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="SDRAM" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_256_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT1=y +CONFIG_BAT1_NAME="PCI1_MEM" +CONFIG_BAT1_BASE=0x80000000 +CONFIG_BAT1_LENGTH_256_MBYTES=y +CONFIG_BAT1_ACCESS_RW=y +CONFIG_BAT1_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT1_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT1_USER_MODE_VALID=y +CONFIG_BAT1_SUPERVISOR_MODE_VALID=y +CONFIG_BAT2=y +CONFIG_BAT2_NAME="PCI1_MMIO" +CONFIG_BAT2_BASE=0x90000000 +CONFIG_BAT2_LENGTH_256_MBYTES=y +CONFIG_BAT2_ACCESS_RW=y +CONFIG_BAT2_ICACHE_INHIBITED=y +CONFIG_BAT2_ICACHE_GUARDED=y +CONFIG_BAT2_DCACHE_INHIBITED=y +CONFIG_BAT2_DCACHE_GUARDED=y +CONFIG_BAT2_USER_MODE_VALID=y +CONFIG_BAT2_SUPERVISOR_MODE_VALID=y +CONFIG_BAT5=y +CONFIG_BAT5_NAME="IMMR_PCIIO" +CONFIG_BAT5_BASE=0xE0000000 +CONFIG_BAT5_LENGTH_256_MBYTES=y +CONFIG_BAT5_ACCESS_RW=y +CONFIG_BAT5_ICACHE_INHIBITED=y +CONFIG_BAT5_ICACHE_GUARDED=y +CONFIG_BAT5_DCACHE_INHIBITED=y +CONFIG_BAT5_DCACHE_GUARDED=y +CONFIG_BAT5_USER_MODE_VALID=y +CONFIG_BAT5_SUPERVISOR_MODE_VALID=y +CONFIG_BAT6=y +CONFIG_BAT6_NAME="LBC_INITRAM_FLASH" +CONFIG_BAT6_BASE=0xF0000000 +CONFIG_BAT6_LENGTH_256_MBYTES=y +CONFIG_BAT6_ACCESS_RW=y +CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT6_ICACHE_GUARDED=y +CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT6_DCACHE_GUARDED=y +CONFIG_BAT6_USER_MODE_VALID=y +CONFIG_BAT6_SUPERVISOR_MODE_VALID=y CONFIG_PCI_64BIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/configs/sbc8349_PCI_66_defconfig b/configs/sbc8349_PCI_66_defconfig index 019341691f..bc9e228894 100644 --- a/configs/sbc8349_PCI_66_defconfig +++ b/configs/sbc8349_PCI_66_defconfig @@ -14,6 +14,57 @@ CONFIG_BOOT_MEMORY_SPACE_LOW=y CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_TSEC1_MODE_GMII=y CONFIG_TSEC2_MODE_GMII=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="SDRAM" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_256_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT1=y +CONFIG_BAT1_NAME="PCI1_MEM" +CONFIG_BAT1_BASE=0x80000000 +CONFIG_BAT1_LENGTH_256_MBYTES=y +CONFIG_BAT1_ACCESS_RW=y +CONFIG_BAT1_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT1_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT1_USER_MODE_VALID=y +CONFIG_BAT1_SUPERVISOR_MODE_VALID=y +CONFIG_BAT2=y +CONFIG_BAT2_NAME="PCI1_MMIO" +CONFIG_BAT2_BASE=0x90000000 +CONFIG_BAT2_LENGTH_256_MBYTES=y +CONFIG_BAT2_ACCESS_RW=y +CONFIG_BAT2_ICACHE_INHIBITED=y +CONFIG_BAT2_ICACHE_GUARDED=y +CONFIG_BAT2_DCACHE_INHIBITED=y +CONFIG_BAT2_DCACHE_GUARDED=y +CONFIG_BAT2_USER_MODE_VALID=y +CONFIG_BAT2_SUPERVISOR_MODE_VALID=y +CONFIG_BAT5=y +CONFIG_BAT5_NAME="IMMR_PCIIO" +CONFIG_BAT5_BASE=0xE0000000 +CONFIG_BAT5_LENGTH_256_MBYTES=y +CONFIG_BAT5_ACCESS_RW=y +CONFIG_BAT5_ICACHE_INHIBITED=y +CONFIG_BAT5_ICACHE_GUARDED=y +CONFIG_BAT5_DCACHE_INHIBITED=y +CONFIG_BAT5_DCACHE_GUARDED=y +CONFIG_BAT5_USER_MODE_VALID=y +CONFIG_BAT5_SUPERVISOR_MODE_VALID=y +CONFIG_BAT6=y +CONFIG_BAT6_NAME="LBC_INITRAM_FLASH" +CONFIG_BAT6_BASE=0xF0000000 +CONFIG_BAT6_LENGTH_256_MBYTES=y +CONFIG_BAT6_ACCESS_RW=y +CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT6_ICACHE_GUARDED=y +CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT6_DCACHE_GUARDED=y +CONFIG_BAT6_USER_MODE_VALID=y +CONFIG_BAT6_SUPERVISOR_MODE_VALID=y CONFIG_PCI_64BIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/configs/sbc8349_defconfig b/configs/sbc8349_defconfig index f7c3de8e9e..d8e60da7be 100644 --- a/configs/sbc8349_defconfig +++ b/configs/sbc8349_defconfig @@ -14,6 +14,37 @@ CONFIG_BOOT_MEMORY_SPACE_LOW=y CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_TSEC1_MODE_GMII=y CONFIG_TSEC2_MODE_GMII=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="SDRAM" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_256_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT5=y +CONFIG_BAT5_NAME="IMMR_PCIIO" +CONFIG_BAT5_BASE=0xE0000000 +CONFIG_BAT5_LENGTH_256_MBYTES=y +CONFIG_BAT5_ACCESS_RW=y +CONFIG_BAT5_ICACHE_INHIBITED=y +CONFIG_BAT5_ICACHE_GUARDED=y +CONFIG_BAT5_DCACHE_INHIBITED=y +CONFIG_BAT5_DCACHE_GUARDED=y +CONFIG_BAT5_USER_MODE_VALID=y +CONFIG_BAT5_SUPERVISOR_MODE_VALID=y +CONFIG_BAT6=y +CONFIG_BAT6_NAME="LBC_INITRAM_FLASH" +CONFIG_BAT6_BASE=0xF0000000 +CONFIG_BAT6_LENGTH_256_MBYTES=y +CONFIG_BAT6_ACCESS_RW=y +CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT6_ICACHE_GUARDED=y +CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT6_DCACHE_GUARDED=y +CONFIG_BAT6_USER_MODE_VALID=y +CONFIG_BAT6_SUPERVISOR_MODE_VALID=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/strider_con_defconfig b/configs/strider_con_defconfig index c2faf3855e..508ffe201a 100644 --- a/configs/strider_con_defconfig +++ b/configs/strider_con_defconfig @@ -9,6 +9,42 @@ CONFIG_SYSTEM_PLL_FACTOR_4_1=y CONFIG_CORE_PLL_RATIO_3_1=y CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_TSEC2_MODE_RGMII=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="DDR" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_128_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT1=y +CONFIG_BAT1_NAME="IMMRBAR" +CONFIG_BAT1_BASE=0xE0000000 +CONFIG_BAT1_LENGTH_8_MBYTES=y +CONFIG_BAT1_ACCESS_RW=y +CONFIG_BAT1_ICACHE_INHIBITED=y +CONFIG_BAT1_ICACHE_GUARDED=y +CONFIG_BAT1_DCACHE_INHIBITED=y +CONFIG_BAT1_DCACHE_GUARDED=y +CONFIG_BAT1_USER_MODE_VALID=y +CONFIG_BAT1_SUPERVISOR_MODE_VALID=y +CONFIG_BAT2=y +CONFIG_BAT2_NAME="FLASH" +CONFIG_BAT2_BASE=0xFE000000 +CONFIG_BAT2_LENGTH_8_MBYTES=y +CONFIG_BAT2_ACCESS_RW=y +CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT2_DCACHE_INHIBITED=y +CONFIG_BAT2_DCACHE_GUARDED=y +CONFIG_BAT2_USER_MODE_VALID=y +CONFIG_BAT2_SUPERVISOR_MODE_VALID=y +CONFIG_BAT3=y +CONFIG_BAT3_NAME="STACK_IN_DCACHE" +CONFIG_BAT3_BASE=0xE6000000 +CONFIG_BAT3_ACCESS_RW=y +CONFIG_BAT3_USER_MODE_VALID=y +CONFIG_BAT3_SUPERVISOR_MODE_VALID=y CONFIG_CMD_IOLOOP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/strider_con_dp_defconfig b/configs/strider_con_dp_defconfig index cff81f41f5..514db1c213 100644 --- a/configs/strider_con_dp_defconfig +++ b/configs/strider_con_dp_defconfig @@ -9,6 +9,42 @@ CONFIG_SYSTEM_PLL_FACTOR_4_1=y CONFIG_CORE_PLL_RATIO_3_1=y CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_TSEC2_MODE_RGMII=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="DDR" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_128_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT1=y +CONFIG_BAT1_NAME="IMMRBAR" +CONFIG_BAT1_BASE=0xE0000000 +CONFIG_BAT1_LENGTH_8_MBYTES=y +CONFIG_BAT1_ACCESS_RW=y +CONFIG_BAT1_ICACHE_INHIBITED=y +CONFIG_BAT1_ICACHE_GUARDED=y +CONFIG_BAT1_DCACHE_INHIBITED=y +CONFIG_BAT1_DCACHE_GUARDED=y +CONFIG_BAT1_USER_MODE_VALID=y +CONFIG_BAT1_SUPERVISOR_MODE_VALID=y +CONFIG_BAT2=y +CONFIG_BAT2_NAME="FLASH" +CONFIG_BAT2_BASE=0xFE000000 +CONFIG_BAT2_LENGTH_8_MBYTES=y +CONFIG_BAT2_ACCESS_RW=y +CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT2_DCACHE_INHIBITED=y +CONFIG_BAT2_DCACHE_GUARDED=y +CONFIG_BAT2_USER_MODE_VALID=y +CONFIG_BAT2_SUPERVISOR_MODE_VALID=y +CONFIG_BAT3=y +CONFIG_BAT3_NAME="STACK_IN_DCACHE" +CONFIG_BAT3_BASE=0xE6000000 +CONFIG_BAT3_ACCESS_RW=y +CONFIG_BAT3_USER_MODE_VALID=y +CONFIG_BAT3_SUPERVISOR_MODE_VALID=y CONFIG_CMD_IOLOOP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/strider_cpu_defconfig b/configs/strider_cpu_defconfig index f72bec439b..a998585f3a 100644 --- a/configs/strider_cpu_defconfig +++ b/configs/strider_cpu_defconfig @@ -9,6 +9,42 @@ CONFIG_SYSTEM_PLL_FACTOR_4_1=y CONFIG_CORE_PLL_RATIO_3_1=y CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_TSEC2_MODE_RGMII=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="DDR" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_128_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT1=y +CONFIG_BAT1_NAME="IMMRBAR" +CONFIG_BAT1_BASE=0xE0000000 +CONFIG_BAT1_LENGTH_8_MBYTES=y +CONFIG_BAT1_ACCESS_RW=y +CONFIG_BAT1_ICACHE_INHIBITED=y +CONFIG_BAT1_ICACHE_GUARDED=y +CONFIG_BAT1_DCACHE_INHIBITED=y +CONFIG_BAT1_DCACHE_GUARDED=y +CONFIG_BAT1_USER_MODE_VALID=y +CONFIG_BAT1_SUPERVISOR_MODE_VALID=y +CONFIG_BAT2=y +CONFIG_BAT2_NAME="FLASH" +CONFIG_BAT2_BASE=0xFE000000 +CONFIG_BAT2_LENGTH_8_MBYTES=y +CONFIG_BAT2_ACCESS_RW=y +CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT2_DCACHE_INHIBITED=y +CONFIG_BAT2_DCACHE_GUARDED=y +CONFIG_BAT2_USER_MODE_VALID=y +CONFIG_BAT2_SUPERVISOR_MODE_VALID=y +CONFIG_BAT3=y +CONFIG_BAT3_NAME="STACK_IN_DCACHE" +CONFIG_BAT3_BASE=0xE6000000 +CONFIG_BAT3_ACCESS_RW=y +CONFIG_BAT3_USER_MODE_VALID=y +CONFIG_BAT3_SUPERVISOR_MODE_VALID=y CONFIG_CMD_IOLOOP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/strider_cpu_dp_defconfig b/configs/strider_cpu_dp_defconfig index 0e43049663..48579c7563 100644 --- a/configs/strider_cpu_dp_defconfig +++ b/configs/strider_cpu_dp_defconfig @@ -9,6 +9,42 @@ CONFIG_SYSTEM_PLL_FACTOR_4_1=y CONFIG_CORE_PLL_RATIO_3_1=y CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_TSEC2_MODE_RGMII=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="DDR" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_128_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT1=y +CONFIG_BAT1_NAME="IMMRBAR" +CONFIG_BAT1_BASE=0xE0000000 +CONFIG_BAT1_LENGTH_8_MBYTES=y +CONFIG_BAT1_ACCESS_RW=y +CONFIG_BAT1_ICACHE_INHIBITED=y +CONFIG_BAT1_ICACHE_GUARDED=y +CONFIG_BAT1_DCACHE_INHIBITED=y +CONFIG_BAT1_DCACHE_GUARDED=y +CONFIG_BAT1_USER_MODE_VALID=y +CONFIG_BAT1_SUPERVISOR_MODE_VALID=y +CONFIG_BAT2=y +CONFIG_BAT2_NAME="FLASH" +CONFIG_BAT2_BASE=0xFE000000 +CONFIG_BAT2_LENGTH_8_MBYTES=y +CONFIG_BAT2_ACCESS_RW=y +CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT2_DCACHE_INHIBITED=y +CONFIG_BAT2_DCACHE_GUARDED=y +CONFIG_BAT2_USER_MODE_VALID=y +CONFIG_BAT2_SUPERVISOR_MODE_VALID=y +CONFIG_BAT3=y +CONFIG_BAT3_NAME="STACK_IN_DCACHE" +CONFIG_BAT3_BASE=0xE6000000 +CONFIG_BAT3_ACCESS_RW=y +CONFIG_BAT3_USER_MODE_VALID=y +CONFIG_BAT3_SUPERVISOR_MODE_VALID=y CONFIG_CMD_IOLOOP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/suvd3_defconfig b/configs/suvd3_defconfig index b6f17d2f29..4dd36cac91 100644 --- a/configs/suvd3_defconfig +++ b/configs/suvd3_defconfig @@ -8,6 +8,74 @@ CONFIG_CORE_PLL_RATIO_25_1=y CONFIG_QUICC_MULT_FACTOR_3=y CONFIG_BOOT_MEMORY_SPACE_LOW=y CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="SDRAM" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_256_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_ICACHE_INHIBITED=y +CONFIG_BAT0_ICACHE_GUARDED=y +CONFIG_BAT0_DCACHE_INHIBITED=y +CONFIG_BAT0_DCACHE_GUARDED=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT1=y +CONFIG_BAT1_NAME="IMMR" +CONFIG_BAT1_BASE=0xE0000000 +CONFIG_BAT1_LENGTH_4_MBYTES=y +CONFIG_BAT1_ACCESS_RW=y +CONFIG_BAT1_ICACHE_INHIBITED=y +CONFIG_BAT1_ICACHE_GUARDED=y +CONFIG_BAT1_DCACHE_INHIBITED=y +CONFIG_BAT1_DCACHE_GUARDED=y +CONFIG_BAT1_USER_MODE_VALID=y +CONFIG_BAT1_SUPERVISOR_MODE_VALID=y +CONFIG_BAT2=y +CONFIG_BAT2_NAME="KMBEC_FPGA" +CONFIG_BAT2_BASE=0xE8000000 +CONFIG_BAT2_LENGTH_128_MBYTES=y +CONFIG_BAT2_ACCESS_RW=y +CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT2_DCACHE_INHIBITED=y +CONFIG_BAT2_DCACHE_GUARDED=y +CONFIG_BAT2_USER_MODE_VALID=y +CONFIG_BAT2_SUPERVISOR_MODE_VALID=y +CONFIG_BAT3=y +CONFIG_BAT3_NAME="FLASH" +CONFIG_BAT3_BASE=0xF0000000 +CONFIG_BAT3_LENGTH_256_MBYTES=y +CONFIG_BAT3_ACCESS_RW=y +CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT3_DCACHE_INHIBITED=y +CONFIG_BAT3_DCACHE_GUARDED=y +CONFIG_BAT3_USER_MODE_VALID=y +CONFIG_BAT3_SUPERVISOR_MODE_VALID=y +CONFIG_BAT4=y +CONFIG_BAT4_NAME="STACK_IN_DCACHE" +CONFIG_BAT4_BASE=0xE6000000 +CONFIG_BAT4_ACCESS_RW=y +CONFIG_BAT4_USER_MODE_VALID=y +CONFIG_BAT4_SUPERVISOR_MODE_VALID=y +CONFIG_BAT5=y +CONFIG_BAT5_NAME="APP1" +CONFIG_BAT5_BASE=0xA0000000 +CONFIG_BAT5_LENGTH_256_MBYTES=y +CONFIG_BAT5_ACCESS_RW=y +CONFIG_BAT5_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT5_DCACHE_INHIBITED=y +CONFIG_BAT5_DCACHE_GUARDED=y +CONFIG_BAT5_USER_MODE_VALID=y +CONFIG_BAT5_SUPERVISOR_MODE_VALID=y +CONFIG_BAT6=y +CONFIG_BAT6_NAME="APP2" +CONFIG_BAT6_BASE=0xB0000000 +CONFIG_BAT6_LENGTH_256_MBYTES=y +CONFIG_BAT6_ACCESS_RW=y +CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT6_DCACHE_INHIBITED=y +CONFIG_BAT6_DCACHE_GUARDED=y +CONFIG_BAT6_USER_MODE_VALID=y +CONFIG_BAT6_SUPERVISOR_MODE_VALID=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SUVD3" diff --git a/configs/tuge1_defconfig b/configs/tuge1_defconfig index 445b89d483..7db157bf21 100644 --- a/configs/tuge1_defconfig +++ b/configs/tuge1_defconfig @@ -8,6 +8,64 @@ CONFIG_CORE_PLL_RATIO_25_1=y CONFIG_QUICC_MULT_FACTOR_3=y CONFIG_BOOT_MEMORY_SPACE_LOW=y CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="SDRAM" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_256_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_ICACHE_INHIBITED=y +CONFIG_BAT0_ICACHE_GUARDED=y +CONFIG_BAT0_DCACHE_INHIBITED=y +CONFIG_BAT0_DCACHE_GUARDED=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT1=y +CONFIG_BAT1_NAME="IMMR" +CONFIG_BAT1_BASE=0xE0000000 +CONFIG_BAT1_LENGTH_4_MBYTES=y +CONFIG_BAT1_ACCESS_RW=y +CONFIG_BAT1_ICACHE_INHIBITED=y +CONFIG_BAT1_ICACHE_GUARDED=y +CONFIG_BAT1_DCACHE_INHIBITED=y +CONFIG_BAT1_DCACHE_GUARDED=y +CONFIG_BAT1_USER_MODE_VALID=y +CONFIG_BAT1_SUPERVISOR_MODE_VALID=y +CONFIG_BAT2=y +CONFIG_BAT2_NAME="KMBEC_FPGA" +CONFIG_BAT2_BASE=0xE8000000 +CONFIG_BAT2_LENGTH_128_MBYTES=y +CONFIG_BAT2_ACCESS_RW=y +CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT2_DCACHE_INHIBITED=y +CONFIG_BAT2_DCACHE_GUARDED=y +CONFIG_BAT2_USER_MODE_VALID=y +CONFIG_BAT2_SUPERVISOR_MODE_VALID=y +CONFIG_BAT3=y +CONFIG_BAT3_NAME="FLASH" +CONFIG_BAT3_BASE=0xF0000000 +CONFIG_BAT3_LENGTH_256_MBYTES=y +CONFIG_BAT3_ACCESS_RW=y +CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT3_DCACHE_INHIBITED=y +CONFIG_BAT3_DCACHE_GUARDED=y +CONFIG_BAT3_USER_MODE_VALID=y +CONFIG_BAT3_SUPERVISOR_MODE_VALID=y +CONFIG_BAT4=y +CONFIG_BAT4_NAME="STACK_IN_DCACHE" +CONFIG_BAT4_BASE=0xE6000000 +CONFIG_BAT4_ACCESS_RW=y +CONFIG_BAT4_USER_MODE_VALID=y +CONFIG_BAT4_SUPERVISOR_MODE_VALID=y +CONFIG_BAT5=y +CONFIG_BAT5_NAME="APP1" +CONFIG_BAT5_BASE=0xA0000000 +CONFIG_BAT5_LENGTH_256_MBYTES=y +CONFIG_BAT5_ACCESS_RW=y +CONFIG_BAT5_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT5_DCACHE_INHIBITED=y +CONFIG_BAT5_DCACHE_GUARDED=y +CONFIG_BAT5_USER_MODE_VALID=y +CONFIG_BAT5_SUPERVISOR_MODE_VALID=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_MISC_INIT_R=y diff --git a/configs/tuxx1_defconfig b/configs/tuxx1_defconfig index d7b0a94ada..e0c1366291 100644 --- a/configs/tuxx1_defconfig +++ b/configs/tuxx1_defconfig @@ -8,6 +8,74 @@ CONFIG_CORE_PLL_RATIO_25_1=y CONFIG_QUICC_MULT_FACTOR_3=y CONFIG_BOOT_MEMORY_SPACE_LOW=y CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="SDRAM" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_256_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_ICACHE_INHIBITED=y +CONFIG_BAT0_ICACHE_GUARDED=y +CONFIG_BAT0_DCACHE_INHIBITED=y +CONFIG_BAT0_DCACHE_GUARDED=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT1=y +CONFIG_BAT1_NAME="IMMR" +CONFIG_BAT1_BASE=0xE0000000 +CONFIG_BAT1_LENGTH_4_MBYTES=y +CONFIG_BAT1_ACCESS_RW=y +CONFIG_BAT1_ICACHE_INHIBITED=y +CONFIG_BAT1_ICACHE_GUARDED=y +CONFIG_BAT1_DCACHE_INHIBITED=y +CONFIG_BAT1_DCACHE_GUARDED=y +CONFIG_BAT1_USER_MODE_VALID=y +CONFIG_BAT1_SUPERVISOR_MODE_VALID=y +CONFIG_BAT2=y +CONFIG_BAT2_NAME="KMBEC_FPGA" +CONFIG_BAT2_BASE=0xE8000000 +CONFIG_BAT2_LENGTH_128_MBYTES=y +CONFIG_BAT2_ACCESS_RW=y +CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT2_DCACHE_INHIBITED=y +CONFIG_BAT2_DCACHE_GUARDED=y +CONFIG_BAT2_USER_MODE_VALID=y +CONFIG_BAT2_SUPERVISOR_MODE_VALID=y +CONFIG_BAT3=y +CONFIG_BAT3_NAME="FLASH" +CONFIG_BAT3_BASE=0xF0000000 +CONFIG_BAT3_LENGTH_256_MBYTES=y +CONFIG_BAT3_ACCESS_RW=y +CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT3_DCACHE_INHIBITED=y +CONFIG_BAT3_DCACHE_GUARDED=y +CONFIG_BAT3_USER_MODE_VALID=y +CONFIG_BAT3_SUPERVISOR_MODE_VALID=y +CONFIG_BAT4=y +CONFIG_BAT4_NAME="STACK_IN_DCACHE" +CONFIG_BAT4_BASE=0xE6000000 +CONFIG_BAT4_ACCESS_RW=y +CONFIG_BAT4_USER_MODE_VALID=y +CONFIG_BAT4_SUPERVISOR_MODE_VALID=y +CONFIG_BAT5=y +CONFIG_BAT5_NAME="APP1" +CONFIG_BAT5_BASE=0xA0000000 +CONFIG_BAT5_LENGTH_256_MBYTES=y +CONFIG_BAT5_ACCESS_RW=y +CONFIG_BAT5_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT5_DCACHE_INHIBITED=y +CONFIG_BAT5_DCACHE_GUARDED=y +CONFIG_BAT5_USER_MODE_VALID=y +CONFIG_BAT5_SUPERVISOR_MODE_VALID=y +CONFIG_BAT6=y +CONFIG_BAT6_NAME="APP2" +CONFIG_BAT6_BASE=0xB0000000 +CONFIG_BAT6_LENGTH_256_MBYTES=y +CONFIG_BAT6_ACCESS_RW=y +CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT6_DCACHE_INHIBITED=y +CONFIG_BAT6_DCACHE_GUARDED=y +CONFIG_BAT6_USER_MODE_VALID=y +CONFIG_BAT6_SUPERVISOR_MODE_VALID=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_MISC_INIT_R=y diff --git a/configs/ve8313_defconfig b/configs/ve8313_defconfig index 52a51cc5bb..517c4aa854 100644 --- a/configs/ve8313_defconfig +++ b/configs/ve8313_defconfig @@ -11,6 +11,60 @@ CONFIG_PCI_INT_ARBITER1_ENABLE=y CONFIG_BOOT_MEMORY_SPACE_LOW=y CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_LALE_TIMING_EARLIER=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="SDRAM" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_256_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT1=y +CONFIG_BAT1_NAME="PCI_MEM" +CONFIG_BAT1_BASE=0x80000000 +CONFIG_BAT1_LENGTH_256_MBYTES=y +CONFIG_BAT1_ACCESS_RW=y +CONFIG_BAT1_USER_MODE_VALID=y +CONFIG_BAT1_SUPERVISOR_MODE_VALID=y +CONFIG_BAT2=y +CONFIG_BAT2_NAME="PCI_MMIO" +CONFIG_BAT2_BASE=0x90000000 +CONFIG_BAT2_LENGTH_256_MBYTES=y +CONFIG_BAT2_ACCESS_RW=y +CONFIG_BAT2_ICACHE_INHIBITED=y +CONFIG_BAT2_ICACHE_GUARDED=y +CONFIG_BAT2_DCACHE_INHIBITED=y +CONFIG_BAT2_DCACHE_GUARDED=y +CONFIG_BAT2_USER_MODE_VALID=y +CONFIG_BAT2_SUPERVISOR_MODE_VALID=y +CONFIG_BAT5=y +CONFIG_BAT5_NAME="IMMR_PCIIO_BCSR" +CONFIG_BAT5_BASE=0xE0000000 +CONFIG_BAT5_LENGTH_256_MBYTES=y +CONFIG_BAT5_ACCESS_RW=y +CONFIG_BAT5_ICACHE_INHIBITED=y +CONFIG_BAT5_ICACHE_GUARDED=y +CONFIG_BAT5_DCACHE_INHIBITED=y +CONFIG_BAT5_DCACHE_GUARDED=y +CONFIG_BAT5_USER_MODE_VALID=y +CONFIG_BAT5_SUPERVISOR_MODE_VALID=y +CONFIG_BAT6=y +CONFIG_BAT6_NAME="INITRAM_FLASH" +CONFIG_BAT6_BASE=0xF0000000 +CONFIG_BAT6_LENGTH_256_MBYTES=y +CONFIG_BAT6_ACCESS_RW=y +CONFIG_BAT6_ICACHE_GUARDED=y +CONFIG_BAT6_DCACHE_GUARDED=y +CONFIG_BAT6_USER_MODE_VALID=y +CONFIG_BAT6_SUPERVISOR_MODE_VALID=y +CONFIG_BAT7=y +CONFIG_BAT7_NAME="FPGA_SRAM_NAND" +CONFIG_BAT7_BASE=0x60000000 +CONFIG_BAT7_LENGTH_256_MBYTES=y +CONFIG_BAT7_ACCESS_RW=y +CONFIG_BAT7_ICACHE_GUARDED=y +CONFIG_BAT7_DCACHE_GUARDED=y +CONFIG_BAT7_USER_MODE_VALID=y +CONFIG_BAT7_SUPERVISOR_MODE_VALID=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/vme8349_defconfig b/configs/vme8349_defconfig index 3f1f5c069b..b7cf6a44bc 100644 --- a/configs/vme8349_defconfig +++ b/configs/vme8349_defconfig @@ -14,6 +14,55 @@ CONFIG_BOOT_MEMORY_SPACE_LOW=y CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_TSEC1_MODE_GMII=y CONFIG_TSEC2_MODE_GMII=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="SDRAM" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_256_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT1=y +CONFIG_BAT1_NAME="PCI1_MEM" +CONFIG_BAT1_BASE=0x80000000 +CONFIG_BAT1_LENGTH_256_MBYTES=y +CONFIG_BAT1_ACCESS_RW=y +CONFIG_BAT1_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT1_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT1_USER_MODE_VALID=y +CONFIG_BAT1_SUPERVISOR_MODE_VALID=y +CONFIG_BAT2=y +CONFIG_BAT2_NAME="PCI1_MMIO" +CONFIG_BAT2_BASE=0x90000000 +CONFIG_BAT2_LENGTH_256_MBYTES=y +CONFIG_BAT2_ACCESS_RW=y +CONFIG_BAT2_ICACHE_INHIBITED=y +CONFIG_BAT2_ICACHE_GUARDED=y +CONFIG_BAT2_DCACHE_INHIBITED=y +CONFIG_BAT2_DCACHE_GUARDED=y +CONFIG_BAT2_USER_MODE_VALID=y +CONFIG_BAT2_SUPERVISOR_MODE_VALID=y +CONFIG_BAT5=y +CONFIG_BAT5_NAME="IMMR_PCIIO" +CONFIG_BAT5_BASE=0xE0000000 +CONFIG_BAT5_LENGTH_256_MBYTES=y +CONFIG_BAT5_ACCESS_RW=y +CONFIG_BAT5_ICACHE_INHIBITED=y +CONFIG_BAT5_ICACHE_GUARDED=y +CONFIG_BAT5_DCACHE_INHIBITED=y +CONFIG_BAT5_DCACHE_GUARDED=y +CONFIG_BAT5_USER_MODE_VALID=y +CONFIG_BAT5_SUPERVISOR_MODE_VALID=y +CONFIG_BAT6=y +CONFIG_BAT6_NAME="UNKNOWN" +CONFIG_BAT6_BASE=0xF0000000 +CONFIG_BAT6_LENGTH_256_MBYTES=y +CONFIG_BAT6_ACCESS_RW=y +CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT6_USER_MODE_VALID=y +CONFIG_BAT6_SUPERVISOR_MODE_VALID=y CONFIG_PCI_64BIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h index db283578b9..dc7a8b8aa8 100644 --- a/include/configs/MPC8308RDB.h +++ b/include/configs/MPC8308RDB.h @@ -387,43 +387,6 @@ HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) #define CONFIG_SYS_HID2 HID2_HBE -/* - * MMU Setup - */ - -/* DDR: cache cacheable */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U - -/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \ - BATU_VP) -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U - -/* FLASH: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | \ - BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U - -/* Stack in dcache: cacheable, no memory coherence */ -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) -#define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - /* * Environment Configuration */ diff --git a/include/configs/MPC8313ERDB_NAND.h b/include/configs/MPC8313ERDB_NAND.h index e3bcc63e13..596d39ee5e 100644 --- a/include/configs/MPC8313ERDB_NAND.h +++ b/include/configs/MPC8313ERDB_NAND.h @@ -438,68 +438,6 @@ #define CONFIG_SYS_HID2 HID2_HBE -/* DDR @ 0x00000000 */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) - -/* PCI @ 0x80000000 */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) - -/* PCI2 not supported on 8313 */ -#define CONFIG_SYS_IBAT3L (0) -#define CONFIG_SYS_IBAT3U (0) -#define CONFIG_SYS_IBAT4L (0) -#define CONFIG_SYS_IBAT4U (0) - -/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) - -/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ -#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CONFIG_SYS_IBAT7L (0) -#define CONFIG_SYS_IBAT7U (0) - -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U -#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U -#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U -#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L -#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U -#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L -#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U -#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U - /* * Environment Configuration */ diff --git a/include/configs/MPC8313ERDB_NOR.h b/include/configs/MPC8313ERDB_NOR.h index af2432b12d..9d1ce200ec 100644 --- a/include/configs/MPC8313ERDB_NOR.h +++ b/include/configs/MPC8313ERDB_NOR.h @@ -412,68 +412,6 @@ #define CONFIG_SYS_HID2 HID2_HBE -/* DDR @ 0x00000000 */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) - -/* PCI @ 0x80000000 */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) - -/* PCI2 not supported on 8313 */ -#define CONFIG_SYS_IBAT3L (0) -#define CONFIG_SYS_IBAT3U (0) -#define CONFIG_SYS_IBAT4L (0) -#define CONFIG_SYS_IBAT4U (0) - -/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) - -/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ -#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CONFIG_SYS_IBAT7L (0) -#define CONFIG_SYS_IBAT7U (0) - -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U -#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U -#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U -#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L -#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U -#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L -#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U -#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U - /* * Environment Configuration */ diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index d2f9309cd6..fb568efe2d 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -405,85 +405,6 @@ * MMU Setup */ -/* DDR: cache cacheable */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ - | BATU_BL_128M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U - -/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \ - | BATU_BL_8M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U - -/* FLASH: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE \ - | BATU_BL_32M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U - -/* Stack in dcache: cacheable, no memory coherence */ -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) -#define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR \ - | BATU_BL_128K \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -/* PCI MEM space: cacheable */ -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI_MEM_PHYS \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI_MEM_PHYS \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L -#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U - -/* PCI MMIO space: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI_MMIO_PHYS \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI_MMIO_PHYS \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L -#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U - -#define CONFIG_SYS_IBAT6L 0 -#define CONFIG_SYS_IBAT6U 0 -#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U - -#define CONFIG_SYS_IBAT7L 0 -#define CONFIG_SYS_IBAT7U 0 -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U - #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ #endif diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index 37f173ef74..489e7c3368 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -297,100 +297,6 @@ HID0_ENABLE_INSTRUCTION_CACHE) #define CONFIG_SYS_HID2 HID2_HBE -/* - * MMU Setup - */ - -/* DDR: cache cacheable */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U - -/* IMMRBAR & PCI IO: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \ - | BATU_BL_4M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U - -/* FLASH: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE \ - | BATU_BL_32M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U - -#define CONFIG_SYS_IBAT3L (0) -#define CONFIG_SYS_IBAT3U (0) -#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -/* Stack in dcache: cacheable, no memory coherence */ -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) -#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR \ - | BATU_BL_128K \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L -#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U - -#ifdef CONFIG_PCI -/* PCI MEM space: cacheable */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI1_MEM_PHYS \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI1_MEM_PHYS \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L -#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U -/* PCI MMIO space: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MMIO_PHYS \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MMIO_PHYS \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U -#else -#define CONFIG_SYS_IBAT5L (0) -#define CONFIG_SYS_IBAT5U (0) -#define CONFIG_SYS_IBAT6L (0) -#define CONFIG_SYS_IBAT6U (0) -#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L -#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U -#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U -#endif - -/* Nothing in BAT7 */ -#define CONFIG_SYS_IBAT7L (0) -#define CONFIG_SYS_IBAT7U (0) -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U - #if (CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ #endif diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index d8cadde0e0..15fca456cc 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -360,106 +360,6 @@ HID0_ENABLE_INSTRUCTION_CACHE) #define CONFIG_SYS_HID2 HID2_HBE -/* - * MMU Setup - */ - -/* DDR: cache cacheable */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U - -/* IMMRBAR & PCI IO: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \ - | BATU_BL_4M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U - -/* BCSR: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_BCSR \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_BCSR \ - | BATU_BL_128K \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U - -/* FLASH: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE \ - | BATU_BL_32M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -#define CONFIG_SYS_IBAT4L (0) -#define CONFIG_SYS_IBAT4U (0) -#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L -#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U - -/* Stack in dcache: cacheable, no memory coherence */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) -#define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \ - | BATU_BL_128K \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L -#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U - -#ifdef CONFIG_PCI -/* PCI MEM space: cacheable */ -#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MEM_PHYS \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MEM_PHYS \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U -/* PCI MMIO space: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI1_MMIO_PHYS \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI1_MMIO_PHYS \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U -#else -#define CONFIG_SYS_IBAT6L (0) -#define CONFIG_SYS_IBAT6U (0) -#define CONFIG_SYS_IBAT7L (0) -#define CONFIG_SYS_IBAT7U (0) -#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U -#endif - #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ #endif diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index d70e477f80..e4d90589e9 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -382,103 +382,10 @@ #define CONFIG_SYS_HID2 HID2_HBE -/* DDR @ 0x00000000 */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) - -/* PCI @ 0x80000000 */ #ifdef CONFIG_PCI #define CONFIG_PCI_INDIRECT_BRIDGE -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#else -#define CONFIG_SYS_IBAT1L (0) -#define CONFIG_SYS_IBAT1U (0) -#define CONFIG_SYS_IBAT2L (0) -#define CONFIG_SYS_IBAT2U (0) #endif -#ifdef CONFIG_MPC83XX_PCI2 -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#else -#define CONFIG_SYS_IBAT3L (0) -#define CONFIG_SYS_IBAT3U (0) -#define CONFIG_SYS_IBAT4L (0) -#define CONFIG_SYS_IBAT4U (0) -#endif - -/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) - -/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ -#define CONFIG_SYS_IBAT6L (0xF0000000 \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT6U (0xF0000000 \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) - -#define CONFIG_SYS_IBAT7L (0) -#define CONFIG_SYS_IBAT7U (0) - -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U -#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U -#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U -#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L -#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U -#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L -#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U -#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U - #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ #endif diff --git a/include/configs/MPC8349EMDS_SDRAM.h b/include/configs/MPC8349EMDS_SDRAM.h index 286654066c..a24a2011d2 100644 --- a/include/configs/MPC8349EMDS_SDRAM.h +++ b/include/configs/MPC8349EMDS_SDRAM.h @@ -454,103 +454,10 @@ #define CONFIG_SYS_HID2 HID2_HBE -/* DDR @ 0x00000000 */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) - -/* PCI @ 0x80000000 */ #ifdef CONFIG_PCI #define CONFIG_PCI_INDIRECT_BRIDGE -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#else -#define CONFIG_SYS_IBAT1L (0) -#define CONFIG_SYS_IBAT1U (0) -#define CONFIG_SYS_IBAT2L (0) -#define CONFIG_SYS_IBAT2U (0) #endif -#ifdef CONFIG_MPC83XX_PCI2 -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#else -#define CONFIG_SYS_IBAT3L (0) -#define CONFIG_SYS_IBAT3U (0) -#define CONFIG_SYS_IBAT4L (0) -#define CONFIG_SYS_IBAT4U (0) -#endif - -/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) - -/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ -#define CONFIG_SYS_IBAT6L (0xF0000000 \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT6U (0xF0000000 \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) - -#define CONFIG_SYS_IBAT7L (0) -#define CONFIG_SYS_IBAT7U (0) - -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U -#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U -#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U -#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L -#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U -#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L -#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U -#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U - #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ #endif diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index e7031e94fd..aeee6e0408 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -482,102 +482,6 @@ boards, we say we have two, but don't display a message if we find only one. */ #define CONFIG_SYS_HID2 HID2_HBE -/* DDR */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) - -/* PCI */ -#ifdef CONFIG_PCI -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#else -#define CONFIG_SYS_IBAT1L 0 -#define CONFIG_SYS_IBAT1U 0 -#define CONFIG_SYS_IBAT2L 0 -#define CONFIG_SYS_IBAT2U 0 -#endif - -#ifdef CONFIG_MPC83XX_PCI2 -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#else -#define CONFIG_SYS_IBAT3L 0 -#define CONFIG_SYS_IBAT3U 0 -#define CONFIG_SYS_IBAT4L 0 -#define CONFIG_SYS_IBAT4U 0 -#endif - -/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) - -/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ -#define CONFIG_SYS_IBAT6L (0xF0000000 \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT6U (0xF0000000 \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) - -#define CONFIG_SYS_IBAT7L 0 -#define CONFIG_SYS_IBAT7U 0 - -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U -#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U -#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U -#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L -#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U -#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L -#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U -#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U - #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ #endif diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index 3473ca6102..01a3a77e99 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -420,114 +420,6 @@ extern int board_pci_host_broken(void); HID0_ENABLE_INSTRUCTION_CACHE) #define CONFIG_SYS_HID2 HID2_HBE -/* - * MMU Setup - */ - -/* DDR: cache cacheable */ -#define CONFIG_SYS_SDRAM_LOWER CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_SDRAM_UPPER (CONFIG_SYS_SDRAM_BASE + 0x10000000) - -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_LOWER \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_LOWER \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U - -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_UPPER \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_UPPER \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U - -/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR \ - | BATU_BL_8M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U - -/* BCSR: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_BCSR \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT3U (CONFIG_SYS_BCSR \ - | BATU_BL_128K \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -/* FLASH: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT4U (CONFIG_SYS_FLASH_BASE \ - | BATU_BL_32M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U - -/* Stack in dcache: cacheable, no memory coherence */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) -#define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \ - | BATU_BL_128K \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L -#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U - -#ifdef CONFIG_PCI -/* PCI MEM space: cacheable */ -#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U -/* PCI MMIO space: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U -#else -#define CONFIG_SYS_IBAT6L (0) -#define CONFIG_SYS_IBAT6U (0) -#define CONFIG_SYS_IBAT7L (0) -#define CONFIG_SYS_IBAT7U (0) -#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U -#endif - #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ #endif diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index 9ddd2af0d9..9a4eeb6390 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -435,114 +435,6 @@ | HID0_ENABLE_INSTRUCTION_CACHE) #define CONFIG_SYS_HID2 HID2_HBE -/* - * MMU Setup - */ - -/* DDR: cache cacheable */ -#define CONFIG_SYS_SDRAM_LOWER CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_SDRAM_UPPER (CONFIG_SYS_SDRAM_BASE + 0x10000000) - -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_LOWER \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_LOWER \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U - -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_UPPER \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_UPPER \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U - -/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR \ - | BATU_BL_8M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U - -/* L2 Switch: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_VSC7385_BASE \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT3U (CONFIG_SYS_VSC7385_BASE \ - | BATU_BL_128K \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -/* FLASH: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT4U (CONFIG_SYS_FLASH_BASE \ - | BATU_BL_32M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U - -/* Stack in dcache: cacheable, no memory coherence */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) -#define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \ - | BATU_BL_128K \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L -#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U - -#ifdef CONFIG_PCI -/* PCI MEM space: cacheable */ -#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U -/* PCI MMIO space: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U -#else -#define CONFIG_SYS_IBAT6L (0) -#define CONFIG_SYS_IBAT6U (0) -#define CONFIG_SYS_IBAT7L (0) -#define CONFIG_SYS_IBAT7U (0) -#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U -#endif - #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ #endif diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index c27a04ace9..c5a6203001 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -270,103 +270,11 @@ HID0_ENABLE_INSTRUCTION_CACHE) #define CONFIG_SYS_HID2 HID2_HBE -/* DDR 0 - 512M */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_BASE + 0x10000000 \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_BASE + 0x10000000 \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) - -/* stack in DCACHE @ 512M (no backing mem) */ -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_INIT_RAM_ADDR \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_INIT_RAM_ADDR \ - | BATU_BL_128K \ - | BATU_VS \ - | BATU_VP) - /* PCI */ #ifdef CONFIG_PCI #define CONFIG_PCI_INDIRECT_BRIDGE -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI1_MEM_BASE \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI1_MEM_BASE \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI1_MMIO_BASE \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI1_MMIO_BASE \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI1_IO_BASE \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI1_IO_BASE \ - | BATU_BL_16M \ - | BATU_VS \ - | BATU_VP) -#else -#define CONFIG_SYS_IBAT3L (0) -#define CONFIG_SYS_IBAT3U (0) -#define CONFIG_SYS_IBAT4L (0) -#define CONFIG_SYS_IBAT4U (0) -#define CONFIG_SYS_IBAT5L (0) -#define CONFIG_SYS_IBAT5U (0) #endif -/* IMMRBAR */ -#define CONFIG_SYS_IBAT6L (CONFIG_SYS_IMMR \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT6U (CONFIG_SYS_IMMR \ - | BATU_BL_1M \ - | BATU_VS \ - | BATU_VP) - -/* FLASH */ -#define CONFIG_SYS_IBAT7L (CONFIG_SYS_FLASH_BASE \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT7U (CONFIG_SYS_FLASH_BASE \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) - -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U -#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U -#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U -#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L -#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U -#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L -#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U -#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U - #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ #endif diff --git a/include/configs/caddy2.h b/include/configs/caddy2.h index 007ded0299..f4ee222808 100644 --- a/include/configs/caddy2.h +++ b/include/configs/caddy2.h @@ -302,82 +302,10 @@ #define CONFIG_SYS_GPIO2_DIR 0x78900000 #define CONFIG_SYS_GPIO2_DAT 0x70100000 -/* DDR @ 0x00000000 */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \ - BATU_VS | BATU_VP) - -/* PCI @ 0x80000000 */ #ifdef CONFIG_PCI #define CONFIG_PCI_INDIRECT_BRIDGE -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | \ - BATU_VS | BATU_VP) -#else -#define CONFIG_SYS_IBAT1L (0) -#define CONFIG_SYS_IBAT1U (0) -#define CONFIG_SYS_IBAT2L (0) -#define CONFIG_SYS_IBAT2U (0) #endif -#ifdef CONFIG_MPC83XX_PCI2 -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_RW | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | \ - BATU_VS | BATU_VP) -#else -#define CONFIG_SYS_IBAT3L (0) -#define CONFIG_SYS_IBAT3U (0) -#define CONFIG_SYS_IBAT4L (0) -#define CONFIG_SYS_IBAT4U (0) -#endif - -/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | \ - BATU_VS | BATU_VP) - -#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#if (CONFIG_SYS_DDR_SIZE == 512) -#define CONFIG_SYS_IBAT7L (CONFIG_SYS_SDRAM_BASE+0x10000000 | \ - BATL_PP_RW | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT7U (CONFIG_SYS_SDRAM_BASE+0x10000000 | \ - BATU_BL_256M | BATU_VS | BATU_VP) -#else -#define CONFIG_SYS_IBAT7L (0) -#define CONFIG_SYS_IBAT7U (0) -#endif - -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U -#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U -#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U -#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L -#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U -#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L -#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U -#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U - #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ #endif diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h index c1fe6b45bd..c8fabf9da5 100644 --- a/include/configs/hrcon.h +++ b/include/configs/hrcon.h @@ -482,43 +482,6 @@ void fpga_control_clear(unsigned int bus, int pin); HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) #define CONFIG_SYS_HID2 HID2_HBE -/* - * MMU Setup - */ - -/* DDR: cache cacheable */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U - -/* IMMRBAR, PCI IO and FPGA: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \ - BATU_VP) -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U - -/* FLASH: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | \ - BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U - -/* Stack in dcache: cacheable, no memory coherence */ -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) -#define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - /* * Environment Configuration */ diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h index ac151dccba..120eb0a6b7 100644 --- a/include/configs/ids8313.h +++ b/include/configs/ids8313.h @@ -282,83 +282,6 @@ #define CONFIG_HAS_FSL_DR_USB #define CONFIG_SYS_SCCR_USBDRCM 3 -/* - * BAT's - */ - -/* DDR @ 0x00000000 */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE |\ - BATL_PP_10) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE |\ - BATU_BL_256M |\ - BATU_VS |\ - BATU_VP) -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U - -/* Initial RAM @ 0xFD000000 */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR |\ - BATL_PP_10 |\ - BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR |\ - BATU_BL_256K |\ - BATU_VS |\ - BATU_VP) -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U - -/* FLASH @ 0xFF800000 */ -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE |\ - BATL_PP_10 |\ - BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE |\ - BATU_BL_8M |\ - BATU_VS |\ - BATU_VP) -#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE |\ - BATL_PP_10 |\ - BATL_CACHEINHIBIT |\ - BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U - -#define CONFIG_SYS_IBAT3L (0) -#define CONFIG_SYS_IBAT3U (0) -#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -#define CONFIG_SYS_IBAT4L (0) -#define CONFIG_SYS_IBAT4U (0) -#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L -#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U - -/* IMMRBAR @ 0xF0000000 */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR |\ - BATL_PP_10 |\ - BATL_CACHEINHIBIT |\ - BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR |\ - BATU_BL_128M |\ - BATU_VS |\ - BATU_VP) -#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L -#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U - -/* NAND-Flash @ 0xE1000000, MRAM @ 0xE2000000, CPLD @ 0xE3000000 */ -#define CONFIG_SYS_IBAT6L (0xE0000000 |\ - BATL_PP_10 |\ - BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT6U (0xE0000000 |\ - BATU_BL_256M |\ - BATU_VS |\ - BATU_VP) -#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U - -#define CONFIG_SYS_IBAT7L (0) -#define CONFIG_SYS_IBAT7U (0) -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U - /* * U-Boot environment setup */ diff --git a/include/configs/kmcoge5ne.h b/include/configs/kmcoge5ne.h index a45ea521ac..a4a0fb222b 100644 --- a/include/configs/kmcoge5ne.h +++ b/include/configs/kmcoge5ne.h @@ -234,51 +234,6 @@ HID0_ENABLE_INSTRUCTION_CACHE) #define CONFIG_SYS_HID2 HID2_HBE -/* - * MMU Setup - */ - -/* DDR: cache cacheable */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U - -/* IMMRBAR & PCI IO: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U - -/* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_KMBEC_FPGA_BASE | BATU_BL_128M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U - -/* FLASH: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -/* Stack in dcache: cacheable, no memory coherence */ -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) -#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L -#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U - /* * Internal Definitions */ @@ -434,62 +389,6 @@ OR_GPCM_TRLX |\ OR_GPCM_EAD) -/* - * MMU Setup - */ - -/* PAXE: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT5L (\ - CONFIG_SYS_PAXE_BASE | \ - BATL_PP_10 | \ - BATL_MEMCOHERENCE) - -#define CONFIG_SYS_IBAT5U (\ - CONFIG_SYS_PAXE_BASE | \ - BATU_BL_256M | \ - BATU_VS | \ - BATU_VP) - -#define CONFIG_SYS_DBAT5L (\ - CONFIG_SYS_PAXE_BASE | \ - BATL_PP_10 | \ - BATL_CACHEINHIBIT | \ - BATL_GUARDEDSTORAGE) - -#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U - -/* BFTIC3: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT6L (\ - CONFIG_SYS_BFTIC3_BASE | \ - BATL_PP_10 | \ - BATL_MEMCOHERENCE) - -#define CONFIG_SYS_IBAT6U (\ - CONFIG_SYS_BFTIC3_BASE | \ - BATU_BL_256M | \ - BATU_VS | \ - BATU_VP) - -#define CONFIG_SYS_DBAT6L (\ - CONFIG_SYS_BFTIC3_BASE | \ - BATL_PP_10 | \ - BATL_CACHEINHIBIT | \ - BATL_GUARDEDSTORAGE) - -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U - -/* DDR/LBC SDRAM next 256M: cacheable */ -#define CONFIG_SYS_IBAT7L (\ - CONFIG_SYS_SDRAM_BASE2 |\ - BATL_PP_10 |\ - BATL_CACHEINHIBIT |\ - BATL_GUARDEDSTORAGE) - -#define CONFIG_SYS_IBAT7U (\ - CONFIG_SYS_SDRAM_BASE2 |\ - BATU_BL_256M |\ - BATU_VS |\ - BATU_VP) /* enable POST tests */ #define CONFIG_POST (CONFIG_SYS_POST_MEMORY|CONFIG_SYS_POST_MEM_REGIONS) #define CONFIG_POST_EXTERNAL_WORD_FUNCS /* use own functions, not generic */ @@ -497,7 +396,4 @@ #define CONFIG_TESTPIN_REG gprt3 /* for kmcoge5ne */ #define CONFIG_TESTPIN_MASK 0x20 /* for kmcoge5ne */ -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U - #endif /* CONFIG */ diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h index 2d7b3106dd..f6c7cfce43 100644 --- a/include/configs/kmeter1.h +++ b/include/configs/kmeter1.h @@ -220,51 +220,6 @@ HID0_ENABLE_INSTRUCTION_CACHE) #define CONFIG_SYS_HID2 HID2_HBE -/* - * MMU Setup - */ - -/* DDR: cache cacheable */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U - -/* IMMRBAR & PCI IO: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U - -/* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_KMBEC_FPGA_BASE | BATU_BL_128M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U - -/* FLASH: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -/* Stack in dcache: cacheable, no memory coherence */ -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) -#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L -#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U - /* * Internal Definitions */ @@ -395,36 +350,4 @@ OR_GPCM_TRLX | \ OR_GPCM_EAD) -/* - * MMU Setup - */ - -/* PAXE: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT5L (\ - CONFIG_SYS_PAXE_BASE | \ - BATL_PP_10 | \ - BATL_MEMCOHERENCE) - -#define CONFIG_SYS_IBAT5U (\ - CONFIG_SYS_PAXE_BASE | \ - BATU_BL_256M | \ - BATU_VS | \ - BATU_VP) - -#define CONFIG_SYS_DBAT5L (\ - CONFIG_SYS_PAXE_BASE | \ - BATL_PP_10 | \ - BATL_CACHEINHIBIT | \ - BATL_GUARDEDSTORAGE) - -#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U -#define CONFIG_SYS_IBAT6L (0) -#define CONFIG_SYS_IBAT6U (0) -#define CONFIG_SYS_IBAT7L (0) -#define CONFIG_SYS_IBAT7U (0) -#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U - #endif /* CONFIG */ diff --git a/include/configs/kmopti2.h b/include/configs/kmopti2.h index 2f19b2e9ef..6ac36c0f92 100644 --- a/include/configs/kmopti2.h +++ b/include/configs/kmopti2.h @@ -239,51 +239,6 @@ HID0_ENABLE_INSTRUCTION_CACHE) #define CONFIG_SYS_HID2 HID2_HBE -/* - * MMU Setup - */ - -/* DDR: cache cacheable */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U - -/* IMMRBAR & PCI IO: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U - -/* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_KMBEC_FPGA_BASE | BATU_BL_128M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U - -/* FLASH: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -/* Stack in dcache: cacheable, no memory coherence */ -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) -#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L -#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U - /* * Internal Definitions */ @@ -389,14 +344,6 @@ #define CONFIG_SYS_LBC_LBCR 0x00000000 -/* - * MMU Setup - */ -#define CONFIG_SYS_IBAT7L (0) -#define CONFIG_SYS_IBAT7U (0) -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U - #define CONFIG_SYS_APP1_BASE 0xA0000000 /* PAXG */ #define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ #define CONFIG_SYS_APP2_BASE 0xB0000000 /* PINC3 */ @@ -451,41 +398,5 @@ OR_GPCM_SCY_4 | \ OR_GPCM_TRLX_CLEAR | \ OR_GPCM_EHTR_CLEAR) -/* - * MMU Setup - */ -/* APP1: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_APP1_BASE | \ - BATL_PP_RW | \ - BATL_MEMCOHERENCE) -/* 512M should also include APP2... */ -#define CONFIG_SYS_IBAT5U (CONFIG_SYS_APP1_BASE | \ - BATU_BL_256M | \ - BATU_VS | \ - BATU_VP) -#define CONFIG_SYS_DBAT5L (CONFIG_SYS_APP1_BASE | \ - BATL_PP_RW | \ - BATL_CACHEINHIBIT | \ - BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U - -/* APP2: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT6L (CONFIG_SYS_APP2_BASE | \ - BATL_PP_RW | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT6U (CONFIG_SYS_APP2_BASE | \ - BATU_BL_256M | \ - BATU_VS | \ - BATU_VP) -#define CONFIG_SYS_DBAT6L (CONFIG_SYS_APP2_BASE | \ - BATL_PP_RW | \ - BATL_CACHEINHIBIT | \ - BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U - -#define CONFIG_SYS_IBAT7L (0) -#define CONFIG_SYS_IBAT7U (0) -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U #endif /* __CONFIG_H */ diff --git a/include/configs/kmsupx5.h b/include/configs/kmsupx5.h index ae997a71f6..7ee9a914a4 100644 --- a/include/configs/kmsupx5.h +++ b/include/configs/kmsupx5.h @@ -239,51 +239,6 @@ HID0_ENABLE_INSTRUCTION_CACHE) #define CONFIG_SYS_HID2 HID2_HBE -/* - * MMU Setup - */ - -/* DDR: cache cacheable */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U - -/* IMMRBAR & PCI IO: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U - -/* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_KMBEC_FPGA_BASE | BATU_BL_128M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U - -/* FLASH: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -/* Stack in dcache: cacheable, no memory coherence */ -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) -#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L -#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U - /* * Internal Definitions */ @@ -389,14 +344,6 @@ #define CONFIG_SYS_LBC_LBCR 0x00000000 -/* - * MMU Setup - */ -#define CONFIG_SYS_IBAT7L (0) -#define CONFIG_SYS_IBAT7U (0) -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U - #define CONFIG_SYS_APP1_BASE 0xA0000000 /* PAXG */ #define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ @@ -436,32 +383,4 @@ OR_GPCM_EHTR_CLEAR | \ OR_GPCM_EAD) -/* - * MMU Setup - */ -/* APP1: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_APP1_BASE | \ - BATL_PP_RW | \ - BATL_MEMCOHERENCE) -/* 512M should also include APP2... */ -#define CONFIG_SYS_IBAT5U (CONFIG_SYS_APP1_BASE | \ - BATU_BL_256M | \ - BATU_VS | \ - BATU_VP) -#define CONFIG_SYS_DBAT5L (CONFIG_SYS_APP1_BASE | \ - BATL_PP_RW | \ - BATL_CACHEINHIBIT | \ - BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U - -#define CONFIG_SYS_IBAT6L (0) -#define CONFIG_SYS_IBAT6U (0) -#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U - -#define CONFIG_SYS_IBAT7L (0) -#define CONFIG_SYS_IBAT7U (0) -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U - #endif /* __CONFIG_H */ diff --git a/include/configs/kmtegr1.h b/include/configs/kmtegr1.h index 2e4e2a3b5f..53017faa1c 100644 --- a/include/configs/kmtegr1.h +++ b/include/configs/kmtegr1.h @@ -243,51 +243,6 @@ HID0_ENABLE_INSTRUCTION_CACHE) #define CONFIG_SYS_HID2 HID2_HBE -/* - * MMU Setup - */ - -/* DDR: cache cacheable */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U - -/* IMMRBAR & PCI IO: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U - -/* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_KMBEC_FPGA_BASE | BATU_BL_128M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U - -/* FLASH: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -/* Stack in dcache: cacheable, no memory coherence */ -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) -#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L -#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U - /* * Internal Definitions */ @@ -441,14 +396,6 @@ #define CONFIG_SYS_LBC_LBCR 0x00000000 -/* - * MMU Setup - */ -#define CONFIG_SYS_IBAT7L (0) -#define CONFIG_SYS_IBAT7U (0) -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U - /* must be after the include because KMBEC_FPGA is otherwise undefined */ #define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */ @@ -483,21 +430,6 @@ #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_APP2_BASE #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) -/* - * MMU Setup - */ -#define CONFIG_SYS_IBAT5L (0) -#define CONFIG_SYS_IBAT5U (0) -#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L -#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U -#define CONFIG_SYS_IBAT6L (CONFIG_SYS_APP2_BASE | BATL_PP_RW | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT6U (CONFIG_SYS_APP2_BASE | BATU_BL_256M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT6L (CONFIG_SYS_APP2_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U - /* ethernet port connected to piggy (UEC2) */ #define CONFIG_HAS_ETH1 #define CONFIG_UEC_ETH2 diff --git a/include/configs/kmtepr2.h b/include/configs/kmtepr2.h index f998b95f93..8f2be980a0 100644 --- a/include/configs/kmtepr2.h +++ b/include/configs/kmtepr2.h @@ -239,51 +239,6 @@ HID0_ENABLE_INSTRUCTION_CACHE) #define CONFIG_SYS_HID2 HID2_HBE -/* - * MMU Setup - */ - -/* DDR: cache cacheable */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U - -/* IMMRBAR & PCI IO: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U - -/* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_KMBEC_FPGA_BASE | BATU_BL_128M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U - -/* FLASH: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -/* Stack in dcache: cacheable, no memory coherence */ -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) -#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L -#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U - /* * Internal Definitions */ @@ -389,14 +344,6 @@ #define CONFIG_SYS_LBC_LBCR 0x00000000 -/* - * MMU Setup - */ -#define CONFIG_SYS_IBAT7L (0) -#define CONFIG_SYS_IBAT7U (0) -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U - #define CONFIG_SYS_APP1_BASE 0xA0000000 /* PAXG */ #define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ #define CONFIG_SYS_APP2_BASE 0xB0000000 /* PINC3 */ @@ -452,41 +399,4 @@ OR_GPCM_TRLX_CLEAR | \ OR_GPCM_EHTR_CLEAR) -/* - * MMU Setup - */ -/* APP1: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_APP1_BASE | \ - BATL_PP_RW | \ - BATL_MEMCOHERENCE) -/* 512M should also include APP2... */ -#define CONFIG_SYS_IBAT5U (CONFIG_SYS_APP1_BASE | \ - BATU_BL_256M | \ - BATU_VS | \ - BATU_VP) -#define CONFIG_SYS_DBAT5L (CONFIG_SYS_APP1_BASE | \ - BATL_PP_RW | \ - BATL_CACHEINHIBIT | \ - BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U - -/* APP2: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT6L (CONFIG_SYS_APP2_BASE | \ - BATL_PP_RW | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT6U (CONFIG_SYS_APP2_BASE | \ - BATU_BL_256M | \ - BATU_VS | \ - BATU_VP) -#define CONFIG_SYS_DBAT6L (CONFIG_SYS_APP2_BASE | \ - BATL_PP_RW | \ - BATL_CACHEINHIBIT | \ - BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U - -#define CONFIG_SYS_IBAT7L (0) -#define CONFIG_SYS_IBAT7U (0) -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U - #endif /* __CONFIG_H */ diff --git a/include/configs/kmvect1.h b/include/configs/kmvect1.h index f4da14a616..172a28e850 100644 --- a/include/configs/kmvect1.h +++ b/include/configs/kmvect1.h @@ -235,51 +235,6 @@ HID0_ENABLE_INSTRUCTION_CACHE) #define CONFIG_SYS_HID2 HID2_HBE -/* - * MMU Setup - */ - -/* DDR: cache cacheable */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U - -/* IMMRBAR & PCI IO: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U - -/* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_KMBEC_FPGA_BASE | BATU_BL_128M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U - -/* FLASH: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -/* Stack in dcache: cacheable, no memory coherence */ -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) -#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L -#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U - /* * Internal Definitions */ @@ -433,14 +388,6 @@ #define CONFIG_SYS_LBC_LBCR 0x00000000 -/* - * MMU Setup - */ -#define CONFIG_SYS_IBAT7L (0) -#define CONFIG_SYS_IBAT7U (0) -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U - #define CONFIG_SYS_APP1_BASE 0xA0000000 #define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ #define CONFIG_SYS_APP2_BASE 0xB0000000 @@ -488,25 +435,6 @@ #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_APP2_BASE #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) -/* - * MMU Setup - */ -/* APP1: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_APP1_BASE | BATL_PP_RW | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT5U (CONFIG_SYS_APP1_BASE | BATU_BL_256M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT5L (CONFIG_SYS_APP1_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U -#define CONFIG_SYS_IBAT6L (CONFIG_SYS_APP2_BASE | BATL_PP_RW | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT6U (CONFIG_SYS_APP2_BASE | BATU_BL_256M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT6L (CONFIG_SYS_APP2_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U - /* * QE UEC ethernet configuration */ diff --git a/include/configs/mpc8308_p1m.h b/include/configs/mpc8308_p1m.h index 2822aa3b9d..1bca11bd6e 100644 --- a/include/configs/mpc8308_p1m.h +++ b/include/configs/mpc8308_p1m.h @@ -354,43 +354,6 @@ HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) #define CONFIG_SYS_HID2 HID2_HBE -/* - * MMU Setup - */ - -/* DDR: cache cacheable */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U - -/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \ - BATU_VP) -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U - -/* FLASH: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | \ - BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U - -/* Stack in dcache: cacheable, no memory coherence */ -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) -#define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - /* * Environment Configuration */ diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index d6f2813e50..8179147bc2 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -383,103 +383,10 @@ #define CONFIG_SYS_HID2 HID2_HBE -/* DDR @ 0x00000000 */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) - -/* PCI @ 0x80000000 */ #ifdef CONFIG_PCI #define CONFIG_PCI_INDIRECT_BRIDGE -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#else -#define CONFIG_SYS_IBAT1L (0) -#define CONFIG_SYS_IBAT1U (0) -#define CONFIG_SYS_IBAT2L (0) -#define CONFIG_SYS_IBAT2U (0) #endif -#ifdef CONFIG_MPC83XX_PCI2 -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#else -#define CONFIG_SYS_IBAT3L (0) -#define CONFIG_SYS_IBAT3U (0) -#define CONFIG_SYS_IBAT4L (0) -#define CONFIG_SYS_IBAT4U (0) -#endif - -/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) - -/* LBC SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ -#define CONFIG_SYS_IBAT6L (CONFIG_SYS_LBC_SDRAM_BASE \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT6U (CONFIG_SYS_LBC_SDRAM_BASE \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) - -#define CONFIG_SYS_IBAT7L (0) -#define CONFIG_SYS_IBAT7U (0) - -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U -#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U -#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U -#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L -#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U -#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L -#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U -#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U - #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ #endif diff --git a/include/configs/strider.h b/include/configs/strider.h index ef33eaef9b..a716096bed 100644 --- a/include/configs/strider.h +++ b/include/configs/strider.h @@ -514,43 +514,6 @@ void fpga_control_clear(unsigned int bus, int pin); HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) #define CONFIG_SYS_HID2 HID2_HBE -/* - * MMU Setup - */ - -/* DDR: cache cacheable */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U - -/* IMMRBAR, PCI IO and FPGA: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \ - BATU_VP) -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U - -/* FLASH: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | \ - BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U - -/* Stack in dcache: cacheable, no memory coherence */ -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) -#define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - /* * Environment Configuration */ diff --git a/include/configs/suvd3.h b/include/configs/suvd3.h index 4cc9f13d37..6a4006ef6a 100644 --- a/include/configs/suvd3.h +++ b/include/configs/suvd3.h @@ -236,51 +236,6 @@ HID0_ENABLE_INSTRUCTION_CACHE) #define CONFIG_SYS_HID2 HID2_HBE -/* - * MMU Setup - */ - -/* DDR: cache cacheable */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U - -/* IMMRBAR & PCI IO: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U - -/* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_KMBEC_FPGA_BASE | BATU_BL_128M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U - -/* FLASH: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -/* Stack in dcache: cacheable, no memory coherence */ -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) -#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L -#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U - /* * Internal Definitions */ @@ -386,14 +341,6 @@ #define CONFIG_SYS_LBC_LBCR 0x00000000 -/* - * MMU Setup - */ -#define CONFIG_SYS_IBAT7L (0) -#define CONFIG_SYS_IBAT7U (0) -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U - #define CONFIG_SYS_APP1_BASE 0xA0000000 #define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ #define CONFIG_SYS_APP2_BASE 0xB0000000 @@ -441,23 +388,4 @@ #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_APP2_BASE #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) -/* - * MMU Setup - */ -/* APP1: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_APP1_BASE | BATL_PP_RW | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT5U (CONFIG_SYS_APP1_BASE | BATU_BL_256M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT5L (CONFIG_SYS_APP1_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U -#define CONFIG_SYS_IBAT6L (CONFIG_SYS_APP2_BASE | BATL_PP_RW | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT6U (CONFIG_SYS_APP2_BASE | BATU_BL_256M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT6L (CONFIG_SYS_APP2_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U - #endif /* __CONFIG_H */ diff --git a/include/configs/tuge1.h b/include/configs/tuge1.h index 8d254689cf..5bb74fd9ae 100644 --- a/include/configs/tuge1.h +++ b/include/configs/tuge1.h @@ -239,51 +239,6 @@ HID0_ENABLE_INSTRUCTION_CACHE) #define CONFIG_SYS_HID2 HID2_HBE -/* - * MMU Setup - */ - -/* DDR: cache cacheable */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U - -/* IMMRBAR & PCI IO: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U - -/* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_KMBEC_FPGA_BASE | BATU_BL_128M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U - -/* FLASH: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -/* Stack in dcache: cacheable, no memory coherence */ -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) -#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L -#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U - /* * Internal Definitions */ @@ -389,14 +344,6 @@ #define CONFIG_SYS_LBC_LBCR 0x00000000 -/* - * MMU Setup - */ -#define CONFIG_SYS_IBAT7L (0) -#define CONFIG_SYS_IBAT7U (0) -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U - #define CONFIG_SYS_APP1_BASE 0xA0000000 /* PAXG */ #define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ @@ -436,32 +383,4 @@ OR_GPCM_EHTR_CLEAR | \ OR_GPCM_EAD) -/* - * MMU Setup - */ -/* APP1: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_APP1_BASE | \ - BATL_PP_RW | \ - BATL_MEMCOHERENCE) -/* 512M should also include APP2... */ -#define CONFIG_SYS_IBAT5U (CONFIG_SYS_APP1_BASE | \ - BATU_BL_256M | \ - BATU_VS | \ - BATU_VP) -#define CONFIG_SYS_DBAT5L (CONFIG_SYS_APP1_BASE | \ - BATL_PP_RW | \ - BATL_CACHEINHIBIT | \ - BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U - -#define CONFIG_SYS_IBAT6L (0) -#define CONFIG_SYS_IBAT6U (0) -#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U - -#define CONFIG_SYS_IBAT7L (0) -#define CONFIG_SYS_IBAT7U (0) -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U - #endif /* __CONFIG_H */ diff --git a/include/configs/tuxx1.h b/include/configs/tuxx1.h index 63fbf1b45c..49f77efa74 100644 --- a/include/configs/tuxx1.h +++ b/include/configs/tuxx1.h @@ -239,51 +239,6 @@ HID0_ENABLE_INSTRUCTION_CACHE) #define CONFIG_SYS_HID2 HID2_HBE -/* - * MMU Setup - */ - -/* DDR: cache cacheable */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U - -/* IMMRBAR & PCI IO: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U - -/* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_KMBEC_FPGA_BASE | BATU_BL_128M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U - -/* FLASH: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -/* Stack in dcache: cacheable, no memory coherence */ -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) -#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L -#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U - /* * Internal Definitions */ @@ -389,14 +344,6 @@ #define CONFIG_SYS_LBC_LBCR 0x00000000 -/* - * MMU Setup - */ -#define CONFIG_SYS_IBAT7L (0) -#define CONFIG_SYS_IBAT7U (0) -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U - #define CONFIG_SYS_APP1_BASE 0xA0000000 /* PAXG */ #define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ #define CONFIG_SYS_APP2_BASE 0xB0000000 /* PINC3 */ @@ -462,41 +409,4 @@ 0x0000c000 | \ MxMR_WLFx_2X) -/* - * MMU Setup - */ -/* APP1: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_APP1_BASE | \ - BATL_PP_RW | \ - BATL_MEMCOHERENCE) -/* 512M should also include APP2... */ -#define CONFIG_SYS_IBAT5U (CONFIG_SYS_APP1_BASE | \ - BATU_BL_256M | \ - BATU_VS | \ - BATU_VP) -#define CONFIG_SYS_DBAT5L (CONFIG_SYS_APP1_BASE | \ - BATL_PP_RW | \ - BATL_CACHEINHIBIT | \ - BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U - -/* APP2: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT6L (CONFIG_SYS_APP2_BASE | \ - BATL_PP_RW | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT6U (CONFIG_SYS_APP2_BASE | \ - BATU_BL_256M | \ - BATU_VS | \ - BATU_VP) -#define CONFIG_SYS_DBAT6L (CONFIG_SYS_APP2_BASE | \ - BATL_PP_RW | \ - BATL_CACHEINHIBIT | \ - BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U - -#define CONFIG_SYS_IBAT7L (0) -#define CONFIG_SYS_IBAT7U (0) -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U - #endif /* __CONFIG_H */ diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h index b15cd218f2..84d2c897d7 100644 --- a/include/configs/ve8313.h +++ b/include/configs/ve8313.h @@ -333,76 +333,6 @@ #define CONFIG_SYS_HID2 HID2_HBE -/* DDR @ 0x00000000 */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) - -#if defined(CONFIG_PCI) -/* PCI @ 0x80000000 */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#else -#define CONFIG_SYS_IBAT1L (0) -#define CONFIG_SYS_IBAT1U (0) -#define CONFIG_SYS_IBAT2L (0) -#define CONFIG_SYS_IBAT2U (0) -#endif - -/* PCI2 not supported on 8313 */ -#define CONFIG_SYS_IBAT3L (0) -#define CONFIG_SYS_IBAT3U (0) -#define CONFIG_SYS_IBAT4L (0) -#define CONFIG_SYS_IBAT4U (0) - -/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) - -/* stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ -#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -/* FPGA, SRAM, NAND @ 0x60000000 */ -#define CONFIG_SYS_IBAT7L (0x60000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT7U (0x60000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U -#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U -#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U -#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L -#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U -#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L -#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U -#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U - #define CONFIG_NETDEV eth0 #define CONFIG_HOSTNAME "ve8313" diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h index d73265e064..249783720c 100644 --- a/include/configs/vme8349.h +++ b/include/configs/vme8349.h @@ -302,82 +302,10 @@ #define CONFIG_SYS_GPIO2_DIR 0x78900000 #define CONFIG_SYS_GPIO2_DAT 0x70100000 -/* DDR @ 0x00000000 */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \ - BATU_VS | BATU_VP) - -/* PCI @ 0x80000000 */ #ifdef CONFIG_PCI #define CONFIG_PCI_INDIRECT_BRIDGE -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | \ - BATU_VS | BATU_VP) -#else -#define CONFIG_SYS_IBAT1L (0) -#define CONFIG_SYS_IBAT1U (0) -#define CONFIG_SYS_IBAT2L (0) -#define CONFIG_SYS_IBAT2U (0) #endif -#ifdef CONFIG_MPC83XX_PCI2 -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_RW | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | \ - BATU_VS | BATU_VP) -#else -#define CONFIG_SYS_IBAT3L (0) -#define CONFIG_SYS_IBAT3U (0) -#define CONFIG_SYS_IBAT4L (0) -#define CONFIG_SYS_IBAT4U (0) -#endif - -/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | \ - BATU_VS | BATU_VP) - -#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#if (CONFIG_SYS_DDR_SIZE == 512) -#define CONFIG_SYS_IBAT7L (CONFIG_SYS_SDRAM_BASE+0x10000000 | \ - BATL_PP_RW | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT7U (CONFIG_SYS_SDRAM_BASE+0x10000000 | \ - BATU_BL_256M | BATU_VS | BATU_VP) -#else -#define CONFIG_SYS_IBAT7L (0) -#define CONFIG_SYS_IBAT7U (0) -#endif - -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U -#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U -#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U -#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L -#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U -#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L -#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U -#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U - #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ #endif From 9c5df7a2a9f72ee397a67c2f19476566a35d7c18 Mon Sep 17 00:00:00 2001 From: Mario Six Date: Mon, 21 Jan 2019 09:17:58 +0100 Subject: [PATCH 35/86] mpc83xx: Migrate LBLAW_* to Kconfig The LBLAW_* values determine the window configuration of the memory controller. Hence, they must be known at compile time, and cannot be implemented in the DT mechanism. Configuration of this crucial variable should still be somewhat comfortable. Hence, make its fields configurable in Kconfig, and assemble the final value from these. Signed-off-by: Mario Six --- arch/powerpc/cpu/mpc83xx/Kconfig | 1 + arch/powerpc/cpu/mpc83xx/cpu_init.c | 2 + arch/powerpc/cpu/mpc83xx/lblaw/Kconfig | 519 +++++++++++++++++++++++++ arch/powerpc/cpu/mpc83xx/lblaw/lblaw.h | 55 +++ arch/powerpc/cpu/mpc83xx/spl_minimal.c | 2 + configs/MPC8308RDB_defconfig | 12 + configs/MPC8313ERDB_33_defconfig | 16 + configs/MPC8313ERDB_66_defconfig | 16 + configs/MPC8313ERDB_NAND_33_defconfig | 17 + configs/MPC8313ERDB_NAND_66_defconfig | 17 + configs/MPC8315ERDB_defconfig | 8 + configs/MPC8323ERDB_defconfig | 4 + configs/MPC832XEMDS_ATM_defconfig | 12 + configs/MPC832XEMDS_HOST_33_defconfig | 12 + configs/MPC832XEMDS_HOST_66_defconfig | 12 + configs/MPC832XEMDS_SLAVE_defconfig | 12 + configs/MPC832XEMDS_defconfig | 12 + configs/MPC8349EMDS_PCI64_defconfig | 8 + configs/MPC8349EMDS_SDRAM_defconfig | 12 + configs/MPC8349EMDS_SLAVE_defconfig | 8 + configs/MPC8349EMDS_defconfig | 8 + configs/MPC8349ITXGP_defconfig | 12 + configs/MPC8349ITX_LOWBOOT_defconfig | 12 + configs/MPC8349ITX_defconfig | 12 + configs/MPC837XEMDS_HOST_defconfig | 12 + configs/MPC837XEMDS_SLAVE_defconfig | 12 + configs/MPC837XEMDS_defconfig | 12 + configs/MPC837XERDB_SLAVE_defconfig | 12 + configs/MPC837XERDB_defconfig | 12 + configs/TQM834x_defconfig | 10 + configs/caddy2_defconfig | 8 + configs/hrcon_defconfig | 8 + configs/hrcon_dh_defconfig | 8 + configs/ids8313_defconfig | 17 + configs/kmcoge5ne_defconfig | 12 + configs/kmeter1_defconfig | 12 + configs/kmopti2_defconfig | 16 + configs/kmsupx5_defconfig | 12 + configs/kmtegr1_defconfig | 12 + configs/kmtepr2_defconfig | 16 + configs/kmvect1_defconfig | 16 + configs/mpc8308_p1m_defconfig | 12 + configs/sbc8349_PCI_33_defconfig | 4 + configs/sbc8349_PCI_66_defconfig | 4 + configs/sbc8349_defconfig | 4 + configs/strider_con_defconfig | 8 + configs/strider_con_dp_defconfig | 8 + configs/strider_cpu_defconfig | 8 + configs/strider_cpu_dp_defconfig | 8 + configs/suvd3_defconfig | 16 + configs/tuge1_defconfig | 12 + configs/tuxx1_defconfig | 16 + configs/ve8313_defconfig | 9 + configs/vme8349_defconfig | 8 + include/configs/MPC8308RDB.h | 10 - include/configs/MPC8313ERDB_NAND.h | 18 - include/configs/MPC8313ERDB_NOR.h | 18 - include/configs/MPC8315ERDB.h | 10 - include/configs/MPC8323ERDB.h | 3 - include/configs/MPC832XEMDS.h | 8 - include/configs/MPC8349EMDS.h | 6 - include/configs/MPC8349EMDS_SDRAM.h | 8 - include/configs/MPC8349ITX.h | 10 - include/configs/MPC837XEMDS.h | 10 - include/configs/MPC837XERDB.h | 12 - include/configs/TQM834x.h | 11 - include/configs/caddy2.h | 4 - include/configs/hrcon.h | 6 - include/configs/ids8313.h | 12 - include/configs/kmcoge5ne.h | 10 - include/configs/kmeter1.h | 10 - include/configs/kmopti2.h | 13 - include/configs/kmsupx5.h | 11 - include/configs/kmtegr1.h | 9 - include/configs/kmtepr2.h | 13 - include/configs/kmvect1.h | 13 - include/configs/mpc8308_p1m.h | 9 - include/configs/sbc8349.h | 7 - include/configs/strider.h | 6 - include/configs/suvd3.h | 13 - include/configs/tuge1.h | 11 - include/configs/tuxx1.h | 16 - include/configs/ve8313.h | 9 - include/configs/vme8349.h | 4 - scripts/config_whitelist.txt | 16 - 85 files changed, 1125 insertions(+), 316 deletions(-) create mode 100644 arch/powerpc/cpu/mpc83xx/lblaw/Kconfig create mode 100644 arch/powerpc/cpu/mpc83xx/lblaw/lblaw.h diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index f7f625aea1..8c84196b97 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -284,6 +284,7 @@ config ARCH_MPC837X source "arch/powerpc/cpu/mpc83xx/hrcw/Kconfig" source "arch/powerpc/cpu/mpc83xx/bats/Kconfig" +source "arch/powerpc/cpu/mpc83xx/lblaw/Kconfig" menu "Legacy options" diff --git a/arch/powerpc/cpu/mpc83xx/cpu_init.c b/arch/powerpc/cpu/mpc83xx/cpu_init.c index 7c378671fe..91451e7b30 100644 --- a/arch/powerpc/cpu/mpc83xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc83xx/cpu_init.c @@ -12,6 +12,8 @@ #include #endif +#include "lblaw/lblaw.h" + DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_QE diff --git a/arch/powerpc/cpu/mpc83xx/lblaw/Kconfig b/arch/powerpc/cpu/mpc83xx/lblaw/Kconfig new file mode 100644 index 0000000000..b20f68b77a --- /dev/null +++ b/arch/powerpc/cpu/mpc83xx/lblaw/Kconfig @@ -0,0 +1,519 @@ +menu "LBLAW setup" + +choice + prompt "NAND LAWBAR for NAND SPL" + +config NAND_LBLAWBAR_PRELIM_NONE + bool "None" + +config NAND_LBLAWBAR_PRELIM_0 + bool "0" + depends on LBLAW0 + +config NAND_LBLAWBAR_PRELIM_1 + bool "1" + depends on LBLAW1 + +config NAND_LBLAWBAR_PRELIM_2 + bool "2" + depends on LBLAW2 + +config NAND_LBLAWBAR_PRELIM_3 + bool "3" + depends on LBLAW3 + +endchoice + +menuconfig LBLAW0 + bool "LBLAW0" + +if LBLAW0 + +config LBLAW0_ENABLE + bool "Window enable" + default "y" + +if !LBLAW0_ENABLE + +config LBLAW0_BASE + hex + default 0x0 + +endif + +if LBLAW0_ENABLE + +config LBLAW0_NAME + string "Identifier" + +config LBLAW0_BASE + hex "Window base" + +choice + prompt "Window size" + +config LBLAW0_LENGTH_4_KBYTES + bool "4 kb" + +config LBLAW0_LENGTH_8_KBYTES + bool "8 kb" + +config LBLAW0_LENGTH_16_KBYTES + bool "16 kb" + +config LBLAW0_LENGTH_32_KBYTES + bool "32 kb" + +config LBLAW0_LENGTH_64_KBYTES + bool "64 kb" + +config LBLAW0_LENGTH_128_KBYTES + bool "128 kb" + +config LBLAW0_LENGTH_256_KBYTES + bool "256 kb" + +config LBLAW0_LENGTH_512_KBYTES + bool "512 kb" + +config LBLAW0_LENGTH_1_MBYTES + bool "1 mb" + +config LBLAW0_LENGTH_2_MBYTES + bool "2 mb" + +config LBLAW0_LENGTH_4_MBYTES + bool "4 mb" + +config LBLAW0_LENGTH_8_MBYTES + bool "8 mb" + +config LBLAW0_LENGTH_16_MBYTES + bool "16 mb" + +config LBLAW0_LENGTH_32_MBYTES + bool "32 mb" + +config LBLAW0_LENGTH_64_MBYTES + bool "64 mb" + +config LBLAW0_LENGTH_128_MBYTES + bool "128 mb" + +config LBLAW0_LENGTH_256_MBYTES + bool "256 mb" + +config LBLAW0_LENGTH_512_MBYTES + bool "512 mb" + +config LBLAW0_LENGTH_1_GBYTES + bool "1 gb" + +config LBLAW0_LENGTH_2_GBYTES + bool "2 gb" + +endchoice + +endif # LBLAW0_ENABLE + +endif # LBLAW0 + +config LBLAW0_ENABLE_BIT + hex + default 0x0 if !LBLAW0_ENABLE + default 0x80000000 if LBLAW0_ENABLE + +config LBLAW0_LENGTH + hex + default 0x0 if !LBLAW0_ENABLE + default 0x0000000B if LBLAW0_LENGTH_4_KBYTES + default 0x0000000C if LBLAW0_LENGTH_8_KBYTES + default 0x0000000D if LBLAW0_LENGTH_16_KBYTES + default 0x0000000E if LBLAW0_LENGTH_32_KBYTES + default 0x0000000F if LBLAW0_LENGTH_64_KBYTES + default 0x00000010 if LBLAW0_LENGTH_128_KBYTES + default 0x00000011 if LBLAW0_LENGTH_256_KBYTES + default 0x00000012 if LBLAW0_LENGTH_512_KBYTES + default 0x00000013 if LBLAW0_LENGTH_1_MBYTES + default 0x00000014 if LBLAW0_LENGTH_2_MBYTES + default 0x00000015 if LBLAW0_LENGTH_4_MBYTES + default 0x00000016 if LBLAW0_LENGTH_8_MBYTES + default 0x00000017 if LBLAW0_LENGTH_16_MBYTES + default 0x00000018 if LBLAW0_LENGTH_32_MBYTES + default 0x00000019 if LBLAW0_LENGTH_64_MBYTES + default 0x0000001A if LBLAW0_LENGTH_128_MBYTES + default 0x0000001B if LBLAW0_LENGTH_256_MBYTES + default 0x0000001C if LBLAW0_LENGTH_512_MBYTES + default 0x0000001D if LBLAW0_LENGTH_1_GBYTES + default 0x0000001E if LBLAW0_LENGTH_2_GBYTES + +menuconfig LBLAW1 + bool "LBLAW1" + +if LBLAW1 + +config LBLAW1_ENABLE + bool "Window enable" + default "y" + +if !LBLAW1_ENABLE + +config LBLAW1_BASE + hex + default 0x0 + +endif + +if LBLAW1_ENABLE + +config LBLAW1_NAME + string "Identifier" + +config LBLAW1_BASE + hex "Window base" + +choice + prompt "Window size" + +config LBLAW1_LENGTH_4_KBYTES + bool "4 kb" + +config LBLAW1_LENGTH_8_KBYTES + bool "8 kb" + +config LBLAW1_LENGTH_16_KBYTES + bool "16 kb" + +config LBLAW1_LENGTH_32_KBYTES + bool "32 kb" + +config LBLAW1_LENGTH_64_KBYTES + bool "64 kb" + +config LBLAW1_LENGTH_128_KBYTES + bool "128 kb" + +config LBLAW1_LENGTH_256_KBYTES + bool "256 kb" + +config LBLAW1_LENGTH_512_KBYTES + bool "512 kb" + +config LBLAW1_LENGTH_1_MBYTES + bool "1 mb" + +config LBLAW1_LENGTH_2_MBYTES + bool "2 mb" + +config LBLAW1_LENGTH_4_MBYTES + bool "4 mb" + +config LBLAW1_LENGTH_8_MBYTES + bool "8 mb" + +config LBLAW1_LENGTH_16_MBYTES + bool "16 mb" + +config LBLAW1_LENGTH_32_MBYTES + bool "32 mb" + +config LBLAW1_LENGTH_64_MBYTES + bool "64 mb" + +config LBLAW1_LENGTH_128_MBYTES + bool "128 mb" + +config LBLAW1_LENGTH_256_MBYTES + bool "256 mb" + +config LBLAW1_LENGTH_512_MBYTES + bool "512 mb" + +config LBLAW1_LENGTH_1_GBYTES + bool "1 gb" + +config LBLAW1_LENGTH_2_GBYTES + bool "2 gb" + +endchoice + +endif # LBLAW1_ENABLE + +endif # LBLAW1 + +config LBLAW1_ENABLE_BIT + hex + default 0x0 if !LBLAW1_ENABLE + default 0x80000000 if LBLAW1_ENABLE + +config LBLAW1_LENGTH + hex + default 0x0 if !LBLAW1_ENABLE + default 0x0000000B if LBLAW1_LENGTH_4_KBYTES + default 0x0000000C if LBLAW1_LENGTH_8_KBYTES + default 0x0000000D if LBLAW1_LENGTH_16_KBYTES + default 0x0000000E if LBLAW1_LENGTH_32_KBYTES + default 0x0000000F if LBLAW1_LENGTH_64_KBYTES + default 0x00000010 if LBLAW1_LENGTH_128_KBYTES + default 0x00000011 if LBLAW1_LENGTH_256_KBYTES + default 0x00000012 if LBLAW1_LENGTH_512_KBYTES + default 0x00000013 if LBLAW1_LENGTH_1_MBYTES + default 0x00000014 if LBLAW1_LENGTH_2_MBYTES + default 0x00000015 if LBLAW1_LENGTH_4_MBYTES + default 0x00000016 if LBLAW1_LENGTH_8_MBYTES + default 0x00000017 if LBLAW1_LENGTH_16_MBYTES + default 0x00000018 if LBLAW1_LENGTH_32_MBYTES + default 0x00000019 if LBLAW1_LENGTH_64_MBYTES + default 0x0000001A if LBLAW1_LENGTH_128_MBYTES + default 0x0000001B if LBLAW1_LENGTH_256_MBYTES + default 0x0000001C if LBLAW1_LENGTH_512_MBYTES + default 0x0000001D if LBLAW1_LENGTH_1_GBYTES + default 0x0000001E if LBLAW1_LENGTH_2_GBYTES + +menuconfig LBLAW2 + bool "LBLAW2" + +if LBLAW2 + +config LBLAW2_ENABLE + bool "Window enable" + default "y" + +if !LBLAW2_ENABLE + +config LBLAW2_BASE + hex + default 0x0 + +endif + +if LBLAW2_ENABLE + +config LBLAW2_NAME + string "Identifier" + +config LBLAW2_BASE + hex "Window base" + +choice + prompt "Window size" + +config LBLAW2_LENGTH_4_KBYTES + bool "4 kb" + +config LBLAW2_LENGTH_8_KBYTES + bool "8 kb" + +config LBLAW2_LENGTH_16_KBYTES + bool "16 kb" + +config LBLAW2_LENGTH_32_KBYTES + bool "32 kb" + +config LBLAW2_LENGTH_64_KBYTES + bool "64 kb" + +config LBLAW2_LENGTH_128_KBYTES + bool "128 kb" + +config LBLAW2_LENGTH_256_KBYTES + bool "256 kb" + +config LBLAW2_LENGTH_512_KBYTES + bool "512 kb" + +config LBLAW2_LENGTH_1_MBYTES + bool "1 mb" + +config LBLAW2_LENGTH_2_MBYTES + bool "2 mb" + +config LBLAW2_LENGTH_4_MBYTES + bool "4 mb" + +config LBLAW2_LENGTH_8_MBYTES + bool "8 mb" + +config LBLAW2_LENGTH_16_MBYTES + bool "16 mb" + +config LBLAW2_LENGTH_32_MBYTES + bool "32 mb" + +config LBLAW2_LENGTH_64_MBYTES + bool "64 mb" + +config LBLAW2_LENGTH_128_MBYTES + bool "128 mb" + +config LBLAW2_LENGTH_256_MBYTES + bool "256 mb" + +config LBLAW2_LENGTH_512_MBYTES + bool "512 mb" + +config LBLAW2_LENGTH_1_GBYTES + bool "1 gb" + +config LBLAW2_LENGTH_2_GBYTES + bool "2 gb" + +endchoice + +endif # LBLAW2_ENABLE + +endif # LBLAW2 + +config LBLAW2_ENABLE_BIT + hex + default 0x0 if !LBLAW2_ENABLE + default 0x80000000 if LBLAW2_ENABLE + +config LBLAW2_LENGTH + hex + default 0x0 if !LBLAW2_ENABLE + default 0x0000000B if LBLAW2_LENGTH_4_KBYTES + default 0x0000000C if LBLAW2_LENGTH_8_KBYTES + default 0x0000000D if LBLAW2_LENGTH_16_KBYTES + default 0x0000000E if LBLAW2_LENGTH_32_KBYTES + default 0x0000000F if LBLAW2_LENGTH_64_KBYTES + default 0x00000010 if LBLAW2_LENGTH_128_KBYTES + default 0x00000011 if LBLAW2_LENGTH_256_KBYTES + default 0x00000012 if LBLAW2_LENGTH_512_KBYTES + default 0x00000013 if LBLAW2_LENGTH_1_MBYTES + default 0x00000014 if LBLAW2_LENGTH_2_MBYTES + default 0x00000015 if LBLAW2_LENGTH_4_MBYTES + default 0x00000016 if LBLAW2_LENGTH_8_MBYTES + default 0x00000017 if LBLAW2_LENGTH_16_MBYTES + default 0x00000018 if LBLAW2_LENGTH_32_MBYTES + default 0x00000019 if LBLAW2_LENGTH_64_MBYTES + default 0x0000001A if LBLAW2_LENGTH_128_MBYTES + default 0x0000001B if LBLAW2_LENGTH_256_MBYTES + default 0x0000001C if LBLAW2_LENGTH_512_MBYTES + default 0x0000001D if LBLAW2_LENGTH_1_GBYTES + default 0x0000001E if LBLAW2_LENGTH_2_GBYTES + +menuconfig LBLAW3 + bool "LBLAW3" + +if LBLAW3 + +config LBLAW3_ENABLE + bool "Window enable" + default "y" + +if !LBLAW3_ENABLE + +config LBLAW3_BASE + hex + default 0x0 + +endif + +if LBLAW3_ENABLE + +config LBLAW3_NAME + string "Identifier" + +config LBLAW3_BASE + hex "Window base" + +choice + prompt "Window size" + +config LBLAW3_LENGTH_4_KBYTES + bool "4 kb" + +config LBLAW3_LENGTH_8_KBYTES + bool "8 kb" + +config LBLAW3_LENGTH_16_KBYTES + bool "16 kb" + +config LBLAW3_LENGTH_32_KBYTES + bool "32 kb" + +config LBLAW3_LENGTH_64_KBYTES + bool "64 kb" + +config LBLAW3_LENGTH_128_KBYTES + bool "128 kb" + +config LBLAW3_LENGTH_256_KBYTES + bool "256 kb" + +config LBLAW3_LENGTH_512_KBYTES + bool "512 kb" + +config LBLAW3_LENGTH_1_MBYTES + bool "1 mb" + +config LBLAW3_LENGTH_2_MBYTES + bool "2 mb" + +config LBLAW3_LENGTH_4_MBYTES + bool "4 mb" + +config LBLAW3_LENGTH_8_MBYTES + bool "8 mb" + +config LBLAW3_LENGTH_16_MBYTES + bool "16 mb" + +config LBLAW3_LENGTH_32_MBYTES + bool "32 mb" + +config LBLAW3_LENGTH_64_MBYTES + bool "64 mb" + +config LBLAW3_LENGTH_128_MBYTES + bool "128 mb" + +config LBLAW3_LENGTH_256_MBYTES + bool "256 mb" + +config LBLAW3_LENGTH_512_MBYTES + bool "512 mb" + +config LBLAW3_LENGTH_1_GBYTES + bool "1 gb" + +config LBLAW3_LENGTH_2_GBYTES + bool "2 gb" + +endchoice + +endif # LBLAW3_ENABLE + +endif # LBLAW3 + +config LBLAW3_ENABLE_BIT + hex + default 0x0 if !LBLAW3_ENABLE + default 0x80000000 if LBLAW3_ENABLE + +config LBLAW3_LENGTH + hex + default 0x0 if !LBLAW3_ENABLE + default 0x0000000B if LBLAW3_LENGTH_4_KBYTES + default 0x0000000C if LBLAW3_LENGTH_8_KBYTES + default 0x0000000D if LBLAW3_LENGTH_16_KBYTES + default 0x0000000E if LBLAW3_LENGTH_32_KBYTES + default 0x0000000F if LBLAW3_LENGTH_64_KBYTES + default 0x00000010 if LBLAW3_LENGTH_128_KBYTES + default 0x00000011 if LBLAW3_LENGTH_256_KBYTES + default 0x00000012 if LBLAW3_LENGTH_512_KBYTES + default 0x00000013 if LBLAW3_LENGTH_1_MBYTES + default 0x00000014 if LBLAW3_LENGTH_2_MBYTES + default 0x00000015 if LBLAW3_LENGTH_4_MBYTES + default 0x00000016 if LBLAW3_LENGTH_8_MBYTES + default 0x00000017 if LBLAW3_LENGTH_16_MBYTES + default 0x00000018 if LBLAW3_LENGTH_32_MBYTES + default 0x00000019 if LBLAW3_LENGTH_64_MBYTES + default 0x0000001A if LBLAW3_LENGTH_128_MBYTES + default 0x0000001B if LBLAW3_LENGTH_256_MBYTES + default 0x0000001C if LBLAW3_LENGTH_512_MBYTES + default 0x0000001D if LBLAW3_LENGTH_1_GBYTES + default 0x0000001E if LBLAW3_LENGTH_2_GBYTES + +endmenu diff --git a/arch/powerpc/cpu/mpc83xx/lblaw/lblaw.h b/arch/powerpc/cpu/mpc83xx/lblaw/lblaw.h new file mode 100644 index 0000000000..6972afcc2c --- /dev/null +++ b/arch/powerpc/cpu/mpc83xx/lblaw/lblaw.h @@ -0,0 +1,55 @@ +#if defined(CONFIG_LBLAW0) +#define CONFIG_SYS_LBLAWBAR0_PRELIM \ + CONFIG_LBLAW0_BASE +#define CONFIG_SYS_LBLAWAR0_PRELIM (\ + CONFIG_LBLAW0_ENABLE_BIT |\ + CONFIG_LBLAW0_LENGTH \ +) +#endif + +#if defined(CONFIG_LBLAW1) +#define CONFIG_SYS_LBLAWBAR1_PRELIM \ + CONFIG_LBLAW1_BASE +#define CONFIG_SYS_LBLAWAR1_PRELIM (\ + CONFIG_LBLAW1_ENABLE_BIT |\ + CONFIG_LBLAW1_LENGTH \ +) +#endif + +#if defined(CONFIG_LBLAW2) +#define CONFIG_SYS_LBLAWBAR2_PRELIM \ + CONFIG_LBLAW2_BASE +#define CONFIG_SYS_LBLAWAR2_PRELIM (\ + CONFIG_LBLAW2_ENABLE_BIT |\ + CONFIG_LBLAW2_LENGTH \ +) +#endif + +#if defined(CONFIG_LBLAW3) +#define CONFIG_SYS_LBLAWBAR3_PRELIM \ + CONFIG_LBLAW3_BASE +#define CONFIG_SYS_LBLAWAR3_PRELIM (\ + CONFIG_LBLAW3_ENABLE_BIT |\ + CONFIG_LBLAW3_LENGTH \ +) +#endif + +#ifdef CONFIG_NAND_LBLAWBAR_PRELIM_0 +#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR0_PRELIM +#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR0_PRELIM +#endif + +#ifdef CONFIG_NAND_LBLAWBAR_PRELIM_1 +#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM +#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM +#endif + +#ifdef CONFIG_NAND_LBLAWBAR_PRELIM_2 +#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR2_PRELIM +#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR2_PRELIM +#endif + +#ifdef CONFIG_NAND_LBLAWBAR_PRELIM_3 +#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR3_PRELIM +#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR3_PRELIM +#endif diff --git a/arch/powerpc/cpu/mpc83xx/spl_minimal.c b/arch/powerpc/cpu/mpc83xx/spl_minimal.c index 2d6ba12e2d..75eb65010e 100644 --- a/arch/powerpc/cpu/mpc83xx/spl_minimal.c +++ b/arch/powerpc/cpu/mpc83xx/spl_minimal.c @@ -6,6 +6,8 @@ #include #include +#include "lblaw/lblaw.h" + DECLARE_GLOBAL_DATA_PTR; /* diff --git a/configs/MPC8308RDB_defconfig b/configs/MPC8308RDB_defconfig index 14136f6b67..38c5d8d532 100644 --- a/configs/MPC8308RDB_defconfig +++ b/configs/MPC8308RDB_defconfig @@ -46,6 +46,18 @@ CONFIG_BAT3_BASE=0xE6000000 CONFIG_BAT3_ACCESS_RW=y CONFIG_BAT3_USER_MODE_VALID=y CONFIG_BAT3_SUPERVISOR_MODE_VALID=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xFE000000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_8_MBYTES=y +CONFIG_LBLAW1=y +CONFIG_LBLAW1_BASE=0xE0600000 +CONFIG_LBLAW1_NAME="NAND" +CONFIG_LBLAW1_LENGTH_32_KBYTES=y +CONFIG_LBLAW2=y +CONFIG_LBLAW2_BASE=0xF0000000 +CONFIG_LBLAW2_NAME="VSC7385" +CONFIG_LBLAW2_LENGTH_128_KBYTES=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/MPC8313ERDB_33_defconfig b/configs/MPC8313ERDB_33_defconfig index 8e34ee2c2b..5783165e5d 100644 --- a/configs/MPC8313ERDB_33_defconfig +++ b/configs/MPC8313ERDB_33_defconfig @@ -57,6 +57,22 @@ CONFIG_BAT6_ICACHE_GUARDED=y CONFIG_BAT6_DCACHE_GUARDED=y CONFIG_BAT6_USER_MODE_VALID=y CONFIG_BAT6_SUPERVISOR_MODE_VALID=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xFE000000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_16_MBYTES=y +CONFIG_LBLAW1=y +CONFIG_LBLAW1_BASE=0xE2800000 +CONFIG_LBLAW1_NAME="NAND" +CONFIG_LBLAW1_LENGTH_32_KBYTES=y +CONFIG_LBLAW2=y +CONFIG_LBLAW2_BASE=0xF0000000 +CONFIG_LBLAW2_NAME="VSC7385" +CONFIG_LBLAW2_LENGTH_128_KBYTES=y +CONFIG_LBLAW3=y +CONFIG_LBLAW3_BASE=0xFA000000 +CONFIG_LBLAW3_NAME="BCSR" +CONFIG_LBLAW3_LENGTH_32_KBYTES=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SYS_33MHZ" diff --git a/configs/MPC8313ERDB_66_defconfig b/configs/MPC8313ERDB_66_defconfig index a2f7eb5837..2395b8e397 100644 --- a/configs/MPC8313ERDB_66_defconfig +++ b/configs/MPC8313ERDB_66_defconfig @@ -56,6 +56,22 @@ CONFIG_BAT6_ICACHE_GUARDED=y CONFIG_BAT6_DCACHE_GUARDED=y CONFIG_BAT6_USER_MODE_VALID=y CONFIG_BAT6_SUPERVISOR_MODE_VALID=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xFE000000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_16_MBYTES=y +CONFIG_LBLAW1=y +CONFIG_LBLAW1_BASE=0xE2800000 +CONFIG_LBLAW1_NAME="NAND" +CONFIG_LBLAW1_LENGTH_32_KBYTES=y +CONFIG_LBLAW2=y +CONFIG_LBLAW2_BASE=0xF0000000 +CONFIG_LBLAW2_NAME="VSC7385" +CONFIG_LBLAW2_LENGTH_128_KBYTES=y +CONFIG_LBLAW3=y +CONFIG_LBLAW3_BASE=0xFA000000 +CONFIG_LBLAW3_NAME="BCSR" +CONFIG_LBLAW3_LENGTH_32_KBYTES=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SYS_66MHZ" diff --git a/configs/MPC8313ERDB_NAND_33_defconfig b/configs/MPC8313ERDB_NAND_33_defconfig index 9946bf965e..ce97914934 100644 --- a/configs/MPC8313ERDB_NAND_33_defconfig +++ b/configs/MPC8313ERDB_NAND_33_defconfig @@ -58,6 +58,23 @@ CONFIG_BAT6_ICACHE_GUARDED=y CONFIG_BAT6_DCACHE_GUARDED=y CONFIG_BAT6_USER_MODE_VALID=y CONFIG_BAT6_SUPERVISOR_MODE_VALID=y +CONFIG_NAND_LBLAWBAR_PRELIM_1=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xFE000000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_16_MBYTES=y +CONFIG_LBLAW1=y +CONFIG_LBLAW1_BASE=0xE2800000 +CONFIG_LBLAW1_NAME="NAND" +CONFIG_LBLAW1_LENGTH_32_KBYTES=y +CONFIG_LBLAW2=y +CONFIG_LBLAW2_BASE=0xF0000000 +CONFIG_LBLAW2_NAME="VSC7385" +CONFIG_LBLAW2_LENGTH_128_KBYTES=y +CONFIG_LBLAW3=y +CONFIG_LBLAW3_BASE=0xFA000000 +CONFIG_LBLAW3_NAME="BCSR" +CONFIG_LBLAW3_LENGTH_32_KBYTES=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SYS_33MHZ" diff --git a/configs/MPC8313ERDB_NAND_66_defconfig b/configs/MPC8313ERDB_NAND_66_defconfig index ffa22bfb83..92d33b07db 100644 --- a/configs/MPC8313ERDB_NAND_66_defconfig +++ b/configs/MPC8313ERDB_NAND_66_defconfig @@ -57,6 +57,23 @@ CONFIG_BAT6_ICACHE_GUARDED=y CONFIG_BAT6_DCACHE_GUARDED=y CONFIG_BAT6_USER_MODE_VALID=y CONFIG_BAT6_SUPERVISOR_MODE_VALID=y +CONFIG_NAND_LBLAWBAR_PRELIM_1=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xFE000000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_16_MBYTES=y +CONFIG_LBLAW1=y +CONFIG_LBLAW1_BASE=0xE2800000 +CONFIG_LBLAW1_NAME="NAND" +CONFIG_LBLAW1_LENGTH_32_KBYTES=y +CONFIG_LBLAW2=y +CONFIG_LBLAW2_BASE=0xF0000000 +CONFIG_LBLAW2_NAME="VSC7385" +CONFIG_LBLAW2_LENGTH_128_KBYTES=y +CONFIG_LBLAW3=y +CONFIG_LBLAW3_BASE=0xFA000000 +CONFIG_LBLAW3_NAME="BCSR" +CONFIG_LBLAW3_LENGTH_32_KBYTES=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SYS_66MHZ" diff --git a/configs/MPC8315ERDB_defconfig b/configs/MPC8315ERDB_defconfig index 43daee1f19..b6e43b66aa 100644 --- a/configs/MPC8315ERDB_defconfig +++ b/configs/MPC8315ERDB_defconfig @@ -68,6 +68,14 @@ CONFIG_BAT5_DCACHE_INHIBITED=y CONFIG_BAT5_DCACHE_GUARDED=y CONFIG_BAT5_USER_MODE_VALID=y CONFIG_BAT5_SUPERVISOR_MODE_VALID=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xFE000000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_8_MBYTES=y +CONFIG_LBLAW1=y +CONFIG_LBLAW1_BASE=0xE0600000 +CONFIG_LBLAW1_NAME="NAND" +CONFIG_LBLAW1_LENGTH_32_KBYTES=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC8323ERDB_defconfig b/configs/MPC8323ERDB_defconfig index 9039652d4b..7243cf67f9 100644 --- a/configs/MPC8323ERDB_defconfig +++ b/configs/MPC8323ERDB_defconfig @@ -66,6 +66,10 @@ CONFIG_BAT6_DCACHE_INHIBITED=y CONFIG_BAT6_DCACHE_GUARDED=y CONFIG_BAT6_USER_MODE_VALID=y CONFIG_BAT6_SUPERVISOR_MODE_VALID=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xFE000000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_32_MBYTES=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC832XEMDS_ATM_defconfig b/configs/MPC832XEMDS_ATM_defconfig index aefb01f150..8cbc14022b 100644 --- a/configs/MPC832XEMDS_ATM_defconfig +++ b/configs/MPC832XEMDS_ATM_defconfig @@ -56,6 +56,18 @@ CONFIG_BAT5_BASE=0xE6000000 CONFIG_BAT5_ACCESS_RW=y CONFIG_BAT5_USER_MODE_VALID=y CONFIG_BAT5_SUPERVISOR_MODE_VALID=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xFE000000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_32_MBYTES=y +CONFIG_LBLAW1=y +CONFIG_LBLAW1_BASE=0xF8000000 +CONFIG_LBLAW1_NAME="BCSR" +CONFIG_LBLAW1_LENGTH_32_KBYTES=y +CONFIG_LBLAW3=y +CONFIG_LBLAW3_BASE=0xF8008000 +CONFIG_LBLAW3_NAME="PIB" +CONFIG_LBLAW3_LENGTH_64_KBYTES=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PQ_MDS_PIB=1,PQ_MDS_PIB_ATM=1" diff --git a/configs/MPC832XEMDS_HOST_33_defconfig b/configs/MPC832XEMDS_HOST_33_defconfig index f410f8dac0..487d1d8544 100644 --- a/configs/MPC832XEMDS_HOST_33_defconfig +++ b/configs/MPC832XEMDS_HOST_33_defconfig @@ -76,6 +76,18 @@ CONFIG_BAT7_DCACHE_INHIBITED=y CONFIG_BAT7_DCACHE_GUARDED=y CONFIG_BAT7_USER_MODE_VALID=y CONFIG_BAT7_SUPERVISOR_MODE_VALID=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xFE000000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_32_MBYTES=y +CONFIG_LBLAW1=y +CONFIG_LBLAW1_BASE=0xF8000000 +CONFIG_LBLAW1_NAME="BCSR" +CONFIG_LBLAW1_LENGTH_32_KBYTES=y +CONFIG_LBLAW3=y +CONFIG_LBLAW3_BASE=0xF8008000 +CONFIG_LBLAW3_NAME="PIB" +CONFIG_LBLAW3_LENGTH_64_KBYTES=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PCI_33M,PQ_MDS_PIB=1" diff --git a/configs/MPC832XEMDS_HOST_66_defconfig b/configs/MPC832XEMDS_HOST_66_defconfig index dac8f28a4d..10ea03422c 100644 --- a/configs/MPC832XEMDS_HOST_66_defconfig +++ b/configs/MPC832XEMDS_HOST_66_defconfig @@ -76,6 +76,18 @@ CONFIG_BAT7_DCACHE_INHIBITED=y CONFIG_BAT7_DCACHE_GUARDED=y CONFIG_BAT7_USER_MODE_VALID=y CONFIG_BAT7_SUPERVISOR_MODE_VALID=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xFE000000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_32_MBYTES=y +CONFIG_LBLAW1=y +CONFIG_LBLAW1_BASE=0xF8000000 +CONFIG_LBLAW1_NAME="BCSR" +CONFIG_LBLAW1_LENGTH_32_KBYTES=y +CONFIG_LBLAW3=y +CONFIG_LBLAW3_BASE=0xF8008000 +CONFIG_LBLAW3_NAME="PIB" +CONFIG_LBLAW3_LENGTH_64_KBYTES=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PCI_66M,PQ_MDS_PIB=1" diff --git a/configs/MPC832XEMDS_SLAVE_defconfig b/configs/MPC832XEMDS_SLAVE_defconfig index c1cb69ad93..b1afa2fa47 100644 --- a/configs/MPC832XEMDS_SLAVE_defconfig +++ b/configs/MPC832XEMDS_SLAVE_defconfig @@ -73,6 +73,18 @@ CONFIG_BAT7_DCACHE_INHIBITED=y CONFIG_BAT7_DCACHE_GUARDED=y CONFIG_BAT7_USER_MODE_VALID=y CONFIG_BAT7_SUPERVISOR_MODE_VALID=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xFE000000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_32_MBYTES=y +CONFIG_LBLAW1=y +CONFIG_LBLAW1_BASE=0xF8000000 +CONFIG_LBLAW1_NAME="BCSR" +CONFIG_LBLAW1_LENGTH_32_KBYTES=y +CONFIG_LBLAW3=y +CONFIG_LBLAW3_BASE=0xF8008000 +CONFIG_LBLAW3_NAME="PIB" +CONFIG_LBLAW3_LENGTH_64_KBYTES=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PCISLAVE" diff --git a/configs/MPC832XEMDS_defconfig b/configs/MPC832XEMDS_defconfig index 38e0b7f6de..a9bb8a7713 100644 --- a/configs/MPC832XEMDS_defconfig +++ b/configs/MPC832XEMDS_defconfig @@ -56,6 +56,18 @@ CONFIG_BAT5_BASE=0xE6000000 CONFIG_BAT5_ACCESS_RW=y CONFIG_BAT5_USER_MODE_VALID=y CONFIG_BAT5_SUPERVISOR_MODE_VALID=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xFE000000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_32_MBYTES=y +CONFIG_LBLAW1=y +CONFIG_LBLAW1_BASE=0xF8000000 +CONFIG_LBLAW1_NAME="BCSR" +CONFIG_LBLAW1_LENGTH_32_KBYTES=y +CONFIG_LBLAW3=y +CONFIG_LBLAW3_BASE=0xF8008000 +CONFIG_LBLAW3_NAME="PIB" +CONFIG_LBLAW3_LENGTH_64_KBYTES=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC8349EMDS_PCI64_defconfig b/configs/MPC8349EMDS_PCI64_defconfig index 6daab44b62..28779bbeb7 100644 --- a/configs/MPC8349EMDS_PCI64_defconfig +++ b/configs/MPC8349EMDS_PCI64_defconfig @@ -45,6 +45,14 @@ CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y CONFIG_BAT6_DCACHE_GUARDED=y CONFIG_BAT6_USER_MODE_VALID=y CONFIG_BAT6_SUPERVISOR_MODE_VALID=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xFE000000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_32_MBYTES=y +CONFIG_LBLAW1=y +CONFIG_LBLAW1_BASE=0xE2400000 +CONFIG_LBLAW1_NAME="BCSR" +CONFIG_LBLAW1_LENGTH_32_KBYTES=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC8349EMDS_SDRAM_defconfig b/configs/MPC8349EMDS_SDRAM_defconfig index d3f42f99e0..a157066968 100644 --- a/configs/MPC8349EMDS_SDRAM_defconfig +++ b/configs/MPC8349EMDS_SDRAM_defconfig @@ -45,6 +45,18 @@ CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y CONFIG_BAT6_DCACHE_GUARDED=y CONFIG_BAT6_USER_MODE_VALID=y CONFIG_BAT6_SUPERVISOR_MODE_VALID=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xFE000000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_32_MBYTES=y +CONFIG_LBLAW1=y +CONFIG_LBLAW1_BASE=0xE2400000 +CONFIG_LBLAW1_NAME="BCSR" +CONFIG_LBLAW1_LENGTH_32_KBYTES=y +CONFIG_LBLAW2=y +CONFIG_LBLAW2_BASE=0xF0000000 +CONFIG_LBLAW2_NAME="SDRAM" +CONFIG_LBLAW2_LENGTH_64_MBYTES=y CONFIG_PCI_ONE_PCI1=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/configs/MPC8349EMDS_SLAVE_defconfig b/configs/MPC8349EMDS_SLAVE_defconfig index c264f7b53d..588d9420f1 100644 --- a/configs/MPC8349EMDS_SLAVE_defconfig +++ b/configs/MPC8349EMDS_SLAVE_defconfig @@ -43,6 +43,14 @@ CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y CONFIG_BAT6_DCACHE_GUARDED=y CONFIG_BAT6_USER_MODE_VALID=y CONFIG_BAT6_SUPERVISOR_MODE_VALID=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xFE000000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_32_MBYTES=y +CONFIG_LBLAW1=y +CONFIG_LBLAW1_BASE=0xE2400000 +CONFIG_LBLAW1_NAME="BCSR" +CONFIG_LBLAW1_LENGTH_32_KBYTES=y CONFIG_PCI_ONE_PCI1=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/configs/MPC8349EMDS_defconfig b/configs/MPC8349EMDS_defconfig index 4018d81825..a38edb5293 100644 --- a/configs/MPC8349EMDS_defconfig +++ b/configs/MPC8349EMDS_defconfig @@ -45,6 +45,14 @@ CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y CONFIG_BAT6_DCACHE_GUARDED=y CONFIG_BAT6_USER_MODE_VALID=y CONFIG_BAT6_SUPERVISOR_MODE_VALID=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xFE000000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_32_MBYTES=y +CONFIG_LBLAW1=y +CONFIG_LBLAW1_BASE=0xE2400000 +CONFIG_LBLAW1_NAME="BCSR" +CONFIG_LBLAW1_LENGTH_32_KBYTES=y CONFIG_PCI_ONE_PCI1=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/configs/MPC8349ITXGP_defconfig b/configs/MPC8349ITXGP_defconfig index 0434118419..844b897329 100644 --- a/configs/MPC8349ITXGP_defconfig +++ b/configs/MPC8349ITXGP_defconfig @@ -85,6 +85,18 @@ CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y CONFIG_BAT6_DCACHE_GUARDED=y CONFIG_BAT6_USER_MODE_VALID=y CONFIG_BAT6_SUPERVISOR_MODE_VALID=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xFE000000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_16_MBYTES=y +CONFIG_LBLAW1=y +CONFIG_LBLAW1_BASE=0xF8000000 +CONFIG_LBLAW1_NAME="VSC7385" +CONFIG_LBLAW1_LENGTH_128_KBYTES=y +CONFIG_LBLAW3=y +CONFIG_LBLAW3_BASE=0xF0000000 +CONFIG_LBLAW3_NAME="CF" +CONFIG_LBLAW3_LENGTH_64_KBYTES=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFE000000" diff --git a/configs/MPC8349ITX_LOWBOOT_defconfig b/configs/MPC8349ITX_LOWBOOT_defconfig index de97bb15b2..91ed6686f8 100644 --- a/configs/MPC8349ITX_LOWBOOT_defconfig +++ b/configs/MPC8349ITX_LOWBOOT_defconfig @@ -85,6 +85,18 @@ CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y CONFIG_BAT6_DCACHE_GUARDED=y CONFIG_BAT6_USER_MODE_VALID=y CONFIG_BAT6_SUPERVISOR_MODE_VALID=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xFE000000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_16_MBYTES=y +CONFIG_LBLAW1=y +CONFIG_LBLAW1_BASE=0xF8000000 +CONFIG_LBLAW1_NAME="VSC7385" +CONFIG_LBLAW1_LENGTH_128_KBYTES=y +CONFIG_LBLAW3=y +CONFIG_LBLAW3_BASE=0xF0000000 +CONFIG_LBLAW3_NAME="CF" +CONFIG_LBLAW3_LENGTH_64_KBYTES=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC8349ITX_defconfig b/configs/MPC8349ITX_defconfig index b1e687ceab..cfa31c7230 100644 --- a/configs/MPC8349ITX_defconfig +++ b/configs/MPC8349ITX_defconfig @@ -84,6 +84,18 @@ CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y CONFIG_BAT6_DCACHE_GUARDED=y CONFIG_BAT6_USER_MODE_VALID=y CONFIG_BAT6_SUPERVISOR_MODE_VALID=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xFE000000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_16_MBYTES=y +CONFIG_LBLAW1=y +CONFIG_LBLAW1_BASE=0xF8000000 +CONFIG_LBLAW1_NAME="VSC7385" +CONFIG_LBLAW1_LENGTH_128_KBYTES=y +CONFIG_LBLAW3=y +CONFIG_LBLAW3_BASE=0xF0000000 +CONFIG_LBLAW3_NAME="CF" +CONFIG_LBLAW3_LENGTH_64_KBYTES=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC837XEMDS_HOST_defconfig b/configs/MPC837XEMDS_HOST_defconfig index 86b9f6071a..4cc36a5c7f 100644 --- a/configs/MPC837XEMDS_HOST_defconfig +++ b/configs/MPC837XEMDS_HOST_defconfig @@ -89,6 +89,18 @@ CONFIG_BAT7_DCACHE_INHIBITED=y CONFIG_BAT7_DCACHE_GUARDED=y CONFIG_BAT7_USER_MODE_VALID=y CONFIG_BAT7_SUPERVISOR_MODE_VALID=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xFE000000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_32_MBYTES=y +CONFIG_LBLAW1=y +CONFIG_LBLAW1_BASE=0xF8000000 +CONFIG_LBLAW1_NAME="BCSR" +CONFIG_LBLAW1_LENGTH_32_KBYTES=y +CONFIG_LBLAW3=y +CONFIG_LBLAW3_BASE=0xE0600000 +CONFIG_LBLAW3_NAME="NAND" +CONFIG_LBLAW3_LENGTH_32_KBYTES=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC837XEMDS_SLAVE_defconfig b/configs/MPC837XEMDS_SLAVE_defconfig index 44c23eade5..ba58e49ba2 100644 --- a/configs/MPC837XEMDS_SLAVE_defconfig +++ b/configs/MPC837XEMDS_SLAVE_defconfig @@ -49,6 +49,18 @@ CONFIG_BAT3_DCACHE_INHIBITED=y CONFIG_BAT3_DCACHE_GUARDED=y CONFIG_BAT3_USER_MODE_VALID=y CONFIG_BAT3_SUPERVISOR_MODE_VALID=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xFE000000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_32_MBYTES=y +CONFIG_LBLAW1=y +CONFIG_LBLAW1_BASE=0xF8000000 +CONFIG_LBLAW1_NAME="BCSR" +CONFIG_LBLAW1_LENGTH_32_KBYTES=y +CONFIG_LBLAW3=y +CONFIG_LBLAW3_BASE=0xE0600000 +CONFIG_LBLAW3_NAME="NAND" +CONFIG_LBLAW3_LENGTH_32_KBYTES=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PCISLAVE" diff --git a/configs/MPC837XEMDS_defconfig b/configs/MPC837XEMDS_defconfig index f21cdbd179..b3c1c87824 100644 --- a/configs/MPC837XEMDS_defconfig +++ b/configs/MPC837XEMDS_defconfig @@ -69,6 +69,18 @@ CONFIG_BAT5_BASE=0xE6000000 CONFIG_BAT5_ACCESS_RW=y CONFIG_BAT5_USER_MODE_VALID=y CONFIG_BAT5_SUPERVISOR_MODE_VALID=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xFE000000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_32_MBYTES=y +CONFIG_LBLAW1=y +CONFIG_LBLAW1_BASE=0xF8000000 +CONFIG_LBLAW1_NAME="BCSR" +CONFIG_LBLAW1_LENGTH_32_KBYTES=y +CONFIG_LBLAW3=y +CONFIG_LBLAW3_BASE=0xE0600000 +CONFIG_LBLAW3_NAME="NAND" +CONFIG_LBLAW3_LENGTH_32_KBYTES=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC837XERDB_SLAVE_defconfig b/configs/MPC837XERDB_SLAVE_defconfig index d1455b0e9d..07016936d6 100644 --- a/configs/MPC837XERDB_SLAVE_defconfig +++ b/configs/MPC837XERDB_SLAVE_defconfig @@ -49,6 +49,18 @@ CONFIG_BAT3_DCACHE_INHIBITED=y CONFIG_BAT3_DCACHE_GUARDED=y CONFIG_BAT3_USER_MODE_VALID=y CONFIG_BAT3_SUPERVISOR_MODE_VALID=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xFE000000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_8_MBYTES=y +CONFIG_LBLAW1=y +CONFIG_LBLAW1_BASE=0xE0600000 +CONFIG_LBLAW1_NAME="NAND" +CONFIG_LBLAW1_LENGTH_32_KBYTES=y +CONFIG_LBLAW2=y +CONFIG_LBLAW2_BASE=0xF0000000 +CONFIG_LBLAW2_NAME="VSC7385" +CONFIG_LBLAW2_LENGTH_128_KBYTES=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PCISLAVE,PCIE" diff --git a/configs/MPC837XERDB_defconfig b/configs/MPC837XERDB_defconfig index e6138c06fc..59d591fa05 100644 --- a/configs/MPC837XERDB_defconfig +++ b/configs/MPC837XERDB_defconfig @@ -89,6 +89,18 @@ CONFIG_BAT7_DCACHE_INHIBITED=y CONFIG_BAT7_DCACHE_GUARDED=y CONFIG_BAT7_USER_MODE_VALID=y CONFIG_BAT7_SUPERVISOR_MODE_VALID=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xFE000000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_8_MBYTES=y +CONFIG_LBLAW1=y +CONFIG_LBLAW1_BASE=0xE0600000 +CONFIG_LBLAW1_NAME="NAND" +CONFIG_LBLAW1_LENGTH_32_KBYTES=y +CONFIG_LBLAW2=y +CONFIG_LBLAW2_BASE=0xF0000000 +CONFIG_LBLAW2_NAME="VSC7385" +CONFIG_LBLAW2_LENGTH_128_KBYTES=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PCIE" diff --git a/configs/TQM834x_defconfig b/configs/TQM834x_defconfig index 677f0513a3..fdaded2970 100644 --- a/configs/TQM834x_defconfig +++ b/configs/TQM834x_defconfig @@ -92,6 +92,16 @@ CONFIG_BAT7_DCACHE_INHIBITED=y CONFIG_BAT7_DCACHE_GUARDED=y CONFIG_BAT7_USER_MODE_VALID=y CONFIG_BAT7_SUPERVISOR_MODE_VALID=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0x80000000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_1_GBYTES=y +CONFIG_LBLAW1=y +# CONFIG_LBLAW1_ENABLE is not set +CONFIG_LBLAW2=y +# CONFIG_LBLAW2_ENABLE is not set +CONFIG_LBLAW3=y +# CONFIG_LBLAW3_ENABLE is not set CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/caddy2_defconfig b/configs/caddy2_defconfig index 2665e72573..12721f8db4 100644 --- a/configs/caddy2_defconfig +++ b/configs/caddy2_defconfig @@ -63,6 +63,14 @@ CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y CONFIG_BAT6_USER_MODE_VALID=y CONFIG_BAT6_SUPERVISOR_MODE_VALID=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xFFC00000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_4_MBYTES=y +CONFIG_LBLAW1=y +CONFIG_LBLAW1_BASE=0xF0000000 +CONFIG_LBLAW1_NAME="WINDOW1" +CONFIG_LBLAW1_LENGTH_256_KBYTES=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/hrcon_defconfig b/configs/hrcon_defconfig index deed831c11..f1aa24683c 100644 --- a/configs/hrcon_defconfig +++ b/configs/hrcon_defconfig @@ -46,6 +46,14 @@ CONFIG_BAT3_BASE=0xE6000000 CONFIG_BAT3_ACCESS_RW=y CONFIG_BAT3_USER_MODE_VALID=y CONFIG_BAT3_SUPERVISOR_MODE_VALID=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xFE000000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_8_MBYTES=y +CONFIG_LBLAW1=y +CONFIG_LBLAW1_BASE=0xE0600000 +CONFIG_LBLAW1_NAME="FPGA0" +CONFIG_LBLAW1_LENGTH_1_MBYTES=y CONFIG_CMD_IOLOOP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/hrcon_dh_defconfig b/configs/hrcon_dh_defconfig index c113543472..22689ef0ac 100644 --- a/configs/hrcon_dh_defconfig +++ b/configs/hrcon_dh_defconfig @@ -46,6 +46,14 @@ CONFIG_BAT3_BASE=0xE6000000 CONFIG_BAT3_ACCESS_RW=y CONFIG_BAT3_USER_MODE_VALID=y CONFIG_BAT3_SUPERVISOR_MODE_VALID=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xFE000000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_8_MBYTES=y +CONFIG_LBLAW1=y +CONFIG_LBLAW1_BASE=0xE0600000 +CONFIG_LBLAW1_NAME="FPGA0" +CONFIG_LBLAW1_LENGTH_1_MBYTES=y CONFIG_CMD_IOLOOP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/ids8313_defconfig b/configs/ids8313_defconfig index 4afed47033..168564606c 100644 --- a/configs/ids8313_defconfig +++ b/configs/ids8313_defconfig @@ -53,6 +53,23 @@ CONFIG_BAT6_ICACHE_GUARDED=y CONFIG_BAT6_DCACHE_GUARDED=y CONFIG_BAT6_USER_MODE_VALID=y CONFIG_BAT6_SUPERVISOR_MODE_VALID=y +CONFIG_NAND_LBLAWBAR_PRELIM_1=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xFF800000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_8_MBYTES=y +CONFIG_LBLAW1=y +CONFIG_LBLAW1_BASE=0xE1000000 +CONFIG_LBLAW1_NAME="NAND" +CONFIG_LBLAW1_LENGTH_32_KBYTES=y +CONFIG_LBLAW2=y +CONFIG_LBLAW2_BASE=0xE2000000 +CONFIG_LBLAW2_NAME="MRAM" +CONFIG_LBLAW2_LENGTH_128_KBYTES=y +CONFIG_LBLAW3=y +CONFIG_LBLAW3_BASE=0xE3000000 +CONFIG_LBLAW3_NAME="CPLD" +CONFIG_LBLAW3_LENGTH_32_KBYTES=y CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_IMAGE_FORMAT_LEGACY=y diff --git a/configs/kmcoge5ne_defconfig b/configs/kmcoge5ne_defconfig index a358e28886..088dee63ba 100644 --- a/configs/kmcoge5ne_defconfig +++ b/configs/kmcoge5ne_defconfig @@ -92,6 +92,18 @@ CONFIG_BAT7_DCACHE_INHIBITED=y CONFIG_BAT7_DCACHE_GUARDED=y CONFIG_BAT7_USER_MODE_VALID=y CONFIG_BAT7_SUPERVISOR_MODE_VALID=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xF0000000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_256_MBYTES=y +CONFIG_LBLAW1=y +CONFIG_LBLAW1_BASE=0xE8000000 +CONFIG_LBLAW1_NAME="KMBEC_FPGA" +CONFIG_LBLAW1_LENGTH_128_MBYTES=y +CONFIG_LBLAW3=y +CONFIG_LBLAW3_BASE=0xA0000000 +CONFIG_LBLAW3_NAME="PAXE" +CONFIG_LBLAW3_LENGTH_512_MBYTES=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_MISC_INIT_R=y diff --git a/configs/kmeter1_defconfig b/configs/kmeter1_defconfig index 10f7fdf110..64ea83fd12 100644 --- a/configs/kmeter1_defconfig +++ b/configs/kmeter1_defconfig @@ -65,6 +65,18 @@ CONFIG_BAT5_DCACHE_INHIBITED=y CONFIG_BAT5_DCACHE_GUARDED=y CONFIG_BAT5_USER_MODE_VALID=y CONFIG_BAT5_SUPERVISOR_MODE_VALID=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xF0000000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_256_MBYTES=y +CONFIG_LBLAW1=y +CONFIG_LBLAW1_BASE=0xE8000000 +CONFIG_LBLAW1_NAME="KMBEC_FPGA" +CONFIG_LBLAW1_LENGTH_128_MBYTES=y +CONFIG_LBLAW3=y +CONFIG_LBLAW3_BASE=0xA0000000 +CONFIG_LBLAW3_NAME="PAXE" +CONFIG_LBLAW3_LENGTH_512_MBYTES=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_MISC_INIT_R=y diff --git a/configs/kmopti2_defconfig b/configs/kmopti2_defconfig index b32b39113f..3a88b6a027 100644 --- a/configs/kmopti2_defconfig +++ b/configs/kmopti2_defconfig @@ -76,6 +76,22 @@ CONFIG_BAT6_DCACHE_INHIBITED=y CONFIG_BAT6_DCACHE_GUARDED=y CONFIG_BAT6_USER_MODE_VALID=y CONFIG_BAT6_SUPERVISOR_MODE_VALID=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xF0000000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_256_MBYTES=y +CONFIG_LBLAW1=y +CONFIG_LBLAW1_BASE=0xE8000000 +CONFIG_LBLAW1_NAME="KMBEC_FPGA" +CONFIG_LBLAW1_LENGTH_128_MBYTES=y +CONFIG_LBLAW2=y +CONFIG_LBLAW2_BASE=0xA0000000 +CONFIG_LBLAW2_NAME="APP1" +CONFIG_LBLAW2_LENGTH_256_MBYTES=y +CONFIG_LBLAW3=y +CONFIG_LBLAW3_BASE=0xB0000000 +CONFIG_LBLAW3_NAME="APP2" +CONFIG_LBLAW3_LENGTH_256_MBYTES=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_MISC_INIT_R=y diff --git a/configs/kmsupx5_defconfig b/configs/kmsupx5_defconfig index cc94d174f0..c818d7e4a1 100644 --- a/configs/kmsupx5_defconfig +++ b/configs/kmsupx5_defconfig @@ -66,6 +66,18 @@ CONFIG_BAT5_DCACHE_INHIBITED=y CONFIG_BAT5_DCACHE_GUARDED=y CONFIG_BAT5_USER_MODE_VALID=y CONFIG_BAT5_SUPERVISOR_MODE_VALID=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xF0000000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_256_MBYTES=y +CONFIG_LBLAW1=y +CONFIG_LBLAW1_BASE=0xE8000000 +CONFIG_LBLAW1_NAME="KMBEC_FPGA" +CONFIG_LBLAW1_LENGTH_128_MBYTES=y +CONFIG_LBLAW2=y +CONFIG_LBLAW2_BASE=0xA0000000 +CONFIG_LBLAW2_NAME="APP1" +CONFIG_LBLAW2_LENGTH_256_MBYTES=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_MISC_INIT_R=y diff --git a/configs/kmtegr1_defconfig b/configs/kmtegr1_defconfig index 994e1525f7..640e0c7c3c 100644 --- a/configs/kmtegr1_defconfig +++ b/configs/kmtegr1_defconfig @@ -67,6 +67,18 @@ CONFIG_BAT6_DCACHE_INHIBITED=y CONFIG_BAT6_DCACHE_GUARDED=y CONFIG_BAT6_USER_MODE_VALID=y CONFIG_BAT6_SUPERVISOR_MODE_VALID=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xF0000000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_256_MBYTES=y +CONFIG_LBLAW1=y +CONFIG_LBLAW1_BASE=0xE8000000 +CONFIG_LBLAW1_NAME="KMBEC_FPGA" +CONFIG_LBLAW1_LENGTH_128_MBYTES=y +CONFIG_LBLAW3=y +CONFIG_LBLAW3_BASE=0xB0000000 +CONFIG_LBLAW3_NAME="APP2" +CONFIG_LBLAW3_LENGTH_256_MBYTES=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="KMTEGR1" diff --git a/configs/kmtepr2_defconfig b/configs/kmtepr2_defconfig index bb23786057..81579c6b02 100644 --- a/configs/kmtepr2_defconfig +++ b/configs/kmtepr2_defconfig @@ -76,6 +76,22 @@ CONFIG_BAT6_DCACHE_INHIBITED=y CONFIG_BAT6_DCACHE_GUARDED=y CONFIG_BAT6_USER_MODE_VALID=y CONFIG_BAT6_SUPERVISOR_MODE_VALID=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xF0000000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_256_MBYTES=y +CONFIG_LBLAW1=y +CONFIG_LBLAW1_BASE=0xE8000000 +CONFIG_LBLAW1_NAME="KMBEC_FPGA" +CONFIG_LBLAW1_LENGTH_128_MBYTES=y +CONFIG_LBLAW2=y +CONFIG_LBLAW2_BASE=0xA0000000 +CONFIG_LBLAW2_NAME="APP1" +CONFIG_LBLAW2_LENGTH_256_MBYTES=y +CONFIG_LBLAW3=y +CONFIG_LBLAW3_BASE=0xB0000000 +CONFIG_LBLAW3_NAME="APP2" +CONFIG_LBLAW3_LENGTH_256_MBYTES=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_MISC_INIT_R=y diff --git a/configs/kmvect1_defconfig b/configs/kmvect1_defconfig index 666dbf32cc..709947b539 100644 --- a/configs/kmvect1_defconfig +++ b/configs/kmvect1_defconfig @@ -77,6 +77,22 @@ CONFIG_BAT6_DCACHE_INHIBITED=y CONFIG_BAT6_DCACHE_GUARDED=y CONFIG_BAT6_USER_MODE_VALID=y CONFIG_BAT6_SUPERVISOR_MODE_VALID=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xF0000000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_256_MBYTES=y +CONFIG_LBLAW1=y +CONFIG_LBLAW1_BASE=0xE8000000 +CONFIG_LBLAW1_NAME="KMBEC_FPGA" +CONFIG_LBLAW1_LENGTH_128_MBYTES=y +CONFIG_LBLAW2=y +CONFIG_LBLAW2_BASE=0xA0000000 +CONFIG_LBLAW2_NAME="APP1" +CONFIG_LBLAW2_LENGTH_256_MBYTES=y +CONFIG_LBLAW3=y +CONFIG_LBLAW3_BASE=0xB0000000 +CONFIG_LBLAW3_NAME="APP2" +CONFIG_LBLAW3_LENGTH_256_MBYTES=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="KMVECT1" diff --git a/configs/mpc8308_p1m_defconfig b/configs/mpc8308_p1m_defconfig index f583fa922e..b44e04e1ae 100644 --- a/configs/mpc8308_p1m_defconfig +++ b/configs/mpc8308_p1m_defconfig @@ -44,6 +44,18 @@ CONFIG_BAT3_BASE=0xE6000000 CONFIG_BAT3_ACCESS_RW=y CONFIG_BAT3_USER_MODE_VALID=y CONFIG_BAT3_SUPERVISOR_MODE_VALID=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xFC000000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_64_MBYTES=y +CONFIG_LBLAW1=y +CONFIG_LBLAW1_BASE=0xFBFF0000 +CONFIG_LBLAW1_NAME="SJA1000" +CONFIG_LBLAW1_LENGTH_32_KBYTES=y +CONFIG_LBLAW2=y +CONFIG_LBLAW2_BASE=0xFBFF8000 +CONFIG_LBLAW2_NAME="CPLD" +CONFIG_LBLAW2_LENGTH_32_KBYTES=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=5 diff --git a/configs/sbc8349_PCI_33_defconfig b/configs/sbc8349_PCI_33_defconfig index f8ce309376..6f407d56d5 100644 --- a/configs/sbc8349_PCI_33_defconfig +++ b/configs/sbc8349_PCI_33_defconfig @@ -65,6 +65,10 @@ CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y CONFIG_BAT6_DCACHE_GUARDED=y CONFIG_BAT6_USER_MODE_VALID=y CONFIG_BAT6_SUPERVISOR_MODE_VALID=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xFF800000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_8_MBYTES=y CONFIG_PCI_64BIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/configs/sbc8349_PCI_66_defconfig b/configs/sbc8349_PCI_66_defconfig index bc9e228894..9c0b30f446 100644 --- a/configs/sbc8349_PCI_66_defconfig +++ b/configs/sbc8349_PCI_66_defconfig @@ -65,6 +65,10 @@ CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y CONFIG_BAT6_DCACHE_GUARDED=y CONFIG_BAT6_USER_MODE_VALID=y CONFIG_BAT6_SUPERVISOR_MODE_VALID=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xFF800000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_8_MBYTES=y CONFIG_PCI_64BIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/configs/sbc8349_defconfig b/configs/sbc8349_defconfig index d8e60da7be..05361f76fc 100644 --- a/configs/sbc8349_defconfig +++ b/configs/sbc8349_defconfig @@ -45,6 +45,10 @@ CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y CONFIG_BAT6_DCACHE_GUARDED=y CONFIG_BAT6_USER_MODE_VALID=y CONFIG_BAT6_SUPERVISOR_MODE_VALID=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xFF800000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_8_MBYTES=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/strider_con_defconfig b/configs/strider_con_defconfig index 508ffe201a..196c44470a 100644 --- a/configs/strider_con_defconfig +++ b/configs/strider_con_defconfig @@ -45,6 +45,14 @@ CONFIG_BAT3_BASE=0xE6000000 CONFIG_BAT3_ACCESS_RW=y CONFIG_BAT3_USER_MODE_VALID=y CONFIG_BAT3_SUPERVISOR_MODE_VALID=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xFE000000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_8_MBYTES=y +CONFIG_LBLAW1=y +CONFIG_LBLAW1_BASE=0xE0600000 +CONFIG_LBLAW1_NAME="FPGA0" +CONFIG_LBLAW1_LENGTH_1_MBYTES=y CONFIG_CMD_IOLOOP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/strider_con_dp_defconfig b/configs/strider_con_dp_defconfig index 514db1c213..c407bed189 100644 --- a/configs/strider_con_dp_defconfig +++ b/configs/strider_con_dp_defconfig @@ -45,6 +45,14 @@ CONFIG_BAT3_BASE=0xE6000000 CONFIG_BAT3_ACCESS_RW=y CONFIG_BAT3_USER_MODE_VALID=y CONFIG_BAT3_SUPERVISOR_MODE_VALID=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xFE000000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_8_MBYTES=y +CONFIG_LBLAW1=y +CONFIG_LBLAW1_BASE=0xE0600000 +CONFIG_LBLAW1_NAME="FPGA0" +CONFIG_LBLAW1_LENGTH_1_MBYTES=y CONFIG_CMD_IOLOOP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/strider_cpu_defconfig b/configs/strider_cpu_defconfig index a998585f3a..1128950ace 100644 --- a/configs/strider_cpu_defconfig +++ b/configs/strider_cpu_defconfig @@ -45,6 +45,14 @@ CONFIG_BAT3_BASE=0xE6000000 CONFIG_BAT3_ACCESS_RW=y CONFIG_BAT3_USER_MODE_VALID=y CONFIG_BAT3_SUPERVISOR_MODE_VALID=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xFE000000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_8_MBYTES=y +CONFIG_LBLAW1=y +CONFIG_LBLAW1_BASE=0xE0600000 +CONFIG_LBLAW1_NAME="FPGA0" +CONFIG_LBLAW1_LENGTH_1_MBYTES=y CONFIG_CMD_IOLOOP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/strider_cpu_dp_defconfig b/configs/strider_cpu_dp_defconfig index 48579c7563..f0b2c44efb 100644 --- a/configs/strider_cpu_dp_defconfig +++ b/configs/strider_cpu_dp_defconfig @@ -45,6 +45,14 @@ CONFIG_BAT3_BASE=0xE6000000 CONFIG_BAT3_ACCESS_RW=y CONFIG_BAT3_USER_MODE_VALID=y CONFIG_BAT3_SUPERVISOR_MODE_VALID=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xFE000000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_8_MBYTES=y +CONFIG_LBLAW1=y +CONFIG_LBLAW1_BASE=0xE0600000 +CONFIG_LBLAW1_NAME="FPGA0" +CONFIG_LBLAW1_LENGTH_1_MBYTES=y CONFIG_CMD_IOLOOP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/suvd3_defconfig b/configs/suvd3_defconfig index 4dd36cac91..10a32178f1 100644 --- a/configs/suvd3_defconfig +++ b/configs/suvd3_defconfig @@ -76,6 +76,22 @@ CONFIG_BAT6_DCACHE_INHIBITED=y CONFIG_BAT6_DCACHE_GUARDED=y CONFIG_BAT6_USER_MODE_VALID=y CONFIG_BAT6_SUPERVISOR_MODE_VALID=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xF0000000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_256_MBYTES=y +CONFIG_LBLAW1=y +CONFIG_LBLAW1_BASE=0xE8000000 +CONFIG_LBLAW1_NAME="KMBEC_FPGA" +CONFIG_LBLAW1_LENGTH_128_MBYTES=y +CONFIG_LBLAW2=y +CONFIG_LBLAW2_BASE=0xA0000000 +CONFIG_LBLAW2_NAME="APP1" +CONFIG_LBLAW2_LENGTH_256_MBYTES=y +CONFIG_LBLAW3=y +CONFIG_LBLAW3_BASE=0xB0000000 +CONFIG_LBLAW3_NAME="APP2" +CONFIG_LBLAW3_LENGTH_256_MBYTES=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SUVD3" diff --git a/configs/tuge1_defconfig b/configs/tuge1_defconfig index 7db157bf21..6fada9bdf7 100644 --- a/configs/tuge1_defconfig +++ b/configs/tuge1_defconfig @@ -66,6 +66,18 @@ CONFIG_BAT5_DCACHE_INHIBITED=y CONFIG_BAT5_DCACHE_GUARDED=y CONFIG_BAT5_USER_MODE_VALID=y CONFIG_BAT5_SUPERVISOR_MODE_VALID=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xF0000000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_256_MBYTES=y +CONFIG_LBLAW1=y +CONFIG_LBLAW1_BASE=0xE8000000 +CONFIG_LBLAW1_NAME="KMBEC_FPGA" +CONFIG_LBLAW1_LENGTH_128_MBYTES=y +CONFIG_LBLAW2=y +CONFIG_LBLAW2_BASE=0xA0000000 +CONFIG_LBLAW2_NAME="APP1" +CONFIG_LBLAW2_LENGTH_256_MBYTES=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_MISC_INIT_R=y diff --git a/configs/tuxx1_defconfig b/configs/tuxx1_defconfig index e0c1366291..1eb21e0e5a 100644 --- a/configs/tuxx1_defconfig +++ b/configs/tuxx1_defconfig @@ -76,6 +76,22 @@ CONFIG_BAT6_DCACHE_INHIBITED=y CONFIG_BAT6_DCACHE_GUARDED=y CONFIG_BAT6_USER_MODE_VALID=y CONFIG_BAT6_SUPERVISOR_MODE_VALID=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xF0000000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_256_MBYTES=y +CONFIG_LBLAW1=y +CONFIG_LBLAW1_BASE=0xE8000000 +CONFIG_LBLAW1_NAME="KMBEC_FPGA" +CONFIG_LBLAW1_LENGTH_128_MBYTES=y +CONFIG_LBLAW2=y +CONFIG_LBLAW2_BASE=0xA0000000 +CONFIG_LBLAW2_NAME="APP1" +CONFIG_LBLAW2_LENGTH_256_MBYTES=y +CONFIG_LBLAW3=y +CONFIG_LBLAW3_BASE=0xB0000000 +CONFIG_LBLAW3_NAME="APP2" +CONFIG_LBLAW3_LENGTH_256_MBYTES=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_MISC_INIT_R=y diff --git a/configs/ve8313_defconfig b/configs/ve8313_defconfig index 517c4aa854..1df5195e97 100644 --- a/configs/ve8313_defconfig +++ b/configs/ve8313_defconfig @@ -65,6 +65,15 @@ CONFIG_BAT7_ICACHE_GUARDED=y CONFIG_BAT7_DCACHE_GUARDED=y CONFIG_BAT7_USER_MODE_VALID=y CONFIG_BAT7_SUPERVISOR_MODE_VALID=y +CONFIG_NAND_LBLAWBAR_PRELIM_1=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xFE000000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_32_MBYTES=y +CONFIG_LBLAW1=y +CONFIG_LBLAW1_BASE=0x61000000 +CONFIG_LBLAW1_NAME="NAND" +CONFIG_LBLAW1_LENGTH_32_KBYTES=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/vme8349_defconfig b/configs/vme8349_defconfig index b7cf6a44bc..9336dfac5c 100644 --- a/configs/vme8349_defconfig +++ b/configs/vme8349_defconfig @@ -63,6 +63,14 @@ CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y CONFIG_BAT6_USER_MODE_VALID=y CONFIG_BAT6_SUPERVISOR_MODE_VALID=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xF8000000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_128_MBYTES=y +CONFIG_LBLAW1=y +CONFIG_LBLAW1_BASE=0xF0000000 +CONFIG_LBLAW1_NAME="WINDOW1" +CONFIG_LBLAW1_LENGTH_256_KBYTES=y CONFIG_PCI_64BIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h index dc7a8b8aa8..1953d18e87 100644 --- a/include/configs/MPC8308RDB.h +++ b/include/configs/MPC8308RDB.h @@ -176,9 +176,6 @@ #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is 8M */ /* Window base at flash base */ -#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB) - #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ | BR_PS_16 /* 16 bit port */ \ | BR_MS_GPCM /* MSEL = GPCM */ \ @@ -218,9 +215,6 @@ | OR_FCM_EHTR) /* 0xFFFF8396 */ -#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE -#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) - #ifdef CONFIG_VSC7385_ENET #define CONFIG_TSEC2 /* VSC7385 Base address on CS2 */ @@ -239,10 +233,6 @@ | OR_GPCM_TRLX_SET \ | OR_GPCM_EHTR_SET) /* 0xFFFE09FF */ -/* Access window base at VSC7385 base */ -#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE -/* Access window size 128K */ -#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) /* The flash address and size of the VSC7385 firmware image */ #define CONFIG_VSC7385_IMAGE 0xFE7FE000 #define CONFIG_VSC7385_IMAGE_SIZE 8192 diff --git a/include/configs/MPC8313ERDB_NAND.h b/include/configs/MPC8313ERDB_NAND.h index 596d39ee5e..79c7f12bae 100644 --- a/include/configs/MPC8313ERDB_NAND.h +++ b/include/configs/MPC8313ERDB_NAND.h @@ -180,10 +180,6 @@ | OR_GPCM_EHTR \ | OR_GPCM_EAD) /* 0xFF006FF7 TODO SLOW 16 MB flash size */ - /* window base at flash base */ -#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE - /* 16 MB window size */ -#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_16MB) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 135 /* sectors per device */ @@ -253,12 +249,6 @@ #define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR0_PRELIM #define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR0_PRELIM -#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE -#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) - -#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM -#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM - /* local bus write LED / read status buffer (BCSR) mapping */ #define CONFIG_SYS_BCSR_ADDR 0xFA000000 #define CONFIG_SYS_BCSR_SIZE (32 * 1024) /* 0x00008000 */ @@ -277,9 +267,6 @@ | OR_GPCM_EHTR_SET \ | OR_GPCM_EAD) /* 0xFFFF8FF7 */ -#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_BCSR_ADDR -#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) - /* Vitesse 7385 */ #ifdef CONFIG_VSC7385_ENET @@ -301,11 +288,6 @@ | OR_GPCM_EHTR_SET \ | OR_GPCM_EAD) /* 0xFFFE09FF */ - - /* Access window base at VSC7385 base */ -#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE -#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) - #endif #define CONFIG_MPC83XX_GPIO 1 diff --git a/include/configs/MPC8313ERDB_NOR.h b/include/configs/MPC8313ERDB_NOR.h index 9d1ce200ec..1b2bba96d3 100644 --- a/include/configs/MPC8313ERDB_NOR.h +++ b/include/configs/MPC8313ERDB_NOR.h @@ -153,10 +153,6 @@ | OR_GPCM_EHTR \ | OR_GPCM_EAD) /* 0xFF006FF7 TODO SLOW 16 MB flash size */ - /* window base at flash base */ -#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE - /* 16 MB window size */ -#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_16MB) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 135 /* sectors per device */ @@ -222,12 +218,6 @@ #define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM #define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM -#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE -#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) - -#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM -#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM - /* local bus write LED / read status buffer (BCSR) mapping */ #define CONFIG_SYS_BCSR_ADDR 0xFA000000 #define CONFIG_SYS_BCSR_SIZE (32 * 1024) /* 0x00008000 */ @@ -246,9 +236,6 @@ | OR_GPCM_EHTR_SET \ | OR_GPCM_EAD) /* 0xFFFF8FF7 */ -#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_BCSR_ADDR -#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) - /* Vitesse 7385 */ #ifdef CONFIG_VSC7385_ENET @@ -270,11 +257,6 @@ | OR_GPCM_EHTR_SET \ | OR_GPCM_EAD) /* 0xFFFE09FF */ - - /* Access window base at VSC7385 base */ -#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE -#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) - #endif #define CONFIG_MPC83XX_GPIO 1 diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index fb568efe2d..86491b41d6 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -146,10 +146,6 @@ #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is 8M */ - /* Window base at flash base */ -#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB) - #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ /* 127 64KB sectors and 8 8KB top sectors per device */ #define CONFIG_SYS_MAX_FLASH_SECT 135 @@ -213,12 +209,6 @@ #define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM #define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM -#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE -#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) - -#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM -#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM - #if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE && \ !defined(CONFIG_NAND_SPL) #define CONFIG_SYS_RAMBOOT diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index 489e7c3368..cb17c7644d 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -141,9 +141,6 @@ #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ #define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size is 16M */ - /* Window base at flash base */ -#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB) #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ | BR_PS_16 /* 16 bit port */ \ diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index 15fca456cc..d51d5ce06d 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -133,10 +133,6 @@ #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ #define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size is 16M */ - /* Window base at flash base */ -#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB) - #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ | BR_PS_16 /* 16 bit port */ \ | BR_MS_GPCM /* MSEL = GPCM */ \ @@ -162,8 +158,6 @@ */ #define CONFIG_SYS_BCSR 0xF8000000 /* Access window base at BCSR base */ -#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR -#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \ | BR_PS_8 \ @@ -185,8 +179,6 @@ /* PIB window base 0xF8008000 */ #define CONFIG_SYS_PIB_BASE 0xF8008000 #define CONFIG_SYS_PIB_WINDOW_SIZE (32 * 1024) -#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_PIB_BASE -#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_64KB) /* * CS2 on Local Bus, to PIB diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index e4d90589e9..06017a81bc 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -137,10 +137,6 @@ | OR_GPCM_EHTR_SET \ | OR_GPCM_EAD) - /* window base at flash base */ -#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB) - #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ @@ -161,8 +157,6 @@ */ #define CONFIG_SYS_BCSR 0xE2400000 /* Access window base at BCSR base */ -#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR -#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \ | BR_PS_8 \ | BR_MS_GPCM \ diff --git a/include/configs/MPC8349EMDS_SDRAM.h b/include/configs/MPC8349EMDS_SDRAM.h index a24a2011d2..708a21f164 100644 --- a/include/configs/MPC8349EMDS_SDRAM.h +++ b/include/configs/MPC8349EMDS_SDRAM.h @@ -137,10 +137,6 @@ | OR_GPCM_EHTR_SET \ | OR_GPCM_EAD) - /* window base at flash base */ -#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB) - #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ @@ -161,8 +157,6 @@ */ #define CONFIG_SYS_BCSR 0xE2400000 /* Access window base at BCSR base */ -#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR -#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \ | BR_PS_8 \ | BR_MS_GPCM \ @@ -222,8 +216,6 @@ | BR_MS_SDRAM /* MSEL = SDRAM */ \ | BR_V) /* Valid */ /* 0xF0001861 */ -#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LBC_SDRAM_BASE -#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_64MB) /* * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index aeee6e0408..16d615dcc6 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -226,9 +226,6 @@ boards, we say we have two, but don't display a message if we find only one. */ | OR_GPCM_TRLX_SET \ | OR_GPCM_EHTR_SET \ | OR_GPCM_EAD) -#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_16MB) - /* Vitesse 7385 */ #define CONFIG_SYS_VSC7385_BASE 0xF8000000 @@ -247,10 +244,6 @@ boards, we say we have two, but don't display a message if we find only one. */ | OR_GPCM_TRLX_SET \ | OR_GPCM_EHTR_SET \ | OR_GPCM_EAD) - -#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_VSC7385_BASE -#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) - #endif /* LED */ @@ -281,9 +274,6 @@ boards, we say we have two, but don't display a message if we find only one. */ | BR_V) #define CONFIG_SYS_OR3_PRELIM (OR_UPM_AM | OR_UPM_BI) -#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_CF_BASE -#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_64KB) - #endif /* diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index 01a3a77e99..9d6dc767ef 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -162,10 +162,6 @@ #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ #define CONFIG_SYS_FLASH_SIZE 32 /* max FLASH size is 32M */ - /* Window base at flash base */ -#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB) - #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ | BR_PS_16 /* 16 bit port */ \ | BR_MS_GPCM /* MSEL = GPCM */ \ @@ -193,9 +189,6 @@ */ #define CONFIG_SYS_BCSR 0xF8000000 /* Access window base at BCSR base */ -#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR -#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) - #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \ | BR_PS_8 \ | BR_MS_GPCM \ @@ -233,9 +226,6 @@ | OR_FCM_EHTR) /* 0xFFFF919E */ -#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_NAND_BASE -#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) - /* * Serial Port */ diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index 9a4eeb6390..a1de8acc5c 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -188,10 +188,6 @@ #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */ - /* Window base at flash base */ -#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016 /* 8 MB window size */ - #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ | BR_PS_16 /* 16 bit port */ \ | BR_MS_GPCM /* MSEL = GPCM */ \ @@ -226,9 +222,6 @@ | OR_FCM_SCY_1 \ | OR_FCM_TRLX \ | OR_FCM_EHTR) -#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE -#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) - /* Vitesse 7385 */ #define CONFIG_SYS_VSC7385_BASE 0xF0000000 @@ -249,11 +242,6 @@ | OR_GPCM_EHTR_SET \ | OR_GPCM_EAD) /* 0xfffe09ff */ - - /* Access Base */ -#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE -#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) - #endif /* diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index c5a6203001..4479000d25 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -93,26 +93,15 @@ #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM \ | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_1GB) - - /* Window base at flash base */ -#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE - /* disable remaining mappings */ #define CONFIG_SYS_BR1_PRELIM 0x00000000 #define CONFIG_SYS_OR1_PRELIM 0x00000000 -#define CONFIG_SYS_LBLAWBAR1_PRELIM 0x00000000 -#define CONFIG_SYS_LBLAWAR1_PRELIM 0x00000000 #define CONFIG_SYS_BR2_PRELIM 0x00000000 #define CONFIG_SYS_OR2_PRELIM 0x00000000 -#define CONFIG_SYS_LBLAWBAR2_PRELIM 0x00000000 -#define CONFIG_SYS_LBLAWAR2_PRELIM 0x00000000 #define CONFIG_SYS_BR3_PRELIM 0x00000000 #define CONFIG_SYS_OR3_PRELIM 0x00000000 -#define CONFIG_SYS_LBLAWBAR3_PRELIM 0x00000000 -#define CONFIG_SYS_LBLAWAR3_PRELIM 0x00000000 /* * Monitor config diff --git a/include/configs/caddy2.h b/include/configs/caddy2.h index f4ee222808..b355e56355 100644 --- a/include/configs/caddy2.h +++ b/include/configs/caddy2.h @@ -84,8 +84,6 @@ | OR_GPCM_EHTR_SET \ | OR_GPCM_EAD) /* 0xffc06ff7 */ -#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_4MB) #define CONFIG_SYS_WINDOW1_BASE 0xf0000000 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_WINDOW1_BASE \ @@ -96,8 +94,6 @@ #define CONFIG_SYS_OR1_PRELIM (OR_AM_256KB \ | OR_GPCM_SETA) /* 0xfffc0208 */ -#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_WINDOW1_BASE -#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_256KB) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device*/ diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h index c8fabf9da5..d86de800db 100644 --- a/include/configs/hrcon.h +++ b/include/configs/hrcon.h @@ -170,9 +170,6 @@ #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */ /* Window base at flash base */ -#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB) - #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ | BR_PS_16 /* 16 bit port */ \ | BR_MS_GPCM /* MSEL = GPCM */ \ @@ -199,9 +196,6 @@ #define CONFIG_SYS_FPGA0_SIZE 1 /* FPGA size is 1M */ /* Window base at FPGA base */ -#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_FPGA0_BASE -#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_1MB) - #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FPGA0_BASE \ | BR_PS_16 /* 16 bit port */ \ | BR_MS_GPCM /* MSEL = GPCM */ \ diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h index 120eb0a6b7..e930c65637 100644 --- a/include/configs/ids8313.h +++ b/include/configs/ids8313.h @@ -142,9 +142,6 @@ #define CONFIG_SYS_FLASH_BASE 0xFF800000 #define CONFIG_SYS_FLASH_SIZE 8 -#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016 - #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE |\ BR_PS_8 |\ BR_MS_GPCM |\ @@ -173,11 +170,6 @@ #define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10) #define NAND_CACHE_PAGES 64 -#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE -#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E -#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM -#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM - #define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_NAND_BASE) |\ (2< Date: Mon, 21 Jan 2019 09:17:59 +0100 Subject: [PATCH 36/86] mpc83xx: Normalize BR/OR option lines All BR/OR option lines should have the same layout to make them easier to migrate to Kconfig. This includes using the same option macros everywhere. The normalize the lines, * replace function macros with their results, and * replace hardcoded hex values with standard macros Signed-off-by: Mario Six --- include/configs/MPC8308RDB.h | 6 +++--- include/configs/MPC8313ERDB_NAND.h | 4 ++-- include/configs/MPC8313ERDB_NOR.h | 4 ++-- include/configs/MPC8323ERDB.h | 2 +- include/configs/MPC832XEMDS.h | 6 +++--- include/configs/MPC8349EMDS.h | 2 +- include/configs/MPC8349EMDS_SDRAM.h | 2 +- include/configs/MPC8349ITX.h | 2 +- include/configs/MPC837XEMDS.h | 2 +- include/configs/MPC837XERDB.h | 2 +- include/configs/caddy2.h | 2 +- include/configs/hrcon.h | 4 ++-- include/configs/ids8313.h | 10 +++++----- include/configs/kmcoge5ne.h | 12 ++++++------ include/configs/kmeter1.h | 8 ++++---- include/configs/kmopti2.h | 8 ++++---- include/configs/kmsupx5.h | 6 +++--- include/configs/kmtegr1.h | 6 +++--- include/configs/kmtepr2.h | 8 ++++---- include/configs/kmvect1.h | 8 ++++---- include/configs/mpc8308_p1m.h | 2 +- include/configs/sbc8349.h | 4 ++-- include/configs/strider.h | 4 ++-- include/configs/suvd3.h | 8 ++++---- include/configs/tuge1.h | 6 +++--- include/configs/tuxx1.h | 8 ++++---- include/configs/vme8349.h | 2 +- 27 files changed, 69 insertions(+), 69 deletions(-) diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h index 1953d18e87..e19bcafd5c 100644 --- a/include/configs/MPC8308RDB.h +++ b/include/configs/MPC8308RDB.h @@ -180,7 +180,7 @@ | BR_PS_16 /* 16 bit port */ \ | BR_MS_GPCM /* MSEL = GPCM */ \ | BR_V) /* valid */ -#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ +#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB \ | OR_UPM_XAM \ | OR_GPCM_CSNT \ | OR_GPCM_ACS_DIV2 \ @@ -206,7 +206,7 @@ | BR_PS_8 /* 8 bit Port */ \ | BR_MS_FCM /* MSEL = FCM */ \ | BR_V) /* valid */ -#define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \ +#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \ | OR_FCM_CSCT \ | OR_FCM_CST \ | OR_FCM_CHT \ @@ -225,7 +225,7 @@ | BR_MS_GPCM /* MSEL = GPCM */ \ | BR_V) /* valid */ /* 0xF0000801 */ -#define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \ +#define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB \ | OR_GPCM_CSNT \ | OR_GPCM_XACS \ | OR_GPCM_SCY_15 \ diff --git a/include/configs/MPC8313ERDB_NAND.h b/include/configs/MPC8313ERDB_NAND.h index 79c7f12bae..bbb9d4b936 100644 --- a/include/configs/MPC8313ERDB_NAND.h +++ b/include/configs/MPC8313ERDB_NAND.h @@ -258,7 +258,7 @@ | BR_MS_GPCM /* MSEL = GPCM */ \ | BR_V) /* valid */ /* 0xFA000801 */ -#define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(CONFIG_SYS_BCSR_SIZE) \ +#define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB \ | OR_GPCM_CSNT \ | OR_GPCM_ACS_DIV2 \ | OR_GPCM_XACS \ @@ -279,7 +279,7 @@ | BR_PS_8 /* 8 bit port */ \ | BR_MS_GPCM /* MSEL = GPCM */ \ | BR_V) /* valid */ -#define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \ +#define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB \ | OR_GPCM_CSNT \ | OR_GPCM_XACS \ | OR_GPCM_SCY_15 \ diff --git a/include/configs/MPC8313ERDB_NOR.h b/include/configs/MPC8313ERDB_NOR.h index 1b2bba96d3..1cb001864a 100644 --- a/include/configs/MPC8313ERDB_NOR.h +++ b/include/configs/MPC8313ERDB_NOR.h @@ -227,7 +227,7 @@ | BR_MS_GPCM /* MSEL = GPCM */ \ | BR_V) /* valid */ /* 0xFA000801 */ -#define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(CONFIG_SYS_BCSR_SIZE) \ +#define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB \ | OR_GPCM_CSNT \ | OR_GPCM_ACS_DIV2 \ | OR_GPCM_XACS \ @@ -248,7 +248,7 @@ | BR_PS_8 /* 8 bit port */ \ | BR_MS_GPCM /* MSEL = GPCM */ \ | BR_V) /* valid */ -#define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \ +#define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB \ | OR_GPCM_CSNT \ | OR_GPCM_XACS \ | OR_GPCM_SCY_15 \ diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index cb17c7644d..30f1e4453d 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -146,7 +146,7 @@ | BR_PS_16 /* 16 bit port */ \ | BR_MS_GPCM /* MSEL = GPCM */ \ | BR_V) /* valid */ -#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ +#define CONFIG_SYS_OR0_PRELIM (OR_AM_16MB \ | OR_GPCM_XAM \ | OR_GPCM_CSNT \ | OR_GPCM_ACS_DIV2 \ diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index d51d5ce06d..3a8a3e4fb8 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -137,7 +137,7 @@ | BR_PS_16 /* 16 bit port */ \ | BR_MS_GPCM /* MSEL = GPCM */ \ | BR_V) /* valid */ -#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ +#define CONFIG_SYS_OR0_PRELIM (OR_AM_16MB \ | OR_GPCM_XAM \ | OR_GPCM_CSNT \ | OR_GPCM_ACS_DIV2 \ @@ -188,7 +188,7 @@ | BR_MS_GPCM \ | BR_V) /* 0xF8008801 */ -#define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_PIB_WINDOW_SIZE) \ +#define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB \ | OR_GPCM_XAM \ | OR_GPCM_CSNT \ | OR_GPCM_XACS \ @@ -207,7 +207,7 @@ | BR_MS_GPCM \ | BR_V) /* 0xF8010801 */ -#define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(CONFIG_SYS_PIB_WINDOW_SIZE) \ +#define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB \ | OR_GPCM_XAM \ | OR_GPCM_CSNT \ | OR_GPCM_XACS \ diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 06017a81bc..fa73b81c3a 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -127,7 +127,7 @@ | BR_PS_16 /* 16 bit port */ \ | BR_MS_GPCM /* MSEL = GPCM */ \ | BR_V) /* valid */ -#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ +#define CONFIG_SYS_OR0_PRELIM (OR_AM_32MB \ | OR_UPM_XAM \ | OR_GPCM_CSNT \ | OR_GPCM_ACS_DIV2 \ diff --git a/include/configs/MPC8349EMDS_SDRAM.h b/include/configs/MPC8349EMDS_SDRAM.h index 708a21f164..218c4b1fc9 100644 --- a/include/configs/MPC8349EMDS_SDRAM.h +++ b/include/configs/MPC8349EMDS_SDRAM.h @@ -127,7 +127,7 @@ | BR_PS_16 /* 16 bit port */ \ | BR_MS_GPCM /* MSEL = GPCM */ \ | BR_V) /* valid */ -#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ +#define CONFIG_SYS_OR0_PRELIM (OR_AM_32MB \ | OR_UPM_XAM \ | OR_GPCM_CSNT \ | OR_GPCM_ACS_DIV2 \ diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index 16d615dcc6..0bf179a70b 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -217,7 +217,7 @@ boards, we say we have two, but don't display a message if we find only one. */ | BR_PS_16 \ | BR_MS_GPCM \ | BR_V) -#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ +#define CONFIG_SYS_OR0_PRELIM (OR_AM_16MB \ | OR_UPM_XAM \ | OR_GPCM_CSNT \ | OR_GPCM_ACS_DIV2 \ diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index 9d6dc767ef..e10c58d7ed 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -166,7 +166,7 @@ | BR_PS_16 /* 16 bit port */ \ | BR_MS_GPCM /* MSEL = GPCM */ \ | BR_V) /* valid */ -#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ +#define CONFIG_SYS_OR0_PRELIM (OR_AM_32MB \ | OR_UPM_XAM \ | OR_GPCM_CSNT \ | OR_GPCM_ACS_DIV2 \ diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index a1de8acc5c..1e45b5ee3f 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -192,7 +192,7 @@ | BR_PS_16 /* 16 bit port */ \ | BR_MS_GPCM /* MSEL = GPCM */ \ | BR_V) /* valid */ -#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ +#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB \ | OR_GPCM_XACS \ | OR_GPCM_SCY_9 \ | OR_GPCM_EHTR_SET \ diff --git a/include/configs/caddy2.h b/include/configs/caddy2.h index b355e56355..ffd52a200a 100644 --- a/include/configs/caddy2.h +++ b/include/configs/caddy2.h @@ -74,7 +74,7 @@ BR_MS_GPCM | /* MSEL = GPCM */ \ BR_V) /* valid */ -#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ +#define CONFIG_SYS_OR0_PRELIM (OR_AM_4MB \ | OR_GPCM_XAM \ | OR_GPCM_CSNT \ | OR_GPCM_ACS_DIV2 \ diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h index d86de800db..4193ceb379 100644 --- a/include/configs/hrcon.h +++ b/include/configs/hrcon.h @@ -174,7 +174,7 @@ | BR_PS_16 /* 16 bit port */ \ | BR_MS_GPCM /* MSEL = GPCM */ \ | BR_V) /* valid */ -#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ +#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB \ | OR_UPM_XAM \ | OR_GPCM_CSNT \ | OR_GPCM_ACS_DIV2 \ @@ -200,7 +200,7 @@ | BR_PS_16 /* 16 bit port */ \ | BR_MS_GPCM /* MSEL = GPCM */ \ | BR_V) /* valid */ -#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_FPGA0_SIZE) \ +#define CONFIG_SYS_OR1_PRELIM (OR_AM_1MB \ | OR_UPM_XAM \ | OR_GPCM_CSNT \ | OR_GPCM_ACS_DIV2 \ diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h index e930c65637..871b91f218 100644 --- a/include/configs/ids8313.h +++ b/include/configs/ids8313.h @@ -147,7 +147,7 @@ BR_MS_GPCM |\ BR_V) -#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\ +#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB |\ OR_GPCM_SCY_10 |\ OR_GPCM_EHTR |\ OR_GPCM_TRLX |\ @@ -171,12 +171,12 @@ #define NAND_CACHE_PAGES 64 #define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_NAND_BASE) |\ - (2< Date: Mon, 21 Jan 2019 09:18:00 +0100 Subject: [PATCH 37/86] tqm834x: Expand CONFIG_SYS_OR_TIMING_FLASH macro We want to normalize all BR/OR config lines as much as possible. The TQM834x board uses CONFIG_SYS_OR_TIMING_FLASH in a OR definition, which we want to remove. But CONFIG_SYS_OR_TIMING_FLASH is also used outside of the config file. Replace these usages with the definition of the variable, so we can remove the variable in the next patch. Signed-off-by: Mario Six --- board/tqc/tqm834x/tqm834x.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/tqc/tqm834x/tqm834x.c b/board/tqc/tqm834x/tqm834x.c index 7c92f4f54c..c75251e132 100644 --- a/board/tqc/tqm834x/tqm834x.c +++ b/board/tqc/tqm834x/tqm834x.c @@ -235,8 +235,8 @@ static int detect_num_flash_banks(void) debug("Number of flash banks detected: %d\n", cfi_flash_num_flash_banks); /* set OR0 and BR0 */ - set_lbc_or(0, CONFIG_SYS_OR_TIMING_FLASH | - (-(total_size) & OR_GPCM_AM)); + set_lbc_or(0, OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_5 | + OR_GPCM_TRLX | (-(total_size) & OR_GPCM_AM)); set_lbc_br(0, (CONFIG_SYS_FLASH_BASE & BR_BA) | (BR_MS_GPCM | BR_PS_32 | BR_V)); From a8f975391f2452bc7a51eeafd030c85c32e1aca5 Mon Sep 17 00:00:00 2001 From: Mario Six Date: Mon, 21 Jan 2019 09:18:01 +0100 Subject: [PATCH 38/86] mpc83xx: Simplify BR,OR lines Re-format all BR,OR #define lines into single lines. This makes them harder to read, but accessible to semi-automatic replacement. Signed-off-by: Mario Six --- include/configs/MPC8308RDB.h | 46 ++++--------------- include/configs/MPC8313ERDB_NAND.h | 67 +++++++-------------------- include/configs/MPC8313ERDB_NOR.h | 66 ++++++--------------------- include/configs/MPC8315ERDB.h | 34 +++----------- include/configs/MPC8323ERDB.h | 17 ++----- include/configs/MPC832XEMDS.h | 70 ++++++----------------------- include/configs/MPC8349EMDS.h | 32 +++---------- include/configs/MPC8349EMDS_SDRAM.h | 45 ++++--------------- include/configs/MPC8349ITX.h | 58 ++++++------------------ include/configs/MPC837XEMDS.h | 52 +++++---------------- include/configs/MPC837XERDB.h | 48 +++++--------------- include/configs/TQM834x.h | 19 ++------ include/configs/caddy2.h | 29 +++--------- include/configs/hrcon.h | 32 +++---------- include/configs/ids8313.h | 45 +++++-------------- include/configs/kmcoge5ne.h | 55 ++++++----------------- include/configs/kmeter1.h | 40 +++++------------ include/configs/kmopti2.h | 51 ++++++--------------- include/configs/kmsupx5.h | 43 +++++------------- include/configs/kmtegr1.h | 37 +++++---------- include/configs/kmtepr2.h | 57 ++++++----------------- include/configs/kmvect1.h | 46 +++++-------------- include/configs/mpc8308_p1m.h | 40 +++++------------ include/configs/sbc8349.h | 18 ++------ include/configs/strider.h | 31 +++---------- include/configs/suvd3.h | 46 +++++-------------- include/configs/tuge1.h | 43 +++++------------- include/configs/tuxx1.h | 60 ++++++------------------- include/configs/ve8313.h | 62 +++++-------------------- include/configs/vme8349.h | 29 +++--------- 30 files changed, 296 insertions(+), 1022 deletions(-) diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h index e19bcafd5c..185f6490d7 100644 --- a/include/configs/MPC8308RDB.h +++ b/include/configs/MPC8308RDB.h @@ -175,19 +175,9 @@ #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is 8M */ -/* Window base at flash base */ -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ - | BR_PS_16 /* 16 bit port */ \ - | BR_MS_GPCM /* MSEL = GPCM */ \ - | BR_V) /* valid */ -#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB \ - | OR_UPM_XAM \ - | OR_GPCM_CSNT \ - | OR_GPCM_ACS_DIV2 \ - | OR_GPCM_XACS \ - | OR_GPCM_SCY_15 \ - | OR_GPCM_TRLX_SET \ - | OR_GPCM_EHTR_SET) +/* FLASH */ +#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB | OR_UPM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ /* 127 64KB sectors and 8 8KB top sectors per device */ @@ -201,18 +191,9 @@ */ #define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */ #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) /* 0x00008000 */ -#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \ - | BR_DECC_CHK_GEN /* Use HW ECC */ \ - | BR_PS_8 /* 8 bit Port */ \ - | BR_MS_FCM /* MSEL = FCM */ \ - | BR_V) /* valid */ -#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \ - | OR_FCM_CSCT \ - | OR_FCM_CST \ - | OR_FCM_CHT \ - | OR_FCM_SCY_1 \ - | OR_FCM_TRLX \ - | OR_FCM_EHTR) +/* NAND */ +#define CONFIG_SYS_BR1_PRELIM (0xE0600000 | BR_DECC_CHK_GEN | BR_PS_8 | BR_MS_FCM | BR_V) +#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_FCM_CSCT | OR_FCM_CST | OR_FCM_CHT | OR_FCM_SCY_1 | OR_FCM_TRLX | OR_FCM_EHTR) /* 0xFFFF8396 */ #ifdef CONFIG_VSC7385_ENET @@ -220,18 +201,9 @@ /* VSC7385 Base address on CS2 */ #define CONFIG_SYS_VSC7385_BASE 0xF0000000 #define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */ -#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE \ - | BR_PS_8 /* 8-bit port */ \ - | BR_MS_GPCM /* MSEL = GPCM */ \ - | BR_V) /* valid */ - /* 0xF0000801 */ -#define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB \ - | OR_GPCM_CSNT \ - | OR_GPCM_XACS \ - | OR_GPCM_SCY_15 \ - | OR_GPCM_SETA \ - | OR_GPCM_TRLX_SET \ - | OR_GPCM_EHTR_SET) +/* VSC7385_BASE */ +#define CONFIG_SYS_BR2_PRELIM (0xF0000000 | BR_PS_8 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET) /* 0xFFFE09FF */ /* The flash address and size of the VSC7385 firmware image */ #define CONFIG_VSC7385_IMAGE 0xFE7FE000 diff --git a/include/configs/MPC8313ERDB_NAND.h b/include/configs/MPC8313ERDB_NAND.h index bbb9d4b936..40b0264dbe 100644 --- a/include/configs/MPC8313ERDB_NAND.h +++ b/include/configs/MPC8313ERDB_NAND.h @@ -170,17 +170,6 @@ #define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */ #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */ -#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE \ - | BR_PS_16 /* 16 bit port */ \ - | BR_MS_GPCM /* MSEL = GPCM */ \ - | BR_V) /* valid */ -#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ - | OR_GPCM_XACS \ - | OR_GPCM_SCY_9 \ - | OR_GPCM_EHTR \ - | OR_GPCM_EAD) - /* 0xFF006FF7 TODO SLOW 16 MB flash size */ - #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 135 /* sectors per device */ @@ -230,20 +219,13 @@ #define CONFIG_SYS_NAND_BLOCK_SIZE 16384 #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_NAND_BASE \ - | BR_DECC_CHK_GEN /* Use HW ECC */ \ - | BR_PS_8 /* 8 bit port */ \ - | BR_MS_FCM /* MSEL = FCM */ \ - | BR_V) /* valid */ -#define CONFIG_SYS_OR0_PRELIM \ - (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \ - | OR_FCM_CSCT \ - | OR_FCM_CST \ - | OR_FCM_CHT \ - | OR_FCM_SCY_1 \ - | OR_FCM_TRLX \ - | OR_FCM_EHTR) - /* 0xFFFF8396 */ +/* NAND */ +#define CONFIG_SYS_BR0_PRELIM (0xE2800000 | BR_DECC_CHK_GEN | BR_PS_8 | BR_MS_FCM | BR_V) +#define CONFIG_SYS_OR0_PRELIM (OR_AM_32KB | OR_FCM_CSCT | OR_FCM_CST | OR_FCM_CHT | OR_FCM_SCY_1 | OR_FCM_TRLX | OR_FCM_EHTR) + +/* FLASH */ +#define CONFIG_SYS_BR1_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR1_PRELIM (OR_AM_8MB | OR_GPCM_XACS | OR_GPCM_SCY_9 | OR_GPCM_EHTR_SET | OR_GPCM_EAD) /* Still needed for spl_minimal.c */ #define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR0_PRELIM @@ -253,20 +235,10 @@ #define CONFIG_SYS_BCSR_ADDR 0xFA000000 #define CONFIG_SYS_BCSR_SIZE (32 * 1024) /* 0x00008000 */ /* map at 0xFA000000 on LCS3 */ -#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_BCSR_ADDR \ - | BR_PS_8 /* 8 bit port */ \ - | BR_MS_GPCM /* MSEL = GPCM */ \ - | BR_V) /* valid */ - /* 0xFA000801 */ -#define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB \ - | OR_GPCM_CSNT \ - | OR_GPCM_ACS_DIV2 \ - | OR_GPCM_XACS \ - | OR_GPCM_SCY_15 \ - | OR_GPCM_TRLX_SET \ - | OR_GPCM_EHTR_SET \ - | OR_GPCM_EAD) - /* 0xFFFF8FF7 */ +/* BCSR */ +#define CONFIG_SYS_BR3_PRELIM (0xFA000000 | BR_PS_8 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) + /* Vitesse 7385 */ #ifdef CONFIG_VSC7385_ENET @@ -275,19 +247,10 @@ #define CONFIG_SYS_VSC7385_BASE 0xF0000000 #define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */ -#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE \ - | BR_PS_8 /* 8 bit port */ \ - | BR_MS_GPCM /* MSEL = GPCM */ \ - | BR_V) /* valid */ -#define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB \ - | OR_GPCM_CSNT \ - | OR_GPCM_XACS \ - | OR_GPCM_SCY_15 \ - | OR_GPCM_SETA \ - | OR_GPCM_TRLX_SET \ - | OR_GPCM_EHTR_SET \ - | OR_GPCM_EAD) - /* 0xFFFE09FF */ +/* VSC7385 */ +#define CONFIG_SYS_BR2_PRELIM (0xF0000000 | BR_PS_8 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) + #endif #define CONFIG_MPC83XX_GPIO 1 diff --git a/include/configs/MPC8313ERDB_NOR.h b/include/configs/MPC8313ERDB_NOR.h index 1cb001864a..390ee4eb26 100644 --- a/include/configs/MPC8313ERDB_NOR.h +++ b/include/configs/MPC8313ERDB_NOR.h @@ -143,17 +143,6 @@ #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */ -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ - | BR_PS_16 /* 16 bit port */ \ - | BR_MS_GPCM /* MSEL = GPCM */ \ - | BR_V) /* valid */ -#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ - | OR_GPCM_XACS \ - | OR_GPCM_SCY_9 \ - | OR_GPCM_EHTR \ - | OR_GPCM_EAD) - /* 0xFF006FF7 TODO SLOW 16 MB flash size */ - #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 135 /* sectors per device */ @@ -199,20 +188,13 @@ #define CONFIG_SYS_NAND_BLOCK_SIZE 16384 #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) -#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \ - | BR_DECC_CHK_GEN /* Use HW ECC */ \ - | BR_PS_8 /* 8 bit port */ \ - | BR_MS_FCM /* MSEL = FCM */ \ - | BR_V) /* valid */ -#define CONFIG_SYS_OR1_PRELIM \ - (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \ - | OR_FCM_CSCT \ - | OR_FCM_CST \ - | OR_FCM_CHT \ - | OR_FCM_SCY_1 \ - | OR_FCM_TRLX \ - | OR_FCM_EHTR) - /* 0xFFFF8396 */ +/* FLASH*/ +#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB | OR_GPCM_XACS | OR_GPCM_SCY_9 | OR_GPCM_EHTR_SET | OR_GPCM_EAD) + +/* NAND */ +#define CONFIG_SYS_BR1_PRELIM (0xE2800000 | BR_DECC_CHK_GEN | BR_PS_8 | BR_MS_FCM | BR_V) +#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_FCM_CSCT | OR_FCM_CST | OR_FCM_CHT | OR_FCM_SCY_1 | OR_FCM_TRLX | OR_FCM_EHTR) /* Still needed for spl_minimal.c */ #define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM @@ -222,20 +204,9 @@ #define CONFIG_SYS_BCSR_ADDR 0xFA000000 #define CONFIG_SYS_BCSR_SIZE (32 * 1024) /* 0x00008000 */ /* map at 0xFA000000 on LCS3 */ -#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_BCSR_ADDR \ - | BR_PS_8 /* 8 bit port */ \ - | BR_MS_GPCM /* MSEL = GPCM */ \ - | BR_V) /* valid */ - /* 0xFA000801 */ -#define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB \ - | OR_GPCM_CSNT \ - | OR_GPCM_ACS_DIV2 \ - | OR_GPCM_XACS \ - | OR_GPCM_SCY_15 \ - | OR_GPCM_TRLX_SET \ - | OR_GPCM_EHTR_SET \ - | OR_GPCM_EAD) - /* 0xFFFF8FF7 */ +/* BCSR */ +#define CONFIG_SYS_BR3_PRELIM (0xFA000000 | BR_PS_8 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) /* Vitesse 7385 */ #ifdef CONFIG_VSC7385_ENET @@ -244,19 +215,10 @@ #define CONFIG_SYS_VSC7385_BASE 0xF0000000 #define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */ -#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE \ - | BR_PS_8 /* 8 bit port */ \ - | BR_MS_GPCM /* MSEL = GPCM */ \ - | BR_V) /* valid */ -#define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB \ - | OR_GPCM_CSNT \ - | OR_GPCM_XACS \ - | OR_GPCM_SCY_15 \ - | OR_GPCM_SETA \ - | OR_GPCM_TRLX_SET \ - | OR_GPCM_EHTR_SET \ - | OR_GPCM_EAD) - /* 0xFFFE09FF */ +/* VSC7385 */ +#define CONFIG_SYS_BR2_PRELIM (0xF0000000 | BR_PS_8 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) + #endif #define CONFIG_MPC83XX_GPIO 1 diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index 86491b41d6..97b66415c9 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -177,33 +177,13 @@ #define CONFIG_SYS_NAND_U_BOOT_OFFS 16384 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000 -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ - | BR_PS_16 /* 16 bit port */ \ - | BR_MS_GPCM /* MSEL = GPCM */ \ - | BR_V) /* valid */ -#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB \ - | OR_UPM_XAM \ - | OR_GPCM_CSNT \ - | OR_GPCM_ACS_DIV2 \ - | OR_GPCM_XACS \ - | OR_GPCM_SCY_15 \ - | OR_GPCM_TRLX_SET \ - | OR_GPCM_EHTR_SET \ - | OR_GPCM_EAD) -#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \ - | BR_DECC_CHK_GEN /* Use HW ECC */ \ - | BR_PS_8 /* 8 bit port */ \ - | BR_MS_FCM /* MSEL = FCM */ \ - | BR_V) /* valid */ -#define CONFIG_SYS_OR1_PRELIM \ - (OR_AM_32KB \ - | OR_FCM_CSCT \ - | OR_FCM_CST \ - | OR_FCM_CHT \ - | OR_FCM_SCY_1 \ - | OR_FCM_TRLX \ - | OR_FCM_EHTR) - /* 0xFFFF8396 */ +/* FLASH */ +#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB | OR_UPM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) + +/* NAND */ +#define CONFIG_SYS_BR1_PRELIM (0xE0600000 | BR_DECC_CHK_GEN | BR_PS_8 | BR_MS_FCM | BR_V) +#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_FCM_CSCT | OR_FCM_CST | OR_FCM_CHT | OR_FCM_SCY_1 | OR_FCM_TRLX | OR_FCM_EHTR) /* Still needed for spl_minimal.c */ #define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index 30f1e4453d..fd884a1e65 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -142,20 +142,9 @@ #define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size is 16M */ -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ - | BR_PS_16 /* 16 bit port */ \ - | BR_MS_GPCM /* MSEL = GPCM */ \ - | BR_V) /* valid */ -#define CONFIG_SYS_OR0_PRELIM (OR_AM_16MB \ - | OR_GPCM_XAM \ - | OR_GPCM_CSNT \ - | OR_GPCM_ACS_DIV2 \ - | OR_GPCM_XACS \ - | OR_GPCM_SCY_15 \ - | OR_GPCM_TRLX_SET \ - | OR_GPCM_EHTR_SET \ - | OR_GPCM_EAD) - /* 0xFE006FF7 */ +/* FLASH */ +#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR0_PRELIM (OR_AM_16MB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index 3a8a3e4fb8..41b0223135 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -133,20 +133,9 @@ #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ #define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size is 16M */ -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ - | BR_PS_16 /* 16 bit port */ \ - | BR_MS_GPCM /* MSEL = GPCM */ \ - | BR_V) /* valid */ -#define CONFIG_SYS_OR0_PRELIM (OR_AM_16MB \ - | OR_GPCM_XAM \ - | OR_GPCM_CSNT \ - | OR_GPCM_ACS_DIV2 \ - | OR_GPCM_XACS \ - | OR_GPCM_SCY_15 \ - | OR_GPCM_TRLX_SET \ - | OR_GPCM_EHTR_SET \ - | OR_GPCM_EAD) - /* 0xfe006ff7 */ +/* FLASH */ +#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR0_PRELIM (OR_AM_16MB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ @@ -159,19 +148,9 @@ #define CONFIG_SYS_BCSR 0xF8000000 /* Access window base at BCSR base */ -#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \ - | BR_PS_8 \ - | BR_MS_GPCM \ - | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \ - | OR_GPCM_XAM \ - | OR_GPCM_CSNT \ - | OR_GPCM_XACS \ - | OR_GPCM_SCY_15 \ - | OR_GPCM_TRLX_SET \ - | OR_GPCM_EHTR_SET \ - | OR_GPCM_EAD) - /* 0xFFFFE9F7 */ +/* BCSR */ +#define CONFIG_SYS_BR1_PRELIM (0xF8000000 | BR_PS_8 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) /* * Windows to access PIB via local bus @@ -183,39 +162,18 @@ /* * CS2 on Local Bus, to PIB */ -#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_PIB_BASE \ - | BR_PS_8 \ - | BR_MS_GPCM \ - | BR_V) - /* 0xF8008801 */ -#define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB \ - | OR_GPCM_XAM \ - | OR_GPCM_CSNT \ - | OR_GPCM_XACS \ - | OR_GPCM_SCY_15 \ - | OR_GPCM_TRLX_SET \ - | OR_GPCM_EHTR_SET \ - | OR_GPCM_EAD) - /* 0xffffe9f7 */ + +/* PIB1 */ +#define CONFIG_SYS_BR2_PRELIM (0xF8008000 | BR_PS_8 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) /* * CS3 on Local Bus, to PIB */ -#define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_PIB_BASE + \ - CONFIG_SYS_PIB_WINDOW_SIZE) \ - | BR_PS_8 \ - | BR_MS_GPCM \ - | BR_V) - /* 0xF8010801 */ -#define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB \ - | OR_GPCM_XAM \ - | OR_GPCM_CSNT \ - | OR_GPCM_XACS \ - | OR_GPCM_SCY_15 \ - | OR_GPCM_TRLX_SET \ - | OR_GPCM_EHTR_SET \ - | OR_GPCM_EAD) - /* 0xffffe9f7 */ + +/* PIB2 */ +#define CONFIG_SYS_BR3_PRELIM (0xF8010000 | BR_PS_8 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) /* * Serial Port diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index fa73b81c3a..4cda1589b6 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -123,19 +123,9 @@ #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ #define CONFIG_SYS_FLASH_SIZE 32 /* max flash size in MB */ -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ - | BR_PS_16 /* 16 bit port */ \ - | BR_MS_GPCM /* MSEL = GPCM */ \ - | BR_V) /* valid */ -#define CONFIG_SYS_OR0_PRELIM (OR_AM_32MB \ - | OR_UPM_XAM \ - | OR_GPCM_CSNT \ - | OR_GPCM_ACS_DIV2 \ - | OR_GPCM_XACS \ - | OR_GPCM_SCY_15 \ - | OR_GPCM_TRLX_SET \ - | OR_GPCM_EHTR_SET \ - | OR_GPCM_EAD) +/* FLASH */ +#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR0_PRELIM (OR_AM_32MB | OR_UPM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ @@ -157,18 +147,10 @@ */ #define CONFIG_SYS_BCSR 0xE2400000 /* Access window base at BCSR base */ -#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \ - | BR_PS_8 \ - | BR_MS_GPCM \ - | BR_V) - /* 0x00000801 */ -#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \ - | OR_GPCM_XAM \ - | OR_GPCM_CSNT \ - | OR_GPCM_SCY_15 \ - | OR_GPCM_TRLX_CLEAR \ - | OR_GPCM_EHTR_CLEAR) - /* 0xFFFFE8F0 */ + +/* BCSR */ +#define CONFIG_SYS_BR1_PRELIM (0xE2400000 | BR_PS_8 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_SCY_15 | OR_GPCM_TRLX_CLEAR | OR_GPCM_EHTR_CLEAR) #define CONFIG_SYS_INIT_RAM_LOCK 1 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */ diff --git a/include/configs/MPC8349EMDS_SDRAM.h b/include/configs/MPC8349EMDS_SDRAM.h index 218c4b1fc9..7f906c38d8 100644 --- a/include/configs/MPC8349EMDS_SDRAM.h +++ b/include/configs/MPC8349EMDS_SDRAM.h @@ -123,19 +123,9 @@ #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ #define CONFIG_SYS_FLASH_SIZE 32 /* max flash size in MB */ -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ - | BR_PS_16 /* 16 bit port */ \ - | BR_MS_GPCM /* MSEL = GPCM */ \ - | BR_V) /* valid */ -#define CONFIG_SYS_OR0_PRELIM (OR_AM_32MB \ - | OR_UPM_XAM \ - | OR_GPCM_CSNT \ - | OR_GPCM_ACS_DIV2 \ - | OR_GPCM_XACS \ - | OR_GPCM_SCY_15 \ - | OR_GPCM_TRLX_SET \ - | OR_GPCM_EHTR_SET \ - | OR_GPCM_EAD) +/* FLASH */ +#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR0_PRELIM (OR_AM_32MB | OR_UPM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ @@ -157,18 +147,9 @@ */ #define CONFIG_SYS_BCSR 0xE2400000 /* Access window base at BCSR base */ -#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \ - | BR_PS_8 \ - | BR_MS_GPCM \ - | BR_V) - /* 0x00000801 */ -#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \ - | OR_GPCM_XAM \ - | OR_GPCM_CSNT \ - | OR_GPCM_SCY_15 \ - | OR_GPCM_TRLX_CLEAR \ - | OR_GPCM_EHTR_CLEAR) - /* 0xFFFFE8F0 */ +/* BCSR */ +#define CONFIG_SYS_BR1_PRELIM (0xE2400000 | BR_PS_8 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_SCY_15 | OR_GPCM_TRLX_CLEAR | OR_GPCM_EHTR_CLEAR) #define CONFIG_SYS_INIT_RAM_LOCK 1 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */ @@ -211,11 +192,9 @@ * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861 */ -#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LBC_SDRAM_BASE \ - | BR_PS_32 /* 32-bit port */ \ - | BR_MS_SDRAM /* MSEL = SDRAM */ \ - | BR_V) /* Valid */ - /* 0xF0001861 */ +/* SDRAM */ +#define CONFIG_SYS_BR2_PRELIM (0xF0000000 | BR_PS_32 | BR_MS_SDRAM | BR_V) +#define CONFIG_SYS_OR2_PRELIM (OR_AM_64MB | OR_SDRAM_XAM | ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) | ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) | OR_SDRAM_EAD) /* * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. @@ -231,12 +210,6 @@ * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901 */ -#define CONFIG_SYS_OR2_PRELIM (OR_AM_64MB \ - | OR_SDRAM_XAM \ - | ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \ - | ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \ - | OR_SDRAM_EAD) - /* 0xFC006901 */ /* LB sdram refresh timer, about 6us */ #define CONFIG_SYS_LBC_LSRT 0x32000000 diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index 0bf179a70b..e90d497f5e 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -211,56 +211,28 @@ boards, we say we have two, but don't display a message if we find only one. */ * BRx, ORx, LBLAWBARx, and LBLAWARx */ -/* Flash */ +/* FLASH */ +#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR0_PRELIM (OR_AM_16MB | OR_UPM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ - | BR_PS_16 \ - | BR_MS_GPCM \ - | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_16MB \ - | OR_UPM_XAM \ - | OR_GPCM_CSNT \ - | OR_GPCM_ACS_DIV2 \ - | OR_GPCM_XACS \ - | OR_GPCM_SCY_15 \ - | OR_GPCM_TRLX_SET \ - | OR_GPCM_EHTR_SET \ - | OR_GPCM_EAD) /* Vitesse 7385 */ #define CONFIG_SYS_VSC7385_BASE 0xF8000000 #ifdef CONFIG_VSC7385_ENET -#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_VSC7385_BASE \ - | BR_PS_8 \ - | BR_MS_GPCM \ - | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_128KB \ - | OR_GPCM_CSNT \ - | OR_GPCM_XACS \ - | OR_GPCM_SCY_15 \ - | OR_GPCM_SETA \ - | OR_GPCM_TRLX_SET \ - | OR_GPCM_EHTR_SET \ - | OR_GPCM_EAD) +/* VSC7385 */ +#define CONFIG_SYS_BR1_PRELIM (0xF8000000 | BR_PS_8 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR1_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) + #endif -/* LED */ #define CONFIG_SYS_LED_BASE 0xF9000000 -#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LED_BASE \ - | BR_PS_8 \ - | BR_MS_GPCM \ - | BR_V) -#define CONFIG_SYS_OR2_PRELIM (OR_AM_2MB \ - | OR_GPCM_CSNT \ - | OR_GPCM_ACS_DIV2 \ - | OR_GPCM_XACS \ - | OR_GPCM_SCY_9 \ - | OR_GPCM_TRLX_SET \ - | OR_GPCM_EHTR_SET \ - | OR_GPCM_EAD) + +/* LED */ +#define CONFIG_SYS_BR2_PRELIM (0xF9000000 | BR_PS_8 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR2_PRELIM (OR_AM_2MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_9 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) /* Compact Flash */ @@ -268,11 +240,9 @@ boards, we say we have two, but don't display a message if we find only one. */ #define CONFIG_SYS_CF_BASE 0xF0000000 -#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_CF_BASE \ - | BR_PS_16 \ - | BR_MS_UPMA \ - | BR_V) -#define CONFIG_SYS_OR3_PRELIM (OR_UPM_AM | OR_UPM_BI) +/* CF */ +#define CONFIG_SYS_BR3_PRELIM (0xF0000000 | BR_PS_16 | BR_MS_UPMA | BR_V) +#define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB | OR_UPM_BI) #endif diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index e10c58d7ed..e569e63741 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -162,20 +162,9 @@ #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ #define CONFIG_SYS_FLASH_SIZE 32 /* max FLASH size is 32M */ -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ - | BR_PS_16 /* 16 bit port */ \ - | BR_MS_GPCM /* MSEL = GPCM */ \ - | BR_V) /* valid */ -#define CONFIG_SYS_OR0_PRELIM (OR_AM_32MB \ - | OR_UPM_XAM \ - | OR_GPCM_CSNT \ - | OR_GPCM_ACS_DIV2 \ - | OR_GPCM_XACS \ - | OR_GPCM_SCY_15 \ - | OR_GPCM_TRLX_SET \ - | OR_GPCM_EHTR_SET \ - | OR_GPCM_EAD) - /* 0xFE000FF7 */ +/* FLASH */ +#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR0_PRELIM (OR_AM_32MB | OR_UPM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ @@ -189,20 +178,9 @@ */ #define CONFIG_SYS_BCSR 0xF8000000 /* Access window base at BCSR base */ -#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \ - | BR_PS_8 \ - | BR_MS_GPCM \ - | BR_V) - /* 0xF8000801 */ -#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \ - | OR_GPCM_XAM \ - | OR_GPCM_CSNT \ - | OR_GPCM_XACS \ - | OR_GPCM_SCY_15 \ - | OR_GPCM_TRLX_SET \ - | OR_GPCM_EHTR_SET \ - | OR_GPCM_EAD) - /* 0xFFFFE9F7 */ +/* BCSR */ +#define CONFIG_SYS_BR1_PRELIM (0xF8000000 | BR_PS_8 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) /* * NAND Flash on the Local Bus @@ -211,20 +189,10 @@ #define CONFIG_NAND_FSL_ELBC 1 #define CONFIG_SYS_NAND_BASE 0xE0600000 -#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE \ - | BR_DECC_CHK_GEN /* Use HW ECC */ \ - | BR_PS_8 /* 8 bit port */ \ - | BR_MS_FCM /* MSEL = FCM */ \ - | BR_V) /* valid */ -#define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB \ - | OR_FCM_BCTLD \ - | OR_FCM_CST \ - | OR_FCM_CHT \ - | OR_FCM_SCY_1 \ - | OR_FCM_RST \ - | OR_FCM_TRLX \ - | OR_FCM_EHTR) - /* 0xFFFF919E */ + +/* NAND */ +#define CONFIG_SYS_BR3_PRELIM (0xE0600000 | BR_DECC_CHK_GEN | BR_PS_8 | BR_MS_FCM | BR_V) +#define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB | OR_FCM_BCTLD | OR_FCM_CST | OR_FCM_CHT | OR_FCM_SCY_1 | OR_FCM_RST | OR_FCM_TRLX | OR_FCM_EHTR) /* * Serial Port diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index 1e45b5ee3f..c1898a53a6 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -188,16 +188,9 @@ #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */ -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ - | BR_PS_16 /* 16 bit port */ \ - | BR_MS_GPCM /* MSEL = GPCM */ \ - | BR_V) /* valid */ -#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB \ - | OR_GPCM_XACS \ - | OR_GPCM_SCY_9 \ - | OR_GPCM_EHTR_SET \ - | OR_GPCM_EAD) - /* 0xFF800191 */ +/* FLASH */ +#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB | OR_GPCM_XACS | OR_GPCM_SCY_9 | OR_GPCM_EHTR_SET | OR_GPCM_EAD) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ @@ -210,38 +203,21 @@ * NAND Flash on the Local Bus */ #define CONFIG_SYS_NAND_BASE 0xE0600000 -#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \ - | BR_DECC_CHK_GEN /* Use HW ECC */ \ - | BR_PS_8 /* 8 bit port */ \ - | BR_MS_FCM /* MSEL = FCM */ \ - | BR_V) /* valid */ -#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \ - | OR_FCM_CSCT \ - | OR_FCM_CST \ - | OR_FCM_CHT \ - | OR_FCM_SCY_1 \ - | OR_FCM_TRLX \ - | OR_FCM_EHTR) + +/* NAND */ +#define CONFIG_SYS_BR1_PRELIM (0xE0600000 | BR_DECC_CHK_GEN | BR_PS_8 | BR_MS_FCM | BR_V) +#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_FCM_CSCT | OR_FCM_CST | OR_FCM_CHT | OR_FCM_SCY_1 | OR_FCM_TRLX | OR_FCM_EHTR) + /* Vitesse 7385 */ #define CONFIG_SYS_VSC7385_BASE 0xF0000000 #ifdef CONFIG_VSC7385_ENET -#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE \ - | BR_PS_8 \ - | BR_MS_GPCM \ - | BR_V) - /* 0xF0000801 */ -#define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB \ - | OR_GPCM_CSNT \ - | OR_GPCM_XACS \ - | OR_GPCM_SCY_15 \ - | OR_GPCM_SETA \ - | OR_GPCM_TRLX_SET \ - | OR_GPCM_EHTR_SET \ - | OR_GPCM_EAD) - /* 0xfffe09ff */ +/* VSC7385 */ +#define CONFIG_SYS_BR2_PRELIM (0xF0000000 | BR_PS_8 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) + #endif /* diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index 4479000d25..c76df2847d 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -76,22 +76,9 @@ #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors per device */ -/* 32 bit device at 0x80000000 via GPCM (0x8000_1801) */ -#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BR_BA) \ - | BR_MS_GPCM \ - | BR_PS_32 \ - | BR_V) - -/* FLASH timing (0x0000_0c54) */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_GPCM_CSNT \ - | OR_GPCM_ACS_DIV4 \ - | OR_GPCM_SCY_5 \ - | OR_GPCM_TRLX) - -#define CONFIG_SYS_PRELIM_OR_AM OR_AM_1GB /* OR addr mask: 1 GiB */ - -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM \ - | CONFIG_SYS_OR_TIMING_FLASH) +/* FLASH */ +#define CONFIG_SYS_BR0_PRELIM (0x80000000 | BR_MS_GPCM | BR_PS_32 | BR_V) +#define CONFIG_SYS_OR0_PRELIM (OR_AM_1GB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET) /* disable remaining mappings */ #define CONFIG_SYS_BR1_PRELIM 0x00000000 diff --git a/include/configs/caddy2.h b/include/configs/caddy2.h index ffd52a200a..a7eb5f5295 100644 --- a/include/configs/caddy2.h +++ b/include/configs/caddy2.h @@ -69,31 +69,16 @@ */ #define CONFIG_SYS_FLASH_BASE 0xffc00000 /* start of FLASH */ #define CONFIG_SYS_FLASH_SIZE 4 /* flash size in MB */ -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ - BR_PS_16 | /* 16bit */ \ - BR_MS_GPCM | /* MSEL = GPCM */ \ - BR_V) /* valid */ -#define CONFIG_SYS_OR0_PRELIM (OR_AM_4MB \ - | OR_GPCM_XAM \ - | OR_GPCM_CSNT \ - | OR_GPCM_ACS_DIV2 \ - | OR_GPCM_XACS \ - | OR_GPCM_SCY_15 \ - | OR_GPCM_TRLX_SET \ - | OR_GPCM_EHTR_SET \ - | OR_GPCM_EAD) - /* 0xffc06ff7 */ +/* FLASH */ +#define CONFIG_SYS_BR0_PRELIM (0xFFC00000 | BR_PS_16 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR0_PRELIM (OR_AM_4MB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) #define CONFIG_SYS_WINDOW1_BASE 0xf0000000 -#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_WINDOW1_BASE \ - | BR_PS_32 \ - | BR_MS_GPCM \ - | BR_V) - /* 0xF0001801 */ -#define CONFIG_SYS_OR1_PRELIM (OR_AM_256KB \ - | OR_GPCM_SETA) - /* 0xfffc0208 */ + +/* WINDOW1 */ +#define CONFIG_SYS_BR1_PRELIM (0xF0000000 | BR_PS_32 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR1_PRELIM (OR_AM_256KB | OR_GPCM_SETA) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device*/ diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h index 4193ceb379..3fe72db188 100644 --- a/include/configs/hrcon.h +++ b/include/configs/hrcon.h @@ -169,19 +169,9 @@ #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */ -/* Window base at flash base */ -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ - | BR_PS_16 /* 16 bit port */ \ - | BR_MS_GPCM /* MSEL = GPCM */ \ - | BR_V) /* valid */ -#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB \ - | OR_UPM_XAM \ - | OR_GPCM_CSNT \ - | OR_GPCM_ACS_DIV2 \ - | OR_GPCM_XACS \ - | OR_GPCM_SCY_15 \ - | OR_GPCM_TRLX_SET \ - | OR_GPCM_EHTR_SET) +/* FLASH */ +#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB | OR_UPM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 135 @@ -195,19 +185,9 @@ #define CONFIG_SYS_FPGA0_BASE 0xE0600000 #define CONFIG_SYS_FPGA0_SIZE 1 /* FPGA size is 1M */ -/* Window base at FPGA base */ -#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FPGA0_BASE \ - | BR_PS_16 /* 16 bit port */ \ - | BR_MS_GPCM /* MSEL = GPCM */ \ - | BR_V) /* valid */ -#define CONFIG_SYS_OR1_PRELIM (OR_AM_1MB \ - | OR_UPM_XAM \ - | OR_GPCM_CSNT \ - | OR_GPCM_ACS_DIV2 \ - | OR_GPCM_XACS \ - | OR_GPCM_SCY_15 \ - | OR_GPCM_TRLX_SET \ - | OR_GPCM_EHTR_SET) +/* FPGA */ +#define CONFIG_SYS_BR1_PRELIM (0xE0600000 | BR_PS_16 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR1_PRELIM (OR_AM_1MB | OR_UPM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET) #define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE #define CONFIG_SYS_FPGA_DONE(k) 0x0010 diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h index 871b91f218..61f64ebbbc 100644 --- a/include/configs/ids8313.h +++ b/include/configs/ids8313.h @@ -142,17 +142,10 @@ #define CONFIG_SYS_FLASH_BASE 0xFF800000 #define CONFIG_SYS_FLASH_SIZE 8 -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE |\ - BR_PS_8 |\ - BR_MS_GPCM |\ - BR_V) +/* FLASH */ +#define CONFIG_SYS_BR0_PRELIM (0xFF800000 | BR_PS_8 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB | OR_GPCM_SCY_10 | OR_GPCM_EHTR_SET | OR_GPCM_TRLX_SET | OR_GPCM_CSNT | OR_GPCM_EAD) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB |\ - OR_GPCM_SCY_10 |\ - OR_GPCM_EHTR |\ - OR_GPCM_TRLX |\ - OR_GPCM_CSNT |\ - OR_GPCM_EAD) #define CONFIG_SYS_MAX_FLASH_BANKS 1 #define CONFIG_SYS_MAX_FLASH_SECT 128 @@ -170,21 +163,9 @@ #define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10) #define NAND_CACHE_PAGES 64 -#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_NAND_BASE) |\ - BR_DECC_CHK_GEN |\ - BR_PS_8 |\ - BR_MS_FCM |\ - BR_V) - -#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB |\ - OR_FCM_PGS |\ - OR_FCM_CSCT |\ - OR_FCM_CST |\ - OR_FCM_CHT |\ - OR_FCM_SCY_4 |\ - OR_FCM_TRLX |\ - OR_FCM_EHTR |\ - OR_FCM_RST) +/* NAND */ +#define CONFIG_SYS_BR1_PRELIM (0xE1000000 | BR_DECC_CHK_GEN | BR_PS_8 | BR_MS_FCM | BR_V) +#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_FCM_PGS | OR_FCM_CSCT | OR_FCM_CST | OR_FCM_CHT | OR_FCM_SCY_4 | OR_FCM_TRLX | OR_FCM_EHTR | OR_FCM_RST) /* * MRAM setup @@ -194,11 +175,8 @@ #define CONFIG_SYS_OR_TIMING_MRAM -#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_MRAM_BASE |\ - BR_PS_8 |\ - BR_MS_GPCM |\ - BR_V) - +/* MRAM */ +#define CONFIG_SYS_BR2_PRELIM (0xE2000000 | BR_PS_8 | BR_MS_GPCM | BR_V) #define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_7 | OR_GPCM_TRLX_SET) /* @@ -209,11 +187,8 @@ #define CONFIG_SYS_OR_TIMING_MRAM -#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_CPLD_BASE |\ - BR_PS_8 |\ - BR_MS_GPCM |\ - BR_V) - +/* CPLD */ +#define CONFIG_SYS_BR3_PRELIM (0xE3000000 | BR_PS_8 | BR_MS_GPCM | BR_V) #define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB | OR_GPCM_CSNT | OR_GPCM_SCY_1 | OR_GPCM_TRLX_SET) /* diff --git a/include/configs/kmcoge5ne.h b/include/configs/kmcoge5ne.h index 370e6b496a..5027073d6e 100644 --- a/include/configs/kmcoge5ne.h +++ b/include/configs/kmcoge5ne.h @@ -108,15 +108,9 @@ */ #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ - BR_PS_16 | /* 16 bit port size */ \ - BR_MS_GPCM | /* MSEL = GPCM */ \ - BR_V) - -#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | \ - OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ - OR_GPCM_SCY_5 | \ - OR_GPCM_TRLX_SET | OR_GPCM_EAD) +/* FLASH */ +#define CONFIG_SYS_BR0_PRELIM (0xF0000000 | BR_PS_16 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ @@ -125,15 +119,10 @@ /* * PRIO1/PIGGY on the local bus CS1 */ -/* Window base at flash base */ -#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_KMBEC_FPGA_BASE | \ - BR_PS_8 | /* 8 bit port size */ \ - BR_MS_GPCM | /* MSEL = GPCM */ \ - BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_64MB | \ - OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ - OR_GPCM_SCY_2 | \ - OR_GPCM_TRLX_SET | OR_GPCM_EAD) + +/* KMBEC_FPGA */ +#define CONFIG_SYS_BR1_PRELIM (0xE8000000 | BR_PS_8 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR1_PRELIM (OR_AM_64MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) /* * Serial Port @@ -347,18 +336,9 @@ #define CONFIG_SYS_PAXE_BASE 0xA0000000 #define CONFIG_SYS_PAXE_SIZE 256 -#define CONFIG_SYS_BR3_PRELIM (\ - CONFIG_SYS_PAXE_BASE | \ - BR_PS_8 | \ - BR_V) - -#define CONFIG_SYS_OR3_PRELIM (\ - OR_AM_256MB | \ - OR_GPCM_CSNT | \ - OR_GPCM_ACS_DIV2 | \ - OR_GPCM_SCY_2 | \ - OR_GPCM_TRLX | \ - OR_GPCM_EAD) +/* PAXE */ +#define CONFIG_SYS_BR3_PRELIM (0xA0000000 | BR_PS_8 | BR_V) +#define CONFIG_SYS_OR3_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) /* * BFTIC3 on the local bus CS4 @@ -366,18 +346,9 @@ #define CONFIG_SYS_BFTIC3_BASE 0xB0000000 #define CONFIG_SYS_BFTIC3_SIZE 256 -#define CONFIG_SYS_BR4_PRELIM (\ - CONFIG_SYS_BFTIC3_BASE |\ - BR_PS_8 | \ - BR_V) - -#define CONFIG_SYS_OR4_PRELIM (\ - OR_AM_256MB|\ - OR_GPCM_CSNT | \ - OR_GPCM_ACS_DIV2 |\ - OR_GPCM_SCY_2 |\ - OR_GPCM_TRLX |\ - OR_GPCM_EAD) +/* BFTIC3 */ +#define CONFIG_SYS_BR4_PRELIM (0xB0000000 | BR_PS_8 | BR_V) +#define CONFIG_SYS_OR4_PRELIM (OR_AM_256MB| OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) /* enable POST tests */ #define CONFIG_POST (CONFIG_SYS_POST_MEMORY|CONFIG_SYS_POST_MEM_REGIONS) diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h index 2650544305..84516bb9bb 100644 --- a/include/configs/kmeter1.h +++ b/include/configs/kmeter1.h @@ -93,15 +93,9 @@ */ #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ - BR_PS_16 | /* 16 bit port size */ \ - BR_MS_GPCM | /* MSEL = GPCM */ \ - BR_V) - -#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | \ - OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ - OR_GPCM_SCY_5 | \ - OR_GPCM_TRLX_SET | OR_GPCM_EAD) +/* FLASH */ +#define CONFIG_SYS_BR0_PRELIM (0xF0000000 | BR_PS_16 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ @@ -110,15 +104,10 @@ /* * PRIO1/PIGGY on the local bus CS1 */ -/* Window base at flash base */ -#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_KMBEC_FPGA_BASE | \ - BR_PS_8 | /* 8 bit port size */ \ - BR_MS_GPCM | /* MSEL = GPCM */ \ - BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_64MB | \ - OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ - OR_GPCM_SCY_2 | \ - OR_GPCM_TRLX_SET | OR_GPCM_EAD) + +/* KMBEC_FPGA */ +#define CONFIG_SYS_BR1_PRELIM (0xE8000000 | BR_PS_8 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR1_PRELIM (OR_AM_64MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) /* * Serial Port @@ -327,17 +316,8 @@ #define CONFIG_SYS_PAXE_BASE 0xA0000000 #define CONFIG_SYS_PAXE_SIZE 256 -#define CONFIG_SYS_BR3_PRELIM (\ - CONFIG_SYS_PAXE_BASE | \ - BR_PS_8 | \ - BR_V) - -#define CONFIG_SYS_OR3_PRELIM (\ - OR_AM_256MB | \ - OR_GPCM_CSNT | \ - OR_GPCM_ACS_DIV2 | \ - OR_GPCM_SCY_2 | \ - OR_GPCM_TRLX | \ - OR_GPCM_EAD) +/* PAXE */ +#define CONFIG_SYS_BR3_PRELIM (0xA0000000 | BR_PS_8 | BR_V) +#define CONFIG_SYS_OR3_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) #endif /* CONFIG */ diff --git a/include/configs/kmopti2.h b/include/configs/kmopti2.h index 6e59fde6bd..678cb6a7cc 100644 --- a/include/configs/kmopti2.h +++ b/include/configs/kmopti2.h @@ -113,15 +113,9 @@ */ #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ - BR_PS_16 | /* 16 bit port size */ \ - BR_MS_GPCM | /* MSEL = GPCM */ \ - BR_V) - -#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | \ - OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ - OR_GPCM_SCY_5 | \ - OR_GPCM_TRLX_SET | OR_GPCM_EAD) +/* FLASH */ +#define CONFIG_SYS_BR0_PRELIM (0xF0000000 | BR_PS_16 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ @@ -130,15 +124,10 @@ /* * PRIO1/PIGGY on the local bus CS1 */ -/* Window base at flash base */ -#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_KMBEC_FPGA_BASE | \ - BR_PS_8 | /* 8 bit port size */ \ - BR_MS_GPCM | /* MSEL = GPCM */ \ - BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_128MB | \ - OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ - OR_GPCM_SCY_2 | \ - OR_GPCM_TRLX_SET | OR_GPCM_EAD) + +/* KMBEC_FPGA */ +#define CONFIG_SYS_BR1_PRELIM (0xE8000000 | BR_PS_8 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR1_PRELIM (OR_AM_128MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) /* * Serial Port @@ -361,29 +350,17 @@ /* * Configuration for C2 on the local bus */ -#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_APP1_BASE | \ - BR_PS_8 | \ - BR_MS_GPCM | \ - BR_V) -#define CONFIG_SYS_OR2_PRELIM (OR_AM_256MB | \ - OR_GPCM_CSNT | \ - OR_GPCM_ACS_DIV4 | \ - OR_GPCM_SCY_2 | \ - OR_GPCM_TRLX_SET | \ - OR_GPCM_EHTR_CLEAR | \ - OR_GPCM_EAD) +/* APP1 */ +#define CONFIG_SYS_BR2_PRELIM (0xA0000000 | BR_PS_8 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR2_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_CLEAR | OR_GPCM_EAD) /* * Configuration for C3 on the local bus */ -#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_APP2_BASE | \ - BR_PS_16 | \ - BR_MS_GPCM | \ - BR_V) -#define CONFIG_SYS_OR3_PRELIM (OR_AM_256MB | \ - OR_GPCM_SCY_4 | \ - OR_GPCM_TRLX_CLEAR | \ - OR_GPCM_EHTR_CLEAR) + +/* APP2 */ +#define CONFIG_SYS_BR3_PRELIM (0xB0000000 | BR_PS_16 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR3_PRELIM (OR_AM_256MB | OR_GPCM_SCY_4 | OR_GPCM_TRLX_CLEAR | OR_GPCM_EHTR_CLEAR) #endif /* __CONFIG_H */ diff --git a/include/configs/kmsupx5.h b/include/configs/kmsupx5.h index af39e8bb85..3e2e425c34 100644 --- a/include/configs/kmsupx5.h +++ b/include/configs/kmsupx5.h @@ -113,15 +113,9 @@ */ #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ - BR_PS_16 | /* 16 bit port size */ \ - BR_MS_GPCM | /* MSEL = GPCM */ \ - BR_V) - -#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | \ - OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ - OR_GPCM_SCY_5 | \ - OR_GPCM_TRLX_SET | OR_GPCM_EAD) +/* FLASH */ +#define CONFIG_SYS_BR0_PRELIM (0xF0000000 | BR_PS_16 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ @@ -130,15 +124,10 @@ /* * PRIO1/PIGGY on the local bus CS1 */ -/* Window base at flash base */ -#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_KMBEC_FPGA_BASE | \ - BR_PS_8 | /* 8 bit port size */ \ - BR_MS_GPCM | /* MSEL = GPCM */ \ - BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_128MB | \ - OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ - OR_GPCM_SCY_2 | \ - OR_GPCM_TRLX_SET | OR_GPCM_EAD) + +/* KMBEC_FPGA */ +#define CONFIG_SYS_BR1_PRELIM (0xE8000000 | BR_PS_8 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR1_PRELIM (OR_AM_128MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) /* * Serial Port @@ -356,20 +345,8 @@ * 3 Local GPCM 8 bit 256MB TEP2 (16 bit) */ -/* - * Configuration for C2 on the local bus - */ -#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_APP1_BASE | \ - BR_PS_8 | \ - BR_MS_GPCM | \ - BR_V) - -#define CONFIG_SYS_OR2_PRELIM (OR_AM_256MB | \ - OR_GPCM_CSNT | \ - OR_GPCM_ACS_DIV4 | \ - OR_GPCM_SCY_2 | \ - OR_GPCM_TRLX_SET | \ - OR_GPCM_EHTR_CLEAR | \ - OR_GPCM_EAD) +/* APP1 */ +#define CONFIG_SYS_BR2_PRELIM (0xA0000000 | BR_PS_8 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR2_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_CLEAR | OR_GPCM_EAD) #endif /* __CONFIG_H */ diff --git a/include/configs/kmtegr1.h b/include/configs/kmtegr1.h index 1312aa2fa9..ed221e2301 100644 --- a/include/configs/kmtegr1.h +++ b/include/configs/kmtegr1.h @@ -120,15 +120,9 @@ */ #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ - BR_PS_16 | /* 16 bit port size */ \ - BR_MS_GPCM | /* MSEL = GPCM */ \ - BR_V) - -#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | \ - OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ - OR_GPCM_SCY_5 | \ - OR_GPCM_TRLX_SET | OR_GPCM_EAD) +/* FLASH */ +#define CONFIG_SYS_BR0_PRELIM (0xF0000000 | BR_PS_16 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ @@ -137,15 +131,10 @@ /* * PRIO1/PIGGY on the local bus CS1 */ -/* Window base at flash base */ -#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_KMBEC_FPGA_BASE | \ - BR_PS_8 | /* 8 bit port size */ \ - BR_MS_GPCM | /* MSEL = GPCM */ \ - BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_128MB | \ - OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ - OR_GPCM_SCY_2 | \ - OR_GPCM_TRLX_SET | OR_GPCM_EAD) + +/* KMBEC_FPGA */ +#define CONFIG_SYS_BR1_PRELIM (0xE8000000 | BR_PS_8 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR1_PRELIM (OR_AM_128MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) /* * Serial Port @@ -411,15 +400,9 @@ * */ -#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_APP2_BASE | \ - BR_PS_16 | \ - BR_MS_GPCM | \ - BR_V) - -#define CONFIG_SYS_OR3_PRELIM (OR_AM_256MB | \ - OR_GPCM_SCY_5 | \ - OR_GPCM_TRLX_CLEAR | \ - OR_GPCM_EHTR_CLEAR) +/* APP2 */ +#define CONFIG_SYS_BR3_PRELIM (0xB0000000 | BR_PS_16 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR3_PRELIM (OR_AM_256MB | OR_GPCM_SCY_5 | OR_GPCM_TRLX_CLEAR | OR_GPCM_EHTR_CLEAR) /* ethernet port connected to piggy (UEC2) */ #define CONFIG_HAS_ETH1 diff --git a/include/configs/kmtepr2.h b/include/configs/kmtepr2.h index fd00ea86a9..c1ed71e2af 100644 --- a/include/configs/kmtepr2.h +++ b/include/configs/kmtepr2.h @@ -113,15 +113,9 @@ */ #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ - BR_PS_16 | /* 16 bit port size */ \ - BR_MS_GPCM | /* MSEL = GPCM */ \ - BR_V) - -#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | \ - OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ - OR_GPCM_SCY_5 | \ - OR_GPCM_TRLX_SET | OR_GPCM_EAD) +/* FLASH */ +#define CONFIG_SYS_BR0_PRELIM (0xF0000000 | BR_PS_16 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ @@ -130,15 +124,10 @@ /* * PRIO1/PIGGY on the local bus CS1 */ -/* Window base at flash base */ -#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_KMBEC_FPGA_BASE | \ - BR_PS_8 | /* 8 bit port size */ \ - BR_MS_GPCM | /* MSEL = GPCM */ \ - BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_128MB | \ - OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ - OR_GPCM_SCY_2 | \ - OR_GPCM_TRLX_SET | OR_GPCM_EAD) + +/* KMBEC_FPGA */ +#define CONFIG_SYS_BR1_PRELIM (0xE8000000 | BR_PS_8 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR1_PRELIM (OR_AM_128MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) /* * Serial Port @@ -358,32 +347,12 @@ * 3 Local GPCM 8 bit 256MB TEP2 (16 bit) */ -/* - * Configuration for C2 on the local bus - */ -#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_APP1_BASE | \ - BR_PS_8 | \ - BR_MS_GPCM | \ - BR_V) +/* APP1 */ +#define CONFIG_SYS_BR2_PRELIM (0xA0000000 | BR_PS_8 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR2_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_CLEAR | OR_GPCM_EAD) -#define CONFIG_SYS_OR2_PRELIM (OR_AM_256MB | \ - OR_GPCM_CSNT | \ - OR_GPCM_ACS_DIV4 | \ - OR_GPCM_SCY_2 | \ - OR_GPCM_TRLX_SET | \ - OR_GPCM_EHTR_CLEAR | \ - OR_GPCM_EAD) - -/* - * Configuration for C3 on the local bus - */ -#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_APP2_BASE | \ - BR_PS_16 | \ - BR_MS_GPCM | \ - BR_V) -#define CONFIG_SYS_OR3_PRELIM (OR_AM_256MB | \ - OR_GPCM_SCY_4 | \ - OR_GPCM_TRLX_CLEAR | \ - OR_GPCM_EHTR_CLEAR) +/* APP2 */ +#define CONFIG_SYS_BR3_PRELIM (0xB0000000 | BR_PS_16 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR3_PRELIM (OR_AM_256MB | OR_GPCM_SCY_4 | OR_GPCM_TRLX_CLEAR | OR_GPCM_EHTR_CLEAR) #endif /* __CONFIG_H */ diff --git a/include/configs/kmvect1.h b/include/configs/kmvect1.h index 3d9164714c..406b6e7824 100644 --- a/include/configs/kmvect1.h +++ b/include/configs/kmvect1.h @@ -112,15 +112,9 @@ */ #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ - BR_PS_16 | /* 16 bit port size */ \ - BR_MS_GPCM | /* MSEL = GPCM */ \ - BR_V) - -#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | \ - OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ - OR_GPCM_SCY_5 | \ - OR_GPCM_TRLX_SET | OR_GPCM_EAD) +/* FLASH */ +#define CONFIG_SYS_BR0_PRELIM (0xF0000000 | BR_PS_16 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ @@ -129,15 +123,10 @@ /* * PRIO1/PIGGY on the local bus CS1 */ -/* Window base at flash base */ -#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_KMBEC_FPGA_BASE | \ - BR_PS_8 | /* 8 bit port size */ \ - BR_MS_GPCM | /* MSEL = GPCM */ \ - BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_128MB | \ - OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ - OR_GPCM_SCY_2 | \ - OR_GPCM_TRLX_SET | OR_GPCM_EAD) + +/* KMBEC_FPGA */ +#define CONFIG_SYS_BR1_PRELIM (0xE8000000 | BR_PS_8 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR1_PRELIM (OR_AM_128MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) /* * Serial Port @@ -400,24 +389,13 @@ * */ -/* - * APP1 on the local bus CS2 - */ -#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_APP1_BASE | \ - BR_PS_16 | \ - BR_MS_UPMA | \ - BR_V) +/* APP1 */ +#define CONFIG_SYS_BR2_PRELIM (0xA0000000 | BR_PS_16 | BR_MS_UPMA | BR_V) #define CONFIG_SYS_OR2_PRELIM (OR_AM_256MB) -#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_APP2_BASE | \ - BR_PS_16 | \ - BR_V) - -#define CONFIG_SYS_OR3_PRELIM (OR_AM_256MB | \ - OR_GPCM_CSNT | \ - OR_GPCM_ACS_DIV4 | \ - OR_GPCM_SCY_3 | \ - OR_GPCM_TRLX_SET) +/* APP2 */ +#define CONFIG_SYS_BR3_PRELIM (0xB0000000 | BR_PS_16 | BR_V) +#define CONFIG_SYS_OR3_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_3 | OR_GPCM_TRLX_SET) #define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \ 0x0000c000 | \ diff --git a/include/configs/mpc8308_p1m.h b/include/configs/mpc8308_p1m.h index 046355f645..31bf9971ab 100644 --- a/include/configs/mpc8308_p1m.h +++ b/include/configs/mpc8308_p1m.h @@ -179,19 +179,9 @@ #define CONFIG_SYS_FLASH_BASE 0xFC000000 /* FLASH base address */ #define CONFIG_SYS_FLASH_SIZE 64 /* FLASH size is 64M */ -/* Window base at flash base */ -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ - | BR_PS_16 /* 16 bit port */ \ - | BR_MS_GPCM /* MSEL = GPCM */ \ - | BR_V) /* valid */ -#define CONFIG_SYS_OR0_PRELIM (OR_AM_64MB \ - | OR_UPM_XAM \ - | OR_GPCM_CSNT \ - | OR_GPCM_ACS_DIV2 \ - | OR_GPCM_XACS \ - | OR_GPCM_SCY_4 \ - | OR_GPCM_TRLX_SET \ - | OR_GPCM_EHTR_SET) +/* FLASH */ +#define CONFIG_SYS_BR0_PRELIM (0xFC000000 | BR_PS_16 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR0_PRELIM (OR_AM_64MB | OR_UPM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_4 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 512 @@ -205,27 +195,19 @@ * SJA1000 CAN controller on Local Bus */ #define CONFIG_SYS_SJA1000_BASE 0xFBFF0000 -#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_SJA1000_BASE \ - | BR_PS_8 /* 8 bit port size */ \ - | BR_MS_GPCM /* MSEL = GPCM */ \ - | BR_V) /* valid */ -#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \ - | OR_GPCM_SCY_5 \ - | OR_GPCM_EHTR_SET) - /* 0xFFFF8052 */ + +/* SJA1000 */ +#define CONFIG_SYS_BR1_PRELIM (0xFBFF0000 | BR_PS_8 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_GPCM_SCY_5 | OR_GPCM_EHTR_SET) /* * CPLD on Local Bus */ #define CONFIG_SYS_CPLD_BASE 0xFBFF8000 -#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_CPLD_BASE \ - | BR_PS_8 /* 8 bit port */ \ - | BR_MS_GPCM /* MSEL = GPCM */ \ - | BR_V) /* valid */ -#define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB \ - | OR_GPCM_SCY_4 \ - | OR_GPCM_EHTR_SET) - /* 0xFFFF8042 */ + +/* CPLD */ +#define CONFIG_SYS_BR2_PRELIM (0xFBFF8000 | BR_PS_8 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB | OR_GPCM_SCY_4 | OR_GPCM_EHTR_SET) /* * Serial Port diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index dffb7c6108..09cdb7c1a8 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -98,21 +98,9 @@ #define CONFIG_SYS_FLASH_BASE 0xFF800000 /* start of FLASH */ #define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */ -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ - | BR_PS_16 /* 16 bit port */ \ - | BR_MS_GPCM /* MSEL = GPCM */ \ - | BR_V) /* valid */ - -#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB \ - | OR_GPCM_XAM \ - | OR_GPCM_CSNT \ - | OR_GPCM_ACS_DIV2 \ - | OR_GPCM_XACS \ - | OR_GPCM_SCY_15 \ - | OR_GPCM_TRLX_SET \ - | OR_GPCM_EHTR_SET \ - | OR_GPCM_EAD) - /* 0xFF806FF7 */ +/* FLASH */ +#define CONFIG_SYS_BR0_PRELIM (0xFF800000 | BR_PS_16 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */ diff --git a/include/configs/strider.h b/include/configs/strider.h index 184396e037..1519dad321 100644 --- a/include/configs/strider.h +++ b/include/configs/strider.h @@ -167,19 +167,9 @@ #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */ -/* Window base at flash base */ -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ - | BR_PS_16 /* 16 bit port */ \ - | BR_MS_GPCM /* MSEL = GPCM */ \ - | BR_V) /* valid */ -#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB \ - | OR_UPM_XAM \ - | OR_GPCM_CSNT \ - | OR_GPCM_ACS_DIV2 \ - | OR_GPCM_XACS \ - | OR_GPCM_SCY_15 \ - | OR_GPCM_TRLX_SET \ - | OR_GPCM_EHTR_SET) +/* FLASH */ +#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB | OR_UPM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 135 @@ -193,18 +183,9 @@ #define CONFIG_SYS_FPGA0_BASE 0xE0600000 #define CONFIG_SYS_FPGA0_SIZE 1 /* FPGA size is 1M */ -/* Window base at FPGA base */ -#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FPGA0_BASE \ - | BR_PS_16 /* 16 bit port */ \ - | BR_MS_GPCM /* MSEL = GPCM */ \ - | BR_V) /* valid */ - -#define CONFIG_SYS_OR1_PRELIM (OR_AM_1MB \ - | OR_UPM_XAM \ - | OR_GPCM_CSNT \ - | OR_GPCM_SCY_5 \ - | OR_GPCM_TRLX_CLEAR \ - | OR_GPCM_EHTR_CLEAR) +/* FPGA */ +#define CONFIG_SYS_BR1_PRELIM (0xE0600000 | BR_PS_16 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR1_PRELIM (OR_AM_1MB | OR_UPM_XAM | OR_GPCM_CSNT | OR_GPCM_SCY_5 | OR_GPCM_TRLX_CLEAR | OR_GPCM_EHTR_CLEAR) #define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE #define CONFIG_SYS_FPGA_DONE(k) 0x0010 diff --git a/include/configs/suvd3.h b/include/configs/suvd3.h index ad270de87d..6aacbc2077 100644 --- a/include/configs/suvd3.h +++ b/include/configs/suvd3.h @@ -110,15 +110,9 @@ */ #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ - BR_PS_16 | /* 16 bit port size */ \ - BR_MS_GPCM | /* MSEL = GPCM */ \ - BR_V) - -#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | \ - OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ - OR_GPCM_SCY_5 | \ - OR_GPCM_TRLX_SET | OR_GPCM_EAD) +/* FLASH */ +#define CONFIG_SYS_BR0_PRELIM (0xF0000000 | BR_PS_16 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ @@ -127,15 +121,10 @@ /* * PRIO1/PIGGY on the local bus CS1 */ -/* Window base at flash base */ -#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_KMBEC_FPGA_BASE | \ - BR_PS_8 | /* 8 bit port size */ \ - BR_MS_GPCM | /* MSEL = GPCM */ \ - BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_128MB | \ - OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ - OR_GPCM_SCY_2 | \ - OR_GPCM_TRLX_SET | OR_GPCM_EAD) + +/* KMBEC_FPGA */ +#define CONFIG_SYS_BR1_PRELIM (0xE8000000 | BR_PS_8 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR1_PRELIM (OR_AM_128MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) /* * Serial Port @@ -353,24 +342,13 @@ * */ -/* - * APP1 on the local bus CS2 - */ -#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_APP1_BASE | \ - BR_PS_16 | \ - BR_MS_UPMA | \ - BR_V) +/* APP1 */ +#define CONFIG_SYS_BR2_PRELIM (0xA0000000 | BR_PS_16 | BR_MS_UPMA | BR_V) #define CONFIG_SYS_OR2_PRELIM (OR_AM_256MB) -#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_APP2_BASE | \ - BR_PS_16 | \ - BR_V) - -#define CONFIG_SYS_OR3_PRELIM (OR_AM_256MB | \ - OR_GPCM_CSNT | \ - OR_GPCM_ACS_DIV4 | \ - OR_GPCM_SCY_3 | \ - OR_GPCM_TRLX_SET) +/* APP2 */ +#define CONFIG_SYS_BR3_PRELIM (0xB0000000 | BR_PS_16 | BR_V) +#define CONFIG_SYS_OR3_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_3 | OR_GPCM_TRLX_SET) #define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \ 0x0000c000 | \ diff --git a/include/configs/tuge1.h b/include/configs/tuge1.h index af6a348ba5..b11d49629a 100644 --- a/include/configs/tuge1.h +++ b/include/configs/tuge1.h @@ -113,15 +113,9 @@ */ #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ - BR_PS_16 | /* 16 bit port size */ \ - BR_MS_GPCM | /* MSEL = GPCM */ \ - BR_V) - -#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | \ - OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ - OR_GPCM_SCY_5 | \ - OR_GPCM_TRLX_SET | OR_GPCM_EAD) +/* FLASH */ +#define CONFIG_SYS_BR0_PRELIM (0xF0000000 | BR_PS_16 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ @@ -130,15 +124,10 @@ /* * PRIO1/PIGGY on the local bus CS1 */ -/* Window base at flash base */ -#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_KMBEC_FPGA_BASE | \ - BR_PS_8 | /* 8 bit port size */ \ - BR_MS_GPCM | /* MSEL = GPCM */ \ - BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_128MB | \ - OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ - OR_GPCM_SCY_2 | \ - OR_GPCM_TRLX_SET | OR_GPCM_EAD) + +/* KMBEC_FPGA */ +#define CONFIG_SYS_BR1_PRELIM (0xE8000000 | BR_PS_8 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR1_PRELIM (OR_AM_128MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) /* * Serial Port @@ -356,20 +345,8 @@ * 3 Local GPCM 8 bit 256MB TEP2 (16 bit) */ -/* - * Configuration for C2 on the local bus - */ -#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_APP1_BASE | \ - BR_PS_8 | \ - BR_MS_GPCM | \ - BR_V) - -#define CONFIG_SYS_OR2_PRELIM (OR_AM_256MB | \ - OR_GPCM_CSNT | \ - OR_GPCM_ACS_DIV4 | \ - OR_GPCM_SCY_2 | \ - OR_GPCM_TRLX_SET | \ - OR_GPCM_EHTR_CLEAR | \ - OR_GPCM_EAD) +/* APP1 */ +#define CONFIG_SYS_BR2_PRELIM (0xA0000000 | BR_PS_8 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR2_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_CLEAR | OR_GPCM_EAD) #endif /* __CONFIG_H */ diff --git a/include/configs/tuxx1.h b/include/configs/tuxx1.h index 18476c12de..1bff837198 100644 --- a/include/configs/tuxx1.h +++ b/include/configs/tuxx1.h @@ -113,15 +113,9 @@ */ #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ - BR_PS_16 | /* 16 bit port size */ \ - BR_MS_GPCM | /* MSEL = GPCM */ \ - BR_V) - -#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | \ - OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ - OR_GPCM_SCY_5 | \ - OR_GPCM_TRLX_SET | OR_GPCM_EAD) +/* FLASH */ +#define CONFIG_SYS_BR0_PRELIM (0xF0000000 | BR_PS_16 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ @@ -130,15 +124,10 @@ /* * PRIO1/PIGGY on the local bus CS1 */ -/* Window base at flash base */ -#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_KMBEC_FPGA_BASE | \ - BR_PS_8 | /* 8 bit port size */ \ - BR_MS_GPCM | /* MSEL = GPCM */ \ - BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_128MB | \ - OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ - OR_GPCM_SCY_2 | \ - OR_GPCM_TRLX_SET | OR_GPCM_EAD) + +/* KMBEC_FPGA */ +#define CONFIG_SYS_BR1_PRELIM (0xE8000000 | BR_PS_8 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR1_PRELIM (OR_AM_128MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) /* * Serial Port @@ -358,36 +347,13 @@ * 3 Local GPCM 8 bit 256MB TEP2 (16 bit) */ -/* - * Configuration for C2 on the local bus - */ -#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_APP1_BASE | \ - BR_PS_8 | \ - BR_MS_GPCM | \ - BR_V) +/* APP1 */ +#define CONFIG_SYS_BR2_PRELIM (0xA0000000 | BR_PS_8 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR2_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_CLEAR | OR_GPCM_EAD) -#define CONFIG_SYS_OR2_PRELIM (OR_AM_256MB | \ - OR_GPCM_CSNT | \ - OR_GPCM_ACS_DIV4 | \ - OR_GPCM_SCY_2 | \ - OR_GPCM_TRLX_SET | \ - OR_GPCM_EHTR_CLEAR | \ - OR_GPCM_EAD) - -/* - * Configuration for C3 on the local bus - */ -#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_APP2_BASE | \ - BR_PS_8 | \ - BR_MS_GPCM | \ - BR_V) - -#define CONFIG_SYS_OR3_PRELIM (OR_AM_256MB | \ - OR_GPCM_CSNT | \ - OR_GPCM_ACS_DIV2 | \ - OR_GPCM_SCY_2 | \ - OR_GPCM_TRLX_SET | \ - OR_GPCM_EHTR_CLEAR) +/* APP2 */ +#define CONFIG_SYS_BR3_PRELIM (0xB0000000 | BR_PS_8 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR3_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_CLEAR) #define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \ 0x0000c000 | \ diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h index 7dcc150f19..3a5bcf9c62 100644 --- a/include/configs/ve8313.h +++ b/include/configs/ve8313.h @@ -153,63 +153,25 @@ #define CONFIG_NAND_FSL_ELBC 1 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384 +/* FLASH */ +#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR0_PRELIM (OR_AM_32MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ - | BR_PS_16 /* 16 bit */ \ - | BR_MS_GPCM /* MSEL = GPCM */ \ - | BR_V) /* valid */ -#define CONFIG_SYS_OR0_PRELIM (OR_AM_32MB \ - | OR_GPCM_CSNT \ - | OR_GPCM_ACS_DIV4 \ - | OR_GPCM_SCY_5 \ - | OR_GPCM_TRLX_SET \ - | OR_GPCM_EAD) - /* 0xfe000c55 */ - -#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \ - | BR_PS_8 \ - | BR_DECC_CHK_GEN \ - | BR_MS_FCM \ - | BR_V) /* valid */ - /* 0x61000c21 */ -#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \ - | OR_FCM_BCTLD \ - | OR_FCM_CHT \ - | OR_FCM_SCY_2 \ - | OR_FCM_RST \ - | OR_FCM_TRLX) /* 0xffff90ac */ +/* NAND */ +#define CONFIG_SYS_BR1_PRELIM (0x61000000 | BR_PS_8 | BR_DECC_CHK_GEN | BR_MS_FCM | BR_V) +#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_FCM_BCTLD | OR_FCM_CHT | OR_FCM_SCY_2 | OR_FCM_RST | OR_FCM_TRLX) /* Still needed for spl_minimal.c */ #define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM #define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM -/* CS2 NvRAM */ -#define CONFIG_SYS_BR2_PRELIM (0x60000000 \ - | BR_PS_8 \ - | BR_V) - /* 0x60000801 */ -#define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB \ - | OR_GPCM_CSNT \ - | OR_GPCM_XACS \ - | OR_GPCM_SCY_3 \ - | OR_GPCM_TRLX_SET \ - | OR_GPCM_EHTR_SET \ - | OR_GPCM_EAD) - /* 0xfffe0937 */ -/* local bus read write buffer mapping SRAM@0x64000000 */ -#define CONFIG_SYS_BR3_PRELIM (0x62000000 \ - | BR_PS_16 \ - | BR_V) - /* 0x62001001 */ +/* NVRAM */ +#define CONFIG_SYS_BR2_PRELIM (0x60000000 | BR_PS_8 | BR_V) +#define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_3 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) -#define CONFIG_SYS_OR3_PRELIM (OR_AM_32MB \ - | OR_GPCM_CSNT \ - | OR_GPCM_XACS \ - | OR_GPCM_SCY_15 \ - | OR_GPCM_TRLX_SET \ - | OR_GPCM_EHTR_SET \ - | OR_GPCM_EAD) - /* 0xfe0009f7 */ +/* SRAM */ +#define CONFIG_SYS_BR3_PRELIM (0x62000000 | BR_PS_16 | BR_V) +#define CONFIG_SYS_OR3_PRELIM (OR_AM_32MB | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) /* * Serial Port diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h index 76821e7a40..dd8aae5117 100644 --- a/include/configs/vme8349.h +++ b/include/configs/vme8349.h @@ -69,31 +69,16 @@ */ #define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH */ #define CONFIG_SYS_FLASH_SIZE 128 /* flash size in MB */ -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ - BR_PS_16 | /* 16bit */ \ - BR_MS_GPCM | /* MSEL = GPCM */ \ - BR_V) /* valid */ -#define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB \ - | OR_GPCM_XAM \ - | OR_GPCM_CSNT \ - | OR_GPCM_ACS_DIV2 \ - | OR_GPCM_XACS \ - | OR_GPCM_SCY_15 \ - | OR_GPCM_TRLX_SET \ - | OR_GPCM_EHTR_SET \ - | OR_GPCM_EAD) - /* 0xf8006ff7 */ +/* FLASH */ +#define CONFIG_SYS_BR0_PRELIM (0xF8000000 | BR_PS_16 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) #define CONFIG_SYS_WINDOW1_BASE 0xf0000000 -#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_WINDOW1_BASE \ - | BR_PS_32 \ - | BR_MS_GPCM \ - | BR_V) - /* 0xF0001801 */ -#define CONFIG_SYS_OR1_PRELIM (OR_AM_256KB \ - | OR_GPCM_SETA) - /* 0xfffc0208 */ + +/* WINDOW1 */ +#define CONFIG_SYS_BR1_PRELIM (0xF0000000 | BR_PS_32 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR1_PRELIM (OR_AM_256KB | OR_GPCM_SETA) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device*/ From daac2086ce1a36ffbd603eb643f45d14faae40e7 Mon Sep 17 00:00:00 2001 From: Mario Six Date: Mon, 21 Jan 2019 09:18:02 +0100 Subject: [PATCH 39/86] sbc8349: Remove SDRAM functionality The MPC8349EMDS configuration was the basis for the sbc8349, so it also contains its SDRAM option. Since * the SDRAM has to be soldered onto the board, * the sbc8349 never used the support, and * the support never worked (see previous patch fixing it), we can assume that the support on the sbc8349 is an artifact created by copying the MPC8349EMDS config wholesome. Hence, instead of creating a separate sbc8349 config that supports SDRAM, we can remove the SDRAM option for this board. Should it be needed in the future, it can be copied from the new MPC8349EMDS_SDRAM board. Signed-off-by: Mario Six --- include/configs/sbc8349.h | 67 --------------------------------------- 1 file changed, 67 deletions(-) diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index 09cdb7c1a8..42a1e1682d 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -142,73 +142,6 @@ #undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */ -#ifdef CONFIG_SYS_LB_SDRAM -/* Local bus BR2, OR2 definition for SDRAM if soldered on the board*/ -/* - * Base Register 2 and Option Register 2 configure SDRAM. - * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. - * - * For BR2, need: - * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 - * port-size = 32-bits = BR2[19:20] = 11 - * no parity checking = BR2[21:22] = 00 - * SDRAM for MSEL = BR2[24:26] = 011 - * Valid = BR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861 - */ - -#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LBC_SDRAM_BASE \ - | BR_PS_32 \ - | BR_MS_SDRAM \ - | BR_V) - /* 0xF0001861 */ -/* - * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. - * - * For OR2, need: - * 64MB mask for AM, OR2[0:7] = 1111 1100 - * XAM, OR2[17:18] = 11 - * 9 columns OR2[19-21] = 010 - * 13 rows OR2[23-25] = 100 - * EAD set for extra time OR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901 - */ - -#define CONFIG_SYS_OR2_PRELIM (OR_AM_64MB \ - | OR_SDRAM_XAM \ - | ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \ - | ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \ - | OR_SDRAM_EAD) - /* 0xFC006901 */ - - /* LB sdram refresh timer, about 6us */ -#define CONFIG_SYS_LBC_LSRT 0x32000000 - /* LB refresh timer prescal, 266MHz/32 */ -#define CONFIG_SYS_LBC_MRTPR 0x20000000 - -#define CONFIG_SYS_LBC_LSDMR_COMMON (LSDMR_RFEN \ - | LSDMR_BSMA1516 \ - | LSDMR_RFCR8 \ - | LSDMR_PRETOACT6 \ - | LSDMR_ACTTORW3 \ - | LSDMR_BL8 \ - | LSDMR_WRC3 \ - | LSDMR_CL3) - -/* - * SDRAM Controller configuration sequence. - */ -#define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) -#define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) -#define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) -#define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) -#define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL) -#endif - /* * Serial Port */ From fe7d654d04a4ba87813dcf8acb7a17373029770d Mon Sep 17 00:00:00 2001 From: Mario Six Date: Mon, 21 Jan 2019 09:18:03 +0100 Subject: [PATCH 40/86] mpc83xx: Migrate CONFIG_SYS_{BR, OR}*_PRELIM to Kconfig Migrate the BR/OR settings to Kconfig. These must be known at compile time, so cannot be configured via DT. Configuration of this crucial variable should still be somewhat comfortable. Hence, make its fields configurable in Kconfig, and assemble the final value from these. Signed-off-by: Mario Six --- arch/powerpc/cpu/mpc83xx/Kconfig | 1 + arch/powerpc/cpu/mpc83xx/cpu_init.c | 1 + arch/powerpc/cpu/mpc83xx/elbc/Kconfig | 32 + arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc0 | 733 ++++++++++++++++++++ arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc1 | 733 ++++++++++++++++++++ arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc2 | 733 ++++++++++++++++++++ arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc3 | 733 ++++++++++++++++++++ arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc4 | 733 ++++++++++++++++++++ arch/powerpc/cpu/mpc83xx/elbc/elbc.h | 186 +++++ arch/powerpc/cpu/mpc83xx/spl_minimal.c | 1 + arch/powerpc/cpu/mpc8xxx/fsl_lbc.c | 4 + board/freescale/mpc8349itx/mpc8349itx.c | 1 + configs/MPC8308RDB_defconfig | 38 + configs/MPC8313ERDB_33_defconfig | 50 ++ configs/MPC8313ERDB_66_defconfig | 50 ++ configs/MPC8313ERDB_NAND_33_defconfig | 50 ++ configs/MPC8313ERDB_NAND_66_defconfig | 50 ++ configs/MPC8315ERDB_defconfig | 27 + configs/MPC8323ERDB_defconfig | 14 + configs/MPC832XEMDS_ATM_defconfig | 53 ++ configs/MPC832XEMDS_HOST_33_defconfig | 53 ++ configs/MPC832XEMDS_HOST_66_defconfig | 53 ++ configs/MPC832XEMDS_SLAVE_defconfig | 53 ++ configs/MPC832XEMDS_defconfig | 53 ++ configs/MPC8349EMDS_PCI64_defconfig | 24 + configs/MPC8349EMDS_SDRAM_defconfig | 27 + configs/MPC8349EMDS_SLAVE_defconfig | 24 + configs/MPC8349EMDS_defconfig | 24 + configs/MPC8349ITXGP_defconfig | 47 ++ configs/MPC8349ITX_LOWBOOT_defconfig | 47 ++ configs/MPC8349ITX_defconfig | 47 ++ configs/MPC837XEMDS_HOST_defconfig | 41 ++ configs/MPC837XEMDS_SLAVE_defconfig | 41 ++ configs/MPC837XEMDS_defconfig | 41 ++ configs/MPC837XERDB_SLAVE_defconfig | 36 + configs/MPC837XERDB_defconfig | 36 + configs/TQM834x_defconfig | 10 + configs/caddy2_defconfig | 21 + configs/hrcon_defconfig | 26 + configs/hrcon_dh_defconfig | 26 + configs/ids8313_defconfig | 45 ++ configs/kmcoge5ne_defconfig | 42 ++ configs/kmeter1_defconfig | 32 + configs/kmopti2_defconfig | 42 ++ configs/kmsupx5_defconfig | 34 + configs/kmtegr1_defconfig | 30 + configs/kmtepr2_defconfig | 42 ++ configs/kmvect1_defconfig | 37 + configs/mpc8308_p1m_defconfig | 29 + configs/sbc8349_PCI_33_defconfig | 14 + configs/sbc8349_PCI_66_defconfig | 14 + configs/sbc8349_defconfig | 14 + configs/strider_con_defconfig | 23 + configs/strider_con_dp_defconfig | 23 + configs/strider_cpu_defconfig | 23 + configs/strider_cpu_dp_defconfig | 23 + configs/suvd3_defconfig | 37 + configs/tuge1_defconfig | 34 + configs/tuxx1_defconfig | 45 ++ configs/ve8313_defconfig | 45 ++ configs/vme8349_defconfig | 21 + drivers/mtd/nand/raw/fsl_elbc_spl.c | 4 + include/configs/MPC8308RDB.h | 9 - include/configs/MPC8313ERDB_NAND.h | 14 - include/configs/MPC8313ERDB_NOR.h | 14 - include/configs/MPC8315ERDB.h | 6 - include/configs/MPC8323ERDB.h | 3 - include/configs/MPC832XEMDS.h | 12 - include/configs/MPC8349EMDS.h | 6 - include/configs/MPC8349EMDS_SDRAM.h | 12 - include/configs/MPC8349ITX.h | 12 - include/configs/MPC837XEMDS.h | 9 - include/configs/MPC837XERDB.h | 9 - include/configs/TQM834x.h | 3 - include/configs/caddy2.h | 6 - include/configs/hrcon.h | 6 - include/configs/ids8313.h | 12 - include/configs/kmcoge5ne.h | 12 - include/configs/kmeter1.h | 9 - include/configs/kmopti2.h | 12 - include/configs/kmsupx5.h | 9 - include/configs/kmtegr1.h | 9 - include/configs/kmtepr2.h | 12 - include/configs/kmvect1.h | 12 - include/configs/mpc8308_p1m.h | 9 - include/configs/sbc8349.h | 3 - include/configs/strider.h | 6 - include/configs/suvd3.h | 12 - include/configs/tuge1.h | 9 - include/configs/tuxx1.h | 12 - include/configs/ve8313.h | 12 - include/configs/vme8349.h | 6 - 92 files changed, 5606 insertions(+), 277 deletions(-) create mode 100644 arch/powerpc/cpu/mpc83xx/elbc/Kconfig create mode 100644 arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc0 create mode 100644 arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc1 create mode 100644 arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc2 create mode 100644 arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc3 create mode 100644 arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc4 create mode 100644 arch/powerpc/cpu/mpc83xx/elbc/elbc.h diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index 8c84196b97..474572f245 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -285,6 +285,7 @@ config ARCH_MPC837X source "arch/powerpc/cpu/mpc83xx/hrcw/Kconfig" source "arch/powerpc/cpu/mpc83xx/bats/Kconfig" source "arch/powerpc/cpu/mpc83xx/lblaw/Kconfig" +source "arch/powerpc/cpu/mpc83xx/elbc/Kconfig" menu "Legacy options" diff --git a/arch/powerpc/cpu/mpc83xx/cpu_init.c b/arch/powerpc/cpu/mpc83xx/cpu_init.c index 91451e7b30..5ce7b794b2 100644 --- a/arch/powerpc/cpu/mpc83xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc83xx/cpu_init.c @@ -13,6 +13,7 @@ #endif #include "lblaw/lblaw.h" +#include "elbc/elbc.h" DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/powerpc/cpu/mpc83xx/elbc/Kconfig b/arch/powerpc/cpu/mpc83xx/elbc/Kconfig new file mode 100644 index 0000000000..74c4ff3ed4 --- /dev/null +++ b/arch/powerpc/cpu/mpc83xx/elbc/Kconfig @@ -0,0 +1,32 @@ +menu "ELBC register setup" + +choice + prompt "OR/BR for NAND SPL" + +config ELBC_BR_OR_NAND_PRELIM_NONE + bool "None" + +config ELBC_BR_OR_NAND_PRELIM_0 + bool "0" + +config ELBC_BR_OR_NAND_PRELIM_1 + bool "1" + +config ELBC_BR_OR_NAND_PRELIM_2 + bool "2" + +config ELBC_BR_OR_NAND_PRELIM_3 + bool "3" + +config ELBC_BR_OR_NAND_PRELIM_4 + bool "4" + +endchoice + +source "arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc0" +source "arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc1" +source "arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc2" +source "arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc3" +source "arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc4" + +endmenu diff --git a/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc0 b/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc0 new file mode 100644 index 0000000000..23e81ab0bf --- /dev/null +++ b/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc0 @@ -0,0 +1,733 @@ +menuconfig ELBC_BR0_OR0 + bool "ELBC BR0/OR0" + +if ELBC_BR0_OR0 + +config BR0_OR0_NAME + string "Identifier" + +config BR0_OR0_BASE + hex "Port base" + +choice + prompt "Port size" + +config BR0_PORTSIZE_8BIT + bool "8-bit" + +config BR0_PORTSIZE_16BIT + depends on !BR0_MACHINE_FCM + bool "16-bit" + + +config BR0_PORTSIZE_32BIT + depends on !BR0_MACHINE_FCM + depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379 + bool "32-bit" + +endchoice + +if BR0_MACHINE_FCM + +choice + prompt "Data Error Checking" + +config BR0_ERRORCHECKING_DISABLED + bool "Disabled" + +config BR0_ERRORCHECKING_ECC_CHECKING + bool "ECC checking / No ECC generation" + +config BR0_ERRORCHECKING_BOTH + bool "ECC checking and generation" + +endchoice + +endif + +config BR0_WRITE_PROTECT + bool "Write-protect" + +config BR0_MACHINE_UPM + bool + +choice + prompt "Machine select" + +config BR0_MACHINE_GPCM + bool "GPCM" + +config BR0_MACHINE_FCM + depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360 + bool "FCM" + +config BR0_MACHINE_SDRAM + depends on ARCH_MPC8349 || ARCH_MPC8360 + bool "SDRAM" + +config BR0_MACHINE_UPMA + select BR0_MACHINE_UPM + bool "UPM (A)" + +config BR0_MACHINE_UPMB + select BR0_MACHINE_UPM + bool "UPM (B)" + +config BR0_MACHINE_UPMC + select BR0_MACHINE_UPM + bool "UPM (C)" + +endchoice + +if ARCH_MPC8313 || ARCH_MPC8323 || ARCH_MPC8360 + +choice + prompt "Atomic operations" + +config BR0_ATOMIC_NONE + bool "No atomic operations" + +config BR0_ATOMIC_RAWA + bool "Read-after-write-atomic" + +config BR0_ATOMIC_WARA + bool "Write-after-read-atomic" + +endchoice + +endif + +if BR0_MACHINE_GPCM || BR0_MACHINE_FCM || BR0_MACHINE_UPM || BR0_MACHINE_SDRAM + +choice + prompt "Address mask" + +config OR0_AM_32_KBYTES + depends on !BR0_MACHINE_SDRAM + bool "32 kb" + +config OR0_AM_64_KBYTES + bool "64 kb" + +config OR0_AM_128_KBYTES + bool "128 kb" + +config OR0_AM_256_KBYTES + bool "256 kb" + +config OR0_AM_512_KBYTES + bool "512 kb" + +config OR0_AM_1_MBYTES + bool "1 mb" + +config OR0_AM_2_MBYTES + bool "2 mb" + +config OR0_AM_4_MBYTES + bool "4 mb" + +config OR0_AM_8_MBYTES + bool "8 mb" + +config OR0_AM_16_MBYTES + bool "16 mb" + +config OR0_AM_32_MBYTES + bool "32 mb" + +config OR0_AM_64_MBYTES + bool "64 mb" + +# XXX: Some boards define 128MB AM with GPCM, even though it should not be +# possible according to the manuals +config OR0_AM_128_MBYTES + bool "128 mb" + +# XXX: Some boards define 256MB AM with GPCM, even though it should not be +# possible according to the manuals +config OR0_AM_256_MBYTES + bool "256 mb" + +config OR0_AM_512_MBYTES + depends on BR0_MACHINE_FCM + bool "512 mb" + +# XXX: Some boards define 1GB AM with GPCM, even though it should not be +# possible according to the manuals +config OR0_AM_1_GBYTES + bool "1 gb" + +config OR0_AM_2_GBYTES + depends on BR0_MACHINE_FCM + bool "2 gb" + +config OR0_AM_4_GBYTES + depends on BR0_MACHINE_FCM + bool "4 gb" + +endchoice + +config OR0_XAM_SET + bool "Set unused bytes after address mask" +choice + prompt "Buffer control disable" + +config OR0_BCTLD_ASSERTED + bool "Asserted" + +config OR0_BCTLD_NOT_ASSERTED + bool "Not asserted" + +endchoice + +endif + +if BR0_MACHINE_GPCM || BR0_MACHINE_FCM + +choice + prompt "Cycle length in bus clocks" + +config OR0_SCY_0 + bool "No wait states" + +config OR0_SCY_1 + bool "1 wait state" + +config OR0_SCY_2 + bool "2 wait states" + +config OR0_SCY_3 + bool "3 wait states" + +config OR0_SCY_4 + bool "4 wait states" + +config OR0_SCY_5 + bool "5 wait states" + +config OR0_SCY_6 + bool "6 wait states" + +config OR0_SCY_7 + bool "7 wait states" + +config OR0_SCY_8 + depends on BR0_MACHINE_GPCM + bool "8 wait states" + +config OR0_SCY_9 + depends on BR0_MACHINE_GPCM + bool "9 wait states" + +config OR0_SCY_10 + depends on BR0_MACHINE_GPCM + bool "10 wait states" + +config OR0_SCY_11 + depends on BR0_MACHINE_GPCM + bool "11 wait states" + +config OR0_SCY_12 + depends on BR0_MACHINE_GPCM + bool "12 wait states" + +config OR0_SCY_13 + depends on BR0_MACHINE_GPCM + bool "13 wait states" + +config OR0_SCY_14 + depends on BR0_MACHINE_GPCM + bool "14 wait states" + +config OR0_SCY_15 + depends on BR0_MACHINE_GPCM + bool "15 wait states" + +endchoice + +endif # BR0_MACHINE_GPCM || BR0_MACHINE_FCM + +if BR0_MACHINE_GPCM + +choice + prompt "Chip select negotiation time" + +config OR0_CSNT_NORMAL + bool "Normal" + +config OR0_CSNT_EARLIER + bool "Earlier" + +endchoice + +choice + prompt "Address to chip-select setup" + +config OR0_ACS_SAME_TIME + bool "At the same time" + +config OR0_ACS_HALF_CYCLE_EARLIER + bool "Half of a bus clock cycle earlier" + +config OR0_ACS_QUARTER_CYCLE_EARLIER + bool "Half/Quarter of a bus clock cycle earlier" + +endchoice + +choice + prompt "Extra address to check-select setup" + +config OR0_XACS_NORMAL + bool "Normal" + +config OR0_XACS_EXTENDED + bool "Extended" + +endchoice + +choice + prompt "External address termination" + +config OR0_SETA_INTERNAL + bool "Access is terminated internally" + +config OR0_SETA_EXTERNAL + bool "Access is terminated externally" + +endchoice + +endif # BR0_MACHINE_GPCM + +if BR0_MACHINE_FCM + +choice + prompt "NAND Flash EEPROM page size" + +config OR0_PGS_SMALL + bool "Small page device" + +config OR0_PGS_LARGE + bool "Large page device" + +endchoice + +choice + prompt "Chip select to command time" + +config OR0_CSCT_1_CYCLE + depends on OR0_TRLX_NORMAL + bool "1 cycle" + +config OR0_CSCT_2_CYCLE + depends on OR0_TRLX_RELAXED + bool "2 cycles" + +config OR0_CSCT_4_CYCLE + depends on OR0_TRLX_NORMAL + bool "4 cycles" + +config OR0_CSCT_8_CYCLE + depends on OR0_TRLX_RELAXED + bool "8 cycles" + +endchoice + +choice + prompt "Command setup time" + +config OR0_CST_COINCIDENT + depends on OR0_TRLX_NORMAL + bool "Coincident with any command" + +config OR0_CST_QUARTER_CLOCK + depends on OR0_TRLX_NORMAL + bool "0.25 clocks after" + +config OR0_CST_HALF_CLOCK + depends on OR0_TRLX_RELAXED + bool "0.5 clocks after" + +config OR0_CST_ONE_CLOCK + depends on OR0_TRLX_RELAXED + bool "1 clock after" + +endchoice + +choice + prompt "Command hold time" + +config OR0_CHT_HALF_CLOCK + depends on OR0_TRLX_NORMAL + bool "0.5 clocks before" + +config OR0_CHT_ONE_CLOCK + depends on OR0_TRLX_NORMAL + bool "1 clock before" + +config OR0_CHT_ONE_HALF_CLOCK + depends on OR0_TRLX_RELAXED + bool "1.5 clocks before" + +config OR0_CHT_TWO_CLOCK + depends on OR0_TRLX_RELAXED + bool "2 clocks before" + +endchoice + +choice + prompt "Reset setup time" + +config OR0_RST_THREE_QUARTER_CLOCK + depends on OR0_TRLX_NORMAL + bool "0.75 clocks prior" + +config OR0_RST_ONE_HALF_CLOCK + depends on OR0_TRLX_RELAXED + bool "0.5 clocks prior" + +config OR0_RST_ONE_CLOCK + bool "1 clock prior" + +endchoice + +endif # BR0_MACHINE_FCM + +if BR0_MACHINE_UPM + +choice + prompt "Burst inhibit" + +config OR0_BI_BURSTSUPPORT + bool "Support burst access" + +config OR0_BI_BURSTINHIBIT + bool "Inhibit burst access" + +endchoice + +endif # BR0_MACHINE_UPM + +if BR0_MACHINE_SDRAM + +choice + prompt "Number of column address lines" + +config OR0_COLS_7 + bool "7" + +config OR0_COLS_8 + bool "8" + +config OR0_COLS_9 + bool "9" + +config OR0_COLS_10 + bool "10" + +config OR0_COLS_11 + bool "11" + +config OR0_COLS_12 + bool "12" + +config OR0_COLS_13 + bool "13" + +config OR0_COLS_14 + bool "14" + +endchoice + +choice + prompt "Number of rows address lines" + +config OR0_ROWS_9 + bool "9" + +config OR0_ROWS_10 + bool "10" + +config OR0_ROWS_11 + bool "11" + +config OR0_ROWS_12 + bool "12" + +config OR0_ROWS_13 + bool "13" + +config OR0_ROWS_14 + bool "14" + +config OR0_ROWS_15 + bool "15" + +endchoice + +choice + prompt "Page mode select" + +config OR0_PMSEL_BTB + bool "Back-to-back" + +config OR0_PMSEL_KEPT_OPEN + bool "Page kept open until page miss or refresh" + +endchoice + +endif # BR0_MACHINE_SDRAM + +choice + prompt "Relaxed timing" + +config OR0_TRLX_NORMAL + bool "Normal" + +config OR0_TRLX_RELAXED + bool "Relaxed" + +endchoice + +choice + prompt "Extended hold time" + +config OR0_EHTR_NORMAL + depends on OR0_TRLX_NORMAL + bool "Normal" + +config OR0_EHTR_1_CYCLE + depends on OR0_TRLX_NORMAL + bool "1 idle clock cycle inserted" + +config OR0_EHTR_4_CYCLE + depends on OR0_TRLX_RELAXED + bool "4 idle clock cycles inserted" + +config OR0_EHTR_8_CYCLE + depends on OR0_TRLX_RELAXED + bool "8 idle clock cycles inserted" + +endchoice + +if !ARCH_MPC8308 + +choice + prompt "External address latch delay" + +config OR0_EAD_NONE + bool "None" + +config OR0_EAD_EXTRA + bool "Extra" + +endchoice + +endif # !ARCH_MPC8308 + +endif # ELBC_BR0_OR0 + +config BR0_PORTSIZE + hex + default 0x800 if BR0_PORTSIZE_8BIT + default 0x1000 if BR0_PORTSIZE_16BIT + default 0x1800 if BR0_PORTSIZE_32BIT + +config BR0_ERRORCHECKING + hex + default 0x0 if !BR0_MACHINE_FCM + default 0x0 if BR0_ERRORCHECKING_DISABLED + default 0x200 if BR0_ERRORCHECKING_ECC_CHECKING + default 0x400 if BR0_ERRORCHECKING_BOTH + +config BR0_WRITE_PROTECT_BIT + hex + default 0x0 if !BR0_WRITE_PROTECT + default 0x100 if BR0_WRITE_PROTECT + +config BR0_MACHINE + hex + default 0x0 if BR0_MACHINE_GPCM + default 0x20 if BR0_MACHINE_FCM + default 0x60 if BR0_MACHINE_SDRAM + default 0x80 if BR0_MACHINE_UPMA + default 0xa0 if BR0_MACHINE_UPMB + default 0xc0 if BR0_MACHINE_UPMC + +config BR0_ATOMIC + hex + default 0x0 if !ARCH_MPC8313 && !ARCH_MPC8323 && !ARCH_MPC8360 + default 0x0 if BR0_ATOMIC_NONE + default 0x4 if BR0_ATOMIC_RAWA + default 0x8 if BR0_ATOMIC_WARA + +config BR0_VALID_BIT + hex + default 0x0 if !ELBC_BR0_OR0 + default 0x1 if ELBC_BR0_OR0 + +config OR0_AM + hex + default 0xffff8000 if OR0_AM_32_KBYTES && !BR0_MACHINE_SDRAM + default 0xffff0000 if OR0_AM_64_KBYTES + default 0xfffe0000 if OR0_AM_128_KBYTES + default 0xfffc0000 if OR0_AM_256_KBYTES + default 0xfff80000 if OR0_AM_512_KBYTES + default 0xfff00000 if OR0_AM_1_MBYTES + default 0xffe00000 if OR0_AM_2_MBYTES + default 0xffc00000 if OR0_AM_4_MBYTES + default 0xff800000 if OR0_AM_8_MBYTES + default 0xff000000 if OR0_AM_16_MBYTES + default 0xfe000000 if OR0_AM_32_MBYTES + default 0xfc000000 if OR0_AM_64_MBYTES + default 0xf8000000 if OR0_AM_128_MBYTES + default 0xf0000000 if OR0_AM_256_MBYTES + default 0xe0000000 if OR0_AM_512_MBYTES + default 0xc0000000 if OR0_AM_1_GBYTES + default 0x80000000 if OR0_AM_2_GBYTES + default 0x00000000 if OR0_AM_4_GBYTES + +config OR0_XAM + hex + default 0x0 if !OR0_XAM_SET + default 0x6000 if OR0_XAM_SET + +config OR0_BCTLD + hex + default 0x0 if OR0_BCTLD_ASSERTED + default 0x1000 if OR0_BCTLD_NOT_ASSERTED + +config OR0_BI + hex + default 0x0 if !BR0_MACHINE_UPM + default 0x0 if OR0_BI_BURSTSUPPORT + default 0x100 if OR0_BI_BURSTINHIBIT + +config OR0_COLS + hex + default 0x0 if !BR0_MACHINE_SDRAM + default 0x0 if OR0_COLS_7 + default 0x400 if OR0_COLS_8 + default 0x800 if OR0_COLS_9 + default 0xc00 if OR0_COLS_10 + default 0x1000 if OR0_COLS_11 + default 0x1400 if OR0_COLS_12 + default 0x1800 if OR0_COLS_13 + default 0x1c00 if OR0_COLS_14 + +config OR0_ROWS + hex + default 0x0 if !BR0_MACHINE_SDRAM + default 0x0 if OR0_ROWS_9 + default 0x40 if OR0_ROWS_10 + default 0x80 if OR0_ROWS_11 + default 0xc0 if OR0_ROWS_12 + default 0x100 if OR0_ROWS_13 + default 0x140 if OR0_ROWS_14 + default 0x180 if OR0_ROWS_15 + +config OR0_PMSEL + hex + default 0x0 if !BR0_MACHINE_SDRAM + default 0x0 if OR0_PMSEL_BTB + default 0x20 if OR0_PMSEL_KEPT_OPEN + +config OR0_SCY + hex + default 0x0 if !BR0_MACHINE_GPCM && !BR0_MACHINE_FCM + default 0x0 if OR0_SCY_0 + default 0x10 if OR0_SCY_1 + default 0x20 if OR0_SCY_2 + default 0x30 if OR0_SCY_3 + default 0x40 if OR0_SCY_4 + default 0x50 if OR0_SCY_5 + default 0x60 if OR0_SCY_6 + default 0x70 if OR0_SCY_7 + default 0x80 if OR0_SCY_8 + default 0x90 if OR0_SCY_9 + default 0xa0 if OR0_SCY_10 + default 0xb0 if OR0_SCY_11 + default 0xc0 if OR0_SCY_12 + default 0xd0 if OR0_SCY_13 + default 0xe0 if OR0_SCY_14 + default 0xf0 if OR0_SCY_15 + +config OR0_PGS + hex + default 0x0 if !BR0_MACHINE_FCM + default 0x0 if OR0_PGS_SMALL + default 0x400 if OR0_PGS_LARGE + +config OR0_CSCT + hex + default 0x0 if !BR0_MACHINE_FCM + default 0x0 if OR0_CSCT_1_CYCLE + default 0x0 if OR0_CSCT_2_CYCLE + default 0x200 if OR0_CSCT_4_CYCLE + default 0x200 if OR0_CSCT_8_CYCLE + +config OR0_CST + hex + default 0x0 if !BR0_MACHINE_FCM + default 0x0 if OR0_CST_COINCIDENT + default 0x100 if OR0_CST_QUARTER_CLOCK + default 0x0 if OR0_CST_HALF_CLOCK + default 0x100 if OR0_CST_ONE_CLOCK + +config OR0_CHT + hex + default 0x0 if !BR0_MACHINE_FCM + default 0x0 if OR0_CHT_HALF_CLOCK + default 0x80 if OR0_CHT_ONE_CLOCK + default 0x0 if OR0_CHT_ONE_HALF_CLOCK + default 0x80 if OR0_CHT_TWO_CLOCK + +config OR0_RST + hex + default 0x0 if !BR0_MACHINE_FCM + default 0x0 if OR0_RST_THREE_QUARTER_CLOCK + default 0x8 if OR0_RST_ONE_CLOCK + default 0x0 if OR0_RST_ONE_HALF_CLOCK + +config OR0_CSNT + hex + default 0x0 if !BR0_MACHINE_GPCM + default 0x0 if OR0_CSNT_NORMAL + default 0x800 if OR0_CSNT_EARLIER + +config OR0_ACS + hex + default 0x0 if !BR0_MACHINE_GPCM + default 0x0 if OR0_ACS_SAME_TIME + default 0x400 if OR0_ACS_QUARTER_CYCLE_EARLIER + default 0x600 if OR0_ACS_HALF_CYCLE_EARLIER + +config OR0_XACS + hex + default 0x0 if !BR0_MACHINE_GPCM + default 0x0 if OR0_XACS_NORMAL + default 0x100 if OR0_XACS_EXTENDED + +config OR0_SETA + hex + default 0x0 if !BR0_MACHINE_GPCM + default 0x0 if OR0_SETA_INTERNAL + default 0x8 if OR0_SETA_EXTERNAL + +config OR0_TRLX + hex + default 0x0 if OR0_TRLX_NORMAL + default 0x4 if OR0_TRLX_RELAXED + +config OR0_EHTR + hex + default 0x0 if OR0_EHTR_NORMAL + default 0x2 if OR0_EHTR_1_CYCLE + default 0x0 if OR0_EHTR_4_CYCLE + default 0x2 if OR0_EHTR_8_CYCLE + +config OR0_EAD + hex + default 0x0 if ARCH_MPC8308 + default 0x0 if OR0_EAD_NONE + default 0x1 if OR0_EAD_EXTRA diff --git a/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc1 b/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc1 new file mode 100644 index 0000000000..08dcc7dd2b --- /dev/null +++ b/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc1 @@ -0,0 +1,733 @@ +menuconfig ELBC_BR1_OR1 + bool "ELBC BR1/OR1" + +if ELBC_BR1_OR1 + +config BR1_OR1_NAME + string "Identifier" + +config BR1_OR1_BASE + hex "Port base" + +choice + prompt "Port size" + +config BR1_PORTSIZE_8BIT + bool "8-bit" + +config BR1_PORTSIZE_16BIT + depends on !BR1_MACHINE_FCM + bool "16-bit" + + +config BR1_PORTSIZE_32BIT + depends on !BR1_MACHINE_FCM + depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379 + bool "32-bit" + +endchoice + +if BR1_MACHINE_FCM + +choice + prompt "Data Error Checking" + +config BR1_ERRORCHECKING_DISABLED + bool "Disabled" + +config BR1_ERRORCHECKING_ECC_CHECKING + bool "ECC checking / No ECC generation" + +config BR1_ERRORCHECKING_BOTH + bool "ECC checking and generation" + +endchoice + +endif + +config BR1_WRITE_PROTECT + bool "Write-protect" + +config BR1_MACHINE_UPM + bool + +choice + prompt "Machine select" + +config BR1_MACHINE_GPCM + bool "GPCM" + +config BR1_MACHINE_FCM + depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360 + bool "FCM" + +config BR1_MACHINE_SDRAM + depends on ARCH_MPC8349 || ARCH_MPC8360 + bool "SDRAM" + +config BR1_MACHINE_UPMA + select BR1_MACHINE_UPM + bool "UPM (A)" + +config BR1_MACHINE_UPMB + select BR1_MACHINE_UPM + bool "UPM (B)" + +config BR1_MACHINE_UPMC + select BR1_MACHINE_UPM + bool "UPM (C)" + +endchoice + +if ARCH_MPC8313 || ARCH_MPC8323 || ARCH_MPC8360 + +choice + prompt "Atomic operations" + +config BR1_ATOMIC_NONE + bool "No atomic operations" + +config BR1_ATOMIC_RAWA + bool "Read-after-write-atomic" + +config BR1_ATOMIC_WARA + bool "Write-after-read-atomic" + +endchoice + +endif + +if BR1_MACHINE_GPCM || BR1_MACHINE_FCM || BR1_MACHINE_UPM || BR1_MACHINE_SDRAM + +choice + prompt "Address mask" + +config OR1_AM_32_KBYTES + depends on !BR1_MACHINE_SDRAM + bool "32 kb" + +config OR1_AM_64_KBYTES + bool "64 kb" + +config OR1_AM_128_KBYTES + bool "128 kb" + +config OR1_AM_256_KBYTES + bool "256 kb" + +config OR1_AM_512_KBYTES + bool "512 kb" + +config OR1_AM_1_MBYTES + bool "1 mb" + +config OR1_AM_2_MBYTES + bool "2 mb" + +config OR1_AM_4_MBYTES + bool "4 mb" + +config OR1_AM_8_MBYTES + bool "8 mb" + +config OR1_AM_16_MBYTES + bool "16 mb" + +config OR1_AM_32_MBYTES + bool "32 mb" + +config OR1_AM_64_MBYTES + bool "64 mb" + +# XXX: Some boards define 128MB AM with GPCM, even though it should not be +# possible according to the manuals +config OR1_AM_128_MBYTES + bool "128 mb" + +# XXX: Some boards define 256MB AM with GPCM, even though it should not be +# possible according to the manuals +config OR1_AM_256_MBYTES + bool "256 mb" + +config OR1_AM_512_MBYTES + depends on BR1_MACHINE_FCM + bool "512 mb" + +# XXX: Some boards define 1GB AM with GPCM, even though it should not be +# possible according to the manuals +config OR1_AM_1_GBYTES + bool "1 gb" + +config OR1_AM_2_GBYTES + depends on BR1_MACHINE_FCM + bool "2 gb" + +config OR1_AM_4_GBYTES + depends on BR1_MACHINE_FCM + bool "4 gb" + +endchoice + +config OR1_XAM_SET + bool "Set unused bytes after address mask" +choice + prompt "Buffer control disable" + +config OR1_BCTLD_ASSERTED + bool "Asserted" + +config OR1_BCTLD_NOT_ASSERTED + bool "Not asserted" + +endchoice + +endif + +if BR1_MACHINE_GPCM || BR1_MACHINE_FCM + +choice + prompt "Cycle length in bus clocks" + +config OR1_SCY_0 + bool "No wait states" + +config OR1_SCY_1 + bool "1 wait state" + +config OR1_SCY_2 + bool "2 wait states" + +config OR1_SCY_3 + bool "3 wait states" + +config OR1_SCY_4 + bool "4 wait states" + +config OR1_SCY_5 + bool "5 wait states" + +config OR1_SCY_6 + bool "6 wait states" + +config OR1_SCY_7 + bool "7 wait states" + +config OR1_SCY_8 + depends on BR1_MACHINE_GPCM + bool "8 wait states" + +config OR1_SCY_9 + depends on BR1_MACHINE_GPCM + bool "9 wait states" + +config OR1_SCY_10 + depends on BR1_MACHINE_GPCM + bool "10 wait states" + +config OR1_SCY_11 + depends on BR1_MACHINE_GPCM + bool "11 wait states" + +config OR1_SCY_12 + depends on BR1_MACHINE_GPCM + bool "12 wait states" + +config OR1_SCY_13 + depends on BR1_MACHINE_GPCM + bool "13 wait states" + +config OR1_SCY_14 + depends on BR1_MACHINE_GPCM + bool "14 wait states" + +config OR1_SCY_15 + depends on BR1_MACHINE_GPCM + bool "15 wait states" + +endchoice + +endif # BR1_MACHINE_GPCM || BR1_MACHINE_FCM + +if BR1_MACHINE_GPCM + +choice + prompt "Chip select negotiation time" + +config OR1_CSNT_NORMAL + bool "Normal" + +config OR1_CSNT_EARLIER + bool "Earlier" + +endchoice + +choice + prompt "Address to chip-select setup" + +config OR1_ACS_SAME_TIME + bool "At the same time" + +config OR1_ACS_HALF_CYCLE_EARLIER + bool "Half of a bus clock cycle earlier" + +config OR1_ACS_QUARTER_CYCLE_EARLIER + bool "Half/Quarter of a bus clock cycle earlier" + +endchoice + +choice + prompt "Extra address to check-select setup" + +config OR1_XACS_NORMAL + bool "Normal" + +config OR1_XACS_EXTENDED + bool "Extended" + +endchoice + +choice + prompt "External address termination" + +config OR1_SETA_INTERNAL + bool "Access is terminated internally" + +config OR1_SETA_EXTERNAL + bool "Access is terminated externally" + +endchoice + +endif # BR1_MACHINE_GPCM + +if BR1_MACHINE_FCM + +choice + prompt "NAND Flash EEPROM page size" + +config OR1_PGS_SMALL + bool "Small page device" + +config OR1_PGS_LARGE + bool "Large page device" + +endchoice + +choice + prompt "Chip select to command time" + +config OR1_CSCT_1_CYCLE + depends on OR1_TRLX_NORMAL + bool "1 cycle" + +config OR1_CSCT_2_CYCLE + depends on OR1_TRLX_RELAXED + bool "2 cycles" + +config OR1_CSCT_4_CYCLE + depends on OR1_TRLX_NORMAL + bool "4 cycles" + +config OR1_CSCT_8_CYCLE + depends on OR1_TRLX_RELAXED + bool "8 cycles" + +endchoice + +choice + prompt "Command setup time" + +config OR1_CST_COINCIDENT + depends on OR1_TRLX_NORMAL + bool "Coincident with any command" + +config OR1_CST_QUARTER_CLOCK + depends on OR1_TRLX_NORMAL + bool "0.25 clocks after" + +config OR1_CST_HALF_CLOCK + depends on OR1_TRLX_RELAXED + bool "0.5 clocks after" + +config OR1_CST_ONE_CLOCK + depends on OR1_TRLX_RELAXED + bool "1 clock after" + +endchoice + +choice + prompt "Command hold time" + +config OR1_CHT_HALF_CLOCK + depends on OR1_TRLX_NORMAL + bool "0.5 clocks before" + +config OR1_CHT_ONE_CLOCK + depends on OR1_TRLX_NORMAL + bool "1 clock before" + +config OR1_CHT_ONE_HALF_CLOCK + depends on OR1_TRLX_RELAXED + bool "1.5 clocks before" + +config OR1_CHT_TWO_CLOCK + depends on OR1_TRLX_RELAXED + bool "2 clocks before" + +endchoice + +choice + prompt "Reset setup time" + +config OR1_RST_THREE_QUARTER_CLOCK + depends on OR1_TRLX_NORMAL + bool "0.75 clocks prior" + +config OR1_RST_ONE_HALF_CLOCK + depends on OR1_TRLX_RELAXED + bool "0.5 clocks prior" + +config OR1_RST_ONE_CLOCK + bool "1 clock prior" + +endchoice + +endif # BR1_MACHINE_FCM + +if BR1_MACHINE_UPM + +choice + prompt "Burst inhibit" + +config OR1_BI_BURSTSUPPORT + bool "Support burst access" + +config OR1_BI_BURSTINHIBIT + bool "Inhibit burst access" + +endchoice + +endif # BR1_MACHINE_UPM + +if BR1_MACHINE_SDRAM + +choice + prompt "Number of column address lines" + +config OR1_COLS_7 + bool "7" + +config OR1_COLS_8 + bool "8" + +config OR1_COLS_9 + bool "9" + +config OR1_COLS_10 + bool "10" + +config OR1_COLS_11 + bool "11" + +config OR1_COLS_12 + bool "12" + +config OR1_COLS_13 + bool "13" + +config OR1_COLS_14 + bool "14" + +endchoice + +choice + prompt "Number of rows address lines" + +config OR1_ROWS_9 + bool "9" + +config OR1_ROWS_10 + bool "10" + +config OR1_ROWS_11 + bool "11" + +config OR1_ROWS_12 + bool "12" + +config OR1_ROWS_13 + bool "13" + +config OR1_ROWS_14 + bool "14" + +config OR1_ROWS_15 + bool "15" + +endchoice + +choice + prompt "Page mode select" + +config OR1_PMSEL_BTB + bool "Back-to-back" + +config OR1_PMSEL_KEPT_OPEN + bool "Page kept open until page miss or refresh" + +endchoice + +endif # BR1_MACHINE_SDRAM + +choice + prompt "Relaxed timing" + +config OR1_TRLX_NORMAL + bool "Normal" + +config OR1_TRLX_RELAXED + bool "Relaxed" + +endchoice + +choice + prompt "Extended hold time" + +config OR1_EHTR_NORMAL + depends on OR1_TRLX_NORMAL + bool "Normal" + +config OR1_EHTR_1_CYCLE + depends on OR1_TRLX_NORMAL + bool "1 idle clock cycle inserted" + +config OR1_EHTR_4_CYCLE + depends on OR1_TRLX_RELAXED + bool "4 idle clock cycles inserted" + +config OR1_EHTR_8_CYCLE + depends on OR1_TRLX_RELAXED + bool "8 idle clock cycles inserted" + +endchoice + +if !ARCH_MPC8308 + +choice + prompt "External address latch delay" + +config OR1_EAD_NONE + bool "None" + +config OR1_EAD_EXTRA + bool "Extra" + +endchoice + +endif # !ARCH_MPC8308 + +endif # ELBC_BR1_OR1 + +config BR1_PORTSIZE + hex + default 0x800 if BR1_PORTSIZE_8BIT + default 0x1000 if BR1_PORTSIZE_16BIT + default 0x1800 if BR1_PORTSIZE_32BIT + +config BR1_ERRORCHECKING + hex + default 0x0 if !BR1_MACHINE_FCM + default 0x0 if BR1_ERRORCHECKING_DISABLED + default 0x200 if BR1_ERRORCHECKING_ECC_CHECKING + default 0x400 if BR1_ERRORCHECKING_BOTH + +config BR1_WRITE_PROTECT_BIT + hex + default 0x0 if !BR1_WRITE_PROTECT + default 0x100 if BR1_WRITE_PROTECT + +config BR1_MACHINE + hex + default 0x0 if BR1_MACHINE_GPCM + default 0x20 if BR1_MACHINE_FCM + default 0x60 if BR1_MACHINE_SDRAM + default 0x80 if BR1_MACHINE_UPMA + default 0xa0 if BR1_MACHINE_UPMB + default 0xc0 if BR1_MACHINE_UPMC + +config BR1_ATOMIC + hex + default 0x0 if !ARCH_MPC8313 && !ARCH_MPC8323 && !ARCH_MPC8360 + default 0x0 if BR1_ATOMIC_NONE + default 0x4 if BR1_ATOMIC_RAWA + default 0x8 if BR1_ATOMIC_WARA + +config BR1_VALID_BIT + hex + default 0x0 if !ELBC_BR1_OR1 + default 0x1 if ELBC_BR1_OR1 + +config OR1_AM + hex + default 0xffff8000 if OR1_AM_32_KBYTES && !BR1_MACHINE_SDRAM + default 0xffff0000 if OR1_AM_64_KBYTES + default 0xfffe0000 if OR1_AM_128_KBYTES + default 0xfffc0000 if OR1_AM_256_KBYTES + default 0xfff80000 if OR1_AM_512_KBYTES + default 0xfff00000 if OR1_AM_1_MBYTES + default 0xffe00000 if OR1_AM_2_MBYTES + default 0xffc00000 if OR1_AM_4_MBYTES + default 0xff800000 if OR1_AM_8_MBYTES + default 0xff000000 if OR1_AM_16_MBYTES + default 0xfe000000 if OR1_AM_32_MBYTES + default 0xfc000000 if OR1_AM_64_MBYTES + default 0xf8000000 if OR1_AM_128_MBYTES + default 0xf0000000 if OR1_AM_256_MBYTES + default 0xe0000000 if OR1_AM_512_MBYTES + default 0xc0000000 if OR1_AM_1_GBYTES + default 0x80000000 if OR1_AM_2_GBYTES + default 0x00000000 if OR1_AM_4_GBYTES + +config OR1_XAM + hex + default 0x0 if !OR1_XAM_SET + default 0x6000 if OR1_XAM_SET + +config OR1_BCTLD + hex + default 0x0 if OR1_BCTLD_ASSERTED + default 0x1000 if OR1_BCTLD_NOT_ASSERTED + +config OR1_BI + hex + default 0x0 if !BR1_MACHINE_UPM + default 0x0 if OR1_BI_BURSTSUPPORT + default 0x100 if OR1_BI_BURSTINHIBIT + +config OR1_COLS + hex + default 0x0 if !BR1_MACHINE_SDRAM + default 0x0 if OR1_COLS_7 + default 0x400 if OR1_COLS_8 + default 0x800 if OR1_COLS_9 + default 0xc00 if OR1_COLS_10 + default 0x1000 if OR1_COLS_11 + default 0x1400 if OR1_COLS_12 + default 0x1800 if OR1_COLS_13 + default 0x1c00 if OR1_COLS_14 + +config OR1_ROWS + hex + default 0x0 if !BR1_MACHINE_SDRAM + default 0x0 if OR1_ROWS_9 + default 0x40 if OR1_ROWS_10 + default 0x80 if OR1_ROWS_11 + default 0xc0 if OR1_ROWS_12 + default 0x100 if OR1_ROWS_13 + default 0x140 if OR1_ROWS_14 + default 0x180 if OR1_ROWS_15 + +config OR1_PMSEL + hex + default 0x0 if !BR1_MACHINE_SDRAM + default 0x0 if OR1_PMSEL_BTB + default 0x20 if OR1_PMSEL_KEPT_OPEN + +config OR1_SCY + hex + default 0x0 if !BR1_MACHINE_GPCM && !BR1_MACHINE_FCM + default 0x0 if OR1_SCY_0 + default 0x10 if OR1_SCY_1 + default 0x20 if OR1_SCY_2 + default 0x30 if OR1_SCY_3 + default 0x40 if OR1_SCY_4 + default 0x50 if OR1_SCY_5 + default 0x60 if OR1_SCY_6 + default 0x70 if OR1_SCY_7 + default 0x80 if OR1_SCY_8 + default 0x90 if OR1_SCY_9 + default 0xa0 if OR1_SCY_10 + default 0xb0 if OR1_SCY_11 + default 0xc0 if OR1_SCY_12 + default 0xd0 if OR1_SCY_13 + default 0xe0 if OR1_SCY_14 + default 0xf0 if OR1_SCY_15 + +config OR1_PGS + hex + default 0x0 if !BR1_MACHINE_FCM + default 0x0 if OR1_PGS_SMALL + default 0x400 if OR1_PGS_LARGE + +config OR1_CSCT + hex + default 0x0 if !BR1_MACHINE_FCM + default 0x0 if OR1_CSCT_1_CYCLE + default 0x0 if OR1_CSCT_2_CYCLE + default 0x200 if OR1_CSCT_4_CYCLE + default 0x200 if OR1_CSCT_8_CYCLE + +config OR1_CST + hex + default 0x0 if !BR1_MACHINE_FCM + default 0x0 if OR1_CST_COINCIDENT + default 0x100 if OR1_CST_QUARTER_CLOCK + default 0x0 if OR1_CST_HALF_CLOCK + default 0x100 if OR1_CST_ONE_CLOCK + +config OR1_CHT + hex + default 0x0 if !BR1_MACHINE_FCM + default 0x0 if OR1_CHT_HALF_CLOCK + default 0x80 if OR1_CHT_ONE_CLOCK + default 0x0 if OR1_CHT_ONE_HALF_CLOCK + default 0x80 if OR1_CHT_TWO_CLOCK + +config OR1_RST + hex + default 0x0 if !BR1_MACHINE_FCM + default 0x0 if OR1_RST_THREE_QUARTER_CLOCK + default 0x8 if OR1_RST_ONE_CLOCK + default 0x0 if OR1_RST_ONE_HALF_CLOCK + +config OR1_CSNT + hex + default 0x0 if !BR1_MACHINE_GPCM + default 0x0 if OR1_CSNT_NORMAL + default 0x800 if OR1_CSNT_EARLIER + +config OR1_ACS + hex + default 0x0 if !BR1_MACHINE_GPCM + default 0x0 if OR1_ACS_SAME_TIME + default 0x400 if OR1_ACS_QUARTER_CYCLE_EARLIER + default 0x600 if OR1_ACS_HALF_CYCLE_EARLIER + +config OR1_XACS + hex + default 0x0 if !BR1_MACHINE_GPCM + default 0x0 if OR1_XACS_NORMAL + default 0x100 if OR1_XACS_EXTENDED + +config OR1_SETA + hex + default 0x0 if !BR1_MACHINE_GPCM + default 0x0 if OR1_SETA_INTERNAL + default 0x8 if OR1_SETA_EXTERNAL + +config OR1_TRLX + hex + default 0x0 if OR1_TRLX_NORMAL + default 0x4 if OR1_TRLX_RELAXED + +config OR1_EHTR + hex + default 0x0 if OR1_EHTR_NORMAL + default 0x2 if OR1_EHTR_1_CYCLE + default 0x0 if OR1_EHTR_4_CYCLE + default 0x2 if OR1_EHTR_8_CYCLE + +config OR1_EAD + hex + default 0x0 if ARCH_MPC8308 + default 0x0 if OR1_EAD_NONE + default 0x1 if OR1_EAD_EXTRA diff --git a/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc2 b/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc2 new file mode 100644 index 0000000000..298d87f5e0 --- /dev/null +++ b/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc2 @@ -0,0 +1,733 @@ +menuconfig ELBC_BR2_OR2 + bool "ELBC BR2/OR2" + +if ELBC_BR2_OR2 + +config BR2_OR2_NAME + string "Identifier" + +config BR2_OR2_BASE + hex "Port base" + +choice + prompt "Port size" + +config BR2_PORTSIZE_8BIT + bool "8-bit" + +config BR2_PORTSIZE_16BIT + depends on !BR2_MACHINE_FCM + bool "16-bit" + + +config BR2_PORTSIZE_32BIT + depends on !BR2_MACHINE_FCM + depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379 + bool "32-bit" + +endchoice + +if BR2_MACHINE_FCM + +choice + prompt "Data Error Checking" + +config BR2_ERRORCHECKING_DISABLED + bool "Disabled" + +config BR2_ERRORCHECKING_ECC_CHECKING + bool "ECC checking / No ECC generation" + +config BR2_ERRORCHECKING_BOTH + bool "ECC checking and generation" + +endchoice + +endif + +config BR2_WRITE_PROTECT + bool "Write-protect" + +config BR2_MACHINE_UPM + bool + +choice + prompt "Machine select" + +config BR2_MACHINE_GPCM + bool "GPCM" + +config BR2_MACHINE_FCM + depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360 + bool "FCM" + +config BR2_MACHINE_SDRAM + depends on ARCH_MPC8349 || ARCH_MPC8360 + bool "SDRAM" + +config BR2_MACHINE_UPMA + select BR2_MACHINE_UPM + bool "UPM (A)" + +config BR2_MACHINE_UPMB + select BR2_MACHINE_UPM + bool "UPM (B)" + +config BR2_MACHINE_UPMC + select BR2_MACHINE_UPM + bool "UPM (C)" + +endchoice + +if ARCH_MPC8313 || ARCH_MPC8323 || ARCH_MPC8360 + +choice + prompt "Atomic operations" + +config BR2_ATOMIC_NONE + bool "No atomic operations" + +config BR2_ATOMIC_RAWA + bool "Read-after-write-atomic" + +config BR2_ATOMIC_WARA + bool "Write-after-read-atomic" + +endchoice + +endif + +if BR2_MACHINE_GPCM || BR2_MACHINE_FCM || BR2_MACHINE_UPM || BR2_MACHINE_SDRAM + +choice + prompt "Address mask" + +config OR2_AM_32_KBYTES + depends on !BR2_MACHINE_SDRAM + bool "32 kb" + +config OR2_AM_64_KBYTES + bool "64 kb" + +config OR2_AM_128_KBYTES + bool "128 kb" + +config OR2_AM_256_KBYTES + bool "256 kb" + +config OR2_AM_512_KBYTES + bool "512 kb" + +config OR2_AM_1_MBYTES + bool "1 mb" + +config OR2_AM_2_MBYTES + bool "2 mb" + +config OR2_AM_4_MBYTES + bool "4 mb" + +config OR2_AM_8_MBYTES + bool "8 mb" + +config OR2_AM_16_MBYTES + bool "16 mb" + +config OR2_AM_32_MBYTES + bool "32 mb" + +config OR2_AM_64_MBYTES + bool "64 mb" + +# XXX: Some boards define 128MB AM with GPCM, even though it should not be +# possible according to the manuals +config OR2_AM_128_MBYTES + bool "128 mb" + +# XXX: Some boards define 256MB AM with GPCM, even though it should not be +# possible according to the manuals +config OR2_AM_256_MBYTES + bool "256 mb" + +config OR2_AM_512_MBYTES + depends on BR2_MACHINE_FCM + bool "512 mb" + +# XXX: Some boards define 1GB AM with GPCM, even though it should not be +# possible according to the manuals +config OR2_AM_1_GBYTES + bool "1 gb" + +config OR2_AM_2_GBYTES + depends on BR2_MACHINE_FCM + bool "2 gb" + +config OR2_AM_4_GBYTES + depends on BR2_MACHINE_FCM + bool "4 gb" + +endchoice + +config OR2_XAM_SET + bool "Set unused bytes after address mask" +choice + prompt "Buffer control disable" + +config OR2_BCTLD_ASSERTED + bool "Asserted" + +config OR2_BCTLD_NOT_ASSERTED + bool "Not asserted" + +endchoice + +endif + +if BR2_MACHINE_GPCM || BR2_MACHINE_FCM + +choice + prompt "Cycle length in bus clocks" + +config OR2_SCY_0 + bool "No wait states" + +config OR2_SCY_1 + bool "1 wait state" + +config OR2_SCY_2 + bool "2 wait states" + +config OR2_SCY_3 + bool "3 wait states" + +config OR2_SCY_4 + bool "4 wait states" + +config OR2_SCY_5 + bool "5 wait states" + +config OR2_SCY_6 + bool "6 wait states" + +config OR2_SCY_7 + bool "7 wait states" + +config OR2_SCY_8 + depends on BR2_MACHINE_GPCM + bool "8 wait states" + +config OR2_SCY_9 + depends on BR2_MACHINE_GPCM + bool "9 wait states" + +config OR2_SCY_10 + depends on BR2_MACHINE_GPCM + bool "10 wait states" + +config OR2_SCY_11 + depends on BR2_MACHINE_GPCM + bool "11 wait states" + +config OR2_SCY_12 + depends on BR2_MACHINE_GPCM + bool "12 wait states" + +config OR2_SCY_13 + depends on BR2_MACHINE_GPCM + bool "13 wait states" + +config OR2_SCY_14 + depends on BR2_MACHINE_GPCM + bool "14 wait states" + +config OR2_SCY_15 + depends on BR2_MACHINE_GPCM + bool "15 wait states" + +endchoice + +endif # BR2_MACHINE_GPCM || BR2_MACHINE_FCM + +if BR2_MACHINE_GPCM + +choice + prompt "Chip select negotiation time" + +config OR2_CSNT_NORMAL + bool "Normal" + +config OR2_CSNT_EARLIER + bool "Earlier" + +endchoice + +choice + prompt "Address to chip-select setup" + +config OR2_ACS_SAME_TIME + bool "At the same time" + +config OR2_ACS_HALF_CYCLE_EARLIER + bool "Half of a bus clock cycle earlier" + +config OR2_ACS_QUARTER_CYCLE_EARLIER + bool "Half/Quarter of a bus clock cycle earlier" + +endchoice + +choice + prompt "Extra address to check-select setup" + +config OR2_XACS_NORMAL + bool "Normal" + +config OR2_XACS_EXTENDED + bool "Extended" + +endchoice + +choice + prompt "External address termination" + +config OR2_SETA_INTERNAL + bool "Access is terminated internally" + +config OR2_SETA_EXTERNAL + bool "Access is terminated externally" + +endchoice + +endif # BR2_MACHINE_GPCM + +if BR2_MACHINE_FCM + +choice + prompt "NAND Flash EEPROM page size" + +config OR2_PGS_SMALL + bool "Small page device" + +config OR2_PGS_LARGE + bool "Large page device" + +endchoice + +choice + prompt "Chip select to command time" + +config OR2_CSCT_1_CYCLE + depends on OR2_TRLX_NORMAL + bool "1 cycle" + +config OR2_CSCT_2_CYCLE + depends on OR2_TRLX_RELAXED + bool "2 cycles" + +config OR2_CSCT_4_CYCLE + depends on OR2_TRLX_NORMAL + bool "4 cycles" + +config OR2_CSCT_8_CYCLE + depends on OR2_TRLX_RELAXED + bool "8 cycles" + +endchoice + +choice + prompt "Command setup time" + +config OR2_CST_COINCIDENT + depends on OR2_TRLX_NORMAL + bool "Coincident with any command" + +config OR2_CST_QUARTER_CLOCK + depends on OR2_TRLX_NORMAL + bool "0.25 clocks after" + +config OR2_CST_HALF_CLOCK + depends on OR2_TRLX_RELAXED + bool "0.5 clocks after" + +config OR2_CST_ONE_CLOCK + depends on OR2_TRLX_RELAXED + bool "1 clock after" + +endchoice + +choice + prompt "Command hold time" + +config OR2_CHT_HALF_CLOCK + depends on OR2_TRLX_NORMAL + bool "0.5 clocks before" + +config OR2_CHT_ONE_CLOCK + depends on OR2_TRLX_NORMAL + bool "1 clock before" + +config OR2_CHT_ONE_HALF_CLOCK + depends on OR2_TRLX_RELAXED + bool "1.5 clocks before" + +config OR2_CHT_TWO_CLOCK + depends on OR2_TRLX_RELAXED + bool "2 clocks before" + +endchoice + +choice + prompt "Reset setup time" + +config OR2_RST_THREE_QUARTER_CLOCK + depends on OR2_TRLX_NORMAL + bool "0.75 clocks prior" + +config OR2_RST_ONE_HALF_CLOCK + depends on OR2_TRLX_RELAXED + bool "0.5 clocks prior" + +config OR2_RST_ONE_CLOCK + bool "1 clock prior" + +endchoice + +endif # BR2_MACHINE_FCM + +if BR2_MACHINE_UPM + +choice + prompt "Burst inhibit" + +config OR2_BI_BURSTSUPPORT + bool "Support burst access" + +config OR2_BI_BURSTINHIBIT + bool "Inhibit burst access" + +endchoice + +endif # BR2_MACHINE_UPM + +if BR2_MACHINE_SDRAM + +choice + prompt "Number of column address lines" + +config OR2_COLS_7 + bool "7" + +config OR2_COLS_8 + bool "8" + +config OR2_COLS_9 + bool "9" + +config OR2_COLS_10 + bool "10" + +config OR2_COLS_11 + bool "11" + +config OR2_COLS_12 + bool "12" + +config OR2_COLS_13 + bool "13" + +config OR2_COLS_14 + bool "14" + +endchoice + +choice + prompt "Number of rows address lines" + +config OR2_ROWS_9 + bool "9" + +config OR2_ROWS_10 + bool "10" + +config OR2_ROWS_11 + bool "11" + +config OR2_ROWS_12 + bool "12" + +config OR2_ROWS_13 + bool "13" + +config OR2_ROWS_14 + bool "14" + +config OR2_ROWS_15 + bool "15" + +endchoice + +choice + prompt "Page mode select" + +config OR2_PMSEL_BTB + bool "Back-to-back" + +config OR2_PMSEL_KEPT_OPEN + bool "Page kept open until page miss or refresh" + +endchoice + +endif # BR2_MACHINE_SDRAM + +choice + prompt "Relaxed timing" + +config OR2_TRLX_NORMAL + bool "Normal" + +config OR2_TRLX_RELAXED + bool "Relaxed" + +endchoice + +choice + prompt "Extended hold time" + +config OR2_EHTR_NORMAL + depends on OR2_TRLX_NORMAL + bool "Normal" + +config OR2_EHTR_1_CYCLE + depends on OR2_TRLX_NORMAL + bool "1 idle clock cycle inserted" + +config OR2_EHTR_4_CYCLE + depends on OR2_TRLX_RELAXED + bool "4 idle clock cycles inserted" + +config OR2_EHTR_8_CYCLE + depends on OR2_TRLX_RELAXED + bool "8 idle clock cycles inserted" + +endchoice + +if !ARCH_MPC8308 + +choice + prompt "External address latch delay" + +config OR2_EAD_NONE + bool "None" + +config OR2_EAD_EXTRA + bool "Extra" + +endchoice + +endif # !ARCH_MPC8308 + +endif # ELBC_BR2_OR2 + +config BR2_PORTSIZE + hex + default 0x800 if BR2_PORTSIZE_8BIT + default 0x1000 if BR2_PORTSIZE_16BIT + default 0x1800 if BR2_PORTSIZE_32BIT + +config BR2_ERRORCHECKING + hex + default 0x0 if !BR2_MACHINE_FCM + default 0x0 if BR2_ERRORCHECKING_DISABLED + default 0x200 if BR2_ERRORCHECKING_ECC_CHECKING + default 0x400 if BR2_ERRORCHECKING_BOTH + +config BR2_WRITE_PROTECT_BIT + hex + default 0x0 if !BR2_WRITE_PROTECT + default 0x100 if BR2_WRITE_PROTECT + +config BR2_MACHINE + hex + default 0x0 if BR2_MACHINE_GPCM + default 0x20 if BR2_MACHINE_FCM + default 0x60 if BR2_MACHINE_SDRAM + default 0x80 if BR2_MACHINE_UPMA + default 0xa0 if BR2_MACHINE_UPMB + default 0xc0 if BR2_MACHINE_UPMC + +config BR2_ATOMIC + hex + default 0x0 if !ARCH_MPC8313 && !ARCH_MPC8323 && !ARCH_MPC8360 + default 0x0 if BR2_ATOMIC_NONE + default 0x4 if BR2_ATOMIC_RAWA + default 0x8 if BR2_ATOMIC_WARA + +config BR2_VALID_BIT + hex + default 0x0 if !ELBC_BR2_OR2 + default 0x1 if ELBC_BR2_OR2 + +config OR2_AM + hex + default 0xffff8000 if OR2_AM_32_KBYTES && !BR2_MACHINE_SDRAM + default 0xffff0000 if OR2_AM_64_KBYTES + default 0xfffe0000 if OR2_AM_128_KBYTES + default 0xfffc0000 if OR2_AM_256_KBYTES + default 0xfff80000 if OR2_AM_512_KBYTES + default 0xfff00000 if OR2_AM_1_MBYTES + default 0xffe00000 if OR2_AM_2_MBYTES + default 0xffc00000 if OR2_AM_4_MBYTES + default 0xff800000 if OR2_AM_8_MBYTES + default 0xff000000 if OR2_AM_16_MBYTES + default 0xfe000000 if OR2_AM_32_MBYTES + default 0xfc000000 if OR2_AM_64_MBYTES + default 0xf8000000 if OR2_AM_128_MBYTES + default 0xf0000000 if OR2_AM_256_MBYTES + default 0xe0000000 if OR2_AM_512_MBYTES + default 0xc0000000 if OR2_AM_1_GBYTES + default 0x80000000 if OR2_AM_2_GBYTES + default 0x00000000 if OR2_AM_4_GBYTES + +config OR2_XAM + hex + default 0x0 if !OR2_XAM_SET + default 0x6000 if OR2_XAM_SET + +config OR2_BCTLD + hex + default 0x0 if OR2_BCTLD_ASSERTED + default 0x1000 if OR2_BCTLD_NOT_ASSERTED + +config OR2_BI + hex + default 0x0 if !BR2_MACHINE_UPM + default 0x0 if OR2_BI_BURSTSUPPORT + default 0x100 if OR2_BI_BURSTINHIBIT + +config OR2_COLS + hex + default 0x0 if !BR2_MACHINE_SDRAM + default 0x0 if OR2_COLS_7 + default 0x400 if OR2_COLS_8 + default 0x800 if OR2_COLS_9 + default 0xc00 if OR2_COLS_10 + default 0x1000 if OR2_COLS_11 + default 0x1400 if OR2_COLS_12 + default 0x1800 if OR2_COLS_13 + default 0x1c00 if OR2_COLS_14 + +config OR2_ROWS + hex + default 0x0 if !BR2_MACHINE_SDRAM + default 0x0 if OR2_ROWS_9 + default 0x40 if OR2_ROWS_10 + default 0x80 if OR2_ROWS_11 + default 0xc0 if OR2_ROWS_12 + default 0x100 if OR2_ROWS_13 + default 0x140 if OR2_ROWS_14 + default 0x180 if OR2_ROWS_15 + +config OR2_PMSEL + hex + default 0x0 if !BR2_MACHINE_SDRAM + default 0x0 if OR2_PMSEL_BTB + default 0x20 if OR2_PMSEL_KEPT_OPEN + +config OR2_SCY + hex + default 0x0 if !BR2_MACHINE_GPCM && !BR2_MACHINE_FCM + default 0x0 if OR2_SCY_0 + default 0x10 if OR2_SCY_1 + default 0x20 if OR2_SCY_2 + default 0x30 if OR2_SCY_3 + default 0x40 if OR2_SCY_4 + default 0x50 if OR2_SCY_5 + default 0x60 if OR2_SCY_6 + default 0x70 if OR2_SCY_7 + default 0x80 if OR2_SCY_8 + default 0x90 if OR2_SCY_9 + default 0xa0 if OR2_SCY_10 + default 0xb0 if OR2_SCY_11 + default 0xc0 if OR2_SCY_12 + default 0xd0 if OR2_SCY_13 + default 0xe0 if OR2_SCY_14 + default 0xf0 if OR2_SCY_15 + +config OR2_PGS + hex + default 0x0 if !BR2_MACHINE_FCM + default 0x0 if OR2_PGS_SMALL + default 0x400 if OR2_PGS_LARGE + +config OR2_CSCT + hex + default 0x0 if !BR2_MACHINE_FCM + default 0x0 if OR2_CSCT_1_CYCLE + default 0x0 if OR2_CSCT_2_CYCLE + default 0x200 if OR2_CSCT_4_CYCLE + default 0x200 if OR2_CSCT_8_CYCLE + +config OR2_CST + hex + default 0x0 if !BR2_MACHINE_FCM + default 0x0 if OR2_CST_COINCIDENT + default 0x100 if OR2_CST_QUARTER_CLOCK + default 0x0 if OR2_CST_HALF_CLOCK + default 0x100 if OR2_CST_ONE_CLOCK + +config OR2_CHT + hex + default 0x0 if !BR2_MACHINE_FCM + default 0x0 if OR2_CHT_HALF_CLOCK + default 0x80 if OR2_CHT_ONE_CLOCK + default 0x0 if OR2_CHT_ONE_HALF_CLOCK + default 0x80 if OR2_CHT_TWO_CLOCK + +config OR2_RST + hex + default 0x0 if !BR2_MACHINE_FCM + default 0x0 if OR2_RST_THREE_QUARTER_CLOCK + default 0x8 if OR2_RST_ONE_CLOCK + default 0x0 if OR2_RST_ONE_HALF_CLOCK + +config OR2_CSNT + hex + default 0x0 if !BR2_MACHINE_GPCM + default 0x0 if OR2_CSNT_NORMAL + default 0x800 if OR2_CSNT_EARLIER + +config OR2_ACS + hex + default 0x0 if !BR2_MACHINE_GPCM + default 0x0 if OR2_ACS_SAME_TIME + default 0x400 if OR2_ACS_QUARTER_CYCLE_EARLIER + default 0x600 if OR2_ACS_HALF_CYCLE_EARLIER + +config OR2_XACS + hex + default 0x0 if !BR2_MACHINE_GPCM + default 0x0 if OR2_XACS_NORMAL + default 0x100 if OR2_XACS_EXTENDED + +config OR2_SETA + hex + default 0x0 if !BR2_MACHINE_GPCM + default 0x0 if OR2_SETA_INTERNAL + default 0x8 if OR2_SETA_EXTERNAL + +config OR2_TRLX + hex + default 0x0 if OR2_TRLX_NORMAL + default 0x4 if OR2_TRLX_RELAXED + +config OR2_EHTR + hex + default 0x0 if OR2_EHTR_NORMAL + default 0x2 if OR2_EHTR_1_CYCLE + default 0x0 if OR2_EHTR_4_CYCLE + default 0x2 if OR2_EHTR_8_CYCLE + +config OR2_EAD + hex + default 0x0 if ARCH_MPC8308 + default 0x0 if OR2_EAD_NONE + default 0x1 if OR2_EAD_EXTRA diff --git a/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc3 b/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc3 new file mode 100644 index 0000000000..963831bfcb --- /dev/null +++ b/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc3 @@ -0,0 +1,733 @@ +menuconfig ELBC_BR3_OR3 + bool "ELBC BR3/OR3" + +if ELBC_BR3_OR3 + +config BR3_OR3_NAME + string "Identifier" + +config BR3_OR3_BASE + hex "Port base" + +choice + prompt "Port size" + +config BR3_PORTSIZE_8BIT + bool "8-bit" + +config BR3_PORTSIZE_16BIT + depends on !BR3_MACHINE_FCM + bool "16-bit" + + +config BR3_PORTSIZE_32BIT + depends on !BR3_MACHINE_FCM + depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379 + bool "32-bit" + +endchoice + +if BR3_MACHINE_FCM + +choice + prompt "Data Error Checking" + +config BR3_ERRORCHECKING_DISABLED + bool "Disabled" + +config BR3_ERRORCHECKING_ECC_CHECKING + bool "ECC checking / No ECC generation" + +config BR3_ERRORCHECKING_BOTH + bool "ECC checking and generation" + +endchoice + +endif + +config BR3_WRITE_PROTECT + bool "Write-protect" + +config BR3_MACHINE_UPM + bool + +choice + prompt "Machine select" + +config BR3_MACHINE_GPCM + bool "GPCM" + +config BR3_MACHINE_FCM + depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360 + bool "FCM" + +config BR3_MACHINE_SDRAM + depends on ARCH_MPC8349 || ARCH_MPC8360 + bool "SDRAM" + +config BR3_MACHINE_UPMA + select BR3_MACHINE_UPM + bool "UPM (A)" + +config BR3_MACHINE_UPMB + select BR3_MACHINE_UPM + bool "UPM (B)" + +config BR3_MACHINE_UPMC + select BR3_MACHINE_UPM + bool "UPM (C)" + +endchoice + +if ARCH_MPC8313 || ARCH_MPC8323 || ARCH_MPC8360 + +choice + prompt "Atomic operations" + +config BR3_ATOMIC_NONE + bool "No atomic operations" + +config BR3_ATOMIC_RAWA + bool "Read-after-write-atomic" + +config BR3_ATOMIC_WARA + bool "Write-after-read-atomic" + +endchoice + +endif + +if BR3_MACHINE_GPCM || BR3_MACHINE_FCM || BR3_MACHINE_UPM || BR3_MACHINE_SDRAM + +choice + prompt "Address mask" + +config OR3_AM_32_KBYTES + depends on !BR3_MACHINE_SDRAM + bool "32 kb" + +config OR3_AM_64_KBYTES + bool "64 kb" + +config OR3_AM_128_KBYTES + bool "128 kb" + +config OR3_AM_256_KBYTES + bool "256 kb" + +config OR3_AM_512_KBYTES + bool "512 kb" + +config OR3_AM_1_MBYTES + bool "1 mb" + +config OR3_AM_2_MBYTES + bool "2 mb" + +config OR3_AM_4_MBYTES + bool "4 mb" + +config OR3_AM_8_MBYTES + bool "8 mb" + +config OR3_AM_16_MBYTES + bool "16 mb" + +config OR3_AM_32_MBYTES + bool "32 mb" + +config OR3_AM_64_MBYTES + bool "64 mb" + +# XXX: Some boards define 128MB AM with GPCM, even though it should not be +# possible according to the manuals +config OR3_AM_128_MBYTES + bool "128 mb" + +# XXX: Some boards define 256MB AM with GPCM, even though it should not be +# possible according to the manuals +config OR3_AM_256_MBYTES + bool "256 mb" + +config OR3_AM_512_MBYTES + depends on BR3_MACHINE_FCM + bool "512 mb" + +# XXX: Some boards define 1GB AM with GPCM, even though it should not be +# possible according to the manuals +config OR3_AM_1_GBYTES + bool "1 gb" + +config OR3_AM_2_GBYTES + depends on BR3_MACHINE_FCM + bool "2 gb" + +config OR3_AM_4_GBYTES + depends on BR3_MACHINE_FCM + bool "4 gb" + +endchoice + +config OR3_XAM_SET + bool "Set unused bytes after address mask" +choice + prompt "Buffer control disable" + +config OR3_BCTLD_ASSERTED + bool "Asserted" + +config OR3_BCTLD_NOT_ASSERTED + bool "Not asserted" + +endchoice + +endif + +if BR3_MACHINE_GPCM || BR3_MACHINE_FCM + +choice + prompt "Cycle length in bus clocks" + +config OR3_SCY_0 + bool "No wait states" + +config OR3_SCY_1 + bool "1 wait state" + +config OR3_SCY_2 + bool "2 wait states" + +config OR3_SCY_3 + bool "3 wait states" + +config OR3_SCY_4 + bool "4 wait states" + +config OR3_SCY_5 + bool "5 wait states" + +config OR3_SCY_6 + bool "6 wait states" + +config OR3_SCY_7 + bool "7 wait states" + +config OR3_SCY_8 + depends on BR3_MACHINE_GPCM + bool "8 wait states" + +config OR3_SCY_9 + depends on BR3_MACHINE_GPCM + bool "9 wait states" + +config OR3_SCY_10 + depends on BR3_MACHINE_GPCM + bool "10 wait states" + +config OR3_SCY_11 + depends on BR3_MACHINE_GPCM + bool "11 wait states" + +config OR3_SCY_12 + depends on BR3_MACHINE_GPCM + bool "12 wait states" + +config OR3_SCY_13 + depends on BR3_MACHINE_GPCM + bool "13 wait states" + +config OR3_SCY_14 + depends on BR3_MACHINE_GPCM + bool "14 wait states" + +config OR3_SCY_15 + depends on BR3_MACHINE_GPCM + bool "15 wait states" + +endchoice + +endif # BR3_MACHINE_GPCM || BR3_MACHINE_FCM + +if BR3_MACHINE_GPCM + +choice + prompt "Chip select negotiation time" + +config OR3_CSNT_NORMAL + bool "Normal" + +config OR3_CSNT_EARLIER + bool "Earlier" + +endchoice + +choice + prompt "Address to chip-select setup" + +config OR3_ACS_SAME_TIME + bool "At the same time" + +config OR3_ACS_HALF_CYCLE_EARLIER + bool "Half of a bus clock cycle earlier" + +config OR3_ACS_QUARTER_CYCLE_EARLIER + bool "Half/Quarter of a bus clock cycle earlier" + +endchoice + +choice + prompt "Extra address to check-select setup" + +config OR3_XACS_NORMAL + bool "Normal" + +config OR3_XACS_EXTENDED + bool "Extended" + +endchoice + +choice + prompt "External address termination" + +config OR3_SETA_INTERNAL + bool "Access is terminated internally" + +config OR3_SETA_EXTERNAL + bool "Access is terminated externally" + +endchoice + +endif # BR3_MACHINE_GPCM + +if BR3_MACHINE_FCM + +choice + prompt "NAND Flash EEPROM page size" + +config OR3_PGS_SMALL + bool "Small page device" + +config OR3_PGS_LARGE + bool "Large page device" + +endchoice + +choice + prompt "Chip select to command time" + +config OR3_CSCT_1_CYCLE + depends on OR3_TRLX_NORMAL + bool "1 cycle" + +config OR3_CSCT_2_CYCLE + depends on OR3_TRLX_RELAXED + bool "2 cycles" + +config OR3_CSCT_4_CYCLE + depends on OR3_TRLX_NORMAL + bool "4 cycles" + +config OR3_CSCT_8_CYCLE + depends on OR3_TRLX_RELAXED + bool "8 cycles" + +endchoice + +choice + prompt "Command setup time" + +config OR3_CST_COINCIDENT + depends on OR3_TRLX_NORMAL + bool "Coincident with any command" + +config OR3_CST_QUARTER_CLOCK + depends on OR3_TRLX_NORMAL + bool "0.25 clocks after" + +config OR3_CST_HALF_CLOCK + depends on OR3_TRLX_RELAXED + bool "0.5 clocks after" + +config OR3_CST_ONE_CLOCK + depends on OR3_TRLX_RELAXED + bool "1 clock after" + +endchoice + +choice + prompt "Command hold time" + +config OR3_CHT_HALF_CLOCK + depends on OR3_TRLX_NORMAL + bool "0.5 clocks before" + +config OR3_CHT_ONE_CLOCK + depends on OR3_TRLX_NORMAL + bool "1 clock before" + +config OR3_CHT_ONE_HALF_CLOCK + depends on OR3_TRLX_RELAXED + bool "1.5 clocks before" + +config OR3_CHT_TWO_CLOCK + depends on OR3_TRLX_RELAXED + bool "2 clocks before" + +endchoice + +choice + prompt "Reset setup time" + +config OR3_RST_THREE_QUARTER_CLOCK + depends on OR3_TRLX_NORMAL + bool "0.75 clocks prior" + +config OR3_RST_ONE_HALF_CLOCK + depends on OR3_TRLX_RELAXED + bool "0.5 clocks prior" + +config OR3_RST_ONE_CLOCK + bool "1 clock prior" + +endchoice + +endif # BR3_MACHINE_FCM + +if BR3_MACHINE_UPM + +choice + prompt "Burst inhibit" + +config OR3_BI_BURSTSUPPORT + bool "Support burst access" + +config OR3_BI_BURSTINHIBIT + bool "Inhibit burst access" + +endchoice + +endif # BR3_MACHINE_UPM + +if BR3_MACHINE_SDRAM + +choice + prompt "Number of column address lines" + +config OR3_COLS_7 + bool "7" + +config OR3_COLS_8 + bool "8" + +config OR3_COLS_9 + bool "9" + +config OR3_COLS_10 + bool "10" + +config OR3_COLS_11 + bool "11" + +config OR3_COLS_12 + bool "12" + +config OR3_COLS_13 + bool "13" + +config OR3_COLS_14 + bool "14" + +endchoice + +choice + prompt "Number of rows address lines" + +config OR3_ROWS_9 + bool "9" + +config OR3_ROWS_10 + bool "10" + +config OR3_ROWS_11 + bool "11" + +config OR3_ROWS_12 + bool "12" + +config OR3_ROWS_13 + bool "13" + +config OR3_ROWS_14 + bool "14" + +config OR3_ROWS_15 + bool "15" + +endchoice + +choice + prompt "Page mode select" + +config OR3_PMSEL_BTB + bool "Back-to-back" + +config OR3_PMSEL_KEPT_OPEN + bool "Page kept open until page miss or refresh" + +endchoice + +endif # BR3_MACHINE_SDRAM + +choice + prompt "Relaxed timing" + +config OR3_TRLX_NORMAL + bool "Normal" + +config OR3_TRLX_RELAXED + bool "Relaxed" + +endchoice + +choice + prompt "Extended hold time" + +config OR3_EHTR_NORMAL + depends on OR3_TRLX_NORMAL + bool "Normal" + +config OR3_EHTR_1_CYCLE + depends on OR3_TRLX_NORMAL + bool "1 idle clock cycle inserted" + +config OR3_EHTR_4_CYCLE + depends on OR3_TRLX_RELAXED + bool "4 idle clock cycles inserted" + +config OR3_EHTR_8_CYCLE + depends on OR3_TRLX_RELAXED + bool "8 idle clock cycles inserted" + +endchoice + +if !ARCH_MPC8308 + +choice + prompt "External address latch delay" + +config OR3_EAD_NONE + bool "None" + +config OR3_EAD_EXTRA + bool "Extra" + +endchoice + +endif # !ARCH_MPC8308 + +endif # ELBC_BR3_OR3 + +config BR3_PORTSIZE + hex + default 0x800 if BR3_PORTSIZE_8BIT + default 0x1000 if BR3_PORTSIZE_16BIT + default 0x1800 if BR3_PORTSIZE_32BIT + +config BR3_ERRORCHECKING + hex + default 0x0 if !BR3_MACHINE_FCM + default 0x0 if BR3_ERRORCHECKING_DISABLED + default 0x200 if BR3_ERRORCHECKING_ECC_CHECKING + default 0x400 if BR3_ERRORCHECKING_BOTH + +config BR3_WRITE_PROTECT_BIT + hex + default 0x0 if !BR3_WRITE_PROTECT + default 0x100 if BR3_WRITE_PROTECT + +config BR3_MACHINE + hex + default 0x0 if BR3_MACHINE_GPCM + default 0x20 if BR3_MACHINE_FCM + default 0x60 if BR3_MACHINE_SDRAM + default 0x80 if BR3_MACHINE_UPMA + default 0xa0 if BR3_MACHINE_UPMB + default 0xc0 if BR3_MACHINE_UPMC + +config BR3_ATOMIC + hex + default 0x0 if !ARCH_MPC8313 && !ARCH_MPC8323 && !ARCH_MPC8360 + default 0x0 if BR3_ATOMIC_NONE + default 0x4 if BR3_ATOMIC_RAWA + default 0x8 if BR3_ATOMIC_WARA + +config BR3_VALID_BIT + hex + default 0x0 if !ELBC_BR3_OR3 + default 0x1 if ELBC_BR3_OR3 + +config OR3_AM + hex + default 0xffff8000 if OR3_AM_32_KBYTES && !BR3_MACHINE_SDRAM + default 0xffff0000 if OR3_AM_64_KBYTES + default 0xfffe0000 if OR3_AM_128_KBYTES + default 0xfffc0000 if OR3_AM_256_KBYTES + default 0xfff80000 if OR3_AM_512_KBYTES + default 0xfff00000 if OR3_AM_1_MBYTES + default 0xffe00000 if OR3_AM_2_MBYTES + default 0xffc00000 if OR3_AM_4_MBYTES + default 0xff800000 if OR3_AM_8_MBYTES + default 0xff000000 if OR3_AM_16_MBYTES + default 0xfe000000 if OR3_AM_32_MBYTES + default 0xfc000000 if OR3_AM_64_MBYTES + default 0xf8000000 if OR3_AM_128_MBYTES + default 0xf0000000 if OR3_AM_256_MBYTES + default 0xe0000000 if OR3_AM_512_MBYTES + default 0xc0000000 if OR3_AM_1_GBYTES + default 0x80000000 if OR3_AM_2_GBYTES + default 0x00000000 if OR3_AM_4_GBYTES + +config OR3_XAM + hex + default 0x0 if !OR3_XAM_SET + default 0x6000 if OR3_XAM_SET + +config OR3_BCTLD + hex + default 0x0 if OR3_BCTLD_ASSERTED + default 0x1000 if OR3_BCTLD_NOT_ASSERTED + +config OR3_BI + hex + default 0x0 if !BR3_MACHINE_UPM + default 0x0 if OR3_BI_BURSTSUPPORT + default 0x100 if OR3_BI_BURSTINHIBIT + +config OR3_COLS + hex + default 0x0 if !BR3_MACHINE_SDRAM + default 0x0 if OR3_COLS_7 + default 0x400 if OR3_COLS_8 + default 0x800 if OR3_COLS_9 + default 0xc00 if OR3_COLS_10 + default 0x1000 if OR3_COLS_11 + default 0x1400 if OR3_COLS_12 + default 0x1800 if OR3_COLS_13 + default 0x1c00 if OR3_COLS_14 + +config OR3_ROWS + hex + default 0x0 if !BR3_MACHINE_SDRAM + default 0x0 if OR3_ROWS_9 + default 0x40 if OR3_ROWS_10 + default 0x80 if OR3_ROWS_11 + default 0xc0 if OR3_ROWS_12 + default 0x100 if OR3_ROWS_13 + default 0x140 if OR3_ROWS_14 + default 0x180 if OR3_ROWS_15 + +config OR3_PMSEL + hex + default 0x0 if !BR3_MACHINE_SDRAM + default 0x0 if OR3_PMSEL_BTB + default 0x20 if OR3_PMSEL_KEPT_OPEN + +config OR3_SCY + hex + default 0x0 if !BR3_MACHINE_GPCM && !BR3_MACHINE_FCM + default 0x0 if OR3_SCY_0 + default 0x10 if OR3_SCY_1 + default 0x20 if OR3_SCY_2 + default 0x30 if OR3_SCY_3 + default 0x40 if OR3_SCY_4 + default 0x50 if OR3_SCY_5 + default 0x60 if OR3_SCY_6 + default 0x70 if OR3_SCY_7 + default 0x80 if OR3_SCY_8 + default 0x90 if OR3_SCY_9 + default 0xa0 if OR3_SCY_10 + default 0xb0 if OR3_SCY_11 + default 0xc0 if OR3_SCY_12 + default 0xd0 if OR3_SCY_13 + default 0xe0 if OR3_SCY_14 + default 0xf0 if OR3_SCY_15 + +config OR3_PGS + hex + default 0x0 if !BR3_MACHINE_FCM + default 0x0 if OR3_PGS_SMALL + default 0x400 if OR3_PGS_LARGE + +config OR3_CSCT + hex + default 0x0 if !BR3_MACHINE_FCM + default 0x0 if OR3_CSCT_1_CYCLE + default 0x0 if OR3_CSCT_2_CYCLE + default 0x200 if OR3_CSCT_4_CYCLE + default 0x200 if OR3_CSCT_8_CYCLE + +config OR3_CST + hex + default 0x0 if !BR3_MACHINE_FCM + default 0x0 if OR3_CST_COINCIDENT + default 0x100 if OR3_CST_QUARTER_CLOCK + default 0x0 if OR3_CST_HALF_CLOCK + default 0x100 if OR3_CST_ONE_CLOCK + +config OR3_CHT + hex + default 0x0 if !BR3_MACHINE_FCM + default 0x0 if OR3_CHT_HALF_CLOCK + default 0x80 if OR3_CHT_ONE_CLOCK + default 0x0 if OR3_CHT_ONE_HALF_CLOCK + default 0x80 if OR3_CHT_TWO_CLOCK + +config OR3_RST + hex + default 0x0 if !BR3_MACHINE_FCM + default 0x0 if OR3_RST_THREE_QUARTER_CLOCK + default 0x8 if OR3_RST_ONE_CLOCK + default 0x0 if OR3_RST_ONE_HALF_CLOCK + +config OR3_CSNT + hex + default 0x0 if !BR3_MACHINE_GPCM + default 0x0 if OR3_CSNT_NORMAL + default 0x800 if OR3_CSNT_EARLIER + +config OR3_ACS + hex + default 0x0 if !BR3_MACHINE_GPCM + default 0x0 if OR3_ACS_SAME_TIME + default 0x400 if OR3_ACS_QUARTER_CYCLE_EARLIER + default 0x600 if OR3_ACS_HALF_CYCLE_EARLIER + +config OR3_XACS + hex + default 0x0 if !BR3_MACHINE_GPCM + default 0x0 if OR3_XACS_NORMAL + default 0x100 if OR3_XACS_EXTENDED + +config OR3_SETA + hex + default 0x0 if !BR3_MACHINE_GPCM + default 0x0 if OR3_SETA_INTERNAL + default 0x8 if OR3_SETA_EXTERNAL + +config OR3_TRLX + hex + default 0x0 if OR3_TRLX_NORMAL + default 0x4 if OR3_TRLX_RELAXED + +config OR3_EHTR + hex + default 0x0 if OR3_EHTR_NORMAL + default 0x2 if OR3_EHTR_1_CYCLE + default 0x0 if OR3_EHTR_4_CYCLE + default 0x2 if OR3_EHTR_8_CYCLE + +config OR3_EAD + hex + default 0x0 if ARCH_MPC8308 + default 0x0 if OR3_EAD_NONE + default 0x1 if OR3_EAD_EXTRA diff --git a/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc4 b/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc4 new file mode 100644 index 0000000000..0063dab962 --- /dev/null +++ b/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc4 @@ -0,0 +1,733 @@ +menuconfig ELBC_BR4_OR4 + bool "ELBC BR4/OR4" + +if ELBC_BR4_OR4 + +config BR4_OR4_NAME + string "Identifier" + +config BR4_OR4_BASE + hex "Port base" + +choice + prompt "Port size" + +config BR4_PORTSIZE_8BIT + bool "8-bit" + +config BR4_PORTSIZE_16BIT + depends on !BR4_MACHINE_FCM + bool "16-bit" + + +config BR4_PORTSIZE_32BIT + depends on !BR4_MACHINE_FCM + depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379 + bool "32-bit" + +endchoice + +if BR4_MACHINE_FCM + +choice + prompt "Data Error Checking" + +config BR4_ERRORCHECKING_DISABLED + bool "Disabled" + +config BR4_ERRORCHECKING_ECC_CHECKING + bool "ECC checking / No ECC generation" + +config BR4_ERRORCHECKING_BOTH + bool "ECC checking and generation" + +endchoice + +endif + +config BR4_WRITE_PROTECT + bool "Write-protect" + +config BR4_MACHINE_UPM + bool + +choice + prompt "Machine select" + +config BR4_MACHINE_GPCM + bool "GPCM" + +config BR4_MACHINE_FCM + depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360 + bool "FCM" + +config BR4_MACHINE_SDRAM + depends on ARCH_MPC8349 || ARCH_MPC8360 + bool "SDRAM" + +config BR4_MACHINE_UPMA + select BR4_MACHINE_UPM + bool "UPM (A)" + +config BR4_MACHINE_UPMB + select BR4_MACHINE_UPM + bool "UPM (B)" + +config BR4_MACHINE_UPMC + select BR4_MACHINE_UPM + bool "UPM (C)" + +endchoice + +if ARCH_MPC8313 || ARCH_MPC8323 || ARCH_MPC8360 + +choice + prompt "Atomic operations" + +config BR4_ATOMIC_NONE + bool "No atomic operations" + +config BR4_ATOMIC_RAWA + bool "Read-after-write-atomic" + +config BR4_ATOMIC_WARA + bool "Write-after-read-atomic" + +endchoice + +endif + +if BR4_MACHINE_GPCM || BR4_MACHINE_FCM || BR4_MACHINE_UPM || BR4_MACHINE_SDRAM + +choice + prompt "Address mask" + +config OR4_AM_32_KBYTES + depends on !BR4_MACHINE_SDRAM + bool "32 kb" + +config OR4_AM_64_KBYTES + bool "64 kb" + +config OR4_AM_128_KBYTES + bool "128 kb" + +config OR4_AM_256_KBYTES + bool "256 kb" + +config OR4_AM_512_KBYTES + bool "512 kb" + +config OR4_AM_1_MBYTES + bool "1 mb" + +config OR4_AM_2_MBYTES + bool "2 mb" + +config OR4_AM_4_MBYTES + bool "4 mb" + +config OR4_AM_8_MBYTES + bool "8 mb" + +config OR4_AM_16_MBYTES + bool "16 mb" + +config OR4_AM_32_MBYTES + bool "32 mb" + +config OR4_AM_64_MBYTES + bool "64 mb" + +# XXX: Some boards define 128MB AM with GPCM, even though it should not be +# possible according to the manuals +config OR4_AM_128_MBYTES + bool "128 mb" + +# XXX: Some boards define 256MB AM with GPCM, even though it should not be +# possible according to the manuals +config OR4_AM_256_MBYTES + bool "256 mb" + +config OR4_AM_512_MBYTES + depends on BR4_MACHINE_FCM + bool "512 mb" + +# XXX: Some boards define 1GB AM with GPCM, even though it should not be +# possible according to the manuals +config OR4_AM_1_GBYTES + bool "1 gb" + +config OR4_AM_2_GBYTES + depends on BR4_MACHINE_FCM + bool "2 gb" + +config OR4_AM_4_GBYTES + depends on BR4_MACHINE_FCM + bool "4 gb" + +endchoice + +config OR4_XAM_SET + bool "Set unused bytes after address mask" +choice + prompt "Buffer control disable" + +config OR4_BCTLD_ASSERTED + bool "Asserted" + +config OR4_BCTLD_NOT_ASSERTED + bool "Not asserted" + +endchoice + +endif + +if BR4_MACHINE_GPCM || BR4_MACHINE_FCM + +choice + prompt "Cycle length in bus clocks" + +config OR4_SCY_0 + bool "No wait states" + +config OR4_SCY_1 + bool "1 wait state" + +config OR4_SCY_2 + bool "2 wait states" + +config OR4_SCY_3 + bool "3 wait states" + +config OR4_SCY_4 + bool "4 wait states" + +config OR4_SCY_5 + bool "5 wait states" + +config OR4_SCY_6 + bool "6 wait states" + +config OR4_SCY_7 + bool "7 wait states" + +config OR4_SCY_8 + depends on BR4_MACHINE_GPCM + bool "8 wait states" + +config OR4_SCY_9 + depends on BR4_MACHINE_GPCM + bool "9 wait states" + +config OR4_SCY_10 + depends on BR4_MACHINE_GPCM + bool "10 wait states" + +config OR4_SCY_11 + depends on BR4_MACHINE_GPCM + bool "11 wait states" + +config OR4_SCY_12 + depends on BR4_MACHINE_GPCM + bool "12 wait states" + +config OR4_SCY_13 + depends on BR4_MACHINE_GPCM + bool "13 wait states" + +config OR4_SCY_14 + depends on BR4_MACHINE_GPCM + bool "14 wait states" + +config OR4_SCY_15 + depends on BR4_MACHINE_GPCM + bool "15 wait states" + +endchoice + +endif # BR4_MACHINE_GPCM || BR4_MACHINE_FCM + +if BR4_MACHINE_GPCM + +choice + prompt "Chip select negotiation time" + +config OR4_CSNT_NORMAL + bool "Normal" + +config OR4_CSNT_EARLIER + bool "Earlier" + +endchoice + +choice + prompt "Address to chip-select setup" + +config OR4_ACS_SAME_TIME + bool "At the same time" + +config OR4_ACS_HALF_CYCLE_EARLIER + bool "Half of a bus clock cycle earlier" + +config OR4_ACS_QUARTER_CYCLE_EARLIER + bool "Half/Quarter of a bus clock cycle earlier" + +endchoice + +choice + prompt "Extra address to check-select setup" + +config OR4_XACS_NORMAL + bool "Normal" + +config OR4_XACS_EXTENDED + bool "Extended" + +endchoice + +choice + prompt "External address termination" + +config OR4_SETA_INTERNAL + bool "Access is terminated internally" + +config OR4_SETA_EXTERNAL + bool "Access is terminated externally" + +endchoice + +endif # BR4_MACHINE_GPCM + +if BR4_MACHINE_FCM + +choice + prompt "NAND Flash EEPROM page size" + +config OR4_PGS_SMALL + bool "Small page device" + +config OR4_PGS_LARGE + bool "Large page device" + +endchoice + +choice + prompt "Chip select to command time" + +config OR4_CSCT_1_CYCLE + depends on OR4_TRLX_NORMAL + bool "1 cycle" + +config OR4_CSCT_2_CYCLE + depends on OR4_TRLX_RELAXED + bool "2 cycles" + +config OR4_CSCT_4_CYCLE + depends on OR4_TRLX_NORMAL + bool "4 cycles" + +config OR4_CSCT_8_CYCLE + depends on OR4_TRLX_RELAXED + bool "8 cycles" + +endchoice + +choice + prompt "Command setup time" + +config OR4_CST_COINCIDENT + depends on OR4_TRLX_NORMAL + bool "Coincident with any command" + +config OR4_CST_QUARTER_CLOCK + depends on OR4_TRLX_NORMAL + bool "0.25 clocks after" + +config OR4_CST_HALF_CLOCK + depends on OR4_TRLX_RELAXED + bool "0.5 clocks after" + +config OR4_CST_ONE_CLOCK + depends on OR4_TRLX_RELAXED + bool "1 clock after" + +endchoice + +choice + prompt "Command hold time" + +config OR4_CHT_HALF_CLOCK + depends on OR4_TRLX_NORMAL + bool "0.5 clocks before" + +config OR4_CHT_ONE_CLOCK + depends on OR4_TRLX_NORMAL + bool "1 clock before" + +config OR4_CHT_ONE_HALF_CLOCK + depends on OR4_TRLX_RELAXED + bool "1.5 clocks before" + +config OR4_CHT_TWO_CLOCK + depends on OR4_TRLX_RELAXED + bool "2 clocks before" + +endchoice + +choice + prompt "Reset setup time" + +config OR4_RST_THREE_QUARTER_CLOCK + depends on OR4_TRLX_NORMAL + bool "0.75 clocks prior" + +config OR4_RST_ONE_HALF_CLOCK + depends on OR4_TRLX_RELAXED + bool "0.5 clocks prior" + +config OR4_RST_ONE_CLOCK + bool "1 clock prior" + +endchoice + +endif # BR4_MACHINE_FCM + +if BR4_MACHINE_UPM + +choice + prompt "Burst inhibit" + +config OR4_BI_BURSTSUPPORT + bool "Support burst access" + +config OR4_BI_BURSTINHIBIT + bool "Inhibit burst access" + +endchoice + +endif # BR4_MACHINE_UPM + +if BR4_MACHINE_SDRAM + +choice + prompt "Number of column address lines" + +config OR4_COLS_7 + bool "7" + +config OR4_COLS_8 + bool "8" + +config OR4_COLS_9 + bool "9" + +config OR4_COLS_10 + bool "10" + +config OR4_COLS_11 + bool "11" + +config OR4_COLS_12 + bool "12" + +config OR4_COLS_13 + bool "13" + +config OR4_COLS_14 + bool "14" + +endchoice + +choice + prompt "Number of rows address lines" + +config OR4_ROWS_9 + bool "9" + +config OR4_ROWS_10 + bool "10" + +config OR4_ROWS_11 + bool "11" + +config OR4_ROWS_12 + bool "12" + +config OR4_ROWS_13 + bool "13" + +config OR4_ROWS_14 + bool "14" + +config OR4_ROWS_15 + bool "15" + +endchoice + +choice + prompt "Page mode select" + +config OR4_PMSEL_BTB + bool "Back-to-back" + +config OR4_PMSEL_KEPT_OPEN + bool "Page kept open until page miss or refresh" + +endchoice + +endif # BR4_MACHINE_SDRAM + +choice + prompt "Relaxed timing" + +config OR4_TRLX_NORMAL + bool "Normal" + +config OR4_TRLX_RELAXED + bool "Relaxed" + +endchoice + +choice + prompt "Extended hold time" + +config OR4_EHTR_NORMAL + depends on OR4_TRLX_NORMAL + bool "Normal" + +config OR4_EHTR_1_CYCLE + depends on OR4_TRLX_NORMAL + bool "1 idle clock cycle inserted" + +config OR4_EHTR_4_CYCLE + depends on OR4_TRLX_RELAXED + bool "4 idle clock cycles inserted" + +config OR4_EHTR_8_CYCLE + depends on OR4_TRLX_RELAXED + bool "8 idle clock cycles inserted" + +endchoice + +if !ARCH_MPC8308 + +choice + prompt "External address latch delay" + +config OR4_EAD_NONE + bool "None" + +config OR4_EAD_EXTRA + bool "Extra" + +endchoice + +endif # !ARCH_MPC8308 + +endif # ELBC_BR4_OR4 + +config BR4_PORTSIZE + hex + default 0x800 if BR4_PORTSIZE_8BIT + default 0x1000 if BR4_PORTSIZE_16BIT + default 0x1800 if BR4_PORTSIZE_32BIT + +config BR4_ERRORCHECKING + hex + default 0x0 if !BR4_MACHINE_FCM + default 0x0 if BR4_ERRORCHECKING_DISABLED + default 0x200 if BR4_ERRORCHECKING_ECC_CHECKING + default 0x400 if BR4_ERRORCHECKING_BOTH + +config BR4_WRITE_PROTECT_BIT + hex + default 0x0 if !BR4_WRITE_PROTECT + default 0x100 if BR4_WRITE_PROTECT + +config BR4_MACHINE + hex + default 0x0 if BR4_MACHINE_GPCM + default 0x20 if BR4_MACHINE_FCM + default 0x60 if BR4_MACHINE_SDRAM + default 0x80 if BR4_MACHINE_UPMA + default 0xa0 if BR4_MACHINE_UPMB + default 0xc0 if BR4_MACHINE_UPMC + +config BR4_ATOMIC + hex + default 0x0 if !ARCH_MPC8313 && !ARCH_MPC8323 && !ARCH_MPC8360 + default 0x0 if BR4_ATOMIC_NONE + default 0x4 if BR4_ATOMIC_RAWA + default 0x8 if BR4_ATOMIC_WARA + +config BR4_VALID_BIT + hex + default 0x0 if !ELBC_BR4_OR4 + default 0x1 if ELBC_BR4_OR4 + +config OR4_AM + hex + default 0xffff8000 if OR4_AM_32_KBYTES && !BR4_MACHINE_SDRAM + default 0xffff0000 if OR4_AM_64_KBYTES + default 0xfffe0000 if OR4_AM_128_KBYTES + default 0xfffc0000 if OR4_AM_256_KBYTES + default 0xfff80000 if OR4_AM_512_KBYTES + default 0xfff00000 if OR4_AM_1_MBYTES + default 0xffe00000 if OR4_AM_2_MBYTES + default 0xffc00000 if OR4_AM_4_MBYTES + default 0xff800000 if OR4_AM_8_MBYTES + default 0xff000000 if OR4_AM_16_MBYTES + default 0xfe000000 if OR4_AM_32_MBYTES + default 0xfc000000 if OR4_AM_64_MBYTES + default 0xf8000000 if OR4_AM_128_MBYTES + default 0xf0000000 if OR4_AM_256_MBYTES + default 0xe0000000 if OR4_AM_512_MBYTES + default 0xc0000000 if OR4_AM_1_GBYTES + default 0x80000000 if OR4_AM_2_GBYTES + default 0x00000000 if OR4_AM_4_GBYTES + +config OR4_XAM + hex + default 0x0 if !OR4_XAM_SET + default 0x6000 if OR4_XAM_SET + +config OR4_BCTLD + hex + default 0x0 if OR4_BCTLD_ASSERTED + default 0x1000 if OR4_BCTLD_NOT_ASSERTED + +config OR4_BI + hex + default 0x0 if !BR4_MACHINE_UPM + default 0x0 if OR4_BI_BURSTSUPPORT + default 0x100 if OR4_BI_BURSTINHIBIT + +config OR4_COLS + hex + default 0x0 if !BR4_MACHINE_SDRAM + default 0x0 if OR4_COLS_7 + default 0x400 if OR4_COLS_8 + default 0x800 if OR4_COLS_9 + default 0xc00 if OR4_COLS_10 + default 0x1000 if OR4_COLS_11 + default 0x1400 if OR4_COLS_12 + default 0x1800 if OR4_COLS_13 + default 0x1c00 if OR4_COLS_14 + +config OR4_ROWS + hex + default 0x0 if !BR4_MACHINE_SDRAM + default 0x0 if OR4_ROWS_9 + default 0x40 if OR4_ROWS_10 + default 0x80 if OR4_ROWS_11 + default 0xc0 if OR4_ROWS_12 + default 0x100 if OR4_ROWS_13 + default 0x140 if OR4_ROWS_14 + default 0x180 if OR4_ROWS_15 + +config OR4_PMSEL + hex + default 0x0 if !BR4_MACHINE_SDRAM + default 0x0 if OR4_PMSEL_BTB + default 0x20 if OR4_PMSEL_KEPT_OPEN + +config OR4_SCY + hex + default 0x0 if !BR4_MACHINE_GPCM && !BR4_MACHINE_FCM + default 0x0 if OR4_SCY_0 + default 0x10 if OR4_SCY_1 + default 0x20 if OR4_SCY_2 + default 0x30 if OR4_SCY_3 + default 0x40 if OR4_SCY_4 + default 0x50 if OR4_SCY_5 + default 0x60 if OR4_SCY_6 + default 0x70 if OR4_SCY_7 + default 0x80 if OR4_SCY_8 + default 0x90 if OR4_SCY_9 + default 0xa0 if OR4_SCY_10 + default 0xb0 if OR4_SCY_11 + default 0xc0 if OR4_SCY_12 + default 0xd0 if OR4_SCY_13 + default 0xe0 if OR4_SCY_14 + default 0xf0 if OR4_SCY_15 + +config OR4_PGS + hex + default 0x0 if !BR4_MACHINE_FCM + default 0x0 if OR4_PGS_SMALL + default 0x400 if OR4_PGS_LARGE + +config OR4_CSCT + hex + default 0x0 if !BR4_MACHINE_FCM + default 0x0 if OR4_CSCT_1_CYCLE + default 0x0 if OR4_CSCT_2_CYCLE + default 0x200 if OR4_CSCT_4_CYCLE + default 0x200 if OR4_CSCT_8_CYCLE + +config OR4_CST + hex + default 0x0 if !BR4_MACHINE_FCM + default 0x0 if OR4_CST_COINCIDENT + default 0x100 if OR4_CST_QUARTER_CLOCK + default 0x0 if OR4_CST_HALF_CLOCK + default 0x100 if OR4_CST_ONE_CLOCK + +config OR4_CHT + hex + default 0x0 if !BR4_MACHINE_FCM + default 0x0 if OR4_CHT_HALF_CLOCK + default 0x80 if OR4_CHT_ONE_CLOCK + default 0x0 if OR4_CHT_ONE_HALF_CLOCK + default 0x80 if OR4_CHT_TWO_CLOCK + +config OR4_RST + hex + default 0x0 if !BR4_MACHINE_FCM + default 0x0 if OR4_RST_THREE_QUARTER_CLOCK + default 0x8 if OR4_RST_ONE_CLOCK + default 0x0 if OR4_RST_ONE_HALF_CLOCK + +config OR4_CSNT + hex + default 0x0 if !BR4_MACHINE_GPCM + default 0x0 if OR4_CSNT_NORMAL + default 0x800 if OR4_CSNT_EARLIER + +config OR4_ACS + hex + default 0x0 if !BR4_MACHINE_GPCM + default 0x0 if OR4_ACS_SAME_TIME + default 0x400 if OR4_ACS_QUARTER_CYCLE_EARLIER + default 0x600 if OR4_ACS_HALF_CYCLE_EARLIER + +config OR4_XACS + hex + default 0x0 if !BR4_MACHINE_GPCM + default 0x0 if OR4_XACS_NORMAL + default 0x100 if OR4_XACS_EXTENDED + +config OR4_SETA + hex + default 0x0 if !BR4_MACHINE_GPCM + default 0x0 if OR4_SETA_INTERNAL + default 0x8 if OR4_SETA_EXTERNAL + +config OR4_TRLX + hex + default 0x0 if OR4_TRLX_NORMAL + default 0x4 if OR4_TRLX_RELAXED + +config OR4_EHTR + hex + default 0x0 if OR4_EHTR_NORMAL + default 0x2 if OR4_EHTR_1_CYCLE + default 0x0 if OR4_EHTR_4_CYCLE + default 0x2 if OR4_EHTR_8_CYCLE + +config OR4_EAD + hex + default 0x0 if ARCH_MPC8308 + default 0x0 if OR4_EAD_NONE + default 0x1 if OR4_EAD_EXTRA diff --git a/arch/powerpc/cpu/mpc83xx/elbc/elbc.h b/arch/powerpc/cpu/mpc83xx/elbc/elbc.h new file mode 100644 index 0000000000..245fe7c6fb --- /dev/null +++ b/arch/powerpc/cpu/mpc83xx/elbc/elbc.h @@ -0,0 +1,186 @@ +#ifdef CONFIG_ELBC_BR0_OR0 +#define CONFIG_SYS_BR0_PRELIM (\ + CONFIG_BR0_OR0_BASE |\ + CONFIG_BR0_PORTSIZE |\ + CONFIG_BR0_ERRORCHECKING |\ + CONFIG_BR0_WRITE_PROTECT_BIT |\ + CONFIG_BR0_MACHINE |\ + CONFIG_BR0_ATOMIC |\ + CONFIG_BR0_VALID_BIT \ +) +#define CONFIG_SYS_OR0_PRELIM (\ + CONFIG_OR0_AM |\ + CONFIG_OR0_XAM |\ + CONFIG_OR0_BCTLD |\ + CONFIG_OR0_BI |\ + CONFIG_OR0_COLS |\ + CONFIG_OR0_ROWS |\ + CONFIG_OR0_PMSEL |\ + CONFIG_OR0_SCY |\ + CONFIG_OR0_PGS |\ + CONFIG_OR0_CSCT |\ + CONFIG_OR0_CST |\ + CONFIG_OR0_CHT |\ + CONFIG_OR0_RST |\ + CONFIG_OR0_CSNT |\ + CONFIG_OR0_ACS |\ + CONFIG_OR0_XACS |\ + CONFIG_OR0_SETA |\ + CONFIG_OR0_TRLX |\ + CONFIG_OR0_EHTR |\ + CONFIG_OR0_EAD \ +) +#endif /* CONFIG_ELBC_BR0_OR0 */ + +#ifdef CONFIG_ELBC_BR1_OR1 +#define CONFIG_SYS_BR1_PRELIM (\ + CONFIG_BR1_OR1_BASE |\ + CONFIG_BR1_PORTSIZE |\ + CONFIG_BR1_ERRORCHECKING |\ + CONFIG_BR1_WRITE_PROTECT_BIT |\ + CONFIG_BR1_MACHINE |\ + CONFIG_BR1_ATOMIC |\ + CONFIG_BR1_VALID_BIT \ +) +#define CONFIG_SYS_OR1_PRELIM (\ + CONFIG_OR1_AM |\ + CONFIG_OR1_XAM |\ + CONFIG_OR1_BCTLD |\ + CONFIG_OR1_BI |\ + CONFIG_OR1_COLS |\ + CONFIG_OR1_ROWS |\ + CONFIG_OR1_PMSEL |\ + CONFIG_OR1_SCY |\ + CONFIG_OR1_PGS |\ + CONFIG_OR1_CSCT |\ + CONFIG_OR1_CST |\ + CONFIG_OR1_CHT |\ + CONFIG_OR1_RST |\ + CONFIG_OR1_CSNT |\ + CONFIG_OR1_ACS |\ + CONFIG_OR1_XACS |\ + CONFIG_OR1_SETA |\ + CONFIG_OR1_TRLX |\ + CONFIG_OR1_EHTR |\ + CONFIG_OR1_EAD \ +) +#endif /* CONFIG_ELBC_BR1_OR1 */ + +#ifdef CONFIG_ELBC_BR2_OR2 +#define CONFIG_SYS_BR2_PRELIM (\ + CONFIG_BR2_OR2_BASE |\ + CONFIG_BR2_PORTSIZE |\ + CONFIG_BR2_ERRORCHECKING |\ + CONFIG_BR2_WRITE_PROTECT_BIT |\ + CONFIG_BR2_MACHINE |\ + CONFIG_BR2_ATOMIC |\ + CONFIG_BR2_VALID_BIT \ +) +#define CONFIG_SYS_OR2_PRELIM (\ + CONFIG_OR2_AM |\ + CONFIG_OR2_XAM |\ + CONFIG_OR2_BCTLD |\ + CONFIG_OR2_BI |\ + CONFIG_OR2_COLS |\ + CONFIG_OR2_ROWS |\ + CONFIG_OR2_PMSEL |\ + CONFIG_OR2_SCY |\ + CONFIG_OR2_PGS |\ + CONFIG_OR2_CSCT |\ + CONFIG_OR2_CST |\ + CONFIG_OR2_CHT |\ + CONFIG_OR2_RST |\ + CONFIG_OR2_CSNT |\ + CONFIG_OR2_ACS |\ + CONFIG_OR2_XACS |\ + CONFIG_OR2_SETA |\ + CONFIG_OR2_TRLX |\ + CONFIG_OR2_EHTR |\ + CONFIG_OR2_EAD \ +) +#endif /* CONFIG_ELBC_BR2_OR2 */ + +#ifdef CONFIG_ELBC_BR3_OR3 +#define CONFIG_SYS_BR3_PRELIM (\ + CONFIG_BR3_OR3_BASE |\ + CONFIG_BR3_PORTSIZE |\ + CONFIG_BR3_ERRORCHECKING |\ + CONFIG_BR3_WRITE_PROTECT_BIT |\ + CONFIG_BR3_MACHINE |\ + CONFIG_BR3_ATOMIC |\ + CONFIG_BR3_VALID_BIT \ +) +#define CONFIG_SYS_OR3_PRELIM (\ + CONFIG_OR3_AM |\ + CONFIG_OR3_XAM |\ + CONFIG_OR3_BCTLD |\ + CONFIG_OR3_BI |\ + CONFIG_OR3_COLS |\ + CONFIG_OR3_ROWS |\ + CONFIG_OR3_PMSEL |\ + CONFIG_OR3_SCY |\ + CONFIG_OR3_PGS |\ + CONFIG_OR3_CSCT |\ + CONFIG_OR3_CST |\ + CONFIG_OR3_CHT |\ + CONFIG_OR3_RST |\ + CONFIG_OR3_CSNT |\ + CONFIG_OR3_ACS |\ + CONFIG_OR3_XACS |\ + CONFIG_OR3_SETA |\ + CONFIG_OR3_TRLX |\ + CONFIG_OR3_EHTR |\ + CONFIG_OR3_EAD \ +) +#endif /* CONFIG_ELBC_BR3_OR3 */ + +#ifdef CONFIG_ELBC_BR4_OR4 +#define CONFIG_SYS_BR4_PRELIM (\ + CONFIG_BR4_OR4_BASE |\ + CONFIG_BR4_PORTSIZE |\ + CONFIG_BR4_ERRORCHECKING |\ + CONFIG_BR4_WRITE_PROTECT_BIT |\ + CONFIG_BR4_MACHINE |\ + CONFIG_BR4_ATOMIC |\ + CONFIG_BR4_VALID_BIT \ +) +#define CONFIG_SYS_OR4_PRELIM (\ + CONFIG_OR4_AM |\ + CONFIG_OR4_XAM |\ + CONFIG_OR4_BCTLD |\ + CONFIG_OR4_BI |\ + CONFIG_OR4_COLS |\ + CONFIG_OR4_ROWS |\ + CONFIG_OR4_PMSEL |\ + CONFIG_OR4_SCY |\ + CONFIG_OR4_PGS |\ + CONFIG_OR4_CSCT |\ + CONFIG_OR4_CST |\ + CONFIG_OR4_CHT |\ + CONFIG_OR4_RST |\ + CONFIG_OR4_CSNT |\ + CONFIG_OR4_ACS |\ + CONFIG_OR4_XACS |\ + CONFIG_OR4_SETA |\ + CONFIG_OR4_TRLX |\ + CONFIG_OR4_EHTR |\ + CONFIG_OR4_EAD \ +) +#endif /* CONFIG_ELBC_BR4_OR4 */ + +#if defined(CONFIG_ELBC_BR_OR_NAND_PRELIM_0) +#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR0_PRELIM +#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR0_PRELIM +#elif defined(CONFIG_ELBC_BR_OR_NAND_PRELIM_1) +#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM +#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM +#elif defined(CONFIG_ELBC_BR_OR_NAND_PRELIM_2) +#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR2_PRELIM +#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR2_PRELIM +#elif defined(CONFIG_ELBC_BR_OR_NAND_PRELIM_3) +#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR3_PRELIM +#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR3_PRELIM +#elif defined(CONFIG_ELBC_BR_OR_NAND_PRELIM_4) +#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR4_PRELIM +#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR4_PRELIM +#endif diff --git a/arch/powerpc/cpu/mpc83xx/spl_minimal.c b/arch/powerpc/cpu/mpc83xx/spl_minimal.c index 75eb65010e..b4e2fb1119 100644 --- a/arch/powerpc/cpu/mpc83xx/spl_minimal.c +++ b/arch/powerpc/cpu/mpc83xx/spl_minimal.c @@ -7,6 +7,7 @@ #include #include "lblaw/lblaw.h" +#include "elbc/elbc.h" DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c b/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c index 13545fc6ad..c43732f7c5 100644 --- a/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c +++ b/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c @@ -6,6 +6,10 @@ #include #include +#ifdef CONFIG_MPC83xx +#include "../mpc83xx/elbc/elbc.h" +#endif + #ifdef CONFIG_MPC85xx /* Boards should provide their own version of this if they use lbc sdram */ static void __lbc_sdram_init(void) diff --git a/board/freescale/mpc8349itx/mpc8349itx.c b/board/freescale/mpc8349itx/mpc8349itx.c index c4bec090be..62bcf23571 100644 --- a/board/freescale/mpc8349itx/mpc8349itx.c +++ b/board/freescale/mpc8349itx/mpc8349itx.c @@ -20,6 +20,7 @@ #endif #include "../../../arch/powerpc/cpu/mpc83xx/hrcw/hrcw.h" +#include "../../../arch/powerpc/cpu/mpc83xx/elbc/elbc.h" DECLARE_GLOBAL_DATA_PTR; diff --git a/configs/MPC8308RDB_defconfig b/configs/MPC8308RDB_defconfig index 38c5d8d532..c38ac328d2 100644 --- a/configs/MPC8308RDB_defconfig +++ b/configs/MPC8308RDB_defconfig @@ -86,3 +86,41 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_8_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="NAND" +CONFIG_BR1_OR1_BASE=0xE0600000 +CONFIG_BR1_ERRORCHECKING_BOTH=y +CONFIG_BR1_MACHINE_FCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_32_KBYTES=y +CONFIG_OR1_SCY_1=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_OR1_CHT_TWO_CLOCK=y +CONFIG_OR1_CSCT_8_CYCLE=y +CONFIG_OR1_CST_ONE_CLOCK=y +CONFIG_OR1_EHTR_8_CYCLE=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="VSC7385_BASE" +CONFIG_BR2_OR2_BASE=0xF0000000 +CONFIG_BR2_MACHINE_GPCM=y +CONFIG_BR2_PORTSIZE_8BIT=y +CONFIG_OR2_AM_128_KBYTES=y +CONFIG_OR2_CSNT_EARLIER=y +CONFIG_OR2_SCY_15=y +CONFIG_OR2_SETA_EXTERNAL=y +CONFIG_OR2_XACS_EXTENDED=y +CONFIG_OR2_TRLX_RELAXED=y +CONFIG_OR2_EHTR_8_CYCLE=y diff --git a/configs/MPC8313ERDB_33_defconfig b/configs/MPC8313ERDB_33_defconfig index 5783165e5d..1588adf3d6 100644 --- a/configs/MPC8313ERDB_33_defconfig +++ b/configs/MPC8313ERDB_33_defconfig @@ -103,3 +103,53 @@ CONFIG_PHY_MARVELL=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR_OR_NAND_PRELIM_1=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_8_MBYTES=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_9=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_EHTR_1_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="NAND" +CONFIG_BR1_OR1_BASE=0xE2800000 +CONFIG_BR1_ERRORCHECKING_BOTH=y +CONFIG_BR1_MACHINE_FCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_32_KBYTES=y +CONFIG_OR1_SCY_1=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_OR1_CHT_TWO_CLOCK=y +CONFIG_OR1_CSCT_8_CYCLE=y +CONFIG_OR1_CST_ONE_CLOCK=y +CONFIG_OR1_EHTR_8_CYCLE=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="BCSR" +CONFIG_BR3_OR3_BASE=0xFA000000 +CONFIG_BR3_MACHINE_GPCM=y +CONFIG_BR3_PORTSIZE_8BIT=y +CONFIG_OR3_AM_32_KBYTES=y +CONFIG_OR3_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR3_CSNT_EARLIER=y +CONFIG_OR3_EAD_EXTRA=y +CONFIG_OR3_SCY_15=y +CONFIG_OR3_XACS_EXTENDED=y +CONFIG_OR3_TRLX_RELAXED=y +CONFIG_OR3_EHTR_8_CYCLE=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="VSC7385" +CONFIG_BR2_OR2_BASE=0xF0000000 +CONFIG_BR2_MACHINE_GPCM=y +CONFIG_BR2_PORTSIZE_8BIT=y +CONFIG_OR2_AM_128_KBYTES=y +CONFIG_OR2_CSNT_EARLIER=y +CONFIG_OR2_EAD_EXTRA=y +CONFIG_OR2_SCY_15=y +CONFIG_OR2_SETA_EXTERNAL=y +CONFIG_OR2_XACS_EXTENDED=y +CONFIG_OR2_TRLX_RELAXED=y +CONFIG_OR2_EHTR_8_CYCLE=y diff --git a/configs/MPC8313ERDB_66_defconfig b/configs/MPC8313ERDB_66_defconfig index 2395b8e397..2425256ee3 100644 --- a/configs/MPC8313ERDB_66_defconfig +++ b/configs/MPC8313ERDB_66_defconfig @@ -102,3 +102,53 @@ CONFIG_PHY_MARVELL=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR_OR_NAND_PRELIM_1=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_8_MBYTES=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_9=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_EHTR_1_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="NAND" +CONFIG_BR1_OR1_BASE=0xE2800000 +CONFIG_BR1_ERRORCHECKING_BOTH=y +CONFIG_BR1_MACHINE_FCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_32_KBYTES=y +CONFIG_OR1_SCY_1=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_OR1_CHT_TWO_CLOCK=y +CONFIG_OR1_CSCT_8_CYCLE=y +CONFIG_OR1_CST_ONE_CLOCK=y +CONFIG_OR1_EHTR_8_CYCLE=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="BCSR" +CONFIG_BR3_OR3_BASE=0xFA000000 +CONFIG_BR3_MACHINE_GPCM=y +CONFIG_BR3_PORTSIZE_8BIT=y +CONFIG_OR3_AM_32_KBYTES=y +CONFIG_OR3_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR3_CSNT_EARLIER=y +CONFIG_OR3_EAD_EXTRA=y +CONFIG_OR3_SCY_15=y +CONFIG_OR3_XACS_EXTENDED=y +CONFIG_OR3_TRLX_RELAXED=y +CONFIG_OR3_EHTR_8_CYCLE=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="VSC7385" +CONFIG_BR2_OR2_BASE=0xF0000000 +CONFIG_BR2_MACHINE_GPCM=y +CONFIG_BR2_PORTSIZE_8BIT=y +CONFIG_OR2_AM_128_KBYTES=y +CONFIG_OR2_CSNT_EARLIER=y +CONFIG_OR2_EAD_EXTRA=y +CONFIG_OR2_SCY_15=y +CONFIG_OR2_SETA_EXTERNAL=y +CONFIG_OR2_XACS_EXTENDED=y +CONFIG_OR2_TRLX_RELAXED=y +CONFIG_OR2_EHTR_8_CYCLE=y diff --git a/configs/MPC8313ERDB_NAND_33_defconfig b/configs/MPC8313ERDB_NAND_33_defconfig index ce97914934..8ee257a54e 100644 --- a/configs/MPC8313ERDB_NAND_33_defconfig +++ b/configs/MPC8313ERDB_NAND_33_defconfig @@ -111,3 +111,53 @@ CONFIG_PHY_MARVELL=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR_OR_NAND_PRELIM_0=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="NAND" +CONFIG_BR0_OR0_BASE=0xE2800000 +CONFIG_BR0_ERRORCHECKING_BOTH=y +CONFIG_BR0_MACHINE_FCM=y +CONFIG_BR0_PORTSIZE_8BIT=y +CONFIG_OR0_AM_32_KBYTES=y +CONFIG_OR0_SCY_1=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_CHT_TWO_CLOCK=y +CONFIG_OR0_CSCT_8_CYCLE=y +CONFIG_OR0_CST_ONE_CLOCK=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="FLASH" +CONFIG_BR1_OR1_BASE=0xFE000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_16BIT=y +CONFIG_OR1_AM_8_MBYTES=y +CONFIG_OR1_EAD_EXTRA=y +CONFIG_OR1_SCY_9=y +CONFIG_OR1_XACS_EXTENDED=y +CONFIG_OR1_EHTR_1_CYCLE=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="BCSR" +CONFIG_BR3_OR3_BASE=0xFA000000 +CONFIG_BR3_MACHINE_GPCM=y +CONFIG_BR3_PORTSIZE_8BIT=y +CONFIG_OR3_AM_32_KBYTES=y +CONFIG_OR3_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR3_CSNT_EARLIER=y +CONFIG_OR3_EAD_EXTRA=y +CONFIG_OR3_SCY_15=y +CONFIG_OR3_XACS_EXTENDED=y +CONFIG_OR3_TRLX_RELAXED=y +CONFIG_OR3_EHTR_8_CYCLE=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="VSC7385" +CONFIG_BR2_OR2_BASE=0xF0000000 +CONFIG_BR2_MACHINE_GPCM=y +CONFIG_BR2_PORTSIZE_8BIT=y +CONFIG_OR2_AM_128_KBYTES=y +CONFIG_OR2_CSNT_EARLIER=y +CONFIG_OR2_EAD_EXTRA=y +CONFIG_OR2_SCY_15=y +CONFIG_OR2_SETA_EXTERNAL=y +CONFIG_OR2_XACS_EXTENDED=y +CONFIG_OR2_TRLX_RELAXED=y +CONFIG_OR2_EHTR_8_CYCLE=y diff --git a/configs/MPC8313ERDB_NAND_66_defconfig b/configs/MPC8313ERDB_NAND_66_defconfig index 92d33b07db..baca3d799d 100644 --- a/configs/MPC8313ERDB_NAND_66_defconfig +++ b/configs/MPC8313ERDB_NAND_66_defconfig @@ -110,3 +110,53 @@ CONFIG_PHY_MARVELL=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR_OR_NAND_PRELIM_0=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="NAND" +CONFIG_BR0_OR0_BASE=0xE2800000 +CONFIG_BR0_ERRORCHECKING_BOTH=y +CONFIG_BR0_MACHINE_FCM=y +CONFIG_BR0_PORTSIZE_8BIT=y +CONFIG_OR0_AM_32_KBYTES=y +CONFIG_OR0_SCY_1=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_CHT_TWO_CLOCK=y +CONFIG_OR0_CSCT_8_CYCLE=y +CONFIG_OR0_CST_ONE_CLOCK=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="FLASH" +CONFIG_BR1_OR1_BASE=0xFE000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_16BIT=y +CONFIG_OR1_AM_8_MBYTES=y +CONFIG_OR1_EAD_EXTRA=y +CONFIG_OR1_SCY_9=y +CONFIG_OR1_XACS_EXTENDED=y +CONFIG_OR1_EHTR_1_CYCLE=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="BCSR" +CONFIG_BR3_OR3_BASE=0xFA000000 +CONFIG_BR3_MACHINE_GPCM=y +CONFIG_BR3_PORTSIZE_8BIT=y +CONFIG_OR3_AM_32_KBYTES=y +CONFIG_OR3_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR3_CSNT_EARLIER=y +CONFIG_OR3_EAD_EXTRA=y +CONFIG_OR3_SCY_15=y +CONFIG_OR3_XACS_EXTENDED=y +CONFIG_OR3_TRLX_RELAXED=y +CONFIG_OR3_EHTR_8_CYCLE=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="VSC7385" +CONFIG_BR2_OR2_BASE=0xF0000000 +CONFIG_BR2_MACHINE_GPCM=y +CONFIG_BR2_PORTSIZE_8BIT=y +CONFIG_OR2_AM_128_KBYTES=y +CONFIG_OR2_CSNT_EARLIER=y +CONFIG_OR2_EAD_EXTRA=y +CONFIG_OR2_SCY_15=y +CONFIG_OR2_SETA_EXTERNAL=y +CONFIG_OR2_XACS_EXTENDED=y +CONFIG_OR2_TRLX_RELAXED=y +CONFIG_OR2_EHTR_8_CYCLE=y diff --git a/configs/MPC8315ERDB_defconfig b/configs/MPC8315ERDB_defconfig index b6e43b66aa..b9539893ff 100644 --- a/configs/MPC8315ERDB_defconfig +++ b/configs/MPC8315ERDB_defconfig @@ -109,3 +109,30 @@ CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_8_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="NAND" +CONFIG_BR1_OR1_BASE=0xE0600000 +CONFIG_BR1_ERRORCHECKING_BOTH=y +CONFIG_BR1_MACHINE_FCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_32_KBYTES=y +CONFIG_OR1_SCY_1=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_OR1_CHT_TWO_CLOCK=y +CONFIG_OR1_CSCT_8_CYCLE=y +CONFIG_OR1_CST_ONE_CLOCK=y +CONFIG_OR1_EHTR_8_CYCLE=y diff --git a/configs/MPC8323ERDB_defconfig b/configs/MPC8323ERDB_defconfig index 7243cf67f9..64e6f58f38 100644 --- a/configs/MPC8323ERDB_defconfig +++ b/configs/MPC8323ERDB_defconfig @@ -88,3 +88,17 @@ CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_16_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y diff --git a/configs/MPC832XEMDS_ATM_defconfig b/configs/MPC832XEMDS_ATM_defconfig index 8cbc14022b..ffc82260ec 100644 --- a/configs/MPC832XEMDS_ATM_defconfig +++ b/configs/MPC832XEMDS_ATM_defconfig @@ -87,3 +87,56 @@ CONFIG_SYS_FLASH_CFI=y # CONFIG_PCI is not set CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_16_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="BCSR" +CONFIG_BR1_OR1_BASE=0xF8000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_32_KBYTES=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_EAD_EXTRA=y +CONFIG_OR1_SCY_15=y +CONFIG_OR1_XACS_EXTENDED=y +CONFIG_OR1_XAM_SET=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_OR1_EHTR_8_CYCLE=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="PIB1" +CONFIG_BR2_OR2_BASE=0xF8008000 +CONFIG_BR2_MACHINE_GPCM=y +CONFIG_BR2_PORTSIZE_8BIT=y +CONFIG_OR2_AM_32_KBYTES=y +CONFIG_OR2_CSNT_EARLIER=y +CONFIG_OR2_EAD_EXTRA=y +CONFIG_OR2_SCY_15=y +CONFIG_OR2_XACS_EXTENDED=y +CONFIG_OR2_XAM_SET=y +CONFIG_OR2_TRLX_RELAXED=y +CONFIG_OR2_EHTR_8_CYCLE=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="PIB2" +CONFIG_BR3_OR3_BASE=0xF8010000 +CONFIG_BR3_MACHINE_GPCM=y +CONFIG_BR3_PORTSIZE_8BIT=y +CONFIG_OR3_AM_32_KBYTES=y +CONFIG_OR3_CSNT_EARLIER=y +CONFIG_OR3_EAD_EXTRA=y +CONFIG_OR3_SCY_15=y +CONFIG_OR3_XACS_EXTENDED=y +CONFIG_OR3_XAM_SET=y +CONFIG_OR3_TRLX_RELAXED=y +CONFIG_OR3_EHTR_8_CYCLE=y diff --git a/configs/MPC832XEMDS_HOST_33_defconfig b/configs/MPC832XEMDS_HOST_33_defconfig index 487d1d8544..911f62de65 100644 --- a/configs/MPC832XEMDS_HOST_33_defconfig +++ b/configs/MPC832XEMDS_HOST_33_defconfig @@ -107,3 +107,56 @@ CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_16_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="BCSR" +CONFIG_BR1_OR1_BASE=0xF8000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_32_KBYTES=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_EAD_EXTRA=y +CONFIG_OR1_SCY_15=y +CONFIG_OR1_XACS_EXTENDED=y +CONFIG_OR1_XAM_SET=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_OR1_EHTR_8_CYCLE=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="PIB1" +CONFIG_BR2_OR2_BASE=0xF8008000 +CONFIG_BR2_MACHINE_GPCM=y +CONFIG_BR2_PORTSIZE_8BIT=y +CONFIG_OR2_AM_32_KBYTES=y +CONFIG_OR2_CSNT_EARLIER=y +CONFIG_OR2_EAD_EXTRA=y +CONFIG_OR2_SCY_15=y +CONFIG_OR2_XACS_EXTENDED=y +CONFIG_OR2_XAM_SET=y +CONFIG_OR2_TRLX_RELAXED=y +CONFIG_OR2_EHTR_8_CYCLE=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="PIB2" +CONFIG_BR3_OR3_BASE=0xF8010000 +CONFIG_BR3_MACHINE_GPCM=y +CONFIG_BR3_PORTSIZE_8BIT=y +CONFIG_OR3_AM_32_KBYTES=y +CONFIG_OR3_CSNT_EARLIER=y +CONFIG_OR3_EAD_EXTRA=y +CONFIG_OR3_SCY_15=y +CONFIG_OR3_XACS_EXTENDED=y +CONFIG_OR3_XAM_SET=y +CONFIG_OR3_TRLX_RELAXED=y +CONFIG_OR3_EHTR_8_CYCLE=y diff --git a/configs/MPC832XEMDS_HOST_66_defconfig b/configs/MPC832XEMDS_HOST_66_defconfig index 10ea03422c..7dd02a95c9 100644 --- a/configs/MPC832XEMDS_HOST_66_defconfig +++ b/configs/MPC832XEMDS_HOST_66_defconfig @@ -107,3 +107,56 @@ CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_16_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="BCSR" +CONFIG_BR1_OR1_BASE=0xF8000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_32_KBYTES=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_EAD_EXTRA=y +CONFIG_OR1_SCY_15=y +CONFIG_OR1_XACS_EXTENDED=y +CONFIG_OR1_XAM_SET=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_OR1_EHTR_8_CYCLE=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="PIB1" +CONFIG_BR2_OR2_BASE=0xF8008000 +CONFIG_BR2_MACHINE_GPCM=y +CONFIG_BR2_PORTSIZE_8BIT=y +CONFIG_OR2_AM_32_KBYTES=y +CONFIG_OR2_CSNT_EARLIER=y +CONFIG_OR2_EAD_EXTRA=y +CONFIG_OR2_SCY_15=y +CONFIG_OR2_XACS_EXTENDED=y +CONFIG_OR2_XAM_SET=y +CONFIG_OR2_TRLX_RELAXED=y +CONFIG_OR2_EHTR_8_CYCLE=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="PIB2" +CONFIG_BR3_OR3_BASE=0xF8010000 +CONFIG_BR3_MACHINE_GPCM=y +CONFIG_BR3_PORTSIZE_8BIT=y +CONFIG_OR3_AM_32_KBYTES=y +CONFIG_OR3_CSNT_EARLIER=y +CONFIG_OR3_EAD_EXTRA=y +CONFIG_OR3_SCY_15=y +CONFIG_OR3_XACS_EXTENDED=y +CONFIG_OR3_XAM_SET=y +CONFIG_OR3_TRLX_RELAXED=y +CONFIG_OR3_EHTR_8_CYCLE=y diff --git a/configs/MPC832XEMDS_SLAVE_defconfig b/configs/MPC832XEMDS_SLAVE_defconfig index b1afa2fa47..3e3c82b2ef 100644 --- a/configs/MPC832XEMDS_SLAVE_defconfig +++ b/configs/MPC832XEMDS_SLAVE_defconfig @@ -104,3 +104,56 @@ CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_16_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="BCSR" +CONFIG_BR1_OR1_BASE=0xF8000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_32_KBYTES=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_EAD_EXTRA=y +CONFIG_OR1_SCY_15=y +CONFIG_OR1_XACS_EXTENDED=y +CONFIG_OR1_XAM_SET=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_OR1_EHTR_8_CYCLE=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="PIB1" +CONFIG_BR2_OR2_BASE=0xF8008000 +CONFIG_BR2_MACHINE_GPCM=y +CONFIG_BR2_PORTSIZE_8BIT=y +CONFIG_OR2_AM_32_KBYTES=y +CONFIG_OR2_CSNT_EARLIER=y +CONFIG_OR2_EAD_EXTRA=y +CONFIG_OR2_SCY_15=y +CONFIG_OR2_XACS_EXTENDED=y +CONFIG_OR2_XAM_SET=y +CONFIG_OR2_TRLX_RELAXED=y +CONFIG_OR2_EHTR_8_CYCLE=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="PIB2" +CONFIG_BR3_OR3_BASE=0xF8010000 +CONFIG_BR3_MACHINE_GPCM=y +CONFIG_BR3_PORTSIZE_8BIT=y +CONFIG_OR3_AM_32_KBYTES=y +CONFIG_OR3_CSNT_EARLIER=y +CONFIG_OR3_EAD_EXTRA=y +CONFIG_OR3_SCY_15=y +CONFIG_OR3_XACS_EXTENDED=y +CONFIG_OR3_XAM_SET=y +CONFIG_OR3_TRLX_RELAXED=y +CONFIG_OR3_EHTR_8_CYCLE=y diff --git a/configs/MPC832XEMDS_defconfig b/configs/MPC832XEMDS_defconfig index a9bb8a7713..4cfa01074d 100644 --- a/configs/MPC832XEMDS_defconfig +++ b/configs/MPC832XEMDS_defconfig @@ -86,3 +86,56 @@ CONFIG_SYS_FLASH_CFI=y # CONFIG_PCI is not set CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_16_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="BCSR" +CONFIG_BR1_OR1_BASE=0xF8000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_32_KBYTES=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_EAD_EXTRA=y +CONFIG_OR1_SCY_15=y +CONFIG_OR1_XACS_EXTENDED=y +CONFIG_OR1_XAM_SET=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_OR1_EHTR_8_CYCLE=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="PIB1" +CONFIG_BR2_OR2_BASE=0xF8008000 +CONFIG_BR2_MACHINE_GPCM=y +CONFIG_BR2_PORTSIZE_8BIT=y +CONFIG_OR2_AM_32_KBYTES=y +CONFIG_OR2_CSNT_EARLIER=y +CONFIG_OR2_EAD_EXTRA=y +CONFIG_OR2_SCY_15=y +CONFIG_OR2_XACS_EXTENDED=y +CONFIG_OR2_XAM_SET=y +CONFIG_OR2_TRLX_RELAXED=y +CONFIG_OR2_EHTR_8_CYCLE=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="PIB2" +CONFIG_BR3_OR3_BASE=0xF8010000 +CONFIG_BR3_MACHINE_GPCM=y +CONFIG_BR3_PORTSIZE_8BIT=y +CONFIG_OR3_AM_32_KBYTES=y +CONFIG_OR3_CSNT_EARLIER=y +CONFIG_OR3_EAD_EXTRA=y +CONFIG_OR3_SCY_15=y +CONFIG_OR3_XACS_EXTENDED=y +CONFIG_OR3_XAM_SET=y +CONFIG_OR3_TRLX_RELAXED=y +CONFIG_OR3_EHTR_8_CYCLE=y diff --git a/configs/MPC8349EMDS_PCI64_defconfig b/configs/MPC8349EMDS_PCI64_defconfig index 28779bbeb7..a29d3268f7 100644 --- a/configs/MPC8349EMDS_PCI64_defconfig +++ b/configs/MPC8349EMDS_PCI64_defconfig @@ -73,3 +73,27 @@ CONFIG_TSEC_ENET=y # CONFIG_PCI is not set CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_32_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="BCSR" +CONFIG_BR1_OR1_BASE=0xE2400000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_32_KBYTES=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_SCY_15=y +CONFIG_OR1_XAM_SET=y +CONFIG_OR1_EHTR_NORMAL=y diff --git a/configs/MPC8349EMDS_SDRAM_defconfig b/configs/MPC8349EMDS_SDRAM_defconfig index a157066968..e3058f0b5e 100644 --- a/configs/MPC8349EMDS_SDRAM_defconfig +++ b/configs/MPC8349EMDS_SDRAM_defconfig @@ -57,6 +57,33 @@ CONFIG_LBLAW2=y CONFIG_LBLAW2_BASE=0xF0000000 CONFIG_LBLAW2_NAME="SDRAM" CONFIG_LBLAW2_LENGTH_64_MBYTES=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_32_MBYTES=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="BCSR" +CONFIG_BR1_OR1_BASE=0xE2400000 +CONFIG_OR1_XAM_SET=y +CONFIG_OR1_SCY_15=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="SDRAM" +CONFIG_BR2_OR2_BASE=0xF0000000 +CONFIG_BR2_PORTSIZE_32BIT=y +CONFIG_BR2_MACHINE_SDRAM=y +CONFIG_OR2_COLS_9=y +CONFIG_OR2_ROWS_13=y +CONFIG_OR2_EAD_EXTRA=y CONFIG_PCI_ONE_PCI1=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/configs/MPC8349EMDS_SLAVE_defconfig b/configs/MPC8349EMDS_SLAVE_defconfig index 588d9420f1..d45b6489b4 100644 --- a/configs/MPC8349EMDS_SLAVE_defconfig +++ b/configs/MPC8349EMDS_SLAVE_defconfig @@ -73,3 +73,27 @@ CONFIG_TSEC_ENET=y # CONFIG_PCI is not set CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_32_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="BCSR" +CONFIG_BR1_OR1_BASE=0xE2400000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_32_KBYTES=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_SCY_15=y +CONFIG_OR1_XAM_SET=y +CONFIG_OR1_EHTR_NORMAL=y diff --git a/configs/MPC8349EMDS_defconfig b/configs/MPC8349EMDS_defconfig index a38edb5293..e3ca6811cc 100644 --- a/configs/MPC8349EMDS_defconfig +++ b/configs/MPC8349EMDS_defconfig @@ -76,3 +76,27 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_MPC8XXX_SPI=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_32_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="BCSR" +CONFIG_BR1_OR1_BASE=0xE2400000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_32_KBYTES=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_SCY_15=y +CONFIG_OR1_XAM_SET=y +CONFIG_OR1_EHTR_NORMAL=y diff --git a/configs/MPC8349ITXGP_defconfig b/configs/MPC8349ITXGP_defconfig index 844b897329..cf4ce83307 100644 --- a/configs/MPC8349ITXGP_defconfig +++ b/configs/MPC8349ITXGP_defconfig @@ -125,3 +125,50 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_16_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="VSC7385" +CONFIG_BR1_OR1_BASE=0xF8000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_128_KBYTES=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_EAD_EXTRA=y +CONFIG_OR1_SCY_15=y +CONFIG_OR1_SETA_EXTERNAL=y +CONFIG_OR1_XACS_EXTENDED=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_OR1_EHTR_8_CYCLE=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="LED" +CONFIG_BR2_OR2_BASE=0xF9000000 +CONFIG_BR2_MACHINE_GPCM=y +CONFIG_BR2_PORTSIZE_8BIT=y +CONFIG_OR2_AM_2_MBYTES=y +CONFIG_OR2_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR2_CSNT_EARLIER=y +CONFIG_OR2_EAD_EXTRA=y +CONFIG_OR2_SCY_9=y +CONFIG_OR2_XACS_EXTENDED=y +CONFIG_OR2_TRLX_RELAXED=y +CONFIG_OR2_EHTR_8_CYCLE=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="CF" +CONFIG_BR3_OR3_BASE=0xF0000000 +CONFIG_BR3_MACHINE_UPMA=y +CONFIG_BR3_PORTSIZE_16BIT=y +CONFIG_OR3_AM_32_KBYTES=y +CONFIG_OR3_BI_BURSTINHIBIT=y diff --git a/configs/MPC8349ITX_LOWBOOT_defconfig b/configs/MPC8349ITX_LOWBOOT_defconfig index 91ed6686f8..e0185191bc 100644 --- a/configs/MPC8349ITX_LOWBOOT_defconfig +++ b/configs/MPC8349ITX_LOWBOOT_defconfig @@ -133,3 +133,50 @@ CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_16_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="VSC7385" +CONFIG_BR1_OR1_BASE=0xF8000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_128_KBYTES=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_EAD_EXTRA=y +CONFIG_OR1_SCY_15=y +CONFIG_OR1_SETA_EXTERNAL=y +CONFIG_OR1_XACS_EXTENDED=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_OR1_EHTR_8_CYCLE=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="LED" +CONFIG_BR2_OR2_BASE=0xF9000000 +CONFIG_BR2_MACHINE_GPCM=y +CONFIG_BR2_PORTSIZE_8BIT=y +CONFIG_OR2_AM_2_MBYTES=y +CONFIG_OR2_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR2_CSNT_EARLIER=y +CONFIG_OR2_EAD_EXTRA=y +CONFIG_OR2_SCY_9=y +CONFIG_OR2_XACS_EXTENDED=y +CONFIG_OR2_TRLX_RELAXED=y +CONFIG_OR2_EHTR_8_CYCLE=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="CF" +CONFIG_BR3_OR3_BASE=0xF0000000 +CONFIG_BR3_MACHINE_UPMA=y +CONFIG_BR3_PORTSIZE_16BIT=y +CONFIG_OR3_AM_32_KBYTES=y +CONFIG_OR3_BI_BURSTINHIBIT=y diff --git a/configs/MPC8349ITX_defconfig b/configs/MPC8349ITX_defconfig index cfa31c7230..0187f4f128 100644 --- a/configs/MPC8349ITX_defconfig +++ b/configs/MPC8349ITX_defconfig @@ -132,3 +132,50 @@ CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_16_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="VSC7385" +CONFIG_BR1_OR1_BASE=0xF8000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_128_KBYTES=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_EAD_EXTRA=y +CONFIG_OR1_SCY_15=y +CONFIG_OR1_SETA_EXTERNAL=y +CONFIG_OR1_XACS_EXTENDED=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_OR1_EHTR_8_CYCLE=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="LED" +CONFIG_BR2_OR2_BASE=0xF9000000 +CONFIG_BR2_MACHINE_GPCM=y +CONFIG_BR2_PORTSIZE_8BIT=y +CONFIG_OR2_AM_2_MBYTES=y +CONFIG_OR2_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR2_CSNT_EARLIER=y +CONFIG_OR2_EAD_EXTRA=y +CONFIG_OR2_SCY_9=y +CONFIG_OR2_XACS_EXTENDED=y +CONFIG_OR2_TRLX_RELAXED=y +CONFIG_OR2_EHTR_8_CYCLE=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="CF" +CONFIG_BR3_OR3_BASE=0xF0000000 +CONFIG_BR3_MACHINE_UPMA=y +CONFIG_BR3_PORTSIZE_16BIT=y +CONFIG_OR3_AM_32_KBYTES=y +CONFIG_OR3_BI_BURSTINHIBIT=y diff --git a/configs/MPC837XEMDS_HOST_defconfig b/configs/MPC837XEMDS_HOST_defconfig index 4cc36a5c7f..b048d5b5d0 100644 --- a/configs/MPC837XEMDS_HOST_defconfig +++ b/configs/MPC837XEMDS_HOST_defconfig @@ -131,3 +131,44 @@ CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_32_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="BCSR" +CONFIG_BR1_OR1_BASE=0xF8000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_32_KBYTES=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_EAD_EXTRA=y +CONFIG_OR1_SCY_15=y +CONFIG_OR1_XACS_EXTENDED=y +CONFIG_OR1_XAM_SET=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_OR1_EHTR_8_CYCLE=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="NAND" +CONFIG_BR3_OR3_BASE=0xE0600000 +CONFIG_BR3_ERRORCHECKING_BOTH=y +CONFIG_BR3_MACHINE_FCM=y +CONFIG_BR3_PORTSIZE_8BIT=y +CONFIG_OR3_AM_32_KBYTES=y +CONFIG_OR3_BCTLD_NOT_ASSERTED=y +CONFIG_OR3_RST_ONE_CLOCK=y +CONFIG_OR3_SCY_1=y +CONFIG_OR3_TRLX_RELAXED=y +CONFIG_OR3_CHT_TWO_CLOCK=y +CONFIG_OR3_CST_ONE_CLOCK=y +CONFIG_OR3_EHTR_8_CYCLE=y diff --git a/configs/MPC837XEMDS_SLAVE_defconfig b/configs/MPC837XEMDS_SLAVE_defconfig index ba58e49ba2..9e2966b371 100644 --- a/configs/MPC837XEMDS_SLAVE_defconfig +++ b/configs/MPC837XEMDS_SLAVE_defconfig @@ -84,3 +84,44 @@ CONFIG_TSEC_ENET=y # CONFIG_PCI is not set CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_32_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="BCSR" +CONFIG_BR1_OR1_BASE=0xF8000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_32_KBYTES=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_EAD_EXTRA=y +CONFIG_OR1_SCY_15=y +CONFIG_OR1_XACS_EXTENDED=y +CONFIG_OR1_XAM_SET=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_OR1_EHTR_8_CYCLE=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="NAND" +CONFIG_BR3_OR3_BASE=0xE0600000 +CONFIG_BR3_ERRORCHECKING_BOTH=y +CONFIG_BR3_MACHINE_FCM=y +CONFIG_BR3_PORTSIZE_8BIT=y +CONFIG_OR3_AM_32_KBYTES=y +CONFIG_OR3_BCTLD_NOT_ASSERTED=y +CONFIG_OR3_RST_ONE_CLOCK=y +CONFIG_OR3_SCY_1=y +CONFIG_OR3_TRLX_RELAXED=y +CONFIG_OR3_CHT_TWO_CLOCK=y +CONFIG_OR3_CST_ONE_CLOCK=y +CONFIG_OR3_EHTR_8_CYCLE=y diff --git a/configs/MPC837XEMDS_defconfig b/configs/MPC837XEMDS_defconfig index b3c1c87824..9256aac17c 100644 --- a/configs/MPC837XEMDS_defconfig +++ b/configs/MPC837XEMDS_defconfig @@ -107,3 +107,44 @@ CONFIG_TSEC_ENET=y # CONFIG_PCI is not set CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_32_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="BCSR" +CONFIG_BR1_OR1_BASE=0xF8000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_32_KBYTES=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_EAD_EXTRA=y +CONFIG_OR1_SCY_15=y +CONFIG_OR1_XACS_EXTENDED=y +CONFIG_OR1_XAM_SET=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_OR1_EHTR_8_CYCLE=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="NAND" +CONFIG_BR3_OR3_BASE=0xE0600000 +CONFIG_BR3_ERRORCHECKING_BOTH=y +CONFIG_BR3_MACHINE_FCM=y +CONFIG_BR3_PORTSIZE_8BIT=y +CONFIG_OR3_AM_32_KBYTES=y +CONFIG_OR3_BCTLD_NOT_ASSERTED=y +CONFIG_OR3_RST_ONE_CLOCK=y +CONFIG_OR3_SCY_1=y +CONFIG_OR3_TRLX_RELAXED=y +CONFIG_OR3_CHT_TWO_CLOCK=y +CONFIG_OR3_CST_ONE_CLOCK=y +CONFIG_OR3_EHTR_8_CYCLE=y diff --git a/configs/MPC837XERDB_SLAVE_defconfig b/configs/MPC837XERDB_SLAVE_defconfig index 07016936d6..95400114f2 100644 --- a/configs/MPC837XERDB_SLAVE_defconfig +++ b/configs/MPC837XERDB_SLAVE_defconfig @@ -90,3 +90,39 @@ CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_8_MBYTES=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_9=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_EHTR_1_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="NAND" +CONFIG_BR1_OR1_BASE=0xE0600000 +CONFIG_BR1_ERRORCHECKING_BOTH=y +CONFIG_BR1_MACHINE_FCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_32_KBYTES=y +CONFIG_OR1_SCY_1=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_OR1_CHT_TWO_CLOCK=y +CONFIG_OR1_CSCT_8_CYCLE=y +CONFIG_OR1_CST_ONE_CLOCK=y +CONFIG_OR1_EHTR_8_CYCLE=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="VSC7385" +CONFIG_BR2_OR2_BASE=0xF0000000 +CONFIG_BR2_MACHINE_GPCM=y +CONFIG_BR2_PORTSIZE_8BIT=y +CONFIG_OR2_AM_128_KBYTES=y +CONFIG_OR2_CSNT_EARLIER=y +CONFIG_OR2_EAD_EXTRA=y +CONFIG_OR2_SCY_15=y +CONFIG_OR2_SETA_EXTERNAL=y +CONFIG_OR2_XACS_EXTENDED=y +CONFIG_OR2_TRLX_RELAXED=y +CONFIG_OR2_EHTR_8_CYCLE=y diff --git a/configs/MPC837XERDB_defconfig b/configs/MPC837XERDB_defconfig index 59d591fa05..a8c69eb6bc 100644 --- a/configs/MPC837XERDB_defconfig +++ b/configs/MPC837XERDB_defconfig @@ -133,3 +133,39 @@ CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_8_MBYTES=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_9=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_EHTR_1_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="NAND" +CONFIG_BR1_OR1_BASE=0xE0600000 +CONFIG_BR1_ERRORCHECKING_BOTH=y +CONFIG_BR1_MACHINE_FCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_32_KBYTES=y +CONFIG_OR1_SCY_1=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_OR1_CHT_TWO_CLOCK=y +CONFIG_OR1_CSCT_8_CYCLE=y +CONFIG_OR1_CST_ONE_CLOCK=y +CONFIG_OR1_EHTR_8_CYCLE=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="VSC7385" +CONFIG_BR2_OR2_BASE=0xF0000000 +CONFIG_BR2_MACHINE_GPCM=y +CONFIG_BR2_PORTSIZE_8BIT=y +CONFIG_OR2_AM_128_KBYTES=y +CONFIG_OR2_CSNT_EARLIER=y +CONFIG_OR2_EAD_EXTRA=y +CONFIG_OR2_SCY_15=y +CONFIG_OR2_SETA_EXTERNAL=y +CONFIG_OR2_XACS_EXTENDED=y +CONFIG_OR2_TRLX_RELAXED=y +CONFIG_OR2_EHTR_8_CYCLE=y diff --git a/configs/TQM834x_defconfig b/configs/TQM834x_defconfig index fdaded2970..49f0916663 100644 --- a/configs/TQM834x_defconfig +++ b/configs/TQM834x_defconfig @@ -134,3 +134,13 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0x80000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_32BIT=y +CONFIG_OR0_AM_1_GBYTES=y +CONFIG_OR0_ACS_QUARTER_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_SCY_5=y +CONFIG_OR0_TRLX_RELAXED=y diff --git a/configs/caddy2_defconfig b/configs/caddy2_defconfig index 12721f8db4..e2ea71d11a 100644 --- a/configs/caddy2_defconfig +++ b/configs/caddy2_defconfig @@ -92,3 +92,24 @@ CONFIG_E1000=y CONFIG_BAUDRATE=9600 CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFFC00000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_4_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="WINDOW1" +CONFIG_BR1_OR1_BASE=0xF0000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_32BIT=y +CONFIG_OR1_AM_256_KBYTES=y +CONFIG_OR1_SETA_EXTERNAL=y diff --git a/configs/hrcon_defconfig b/configs/hrcon_defconfig index f1aa24683c..7b17f602b6 100644 --- a/configs/hrcon_defconfig +++ b/configs/hrcon_defconfig @@ -89,3 +89,29 @@ CONFIG_TSEC_ENET=y CONFIG_CONS_INDEX=2 CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_8_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="FPGA" +CONFIG_BR1_OR1_BASE=0xE0600000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_16BIT=y +CONFIG_OR1_AM_1_MBYTES=y +CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_SCY_15=y +CONFIG_OR1_XACS_EXTENDED=y +CONFIG_OR1_XAM_SET=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_OR1_EHTR_8_CYCLE=y diff --git a/configs/hrcon_dh_defconfig b/configs/hrcon_dh_defconfig index 22689ef0ac..9a20a0d069 100644 --- a/configs/hrcon_dh_defconfig +++ b/configs/hrcon_dh_defconfig @@ -87,3 +87,29 @@ CONFIG_TSEC_ENET=y CONFIG_CONS_INDEX=2 CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_8_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="FPGA" +CONFIG_BR1_OR1_BASE=0xE0600000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_16BIT=y +CONFIG_OR1_AM_1_MBYTES=y +CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_SCY_15=y +CONFIG_OR1_XACS_EXTENDED=y +CONFIG_OR1_XAM_SET=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_OR1_EHTR_8_CYCLE=y diff --git a/configs/ids8313_defconfig b/configs/ids8313_defconfig index 168564606c..14104a441b 100644 --- a/configs/ids8313_defconfig +++ b/configs/ids8313_defconfig @@ -119,3 +119,48 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_MPC8XXX_SPI=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFF800000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_8BIT=y +CONFIG_OR0_AM_8_MBYTES=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_10=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="NAND" +CONFIG_BR1_OR1_BASE=0xE1000000 +CONFIG_BR1_ERRORCHECKING_BOTH=y +CONFIG_BR1_MACHINE_FCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_32_KBYTES=y +CONFIG_OR1_PGS_LARGE=y +CONFIG_OR1_RST_ONE_CLOCK=y +CONFIG_OR1_SCY_4=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_OR1_CHT_TWO_CLOCK=y +CONFIG_OR1_CSCT_8_CYCLE=y +CONFIG_OR1_CST_ONE_CLOCK=y +CONFIG_OR1_EHTR_8_CYCLE=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="MRAM" +CONFIG_BR2_OR2_BASE=0xE2000000 +CONFIG_BR2_MACHINE_GPCM=y +CONFIG_BR2_PORTSIZE_8BIT=y +CONFIG_OR2_AM_128_KBYTES=y +CONFIG_OR2_ACS_QUARTER_CYCLE_EARLIER=y +CONFIG_OR2_CSNT_EARLIER=y +CONFIG_OR2_SCY_7=y +CONFIG_OR2_TRLX_RELAXED=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="CPLD" +CONFIG_BR3_OR3_BASE=0xE3000000 +CONFIG_BR3_MACHINE_GPCM=y +CONFIG_BR3_PORTSIZE_8BIT=y +CONFIG_OR3_AM_32_KBYTES=y +CONFIG_OR3_CSNT_EARLIER=y +CONFIG_OR3_SCY_1=y +CONFIG_OR3_TRLX_RELAXED=y diff --git a/configs/kmcoge5ne_defconfig b/configs/kmcoge5ne_defconfig index 088dee63ba..6740c4c8a9 100644 --- a/configs/kmcoge5ne_defconfig +++ b/configs/kmcoge5ne_defconfig @@ -143,3 +143,45 @@ CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_NS16550=y CONFIG_BCH=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xF0000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_256_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_5=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="KMBEC_FPGA" +CONFIG_BR1_OR1_BASE=0xE8000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_64_MBYTES=y +CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_EAD_EXTRA=y +CONFIG_OR1_SCY_2=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="PAXE" +CONFIG_BR3_OR3_BASE=0xA0000000 +CONFIG_BR3_PORTSIZE_8BIT=y +CONFIG_OR3_AM_256_MBYTES=y +CONFIG_OR3_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR3_CSNT_EARLIER=y +CONFIG_OR3_EAD_EXTRA=y +CONFIG_OR3_SCY_2=y +CONFIG_OR3_TRLX_RELAXED=y +CONFIG_ELBC_BR4_OR4=y +CONFIG_BR4_OR4_NAME="BFTIC3" +CONFIG_BR4_OR4_BASE=0xB0000000 +CONFIG_BR4_PORTSIZE_8BIT=y +CONFIG_OR4_AM_256_MBYTES=y +CONFIG_OR4_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR4_CSNT_EARLIER=y +CONFIG_OR4_EAD_EXTRA=y +CONFIG_OR4_SCY_2=y +CONFIG_OR4_TRLX_RELAXED=y diff --git a/configs/kmeter1_defconfig b/configs/kmeter1_defconfig index 64ea83fd12..182fa477f8 100644 --- a/configs/kmeter1_defconfig +++ b/configs/kmeter1_defconfig @@ -115,3 +115,35 @@ CONFIG_SYS_FLASH_CFI=y # CONFIG_PCI is not set CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xF0000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_256_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_5=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="KMBEC_FPGA" +CONFIG_BR1_OR1_BASE=0xE8000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_64_MBYTES=y +CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_EAD_EXTRA=y +CONFIG_OR1_SCY_2=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="PAXE" +CONFIG_BR3_OR3_BASE=0xA0000000 +CONFIG_BR3_PORTSIZE_8BIT=y +CONFIG_OR3_AM_256_MBYTES=y +CONFIG_OR3_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR3_CSNT_EARLIER=y +CONFIG_OR3_EAD_EXTRA=y +CONFIG_OR3_SCY_2=y +CONFIG_OR3_TRLX_RELAXED=y diff --git a/configs/kmopti2_defconfig b/configs/kmopti2_defconfig index 3a88b6a027..678900d05c 100644 --- a/configs/kmopti2_defconfig +++ b/configs/kmopti2_defconfig @@ -130,3 +130,45 @@ CONFIG_SYS_FLASH_CFI=y # CONFIG_PCI is not set CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xF0000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_256_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_5=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="KMBEC_FPGA" +CONFIG_BR1_OR1_BASE=0xE8000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_128_MBYTES=y +CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_EAD_EXTRA=y +CONFIG_OR1_SCY_2=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="APP1" +CONFIG_BR2_OR2_BASE=0xA0000000 +CONFIG_BR2_MACHINE_GPCM=y +CONFIG_BR2_PORTSIZE_8BIT=y +CONFIG_OR2_AM_256_MBYTES=y +CONFIG_OR2_ACS_QUARTER_CYCLE_EARLIER=y +CONFIG_OR2_CSNT_EARLIER=y +CONFIG_OR2_EAD_EXTRA=y +CONFIG_OR2_SCY_2=y +CONFIG_OR2_TRLX_RELAXED=y +CONFIG_OR2_EHTR_4_CYCLE=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="APP2" +CONFIG_BR3_OR3_BASE=0xB0000000 +CONFIG_BR3_MACHINE_GPCM=y +CONFIG_BR3_PORTSIZE_16BIT=y +CONFIG_OR3_AM_256_MBYTES=y +CONFIG_OR3_SCY_4=y +CONFIG_OR3_EHTR_NORMAL=y diff --git a/configs/kmsupx5_defconfig b/configs/kmsupx5_defconfig index c818d7e4a1..49780b4b19 100644 --- a/configs/kmsupx5_defconfig +++ b/configs/kmsupx5_defconfig @@ -116,3 +116,37 @@ CONFIG_SYS_FLASH_CFI=y # CONFIG_PCI is not set CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xF0000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_256_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_5=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="KMBEC_FPGA" +CONFIG_BR1_OR1_BASE=0xE8000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_128_MBYTES=y +CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_EAD_EXTRA=y +CONFIG_OR1_SCY_2=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="APP1" +CONFIG_BR2_OR2_BASE=0xA0000000 +CONFIG_BR2_MACHINE_GPCM=y +CONFIG_BR2_PORTSIZE_8BIT=y +CONFIG_OR2_AM_256_MBYTES=y +CONFIG_OR2_ACS_QUARTER_CYCLE_EARLIER=y +CONFIG_OR2_CSNT_EARLIER=y +CONFIG_OR2_EAD_EXTRA=y +CONFIG_OR2_SCY_2=y +CONFIG_OR2_TRLX_RELAXED=y +CONFIG_OR2_EHTR_4_CYCLE=y diff --git a/configs/kmtegr1_defconfig b/configs/kmtegr1_defconfig index 640e0c7c3c..9a57e43d78 100644 --- a/configs/kmtegr1_defconfig +++ b/configs/kmtegr1_defconfig @@ -120,3 +120,33 @@ CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_NS16550=y CONFIG_BCH=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xF0000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_256_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_5=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="KMBEC_FPGA" +CONFIG_BR1_OR1_BASE=0xE8000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_128_MBYTES=y +CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_EAD_EXTRA=y +CONFIG_OR1_SCY_2=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="APP2" +CONFIG_BR3_OR3_BASE=0xB0000000 +CONFIG_BR3_MACHINE_GPCM=y +CONFIG_BR3_PORTSIZE_16BIT=y +CONFIG_OR3_AM_256_MBYTES=y +CONFIG_OR3_SCY_5=y +CONFIG_OR3_EHTR_NORMAL=y diff --git a/configs/kmtepr2_defconfig b/configs/kmtepr2_defconfig index 81579c6b02..78f7de9899 100644 --- a/configs/kmtepr2_defconfig +++ b/configs/kmtepr2_defconfig @@ -130,3 +130,45 @@ CONFIG_SYS_FLASH_CFI=y # CONFIG_PCI is not set CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xF0000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_256_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_5=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="KMBEC_FPGA" +CONFIG_BR1_OR1_BASE=0xE8000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_128_MBYTES=y +CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_EAD_EXTRA=y +CONFIG_OR1_SCY_2=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="APP1" +CONFIG_BR2_OR2_BASE=0xA0000000 +CONFIG_BR2_MACHINE_GPCM=y +CONFIG_BR2_PORTSIZE_8BIT=y +CONFIG_OR2_AM_256_MBYTES=y +CONFIG_OR2_ACS_QUARTER_CYCLE_EARLIER=y +CONFIG_OR2_CSNT_EARLIER=y +CONFIG_OR2_EAD_EXTRA=y +CONFIG_OR2_SCY_2=y +CONFIG_OR2_TRLX_RELAXED=y +CONFIG_OR2_EHTR_4_CYCLE=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="APP2" +CONFIG_BR3_OR3_BASE=0xB0000000 +CONFIG_BR3_MACHINE_GPCM=y +CONFIG_BR3_PORTSIZE_16BIT=y +CONFIG_OR3_AM_256_MBYTES=y +CONFIG_OR3_SCY_4=y +CONFIG_OR3_EHTR_NORMAL=y diff --git a/configs/kmvect1_defconfig b/configs/kmvect1_defconfig index 709947b539..7256750ea0 100644 --- a/configs/kmvect1_defconfig +++ b/configs/kmvect1_defconfig @@ -133,3 +133,40 @@ CONFIG_SYS_FLASH_CFI=y # CONFIG_PCI is not set CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xF0000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_256_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_5=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="KMBEC_FPGA" +CONFIG_BR1_OR1_BASE=0xE8000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_128_MBYTES=y +CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_EAD_EXTRA=y +CONFIG_OR1_SCY_2=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="APP1" +CONFIG_BR2_OR2_BASE=0xA0000000 +CONFIG_BR2_MACHINE_UPMA=y +CONFIG_BR2_PORTSIZE_16BIT=y +CONFIG_OR2_AM_256_MBYTES=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="APP2" +CONFIG_BR3_OR3_BASE=0xB0000000 +CONFIG_BR3_PORTSIZE_16BIT=y +CONFIG_OR3_AM_256_MBYTES=y +CONFIG_OR3_ACS_QUARTER_CYCLE_EARLIER=y +CONFIG_OR3_CSNT_EARLIER=y +CONFIG_OR3_SCY_3=y +CONFIG_OR3_TRLX_RELAXED=y diff --git a/configs/mpc8308_p1m_defconfig b/configs/mpc8308_p1m_defconfig index b44e04e1ae..ec2e30709c 100644 --- a/configs/mpc8308_p1m_defconfig +++ b/configs/mpc8308_p1m_defconfig @@ -78,3 +78,32 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFC000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_64_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_SCY_4=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="SJA1000" +CONFIG_BR1_OR1_BASE=0xFBFF0000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_32_KBYTES=y +CONFIG_OR1_SCY_5=y +CONFIG_OR1_EHTR_1_CYCLE=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="CPLD" +CONFIG_BR2_OR2_BASE=0xFBFF8000 +CONFIG_BR2_MACHINE_GPCM=y +CONFIG_BR2_PORTSIZE_8BIT=y +CONFIG_OR2_AM_32_KBYTES=y +CONFIG_OR2_SCY_4=y +CONFIG_OR2_EHTR_1_CYCLE=y diff --git a/configs/sbc8349_PCI_33_defconfig b/configs/sbc8349_PCI_33_defconfig index 6f407d56d5..453f85a0e3 100644 --- a/configs/sbc8349_PCI_33_defconfig +++ b/configs/sbc8349_PCI_33_defconfig @@ -89,3 +89,17 @@ CONFIG_PHY_MARVELL=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFF800000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_8_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y diff --git a/configs/sbc8349_PCI_66_defconfig b/configs/sbc8349_PCI_66_defconfig index 9c0b30f446..b304615630 100644 --- a/configs/sbc8349_PCI_66_defconfig +++ b/configs/sbc8349_PCI_66_defconfig @@ -89,3 +89,17 @@ CONFIG_PHY_MARVELL=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFF800000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_8_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y diff --git a/configs/sbc8349_defconfig b/configs/sbc8349_defconfig index 05361f76fc..4ec51af9f2 100644 --- a/configs/sbc8349_defconfig +++ b/configs/sbc8349_defconfig @@ -67,3 +67,17 @@ CONFIG_TSEC_ENET=y # CONFIG_PCI is not set CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFF800000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_8_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y diff --git a/configs/strider_con_defconfig b/configs/strider_con_defconfig index 196c44470a..a806e9957f 100644 --- a/configs/strider_con_defconfig +++ b/configs/strider_con_defconfig @@ -91,3 +91,26 @@ CONFIG_TSEC_ENET=y CONFIG_CONS_INDEX=2 CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_8_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="FPGA" +CONFIG_BR1_OR1_BASE=0xE0600000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_16BIT=y +CONFIG_OR1_AM_1_MBYTES=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_SCY_5=y +CONFIG_OR1_XAM_SET=y +CONFIG_OR1_EHTR_NORMAL=y diff --git a/configs/strider_con_dp_defconfig b/configs/strider_con_dp_defconfig index c407bed189..3687a28fc3 100644 --- a/configs/strider_con_dp_defconfig +++ b/configs/strider_con_dp_defconfig @@ -91,3 +91,26 @@ CONFIG_TSEC_ENET=y CONFIG_CONS_INDEX=2 CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_8_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="FPGA" +CONFIG_BR1_OR1_BASE=0xE0600000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_16BIT=y +CONFIG_OR1_AM_1_MBYTES=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_SCY_5=y +CONFIG_OR1_XAM_SET=y +CONFIG_OR1_EHTR_NORMAL=y diff --git a/configs/strider_cpu_defconfig b/configs/strider_cpu_defconfig index 1128950ace..4231a431b8 100644 --- a/configs/strider_cpu_defconfig +++ b/configs/strider_cpu_defconfig @@ -91,3 +91,26 @@ CONFIG_TSEC_ENET=y CONFIG_CONS_INDEX=2 CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_8_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="FPGA" +CONFIG_BR1_OR1_BASE=0xE0600000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_16BIT=y +CONFIG_OR1_AM_1_MBYTES=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_SCY_5=y +CONFIG_OR1_XAM_SET=y +CONFIG_OR1_EHTR_NORMAL=y diff --git a/configs/strider_cpu_dp_defconfig b/configs/strider_cpu_dp_defconfig index f0b2c44efb..afb991ce1e 100644 --- a/configs/strider_cpu_dp_defconfig +++ b/configs/strider_cpu_dp_defconfig @@ -91,3 +91,26 @@ CONFIG_TSEC_ENET=y CONFIG_CONS_INDEX=2 CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_8_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="FPGA" +CONFIG_BR1_OR1_BASE=0xE0600000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_16BIT=y +CONFIG_OR1_AM_1_MBYTES=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_SCY_5=y +CONFIG_OR1_XAM_SET=y +CONFIG_OR1_EHTR_NORMAL=y diff --git a/configs/suvd3_defconfig b/configs/suvd3_defconfig index 10a32178f1..2b16ceb524 100644 --- a/configs/suvd3_defconfig +++ b/configs/suvd3_defconfig @@ -131,3 +131,40 @@ CONFIG_SYS_FLASH_CFI=y # CONFIG_PCI is not set CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xF0000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_256_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_5=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="KMBEC_FPGA" +CONFIG_BR1_OR1_BASE=0xE8000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_128_MBYTES=y +CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_EAD_EXTRA=y +CONFIG_OR1_SCY_2=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="APP1" +CONFIG_BR2_OR2_BASE=0xA0000000 +CONFIG_BR2_MACHINE_UPMA=y +CONFIG_BR2_PORTSIZE_16BIT=y +CONFIG_OR2_AM_256_MBYTES=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="APP2" +CONFIG_BR3_OR3_BASE=0xB0000000 +CONFIG_BR3_PORTSIZE_16BIT=y +CONFIG_OR3_AM_256_MBYTES=y +CONFIG_OR3_ACS_QUARTER_CYCLE_EARLIER=y +CONFIG_OR3_CSNT_EARLIER=y +CONFIG_OR3_SCY_3=y +CONFIG_OR3_TRLX_RELAXED=y diff --git a/configs/tuge1_defconfig b/configs/tuge1_defconfig index 6fada9bdf7..07666c3b50 100644 --- a/configs/tuge1_defconfig +++ b/configs/tuge1_defconfig @@ -116,3 +116,37 @@ CONFIG_SYS_FLASH_CFI=y # CONFIG_PCI is not set CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xF0000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_256_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_5=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="KMBEC_FPGA" +CONFIG_BR1_OR1_BASE=0xE8000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_128_MBYTES=y +CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_EAD_EXTRA=y +CONFIG_OR1_SCY_2=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="APP1" +CONFIG_BR2_OR2_BASE=0xA0000000 +CONFIG_BR2_MACHINE_GPCM=y +CONFIG_BR2_PORTSIZE_8BIT=y +CONFIG_OR2_AM_256_MBYTES=y +CONFIG_OR2_ACS_QUARTER_CYCLE_EARLIER=y +CONFIG_OR2_CSNT_EARLIER=y +CONFIG_OR2_EAD_EXTRA=y +CONFIG_OR2_SCY_2=y +CONFIG_OR2_TRLX_RELAXED=y +CONFIG_OR2_EHTR_4_CYCLE=y diff --git a/configs/tuxx1_defconfig b/configs/tuxx1_defconfig index 1eb21e0e5a..627bf2febf 100644 --- a/configs/tuxx1_defconfig +++ b/configs/tuxx1_defconfig @@ -130,3 +130,48 @@ CONFIG_SYS_FLASH_CFI=y # CONFIG_PCI is not set CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xF0000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_256_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_5=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="KMBEC_FPGA" +CONFIG_BR1_OR1_BASE=0xE8000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_128_MBYTES=y +CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_EAD_EXTRA=y +CONFIG_OR1_SCY_2=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="APP1" +CONFIG_BR2_OR2_BASE=0xA0000000 +CONFIG_BR2_MACHINE_GPCM=y +CONFIG_BR2_PORTSIZE_8BIT=y +CONFIG_OR2_AM_256_MBYTES=y +CONFIG_OR2_ACS_QUARTER_CYCLE_EARLIER=y +CONFIG_OR2_CSNT_EARLIER=y +CONFIG_OR2_EAD_EXTRA=y +CONFIG_OR2_SCY_2=y +CONFIG_OR2_TRLX_RELAXED=y +CONFIG_OR2_EHTR_4_CYCLE=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="APP2" +CONFIG_BR3_OR3_BASE=0xB0000000 +CONFIG_BR3_MACHINE_GPCM=y +CONFIG_BR3_PORTSIZE_8BIT=y +CONFIG_OR3_AM_256_MBYTES=y +CONFIG_OR3_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR3_CSNT_EARLIER=y +CONFIG_OR3_SCY_2=y +CONFIG_OR3_TRLX_RELAXED=y +CONFIG_OR3_EHTR_4_CYCLE=y diff --git a/configs/ve8313_defconfig b/configs/ve8313_defconfig index 1df5195e97..365c4ea858 100644 --- a/configs/ve8313_defconfig +++ b/configs/ve8313_defconfig @@ -95,3 +95,48 @@ CONFIG_PHY_MARVELL=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_32_MBYTES=y +CONFIG_OR0_ACS_QUARTER_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_5=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="NAND" +CONFIG_BR1_OR1_BASE=0x61000000 +CONFIG_BR1_ERRORCHECKING_BOTH=y +CONFIG_BR1_MACHINE_FCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_32_KBYTES=y +CONFIG_OR1_BCTLD_NOT_ASSERTED=y +CONFIG_OR1_RST_ONE_CLOCK=y +CONFIG_OR1_SCY_2=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_OR1_CHT_TWO_CLOCK=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="NVRAM" +CONFIG_BR2_OR2_BASE=0x60000000 +CONFIG_BR2_PORTSIZE_8BIT=y +CONFIG_OR2_AM_128_KBYTES=y +CONFIG_OR2_CSNT_EARLIER=y +CONFIG_OR2_EAD_EXTRA=y +CONFIG_OR2_SCY_3=y +CONFIG_OR2_XACS_EXTENDED=y +CONFIG_OR2_TRLX_RELAXED=y +CONFIG_OR2_EHTR_8_CYCLE=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="SRAM" +CONFIG_BR3_OR3_BASE=0x62000000 +CONFIG_BR3_PORTSIZE_16BIT=y +CONFIG_OR3_AM_32_MBYTES=y +CONFIG_OR3_CSNT_EARLIER=y +CONFIG_OR3_EAD_EXTRA=y +CONFIG_OR3_SCY_15=y +CONFIG_OR3_XACS_EXTENDED=y +CONFIG_OR3_TRLX_RELAXED=y +CONFIG_OR3_EHTR_8_CYCLE=y diff --git a/configs/vme8349_defconfig b/configs/vme8349_defconfig index 9336dfac5c..072674cbeb 100644 --- a/configs/vme8349_defconfig +++ b/configs/vme8349_defconfig @@ -94,3 +94,24 @@ CONFIG_TSEC_ENET=y CONFIG_BAUDRATE=9600 CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xF8000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_128_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="WINDOW1" +CONFIG_BR1_OR1_BASE=0xF0000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_32BIT=y +CONFIG_OR1_AM_256_KBYTES=y +CONFIG_OR1_SETA_EXTERNAL=y diff --git a/drivers/mtd/nand/raw/fsl_elbc_spl.c b/drivers/mtd/nand/raw/fsl_elbc_spl.c index 30c3308940..099d86427c 100644 --- a/drivers/mtd/nand/raw/fsl_elbc_spl.c +++ b/drivers/mtd/nand/raw/fsl_elbc_spl.c @@ -14,6 +14,10 @@ #include #include +#ifdef CONFIG_MPC83xx +#include "../../../arch/powerpc/cpu/mpc83xx/elbc/elbc.h" +#endif + #define WINDOW_SIZE 8192 static void nand_wait(void) diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h index 185f6490d7..cd78836bcd 100644 --- a/include/configs/MPC8308RDB.h +++ b/include/configs/MPC8308RDB.h @@ -175,9 +175,6 @@ #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is 8M */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB | OR_UPM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ /* 127 64KB sectors and 8 8KB top sectors per device */ @@ -191,9 +188,6 @@ */ #define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */ #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) /* 0x00008000 */ -/* NAND */ -#define CONFIG_SYS_BR1_PRELIM (0xE0600000 | BR_DECC_CHK_GEN | BR_PS_8 | BR_MS_FCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_FCM_CSCT | OR_FCM_CST | OR_FCM_CHT | OR_FCM_SCY_1 | OR_FCM_TRLX | OR_FCM_EHTR) /* 0xFFFF8396 */ #ifdef CONFIG_VSC7385_ENET @@ -201,9 +195,6 @@ /* VSC7385 Base address on CS2 */ #define CONFIG_SYS_VSC7385_BASE 0xF0000000 #define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */ -/* VSC7385_BASE */ -#define CONFIG_SYS_BR2_PRELIM (0xF0000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET) /* 0xFFFE09FF */ /* The flash address and size of the VSC7385 firmware image */ #define CONFIG_VSC7385_IMAGE 0xFE7FE000 diff --git a/include/configs/MPC8313ERDB_NAND.h b/include/configs/MPC8313ERDB_NAND.h index 40b0264dbe..93b553c905 100644 --- a/include/configs/MPC8313ERDB_NAND.h +++ b/include/configs/MPC8313ERDB_NAND.h @@ -219,14 +219,6 @@ #define CONFIG_SYS_NAND_BLOCK_SIZE 16384 #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) -/* NAND */ -#define CONFIG_SYS_BR0_PRELIM (0xE2800000 | BR_DECC_CHK_GEN | BR_PS_8 | BR_MS_FCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_32KB | OR_FCM_CSCT | OR_FCM_CST | OR_FCM_CHT | OR_FCM_SCY_1 | OR_FCM_TRLX | OR_FCM_EHTR) - -/* FLASH */ -#define CONFIG_SYS_BR1_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_8MB | OR_GPCM_XACS | OR_GPCM_SCY_9 | OR_GPCM_EHTR_SET | OR_GPCM_EAD) - /* Still needed for spl_minimal.c */ #define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR0_PRELIM #define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR0_PRELIM @@ -235,9 +227,6 @@ #define CONFIG_SYS_BCSR_ADDR 0xFA000000 #define CONFIG_SYS_BCSR_SIZE (32 * 1024) /* 0x00008000 */ /* map at 0xFA000000 on LCS3 */ -/* BCSR */ -#define CONFIG_SYS_BR3_PRELIM (0xFA000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) /* Vitesse 7385 */ @@ -247,9 +236,6 @@ #define CONFIG_SYS_VSC7385_BASE 0xF0000000 #define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */ -/* VSC7385 */ -#define CONFIG_SYS_BR2_PRELIM (0xF0000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) #endif diff --git a/include/configs/MPC8313ERDB_NOR.h b/include/configs/MPC8313ERDB_NOR.h index 390ee4eb26..18e056e1b2 100644 --- a/include/configs/MPC8313ERDB_NOR.h +++ b/include/configs/MPC8313ERDB_NOR.h @@ -188,14 +188,6 @@ #define CONFIG_SYS_NAND_BLOCK_SIZE 16384 #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) -/* FLASH*/ -#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB | OR_GPCM_XACS | OR_GPCM_SCY_9 | OR_GPCM_EHTR_SET | OR_GPCM_EAD) - -/* NAND */ -#define CONFIG_SYS_BR1_PRELIM (0xE2800000 | BR_DECC_CHK_GEN | BR_PS_8 | BR_MS_FCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_FCM_CSCT | OR_FCM_CST | OR_FCM_CHT | OR_FCM_SCY_1 | OR_FCM_TRLX | OR_FCM_EHTR) - /* Still needed for spl_minimal.c */ #define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM #define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM @@ -204,9 +196,6 @@ #define CONFIG_SYS_BCSR_ADDR 0xFA000000 #define CONFIG_SYS_BCSR_SIZE (32 * 1024) /* 0x00008000 */ /* map at 0xFA000000 on LCS3 */ -/* BCSR */ -#define CONFIG_SYS_BR3_PRELIM (0xFA000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) /* Vitesse 7385 */ #ifdef CONFIG_VSC7385_ENET @@ -215,9 +204,6 @@ #define CONFIG_SYS_VSC7385_BASE 0xF0000000 #define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */ -/* VSC7385 */ -#define CONFIG_SYS_BR2_PRELIM (0xF0000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) #endif diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index 97b66415c9..708829dae8 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -177,13 +177,7 @@ #define CONFIG_SYS_NAND_U_BOOT_OFFS 16384 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000 -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB | OR_UPM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) -/* NAND */ -#define CONFIG_SYS_BR1_PRELIM (0xE0600000 | BR_DECC_CHK_GEN | BR_PS_8 | BR_MS_FCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_FCM_CSCT | OR_FCM_CST | OR_FCM_CHT | OR_FCM_SCY_1 | OR_FCM_TRLX | OR_FCM_EHTR) /* Still needed for spl_minimal.c */ #define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index fd884a1e65..c66e33a247 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -142,9 +142,6 @@ #define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size is 16M */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_16MB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index 41b0223135..ed47bcd5b4 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -133,9 +133,6 @@ #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ #define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size is 16M */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_16MB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ @@ -148,9 +145,6 @@ #define CONFIG_SYS_BCSR 0xF8000000 /* Access window base at BCSR base */ -/* BCSR */ -#define CONFIG_SYS_BR1_PRELIM (0xF8000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) /* * Windows to access PIB via local bus @@ -163,17 +157,11 @@ * CS2 on Local Bus, to PIB */ -/* PIB1 */ -#define CONFIG_SYS_BR2_PRELIM (0xF8008000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) /* * CS3 on Local Bus, to PIB */ -/* PIB2 */ -#define CONFIG_SYS_BR3_PRELIM (0xF8010000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) /* * Serial Port diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 4cda1589b6..3e0907dae4 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -123,9 +123,6 @@ #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ #define CONFIG_SYS_FLASH_SIZE 32 /* max flash size in MB */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_32MB | OR_UPM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ @@ -148,9 +145,6 @@ #define CONFIG_SYS_BCSR 0xE2400000 /* Access window base at BCSR base */ -/* BCSR */ -#define CONFIG_SYS_BR1_PRELIM (0xE2400000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_SCY_15 | OR_GPCM_TRLX_CLEAR | OR_GPCM_EHTR_CLEAR) #define CONFIG_SYS_INIT_RAM_LOCK 1 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */ diff --git a/include/configs/MPC8349EMDS_SDRAM.h b/include/configs/MPC8349EMDS_SDRAM.h index 7f906c38d8..e401c29d6b 100644 --- a/include/configs/MPC8349EMDS_SDRAM.h +++ b/include/configs/MPC8349EMDS_SDRAM.h @@ -123,10 +123,6 @@ #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ #define CONFIG_SYS_FLASH_SIZE 32 /* max flash size in MB */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_32MB | OR_UPM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) - #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ @@ -147,10 +143,6 @@ */ #define CONFIG_SYS_BCSR 0xE2400000 /* Access window base at BCSR base */ -/* BCSR */ -#define CONFIG_SYS_BR1_PRELIM (0xE2400000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_SCY_15 | OR_GPCM_TRLX_CLEAR | OR_GPCM_EHTR_CLEAR) - #define CONFIG_SYS_INIT_RAM_LOCK 1 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */ #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ @@ -192,10 +184,6 @@ * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861 */ -/* SDRAM */ -#define CONFIG_SYS_BR2_PRELIM (0xF0000000 | BR_PS_32 | BR_MS_SDRAM | BR_V) -#define CONFIG_SYS_OR2_PRELIM (OR_AM_64MB | OR_SDRAM_XAM | ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) | ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) | OR_SDRAM_EAD) - /* * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. * diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index e90d497f5e..cc62fc3213 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -211,9 +211,6 @@ boards, we say we have two, but don't display a message if we find only one. */ * BRx, ORx, LBLAWBARx, and LBLAWARx */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_16MB | OR_UPM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) /* Vitesse 7385 */ @@ -221,18 +218,12 @@ boards, we say we have two, but don't display a message if we find only one. */ #ifdef CONFIG_VSC7385_ENET -/* VSC7385 */ -#define CONFIG_SYS_BR1_PRELIM (0xF8000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) #endif #define CONFIG_SYS_LED_BASE 0xF9000000 -/* LED */ -#define CONFIG_SYS_BR2_PRELIM (0xF9000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR2_PRELIM (OR_AM_2MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_9 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) /* Compact Flash */ @@ -240,9 +231,6 @@ boards, we say we have two, but don't display a message if we find only one. */ #define CONFIG_SYS_CF_BASE 0xF0000000 -/* CF */ -#define CONFIG_SYS_BR3_PRELIM (0xF0000000 | BR_PS_16 | BR_MS_UPMA | BR_V) -#define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB | OR_UPM_BI) #endif diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index e569e63741..a244ae87a2 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -162,9 +162,6 @@ #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ #define CONFIG_SYS_FLASH_SIZE 32 /* max FLASH size is 32M */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_32MB | OR_UPM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ @@ -178,9 +175,6 @@ */ #define CONFIG_SYS_BCSR 0xF8000000 /* Access window base at BCSR base */ -/* BCSR */ -#define CONFIG_SYS_BR1_PRELIM (0xF8000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) /* * NAND Flash on the Local Bus @@ -190,9 +184,6 @@ #define CONFIG_SYS_NAND_BASE 0xE0600000 -/* NAND */ -#define CONFIG_SYS_BR3_PRELIM (0xE0600000 | BR_DECC_CHK_GEN | BR_PS_8 | BR_MS_FCM | BR_V) -#define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB | OR_FCM_BCTLD | OR_FCM_CST | OR_FCM_CHT | OR_FCM_SCY_1 | OR_FCM_RST | OR_FCM_TRLX | OR_FCM_EHTR) /* * Serial Port diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index c1898a53a6..006279a58c 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -188,9 +188,6 @@ #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB | OR_GPCM_XACS | OR_GPCM_SCY_9 | OR_GPCM_EHTR_SET | OR_GPCM_EAD) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ @@ -204,9 +201,6 @@ */ #define CONFIG_SYS_NAND_BASE 0xE0600000 -/* NAND */ -#define CONFIG_SYS_BR1_PRELIM (0xE0600000 | BR_DECC_CHK_GEN | BR_PS_8 | BR_MS_FCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_FCM_CSCT | OR_FCM_CST | OR_FCM_CHT | OR_FCM_SCY_1 | OR_FCM_TRLX | OR_FCM_EHTR) /* Vitesse 7385 */ @@ -214,9 +208,6 @@ #ifdef CONFIG_VSC7385_ENET -/* VSC7385 */ -#define CONFIG_SYS_BR2_PRELIM (0xF0000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) #endif diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index c76df2847d..af03c03786 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -76,9 +76,6 @@ #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors per device */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0x80000000 | BR_MS_GPCM | BR_PS_32 | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_1GB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET) /* disable remaining mappings */ #define CONFIG_SYS_BR1_PRELIM 0x00000000 diff --git a/include/configs/caddy2.h b/include/configs/caddy2.h index a7eb5f5295..e9cfeae64d 100644 --- a/include/configs/caddy2.h +++ b/include/configs/caddy2.h @@ -70,15 +70,9 @@ #define CONFIG_SYS_FLASH_BASE 0xffc00000 /* start of FLASH */ #define CONFIG_SYS_FLASH_SIZE 4 /* flash size in MB */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xFFC00000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_4MB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) #define CONFIG_SYS_WINDOW1_BASE 0xf0000000 -/* WINDOW1 */ -#define CONFIG_SYS_BR1_PRELIM (0xF0000000 | BR_PS_32 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_256KB | OR_GPCM_SETA) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device*/ diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h index 3fe72db188..9318e6252a 100644 --- a/include/configs/hrcon.h +++ b/include/configs/hrcon.h @@ -169,9 +169,6 @@ #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB | OR_UPM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 135 @@ -185,9 +182,6 @@ #define CONFIG_SYS_FPGA0_BASE 0xE0600000 #define CONFIG_SYS_FPGA0_SIZE 1 /* FPGA size is 1M */ -/* FPGA */ -#define CONFIG_SYS_BR1_PRELIM (0xE0600000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_1MB | OR_UPM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET) #define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE #define CONFIG_SYS_FPGA_DONE(k) 0x0010 diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h index 61f64ebbbc..d86dda18fb 100644 --- a/include/configs/ids8313.h +++ b/include/configs/ids8313.h @@ -142,9 +142,6 @@ #define CONFIG_SYS_FLASH_BASE 0xFF800000 #define CONFIG_SYS_FLASH_SIZE 8 -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xFF800000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB | OR_GPCM_SCY_10 | OR_GPCM_EHTR_SET | OR_GPCM_TRLX_SET | OR_GPCM_CSNT | OR_GPCM_EAD) #define CONFIG_SYS_MAX_FLASH_BANKS 1 #define CONFIG_SYS_MAX_FLASH_SECT 128 @@ -163,9 +160,6 @@ #define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10) #define NAND_CACHE_PAGES 64 -/* NAND */ -#define CONFIG_SYS_BR1_PRELIM (0xE1000000 | BR_DECC_CHK_GEN | BR_PS_8 | BR_MS_FCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_FCM_PGS | OR_FCM_CSCT | OR_FCM_CST | OR_FCM_CHT | OR_FCM_SCY_4 | OR_FCM_TRLX | OR_FCM_EHTR | OR_FCM_RST) /* * MRAM setup @@ -175,9 +169,6 @@ #define CONFIG_SYS_OR_TIMING_MRAM -/* MRAM */ -#define CONFIG_SYS_BR2_PRELIM (0xE2000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_7 | OR_GPCM_TRLX_SET) /* * CPLD setup @@ -187,9 +178,6 @@ #define CONFIG_SYS_OR_TIMING_MRAM -/* CPLD */ -#define CONFIG_SYS_BR3_PRELIM (0xE3000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB | OR_GPCM_CSNT | OR_GPCM_SCY_1 | OR_GPCM_TRLX_SET) /* * HW-Watchdog diff --git a/include/configs/kmcoge5ne.h b/include/configs/kmcoge5ne.h index 5027073d6e..ede8ae6ba5 100644 --- a/include/configs/kmcoge5ne.h +++ b/include/configs/kmcoge5ne.h @@ -108,9 +108,6 @@ */ #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xF0000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ @@ -120,9 +117,6 @@ * PRIO1/PIGGY on the local bus CS1 */ -/* KMBEC_FPGA */ -#define CONFIG_SYS_BR1_PRELIM (0xE8000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_64MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) /* * Serial Port @@ -336,9 +330,6 @@ #define CONFIG_SYS_PAXE_BASE 0xA0000000 #define CONFIG_SYS_PAXE_SIZE 256 -/* PAXE */ -#define CONFIG_SYS_BR3_PRELIM (0xA0000000 | BR_PS_8 | BR_V) -#define CONFIG_SYS_OR3_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) /* * BFTIC3 on the local bus CS4 @@ -346,9 +337,6 @@ #define CONFIG_SYS_BFTIC3_BASE 0xB0000000 #define CONFIG_SYS_BFTIC3_SIZE 256 -/* BFTIC3 */ -#define CONFIG_SYS_BR4_PRELIM (0xB0000000 | BR_PS_8 | BR_V) -#define CONFIG_SYS_OR4_PRELIM (OR_AM_256MB| OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) /* enable POST tests */ #define CONFIG_POST (CONFIG_SYS_POST_MEMORY|CONFIG_SYS_POST_MEM_REGIONS) diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h index 84516bb9bb..728c9b199f 100644 --- a/include/configs/kmeter1.h +++ b/include/configs/kmeter1.h @@ -93,9 +93,6 @@ */ #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xF0000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ @@ -105,9 +102,6 @@ * PRIO1/PIGGY on the local bus CS1 */ -/* KMBEC_FPGA */ -#define CONFIG_SYS_BR1_PRELIM (0xE8000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_64MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) /* * Serial Port @@ -316,8 +310,5 @@ #define CONFIG_SYS_PAXE_BASE 0xA0000000 #define CONFIG_SYS_PAXE_SIZE 256 -/* PAXE */ -#define CONFIG_SYS_BR3_PRELIM (0xA0000000 | BR_PS_8 | BR_V) -#define CONFIG_SYS_OR3_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) #endif /* CONFIG */ diff --git a/include/configs/kmopti2.h b/include/configs/kmopti2.h index 678cb6a7cc..f39dbe05b7 100644 --- a/include/configs/kmopti2.h +++ b/include/configs/kmopti2.h @@ -113,9 +113,6 @@ */ #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xF0000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ @@ -125,9 +122,6 @@ * PRIO1/PIGGY on the local bus CS1 */ -/* KMBEC_FPGA */ -#define CONFIG_SYS_BR1_PRELIM (0xE8000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_128MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) /* * Serial Port @@ -351,16 +345,10 @@ * Configuration for C2 on the local bus */ -/* APP1 */ -#define CONFIG_SYS_BR2_PRELIM (0xA0000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR2_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_CLEAR | OR_GPCM_EAD) /* * Configuration for C3 on the local bus */ -/* APP2 */ -#define CONFIG_SYS_BR3_PRELIM (0xB0000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR3_PRELIM (OR_AM_256MB | OR_GPCM_SCY_4 | OR_GPCM_TRLX_CLEAR | OR_GPCM_EHTR_CLEAR) #endif /* __CONFIG_H */ diff --git a/include/configs/kmsupx5.h b/include/configs/kmsupx5.h index 3e2e425c34..19e415619a 100644 --- a/include/configs/kmsupx5.h +++ b/include/configs/kmsupx5.h @@ -113,9 +113,6 @@ */ #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xF0000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ @@ -125,9 +122,6 @@ * PRIO1/PIGGY on the local bus CS1 */ -/* KMBEC_FPGA */ -#define CONFIG_SYS_BR1_PRELIM (0xE8000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_128MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) /* * Serial Port @@ -345,8 +339,5 @@ * 3 Local GPCM 8 bit 256MB TEP2 (16 bit) */ -/* APP1 */ -#define CONFIG_SYS_BR2_PRELIM (0xA0000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR2_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_CLEAR | OR_GPCM_EAD) #endif /* __CONFIG_H */ diff --git a/include/configs/kmtegr1.h b/include/configs/kmtegr1.h index ed221e2301..fe4763ce8a 100644 --- a/include/configs/kmtegr1.h +++ b/include/configs/kmtegr1.h @@ -120,9 +120,6 @@ */ #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xF0000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ @@ -132,9 +129,6 @@ * PRIO1/PIGGY on the local bus CS1 */ -/* KMBEC_FPGA */ -#define CONFIG_SYS_BR1_PRELIM (0xE8000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_128MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) /* * Serial Port @@ -400,9 +394,6 @@ * */ -/* APP2 */ -#define CONFIG_SYS_BR3_PRELIM (0xB0000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR3_PRELIM (OR_AM_256MB | OR_GPCM_SCY_5 | OR_GPCM_TRLX_CLEAR | OR_GPCM_EHTR_CLEAR) /* ethernet port connected to piggy (UEC2) */ #define CONFIG_HAS_ETH1 diff --git a/include/configs/kmtepr2.h b/include/configs/kmtepr2.h index c1ed71e2af..9302d35949 100644 --- a/include/configs/kmtepr2.h +++ b/include/configs/kmtepr2.h @@ -113,9 +113,6 @@ */ #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xF0000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ @@ -125,9 +122,6 @@ * PRIO1/PIGGY on the local bus CS1 */ -/* KMBEC_FPGA */ -#define CONFIG_SYS_BR1_PRELIM (0xE8000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_128MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) /* * Serial Port @@ -347,12 +341,6 @@ * 3 Local GPCM 8 bit 256MB TEP2 (16 bit) */ -/* APP1 */ -#define CONFIG_SYS_BR2_PRELIM (0xA0000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR2_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_CLEAR | OR_GPCM_EAD) -/* APP2 */ -#define CONFIG_SYS_BR3_PRELIM (0xB0000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR3_PRELIM (OR_AM_256MB | OR_GPCM_SCY_4 | OR_GPCM_TRLX_CLEAR | OR_GPCM_EHTR_CLEAR) #endif /* __CONFIG_H */ diff --git a/include/configs/kmvect1.h b/include/configs/kmvect1.h index 406b6e7824..06c5923ae1 100644 --- a/include/configs/kmvect1.h +++ b/include/configs/kmvect1.h @@ -112,9 +112,6 @@ */ #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xF0000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ @@ -124,9 +121,6 @@ * PRIO1/PIGGY on the local bus CS1 */ -/* KMBEC_FPGA */ -#define CONFIG_SYS_BR1_PRELIM (0xE8000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_128MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) /* * Serial Port @@ -389,13 +383,7 @@ * */ -/* APP1 */ -#define CONFIG_SYS_BR2_PRELIM (0xA0000000 | BR_PS_16 | BR_MS_UPMA | BR_V) -#define CONFIG_SYS_OR2_PRELIM (OR_AM_256MB) -/* APP2 */ -#define CONFIG_SYS_BR3_PRELIM (0xB0000000 | BR_PS_16 | BR_V) -#define CONFIG_SYS_OR3_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_3 | OR_GPCM_TRLX_SET) #define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \ 0x0000c000 | \ diff --git a/include/configs/mpc8308_p1m.h b/include/configs/mpc8308_p1m.h index 31bf9971ab..cb7dabd932 100644 --- a/include/configs/mpc8308_p1m.h +++ b/include/configs/mpc8308_p1m.h @@ -179,9 +179,6 @@ #define CONFIG_SYS_FLASH_BASE 0xFC000000 /* FLASH base address */ #define CONFIG_SYS_FLASH_SIZE 64 /* FLASH size is 64M */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xFC000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_64MB | OR_UPM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_4 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 512 @@ -196,18 +193,12 @@ */ #define CONFIG_SYS_SJA1000_BASE 0xFBFF0000 -/* SJA1000 */ -#define CONFIG_SYS_BR1_PRELIM (0xFBFF0000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_GPCM_SCY_5 | OR_GPCM_EHTR_SET) /* * CPLD on Local Bus */ #define CONFIG_SYS_CPLD_BASE 0xFBFF8000 -/* CPLD */ -#define CONFIG_SYS_BR2_PRELIM (0xFBFF8000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB | OR_GPCM_SCY_4 | OR_GPCM_EHTR_SET) /* * Serial Port diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index 42a1e1682d..98770ca0a6 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -98,9 +98,6 @@ #define CONFIG_SYS_FLASH_BASE 0xFF800000 /* start of FLASH */ #define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xFF800000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */ diff --git a/include/configs/strider.h b/include/configs/strider.h index 1519dad321..dd89ee8c81 100644 --- a/include/configs/strider.h +++ b/include/configs/strider.h @@ -167,9 +167,6 @@ #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB | OR_UPM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 135 @@ -183,9 +180,6 @@ #define CONFIG_SYS_FPGA0_BASE 0xE0600000 #define CONFIG_SYS_FPGA0_SIZE 1 /* FPGA size is 1M */ -/* FPGA */ -#define CONFIG_SYS_BR1_PRELIM (0xE0600000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_1MB | OR_UPM_XAM | OR_GPCM_CSNT | OR_GPCM_SCY_5 | OR_GPCM_TRLX_CLEAR | OR_GPCM_EHTR_CLEAR) #define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE #define CONFIG_SYS_FPGA_DONE(k) 0x0010 diff --git a/include/configs/suvd3.h b/include/configs/suvd3.h index 6aacbc2077..a65b61bfbf 100644 --- a/include/configs/suvd3.h +++ b/include/configs/suvd3.h @@ -110,9 +110,6 @@ */ #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xF0000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ @@ -122,9 +119,6 @@ * PRIO1/PIGGY on the local bus CS1 */ -/* KMBEC_FPGA */ -#define CONFIG_SYS_BR1_PRELIM (0xE8000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_128MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) /* * Serial Port @@ -342,13 +336,7 @@ * */ -/* APP1 */ -#define CONFIG_SYS_BR2_PRELIM (0xA0000000 | BR_PS_16 | BR_MS_UPMA | BR_V) -#define CONFIG_SYS_OR2_PRELIM (OR_AM_256MB) -/* APP2 */ -#define CONFIG_SYS_BR3_PRELIM (0xB0000000 | BR_PS_16 | BR_V) -#define CONFIG_SYS_OR3_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_3 | OR_GPCM_TRLX_SET) #define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \ 0x0000c000 | \ diff --git a/include/configs/tuge1.h b/include/configs/tuge1.h index b11d49629a..6084e8af60 100644 --- a/include/configs/tuge1.h +++ b/include/configs/tuge1.h @@ -113,9 +113,6 @@ */ #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xF0000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ @@ -125,9 +122,6 @@ * PRIO1/PIGGY on the local bus CS1 */ -/* KMBEC_FPGA */ -#define CONFIG_SYS_BR1_PRELIM (0xE8000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_128MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) /* * Serial Port @@ -345,8 +339,5 @@ * 3 Local GPCM 8 bit 256MB TEP2 (16 bit) */ -/* APP1 */ -#define CONFIG_SYS_BR2_PRELIM (0xA0000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR2_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_CLEAR | OR_GPCM_EAD) #endif /* __CONFIG_H */ diff --git a/include/configs/tuxx1.h b/include/configs/tuxx1.h index 1bff837198..86aec93ee9 100644 --- a/include/configs/tuxx1.h +++ b/include/configs/tuxx1.h @@ -113,9 +113,6 @@ */ #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xF0000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ @@ -125,9 +122,6 @@ * PRIO1/PIGGY on the local bus CS1 */ -/* KMBEC_FPGA */ -#define CONFIG_SYS_BR1_PRELIM (0xE8000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_128MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) /* * Serial Port @@ -347,13 +341,7 @@ * 3 Local GPCM 8 bit 256MB TEP2 (16 bit) */ -/* APP1 */ -#define CONFIG_SYS_BR2_PRELIM (0xA0000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR2_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_CLEAR | OR_GPCM_EAD) -/* APP2 */ -#define CONFIG_SYS_BR3_PRELIM (0xB0000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR3_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_CLEAR) #define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \ 0x0000c000 | \ diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h index 3a5bcf9c62..4c5dad9dc2 100644 --- a/include/configs/ve8313.h +++ b/include/configs/ve8313.h @@ -153,25 +153,13 @@ #define CONFIG_NAND_FSL_ELBC 1 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384 -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_32MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) -/* NAND */ -#define CONFIG_SYS_BR1_PRELIM (0x61000000 | BR_PS_8 | BR_DECC_CHK_GEN | BR_MS_FCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_FCM_BCTLD | OR_FCM_CHT | OR_FCM_SCY_2 | OR_FCM_RST | OR_FCM_TRLX) /* Still needed for spl_minimal.c */ #define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM #define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM -/* NVRAM */ -#define CONFIG_SYS_BR2_PRELIM (0x60000000 | BR_PS_8 | BR_V) -#define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_3 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) -/* SRAM */ -#define CONFIG_SYS_BR3_PRELIM (0x62000000 | BR_PS_16 | BR_V) -#define CONFIG_SYS_OR3_PRELIM (OR_AM_32MB | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) /* * Serial Port diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h index dd8aae5117..9b9c1ff54e 100644 --- a/include/configs/vme8349.h +++ b/include/configs/vme8349.h @@ -70,15 +70,9 @@ #define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH */ #define CONFIG_SYS_FLASH_SIZE 128 /* flash size in MB */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xF8000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) #define CONFIG_SYS_WINDOW1_BASE 0xf0000000 -/* WINDOW1 */ -#define CONFIG_SYS_BR1_PRELIM (0xF0000000 | BR_PS_32 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_256KB | OR_GPCM_SETA) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device*/ From a06e665b47c891d1faf6bfd03a3f7cd3a9fea694 Mon Sep 17 00:00:00 2001 From: Mario Six Date: Mon, 21 Jan 2019 09:18:04 +0100 Subject: [PATCH 41/86] powerpc: mpc83xx: Fix MPC8308 IMMR memory layout The MPC8308 has two I2C controllers, but no PCI controller. Fix the register map layout for this SoC. Signed-off-by: Mario Six --- arch/powerpc/cpu/mpc83xx/Makefile | 2 ++ arch/powerpc/include/asm/immap_83xx.h | 42 +++++++++++++++++++++++++-- 2 files changed, 41 insertions(+), 3 deletions(-) diff --git a/arch/powerpc/cpu/mpc83xx/Makefile b/arch/powerpc/cpu/mpc83xx/Makefile index aa4affa911..304029977e 100644 --- a/arch/powerpc/cpu/mpc83xx/Makefile +++ b/arch/powerpc/cpu/mpc83xx/Makefile @@ -29,7 +29,9 @@ obj-y += interrupts.o obj-y += ecc.o obj-$(CONFIG_QE) += qe_io.o obj-$(CONFIG_FSL_SERDES) += serdes.o +ifndef CONFIG_ARCH_MPC8308 obj-$(CONFIG_PCI) += pci.o +endif obj-$(CONFIG_PCIE) += pcie.o obj-$(CONFIG_OF_LIBFDT) += fdt.o diff --git a/arch/powerpc/include/asm/immap_83xx.h b/arch/powerpc/include/asm/immap_83xx.h index 30bbd5671b..d02da6495c 100644 --- a/arch/powerpc/include/asm/immap_83xx.h +++ b/arch/powerpc/include/asm/immap_83xx.h @@ -714,7 +714,7 @@ typedef struct immap { u8 res7[0xC0000]; } immap_t; -#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC8315) +#elif defined(CONFIG_ARCH_MPC8315) typedef struct immap { sysconf83xx_t sysconf; /* System configuration */ wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */ @@ -729,8 +729,8 @@ typedef struct immap { gpio83xx_t gpio[1]; /* General purpose I/O module */ u8 res0[0x1300]; ddr83xx_t ddr; /* DDR Memory Controller Memory */ - fsl_i2c_t i2c[2]; /* I2C Controllers */ - u8 res1[0x1300]; + fsl_i2c_t i2c[1]; /* I2C Controllers */ + u8 res1[0x1400]; duart83xx_t duart[2]; /* DUART */ u8 res2[0x900]; fsl_lbc_t im_lbc; /* Local Bus Controller Regs */ @@ -759,6 +759,42 @@ typedef struct immap { u8 res12[0x1CF00]; } immap_t; +#elif defined(CONFIG_ARCH_MPC8308) +typedef struct immap { + sysconf83xx_t sysconf; /* System configuration */ + wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */ + rtclk83xx_t rtc; /* Real Time Clock Module Registers */ + rtclk83xx_t pit; /* Periodic Interval Timer */ + gtm83xx_t gtm[1]; /* Global Timers Module */ + u8 res0[0x100]; + ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */ + arbiter83xx_t arbiter; /* System Arbiter Registers */ + reset83xx_t reset; /* Reset Module */ + clk83xx_t clk; /* System Clock Module */ + pmc83xx_t pmc; /* Power Management Control Module */ + gpio83xx_t gpio[1]; /* General purpose I/O module */ + u8 res1[0x1300]; + ddr83xx_t ddr; /* DDR Memory Controller Memory */ + fsl_i2c_t i2c[2]; /* I2C Controllers */ + u8 res2[0x1300]; + duart83xx_t duart[2]; /* DUART */ + u8 res3[0x900]; + fsl_lbc_t im_lbc; /* Local Bus Controller Regs */ + u8 res4[0x1000]; + spi8xxx_t spi; /* Serial Peripheral Interface */ + u8 res5[0x1000]; + pex83xx_t pciexp[1]; /* PCI Express Controller */ + u8 res6[0x19000]; + usb83xx_t usb[1]; /* USB DR Controller */ + tsec83xx_t tsec[2]; + u8 res7[0x6000]; + tdmdmac83xx_t tdmdmac; /* TDM DMAC */ + sdhc83xx_t sdhc; /* SDHC Controller */ + u8 res8[0xb4000]; + serdes83xx_t serdes[1]; /* SerDes Registers */ + u8 res9[0x1CF00]; +} immap_t; + #elif defined(CONFIG_ARCH_MPC837X) typedef struct immap { sysconf83xx_t sysconf; /* System configuration */ From ac016c94ae21ae6bb14632bf1092278f1f096c8e Mon Sep 17 00:00:00 2001 From: Mario Six Date: Mon, 21 Jan 2019 09:18:05 +0100 Subject: [PATCH 42/86] powerpc: mpc83xx: Implement get_serial_clock() DM serial drivers on PowerPC determine their clock frequency via the get_serial_clock function. This function is not Implemented yet for MPC83xx. This patch Implements the function so that DM serial drivers work on MPC83xx. Signed-off-by: Mario Six --- arch/powerpc/cpu/mpc83xx/speed.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/powerpc/cpu/mpc83xx/speed.c b/arch/powerpc/cpu/mpc83xx/speed.c index e870a23103..e118a10fa8 100644 --- a/arch/powerpc/cpu/mpc83xx/speed.c +++ b/arch/powerpc/cpu/mpc83xx/speed.c @@ -516,6 +516,11 @@ ulong get_ddr_freq(ulong dummy) return gd->mem_clk; } +int get_serial_clock(void) +{ + return get_bus_freq(0); +} + static int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { char buf[32]; From 190d3a0c63b7617080b40e4132022aa00a139b36 Mon Sep 17 00:00:00 2001 From: Mario Six Date: Mon, 21 Jan 2019 09:18:06 +0100 Subject: [PATCH 43/86] powerpc: mpc83xx: fdt: Use get_serial_clock() Replace the hard-coded CONFIG_SYS_NS16550_CLK value for the FDT fixup with the previously introduced get_serial_clock function This will make it possible to activate DM for serial devices on MPC83xx later on. Signed-off-by: Mario Six --- arch/powerpc/cpu/mpc83xx/fdt.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/cpu/mpc83xx/fdt.c b/arch/powerpc/cpu/mpc83xx/fdt.c index cfd391b78a..b487e31cc0 100644 --- a/arch/powerpc/cpu/mpc83xx/fdt.c +++ b/arch/powerpc/cpu/mpc83xx/fdt.c @@ -116,8 +116,8 @@ void ft_cpu_setup(void *blob, bd_t *bd) #endif #ifdef CONFIG_SYS_NS16550 - do_fixup_by_compat_u32(blob, "ns16550", - "clock-frequency", CONFIG_SYS_NS16550_CLK, 1); + do_fixup_by_compat_u32(blob, "ns16550", + "clock-frequency", get_serial_clock(), 1); #endif fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); From a84289190c60260da6df8c87c032961404217b6f Mon Sep 17 00:00:00 2001 From: Mario Six Date: Mon, 21 Jan 2019 09:18:07 +0100 Subject: [PATCH 44/86] mpc83xx: Remove last CONFIG_MPC83xx Remove the last instances of the CONFIG_MPC83xx symbol. Signed-off-by: Mario Six --- include/configs/hrcon.h | 1 - include/configs/strider.h | 1 - 2 files changed, 2 deletions(-) diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h index 9318e6252a..4001a0a16b 100644 --- a/include/configs/hrcon.h +++ b/include/configs/hrcon.h @@ -12,7 +12,6 @@ * High Level Configuration Options */ #define CONFIG_E300 1 /* E300 family */ -#define CONFIG_MPC83xx 1 /* MPC83xx family */ #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR diff --git a/include/configs/strider.h b/include/configs/strider.h index dd89ee8c81..94164de06c 100644 --- a/include/configs/strider.h +++ b/include/configs/strider.h @@ -12,7 +12,6 @@ * High Level Configuration Options */ #define CONFIG_E300 1 /* E300 family */ -#define CONFIG_MPC83xx 1 /* MPC83xx family */ #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR From d17e5fdfea01cc53ff6a82725ff02479fbbfa957 Mon Sep 17 00:00:00 2001 From: Mario Six Date: Mon, 21 Jan 2019 09:18:08 +0100 Subject: [PATCH 45/86] mpc83xx: Prepare usage of DM gpio driver The MPC85xx GPIO driver was converted to handle a broader range of SoCs. Prepare the MPC83xx code for usage of this driver. Signed-off-by: Mario Six --- arch/powerpc/include/asm/arch-mpc83xx/gpio.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/powerpc/include/asm/arch-mpc83xx/gpio.h b/arch/powerpc/include/asm/arch-mpc83xx/gpio.h index b5ec50ba44..385d651d20 100644 --- a/arch/powerpc/include/asm/arch-mpc83xx/gpio.h +++ b/arch/powerpc/include/asm/arch-mpc83xx/gpio.h @@ -17,7 +17,15 @@ #define MAX_NUM_GPIOS (32 * MPC83XX_GPIO_CTRLRS) +struct mpc8xxx_gpio_plat { + ulong addr; + unsigned long size; + uint ngpios; +}; + +#ifndef DM_GPIO void mpc83xx_gpio_init_f(void); void mpc83xx_gpio_init_r(void); +#endif /* DM_GPIO */ #endif /* MPC83XX_GPIO_H_ */ From be5abb0a834c346f9b22f983e9002ebab2c72cb3 Mon Sep 17 00:00:00 2001 From: Mario Six Date: Mon, 21 Jan 2019 09:18:09 +0100 Subject: [PATCH 46/86] mpc83xx: Migrate HID config to Kconfig Mirate the HID configuration settings to Kconfig. Signed-off-by: Mario Six --- arch/powerpc/cpu/mpc83xx/Kconfig | 1 + arch/powerpc/cpu/mpc83xx/hid/Kconfig | 565 ++++++++++++++++++++++++++ arch/powerpc/cpu/mpc83xx/hid/hid.h | 72 ++++ arch/powerpc/cpu/mpc83xx/start.S | 1 + configs/MPC8308RDB_defconfig | 4 + configs/MPC8313ERDB_33_defconfig | 4 + configs/MPC8313ERDB_66_defconfig | 4 + configs/MPC8313ERDB_NAND_33_defconfig | 4 + configs/MPC8313ERDB_NAND_66_defconfig | 4 + configs/MPC8315ERDB_defconfig | 4 + configs/MPC8323ERDB_defconfig | 3 + configs/MPC832XEMDS_ATM_defconfig | 3 + configs/MPC832XEMDS_HOST_33_defconfig | 3 + configs/MPC832XEMDS_HOST_66_defconfig | 3 + configs/MPC832XEMDS_SLAVE_defconfig | 3 + configs/MPC832XEMDS_defconfig | 3 + configs/MPC8349EMDS_PCI64_defconfig | 3 + configs/MPC8349EMDS_SDRAM_defconfig | 3 + configs/MPC8349EMDS_SLAVE_defconfig | 3 + configs/MPC8349EMDS_defconfig | 3 + configs/MPC8349ITXGP_defconfig | 2 + configs/MPC8349ITX_LOWBOOT_defconfig | 2 + configs/MPC8349ITX_defconfig | 2 + configs/MPC837XEMDS_HOST_defconfig | 3 + configs/MPC837XEMDS_SLAVE_defconfig | 3 + configs/MPC837XEMDS_defconfig | 3 + configs/MPC837XERDB_SLAVE_defconfig | 3 + configs/MPC837XERDB_defconfig | 3 + configs/TQM834x_defconfig | 2 + configs/caddy2_defconfig | 3 + configs/hrcon_defconfig | 4 + configs/hrcon_dh_defconfig | 4 + configs/ids8313_defconfig | 3 + configs/kmcoge5ne_defconfig | 3 + configs/kmeter1_defconfig | 3 + configs/kmopti2_defconfig | 3 + configs/kmsupx5_defconfig | 3 + configs/kmtegr1_defconfig | 3 + configs/kmtepr2_defconfig | 3 + configs/kmvect1_defconfig | 3 + configs/mpc8308_p1m_defconfig | 4 + configs/sbc8349_PCI_33_defconfig | 3 + configs/sbc8349_PCI_66_defconfig | 3 + configs/sbc8349_defconfig | 3 + configs/strider_con_defconfig | 4 + configs/strider_con_dp_defconfig | 4 + configs/strider_cpu_defconfig | 4 + configs/strider_cpu_dp_defconfig | 4 + configs/suvd3_defconfig | 3 + configs/tuge1_defconfig | 3 + configs/tuxx1_defconfig | 3 + configs/ve8313_defconfig | 3 + configs/vme8349_defconfig | 3 + include/configs/MPC8308RDB.h | 9 - include/configs/MPC8313ERDB_NAND.h | 7 - include/configs/MPC8313ERDB_NOR.h | 7 - include/configs/MPC8315ERDB.h | 9 - include/configs/MPC8323ERDB.h | 8 - include/configs/MPC832XEMDS.h | 8 - include/configs/MPC8349EMDS.h | 11 - include/configs/MPC8349EMDS_SDRAM.h | 11 - include/configs/MPC8349ITX.h | 5 - include/configs/MPC837XEMDS.h | 8 - include/configs/MPC837XERDB.h | 8 - include/configs/TQM834x.h | 6 - include/configs/caddy2.h | 6 - include/configs/hrcon.h | 9 - include/configs/ids8313.h | 7 - include/configs/kmcoge5ne.h | 8 - include/configs/kmeter1.h | 8 - include/configs/kmopti2.h | 8 - include/configs/kmsupx5.h | 8 - include/configs/kmtegr1.h | 8 - include/configs/kmtepr2.h | 8 - include/configs/kmvect1.h | 8 - include/configs/mpc8308_p1m.h | 9 - include/configs/sbc8349.h | 11 - include/configs/strider.h | 9 - include/configs/suvd3.h | 8 - include/configs/tuge1.h | 8 - include/configs/tuxx1.h | 8 - include/configs/ve8313.h | 6 - include/configs/vme8349.h | 6 - scripts/config_whitelist.txt | 3 - 84 files changed, 795 insertions(+), 243 deletions(-) create mode 100644 arch/powerpc/cpu/mpc83xx/hid/Kconfig create mode 100644 arch/powerpc/cpu/mpc83xx/hid/hid.h diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index 474572f245..5fb4228076 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -286,6 +286,7 @@ source "arch/powerpc/cpu/mpc83xx/hrcw/Kconfig" source "arch/powerpc/cpu/mpc83xx/bats/Kconfig" source "arch/powerpc/cpu/mpc83xx/lblaw/Kconfig" source "arch/powerpc/cpu/mpc83xx/elbc/Kconfig" +source "arch/powerpc/cpu/mpc83xx/hid/Kconfig" menu "Legacy options" diff --git a/arch/powerpc/cpu/mpc83xx/hid/Kconfig b/arch/powerpc/cpu/mpc83xx/hid/Kconfig new file mode 100644 index 0000000000..c367ad2ce1 --- /dev/null +++ b/arch/powerpc/cpu/mpc83xx/hid/Kconfig @@ -0,0 +1,565 @@ +menu "HID setup" + +menu "HID0 initial" + +config HID0_INIT_EMCP + bool "Enable machine check int on mcp" + +config HID0_INIT_ECPE + bool "Enable cache parity errors" + +config HID0_INIT_EBA + bool "Enable address parity checking" + +config HID0_INIT_EBD + bool "Enable data parity checking" + +choice + prompt "HID0 clock configuration" + +config HID0_INIT_CLKOUT_OFF + bool "Clock output off" + +config HID0_INIT_CLKOUT_CORE_HALF + bool "Core clock / 2" + +config HID0_INIT_CLKOUT_CORE + bool "Core clock" + +config HID0_INIT_CLKOUT_BUS + bool "Bus clock" + +endchoice + +config HID0_INIT_PAR + bool "Disable precharge of artry_out" + +config HID0_INIT_DOZE + bool "Enable doze mode" + +config HID0_INIT_NAP + bool "Enable nap mode" + +config HID0_INIT_SLEEP + bool "Enable sleep mode" + +config HID0_INIT_DPM + bool "Enable dynamic power management" + +config HID0_INIT_ICE + bool "Enable instruction cache" + +config HID0_INIT_DCE + bool "Enable data cache" + +config HID0_INIT_ILOCK + bool "Lock instruction cache" + +config HID0_INIT_DLOCK + bool "Lock data cache" + +config HID0_INIT_ICFI + bool "Flash invalidate instruction cache" + +config HID0_INIT_DCFI + bool "Flash invalidate data cache" + +config HID0_INIT_IFEM + bool "Enable m bit on bus for instruction fetches" + +config HID0_INIT_DECAREN + bool "Decrementer auto reload" + +config HID0_INIT_FBIOB + bool "Force indirect branch on the bus" + +config HID0_INIT_ABE + bool "Enable address broadcast" + +config HID0_INIT_NOOPTI + bool "No-op data cache touch intructions" + +endmenu + +menu "HID0 final" + +config HID0_FINAL_EMCP + bool "Enable machine check int on mcp" + +config HID0_FINAL_ECPE + bool "Enable cache parity errors" + +config HID0_FINAL_EBA + bool "Enable address parity checking" + +config HID0_FINAL_EBD + bool "Enable data parity checking" + +choice + prompt "HID0 clock configuration" + +config HID0_FINAL_CLKOUT_OFF + bool "Clock output off" + +config HID0_FINAL_CLKOUT_CORE_HALF + bool "Core clock / 2" + +config HID0_FINAL_CLKOUT_CORE + bool "Core clock" + +config HID0_FINAL_CLKOUT_BUS + bool "Bus clock" + +endchoice + +config HID0_FINAL_PAR + bool "Disable precharge of artry_out" + +config HID0_FINAL_DOZE + bool "Enable doze mode" + +config HID0_FINAL_NAP + bool "Enable nap mode" + +config HID0_FINAL_SLEEP + bool "Enable sleep mode" + +config HID0_FINAL_DPM + bool "Enable dynamic power management" + +config HID0_FINAL_ICE + bool "Enable instruction cache" + +config HID0_FINAL_DCE + bool "Enable data cache" + +config HID0_FINAL_ILOCK + bool "Lock instruction cache" + +config HID0_FINAL_DLOCK + bool "Lock data cache" + +config HID0_FINAL_ICFI + bool "Flash invalidate instruction cache" + +config HID0_FINAL_DCFI + bool "Flash invalidate data cache" + +config HID0_FINAL_IFEM + bool "Enable m bit on bus for instruction fetches" + +config HID0_FINAL_DECAREN + bool "Decrementer auto reload" + +config HID0_FINAL_FBIOB + bool "Force indirect branch on the bus" + +config HID0_FINAL_ABE + bool "Enable address broadcast" + +config HID0_FINAL_NOOPTI + bool "No-op data cache touch intructions" + +endmenu + +config HID0_INIT_EMCP_BIT + hex + default 0x0 if !HID0_INIT_EMCP + default 0x80000000 if HID0_INIT_EMCP + +config HID0_INIT_ECPE_BIT + hex + default 0x0 if !HID0_INIT_ECPE + default 0x40000000 if HID0_INIT_ECPE + +config HID0_INIT_EBA_BIT + hex + default 0x0 if !HID0_INIT_EBA + default 0x20000000 if HID0_INIT_EBA + +config HID0_INIT_EBD_BIT + hex + default 0x0 if !HID0_INIT_EBD + default 0x10000000 if HID0_INIT_EBD + +config HID0_INIT_CLKOUT + hex + default 0x0 if HID0_INIT_CLKOUT_OFF + default 0x8000000 if HID0_INIT_CLKOUT_CORE_HALF + default 0x2000000 if HID0_INIT_CLKOUT_CORE + default 0xa000000 if HID0_INIT_CLKOUT_BUS + +config HID0_INIT_PAR_BIT + hex + default 0x0 if !HID0_INIT_PAR + default 0x1000000 if HID0_INIT_PAR + +config HID0_INIT_DOZE_BIT + hex + default 0x0 if !HID0_INIT_DOZE + default 0x800000 if HID0_INIT_DOZE + +config HID0_INIT_NAP_BIT + hex + default 0x0 if !HID0_INIT_NAP + default 0x400000 if HID0_INIT_NAP + +config HID0_INIT_SLEEP_BIT + hex + default 0x0 if !HID0_INIT_SLEEP + default 0x200000 if HID0_INIT_SLEEP + +config HID0_INIT_DPM_BIT + hex + default 0x0 if !HID0_INIT_DPM + default 0x100000 if HID0_INIT_DPM + +config HID0_INIT_ICE_BIT + hex + default 0x0 if !HID0_INIT_ICE + default 0x8000 if HID0_INIT_ICE + +config HID0_INIT_DCE_BIT + hex + default 0x0 if !HID0_INIT_DCE + default 0x4000 if HID0_INIT_DCE + +config HID0_INIT_ILOCK_BIT + hex + default 0x0 if !HID0_INIT_ILOCK + default 0x2000 if HID0_INIT_ILOCK + +config HID0_INIT_DLOCK_BIT + hex + default 0x0 if !HID0_INIT_DLOCK + default 0x1000 if HID0_INIT_DLOCK + +config HID0_INIT_ICFI_BIT + hex + default 0x0 if !HID0_INIT_ICFI + default 0x800 if HID0_INIT_ICFI + +config HID0_INIT_DCFI_BIT + hex + default 0x0 if !HID0_INIT_DCFI + default 0x400 if HID0_INIT_DCFI + +config HID0_INIT_IFEM_BIT + hex + default 0x0 if !HID0_INIT_IFEM + default 0x80 if HID0_INIT_IFEM + +config HID0_INIT_DECAREN_BIT + hex + default 0x0 if !HID0_INIT_DECAREN + default 0x40 if HID0_INIT_DECAREN + +config HID0_INIT_FBIOB_BIT + hex + default 0x0 if !HID0_INIT_FBIOB + default 0x10 if HID0_INIT_FBIOB + +config HID0_INIT_ABE_BIT + hex + default 0x0 if !HID0_INIT_ABE + default 0x8 if HID0_INIT_ABE + +config HID0_INIT_NOOPTI_BIT + hex + default 0x0 if !HID0_INIT_NOOPTI + default 0x1 if HID0_INIT_NOOPTI + +config HID0_FINAL_EMCP_BIT + hex + default 0x0 if !HID0_FINAL_EMCP + default 0x80000000 if HID0_FINAL_EMCP + +config HID0_FINAL_ECPE_BIT + hex + default 0x0 if !HID0_FINAL_ECPE + default 0x40000000 if HID0_FINAL_ECPE + +config HID0_FINAL_EBA_BIT + hex + default 0x0 if !HID0_FINAL_EBA + default 0x20000000 if HID0_FINAL_EBA + +config HID0_FINAL_EBD_BIT + hex + default 0x0 if !HID0_FINAL_EBD + default 0x10000000 if HID0_FINAL_EBD + +config HID0_FINAL_CLKOUT + hex + default 0x0 if HID0_FINAL_CLKOUT_OFF + default 0x8000000 if HID0_FINAL_CLKOUT_CORE_HALF + default 0x2000000 if HID0_FINAL_CLKOUT_CORE + default 0xa000000 if HID0_FINAL_CLKOUT_BUS + +config HID0_FINAL_SBCLK_BIT + hex + default 0x0 if !HID0_FINAL_SBCLK + default 0x8000000 if HID0_FINAL_SBCLK + +config HID0_FINAL_ECLK_BIT + hex + default 0x0 if !HID0_FINAL_ECLK + default 0x2000000 if HID0_FINAL_ECLK + +config HID0_FINAL_PAR_BIT + hex + default 0x0 if !HID0_FINAL_PAR + default 0x1000000 if HID0_FINAL_PAR + +config HID0_FINAL_DOZE_BIT + hex + default 0x0 if !HID0_FINAL_DOZE + default 0x800000 if HID0_FINAL_DOZE + +config HID0_FINAL_NAP_BIT + hex + default 0x0 if !HID0_FINAL_NAP + default 0x400000 if HID0_FINAL_NAP + +config HID0_FINAL_SLEEP_BIT + hex + default 0x0 if !HID0_FINAL_SLEEP + default 0x200000 if HID0_FINAL_SLEEP + +config HID0_FINAL_DPM_BIT + hex + default 0x0 if !HID0_FINAL_DPM + default 0x100000 if HID0_FINAL_DPM + +config HID0_FINAL_ICE_BIT + hex + default 0x0 if !HID0_FINAL_ICE + default 0x8000 if HID0_FINAL_ICE + +config HID0_FINAL_DCE_BIT + hex + default 0x0 if !HID0_FINAL_DCE + default 0x4000 if HID0_FINAL_DCE + +config HID0_FINAL_ILOCK_BIT + hex + default 0x0 if !HID0_FINAL_ILOCK + default 0x2000 if HID0_FINAL_ILOCK + +config HID0_FINAL_DLOCK_BIT + hex + default 0x0 if !HID0_FINAL_DLOCK + default 0x1000 if HID0_FINAL_DLOCK + +config HID0_FINAL_ICFI_BIT + hex + default 0x0 if !HID0_FINAL_ICFI + default 0x800 if HID0_FINAL_ICFI + +config HID0_FINAL_DCFI_BIT + hex + default 0x0 if !HID0_FINAL_DCFI + default 0x400 if HID0_FINAL_DCFI + +config HID0_FINAL_IFEM_BIT + hex + default 0x0 if !HID0_FINAL_IFEM + default 0x80 if HID0_FINAL_IFEM + +config HID0_FINAL_DECAREN_BIT + hex + default 0x0 if !HID0_FINAL_DECAREN + default 0x40 if HID0_FINAL_DECAREN + +config HID0_FINAL_FBIOB_BIT + hex + default 0x0 if !HID0_FINAL_FBIOB + default 0x10 if HID0_FINAL_FBIOB + +config HID0_FINAL_ABE_BIT + hex + default 0x0 if !HID0_FINAL_ABE + default 0x8 if HID0_FINAL_ABE + +config HID0_FINAL_NOOPTI_BIT + hex + default 0x0 if !HID0_FINAL_NOOPTI + default 0x1 if HID0_FINAL_NOOPTI + +menu "HID2" + +config HID2_LET + bool "True little-endian mode" + +config HID2_IFEB + bool "Instruction fetch burst extension" + +config HID2_MESISTATE + bool "MESI state enable" + +config HID2_IFEC + bool "Instruction fetch cancel extension" + +config HID2_EBQS + bool "BIU queue sharing" + +config HID2_EBPX + bool "BIU pipeline extension" + +if !ARCH_MPC8360 + +config HID2_ELRW + bool "Weighted LRU" + +config HID2_NOKS + bool "No kill for snoop" + +endif + +config HID2_HBE + bool "High bat enable" + +choice + prompt "Instruction cache way-lock" + +config HID2_IWLCK_NONE + bool "No ways locked" + +config HID2_IWLCK_0 + bool "Way 0 locked" + +config HID2_IWLCK_1 + bool "Way 0 through 1 locked" + +config HID2_IWLCK_2 + bool "Way 0 through 2 locked" + +if ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379 + +config HID2_IWLCK_3 + bool "Way 0 through 3 locked" + +config HID2_IWLCK_4 + bool "Way 0 through 4 locked" + +config HID2_IWLCK_5 + bool "Way 0 through 5 locked" + +config HID2_IWLCK_6 + bool "Way 0 through 6 locked" + +endif + +endchoice + +config HID2_ICWP + bool "Instruction cache way protection" + +choice + prompt "Data cache way-lock" + +config HID2_DWLCK_NONE + bool "No ways locked" + +config HID2_DWLCK_0 + bool "Way 0 locked" + +config HID2_DWLCK_1 + bool "Way 0 through 1 locked" + +config HID2_DWLCK_2 + bool "Way 0 through 2 locked" + +if ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379 + +config HID2_DWLCK_3 + bool "Way 0 through 3 locked" + +config HID2_DWLCK_4 + bool "Way 0 through 4 locked" + +config HID2_DWLCK_5 + bool "Way 0 through 5 locked" + +config HID2_DWLCK_6 + bool "Way 0 through 6 locked" + +endif + +endchoice + +config HID2_LET_BIT + hex + default 0x0 if !HID2_LET + default 0x8000000 if HID2_LET + +config HID2_IFEB_BIT + hex + default 0x0 if !HID2_IFEB + default 0x4000000 if HID2_IFEB + +config HID2_MESISTATE_BIT + hex + default 0x0 if !HID2_MESISTATE + default 0x1000000 if HID2_MESISTATE + +config HID2_IFEC_BIT + hex + default 0x0 if !HID2_IFEC + default 0x800000 if HID2_IFEC + +config HID2_EBQS_BIT + hex + default 0x0 if !HID2_EBQS + default 0x400000 if HID2_EBQS + +config HID2_EBPX_BIT + hex + default 0x0 if !HID2_EBPX + default 0x200000 if HID2_EBPX + +config HID2_ELRW_BIT + hex + default 0x0 if !HID2_ELRW + default 0x100000 if HID2_ELRW + +config HID2_NOKS_BIT + hex + default 0x0 if !HID2_NOKS + default 0x80000 if HID2_NOKS + +config HID2_HBE_BIT + hex + default 0x0 if !HID2_HBE + default 0x40000 if HID2_HBE + +config HID2_IWLCK + hex + default 0x0 if HID2_IWLCK_NONE + default 0x2000 if HID2_IWLCK_0 + default 0x4000 if HID2_IWLCK_1 + default 0x6000 if HID2_IWLCK_2 + default 0x8000 if HID2_IWLCK_3 + default 0xA000 if HID2_IWLCK_4 + default 0xC000 if HID2_IWLCK_5 + default 0xE000 if HID2_IWLCK_6 + +config HID2_ICWP_BIT + hex + default 0x0 if !HID2_ICWP + default 0x1000 if HID2_ICWP + +config HID2_DWLCK + hex + default 0x0 if HID2_DWLCK_NONE + default 0x20 if HID2_DWLCK_0 + default 0x40 if HID2_DWLCK_1 + default 0x60 if HID2_DWLCK_2 + default 0x80 if HID2_DWLCK_3 + default 0xA0 if HID2_DWLCK_4 + default 0xC0 if HID2_DWLCK_5 + default 0xE0 if HID2_DWLCK_6 + +endmenu + +endmenu diff --git a/arch/powerpc/cpu/mpc83xx/hid/hid.h b/arch/powerpc/cpu/mpc83xx/hid/hid.h new file mode 100644 index 0000000000..9f5260c012 --- /dev/null +++ b/arch/powerpc/cpu/mpc83xx/hid/hid.h @@ -0,0 +1,72 @@ +#define CONFIG_SYS_HID0_FINAL ( \ + CONFIG_HID0_FINAL_ABE_BIT |\ + CONFIG_HID0_FINAL_CLKOUT |\ + CONFIG_HID0_FINAL_DCE_BIT |\ + CONFIG_HID0_FINAL_DCFI_BIT |\ + CONFIG_HID0_FINAL_DECAREN_BIT |\ + CONFIG_HID0_FINAL_DLOCK_BIT |\ + CONFIG_HID0_FINAL_DOZE_BIT |\ + CONFIG_HID0_FINAL_DPM_BIT |\ + CONFIG_HID0_FINAL_EBA_BIT |\ + CONFIG_HID0_FINAL_EBD_BIT |\ + CONFIG_HID0_FINAL_ECLK_BIT |\ + CONFIG_HID0_FINAL_ECPE_BIT |\ + CONFIG_HID0_FINAL_EMCP_BIT |\ + CONFIG_HID0_FINAL_FBIOB_BIT |\ + CONFIG_HID0_FINAL_ICE_BIT |\ + CONFIG_HID0_FINAL_ICFI_BIT |\ + CONFIG_HID0_FINAL_IFEM_BIT |\ + CONFIG_HID0_FINAL_ILOCK_BIT |\ + CONFIG_HID0_FINAL_NAP_BIT |\ + CONFIG_HID0_FINAL_NOOPTI_BIT |\ + CONFIG_HID0_FINAL_PAR_BIT |\ + CONFIG_HID0_FINAL_SBCLK_BIT |\ + CONFIG_HID0_FINAL_SLEEP_BIT \ +) + +#define CONFIG_SYS_HID0_INIT ( \ + CONFIG_HID0_INIT_ABE_BIT |\ + CONFIG_HID0_INIT_CLKOUT |\ + CONFIG_HID0_INIT_DCE_BIT |\ + CONFIG_HID0_INIT_DCFI_BIT |\ + CONFIG_HID0_INIT_DECAREN_BIT |\ + CONFIG_HID0_INIT_DLOCK_BIT |\ + CONFIG_HID0_INIT_DOZE_BIT |\ + CONFIG_HID0_INIT_DPM_BIT |\ + CONFIG_HID0_INIT_EBA_BIT |\ + CONFIG_HID0_INIT_EBD_BIT |\ + CONFIG_HID0_INIT_ECPE_BIT |\ + CONFIG_HID0_INIT_EMCP_BIT |\ + CONFIG_HID0_INIT_FBIOB_BIT |\ + CONFIG_HID0_INIT_ICE_BIT |\ + CONFIG_HID0_INIT_ICFI_BIT |\ + CONFIG_HID0_INIT_IFEM_BIT |\ + CONFIG_HID0_INIT_ILOCK_BIT |\ + CONFIG_HID0_INIT_NAP_BIT |\ + CONFIG_HID0_INIT_NOOPTI_BIT |\ + CONFIG_HID0_INIT_PAR_BIT |\ + CONFIG_HID0_INIT_SLEEP_BIT \ +) + +#ifdef CONFIG_TARGET_IDS8313 +/* IDS8313 defines a reserved bit; keep to not break compatibility */ +#define CONFIG_HID2_SPECIAL 0x00020000 +#else +#define CONFIG_HID2_SPECIAL 0x0 +#endif + +#define CONFIG_SYS_HID2 ( \ + CONFIG_HID2_LET_BIT |\ + CONFIG_HID2_IFEB_BIT |\ + CONFIG_HID2_MESISTATE_BIT |\ + CONFIG_HID2_IFEC_BIT |\ + CONFIG_HID2_EBQS_BIT |\ + CONFIG_HID2_EBPX_BIT |\ + CONFIG_HID2_ELRW_BIT |\ + CONFIG_HID2_NOKS_BIT |\ + CONFIG_HID2_HBE_BIT |\ + CONFIG_HID2_IWLCK |\ + CONFIG_HID2_ICWP_BIT |\ + CONFIG_HID2_DWLCK |\ + CONFIG_HID2_SPECIAL \ +) diff --git a/arch/powerpc/cpu/mpc83xx/start.S b/arch/powerpc/cpu/mpc83xx/start.S index f7fc922af0..9fbbf59ce2 100644 --- a/arch/powerpc/cpu/mpc83xx/start.S +++ b/arch/powerpc/cpu/mpc83xx/start.S @@ -26,6 +26,7 @@ #include "hrcw/hrcw.h" #include "bats/bats.h" +#include "hid/hid.h" /* We don't want the MMU yet. */ diff --git a/configs/MPC8308RDB_defconfig b/configs/MPC8308RDB_defconfig index c38ac328d2..e674848a6c 100644 --- a/configs/MPC8308RDB_defconfig +++ b/configs/MPC8308RDB_defconfig @@ -58,6 +58,10 @@ CONFIG_LBLAW2=y CONFIG_LBLAW2_BASE=0xF0000000 CONFIG_LBLAW2_NAME="VSC7385" CONFIG_LBLAW2_LENGTH_128_KBYTES=y +CONFIG_HID0_FINAL_EMCP=y +CONFIG_HID0_FINAL_DPM=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/MPC8313ERDB_33_defconfig b/configs/MPC8313ERDB_33_defconfig index 1588adf3d6..732beab2e1 100644 --- a/configs/MPC8313ERDB_33_defconfig +++ b/configs/MPC8313ERDB_33_defconfig @@ -73,6 +73,10 @@ CONFIG_LBLAW3=y CONFIG_LBLAW3_BASE=0xFA000000 CONFIG_LBLAW3_NAME="BCSR" CONFIG_LBLAW3_LENGTH_32_KBYTES=y +CONFIG_HID0_FINAL_EMCP=y +CONFIG_HID0_FINAL_DPM=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SYS_33MHZ" diff --git a/configs/MPC8313ERDB_66_defconfig b/configs/MPC8313ERDB_66_defconfig index 2425256ee3..f2ec6cc7db 100644 --- a/configs/MPC8313ERDB_66_defconfig +++ b/configs/MPC8313ERDB_66_defconfig @@ -72,6 +72,10 @@ CONFIG_LBLAW3=y CONFIG_LBLAW3_BASE=0xFA000000 CONFIG_LBLAW3_NAME="BCSR" CONFIG_LBLAW3_LENGTH_32_KBYTES=y +CONFIG_HID0_FINAL_EMCP=y +CONFIG_HID0_FINAL_DPM=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SYS_66MHZ" diff --git a/configs/MPC8313ERDB_NAND_33_defconfig b/configs/MPC8313ERDB_NAND_33_defconfig index 8ee257a54e..95d8ff438e 100644 --- a/configs/MPC8313ERDB_NAND_33_defconfig +++ b/configs/MPC8313ERDB_NAND_33_defconfig @@ -75,6 +75,10 @@ CONFIG_LBLAW3=y CONFIG_LBLAW3_BASE=0xFA000000 CONFIG_LBLAW3_NAME="BCSR" CONFIG_LBLAW3_LENGTH_32_KBYTES=y +CONFIG_HID0_FINAL_EMCP=y +CONFIG_HID0_FINAL_DPM=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SYS_33MHZ" diff --git a/configs/MPC8313ERDB_NAND_66_defconfig b/configs/MPC8313ERDB_NAND_66_defconfig index baca3d799d..c51713ab90 100644 --- a/configs/MPC8313ERDB_NAND_66_defconfig +++ b/configs/MPC8313ERDB_NAND_66_defconfig @@ -74,6 +74,10 @@ CONFIG_LBLAW3=y CONFIG_LBLAW3_BASE=0xFA000000 CONFIG_LBLAW3_NAME="BCSR" CONFIG_LBLAW3_LENGTH_32_KBYTES=y +CONFIG_HID0_FINAL_EMCP=y +CONFIG_HID0_FINAL_DPM=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SYS_66MHZ" diff --git a/configs/MPC8315ERDB_defconfig b/configs/MPC8315ERDB_defconfig index b9539893ff..d19e797731 100644 --- a/configs/MPC8315ERDB_defconfig +++ b/configs/MPC8315ERDB_defconfig @@ -76,6 +76,10 @@ CONFIG_LBLAW1=y CONFIG_LBLAW1_BASE=0xE0600000 CONFIG_LBLAW1_NAME="NAND" CONFIG_LBLAW1_LENGTH_32_KBYTES=y +CONFIG_HID0_FINAL_EMCP=y +CONFIG_HID0_FINAL_DPM=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC8323ERDB_defconfig b/configs/MPC8323ERDB_defconfig index 64e6f58f38..19425abb1d 100644 --- a/configs/MPC8323ERDB_defconfig +++ b/configs/MPC8323ERDB_defconfig @@ -70,6 +70,9 @@ CONFIG_LBLAW0=y CONFIG_LBLAW0_BASE=0xFE000000 CONFIG_LBLAW0_NAME="FLASH" CONFIG_LBLAW0_LENGTH_32_MBYTES=y +CONFIG_HID0_FINAL_EMCP=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC832XEMDS_ATM_defconfig b/configs/MPC832XEMDS_ATM_defconfig index ffc82260ec..807d3e391a 100644 --- a/configs/MPC832XEMDS_ATM_defconfig +++ b/configs/MPC832XEMDS_ATM_defconfig @@ -68,6 +68,9 @@ CONFIG_LBLAW3=y CONFIG_LBLAW3_BASE=0xF8008000 CONFIG_LBLAW3_NAME="PIB" CONFIG_LBLAW3_LENGTH_64_KBYTES=y +CONFIG_HID0_FINAL_EMCP=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PQ_MDS_PIB=1,PQ_MDS_PIB_ATM=1" diff --git a/configs/MPC832XEMDS_HOST_33_defconfig b/configs/MPC832XEMDS_HOST_33_defconfig index 911f62de65..e328deb9fe 100644 --- a/configs/MPC832XEMDS_HOST_33_defconfig +++ b/configs/MPC832XEMDS_HOST_33_defconfig @@ -88,6 +88,9 @@ CONFIG_LBLAW3=y CONFIG_LBLAW3_BASE=0xF8008000 CONFIG_LBLAW3_NAME="PIB" CONFIG_LBLAW3_LENGTH_64_KBYTES=y +CONFIG_HID0_FINAL_EMCP=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PCI_33M,PQ_MDS_PIB=1" diff --git a/configs/MPC832XEMDS_HOST_66_defconfig b/configs/MPC832XEMDS_HOST_66_defconfig index 7dd02a95c9..d5bf354eec 100644 --- a/configs/MPC832XEMDS_HOST_66_defconfig +++ b/configs/MPC832XEMDS_HOST_66_defconfig @@ -88,6 +88,9 @@ CONFIG_LBLAW3=y CONFIG_LBLAW3_BASE=0xF8008000 CONFIG_LBLAW3_NAME="PIB" CONFIG_LBLAW3_LENGTH_64_KBYTES=y +CONFIG_HID0_FINAL_EMCP=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PCI_66M,PQ_MDS_PIB=1" diff --git a/configs/MPC832XEMDS_SLAVE_defconfig b/configs/MPC832XEMDS_SLAVE_defconfig index 3e3c82b2ef..9d9d905118 100644 --- a/configs/MPC832XEMDS_SLAVE_defconfig +++ b/configs/MPC832XEMDS_SLAVE_defconfig @@ -85,6 +85,9 @@ CONFIG_LBLAW3=y CONFIG_LBLAW3_BASE=0xF8008000 CONFIG_LBLAW3_NAME="PIB" CONFIG_LBLAW3_LENGTH_64_KBYTES=y +CONFIG_HID0_FINAL_EMCP=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PCISLAVE" diff --git a/configs/MPC832XEMDS_defconfig b/configs/MPC832XEMDS_defconfig index 4cfa01074d..518f7114d7 100644 --- a/configs/MPC832XEMDS_defconfig +++ b/configs/MPC832XEMDS_defconfig @@ -68,6 +68,9 @@ CONFIG_LBLAW3=y CONFIG_LBLAW3_BASE=0xF8008000 CONFIG_LBLAW3_NAME="PIB" CONFIG_LBLAW3_LENGTH_64_KBYTES=y +CONFIG_HID0_FINAL_EMCP=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC8349EMDS_PCI64_defconfig b/configs/MPC8349EMDS_PCI64_defconfig index a29d3268f7..fef4f34357 100644 --- a/configs/MPC8349EMDS_PCI64_defconfig +++ b/configs/MPC8349EMDS_PCI64_defconfig @@ -53,6 +53,9 @@ CONFIG_LBLAW1=y CONFIG_LBLAW1_BASE=0xE2400000 CONFIG_LBLAW1_NAME="BCSR" CONFIG_LBLAW1_LENGTH_32_KBYTES=y +CONFIG_HID0_FINAL_EMCP=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC8349EMDS_SDRAM_defconfig b/configs/MPC8349EMDS_SDRAM_defconfig index e3058f0b5e..d0774431a3 100644 --- a/configs/MPC8349EMDS_SDRAM_defconfig +++ b/configs/MPC8349EMDS_SDRAM_defconfig @@ -57,6 +57,9 @@ CONFIG_LBLAW2=y CONFIG_LBLAW2_BASE=0xF0000000 CONFIG_LBLAW2_NAME="SDRAM" CONFIG_LBLAW2_LENGTH_64_MBYTES=y +CONFIG_HID0_FINAL_EMCP=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y CONFIG_ELBC_BR0_OR0=y CONFIG_BR0_OR0_NAME="FLASH" CONFIG_BR0_OR0_BASE=0xFE000000 diff --git a/configs/MPC8349EMDS_SLAVE_defconfig b/configs/MPC8349EMDS_SLAVE_defconfig index d45b6489b4..429d273e4e 100644 --- a/configs/MPC8349EMDS_SLAVE_defconfig +++ b/configs/MPC8349EMDS_SLAVE_defconfig @@ -51,6 +51,9 @@ CONFIG_LBLAW1=y CONFIG_LBLAW1_BASE=0xE2400000 CONFIG_LBLAW1_NAME="BCSR" CONFIG_LBLAW1_LENGTH_32_KBYTES=y +CONFIG_HID0_FINAL_EMCP=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y CONFIG_PCI_ONE_PCI1=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/configs/MPC8349EMDS_defconfig b/configs/MPC8349EMDS_defconfig index e3ca6811cc..8c09cd90ee 100644 --- a/configs/MPC8349EMDS_defconfig +++ b/configs/MPC8349EMDS_defconfig @@ -53,6 +53,9 @@ CONFIG_LBLAW1=y CONFIG_LBLAW1_BASE=0xE2400000 CONFIG_LBLAW1_NAME="BCSR" CONFIG_LBLAW1_LENGTH_32_KBYTES=y +CONFIG_HID0_FINAL_EMCP=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y CONFIG_PCI_ONE_PCI1=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/configs/MPC8349ITXGP_defconfig b/configs/MPC8349ITXGP_defconfig index cf4ce83307..c32c8f0d74 100644 --- a/configs/MPC8349ITXGP_defconfig +++ b/configs/MPC8349ITXGP_defconfig @@ -97,6 +97,8 @@ CONFIG_LBLAW3=y CONFIG_LBLAW3_BASE=0xF0000000 CONFIG_LBLAW3_NAME="CF" CONFIG_LBLAW3_LENGTH_64_KBYTES=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFE000000" diff --git a/configs/MPC8349ITX_LOWBOOT_defconfig b/configs/MPC8349ITX_LOWBOOT_defconfig index e0185191bc..4d55fd0088 100644 --- a/configs/MPC8349ITX_LOWBOOT_defconfig +++ b/configs/MPC8349ITX_LOWBOOT_defconfig @@ -97,6 +97,8 @@ CONFIG_LBLAW3=y CONFIG_LBLAW3_BASE=0xF0000000 CONFIG_LBLAW3_NAME="CF" CONFIG_LBLAW3_LENGTH_64_KBYTES=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC8349ITX_defconfig b/configs/MPC8349ITX_defconfig index 0187f4f128..697567f53e 100644 --- a/configs/MPC8349ITX_defconfig +++ b/configs/MPC8349ITX_defconfig @@ -96,6 +96,8 @@ CONFIG_LBLAW3=y CONFIG_LBLAW3_BASE=0xF0000000 CONFIG_LBLAW3_NAME="CF" CONFIG_LBLAW3_LENGTH_64_KBYTES=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC837XEMDS_HOST_defconfig b/configs/MPC837XEMDS_HOST_defconfig index b048d5b5d0..45b2ee74f4 100644 --- a/configs/MPC837XEMDS_HOST_defconfig +++ b/configs/MPC837XEMDS_HOST_defconfig @@ -101,6 +101,9 @@ CONFIG_LBLAW3=y CONFIG_LBLAW3_BASE=0xE0600000 CONFIG_LBLAW3_NAME="NAND" CONFIG_LBLAW3_LENGTH_32_KBYTES=y +CONFIG_HID0_FINAL_EMCP=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC837XEMDS_SLAVE_defconfig b/configs/MPC837XEMDS_SLAVE_defconfig index 9e2966b371..5d5811b85a 100644 --- a/configs/MPC837XEMDS_SLAVE_defconfig +++ b/configs/MPC837XEMDS_SLAVE_defconfig @@ -61,6 +61,9 @@ CONFIG_LBLAW3=y CONFIG_LBLAW3_BASE=0xE0600000 CONFIG_LBLAW3_NAME="NAND" CONFIG_LBLAW3_LENGTH_32_KBYTES=y +CONFIG_HID0_FINAL_EMCP=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PCISLAVE" diff --git a/configs/MPC837XEMDS_defconfig b/configs/MPC837XEMDS_defconfig index 9256aac17c..70f9df7e76 100644 --- a/configs/MPC837XEMDS_defconfig +++ b/configs/MPC837XEMDS_defconfig @@ -81,6 +81,9 @@ CONFIG_LBLAW3=y CONFIG_LBLAW3_BASE=0xE0600000 CONFIG_LBLAW3_NAME="NAND" CONFIG_LBLAW3_LENGTH_32_KBYTES=y +CONFIG_HID0_FINAL_EMCP=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC837XERDB_SLAVE_defconfig b/configs/MPC837XERDB_SLAVE_defconfig index 95400114f2..1b8f33ab01 100644 --- a/configs/MPC837XERDB_SLAVE_defconfig +++ b/configs/MPC837XERDB_SLAVE_defconfig @@ -61,6 +61,9 @@ CONFIG_LBLAW2=y CONFIG_LBLAW2_BASE=0xF0000000 CONFIG_LBLAW2_NAME="VSC7385" CONFIG_LBLAW2_LENGTH_128_KBYTES=y +CONFIG_HID0_FINAL_EMCP=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PCISLAVE,PCIE" diff --git a/configs/MPC837XERDB_defconfig b/configs/MPC837XERDB_defconfig index a8c69eb6bc..40eaf93ac5 100644 --- a/configs/MPC837XERDB_defconfig +++ b/configs/MPC837XERDB_defconfig @@ -101,6 +101,9 @@ CONFIG_LBLAW2=y CONFIG_LBLAW2_BASE=0xF0000000 CONFIG_LBLAW2_NAME="VSC7385" CONFIG_LBLAW2_LENGTH_128_KBYTES=y +CONFIG_HID0_FINAL_EMCP=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PCIE" diff --git a/configs/TQM834x_defconfig b/configs/TQM834x_defconfig index 49f0916663..e85bfaea31 100644 --- a/configs/TQM834x_defconfig +++ b/configs/TQM834x_defconfig @@ -102,6 +102,8 @@ CONFIG_LBLAW2=y # CONFIG_LBLAW2_ENABLE is not set CONFIG_LBLAW3=y # CONFIG_LBLAW3_ENABLE is not set +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/caddy2_defconfig b/configs/caddy2_defconfig index e2ea71d11a..192c3442ce 100644 --- a/configs/caddy2_defconfig +++ b/configs/caddy2_defconfig @@ -71,6 +71,9 @@ CONFIG_LBLAW1=y CONFIG_LBLAW1_BASE=0xF0000000 CONFIG_LBLAW1_NAME="WINDOW1" CONFIG_LBLAW1_LENGTH_256_KBYTES=y +CONFIG_HID0_FINAL_EMCP=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/hrcon_defconfig b/configs/hrcon_defconfig index 7b17f602b6..2046b6067d 100644 --- a/configs/hrcon_defconfig +++ b/configs/hrcon_defconfig @@ -54,6 +54,10 @@ CONFIG_LBLAW1=y CONFIG_LBLAW1_BASE=0xE0600000 CONFIG_LBLAW1_NAME="FPGA0" CONFIG_LBLAW1_LENGTH_1_MBYTES=y +CONFIG_HID0_FINAL_EMCP=y +CONFIG_HID0_FINAL_DPM=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y CONFIG_CMD_IOLOOP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/hrcon_dh_defconfig b/configs/hrcon_dh_defconfig index 9a20a0d069..e9d427be36 100644 --- a/configs/hrcon_dh_defconfig +++ b/configs/hrcon_dh_defconfig @@ -54,6 +54,10 @@ CONFIG_LBLAW1=y CONFIG_LBLAW1_BASE=0xE0600000 CONFIG_LBLAW1_NAME="FPGA0" CONFIG_LBLAW1_LENGTH_1_MBYTES=y +CONFIG_HID0_FINAL_EMCP=y +CONFIG_HID0_FINAL_DPM=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y CONFIG_CMD_IOLOOP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/ids8313_defconfig b/configs/ids8313_defconfig index 14104a441b..24590d1448 100644 --- a/configs/ids8313_defconfig +++ b/configs/ids8313_defconfig @@ -70,6 +70,9 @@ CONFIG_LBLAW3=y CONFIG_LBLAW3_BASE=0xE3000000 CONFIG_LBLAW3_NAME="CPLD" CONFIG_LBLAW3_LENGTH_32_KBYTES=y +CONFIG_HID0_FINAL_EMCP=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_IMAGE_FORMAT_LEGACY=y diff --git a/configs/kmcoge5ne_defconfig b/configs/kmcoge5ne_defconfig index 6740c4c8a9..30af114c8c 100644 --- a/configs/kmcoge5ne_defconfig +++ b/configs/kmcoge5ne_defconfig @@ -104,6 +104,9 @@ CONFIG_LBLAW3=y CONFIG_LBLAW3_BASE=0xA0000000 CONFIG_LBLAW3_NAME="PAXE" CONFIG_LBLAW3_LENGTH_512_MBYTES=y +CONFIG_HID0_FINAL_EMCP=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_MISC_INIT_R=y diff --git a/configs/kmeter1_defconfig b/configs/kmeter1_defconfig index 182fa477f8..e673d6c4db 100644 --- a/configs/kmeter1_defconfig +++ b/configs/kmeter1_defconfig @@ -77,6 +77,9 @@ CONFIG_LBLAW3=y CONFIG_LBLAW3_BASE=0xA0000000 CONFIG_LBLAW3_NAME="PAXE" CONFIG_LBLAW3_LENGTH_512_MBYTES=y +CONFIG_HID0_FINAL_EMCP=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_MISC_INIT_R=y diff --git a/configs/kmopti2_defconfig b/configs/kmopti2_defconfig index 678900d05c..fb4bd41748 100644 --- a/configs/kmopti2_defconfig +++ b/configs/kmopti2_defconfig @@ -92,6 +92,9 @@ CONFIG_LBLAW3=y CONFIG_LBLAW3_BASE=0xB0000000 CONFIG_LBLAW3_NAME="APP2" CONFIG_LBLAW3_LENGTH_256_MBYTES=y +CONFIG_HID0_FINAL_EMCP=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_MISC_INIT_R=y diff --git a/configs/kmsupx5_defconfig b/configs/kmsupx5_defconfig index 49780b4b19..8f5e8aecec 100644 --- a/configs/kmsupx5_defconfig +++ b/configs/kmsupx5_defconfig @@ -78,6 +78,9 @@ CONFIG_LBLAW2=y CONFIG_LBLAW2_BASE=0xA0000000 CONFIG_LBLAW2_NAME="APP1" CONFIG_LBLAW2_LENGTH_256_MBYTES=y +CONFIG_HID0_FINAL_EMCP=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_MISC_INIT_R=y diff --git a/configs/kmtegr1_defconfig b/configs/kmtegr1_defconfig index 9a57e43d78..e3d721e093 100644 --- a/configs/kmtegr1_defconfig +++ b/configs/kmtegr1_defconfig @@ -79,6 +79,9 @@ CONFIG_LBLAW3=y CONFIG_LBLAW3_BASE=0xB0000000 CONFIG_LBLAW3_NAME="APP2" CONFIG_LBLAW3_LENGTH_256_MBYTES=y +CONFIG_HID0_FINAL_EMCP=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="KMTEGR1" diff --git a/configs/kmtepr2_defconfig b/configs/kmtepr2_defconfig index 78f7de9899..749b38586f 100644 --- a/configs/kmtepr2_defconfig +++ b/configs/kmtepr2_defconfig @@ -92,6 +92,9 @@ CONFIG_LBLAW3=y CONFIG_LBLAW3_BASE=0xB0000000 CONFIG_LBLAW3_NAME="APP2" CONFIG_LBLAW3_LENGTH_256_MBYTES=y +CONFIG_HID0_FINAL_EMCP=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_MISC_INIT_R=y diff --git a/configs/kmvect1_defconfig b/configs/kmvect1_defconfig index 7256750ea0..e8bb547b6f 100644 --- a/configs/kmvect1_defconfig +++ b/configs/kmvect1_defconfig @@ -93,6 +93,9 @@ CONFIG_LBLAW3=y CONFIG_LBLAW3_BASE=0xB0000000 CONFIG_LBLAW3_NAME="APP2" CONFIG_LBLAW3_LENGTH_256_MBYTES=y +CONFIG_HID0_FINAL_EMCP=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="KMVECT1" diff --git a/configs/mpc8308_p1m_defconfig b/configs/mpc8308_p1m_defconfig index ec2e30709c..b0da1c0704 100644 --- a/configs/mpc8308_p1m_defconfig +++ b/configs/mpc8308_p1m_defconfig @@ -56,6 +56,10 @@ CONFIG_LBLAW2=y CONFIG_LBLAW2_BASE=0xFBFF8000 CONFIG_LBLAW2_NAME="CPLD" CONFIG_LBLAW2_LENGTH_32_KBYTES=y +CONFIG_HID0_FINAL_EMCP=y +CONFIG_HID0_FINAL_DPM=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=5 diff --git a/configs/sbc8349_PCI_33_defconfig b/configs/sbc8349_PCI_33_defconfig index 453f85a0e3..a213f038ee 100644 --- a/configs/sbc8349_PCI_33_defconfig +++ b/configs/sbc8349_PCI_33_defconfig @@ -69,6 +69,9 @@ CONFIG_LBLAW0=y CONFIG_LBLAW0_BASE=0xFF800000 CONFIG_LBLAW0_NAME="FLASH" CONFIG_LBLAW0_LENGTH_8_MBYTES=y +CONFIG_HID0_FINAL_EMCP=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y CONFIG_PCI_64BIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/configs/sbc8349_PCI_66_defconfig b/configs/sbc8349_PCI_66_defconfig index b304615630..321c3d4073 100644 --- a/configs/sbc8349_PCI_66_defconfig +++ b/configs/sbc8349_PCI_66_defconfig @@ -69,6 +69,9 @@ CONFIG_LBLAW0=y CONFIG_LBLAW0_BASE=0xFF800000 CONFIG_LBLAW0_NAME="FLASH" CONFIG_LBLAW0_LENGTH_8_MBYTES=y +CONFIG_HID0_FINAL_EMCP=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y CONFIG_PCI_64BIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/configs/sbc8349_defconfig b/configs/sbc8349_defconfig index 4ec51af9f2..865a3ef74a 100644 --- a/configs/sbc8349_defconfig +++ b/configs/sbc8349_defconfig @@ -49,6 +49,9 @@ CONFIG_LBLAW0=y CONFIG_LBLAW0_BASE=0xFF800000 CONFIG_LBLAW0_NAME="FLASH" CONFIG_LBLAW0_LENGTH_8_MBYTES=y +CONFIG_HID0_FINAL_EMCP=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/strider_con_defconfig b/configs/strider_con_defconfig index a806e9957f..82db169673 100644 --- a/configs/strider_con_defconfig +++ b/configs/strider_con_defconfig @@ -53,6 +53,10 @@ CONFIG_LBLAW1=y CONFIG_LBLAW1_BASE=0xE0600000 CONFIG_LBLAW1_NAME="FPGA0" CONFIG_LBLAW1_LENGTH_1_MBYTES=y +CONFIG_HID0_FINAL_EMCP=y +CONFIG_HID0_FINAL_DPM=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y CONFIG_CMD_IOLOOP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/strider_con_dp_defconfig b/configs/strider_con_dp_defconfig index 3687a28fc3..b9f43273b0 100644 --- a/configs/strider_con_dp_defconfig +++ b/configs/strider_con_dp_defconfig @@ -53,6 +53,10 @@ CONFIG_LBLAW1=y CONFIG_LBLAW1_BASE=0xE0600000 CONFIG_LBLAW1_NAME="FPGA0" CONFIG_LBLAW1_LENGTH_1_MBYTES=y +CONFIG_HID0_FINAL_EMCP=y +CONFIG_HID0_FINAL_DPM=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y CONFIG_CMD_IOLOOP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/strider_cpu_defconfig b/configs/strider_cpu_defconfig index 4231a431b8..5dc1ddf923 100644 --- a/configs/strider_cpu_defconfig +++ b/configs/strider_cpu_defconfig @@ -53,6 +53,10 @@ CONFIG_LBLAW1=y CONFIG_LBLAW1_BASE=0xE0600000 CONFIG_LBLAW1_NAME="FPGA0" CONFIG_LBLAW1_LENGTH_1_MBYTES=y +CONFIG_HID0_FINAL_EMCP=y +CONFIG_HID0_FINAL_DPM=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y CONFIG_CMD_IOLOOP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/strider_cpu_dp_defconfig b/configs/strider_cpu_dp_defconfig index afb991ce1e..093f3e6b8b 100644 --- a/configs/strider_cpu_dp_defconfig +++ b/configs/strider_cpu_dp_defconfig @@ -53,6 +53,10 @@ CONFIG_LBLAW1=y CONFIG_LBLAW1_BASE=0xE0600000 CONFIG_LBLAW1_NAME="FPGA0" CONFIG_LBLAW1_LENGTH_1_MBYTES=y +CONFIG_HID0_FINAL_EMCP=y +CONFIG_HID0_FINAL_DPM=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y CONFIG_CMD_IOLOOP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/suvd3_defconfig b/configs/suvd3_defconfig index 2b16ceb524..fcd5741092 100644 --- a/configs/suvd3_defconfig +++ b/configs/suvd3_defconfig @@ -92,6 +92,9 @@ CONFIG_LBLAW3=y CONFIG_LBLAW3_BASE=0xB0000000 CONFIG_LBLAW3_NAME="APP2" CONFIG_LBLAW3_LENGTH_256_MBYTES=y +CONFIG_HID0_FINAL_EMCP=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SUVD3" diff --git a/configs/tuge1_defconfig b/configs/tuge1_defconfig index 07666c3b50..5f7f2289f1 100644 --- a/configs/tuge1_defconfig +++ b/configs/tuge1_defconfig @@ -78,6 +78,9 @@ CONFIG_LBLAW2=y CONFIG_LBLAW2_BASE=0xA0000000 CONFIG_LBLAW2_NAME="APP1" CONFIG_LBLAW2_LENGTH_256_MBYTES=y +CONFIG_HID0_FINAL_EMCP=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_MISC_INIT_R=y diff --git a/configs/tuxx1_defconfig b/configs/tuxx1_defconfig index 627bf2febf..600c6f36e0 100644 --- a/configs/tuxx1_defconfig +++ b/configs/tuxx1_defconfig @@ -92,6 +92,9 @@ CONFIG_LBLAW3=y CONFIG_LBLAW3_BASE=0xB0000000 CONFIG_LBLAW3_NAME="APP2" CONFIG_LBLAW3_LENGTH_256_MBYTES=y +CONFIG_HID0_FINAL_EMCP=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_MISC_INIT_R=y diff --git a/configs/ve8313_defconfig b/configs/ve8313_defconfig index 365c4ea858..42e0098a1c 100644 --- a/configs/ve8313_defconfig +++ b/configs/ve8313_defconfig @@ -74,6 +74,9 @@ CONFIG_LBLAW1=y CONFIG_LBLAW1_BASE=0x61000000 CONFIG_LBLAW1_NAME="NAND" CONFIG_LBLAW1_LENGTH_32_KBYTES=y +CONFIG_HID0_FINAL_EMCP=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/vme8349_defconfig b/configs/vme8349_defconfig index 072674cbeb..9ac88c0a4b 100644 --- a/configs/vme8349_defconfig +++ b/configs/vme8349_defconfig @@ -71,6 +71,9 @@ CONFIG_LBLAW1=y CONFIG_LBLAW1_BASE=0xF0000000 CONFIG_LBLAW1_NAME="WINDOW1" CONFIG_LBLAW1_LENGTH_256_KBYTES=y +CONFIG_HID0_FINAL_EMCP=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y CONFIG_PCI_64BIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h index cd78836bcd..9c4de05440 100644 --- a/include/configs/MPC8308RDB.h +++ b/include/configs/MPC8308RDB.h @@ -331,15 +331,6 @@ #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ -/* - * Core HID Setup - */ -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ - HID0_ENABLE_INSTRUCTION_CACHE | \ - HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) -#define CONFIG_SYS_HID2 HID2_HBE - /* * Environment Configuration */ diff --git a/include/configs/MPC8313ERDB_NAND.h b/include/configs/MPC8313ERDB_NAND.h index 93b553c905..2f48b135c4 100644 --- a/include/configs/MPC8313ERDB_NAND.h +++ b/include/configs/MPC8313ERDB_NAND.h @@ -362,13 +362,6 @@ /* Enable Internal USB Phy and GPIO on LCD Connector */ #define CONFIG_SYS_SICRL (SICRL_USBDR_10 | SICRL_LBC) -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ - HID0_ENABLE_INSTRUCTION_CACHE | \ - HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) - -#define CONFIG_SYS_HID2 HID2_HBE - /* * Environment Configuration */ diff --git a/include/configs/MPC8313ERDB_NOR.h b/include/configs/MPC8313ERDB_NOR.h index 18e056e1b2..bd1e54feec 100644 --- a/include/configs/MPC8313ERDB_NOR.h +++ b/include/configs/MPC8313ERDB_NOR.h @@ -335,13 +335,6 @@ /* Enable Internal USB Phy and GPIO on LCD Connector */ #define CONFIG_SYS_SICRL (SICRL_USBDR_10 | SICRL_LBC) -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ - HID0_ENABLE_INSTRUCTION_CACHE | \ - HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) - -#define CONFIG_SYS_HID2 HID2_HBE - /* * Environment Configuration */ diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index 708829dae8..5ce213f594 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -356,15 +356,6 @@ #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ -/* - * Core HID Setup - */ -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ - HID0_ENABLE_INSTRUCTION_CACHE | \ - HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) -#define CONFIG_SYS_HID2 HID2_HBE - /* * MMU Setup */ diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index c66e33a247..abc62f7e69 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -272,14 +272,6 @@ #define CONFIG_SYS_BOOTMAPSZ (256 << 20) #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ -/* - * Core HID Setup - */ -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ - HID0_ENABLE_INSTRUCTION_CACHE) -#define CONFIG_SYS_HID2 HID2_HBE - #if (CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ #endif diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index ed47bcd5b4..a138bd6724 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -290,14 +290,6 @@ #define CONFIG_SYS_BOOTMAPSZ (256 << 20) #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ -/* - * Core HID Setup - */ -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ - HID0_ENABLE_INSTRUCTION_CACHE) -#define CONFIG_SYS_HID2 HID2_HBE - #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ #endif diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 3e0907dae4..d0d6eaf6c2 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -341,17 +341,6 @@ #define CONFIG_SYS_SICRH 0 #define CONFIG_SYS_SICRL SICRL_LDP_A -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \ - | HID0_ENABLE_INSTRUCTION_CACHE) - -/* #define CONFIG_SYS_HID0_FINAL (\ - HID0_ENABLE_INSTRUCTION_CACHE |\ - HID0_ENABLE_M_BIT |\ - HID0_ENABLE_ADDRESS_BROADCAST) */ - -#define CONFIG_SYS_HID2 HID2_HBE - #ifdef CONFIG_PCI #define CONFIG_PCI_INDIRECT_BRIDGE #endif diff --git a/include/configs/MPC8349EMDS_SDRAM.h b/include/configs/MPC8349EMDS_SDRAM.h index e401c29d6b..976c1e8063 100644 --- a/include/configs/MPC8349EMDS_SDRAM.h +++ b/include/configs/MPC8349EMDS_SDRAM.h @@ -396,17 +396,6 @@ #define CONFIG_SYS_SICRH 0 #define CONFIG_SYS_SICRL SICRL_LDP_A -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \ - | HID0_ENABLE_INSTRUCTION_CACHE) - -/* #define CONFIG_SYS_HID0_FINAL (\ - HID0_ENABLE_INSTRUCTION_CACHE |\ - HID0_ENABLE_M_BIT |\ - HID0_ENABLE_ADDRESS_BROADCAST) */ - -#define CONFIG_SYS_HID2 HID2_HBE - #ifdef CONFIG_PCI #define CONFIG_PCI_INDIRECT_BRIDGE #endif diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index cc62fc3213..f37b086b1f 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -425,11 +425,6 @@ boards, we say we have two, but don't display a message if we find only one. */ /* USB DR as device + USB MPH as host */ #define CONFIG_SYS_SICRL (SICRL_LDP_A | SICRL_USB1) -#define CONFIG_SYS_HID0_INIT 0x00000000 -#define CONFIG_SYS_HID0_FINAL HID0_ENABLE_INSTRUCTION_CACHE - -#define CONFIG_SYS_HID2 HID2_HBE - #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ #endif diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index a244ae87a2..7361f0e2f6 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -361,14 +361,6 @@ extern int board_pci_host_broken(void); #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ -/* - * Core HID Setup - */ -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ - HID0_ENABLE_INSTRUCTION_CACHE) -#define CONFIG_SYS_HID2 HID2_HBE - #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ #endif diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index 006279a58c..3f17574cee 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -382,14 +382,6 @@ #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ -/* - * Core HID Setup - */ -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \ - | HID0_ENABLE_INSTRUCTION_CACHE) -#define CONFIG_SYS_HID2 HID2_HBE - #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ #endif diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index af03c03786..dc2bba828c 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -237,12 +237,6 @@ #define CONFIG_SYS_SICRH 0 #define CONFIG_SYS_SICRL SICRL_LDP_A -/* i-cache and d-cache disabled */ -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL (CONFIG_SYS_HID0_INIT | \ - HID0_ENABLE_INSTRUCTION_CACHE) -#define CONFIG_SYS_HID2 HID2_HBE - /* PCI */ #ifdef CONFIG_PCI #define CONFIG_PCI_INDIRECT_BRIDGE diff --git a/include/configs/caddy2.h b/include/configs/caddy2.h index e9cfeae64d..016477c04f 100644 --- a/include/configs/caddy2.h +++ b/include/configs/caddy2.h @@ -263,12 +263,6 @@ #define CONFIG_SYS_SICRH 0 #define CONFIG_SYS_SICRL SICRL_LDP_A -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ - HID0_ENABLE_INSTRUCTION_CACHE) - -#define CONFIG_SYS_HID2 HID2_HBE - #define CONFIG_SYS_GPIO1_PRELIM #define CONFIG_SYS_GPIO1_DIR 0x00100000 #define CONFIG_SYS_GPIO1_DAT 0x00100000 diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h index 4001a0a16b..b28f3c1d45 100644 --- a/include/configs/hrcon.h +++ b/include/configs/hrcon.h @@ -440,15 +440,6 @@ void fpga_control_clear(unsigned int bus, int pin); */ #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ -/* - * Core HID Setup - */ -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ - HID0_ENABLE_INSTRUCTION_CACHE | \ - HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) -#define CONFIG_SYS_HID2 HID2_HBE - /* * Environment Configuration */ diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h index d86dda18fb..1637ed9646 100644 --- a/include/configs/ids8313.h +++ b/include/configs/ids8313.h @@ -30,13 +30,6 @@ #define CONFIG_HWCONFIG -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK |\ - HID0_ENABLE_INSTRUCTION_CACHE |\ - HID0_DISABLE_DYNAMIC_POWER_MANAGMENT) - -#define CONFIG_SYS_HID2 (HID2_HBE | 0x00020000) - /* * Definitions for initial stack pointer and data area (in DCACHE ) */ diff --git a/include/configs/kmcoge5ne.h b/include/configs/kmcoge5ne.h index ede8ae6ba5..f3f78de8de 100644 --- a/include/configs/kmcoge5ne.h +++ b/include/configs/kmcoge5ne.h @@ -203,14 +203,6 @@ */ #define CONFIG_SYS_BOOTMAPSZ (8 << 20) -/* - * Core HID Setup - */ -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ - HID0_ENABLE_INSTRUCTION_CACHE) -#define CONFIG_SYS_HID2 HID2_HBE - /* * Internal Definitions */ diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h index 728c9b199f..aaa0607ed5 100644 --- a/include/configs/kmeter1.h +++ b/include/configs/kmeter1.h @@ -189,14 +189,6 @@ */ #define CONFIG_SYS_BOOTMAPSZ (8 << 20) -/* - * Core HID Setup - */ -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ - HID0_ENABLE_INSTRUCTION_CACHE) -#define CONFIG_SYS_HID2 HID2_HBE - /* * Internal Definitions */ diff --git a/include/configs/kmopti2.h b/include/configs/kmopti2.h index f39dbe05b7..e9bb3f7983 100644 --- a/include/configs/kmopti2.h +++ b/include/configs/kmopti2.h @@ -208,14 +208,6 @@ */ #define CONFIG_SYS_BOOTMAPSZ (8 << 20) -/* - * Core HID Setup - */ -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ - HID0_ENABLE_INSTRUCTION_CACHE) -#define CONFIG_SYS_HID2 HID2_HBE - /* * Internal Definitions */ diff --git a/include/configs/kmsupx5.h b/include/configs/kmsupx5.h index 19e415619a..182357b0c0 100644 --- a/include/configs/kmsupx5.h +++ b/include/configs/kmsupx5.h @@ -208,14 +208,6 @@ */ #define CONFIG_SYS_BOOTMAPSZ (8 << 20) -/* - * Core HID Setup - */ -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ - HID0_ENABLE_INSTRUCTION_CACHE) -#define CONFIG_SYS_HID2 HID2_HBE - /* * Internal Definitions */ diff --git a/include/configs/kmtegr1.h b/include/configs/kmtegr1.h index fe4763ce8a..0855dd152c 100644 --- a/include/configs/kmtegr1.h +++ b/include/configs/kmtegr1.h @@ -212,14 +212,6 @@ */ #define CONFIG_SYS_BOOTMAPSZ (8 << 20) -/* - * Core HID Setup - */ -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ - HID0_ENABLE_INSTRUCTION_CACHE) -#define CONFIG_SYS_HID2 HID2_HBE - /* * Internal Definitions */ diff --git a/include/configs/kmtepr2.h b/include/configs/kmtepr2.h index 9302d35949..7edb573747 100644 --- a/include/configs/kmtepr2.h +++ b/include/configs/kmtepr2.h @@ -208,14 +208,6 @@ */ #define CONFIG_SYS_BOOTMAPSZ (8 << 20) -/* - * Core HID Setup - */ -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ - HID0_ENABLE_INSTRUCTION_CACHE) -#define CONFIG_SYS_HID2 HID2_HBE - /* * Internal Definitions */ diff --git a/include/configs/kmvect1.h b/include/configs/kmvect1.h index 06c5923ae1..b88f158265 100644 --- a/include/configs/kmvect1.h +++ b/include/configs/kmvect1.h @@ -204,14 +204,6 @@ */ #define CONFIG_SYS_BOOTMAPSZ (8 << 20) -/* - * Core HID Setup - */ -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ - HID0_ENABLE_INSTRUCTION_CACHE) -#define CONFIG_SYS_HID2 HID2_HBE - /* * Internal Definitions */ diff --git a/include/configs/mpc8308_p1m.h b/include/configs/mpc8308_p1m.h index cb7dabd932..8ea3ea11dc 100644 --- a/include/configs/mpc8308_p1m.h +++ b/include/configs/mpc8308_p1m.h @@ -309,15 +309,6 @@ */ #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ -/* - * Core HID Setup - */ -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ - HID0_ENABLE_INSTRUCTION_CACHE | \ - HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) -#define CONFIG_SYS_HID2 HID2_HBE - /* * Environment Configuration */ diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index 98770ca0a6..b58628262d 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -283,17 +283,6 @@ #define CONFIG_SYS_SICRH 0 #define CONFIG_SYS_SICRL SICRL_LDP_A -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \ - | HID0_ENABLE_INSTRUCTION_CACHE) - -/* #define CONFIG_SYS_HID0_FINAL (\ - HID0_ENABLE_INSTRUCTION_CACHE |\ - HID0_ENABLE_M_BIT |\ - HID0_ENABLE_ADDRESS_BROADCAST) */ - -#define CONFIG_SYS_HID2 HID2_HBE - #ifdef CONFIG_PCI #define CONFIG_PCI_INDIRECT_BRIDGE #endif diff --git a/include/configs/strider.h b/include/configs/strider.h index 94164de06c..96b31741fd 100644 --- a/include/configs/strider.h +++ b/include/configs/strider.h @@ -473,15 +473,6 @@ void fpga_control_clear(unsigned int bus, int pin); */ #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ -/* - * Core HID Setup - */ -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ - HID0_ENABLE_INSTRUCTION_CACHE | \ - HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) -#define CONFIG_SYS_HID2 HID2_HBE - /* * Environment Configuration */ diff --git a/include/configs/suvd3.h b/include/configs/suvd3.h index a65b61bfbf..5d7d48dd39 100644 --- a/include/configs/suvd3.h +++ b/include/configs/suvd3.h @@ -205,14 +205,6 @@ */ #define CONFIG_SYS_BOOTMAPSZ (8 << 20) -/* - * Core HID Setup - */ -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ - HID0_ENABLE_INSTRUCTION_CACHE) -#define CONFIG_SYS_HID2 HID2_HBE - /* * Internal Definitions */ diff --git a/include/configs/tuge1.h b/include/configs/tuge1.h index 6084e8af60..d95147d1ed 100644 --- a/include/configs/tuge1.h +++ b/include/configs/tuge1.h @@ -208,14 +208,6 @@ */ #define CONFIG_SYS_BOOTMAPSZ (8 << 20) -/* - * Core HID Setup - */ -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ - HID0_ENABLE_INSTRUCTION_CACHE) -#define CONFIG_SYS_HID2 HID2_HBE - /* * Internal Definitions */ diff --git a/include/configs/tuxx1.h b/include/configs/tuxx1.h index 86aec93ee9..e6337d98ac 100644 --- a/include/configs/tuxx1.h +++ b/include/configs/tuxx1.h @@ -208,14 +208,6 @@ */ #define CONFIG_SYS_BOOTMAPSZ (8 << 20) -/* - * Core HID Setup - */ -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ - HID0_ENABLE_INSTRUCTION_CACHE) -#define CONFIG_SYS_HID2 HID2_HBE - /* * Internal Definitions */ diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h index 4c5dad9dc2..87160f2c34 100644 --- a/include/configs/ve8313.h +++ b/include/configs/ve8313.h @@ -268,12 +268,6 @@ SICRL_ETSEC2_A) /* 0x33fc0003) */ -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ - HID0_ENABLE_INSTRUCTION_CACHE) - -#define CONFIG_SYS_HID2 HID2_HBE - #define CONFIG_NETDEV eth0 #define CONFIG_HOSTNAME "ve8313" diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h index 9b9c1ff54e..2a14f561ed 100644 --- a/include/configs/vme8349.h +++ b/include/configs/vme8349.h @@ -263,12 +263,6 @@ #define CONFIG_SYS_SICRH 0 #define CONFIG_SYS_SICRL SICRL_LDP_A -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ - HID0_ENABLE_INSTRUCTION_CACHE) - -#define CONFIG_SYS_HID2 HID2_HBE - #define CONFIG_SYS_GPIO1_PRELIM #define CONFIG_SYS_GPIO1_DIR 0x00100000 #define CONFIG_SYS_GPIO1_DAT 0x00100000 diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 8473c369fe..bde1af251b 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -2932,9 +2932,6 @@ CONFIG_SYS_GPSR2_VAL CONFIG_SYS_GPSR3_VAL CONFIG_SYS_HALT_BEFOR_RAM_JUMP CONFIG_SYS_HELP_CMD_WIDTH -CONFIG_SYS_HID0_FINAL -CONFIG_SYS_HID0_INIT -CONFIG_SYS_HID2 CONFIG_SYS_HIGH CONFIG_SYS_HMI_BASE CONFIG_SYS_HOSTNAME From 71da74743180c81c3af31108839b5d0e6a1aff87 Mon Sep 17 00:00:00 2001 From: Mario Six Date: Mon, 21 Jan 2019 09:18:10 +0100 Subject: [PATCH 47/86] mpc83xx: Migrate CONFIG_SYS_IMMR to Kconfig Migrate CONFIG_SYS_IMMR to Kconfig for MPC83xx. Signed-off-by: Mario Six --- arch/powerpc/cpu/mpc83xx/Kconfig | 7 +++++++ configs/TQM834x_defconfig | 1 + configs/ids8313_defconfig | 1 + include/configs/MPC8308RDB.h | 5 ----- include/configs/MPC8313ERDB_NAND.h | 2 -- include/configs/MPC8313ERDB_NOR.h | 2 -- include/configs/MPC8315ERDB.h | 5 ----- include/configs/MPC8323ERDB.h | 5 ----- include/configs/MPC832XEMDS.h | 5 ----- include/configs/MPC8349EMDS.h | 2 -- include/configs/MPC8349EMDS_SDRAM.h | 2 -- include/configs/MPC8349ITX.h | 5 ----- include/configs/MPC837XEMDS.h | 5 ----- include/configs/MPC837XERDB.h | 5 ----- include/configs/TQM834x.h | 3 --- include/configs/caddy2.h | 2 -- include/configs/hrcon.h | 5 ----- include/configs/ids8313.h | 2 -- include/configs/kmcoge5ne.h | 5 ----- include/configs/kmeter1.h | 5 ----- include/configs/kmopti2.h | 5 ----- include/configs/kmsupx5.h | 5 ----- include/configs/kmtegr1.h | 5 ----- include/configs/kmtepr2.h | 5 ----- include/configs/kmvect1.h | 5 ----- include/configs/mpc8308_p1m.h | 5 ----- include/configs/sbc8349.h | 2 -- include/configs/strider.h | 5 ----- include/configs/suvd3.h | 5 ----- include/configs/tuge1.h | 5 ----- include/configs/tuxx1.h | 5 ----- include/configs/ve8313.h | 2 -- include/configs/vme8349.h | 2 -- 33 files changed, 9 insertions(+), 121 deletions(-) diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index 5fb4228076..96376837ab 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -282,6 +282,13 @@ config ARCH_MPC837X select MPC83XX_LDP_PIN select MPC83XX_SECOND_I2C_SUPPORT +config SYS_IMMR + hex "Value for IMMR" + default 0xE0000000 + help + Address for the Internal Memory-Mapped Registers (IMMR) window used + to configure the features of the SoC. + source "arch/powerpc/cpu/mpc83xx/hrcw/Kconfig" source "arch/powerpc/cpu/mpc83xx/bats/Kconfig" source "arch/powerpc/cpu/mpc83xx/lblaw/Kconfig" diff --git a/configs/TQM834x_defconfig b/configs/TQM834x_defconfig index e85bfaea31..f5746cfad7 100644 --- a/configs/TQM834x_defconfig +++ b/configs/TQM834x_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_CLK_FREQ=66666000 CONFIG_MPC83xx=y CONFIG_HIGH_BATS=y CONFIG_TARGET_TQM834X=y +CONFIG_SYS_IMMR=0xff400000 CONFIG_DDR_MC_CLOCK_MODE_1_1=y CONFIG_SYSTEM_PLL_FACTOR_4_1=y CONFIG_CORE_PLL_RATIO_2_1=y diff --git a/configs/ids8313_defconfig b/configs/ids8313_defconfig index 24590d1448..9c16a1231c 100644 --- a/configs/ids8313_defconfig +++ b/configs/ids8313_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_HIGH_BATS=y CONFIG_TARGET_IDS8313=y +CONFIG_SYS_IMMR=0xF0000000 CONFIG_CORE_PLL_RATIO_2_1=y CONFIG_PCI_HOST_MODE_ENABLE=y CONFIG_BOOT_ROM_INTERFACE_GPCM_8BIT=y diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h index 9c4de05440..e825cfbd17 100644 --- a/include/configs/MPC8308RDB.h +++ b/include/configs/MPC8308RDB.h @@ -52,11 +52,6 @@ SICRL_I2C2_PF0 |\ SICRL_ETSEC1_GTX_CLK125) /* 0x00000040 */ -/* - * IMMR new address - */ -#define CONFIG_SYS_IMMR 0xE0000000 - /* * SERDES */ diff --git a/include/configs/MPC8313ERDB_NAND.h b/include/configs/MPC8313ERDB_NAND.h index 2f48b135c4..e23df14ec1 100644 --- a/include/configs/MPC8313ERDB_NAND.h +++ b/include/configs/MPC8313ERDB_NAND.h @@ -54,8 +54,6 @@ #define CONFIG_VSC7385_ENET #define CONFIG_TSEC2 -#define CONFIG_SYS_IMMR 0xE0000000 - #if !defined(CONFIG_SPL_BUILD) #define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR #endif diff --git a/include/configs/MPC8313ERDB_NOR.h b/include/configs/MPC8313ERDB_NOR.h index bd1e54feec..17cd8adc85 100644 --- a/include/configs/MPC8313ERDB_NOR.h +++ b/include/configs/MPC8313ERDB_NOR.h @@ -30,8 +30,6 @@ #define CONFIG_VSC7385_ENET #define CONFIG_TSEC2 -#define CONFIG_SYS_IMMR 0xE0000000 - #define CONFIG_SYS_MEMTEST_START 0x00001000 #define CONFIG_SYS_MEMTEST_END 0x07f00000 diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index 5ce213f594..fbba2fbb50 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -31,11 +31,6 @@ #define CONFIG_HWCONFIG -/* - * IMMR new address - */ -#define CONFIG_SYS_IMMR 0xE0000000 - /* * Arbiter Setup */ diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index abc62f7e69..b528c2901b 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -20,11 +20,6 @@ */ #define CONFIG_SYS_SICRL 0x00000000 -/* - * IMMR new address - */ -#define CONFIG_SYS_IMMR 0xE0000000 - /* * System performance */ diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index a138bd6724..195d62ce50 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -17,11 +17,6 @@ */ #define CONFIG_SYS_SICRL 0x00000000 -/* - * IMMR new address - */ -#define CONFIG_SYS_IMMR 0xE0000000 - /* * DDR Setup */ diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index d0d6eaf6c2..14ebc8ead3 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -17,8 +17,6 @@ */ #define CONFIG_E300 1 /* E300 Family */ -#define CONFIG_SYS_IMMR 0xE0000000 - #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ #define CONFIG_SYS_MEMTEST_END 0x00100000 diff --git a/include/configs/MPC8349EMDS_SDRAM.h b/include/configs/MPC8349EMDS_SDRAM.h index 976c1e8063..67f3a9bd65 100644 --- a/include/configs/MPC8349EMDS_SDRAM.h +++ b/include/configs/MPC8349EMDS_SDRAM.h @@ -17,8 +17,6 @@ */ #define CONFIG_E300 1 /* E300 Family */ -#define CONFIG_SYS_IMMR 0xE0000000 - #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ #define CONFIG_SYS_MEMTEST_END 0x00100000 diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index f37b086b1f..eef1bdec63 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -39,11 +39,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -/* - * High Level Configuration Options - */ -#define CONFIG_SYS_IMMR 0xE0000000 /* The IMMR is relocated to here */ - #define CONFIG_MISC_INIT_F /* diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index 7361f0e2f6..c1973703c4 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -39,11 +39,6 @@ #define CONFIG_HWCONFIG -/* - * IMMR new address - */ -#define CONFIG_SYS_IMMR 0xE0000000 - /* * DDR Setup */ diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index 3f17574cee..e8173da323 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -46,11 +46,6 @@ */ #define CONFIG_SYS_OBIR 0x30100000 -/* - * IMMR new address - */ -#define CONFIG_SYS_IMMR 0xE0000000 - /* * Device configurations */ diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index dc2bba828c..d713c695f7 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -16,9 +16,6 @@ */ #define CONFIG_E300 1 /* E300 Family */ -/* IMMR Base Address Register, use Freescale default: 0xff400000 */ -#define CONFIG_SYS_IMMR 0xff400000 - /* * Local Bus LCRR * LCRR: DLL bypass, Clock divider is 8 diff --git a/include/configs/caddy2.h b/include/configs/caddy2.h index 016477c04f..b4516267f1 100644 --- a/include/configs/caddy2.h +++ b/include/configs/caddy2.h @@ -25,8 +25,6 @@ /* Don't enable PCI2 on vme834x - it doesn't exist physically. */ #undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */ -#define CONFIG_SYS_IMMR 0xE0000000 - #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ #define CONFIG_SYS_MEMTEST_END 0x00100000 diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h index b28f3c1d45..e8a4b7adf6 100644 --- a/include/configs/hrcon.h +++ b/include/configs/hrcon.h @@ -40,11 +40,6 @@ SICRL_I2C2_PF0 |\ SICRL_ETSEC1_GTX_CLK125) /* 0x00000000 */ -/* - * IMMR new address - */ -#define CONFIG_SYS_IMMR 0xE0000000 - /* * SERDES */ diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h index 1637ed9646..b4acee058c 100644 --- a/include/configs/ids8313.h +++ b/include/configs/ids8313.h @@ -20,8 +20,6 @@ #define CONFIG_BOOT_RETRY_MIN 30 #define CONFIG_RESET_TO_RETRY -#define CONFIG_SYS_IMMR 0xF0000000 - #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ diff --git a/include/configs/kmcoge5ne.h b/include/configs/kmcoge5ne.h index f3f78de8de..8e09160f92 100644 --- a/include/configs/kmcoge5ne.h +++ b/include/configs/kmcoge5ne.h @@ -40,11 +40,6 @@ #define CONFIG_SYS_CLK_FREQ 66000000 #define CONFIG_83XX_PCICLK 66000000 -/* - * IMMR new address - */ -#define CONFIG_SYS_IMMR 0xE0000000 - /* * Bus Arbitration Configuration Register (ACR) */ diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h index aaa0607ed5..48a6172349 100644 --- a/include/configs/kmeter1.h +++ b/include/configs/kmeter1.h @@ -25,11 +25,6 @@ #include "km/keymile-common.h" #include "km/km-powerpc.h" -/* - * IMMR new address - */ -#define CONFIG_SYS_IMMR 0xE0000000 - /* * Bus Arbitration Configuration Register (ACR) */ diff --git a/include/configs/kmopti2.h b/include/configs/kmopti2.h index e9bb3f7983..e34f26e55d 100644 --- a/include/configs/kmopti2.h +++ b/include/configs/kmopti2.h @@ -45,11 +45,6 @@ #define CONFIG_SYS_CLK_FREQ 66000000 #define CONFIG_83XX_PCICLK 66000000 -/* - * IMMR new address - */ -#define CONFIG_SYS_IMMR 0xE0000000 - /* * Bus Arbitration Configuration Register (ACR) */ diff --git a/include/configs/kmsupx5.h b/include/configs/kmsupx5.h index 182357b0c0..96e10325f0 100644 --- a/include/configs/kmsupx5.h +++ b/include/configs/kmsupx5.h @@ -45,11 +45,6 @@ #define CONFIG_SYS_CLK_FREQ 66000000 #define CONFIG_83XX_PCICLK 66000000 -/* - * IMMR new address - */ -#define CONFIG_SYS_IMMR 0xE0000000 - /* * Bus Arbitration Configuration Register (ACR) */ diff --git a/include/configs/kmtegr1.h b/include/configs/kmtegr1.h index 0855dd152c..4b407af036 100644 --- a/include/configs/kmtegr1.h +++ b/include/configs/kmtegr1.h @@ -52,11 +52,6 @@ #define CONFIG_SYS_CLK_FREQ 66000000 #define CONFIG_83XX_PCICLK 66000000 -/* - * IMMR new address - */ -#define CONFIG_SYS_IMMR 0xE0000000 - /* * Bus Arbitration Configuration Register (ACR) */ diff --git a/include/configs/kmtepr2.h b/include/configs/kmtepr2.h index 7edb573747..20cbc1318a 100644 --- a/include/configs/kmtepr2.h +++ b/include/configs/kmtepr2.h @@ -45,11 +45,6 @@ #define CONFIG_SYS_CLK_FREQ 66000000 #define CONFIG_83XX_PCICLK 66000000 -/* - * IMMR new address - */ -#define CONFIG_SYS_IMMR 0xE0000000 - /* * Bus Arbitration Configuration Register (ACR) */ diff --git a/include/configs/kmvect1.h b/include/configs/kmvect1.h index b88f158265..37acb0245b 100644 --- a/include/configs/kmvect1.h +++ b/include/configs/kmvect1.h @@ -44,11 +44,6 @@ #define CONFIG_SYS_CLK_FREQ 66000000 #define CONFIG_83XX_PCICLK 66000000 -/* - * IMMR new address - */ -#define CONFIG_SYS_IMMR 0xE0000000 - /* * Bus Arbitration Configuration Register (ACR) */ diff --git a/include/configs/mpc8308_p1m.h b/include/configs/mpc8308_p1m.h index 8ea3ea11dc..76846c43d0 100644 --- a/include/configs/mpc8308_p1m.h +++ b/include/configs/mpc8308_p1m.h @@ -55,11 +55,6 @@ */ #define CONFIG_SYS_GPIO1_DAT 0x08008C00 -/* - * IMMR new address - */ -#define CONFIG_SYS_IMMR 0xE0000000 - /* * SERDES */ diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index b58628262d..775bbe417a 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -22,8 +22,6 @@ /* Don't enable PCI2 on sbc834x - it doesn't exist physically. */ #undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */ -#define CONFIG_SYS_IMMR 0xE0000000 - #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ #define CONFIG_SYS_MEMTEST_END 0x00100000 diff --git a/include/configs/strider.h b/include/configs/strider.h index 96b31741fd..fe2d89f2a6 100644 --- a/include/configs/strider.h +++ b/include/configs/strider.h @@ -40,11 +40,6 @@ SICRL_I2C2_PF0 |\ SICRL_ETSEC1_TX_CLK) /* 0x00000000 */ -/* - * IMMR new address - */ -#define CONFIG_SYS_IMMR 0xE0000000 - /* * SERDES */ diff --git a/include/configs/suvd3.h b/include/configs/suvd3.h index 5d7d48dd39..82ebbca4db 100644 --- a/include/configs/suvd3.h +++ b/include/configs/suvd3.h @@ -42,11 +42,6 @@ #define CONFIG_SYS_CLK_FREQ 66000000 #define CONFIG_83XX_PCICLK 66000000 -/* - * IMMR new address - */ -#define CONFIG_SYS_IMMR 0xE0000000 - /* * Bus Arbitration Configuration Register (ACR) */ diff --git a/include/configs/tuge1.h b/include/configs/tuge1.h index d95147d1ed..b196c77c4e 100644 --- a/include/configs/tuge1.h +++ b/include/configs/tuge1.h @@ -45,11 +45,6 @@ #define CONFIG_SYS_CLK_FREQ 66000000 #define CONFIG_83XX_PCICLK 66000000 -/* - * IMMR new address - */ -#define CONFIG_SYS_IMMR 0xE0000000 - /* * Bus Arbitration Configuration Register (ACR) */ diff --git a/include/configs/tuxx1.h b/include/configs/tuxx1.h index e6337d98ac..0ce848c911 100644 --- a/include/configs/tuxx1.h +++ b/include/configs/tuxx1.h @@ -45,11 +45,6 @@ #define CONFIG_SYS_CLK_FREQ 66000000 #define CONFIG_83XX_PCICLK 66000000 -/* - * IMMR new address - */ -#define CONFIG_SYS_IMMR 0xE0000000 - /* * Bus Arbitration Configuration Register (ACR) */ diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h index 87160f2c34..1ac6cbefd6 100644 --- a/include/configs/ve8313.h +++ b/include/configs/ve8313.h @@ -24,8 +24,6 @@ * On-board devices * */ -#define CONFIG_SYS_IMMR 0xE0000000 - #define CONFIG_SYS_MEMTEST_START 0x00001000 #define CONFIG_SYS_MEMTEST_END 0x07000000 diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h index 2a14f561ed..1a3a55b707 100644 --- a/include/configs/vme8349.h +++ b/include/configs/vme8349.h @@ -25,8 +25,6 @@ /* Don't enable PCI2 on vme834x - it doesn't exist physically. */ #undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */ -#define CONFIG_SYS_IMMR 0xE0000000 - #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ #define CONFIG_SYS_MEMTEST_END 0x00100000 From ba463c116963e87bf2377ef8e0cdf4967c48fea7 Mon Sep 17 00:00:00 2001 From: Mario Six Date: Mon, 21 Jan 2019 09:18:11 +0100 Subject: [PATCH 48/86] mpc8308: Migrate system io config to Kconfig Migrate the system IO configuration setting to Kconfig. Signed-off-by: Mario Six --- arch/powerpc/cpu/mpc83xx/Kconfig | 1 + arch/powerpc/cpu/mpc83xx/cpu_init.c | 1 + arch/powerpc/cpu/mpc83xx/sysio/Kconfig | 7 + .../powerpc/cpu/mpc83xx/sysio/Kconfig.mpc8308 | 323 ++++++++++++++++++ arch/powerpc/cpu/mpc83xx/sysio/sysio.h | 32 ++ configs/MPC8308RDB_defconfig | 8 + configs/hrcon_defconfig | 9 + configs/hrcon_dh_defconfig | 9 + configs/mpc8308_p1m_defconfig | 8 + configs/strider_con_defconfig | 9 + configs/strider_con_dp_defconfig | 9 + configs/strider_cpu_defconfig | 9 + configs/strider_cpu_dp_defconfig | 9 + include/configs/MPC8308RDB.h | 25 -- include/configs/hrcon.h | 25 -- include/configs/mpc8308_p1m.h | 25 -- include/configs/strider.h | 25 -- 17 files changed, 434 insertions(+), 100 deletions(-) create mode 100644 arch/powerpc/cpu/mpc83xx/sysio/Kconfig create mode 100644 arch/powerpc/cpu/mpc83xx/sysio/Kconfig.mpc8308 create mode 100644 arch/powerpc/cpu/mpc83xx/sysio/sysio.h diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index 96376837ab..9f7b3a2e01 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -294,6 +294,7 @@ source "arch/powerpc/cpu/mpc83xx/bats/Kconfig" source "arch/powerpc/cpu/mpc83xx/lblaw/Kconfig" source "arch/powerpc/cpu/mpc83xx/elbc/Kconfig" source "arch/powerpc/cpu/mpc83xx/hid/Kconfig" +source "arch/powerpc/cpu/mpc83xx/sysio/Kconfig" menu "Legacy options" diff --git a/arch/powerpc/cpu/mpc83xx/cpu_init.c b/arch/powerpc/cpu/mpc83xx/cpu_init.c index 5ce7b794b2..3df01ee1ca 100644 --- a/arch/powerpc/cpu/mpc83xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc83xx/cpu_init.c @@ -14,6 +14,7 @@ #include "lblaw/lblaw.h" #include "elbc/elbc.h" +#include "sysio/sysio.h" DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/powerpc/cpu/mpc83xx/sysio/Kconfig b/arch/powerpc/cpu/mpc83xx/sysio/Kconfig new file mode 100644 index 0000000000..9e1f158712 --- /dev/null +++ b/arch/powerpc/cpu/mpc83xx/sysio/Kconfig @@ -0,0 +1,7 @@ +menu "System I/O configuration" + +if ARCH_MPC8308 +source "arch/powerpc/cpu/mpc83xx/sysio/Kconfig.mpc8308" +endif + +endmenu diff --git a/arch/powerpc/cpu/mpc83xx/sysio/Kconfig.mpc8308 b/arch/powerpc/cpu/mpc83xx/sysio/Kconfig.mpc8308 new file mode 100644 index 0000000000..de62171b30 --- /dev/null +++ b/arch/powerpc/cpu/mpc83xx/sysio/Kconfig.mpc8308 @@ -0,0 +1,323 @@ +choice + prompt "SPI group" + +config SICR_SPI_SPI + bool "SPI" + +config SICR_SPI_MSRCID + bool "MSRCID" + +config SICR_SPI_LSRCID + bool "LSRCID" + +endchoice + +choice + prompt "UART group" + +config SICR_UART_SPI + bool "UART" + +config SICR_UART_MSRCID + bool "MSRCID" + +config SICR_UART_LSRCID + bool "LSRCID" + +endchoice + +choice + prompt "IRQ group" + +config SICR_IRQ_SPI + bool "IRQ" + +config SICR_IRQ_MCP_CKSTOP + bool "MCP/CKSTOP" + +config SICR_IRQ_INTA + bool "INTA" + +endchoice + +choice + prompt "I2C2 group" + +config SICR_I2C2_I2C + bool "IRQ" + +config SICR_I2C2_CKSTOP + bool "CKSTOP" + +endchoice + +choice + prompt "ETSEC1 A group" + +config SICR_ETSEC1_A_TSEC2 + bool "TSEC1" + +config SICR_ETSEC1_A_TSEC_GTX_CLK125 + bool "TSEC1 GTX_CLK125" + +endchoice + +choice + prompt "eSDHC A group" + +config SICR_ESDHC_A_SD + bool "SD" + +config SICR_ESDHC_A_GTM + bool "GTM" + +config SICR_ESDHC_A_GPIO + bool "GPIO" + +endchoice + +choice + prompt "eSDHC B group" + +config SICR_ESDHC_B_SD + bool "SD" + +config SICR_ESDHC_B_GTM + bool "GTM" + +config SICR_ESDHC_B_GPIO + bool "GPIO" + +endchoice + +choice + prompt "eSDHC C group" + +config SICR_ESDHC_C_SD + bool "SD" + +config SICR_ESDHC_C_GTM + bool "GTM" + +config SICR_ESDHC_C_GPIO + bool "GPIO" + +endchoice + +choice + prompt "GPIO A group" + +config SICR_GPIO_A_GPIO + bool "GPIO" + +config SICR_GPIO_A_TSEC2 + bool "TSEC2" + +endchoice + +choice + prompt "GPIO B group" + +config SICR_GPIO_B_GPIO + bool "GPIO" + +config SICR_GPIO_B_TSEC2 + bool "TSEC2" + +config SICR_GPIO_B_TSEC_GTX_CLK125 + bool "TSEC2 GTX_CLK125" + +endchoice + +choice + prompt "IEEE1588 A group" + +config SICR_IEEE1588_A_TSEC + bool "TSEC" + +config SICR_IEEE1588_A_GPIO + bool "GPIO" + +endchoice + +choice + prompt "USB group" + +config SICR_USB_TSEC + bool "USB" + +endchoice + +choice + prompt "GTM group" + +config SICR_GTM_TSEC + bool "GTM" + +config SICR_GTM_GPIO + bool "GPIO" + +endchoice + +choice + prompt "IEEE1588 B group" + +config SICR_IEEE1588_B_GPIO + bool "GPIO" + +endchoice + +choice + prompt "ETSEC2 group" + +config SICR_ETSEC2_TSEC2 + bool "TSEC2" + +config SICR_ETSEC2_GPIO + bool "GPIO" + +endchoice + +choice + prompt "GPIO selection" + +config SICR_GPIOSEL_GPIO + bool "GPIO_A, GPIO_B" + +config SICR_GPIOSEL_IEEE1588 + bool "IEEE1588_A, IEEE1588_B, ETSEC2" + +endchoice + +choice + prompt "IEEE1588 timer output buffer impedance" + +config SICR_TMROBI_3_3_V + bool "40 Ohm, 3.3V" + +config SICR_TMROBI_2_5_V + bool "40 Ohm, 2.5V" + +endchoice + +choice + prompt "TSEC1 output buffer impedance" + +config SICR_TMSOBI1_3_3_V + bool "40 Ohm, 3.3V" + +config SICR_TMSOBI1_2_5_V + bool "40 Ohm, 2.5V" + +endchoice + +choice + prompt "TSEC2 output buffer impedance" + +config SICR_TMSOBI2_3_3_V + bool "40 Ohm, 3.3V" + +config SICR_TMSOBI2_2_5_V + bool "40 Ohm, 2.5V" + +endchoice + +config SICRL_SPI + hex + default 0x0 if SICR_SPI_SPI + default 0x10000000 if SICR_SPI_MSRCID + default 0x30000000 if SICR_SPI_LSRCID + +config SICRL_UART + hex + default 0x0 if SICR_UART_SPI + default 0x4000000 if SICR_UART_MSRCID + default 0xc000000 if SICR_UART_LSRCID + +config SICRL_IRQ + hex + default 0x0 if SICR_IRQ_SPI + default 0x1000000 if SICR_IRQ_MCP_CKSTOP + default 0x3000000 if SICR_IRQ_INTA + +config SICRL_I2C2 + hex + default 0x0 if SICR_I2C2_I2C + default 0x100000 if SICR_I2C2_CKSTOP + +config SICRL_ETSEC1_A + hex + default 0x0 if SICR_ETSEC1_A_TSEC2 + default 0x40 if SICR_ETSEC1_A_TSEC_GTX_CLK125 + +config SICRH_ESDHC_A + hex + default 0x0 if SICR_ESDHC_A_SD + default 0x40000000 if SICR_ESDHC_A_GTM + default 0xc0000000 if SICR_ESDHC_A_GPIO + +config SICRH_ESDHC_B + hex + default 0x0 if SICR_ESDHC_B_SD + default 0x10000000 if SICR_ESDHC_B_GTM + default 0x30000000 if SICR_ESDHC_B_GPIO + +config SICRH_ESDHC_C + hex + default 0x0 if SICR_ESDHC_C_SD + default 0x4000000 if SICR_ESDHC_C_GTM + default 0xc000000 if SICR_ESDHC_C_GPIO + +config SICRH_GPIO_A + hex + default 0x0 if SICR_GPIO_A_GPIO + default 0x1000000 if SICR_GPIO_A_TSEC2 + +config SICRH_GPIO_B + hex + default 0x0 if SICR_GPIO_B_GPIO + default 0x400000 if SICR_GPIO_B_TSEC2 + default 0x800000 if SICR_GPIO_B_TSEC_GTX_CLK125 + +config SICRH_IEEE1588_A + hex + default 0x100000 if SICR_IEEE1588_A_TSEC + default 0x300000 if SICR_IEEE1588_A_GPIO + +config SICRH_USB + hex + default 0x40000 if SICR_USB_TSEC + +config SICRH_GTM + hex + default 0x10000 if SICR_GTM_TSEC + default 0x30000 if SICR_GTM_GPIO + +config SICRH_IEEE1588_B + hex + default 0xc000 if SICR_IEEE1588_B_GPIO + +config SICRH_ETSEC2 + hex + default 0x1000 if SICR_ETSEC2_TSEC2 + default 0x3000 if SICR_ETSEC2_GPIO + +config SICRH_GPIOSEL + hex + default 0x0 if SICR_GPIOSEL_GPIO + default 0x100 if SICR_GPIOSEL_IEEE1588 + +config SICRH_TMROBI + hex + default 0x0 if SICR_TMROBI_3_3_V + default 0x10 if SICR_TMROBI_2_5_V + +config SICRH_TMSOBI1 + hex + default 0x0 if SICR_TMSOBI1_3_3_V + default 0x2 if SICR_TMSOBI1_2_5_V + +config SICRH_TMSOBI2 + hex + default 0x0 if SICR_TMSOBI2_3_3_V + default 0x1 if SICR_TMSOBI2_2_5_V diff --git a/arch/powerpc/cpu/mpc83xx/sysio/sysio.h b/arch/powerpc/cpu/mpc83xx/sysio/sysio.h new file mode 100644 index 0000000000..f8c2f104c1 --- /dev/null +++ b/arch/powerpc/cpu/mpc83xx/sysio/sysio.h @@ -0,0 +1,32 @@ +#ifdef CONFIG_ARCH_MPC8308 + +#ifndef CONFIG_SYS_SICRL +#define CONFIG_SYS_SICRL (\ + CONFIG_SICRL_SPI |\ + CONFIG_SICRL_UART |\ + CONFIG_SICRL_IRQ |\ + CONFIG_SICRL_I2C2 |\ + CONFIG_SICRL_ETSEC1_A \ +) +#endif + +#ifndef CONFIG_SYS_SICRH +#define CONFIG_SYS_SICRH (\ + CONFIG_SICRH_ESDHC_A |\ + CONFIG_SICRH_ESDHC_B |\ + CONFIG_SICRH_ESDHC_C |\ + CONFIG_SICRH_GPIO_A |\ + CONFIG_SICRH_GPIO_B |\ + CONFIG_SICRH_IEEE1588_A |\ + CONFIG_SICRH_USB |\ + CONFIG_SICRH_GTM |\ + CONFIG_SICRH_IEEE1588_B |\ + CONFIG_SICRH_ETSEC2 |\ + CONFIG_SICRH_GPIOSEL |\ + CONFIG_SICRH_TMROBI |\ + CONFIG_SICRH_TMSOBI1 |\ + CONFIG_SICRH_TMSOBI2 \ +) +#endif + +#endif diff --git a/configs/MPC8308RDB_defconfig b/configs/MPC8308RDB_defconfig index e674848a6c..9be515567c 100644 --- a/configs/MPC8308RDB_defconfig +++ b/configs/MPC8308RDB_defconfig @@ -62,6 +62,14 @@ CONFIG_HID0_FINAL_EMCP=y CONFIG_HID0_FINAL_DPM=y CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y +CONFIG_SICR_ETSEC1_A_TSEC_GTX_CLK125=y +CONFIG_SICR_GPIO_A_TSEC2=y +CONFIG_SICR_GPIO_B_TSEC_GTX_CLK125=y +CONFIG_SICR_IEEE1588_A_GPIO=y +CONFIG_SICR_GTM_GPIO=y +CONFIG_SICR_GPIOSEL_IEEE1588=y +CONFIG_SICR_TMSOBI1_2_5_V=y +CONFIG_SICR_TMSOBI2_2_5_V=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/hrcon_defconfig b/configs/hrcon_defconfig index 2046b6067d..3442c9c797 100644 --- a/configs/hrcon_defconfig +++ b/configs/hrcon_defconfig @@ -58,6 +58,15 @@ CONFIG_HID0_FINAL_EMCP=y CONFIG_HID0_FINAL_DPM=y CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y +CONFIG_SICR_ETSEC1_A_TSEC_GTX_CLK125=y +CONFIG_SICR_GPIO_A_GPIO=y +CONFIG_SICR_GPIO_B_GPIO=y +CONFIG_SICR_IEEE1588_A_GPIO=y +CONFIG_SICR_GTM_GPIO=y +CONFIG_SICR_ETSEC2_GPIO=y +CONFIG_SICR_GPIOSEL_IEEE1588=y +CONFIG_SICR_TMSOBI1_2_5_V=y +CONFIG_SICR_TMSOBI2_2_5_V=y CONFIG_CMD_IOLOOP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/hrcon_dh_defconfig b/configs/hrcon_dh_defconfig index e9d427be36..5de0eaa4d0 100644 --- a/configs/hrcon_dh_defconfig +++ b/configs/hrcon_dh_defconfig @@ -58,6 +58,15 @@ CONFIG_HID0_FINAL_EMCP=y CONFIG_HID0_FINAL_DPM=y CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y +CONFIG_SICR_ETSEC1_A_TSEC_GTX_CLK125=y +CONFIG_SICR_GPIO_A_GPIO=y +CONFIG_SICR_GPIO_B_GPIO=y +CONFIG_SICR_IEEE1588_A_GPIO=y +CONFIG_SICR_GTM_GPIO=y +CONFIG_SICR_ETSEC2_GPIO=y +CONFIG_SICR_GPIOSEL_IEEE1588=y +CONFIG_SICR_TMSOBI1_2_5_V=y +CONFIG_SICR_TMSOBI2_2_5_V=y CONFIG_CMD_IOLOOP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/mpc8308_p1m_defconfig b/configs/mpc8308_p1m_defconfig index b0da1c0704..26601ff0a6 100644 --- a/configs/mpc8308_p1m_defconfig +++ b/configs/mpc8308_p1m_defconfig @@ -60,6 +60,14 @@ CONFIG_HID0_FINAL_EMCP=y CONFIG_HID0_FINAL_DPM=y CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y +CONFIG_SICR_ESDHC_A_GPIO=y +CONFIG_SICR_ESDHC_B_GPIO=y +CONFIG_SICR_ESDHC_C_GTM=y +CONFIG_SICR_GPIO_A_TSEC2=y +CONFIG_SICR_GPIO_B_TSEC2=y +CONFIG_SICR_IEEE1588_A_GPIO=y +CONFIG_SICR_GTM_GPIO=y +CONFIG_SICR_GPIOSEL_IEEE1588=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=5 diff --git a/configs/strider_con_defconfig b/configs/strider_con_defconfig index 82db169673..1244652c79 100644 --- a/configs/strider_con_defconfig +++ b/configs/strider_con_defconfig @@ -57,6 +57,15 @@ CONFIG_HID0_FINAL_EMCP=y CONFIG_HID0_FINAL_DPM=y CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y +CONFIG_SICR_ETSEC1_A_TSEC2=y +CONFIG_SICR_GPIO_A_GPIO=y +CONFIG_SICR_GPIO_B_GPIO=y +CONFIG_SICR_IEEE1588_A_GPIO=y +CONFIG_SICR_GTM_GPIO=y +CONFIG_SICR_ETSEC2_GPIO=y +CONFIG_SICR_GPIOSEL_IEEE1588=y +CONFIG_SICR_TMSOBI1_2_5_V=y +CONFIG_SICR_TMSOBI2_2_5_V=y CONFIG_CMD_IOLOOP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/strider_con_dp_defconfig b/configs/strider_con_dp_defconfig index b9f43273b0..05040b056e 100644 --- a/configs/strider_con_dp_defconfig +++ b/configs/strider_con_dp_defconfig @@ -57,6 +57,15 @@ CONFIG_HID0_FINAL_EMCP=y CONFIG_HID0_FINAL_DPM=y CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y +CONFIG_SICR_ETSEC1_A_TSEC2=y +CONFIG_SICR_GPIO_A_GPIO=y +CONFIG_SICR_GPIO_B_GPIO=y +CONFIG_SICR_IEEE1588_A_GPIO=y +CONFIG_SICR_GTM_GPIO=y +CONFIG_SICR_ETSEC2_GPIO=y +CONFIG_SICR_GPIOSEL_IEEE1588=y +CONFIG_SICR_TMSOBI1_2_5_V=y +CONFIG_SICR_TMSOBI2_2_5_V=y CONFIG_CMD_IOLOOP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/strider_cpu_defconfig b/configs/strider_cpu_defconfig index 5dc1ddf923..fbae6546d7 100644 --- a/configs/strider_cpu_defconfig +++ b/configs/strider_cpu_defconfig @@ -57,6 +57,15 @@ CONFIG_HID0_FINAL_EMCP=y CONFIG_HID0_FINAL_DPM=y CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y +CONFIG_SICR_ETSEC1_A_TSEC2=y +CONFIG_SICR_GPIO_A_GPIO=y +CONFIG_SICR_GPIO_B_GPIO=y +CONFIG_SICR_IEEE1588_A_GPIO=y +CONFIG_SICR_GTM_GPIO=y +CONFIG_SICR_ETSEC2_GPIO=y +CONFIG_SICR_GPIOSEL_IEEE1588=y +CONFIG_SICR_TMSOBI1_2_5_V=y +CONFIG_SICR_TMSOBI2_2_5_V=y CONFIG_CMD_IOLOOP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/strider_cpu_dp_defconfig b/configs/strider_cpu_dp_defconfig index 093f3e6b8b..e3405707e5 100644 --- a/configs/strider_cpu_dp_defconfig +++ b/configs/strider_cpu_dp_defconfig @@ -57,6 +57,15 @@ CONFIG_HID0_FINAL_EMCP=y CONFIG_HID0_FINAL_DPM=y CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y +CONFIG_SICR_ETSEC1_A_TSEC2=y +CONFIG_SICR_GPIO_A_GPIO=y +CONFIG_SICR_GPIO_B_GPIO=y +CONFIG_SICR_IEEE1588_A_GPIO=y +CONFIG_SICR_GTM_GPIO=y +CONFIG_SICR_ETSEC2_GPIO=y +CONFIG_SICR_GPIOSEL_IEEE1588=y +CONFIG_SICR_TMSOBI1_2_5_V=y +CONFIG_SICR_TMSOBI2_2_5_V=y CONFIG_CMD_IOLOOP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h index e825cfbd17..7ba44044f7 100644 --- a/include/configs/MPC8308RDB.h +++ b/include/configs/MPC8308RDB.h @@ -27,31 +27,6 @@ #define CONFIG_TSEC1 #define CONFIG_VSC7385_ENET -/* - * System IO Config - */ -#define CONFIG_SYS_SICRH (\ - SICRH_ESDHC_A_SD |\ - SICRH_ESDHC_B_SD |\ - SICRH_ESDHC_C_SD |\ - SICRH_GPIO_A_TSEC2 |\ - SICRH_GPIO_B_TSEC2_GTX_CLK125 |\ - SICRH_IEEE1588_A_GPIO |\ - SICRH_USB |\ - SICRH_GTM_GPIO |\ - SICRH_IEEE1588_B_GPIO |\ - SICRH_ETSEC2_CRS |\ - SICRH_GPIOSEL_1 |\ - SICRH_TMROBI_V3P3 |\ - SICRH_TSOBI1_V2P5 |\ - SICRH_TSOBI2_V2P5) /* 0x01b7d103 */ -#define CONFIG_SYS_SICRL (\ - SICRL_SPI_PF0 |\ - SICRL_UART_PF0 |\ - SICRL_IRQ_PF0 |\ - SICRL_I2C2_PF0 |\ - SICRL_ETSEC1_GTX_CLK125) /* 0x00000040 */ - /* * SERDES */ diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h index e8a4b7adf6..23e0da9624 100644 --- a/include/configs/hrcon.h +++ b/include/configs/hrcon.h @@ -15,31 +15,6 @@ #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR -/* - * System IO Config - */ -#define CONFIG_SYS_SICRH (\ - SICRH_ESDHC_A_SD |\ - SICRH_ESDHC_B_SD |\ - SICRH_ESDHC_C_SD |\ - SICRH_GPIO_A_GPIO |\ - SICRH_GPIO_B_GPIO |\ - SICRH_IEEE1588_A_GPIO |\ - SICRH_USB |\ - SICRH_GTM_GPIO |\ - SICRH_IEEE1588_B_GPIO |\ - SICRH_ETSEC2_GPIO |\ - SICRH_GPIOSEL_1 |\ - SICRH_TMROBI_V3P3 |\ - SICRH_TSOBI1_V2P5 |\ - SICRH_TSOBI2_V2P5) /* 0x0037f103 */ -#define CONFIG_SYS_SICRL (\ - SICRL_SPI_PF0 |\ - SICRL_UART_PF0 |\ - SICRL_IRQ_PF0 |\ - SICRL_I2C2_PF0 |\ - SICRL_ETSEC1_GTX_CLK125) /* 0x00000000 */ - /* * SERDES */ diff --git a/include/configs/mpc8308_p1m.h b/include/configs/mpc8308_p1m.h index 76846c43d0..d0eac0a2ef 100644 --- a/include/configs/mpc8308_p1m.h +++ b/include/configs/mpc8308_p1m.h @@ -21,31 +21,6 @@ #define CONFIG_TSEC1 #define CONFIG_TSEC2 -/* - * System IO Config - */ -#define CONFIG_SYS_SICRH (\ - SICRH_ESDHC_A_GPIO |\ - SICRH_ESDHC_B_GPIO |\ - SICRH_ESDHC_C_GTM |\ - SICRH_GPIO_A_TSEC2 |\ - SICRH_GPIO_B_TSEC2_TX_CLK |\ - SICRH_IEEE1588_A_GPIO |\ - SICRH_USB |\ - SICRH_GTM_GPIO |\ - SICRH_IEEE1588_B_GPIO |\ - SICRH_ETSEC2_CRS |\ - SICRH_GPIOSEL_1 |\ - SICRH_TMROBI_V3P3 |\ - SICRH_TSOBI1_V3P3 |\ - SICRH_TSOBI2_V3P3) /* 0xf577d100 */ -#define CONFIG_SYS_SICRL (\ - SICRL_SPI_PF0 |\ - SICRL_UART_PF0 |\ - SICRL_IRQ_PF0 |\ - SICRL_I2C2_PF0 |\ - SICRL_ETSEC1_TX_CLK) /* 0x00000000 */ - #define CONFIG_SYS_GPIO1_PRELIM /* GPIO Default input/output settings */ #define CONFIG_SYS_GPIO1_DIR 0x7AAF8C00 diff --git a/include/configs/strider.h b/include/configs/strider.h index fe2d89f2a6..8afd17d1b0 100644 --- a/include/configs/strider.h +++ b/include/configs/strider.h @@ -15,31 +15,6 @@ #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR -/* - * System IO Config - */ -#define CONFIG_SYS_SICRH (\ - SICRH_ESDHC_A_SD |\ - SICRH_ESDHC_B_SD |\ - SICRH_ESDHC_C_SD |\ - SICRH_GPIO_A_GPIO |\ - SICRH_GPIO_B_GPIO |\ - SICRH_IEEE1588_A_GPIO |\ - SICRH_USB |\ - SICRH_GTM_GPIO |\ - SICRH_IEEE1588_B_GPIO |\ - SICRH_ETSEC2_GPIO |\ - SICRH_GPIOSEL_1 |\ - SICRH_TMROBI_V3P3 |\ - SICRH_TSOBI1_V2P5 |\ - SICRH_TSOBI2_V2P5) /* 0x0037f103 */ -#define CONFIG_SYS_SICRL (\ - SICRL_SPI_PF0 |\ - SICRL_UART_PF0 |\ - SICRL_IRQ_PF0 |\ - SICRL_I2C2_PF0 |\ - SICRL_ETSEC1_TX_CLK) /* 0x00000000 */ - /* * SERDES */ From 73df96a38e693312bc2d5b565bc439f3b98e63ea Mon Sep 17 00:00:00 2001 From: Mario Six Date: Mon, 21 Jan 2019 09:18:12 +0100 Subject: [PATCH 49/86] mpc83xx: Migrate arbiter config to Kconfig Migrate the arbiter configuration to Kconfig. Signed-off-by: Mario Six --- arch/powerpc/cpu/mpc83xx/Kconfig | 1 + arch/powerpc/cpu/mpc83xx/arbiter/Kconfig | 139 +++++++++++++++++++++ arch/powerpc/cpu/mpc83xx/arbiter/arbiter.h | 28 +++++ arch/powerpc/cpu/mpc83xx/cpu_init.c | 29 +---- arch/powerpc/cpu/mpc83xx/spl_minimal.c | 8 +- configs/MPC8308RDB_defconfig | 2 + configs/MPC8313ERDB_33_defconfig | 2 + configs/MPC8313ERDB_66_defconfig | 2 + configs/MPC8313ERDB_NAND_33_defconfig | 2 + configs/MPC8313ERDB_NAND_66_defconfig | 2 + configs/MPC8315ERDB_defconfig | 2 + configs/MPC8323ERDB_defconfig | 2 + configs/MPC8349EMDS_PCI64_defconfig | 2 + configs/MPC8349EMDS_SDRAM_defconfig | 2 + configs/MPC8349EMDS_SLAVE_defconfig | 2 + configs/MPC8349EMDS_defconfig | 2 + configs/MPC8349ITXGP_defconfig | 2 + configs/MPC8349ITX_LOWBOOT_defconfig | 2 + configs/MPC8349ITX_defconfig | 2 + configs/MPC837XEMDS_HOST_defconfig | 2 + configs/MPC837XEMDS_SLAVE_defconfig | 2 + configs/MPC837XEMDS_defconfig | 2 + configs/MPC837XERDB_SLAVE_defconfig | 2 + configs/MPC837XERDB_defconfig | 2 + configs/hrcon_defconfig | 2 + configs/hrcon_dh_defconfig | 2 + configs/ids8313_defconfig | 2 + configs/kmcoge5ne_defconfig | 4 + configs/kmeter1_defconfig | 4 + configs/kmopti2_defconfig | 4 + configs/kmsupx5_defconfig | 4 + configs/kmtegr1_defconfig | 4 + configs/kmtepr2_defconfig | 4 + configs/kmvect1_defconfig | 4 + configs/mpc8308_p1m_defconfig | 2 + configs/strider_con_defconfig | 2 + configs/strider_con_dp_defconfig | 2 + configs/strider_cpu_defconfig | 2 + configs/strider_cpu_dp_defconfig | 2 + configs/suvd3_defconfig | 4 + configs/tuge1_defconfig | 4 + configs/tuxx1_defconfig | 4 + configs/ve8313_defconfig | 2 + include/configs/MPC8308RDB.h | 5 - include/configs/MPC8313ERDB_NAND.h | 3 - include/configs/MPC8313ERDB_NOR.h | 3 - include/configs/MPC8315ERDB.h | 5 - include/configs/MPC8323ERDB.h | 5 - include/configs/MPC8349EMDS.h | 2 - include/configs/MPC8349EMDS_SDRAM.h | 2 - include/configs/MPC8349ITX.h | 2 - include/configs/MPC837XEMDS.h | 4 - include/configs/MPC837XERDB.h | 4 - include/configs/hrcon.h | 5 - include/configs/ids8313.h | 3 - include/configs/kmcoge5ne.h | 8 -- include/configs/kmeter1.h | 8 -- include/configs/kmopti2.h | 8 -- include/configs/kmsupx5.h | 8 -- include/configs/kmtegr1.h | 8 -- include/configs/kmtepr2.h | 8 -- include/configs/kmvect1.h | 8 -- include/configs/mpc8308_p1m.h | 5 - include/configs/strider.h | 5 - include/configs/suvd3.h | 8 -- include/configs/tuge1.h | 8 -- include/configs/tuxx1.h | 8 -- include/configs/ve8313.h | 3 - scripts/config_whitelist.txt | 4 - 69 files changed, 269 insertions(+), 172 deletions(-) create mode 100644 arch/powerpc/cpu/mpc83xx/arbiter/Kconfig create mode 100644 arch/powerpc/cpu/mpc83xx/arbiter/arbiter.h diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index 9f7b3a2e01..8a3bb10466 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -295,6 +295,7 @@ source "arch/powerpc/cpu/mpc83xx/lblaw/Kconfig" source "arch/powerpc/cpu/mpc83xx/elbc/Kconfig" source "arch/powerpc/cpu/mpc83xx/hid/Kconfig" source "arch/powerpc/cpu/mpc83xx/sysio/Kconfig" +source "arch/powerpc/cpu/mpc83xx/arbiter/Kconfig" menu "Legacy options" diff --git a/arch/powerpc/cpu/mpc83xx/arbiter/Kconfig b/arch/powerpc/cpu/mpc83xx/arbiter/Kconfig new file mode 100644 index 0000000000..f562476da8 --- /dev/null +++ b/arch/powerpc/cpu/mpc83xx/arbiter/Kconfig @@ -0,0 +1,139 @@ +menu "Arbiter" + +choice + prompt "Pipeline depth" + +config ACR_PIPE_DEP_UNSET + bool "Don't set value" + +config ACR_PIPE_DEP_1 + bool "1" + +config ACR_PIPE_DEP_2 + bool "2" + +config ACR_PIPE_DEP_3 + bool "3" + +config ACR_PIPE_DEP_4 + bool "4" + +endchoice + +choice + prompt "Repeat count" + +config ACR_RPTCNT_UNSET + bool "Don't set value" + +config ACR_RPTCNT_1 + bool "1" + +config ACR_RPTCNT_2 + bool "2" + +config ACR_RPTCNT_3 + bool "3" + +config ACR_RPTCNT_4 + bool "4" + +config ACR_RPTCNT_5 + bool "5" + +config ACR_RPTCNT_6 + bool "6" + +config ACR_RPTCNT_7 + bool "7" + +config ACR_RPTCNT_8 + bool "8" + +endchoice + +choice + prompt "Address parking" + +config ACR_APARK_UNSET + bool "Don't set value" + +config ACR_APARK_MASTER + bool "Park to master" + +config ACR_APARK_LAST + bool "Park to last owner" + +config ACR_APARK_DISABLE + bool "Disabled" + +endchoice + +choice + prompt "Parking master" + +config ACR_PARKM_UNSET + bool "Don't set value" + +config ACR_PARKM_E300 + bool "e300 core" + +config ACR_PARKM_TSEC_1_2 + bool "TSEC1, TSEC2" + +config ACR_PARKM_USB_I2C1_BOOT + bool "USB/I2C1_BOOT" + +config ACR_PARKM_DMA_ESDHC_USB + bool "DMA, ESDHC, USB" + +config ACR_PARKM_PEX + bool "PCI Express" + +if MPC83XX_QUICC_ENGINE + +config ACR_PARKM_ENC_CORE + bool "Encryption core" + +endif + +endchoice + +config ACR_PIPE_DEP + hex + default 0x0 if ACR_PIPE_DEP_UNSET + default 0x0 if ACR_PIPE_DEP_1 + default 0x10000 if ACR_PIPE_DEP_2 + default 0x20000 if ACR_PIPE_DEP_3 + default 0x30000 if ACR_PIPE_DEP_4 + +config ACR_RPTCNT + hex + default 0x0 if ACR_RPTCNT_UNSET + default 0x0 if ACR_RPTCNT_1 + default 0x100 if ACR_RPTCNT_2 + default 0x200 if ACR_RPTCNT_3 + default 0x300 if ACR_RPTCNT_4 + default 0x400 if ACR_RPTCNT_5 + default 0x500 if ACR_RPTCNT_6 + default 0x600 if ACR_RPTCNT_7 + default 0x700 if ACR_RPTCNT_8 + +config ACR_APARK + hex + default 0x0 if ACR_APARK_UNSET + default 0x0 if ACR_APARK_MASTER + default 0x10 if ACR_APARK_LAST + default 0x20 if ACR_APARK_DISABLE + +config ACR_PARKM + hex + default 0x0 if ACR_PARKM_UNSET + default 0x0 if ACR_PARKM_E300 + default 0x2 if ACR_PARKM_TSEC_1_2 + default 0x3 if ACR_PARKM_USB_I2C1_BOOT + default 0x4 if ACR_PARKM_DMA_ESDHC_USB + default 0x5 if ACR_PARKM_PEX + default 0x5 if ACR_PARKM_ENC_CORE + +endmenu diff --git a/arch/powerpc/cpu/mpc83xx/arbiter/arbiter.h b/arch/powerpc/cpu/mpc83xx/arbiter/arbiter.h new file mode 100644 index 0000000000..10a47e4987 --- /dev/null +++ b/arch/powerpc/cpu/mpc83xx/arbiter/arbiter.h @@ -0,0 +1,28 @@ + const __be32 acr_mask = +#ifndef CONFIG_ACR_PIPE_DEP_UNSET + ACR_PIPE_DEP | +#endif +#ifndef CONFIG_ACR_RPTCNT_UNSET + ACR_RPTCNT | +#endif +#ifndef CONFIG_ACR_APARK_UNSET + ACR_APARK | +#endif +#ifndef CONFIG_ACR_PARKM_UNSET + ACR_PARKM | +#endif + 0; + const __be32 acr_val = +#ifndef CONFIG_ACR_PIPE_DEP_UNSET + CONFIG_ACR_PIPE_DEP | +#endif +#ifndef CONFIG_ACR_RPTCNT_UNSET + CONFIG_ACR_RPTCNT | +#endif +#ifndef CONFIG_ACR_APARK_UNSET + CONFIG_ACR_APARK | +#endif +#ifndef CONFIG_ACR_PARKM_UNSET + CONFIG_ACR_PARKM | +#endif + 0; diff --git a/arch/powerpc/cpu/mpc83xx/cpu_init.c b/arch/powerpc/cpu/mpc83xx/cpu_init.c index 3df01ee1ca..77502567a7 100644 --- a/arch/powerpc/cpu/mpc83xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc83xx/cpu_init.c @@ -15,6 +15,7 @@ #include "lblaw/lblaw.h" #include "elbc/elbc.h" #include "sysio/sysio.h" +#include "arbiter/arbiter.h" DECLARE_GLOBAL_DATA_PTR; @@ -51,34 +52,6 @@ static void config_qe_ioports(void) */ void cpu_init_f (volatile immap_t * im) { - __be32 acr_mask = -#ifdef CONFIG_SYS_ACR_PIPE_DEP /* Arbiter pipeline depth */ - ACR_PIPE_DEP | -#endif -#ifdef CONFIG_SYS_ACR_RPTCNT /* Arbiter repeat count */ - ACR_RPTCNT | -#endif -#ifdef CONFIG_SYS_ACR_APARK /* Arbiter address parking mode */ - ACR_APARK | -#endif -#ifdef CONFIG_SYS_ACR_PARKM /* Arbiter parking master */ - ACR_PARKM | -#endif - 0; - __be32 acr_val = -#ifdef CONFIG_SYS_ACR_PIPE_DEP /* Arbiter pipeline depth */ - (CONFIG_SYS_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT) | -#endif -#ifdef CONFIG_SYS_ACR_RPTCNT /* Arbiter repeat count */ - (CONFIG_SYS_ACR_RPTCNT << ACR_RPTCNT_SHIFT) | -#endif -#ifdef CONFIG_SYS_ACR_APARK /* Arbiter address parking mode */ - (CONFIG_SYS_ACR_APARK << ACR_APARK_SHIFT) | -#endif -#ifdef CONFIG_SYS_ACR_PARKM /* Arbiter parking master */ - (CONFIG_SYS_ACR_PARKM << ACR_PARKM_SHIFT) | -#endif - 0; __be32 spcr_mask = #ifdef CONFIG_SYS_SPCR_OPT /* Optimize transactions between CSB and other dev */ SPCR_OPT | diff --git a/arch/powerpc/cpu/mpc83xx/spl_minimal.c b/arch/powerpc/cpu/mpc83xx/spl_minimal.c index b4e2fb1119..133f7abc31 100644 --- a/arch/powerpc/cpu/mpc83xx/spl_minimal.c +++ b/arch/powerpc/cpu/mpc83xx/spl_minimal.c @@ -27,16 +27,16 @@ void cpu_init_f (volatile immap_t * im) /* system performance tweaking */ -#ifdef CONFIG_SYS_ACR_PIPE_DEP +#ifndef CONFIG_ACR_PIPE_DEP_UNSET /* Arbiter pipeline depth */ im->arbiter.acr = (im->arbiter.acr & ~ACR_PIPE_DEP) | - (CONFIG_SYS_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT); + CONFIG_ACR_PIPE_DEP; #endif -#ifdef CONFIG_SYS_ACR_RPTCNT +#ifndef CONFIG_ACR_RPTCNT_UNSET /* Arbiter repeat count */ im->arbiter.acr = (im->arbiter.acr & ~(ACR_RPTCNT)) | - (CONFIG_SYS_ACR_RPTCNT << ACR_RPTCNT_SHIFT); + CONFIG_ACR_RPTCNT; #endif #ifdef CONFIG_SYS_SPCR_OPT diff --git a/configs/MPC8308RDB_defconfig b/configs/MPC8308RDB_defconfig index 9be515567c..00feaccc30 100644 --- a/configs/MPC8308RDB_defconfig +++ b/configs/MPC8308RDB_defconfig @@ -70,6 +70,8 @@ CONFIG_SICR_GTM_GPIO=y CONFIG_SICR_GPIOSEL_IEEE1588=y CONFIG_SICR_TMSOBI1_2_5_V=y CONFIG_SICR_TMSOBI2_2_5_V=y +CONFIG_ACR_PIPE_DEP_4=y +CONFIG_ACR_RPTCNT_4=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/MPC8313ERDB_33_defconfig b/configs/MPC8313ERDB_33_defconfig index 732beab2e1..b368aee966 100644 --- a/configs/MPC8313ERDB_33_defconfig +++ b/configs/MPC8313ERDB_33_defconfig @@ -77,6 +77,8 @@ CONFIG_HID0_FINAL_EMCP=y CONFIG_HID0_FINAL_DPM=y CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y +CONFIG_ACR_PIPE_DEP_4=y +CONFIG_ACR_RPTCNT_4=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SYS_33MHZ" diff --git a/configs/MPC8313ERDB_66_defconfig b/configs/MPC8313ERDB_66_defconfig index f2ec6cc7db..ddf9060df4 100644 --- a/configs/MPC8313ERDB_66_defconfig +++ b/configs/MPC8313ERDB_66_defconfig @@ -76,6 +76,8 @@ CONFIG_HID0_FINAL_EMCP=y CONFIG_HID0_FINAL_DPM=y CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y +CONFIG_ACR_PIPE_DEP_4=y +CONFIG_ACR_RPTCNT_4=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SYS_66MHZ" diff --git a/configs/MPC8313ERDB_NAND_33_defconfig b/configs/MPC8313ERDB_NAND_33_defconfig index 95d8ff438e..7c16364d3f 100644 --- a/configs/MPC8313ERDB_NAND_33_defconfig +++ b/configs/MPC8313ERDB_NAND_33_defconfig @@ -79,6 +79,8 @@ CONFIG_HID0_FINAL_EMCP=y CONFIG_HID0_FINAL_DPM=y CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y +CONFIG_ACR_PIPE_DEP_4=y +CONFIG_ACR_RPTCNT_4=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SYS_33MHZ" diff --git a/configs/MPC8313ERDB_NAND_66_defconfig b/configs/MPC8313ERDB_NAND_66_defconfig index c51713ab90..ab8e315e0d 100644 --- a/configs/MPC8313ERDB_NAND_66_defconfig +++ b/configs/MPC8313ERDB_NAND_66_defconfig @@ -78,6 +78,8 @@ CONFIG_HID0_FINAL_EMCP=y CONFIG_HID0_FINAL_DPM=y CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y +CONFIG_ACR_PIPE_DEP_4=y +CONFIG_ACR_RPTCNT_4=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SYS_66MHZ" diff --git a/configs/MPC8315ERDB_defconfig b/configs/MPC8315ERDB_defconfig index d19e797731..2263b9cb51 100644 --- a/configs/MPC8315ERDB_defconfig +++ b/configs/MPC8315ERDB_defconfig @@ -80,6 +80,8 @@ CONFIG_HID0_FINAL_EMCP=y CONFIG_HID0_FINAL_DPM=y CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y +CONFIG_ACR_PIPE_DEP_4=y +CONFIG_ACR_RPTCNT_4=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC8323ERDB_defconfig b/configs/MPC8323ERDB_defconfig index 19425abb1d..b52d1fd62a 100644 --- a/configs/MPC8323ERDB_defconfig +++ b/configs/MPC8323ERDB_defconfig @@ -73,6 +73,8 @@ CONFIG_LBLAW0_LENGTH_32_MBYTES=y CONFIG_HID0_FINAL_EMCP=y CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y +CONFIG_ACR_PIPE_DEP_4=y +CONFIG_ACR_RPTCNT_4=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC8349EMDS_PCI64_defconfig b/configs/MPC8349EMDS_PCI64_defconfig index fef4f34357..9108275f3c 100644 --- a/configs/MPC8349EMDS_PCI64_defconfig +++ b/configs/MPC8349EMDS_PCI64_defconfig @@ -56,6 +56,8 @@ CONFIG_LBLAW1_LENGTH_32_KBYTES=y CONFIG_HID0_FINAL_EMCP=y CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y +CONFIG_ACR_PIPE_DEP_4=y +CONFIG_ACR_RPTCNT_4=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC8349EMDS_SDRAM_defconfig b/configs/MPC8349EMDS_SDRAM_defconfig index d0774431a3..8589470b2e 100644 --- a/configs/MPC8349EMDS_SDRAM_defconfig +++ b/configs/MPC8349EMDS_SDRAM_defconfig @@ -60,6 +60,8 @@ CONFIG_LBLAW2_LENGTH_64_MBYTES=y CONFIG_HID0_FINAL_EMCP=y CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y +CONFIG_ACR_PIPE_DEP_4=y +CONFIG_ACR_RPTCNT_4=y CONFIG_ELBC_BR0_OR0=y CONFIG_BR0_OR0_NAME="FLASH" CONFIG_BR0_OR0_BASE=0xFE000000 diff --git a/configs/MPC8349EMDS_SLAVE_defconfig b/configs/MPC8349EMDS_SLAVE_defconfig index 429d273e4e..7454dd64f1 100644 --- a/configs/MPC8349EMDS_SLAVE_defconfig +++ b/configs/MPC8349EMDS_SLAVE_defconfig @@ -54,6 +54,8 @@ CONFIG_LBLAW1_LENGTH_32_KBYTES=y CONFIG_HID0_FINAL_EMCP=y CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y +CONFIG_ACR_PIPE_DEP_4=y +CONFIG_ACR_RPTCNT_4=y CONFIG_PCI_ONE_PCI1=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/configs/MPC8349EMDS_defconfig b/configs/MPC8349EMDS_defconfig index 8c09cd90ee..328c3aa567 100644 --- a/configs/MPC8349EMDS_defconfig +++ b/configs/MPC8349EMDS_defconfig @@ -56,6 +56,8 @@ CONFIG_LBLAW1_LENGTH_32_KBYTES=y CONFIG_HID0_FINAL_EMCP=y CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y +CONFIG_ACR_PIPE_DEP_4=y +CONFIG_ACR_RPTCNT_4=y CONFIG_PCI_ONE_PCI1=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/configs/MPC8349ITXGP_defconfig b/configs/MPC8349ITXGP_defconfig index c32c8f0d74..fa121d721a 100644 --- a/configs/MPC8349ITXGP_defconfig +++ b/configs/MPC8349ITXGP_defconfig @@ -99,6 +99,8 @@ CONFIG_LBLAW3_NAME="CF" CONFIG_LBLAW3_LENGTH_64_KBYTES=y CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y +CONFIG_ACR_PIPE_DEP_4=y +CONFIG_ACR_RPTCNT_4=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFE000000" diff --git a/configs/MPC8349ITX_LOWBOOT_defconfig b/configs/MPC8349ITX_LOWBOOT_defconfig index 4d55fd0088..0a79d1e625 100644 --- a/configs/MPC8349ITX_LOWBOOT_defconfig +++ b/configs/MPC8349ITX_LOWBOOT_defconfig @@ -99,6 +99,8 @@ CONFIG_LBLAW3_NAME="CF" CONFIG_LBLAW3_LENGTH_64_KBYTES=y CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y +CONFIG_ACR_PIPE_DEP_4=y +CONFIG_ACR_RPTCNT_4=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC8349ITX_defconfig b/configs/MPC8349ITX_defconfig index 697567f53e..e7461072ed 100644 --- a/configs/MPC8349ITX_defconfig +++ b/configs/MPC8349ITX_defconfig @@ -98,6 +98,8 @@ CONFIG_LBLAW3_NAME="CF" CONFIG_LBLAW3_LENGTH_64_KBYTES=y CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y +CONFIG_ACR_PIPE_DEP_4=y +CONFIG_ACR_RPTCNT_4=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC837XEMDS_HOST_defconfig b/configs/MPC837XEMDS_HOST_defconfig index 45b2ee74f4..0df5bdb2c5 100644 --- a/configs/MPC837XEMDS_HOST_defconfig +++ b/configs/MPC837XEMDS_HOST_defconfig @@ -104,6 +104,8 @@ CONFIG_LBLAW3_LENGTH_32_KBYTES=y CONFIG_HID0_FINAL_EMCP=y CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y +CONFIG_ACR_PIPE_DEP_4=y +CONFIG_ACR_RPTCNT_4=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC837XEMDS_SLAVE_defconfig b/configs/MPC837XEMDS_SLAVE_defconfig index 5d5811b85a..99f206e719 100644 --- a/configs/MPC837XEMDS_SLAVE_defconfig +++ b/configs/MPC837XEMDS_SLAVE_defconfig @@ -64,6 +64,8 @@ CONFIG_LBLAW3_LENGTH_32_KBYTES=y CONFIG_HID0_FINAL_EMCP=y CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y +CONFIG_ACR_PIPE_DEP_4=y +CONFIG_ACR_RPTCNT_4=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PCISLAVE" diff --git a/configs/MPC837XEMDS_defconfig b/configs/MPC837XEMDS_defconfig index 70f9df7e76..98dc6ca784 100644 --- a/configs/MPC837XEMDS_defconfig +++ b/configs/MPC837XEMDS_defconfig @@ -84,6 +84,8 @@ CONFIG_LBLAW3_LENGTH_32_KBYTES=y CONFIG_HID0_FINAL_EMCP=y CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y +CONFIG_ACR_PIPE_DEP_4=y +CONFIG_ACR_RPTCNT_4=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC837XERDB_SLAVE_defconfig b/configs/MPC837XERDB_SLAVE_defconfig index 1b8f33ab01..11a33d982f 100644 --- a/configs/MPC837XERDB_SLAVE_defconfig +++ b/configs/MPC837XERDB_SLAVE_defconfig @@ -64,6 +64,8 @@ CONFIG_LBLAW2_LENGTH_128_KBYTES=y CONFIG_HID0_FINAL_EMCP=y CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y +CONFIG_ACR_PIPE_DEP_4=y +CONFIG_ACR_RPTCNT_4=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PCISLAVE,PCIE" diff --git a/configs/MPC837XERDB_defconfig b/configs/MPC837XERDB_defconfig index 40eaf93ac5..d43b364910 100644 --- a/configs/MPC837XERDB_defconfig +++ b/configs/MPC837XERDB_defconfig @@ -104,6 +104,8 @@ CONFIG_LBLAW2_LENGTH_128_KBYTES=y CONFIG_HID0_FINAL_EMCP=y CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y +CONFIG_ACR_PIPE_DEP_4=y +CONFIG_ACR_RPTCNT_4=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PCIE" diff --git a/configs/hrcon_defconfig b/configs/hrcon_defconfig index 3442c9c797..3dad033be0 100644 --- a/configs/hrcon_defconfig +++ b/configs/hrcon_defconfig @@ -67,6 +67,8 @@ CONFIG_SICR_ETSEC2_GPIO=y CONFIG_SICR_GPIOSEL_IEEE1588=y CONFIG_SICR_TMSOBI1_2_5_V=y CONFIG_SICR_TMSOBI2_2_5_V=y +CONFIG_ACR_PIPE_DEP_4=y +CONFIG_ACR_RPTCNT_4=y CONFIG_CMD_IOLOOP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/hrcon_dh_defconfig b/configs/hrcon_dh_defconfig index 5de0eaa4d0..4fb7cb5ffd 100644 --- a/configs/hrcon_dh_defconfig +++ b/configs/hrcon_dh_defconfig @@ -67,6 +67,8 @@ CONFIG_SICR_ETSEC2_GPIO=y CONFIG_SICR_GPIOSEL_IEEE1588=y CONFIG_SICR_TMSOBI1_2_5_V=y CONFIG_SICR_TMSOBI2_2_5_V=y +CONFIG_ACR_PIPE_DEP_4=y +CONFIG_ACR_RPTCNT_4=y CONFIG_CMD_IOLOOP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/ids8313_defconfig b/configs/ids8313_defconfig index 9c16a1231c..f835868209 100644 --- a/configs/ids8313_defconfig +++ b/configs/ids8313_defconfig @@ -74,6 +74,8 @@ CONFIG_LBLAW3_LENGTH_32_KBYTES=y CONFIG_HID0_FINAL_EMCP=y CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y +CONFIG_ACR_PIPE_DEP_4=y +CONFIG_ACR_RPTCNT_4=y CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_IMAGE_FORMAT_LEGACY=y diff --git a/configs/kmcoge5ne_defconfig b/configs/kmcoge5ne_defconfig index 30af114c8c..7751e5a898 100644 --- a/configs/kmcoge5ne_defconfig +++ b/configs/kmcoge5ne_defconfig @@ -107,6 +107,10 @@ CONFIG_LBLAW3_LENGTH_512_MBYTES=y CONFIG_HID0_FINAL_EMCP=y CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y +CONFIG_ACR_PIPE_DEP_4=y +CONFIG_ACR_RPTCNT_4=y +CONFIG_ACR_APARK_MASTER=y +CONFIG_ACR_PARKM_USB_I2C1_BOOT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_MISC_INIT_R=y diff --git a/configs/kmeter1_defconfig b/configs/kmeter1_defconfig index e673d6c4db..2bb3158873 100644 --- a/configs/kmeter1_defconfig +++ b/configs/kmeter1_defconfig @@ -80,6 +80,10 @@ CONFIG_LBLAW3_LENGTH_512_MBYTES=y CONFIG_HID0_FINAL_EMCP=y CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y +CONFIG_ACR_PIPE_DEP_4=y +CONFIG_ACR_RPTCNT_4=y +CONFIG_ACR_APARK_MASTER=y +CONFIG_ACR_PARKM_USB_I2C1_BOOT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_MISC_INIT_R=y diff --git a/configs/kmopti2_defconfig b/configs/kmopti2_defconfig index fb4bd41748..5eb5c939eb 100644 --- a/configs/kmopti2_defconfig +++ b/configs/kmopti2_defconfig @@ -95,6 +95,10 @@ CONFIG_LBLAW3_LENGTH_256_MBYTES=y CONFIG_HID0_FINAL_EMCP=y CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y +CONFIG_ACR_PIPE_DEP_4=y +CONFIG_ACR_RPTCNT_4=y +CONFIG_ACR_APARK_MASTER=y +CONFIG_ACR_PARKM_USB_I2C1_BOOT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_MISC_INIT_R=y diff --git a/configs/kmsupx5_defconfig b/configs/kmsupx5_defconfig index 8f5e8aecec..0ad8801df9 100644 --- a/configs/kmsupx5_defconfig +++ b/configs/kmsupx5_defconfig @@ -81,6 +81,10 @@ CONFIG_LBLAW2_LENGTH_256_MBYTES=y CONFIG_HID0_FINAL_EMCP=y CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y +CONFIG_ACR_PIPE_DEP_4=y +CONFIG_ACR_RPTCNT_4=y +CONFIG_ACR_APARK_MASTER=y +CONFIG_ACR_PARKM_USB_I2C1_BOOT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_MISC_INIT_R=y diff --git a/configs/kmtegr1_defconfig b/configs/kmtegr1_defconfig index e3d721e093..8dfc4438ad 100644 --- a/configs/kmtegr1_defconfig +++ b/configs/kmtegr1_defconfig @@ -82,6 +82,10 @@ CONFIG_LBLAW3_LENGTH_256_MBYTES=y CONFIG_HID0_FINAL_EMCP=y CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y +CONFIG_ACR_PIPE_DEP_4=y +CONFIG_ACR_RPTCNT_4=y +CONFIG_ACR_APARK_MASTER=y +CONFIG_ACR_PARKM_USB_I2C1_BOOT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="KMTEGR1" diff --git a/configs/kmtepr2_defconfig b/configs/kmtepr2_defconfig index 749b38586f..1a84ff5e0b 100644 --- a/configs/kmtepr2_defconfig +++ b/configs/kmtepr2_defconfig @@ -95,6 +95,10 @@ CONFIG_LBLAW3_LENGTH_256_MBYTES=y CONFIG_HID0_FINAL_EMCP=y CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y +CONFIG_ACR_PIPE_DEP_4=y +CONFIG_ACR_RPTCNT_4=y +CONFIG_ACR_APARK_MASTER=y +CONFIG_ACR_PARKM_USB_I2C1_BOOT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_MISC_INIT_R=y diff --git a/configs/kmvect1_defconfig b/configs/kmvect1_defconfig index e8bb547b6f..a746f195e6 100644 --- a/configs/kmvect1_defconfig +++ b/configs/kmvect1_defconfig @@ -96,6 +96,10 @@ CONFIG_LBLAW3_LENGTH_256_MBYTES=y CONFIG_HID0_FINAL_EMCP=y CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y +CONFIG_ACR_PIPE_DEP_4=y +CONFIG_ACR_RPTCNT_4=y +CONFIG_ACR_APARK_MASTER=y +CONFIG_ACR_PARKM_USB_I2C1_BOOT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="KMVECT1" diff --git a/configs/mpc8308_p1m_defconfig b/configs/mpc8308_p1m_defconfig index 26601ff0a6..f73084c0e1 100644 --- a/configs/mpc8308_p1m_defconfig +++ b/configs/mpc8308_p1m_defconfig @@ -68,6 +68,8 @@ CONFIG_SICR_GPIO_B_TSEC2=y CONFIG_SICR_IEEE1588_A_GPIO=y CONFIG_SICR_GTM_GPIO=y CONFIG_SICR_GPIOSEL_IEEE1588=y +CONFIG_ACR_PIPE_DEP_4=y +CONFIG_ACR_RPTCNT_4=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=5 diff --git a/configs/strider_con_defconfig b/configs/strider_con_defconfig index 1244652c79..722f25d63e 100644 --- a/configs/strider_con_defconfig +++ b/configs/strider_con_defconfig @@ -66,6 +66,8 @@ CONFIG_SICR_ETSEC2_GPIO=y CONFIG_SICR_GPIOSEL_IEEE1588=y CONFIG_SICR_TMSOBI1_2_5_V=y CONFIG_SICR_TMSOBI2_2_5_V=y +CONFIG_ACR_PIPE_DEP_4=y +CONFIG_ACR_RPTCNT_4=y CONFIG_CMD_IOLOOP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/strider_con_dp_defconfig b/configs/strider_con_dp_defconfig index 05040b056e..dd3c83d4fc 100644 --- a/configs/strider_con_dp_defconfig +++ b/configs/strider_con_dp_defconfig @@ -66,6 +66,8 @@ CONFIG_SICR_ETSEC2_GPIO=y CONFIG_SICR_GPIOSEL_IEEE1588=y CONFIG_SICR_TMSOBI1_2_5_V=y CONFIG_SICR_TMSOBI2_2_5_V=y +CONFIG_ACR_PIPE_DEP_4=y +CONFIG_ACR_RPTCNT_4=y CONFIG_CMD_IOLOOP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/strider_cpu_defconfig b/configs/strider_cpu_defconfig index fbae6546d7..1a35132987 100644 --- a/configs/strider_cpu_defconfig +++ b/configs/strider_cpu_defconfig @@ -66,6 +66,8 @@ CONFIG_SICR_ETSEC2_GPIO=y CONFIG_SICR_GPIOSEL_IEEE1588=y CONFIG_SICR_TMSOBI1_2_5_V=y CONFIG_SICR_TMSOBI2_2_5_V=y +CONFIG_ACR_PIPE_DEP_4=y +CONFIG_ACR_RPTCNT_4=y CONFIG_CMD_IOLOOP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/strider_cpu_dp_defconfig b/configs/strider_cpu_dp_defconfig index e3405707e5..79fdc140e5 100644 --- a/configs/strider_cpu_dp_defconfig +++ b/configs/strider_cpu_dp_defconfig @@ -66,6 +66,8 @@ CONFIG_SICR_ETSEC2_GPIO=y CONFIG_SICR_GPIOSEL_IEEE1588=y CONFIG_SICR_TMSOBI1_2_5_V=y CONFIG_SICR_TMSOBI2_2_5_V=y +CONFIG_ACR_PIPE_DEP_4=y +CONFIG_ACR_RPTCNT_4=y CONFIG_CMD_IOLOOP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/suvd3_defconfig b/configs/suvd3_defconfig index fcd5741092..28e386db24 100644 --- a/configs/suvd3_defconfig +++ b/configs/suvd3_defconfig @@ -95,6 +95,10 @@ CONFIG_LBLAW3_LENGTH_256_MBYTES=y CONFIG_HID0_FINAL_EMCP=y CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y +CONFIG_ACR_PIPE_DEP_4=y +CONFIG_ACR_RPTCNT_4=y +CONFIG_ACR_APARK_MASTER=y +CONFIG_ACR_PARKM_USB_I2C1_BOOT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SUVD3" diff --git a/configs/tuge1_defconfig b/configs/tuge1_defconfig index 5f7f2289f1..fb18a46ec6 100644 --- a/configs/tuge1_defconfig +++ b/configs/tuge1_defconfig @@ -81,6 +81,10 @@ CONFIG_LBLAW2_LENGTH_256_MBYTES=y CONFIG_HID0_FINAL_EMCP=y CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y +CONFIG_ACR_PIPE_DEP_4=y +CONFIG_ACR_RPTCNT_4=y +CONFIG_ACR_APARK_MASTER=y +CONFIG_ACR_PARKM_USB_I2C1_BOOT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_MISC_INIT_R=y diff --git a/configs/tuxx1_defconfig b/configs/tuxx1_defconfig index 600c6f36e0..a034f302b2 100644 --- a/configs/tuxx1_defconfig +++ b/configs/tuxx1_defconfig @@ -95,6 +95,10 @@ CONFIG_LBLAW3_LENGTH_256_MBYTES=y CONFIG_HID0_FINAL_EMCP=y CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y +CONFIG_ACR_PIPE_DEP_4=y +CONFIG_ACR_RPTCNT_4=y +CONFIG_ACR_APARK_MASTER=y +CONFIG_ACR_PARKM_USB_I2C1_BOOT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_MISC_INIT_R=y diff --git a/configs/ve8313_defconfig b/configs/ve8313_defconfig index 42e0098a1c..79f6430f91 100644 --- a/configs/ve8313_defconfig +++ b/configs/ve8313_defconfig @@ -77,6 +77,8 @@ CONFIG_LBLAW1_LENGTH_32_KBYTES=y CONFIG_HID0_FINAL_EMCP=y CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y +CONFIG_ACR_PIPE_DEP_4=y +CONFIG_ACR_RPTCNT_4=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h index 7ba44044f7..60c6b920f9 100644 --- a/include/configs/MPC8308RDB.h +++ b/include/configs/MPC8308RDB.h @@ -33,11 +33,6 @@ #define CONFIG_FSL_SERDES #define CONFIG_FSL_SERDES1 0xe3000 -/* - * Arbiter Setup - */ -#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */ -#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */ #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */ /* diff --git a/include/configs/MPC8313ERDB_NAND.h b/include/configs/MPC8313ERDB_NAND.h index e23df14ec1..aaf92fe37a 100644 --- a/include/configs/MPC8313ERDB_NAND.h +++ b/include/configs/MPC8313ERDB_NAND.h @@ -67,9 +67,6 @@ */ #define CONFIG_SYS_8313ERDB_BROKEN_PMC 1 -#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ -#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ - /* * Device configurations */ diff --git a/include/configs/MPC8313ERDB_NOR.h b/include/configs/MPC8313ERDB_NOR.h index 17cd8adc85..608565a139 100644 --- a/include/configs/MPC8313ERDB_NOR.h +++ b/include/configs/MPC8313ERDB_NOR.h @@ -39,9 +39,6 @@ */ #define CONFIG_SYS_8313ERDB_BROKEN_PMC 1 -#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ -#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ - /* * Device configurations */ diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index fbba2fbb50..9531be3072 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -31,11 +31,6 @@ #define CONFIG_HWCONFIG -/* - * Arbiter Setup - */ -#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */ -#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */ #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */ /* diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index b528c2901b..23496518b3 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -20,11 +20,6 @@ */ #define CONFIG_SYS_SICRL 0x00000000 -/* - * System performance - */ -#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ -#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ /* (0-1) Optimize transactions between CSB and the SEC and QUICC Engine block */ #define CONFIG_SYS_SPCR_OPT 1 diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 14ebc8ead3..51c47a8221 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -328,8 +328,6 @@ /* * System performance */ -#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ -#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ #define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */ #define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */ #define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */ diff --git a/include/configs/MPC8349EMDS_SDRAM.h b/include/configs/MPC8349EMDS_SDRAM.h index 67f3a9bd65..35210ccfd2 100644 --- a/include/configs/MPC8349EMDS_SDRAM.h +++ b/include/configs/MPC8349EMDS_SDRAM.h @@ -383,8 +383,6 @@ /* * System performance */ -#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ -#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ #define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */ #define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */ #define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */ diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index eef1bdec63..1c8574a40f 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -403,8 +403,6 @@ boards, we say we have two, but don't display a message if we find only one. */ /* * System performance */ -#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ -#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ #define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */ #define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */ #define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */ diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index c1973703c4..d8a02b8e06 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -12,10 +12,6 @@ */ #define CONFIG_E300 1 /* E300 family */ -/* Arbiter Configuration Register */ -#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */ -#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */ - /* System Priority Control Register */ #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC1/2 emergency has highest priority */ diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index e8173da323..6fa57ebee4 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -23,10 +23,6 @@ /* System performance - define the value i.e. CONFIG_SYS_XXX */ -/* Arbiter Configuration Register */ -#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ -#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ - /* System Priority Control Regsiter */ #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC1&2 emergency priority (0-3) */ diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h index 23e0da9624..76b28e07f4 100644 --- a/include/configs/hrcon.h +++ b/include/configs/hrcon.h @@ -21,11 +21,6 @@ #define CONFIG_FSL_SERDES #define CONFIG_FSL_SERDES1 0xe3000 -/* - * Arbiter Setup - */ -#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */ -#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */ #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */ /* diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h index b4acee058c..bd8f786a58 100644 --- a/include/configs/ids8313.h +++ b/include/configs/ids8313.h @@ -20,9 +20,6 @@ #define CONFIG_BOOT_RETRY_MIN 30 #define CONFIG_RESET_TO_RETRY -#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ -#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ - #define CONFIG_SYS_SICRH 0x00000000 #define CONFIG_SYS_SICRL (SICRL_LBC | SICRL_SPI_D) diff --git a/include/configs/kmcoge5ne.h b/include/configs/kmcoge5ne.h index 8e09160f92..08185894b8 100644 --- a/include/configs/kmcoge5ne.h +++ b/include/configs/kmcoge5ne.h @@ -40,14 +40,6 @@ #define CONFIG_SYS_CLK_FREQ 66000000 #define CONFIG_83XX_PCICLK 66000000 -/* - * Bus Arbitration Configuration Register (ACR) - */ -#define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */ -#define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */ -#define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */ -#define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */ - /* * DDR Setup */ diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h index 48a6172349..e0c3065ac6 100644 --- a/include/configs/kmeter1.h +++ b/include/configs/kmeter1.h @@ -25,14 +25,6 @@ #include "km/keymile-common.h" #include "km/km-powerpc.h" -/* - * Bus Arbitration Configuration Register (ACR) - */ -#define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */ -#define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */ -#define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */ -#define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */ - /* * DDR Setup */ diff --git a/include/configs/kmopti2.h b/include/configs/kmopti2.h index e34f26e55d..c2f4188a22 100644 --- a/include/configs/kmopti2.h +++ b/include/configs/kmopti2.h @@ -45,14 +45,6 @@ #define CONFIG_SYS_CLK_FREQ 66000000 #define CONFIG_83XX_PCICLK 66000000 -/* - * Bus Arbitration Configuration Register (ACR) - */ -#define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */ -#define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */ -#define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */ -#define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */ - /* * DDR Setup */ diff --git a/include/configs/kmsupx5.h b/include/configs/kmsupx5.h index 96e10325f0..b1ba474e78 100644 --- a/include/configs/kmsupx5.h +++ b/include/configs/kmsupx5.h @@ -45,14 +45,6 @@ #define CONFIG_SYS_CLK_FREQ 66000000 #define CONFIG_83XX_PCICLK 66000000 -/* - * Bus Arbitration Configuration Register (ACR) - */ -#define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */ -#define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */ -#define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */ -#define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */ - /* * DDR Setup */ diff --git a/include/configs/kmtegr1.h b/include/configs/kmtegr1.h index 4b407af036..d3f7c2c4d3 100644 --- a/include/configs/kmtegr1.h +++ b/include/configs/kmtegr1.h @@ -52,14 +52,6 @@ #define CONFIG_SYS_CLK_FREQ 66000000 #define CONFIG_83XX_PCICLK 66000000 -/* - * Bus Arbitration Configuration Register (ACR) - */ -#define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */ -#define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */ -#define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */ -#define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */ - /* * DDR Setup */ diff --git a/include/configs/kmtepr2.h b/include/configs/kmtepr2.h index 20cbc1318a..796040995d 100644 --- a/include/configs/kmtepr2.h +++ b/include/configs/kmtepr2.h @@ -45,14 +45,6 @@ #define CONFIG_SYS_CLK_FREQ 66000000 #define CONFIG_83XX_PCICLK 66000000 -/* - * Bus Arbitration Configuration Register (ACR) - */ -#define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */ -#define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */ -#define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */ -#define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */ - /* * DDR Setup */ diff --git a/include/configs/kmvect1.h b/include/configs/kmvect1.h index 37acb0245b..cfbf150b11 100644 --- a/include/configs/kmvect1.h +++ b/include/configs/kmvect1.h @@ -44,14 +44,6 @@ #define CONFIG_SYS_CLK_FREQ 66000000 #define CONFIG_83XX_PCICLK 66000000 -/* - * Bus Arbitration Configuration Register (ACR) - */ -#define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */ -#define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */ -#define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */ -#define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */ - /* * DDR Setup */ diff --git a/include/configs/mpc8308_p1m.h b/include/configs/mpc8308_p1m.h index d0eac0a2ef..60871b757d 100644 --- a/include/configs/mpc8308_p1m.h +++ b/include/configs/mpc8308_p1m.h @@ -36,11 +36,6 @@ #define CONFIG_FSL_SERDES #define CONFIG_FSL_SERDES1 0xe3000 -/* - * Arbiter Setup - */ -#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */ -#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */ #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */ /* diff --git a/include/configs/strider.h b/include/configs/strider.h index 8afd17d1b0..95bc20203f 100644 --- a/include/configs/strider.h +++ b/include/configs/strider.h @@ -21,11 +21,6 @@ #define CONFIG_FSL_SERDES #define CONFIG_FSL_SERDES1 0xe3000 -/* - * Arbiter Setup - */ -#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */ -#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */ #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */ /* diff --git a/include/configs/suvd3.h b/include/configs/suvd3.h index 82ebbca4db..e3653ea924 100644 --- a/include/configs/suvd3.h +++ b/include/configs/suvd3.h @@ -42,14 +42,6 @@ #define CONFIG_SYS_CLK_FREQ 66000000 #define CONFIG_83XX_PCICLK 66000000 -/* - * Bus Arbitration Configuration Register (ACR) - */ -#define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */ -#define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */ -#define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */ -#define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */ - /* * DDR Setup */ diff --git a/include/configs/tuge1.h b/include/configs/tuge1.h index b196c77c4e..81e11d2236 100644 --- a/include/configs/tuge1.h +++ b/include/configs/tuge1.h @@ -45,14 +45,6 @@ #define CONFIG_SYS_CLK_FREQ 66000000 #define CONFIG_83XX_PCICLK 66000000 -/* - * Bus Arbitration Configuration Register (ACR) - */ -#define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */ -#define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */ -#define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */ -#define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */ - /* * DDR Setup */ diff --git a/include/configs/tuxx1.h b/include/configs/tuxx1.h index 0ce848c911..28416af225 100644 --- a/include/configs/tuxx1.h +++ b/include/configs/tuxx1.h @@ -45,14 +45,6 @@ #define CONFIG_SYS_CLK_FREQ 66000000 #define CONFIG_83XX_PCICLK 66000000 -/* - * Bus Arbitration Configuration Register (ACR) - */ -#define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */ -#define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */ -#define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */ -#define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */ - /* * DDR Setup */ diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h index 1ac6cbefd6..76fe3be446 100644 --- a/include/configs/ve8313.h +++ b/include/configs/ve8313.h @@ -27,9 +27,6 @@ #define CONFIG_SYS_MEMTEST_START 0x00001000 #define CONFIG_SYS_MEMTEST_END 0x07000000 -#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth */ -#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count */ - /* * Device configurations */ diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index bde1af251b..ae07c8da24 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -1919,10 +1919,6 @@ CONFIG_SYS_64BIT_VSPRINTF CONFIG_SYS_66MHZ CONFIG_SYS_8313ERDB_BROKEN_PMC CONFIG_SYS_83XX_DDR_USES_CS0 -CONFIG_SYS_ACR_APARK -CONFIG_SYS_ACR_PARKM -CONFIG_SYS_ACR_PIPE_DEP -CONFIG_SYS_ACR_RPTCNT CONFIG_SYS_ADDRESS_MAP_A CONFIG_SYS_ADV7611_I2C CONFIG_SYS_ALT_BOOT From e35012e802de17c60cb38d0201ca4f1afb071d4c Mon Sep 17 00:00:00 2001 From: Mario Six Date: Mon, 21 Jan 2019 09:18:13 +0100 Subject: [PATCH 50/86] mpc83xx: Migrate SPCR to Kconfig Migrate the SPCR setting to Kconfig. Signed-off-by: Mario Six --- arch/powerpc/cpu/mpc83xx/Kconfig | 1 + arch/powerpc/cpu/mpc83xx/cpu_init.c | 29 +---- arch/powerpc/cpu/mpc83xx/initreg/Kconfig | 5 + arch/powerpc/cpu/mpc83xx/initreg/Kconfig.spcr | 115 ++++++++++++++++++ arch/powerpc/cpu/mpc83xx/initreg/initreg.h | 43 +++++++ configs/MPC8308RDB_defconfig | 1 + configs/MPC8315ERDB_defconfig | 1 + configs/MPC8323ERDB_defconfig | 1 + configs/MPC8349EMDS_PCI64_defconfig | 2 + configs/MPC8349EMDS_SLAVE_defconfig | 2 + configs/MPC8349EMDS_defconfig | 2 + configs/MPC8349ITXGP_defconfig | 2 + configs/MPC8349ITX_LOWBOOT_defconfig | 2 + configs/MPC8349ITX_defconfig | 2 + configs/MPC837XEMDS_HOST_defconfig | 1 + configs/MPC837XEMDS_SLAVE_defconfig | 1 + configs/MPC837XEMDS_defconfig | 1 + configs/MPC837XERDB_SLAVE_defconfig | 1 + configs/MPC837XERDB_defconfig | 1 + configs/hrcon_defconfig | 1 + configs/hrcon_dh_defconfig | 1 + configs/mpc8308_p1m_defconfig | 1 + configs/strider_con_defconfig | 1 + configs/strider_con_dp_defconfig | 1 + configs/strider_cpu_defconfig | 1 + configs/strider_cpu_dp_defconfig | 1 + include/configs/MPC8308RDB.h | 2 - include/configs/MPC8315ERDB.h | 2 - include/configs/MPC8323ERDB.h | 3 - include/configs/MPC8349EMDS.h | 2 - include/configs/MPC8349ITX.h | 2 - include/configs/MPC837XEMDS.h | 3 - include/configs/MPC837XERDB.h | 3 - include/configs/hrcon.h | 2 - include/configs/mpc8308_p1m.h | 2 - include/configs/strider.h | 2 - scripts/config_whitelist.txt | 1 - 37 files changed, 192 insertions(+), 52 deletions(-) create mode 100644 arch/powerpc/cpu/mpc83xx/initreg/Kconfig create mode 100644 arch/powerpc/cpu/mpc83xx/initreg/Kconfig.spcr create mode 100644 arch/powerpc/cpu/mpc83xx/initreg/initreg.h diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index 8a3bb10466..fe20e85086 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -296,6 +296,7 @@ source "arch/powerpc/cpu/mpc83xx/elbc/Kconfig" source "arch/powerpc/cpu/mpc83xx/hid/Kconfig" source "arch/powerpc/cpu/mpc83xx/sysio/Kconfig" source "arch/powerpc/cpu/mpc83xx/arbiter/Kconfig" +source "arch/powerpc/cpu/mpc83xx/initreg/Kconfig" menu "Legacy options" diff --git a/arch/powerpc/cpu/mpc83xx/cpu_init.c b/arch/powerpc/cpu/mpc83xx/cpu_init.c index 77502567a7..59faa78d24 100644 --- a/arch/powerpc/cpu/mpc83xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc83xx/cpu_init.c @@ -16,6 +16,7 @@ #include "elbc/elbc.h" #include "sysio/sysio.h" #include "arbiter/arbiter.h" +#include "initreg/initreg.h" DECLARE_GLOBAL_DATA_PTR; @@ -52,34 +53,6 @@ static void config_qe_ioports(void) */ void cpu_init_f (volatile immap_t * im) { - __be32 spcr_mask = -#ifdef CONFIG_SYS_SPCR_OPT /* Optimize transactions between CSB and other dev */ - SPCR_OPT | -#endif -#ifdef CONFIG_SYS_SPCR_TSECEP /* all eTSEC's Emergency priority */ - SPCR_TSECEP | -#endif -#ifdef CONFIG_SYS_SPCR_TSEC1EP /* TSEC1 Emergency priority */ - SPCR_TSEC1EP | -#endif -#ifdef CONFIG_SYS_SPCR_TSEC2EP /* TSEC2 Emergency priority */ - SPCR_TSEC2EP | -#endif - 0; - __be32 spcr_val = -#ifdef CONFIG_SYS_SPCR_OPT - (CONFIG_SYS_SPCR_OPT << SPCR_OPT_SHIFT) | -#endif -#ifdef CONFIG_SYS_SPCR_TSECEP /* all eTSEC's Emergency priority */ - (CONFIG_SYS_SPCR_TSECEP << SPCR_TSECEP_SHIFT) | -#endif -#ifdef CONFIG_SYS_SPCR_TSEC1EP /* TSEC1 Emergency priority */ - (CONFIG_SYS_SPCR_TSEC1EP << SPCR_TSEC1EP_SHIFT) | -#endif -#ifdef CONFIG_SYS_SPCR_TSEC2EP /* TSEC2 Emergency priority */ - (CONFIG_SYS_SPCR_TSEC2EP << SPCR_TSEC2EP_SHIFT) | -#endif - 0; __be32 sccr_mask = #ifdef CONFIG_SYS_SCCR_ENCCM /* Encryption clock mode */ SCCR_ENCCM | diff --git a/arch/powerpc/cpu/mpc83xx/initreg/Kconfig b/arch/powerpc/cpu/mpc83xx/initreg/Kconfig new file mode 100644 index 0000000000..82c2489178 --- /dev/null +++ b/arch/powerpc/cpu/mpc83xx/initreg/Kconfig @@ -0,0 +1,5 @@ +menu "Initial register configuration" + +source "arch/powerpc/cpu/mpc83xx/initreg/Kconfig.spcr" + +endmenu diff --git a/arch/powerpc/cpu/mpc83xx/initreg/Kconfig.spcr b/arch/powerpc/cpu/mpc83xx/initreg/Kconfig.spcr new file mode 100644 index 0000000000..f32309e6c0 --- /dev/null +++ b/arch/powerpc/cpu/mpc83xx/initreg/Kconfig.spcr @@ -0,0 +1,115 @@ +menu "SPCR - System priority and configuration register" + +choice + prompt "Optimize" + +config SPCR_OPT_UNSET + bool "Don't set value" + +config SPCR_OPT_NONE + bool "No performance enhancement" + +config SPCR_OPT_SPEC_READ + bool "Performance enhancement by speculative read" + +endchoice + +if ARCH_MPC8308 || ARCH_MPC831X || ARCH_MPC837X + +choice + prompt "TSEC emergency priority" + +config SPCR_TSECEP_UNSET + bool "Don't set value" + +config SPCR_TSECEP_0 + bool "Level 0 (lowest priority)" + +config SPCR_TSECEP_1 + bool "Level 1" + +config SPCR_TSECEP_2 + bool "Level 2" + +config SPCR_TSECEP_3 + bool "Level 3 (highest priority)" + +endchoice + +endif + +if ARCH_MPC8349 + +choice + prompt "TSEC1 emergency priority" + +config SPCR_TSEC1EP_UNSET + bool "Don't set value" + +config SPCR_TSEC1EP_0 + bool "Level 0 (lowest priority)" + +config SPCR_TSEC1EP_1 + bool "Level 1" + +config SPCR_TSEC1EP_2 + bool "Level 2" + +config SPCR_TSEC1EP_3 + bool "Level 3 (highest priority)" + +endchoice + +choice + prompt "TSEC2 emergency priority" + +config SPCR_TSEC2EP_UNSET + bool "Don't set value" + +config SPCR_TSEC2EP_0 + bool "Level 0 (lowest priority)" + +config SPCR_TSEC2EP_1 + bool "Level 1" + +config SPCR_TSEC2EP_2 + bool "Level 2" + +config SPCR_TSEC2EP_3 + bool "Level 3 (highest priority)" + +endchoice + +endif + +config SPCR_OPT + hex + default 0x0 if SPCR_OPT_UNSET + default 0x0 if SPCR_OPT_NONE + default 0x800000 if SPCR_OPT_SPEC_READ + +config SPCR_TSECEP + hex + default 0x0 if SPCR_TSECEP_UNSET + default 0x0 if SPCR_TSECEP_0 + default 0x100 if SPCR_TSECEP_1 + default 0x200 if SPCR_TSECEP_2 + default 0x300 if SPCR_TSECEP_3 + +config SPCR_TSEC1EP + hex + default 0x0 if SPCR_TSEC1EP_UNSET + default 0x0 if SPCR_TSEC1EP_0 + default 0x100 if SPCR_TSEC1EP_1 + default 0x200 if SPCR_TSEC1EP_2 + default 0x300 if SPCR_TSEC1EP_3 + +config SPCR_TSEC2EP + hex + default 0x0 if SPCR_TSEC2EP_UNSET + default 0x0 if SPCR_TSEC2EP_0 + default 0x1 if SPCR_TSEC2EP_1 + default 0x2 if SPCR_TSEC2EP_2 + default 0x3 if SPCR_TSEC2EP_3 + +endmenu diff --git a/arch/powerpc/cpu/mpc83xx/initreg/initreg.h b/arch/powerpc/cpu/mpc83xx/initreg/initreg.h new file mode 100644 index 0000000000..d61c70f1fa --- /dev/null +++ b/arch/powerpc/cpu/mpc83xx/initreg/initreg.h @@ -0,0 +1,43 @@ +#define SPCR_PCIHPE_MASK 0x10000000 +#define SPCR_PCIPR_MASK 0x03000000 +#define SPCR_OPT_MASK 0x00800000 +#define SPCR_TBEN_MASK 0x00400000 +#define SPCR_COREPR_MASK 0x00300000 +#define SPCR_TSEC1DP_MASK 0x00003000 +#define SPCR_TSEC1BDP_MASK 0x00000C00 +#define SPCR_TSEC1EP_MASK 0x00000300 +#define SPCR_TSEC2DP_MASK 0x00000030 +#define SPCR_TSEC2BDP_MASK 0x0000000C +#define SPCR_TSEC2EP_MASK 0x00000003 +#define SPCR_TSECDP_MASK 0x00003000 +#define SPCR_TSECBDP_MASK 0x00000C00 +#define SPCR_TSECEP_MASK 0x00000300 + + const __be32 spcr_mask = +#if defined(CONFIG_SPCR_OPT) && !defined(CONFIG_SPCR_OPT_UNSET) + SPCR_OPT_MASK | +#endif +#if defined(CONFIG_SPCR_TSECEP) && !defined(CONFIG_SPCR_TSECEP_UNSET) + SPCR_TSECEP_MASK | +#endif +#if defined(CONFIG_SPCR_TSEC1EP) && !defined(CONFIG_SPCR_TSEC1EP_UNSET) + SPCR_TSEC1EP_MASK | +#endif +#if defined(CONFIG_SPCR_TSEC2EP) && !defined(CONFIG_SPCR_TSEC2EP_UNSET) + SPCR_TSEC2EP_MASK | +#endif + 0; + const __be32 spcr_val = +#if defined(CONFIG_SPCR_OPT) && !defined(CONFIG_SPCR_OPT_UNSET) + CONFIG_SPCR_OPT | +#endif +#if defined(CONFIG_SPCR_TSECEP) && !defined(CONFIG_SPCR_TSECEP_UNSET) + CONFIG_SPCR_TSECEP | +#endif +#if defined(CONFIG_SPCR_TSEC1EP) && !defined(CONFIG_SPCR_TSEC1EP_UNSET) + CONFIG_SPCR_TSEC1EP | +#endif +#if defined(CONFIG_SPCR_TSEC2EP) && !defined(CONFIG_SPCR_TSEC2EP_UNSET) + CONFIG_SPCR_TSEC2EP | +#endif + 0; diff --git a/configs/MPC8308RDB_defconfig b/configs/MPC8308RDB_defconfig index 00feaccc30..a01ff8920b 100644 --- a/configs/MPC8308RDB_defconfig +++ b/configs/MPC8308RDB_defconfig @@ -72,6 +72,7 @@ CONFIG_SICR_TMSOBI1_2_5_V=y CONFIG_SICR_TMSOBI2_2_5_V=y CONFIG_ACR_PIPE_DEP_4=y CONFIG_ACR_RPTCNT_4=y +CONFIG_SPCR_TSECEP_3=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/MPC8315ERDB_defconfig b/configs/MPC8315ERDB_defconfig index 2263b9cb51..e5e1b7a29d 100644 --- a/configs/MPC8315ERDB_defconfig +++ b/configs/MPC8315ERDB_defconfig @@ -82,6 +82,7 @@ CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y CONFIG_ACR_PIPE_DEP_4=y CONFIG_ACR_RPTCNT_4=y +CONFIG_SPCR_TSECEP_3=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC8323ERDB_defconfig b/configs/MPC8323ERDB_defconfig index b52d1fd62a..08486f81a7 100644 --- a/configs/MPC8323ERDB_defconfig +++ b/configs/MPC8323ERDB_defconfig @@ -75,6 +75,7 @@ CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y CONFIG_ACR_PIPE_DEP_4=y CONFIG_ACR_RPTCNT_4=y +CONFIG_SPCR_OPT_SPEC_READ=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC8349EMDS_PCI64_defconfig b/configs/MPC8349EMDS_PCI64_defconfig index 9108275f3c..fa646f543f 100644 --- a/configs/MPC8349EMDS_PCI64_defconfig +++ b/configs/MPC8349EMDS_PCI64_defconfig @@ -58,6 +58,8 @@ CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y CONFIG_ACR_PIPE_DEP_4=y CONFIG_ACR_RPTCNT_4=y +CONFIG_SPCR_TSEC1EP_3=y +CONFIG_SPCR_TSEC2EP_3=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC8349EMDS_SLAVE_defconfig b/configs/MPC8349EMDS_SLAVE_defconfig index 7454dd64f1..8af1a3d3b2 100644 --- a/configs/MPC8349EMDS_SLAVE_defconfig +++ b/configs/MPC8349EMDS_SLAVE_defconfig @@ -56,6 +56,8 @@ CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y CONFIG_ACR_PIPE_DEP_4=y CONFIG_ACR_RPTCNT_4=y +CONFIG_SPCR_TSEC1EP_3=y +CONFIG_SPCR_TSEC2EP_3=y CONFIG_PCI_ONE_PCI1=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/configs/MPC8349EMDS_defconfig b/configs/MPC8349EMDS_defconfig index 328c3aa567..b2b944a30d 100644 --- a/configs/MPC8349EMDS_defconfig +++ b/configs/MPC8349EMDS_defconfig @@ -58,6 +58,8 @@ CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y CONFIG_ACR_PIPE_DEP_4=y CONFIG_ACR_RPTCNT_4=y +CONFIG_SPCR_TSEC1EP_3=y +CONFIG_SPCR_TSEC2EP_3=y CONFIG_PCI_ONE_PCI1=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/configs/MPC8349ITXGP_defconfig b/configs/MPC8349ITXGP_defconfig index fa121d721a..fcd78338c9 100644 --- a/configs/MPC8349ITXGP_defconfig +++ b/configs/MPC8349ITXGP_defconfig @@ -101,6 +101,8 @@ CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y CONFIG_ACR_PIPE_DEP_4=y CONFIG_ACR_RPTCNT_4=y +CONFIG_SPCR_TSEC1EP_3=y +CONFIG_SPCR_TSEC2EP_3=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFE000000" diff --git a/configs/MPC8349ITX_LOWBOOT_defconfig b/configs/MPC8349ITX_LOWBOOT_defconfig index 0a79d1e625..319b8d8c40 100644 --- a/configs/MPC8349ITX_LOWBOOT_defconfig +++ b/configs/MPC8349ITX_LOWBOOT_defconfig @@ -101,6 +101,8 @@ CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y CONFIG_ACR_PIPE_DEP_4=y CONFIG_ACR_RPTCNT_4=y +CONFIG_SPCR_TSEC1EP_3=y +CONFIG_SPCR_TSEC2EP_3=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC8349ITX_defconfig b/configs/MPC8349ITX_defconfig index e7461072ed..f60527b361 100644 --- a/configs/MPC8349ITX_defconfig +++ b/configs/MPC8349ITX_defconfig @@ -100,6 +100,8 @@ CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y CONFIG_ACR_PIPE_DEP_4=y CONFIG_ACR_RPTCNT_4=y +CONFIG_SPCR_TSEC1EP_3=y +CONFIG_SPCR_TSEC2EP_3=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC837XEMDS_HOST_defconfig b/configs/MPC837XEMDS_HOST_defconfig index 0df5bdb2c5..33e536ce18 100644 --- a/configs/MPC837XEMDS_HOST_defconfig +++ b/configs/MPC837XEMDS_HOST_defconfig @@ -106,6 +106,7 @@ CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y CONFIG_ACR_PIPE_DEP_4=y CONFIG_ACR_RPTCNT_4=y +CONFIG_SPCR_TSECEP_3=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC837XEMDS_SLAVE_defconfig b/configs/MPC837XEMDS_SLAVE_defconfig index 99f206e719..7d1f405171 100644 --- a/configs/MPC837XEMDS_SLAVE_defconfig +++ b/configs/MPC837XEMDS_SLAVE_defconfig @@ -66,6 +66,7 @@ CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y CONFIG_ACR_PIPE_DEP_4=y CONFIG_ACR_RPTCNT_4=y +CONFIG_SPCR_TSECEP_3=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PCISLAVE" diff --git a/configs/MPC837XEMDS_defconfig b/configs/MPC837XEMDS_defconfig index 98dc6ca784..d4515cbb8c 100644 --- a/configs/MPC837XEMDS_defconfig +++ b/configs/MPC837XEMDS_defconfig @@ -86,6 +86,7 @@ CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y CONFIG_ACR_PIPE_DEP_4=y CONFIG_ACR_RPTCNT_4=y +CONFIG_SPCR_TSECEP_3=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC837XERDB_SLAVE_defconfig b/configs/MPC837XERDB_SLAVE_defconfig index 11a33d982f..9730aefd54 100644 --- a/configs/MPC837XERDB_SLAVE_defconfig +++ b/configs/MPC837XERDB_SLAVE_defconfig @@ -66,6 +66,7 @@ CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y CONFIG_ACR_PIPE_DEP_4=y CONFIG_ACR_RPTCNT_4=y +CONFIG_SPCR_TSECEP_3=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PCISLAVE,PCIE" diff --git a/configs/MPC837XERDB_defconfig b/configs/MPC837XERDB_defconfig index d43b364910..7bf081a20b 100644 --- a/configs/MPC837XERDB_defconfig +++ b/configs/MPC837XERDB_defconfig @@ -106,6 +106,7 @@ CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y CONFIG_ACR_PIPE_DEP_4=y CONFIG_ACR_RPTCNT_4=y +CONFIG_SPCR_TSECEP_3=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PCIE" diff --git a/configs/hrcon_defconfig b/configs/hrcon_defconfig index 3dad033be0..9c1ab75e00 100644 --- a/configs/hrcon_defconfig +++ b/configs/hrcon_defconfig @@ -69,6 +69,7 @@ CONFIG_SICR_TMSOBI1_2_5_V=y CONFIG_SICR_TMSOBI2_2_5_V=y CONFIG_ACR_PIPE_DEP_4=y CONFIG_ACR_RPTCNT_4=y +CONFIG_SPCR_TSECEP_3=y CONFIG_CMD_IOLOOP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/hrcon_dh_defconfig b/configs/hrcon_dh_defconfig index 4fb7cb5ffd..0f1cc637cf 100644 --- a/configs/hrcon_dh_defconfig +++ b/configs/hrcon_dh_defconfig @@ -69,6 +69,7 @@ CONFIG_SICR_TMSOBI1_2_5_V=y CONFIG_SICR_TMSOBI2_2_5_V=y CONFIG_ACR_PIPE_DEP_4=y CONFIG_ACR_RPTCNT_4=y +CONFIG_SPCR_TSECEP_3=y CONFIG_CMD_IOLOOP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/mpc8308_p1m_defconfig b/configs/mpc8308_p1m_defconfig index f73084c0e1..f1559bef54 100644 --- a/configs/mpc8308_p1m_defconfig +++ b/configs/mpc8308_p1m_defconfig @@ -70,6 +70,7 @@ CONFIG_SICR_GTM_GPIO=y CONFIG_SICR_GPIOSEL_IEEE1588=y CONFIG_ACR_PIPE_DEP_4=y CONFIG_ACR_RPTCNT_4=y +CONFIG_SPCR_TSECEP_3=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=5 diff --git a/configs/strider_con_defconfig b/configs/strider_con_defconfig index 722f25d63e..b11a26c2fc 100644 --- a/configs/strider_con_defconfig +++ b/configs/strider_con_defconfig @@ -68,6 +68,7 @@ CONFIG_SICR_TMSOBI1_2_5_V=y CONFIG_SICR_TMSOBI2_2_5_V=y CONFIG_ACR_PIPE_DEP_4=y CONFIG_ACR_RPTCNT_4=y +CONFIG_SPCR_TSECEP_3=y CONFIG_CMD_IOLOOP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/strider_con_dp_defconfig b/configs/strider_con_dp_defconfig index dd3c83d4fc..72cb274348 100644 --- a/configs/strider_con_dp_defconfig +++ b/configs/strider_con_dp_defconfig @@ -68,6 +68,7 @@ CONFIG_SICR_TMSOBI1_2_5_V=y CONFIG_SICR_TMSOBI2_2_5_V=y CONFIG_ACR_PIPE_DEP_4=y CONFIG_ACR_RPTCNT_4=y +CONFIG_SPCR_TSECEP_3=y CONFIG_CMD_IOLOOP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/strider_cpu_defconfig b/configs/strider_cpu_defconfig index 1a35132987..f36404deb4 100644 --- a/configs/strider_cpu_defconfig +++ b/configs/strider_cpu_defconfig @@ -68,6 +68,7 @@ CONFIG_SICR_TMSOBI1_2_5_V=y CONFIG_SICR_TMSOBI2_2_5_V=y CONFIG_ACR_PIPE_DEP_4=y CONFIG_ACR_RPTCNT_4=y +CONFIG_SPCR_TSECEP_3=y CONFIG_CMD_IOLOOP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/strider_cpu_dp_defconfig b/configs/strider_cpu_dp_defconfig index 79fdc140e5..0ade98545a 100644 --- a/configs/strider_cpu_dp_defconfig +++ b/configs/strider_cpu_dp_defconfig @@ -68,6 +68,7 @@ CONFIG_SICR_TMSOBI1_2_5_V=y CONFIG_SICR_TMSOBI2_2_5_V=y CONFIG_ACR_PIPE_DEP_4=y CONFIG_ACR_RPTCNT_4=y +CONFIG_SPCR_TSECEP_3=y CONFIG_CMD_IOLOOP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h index 60c6b920f9..c4b604cc0d 100644 --- a/include/configs/MPC8308RDB.h +++ b/include/configs/MPC8308RDB.h @@ -33,8 +33,6 @@ #define CONFIG_FSL_SERDES #define CONFIG_FSL_SERDES1 0xe3000 -#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */ - /* * DDR Setup */ diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index 9531be3072..10742ae312 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -31,8 +31,6 @@ #define CONFIG_HWCONFIG -#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */ - /* * DDR Setup */ diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index 23496518b3..2ef16e543d 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -20,9 +20,6 @@ */ #define CONFIG_SYS_SICRL 0x00000000 -/* (0-1) Optimize transactions between CSB and the SEC and QUICC Engine block */ -#define CONFIG_SYS_SPCR_OPT 1 - /* * DDR Setup */ diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 51c47a8221..b64a911838 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -328,8 +328,6 @@ /* * System performance */ -#define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */ -#define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */ #define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */ #define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */ diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index 1c8574a40f..d8e86f21ea 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -403,8 +403,6 @@ boards, we say we have two, but don't display a message if we find only one. */ /* * System performance */ -#define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */ -#define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */ #define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */ #define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */ #define CONFIG_SYS_SCCR_USBMPHCM 3 /* USB MPH controller's clock */ diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index d8a02b8e06..5d46907331 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -12,9 +12,6 @@ */ #define CONFIG_E300 1 /* E300 family */ -/* System Priority Control Register */ -#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC1/2 emergency has highest priority */ - /* * IP blocks clock configuration */ diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index 6fa57ebee4..b6756c3794 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -23,9 +23,6 @@ /* System performance - define the value i.e. CONFIG_SYS_XXX */ -/* System Priority Control Regsiter */ -#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC1&2 emergency priority (0-3) */ - /* System Clock Configuration Register */ #define CONFIG_SYS_SCCR_TSEC1CM 1 /* eTSEC1 clock mode (0-3) */ #define CONFIG_SYS_SCCR_TSEC2CM 1 /* eTSEC2 clock mode (0-3) */ diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h index 76b28e07f4..9cb5df4a72 100644 --- a/include/configs/hrcon.h +++ b/include/configs/hrcon.h @@ -21,8 +21,6 @@ #define CONFIG_FSL_SERDES #define CONFIG_FSL_SERDES1 0xe3000 -#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */ - /* * DDR Setup */ diff --git a/include/configs/mpc8308_p1m.h b/include/configs/mpc8308_p1m.h index 60871b757d..ce3a899480 100644 --- a/include/configs/mpc8308_p1m.h +++ b/include/configs/mpc8308_p1m.h @@ -36,8 +36,6 @@ #define CONFIG_FSL_SERDES #define CONFIG_FSL_SERDES1 0xe3000 -#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */ - /* * DDR Setup */ diff --git a/include/configs/strider.h b/include/configs/strider.h index 95bc20203f..e4584db7d5 100644 --- a/include/configs/strider.h +++ b/include/configs/strider.h @@ -21,8 +21,6 @@ #define CONFIG_FSL_SERDES #define CONFIG_FSL_SERDES1 0xe3000 -#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */ - /* * DDR Setup */ diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index ae07c8da24..30b8b55132 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -4085,7 +4085,6 @@ CONFIG_SYS_SPANSION_BOOT CONFIG_SYS_SPCR_OPT CONFIG_SYS_SPCR_TSEC1EP CONFIG_SYS_SPCR_TSEC2EP -CONFIG_SYS_SPCR_TSECEP CONFIG_SYS_SPD_BUS_NUM CONFIG_SYS_SPI0 CONFIG_SYS_SPI0_NUM_CS From 7c2e535770f56f5788e3771b9ee2dbf40ec4d93f Mon Sep 17 00:00:00 2001 From: Mario Six Date: Mon, 21 Jan 2019 09:18:14 +0100 Subject: [PATCH 51/86] mpc83xx: Migrate CONFIG_LCRR_* to Kconfig Migrate the CONFIG_LCRR_* settings to Kconfig. Signed-off-by: Mario Six --- arch/powerpc/cpu/mpc83xx/cpu_init.c | 22 --- arch/powerpc/cpu/mpc83xx/initreg/Kconfig | 1 + arch/powerpc/cpu/mpc83xx/initreg/Kconfig.lcrr | 139 ++++++++++++++++++ arch/powerpc/cpu/mpc83xx/initreg/initreg.h | 36 +++++ configs/MPC8308RDB_defconfig | 2 + configs/MPC8313ERDB_33_defconfig | 2 + configs/MPC8313ERDB_66_defconfig | 2 + configs/MPC8313ERDB_NAND_33_defconfig | 2 + configs/MPC8313ERDB_NAND_66_defconfig | 2 + configs/MPC8315ERDB_defconfig | 2 + configs/MPC8323ERDB_defconfig | 2 + configs/MPC832XEMDS_ATM_defconfig | 2 + configs/MPC832XEMDS_HOST_33_defconfig | 2 + configs/MPC832XEMDS_HOST_66_defconfig | 2 + configs/MPC832XEMDS_SLAVE_defconfig | 2 + configs/MPC832XEMDS_defconfig | 2 + configs/MPC8349EMDS_PCI64_defconfig | 2 + configs/MPC8349EMDS_SDRAM_defconfig | 2 + configs/MPC8349EMDS_SLAVE_defconfig | 2 + configs/MPC8349EMDS_defconfig | 2 + configs/MPC8349ITXGP_defconfig | 2 + configs/MPC8349ITX_LOWBOOT_defconfig | 2 + configs/MPC8349ITX_defconfig | 2 + configs/MPC837XEMDS_HOST_defconfig | 2 + configs/MPC837XEMDS_SLAVE_defconfig | 2 + configs/MPC837XEMDS_defconfig | 2 + configs/MPC837XERDB_SLAVE_defconfig | 2 + configs/MPC837XERDB_defconfig | 2 + configs/TQM834x_defconfig | 2 + configs/hrcon_defconfig | 2 + configs/hrcon_dh_defconfig | 2 + configs/ids8313_defconfig | 2 + configs/kmcoge5ne_defconfig | 3 + configs/kmeter1_defconfig | 3 + configs/kmopti2_defconfig | 3 + configs/kmsupx5_defconfig | 3 + configs/kmtegr1_defconfig | 3 + configs/kmtepr2_defconfig | 3 + configs/kmvect1_defconfig | 3 + configs/mpc8308_p1m_defconfig | 2 + configs/sbc8349_PCI_33_defconfig | 2 + configs/sbc8349_PCI_66_defconfig | 2 + configs/sbc8349_defconfig | 2 + configs/strider_con_defconfig | 2 + configs/strider_con_dp_defconfig | 2 + configs/strider_cpu_defconfig | 2 + configs/strider_cpu_dp_defconfig | 2 + configs/suvd3_defconfig | 3 + configs/tuge1_defconfig | 3 + configs/tuxx1_defconfig | 3 + configs/ve8313_defconfig | 2 + configs/vme8349_defconfig | 1 + include/configs/MPC8308RDB.h | 2 - include/configs/MPC8313ERDB_NAND.h | 2 - include/configs/MPC8313ERDB_NOR.h | 2 - include/configs/MPC8315ERDB.h | 2 - include/configs/MPC8323ERDB.h | 2 - include/configs/MPC832XEMDS.h | 2 - include/configs/MPC8349EMDS.h | 2 - include/configs/MPC8349EMDS_SDRAM.h | 2 - include/configs/MPC8349ITX.h | 2 - include/configs/MPC837XEMDS.h | 2 - include/configs/MPC837XERDB.h | 2 - include/configs/TQM834x.h | 12 -- include/configs/caddy2.h | 1 - include/configs/hrcon.h | 2 - include/configs/ids8313.h | 2 - include/configs/kmcoge5ne.h | 7 - include/configs/kmeter1.h | 7 - include/configs/kmopti2.h | 4 - include/configs/kmsupx5.h | 4 - include/configs/kmtegr1.h | 4 - include/configs/kmtepr2.h | 4 - include/configs/kmvect1.h | 4 - include/configs/mpc8308_p1m.h | 2 - include/configs/sbc8349.h | 2 - include/configs/strider.h | 2 - include/configs/suvd3.h | 4 - include/configs/tuge1.h | 4 - include/configs/tuxx1.h | 4 - include/configs/ve8313.h | 3 - include/configs/vme8349.h | 1 - scripts/config_whitelist.txt | 3 - 83 files changed, 281 insertions(+), 120 deletions(-) create mode 100644 arch/powerpc/cpu/mpc83xx/initreg/Kconfig.lcrr diff --git a/arch/powerpc/cpu/mpc83xx/cpu_init.c b/arch/powerpc/cpu/mpc83xx/cpu_init.c index 59faa78d24..af8facad53 100644 --- a/arch/powerpc/cpu/mpc83xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc83xx/cpu_init.c @@ -127,28 +127,6 @@ void cpu_init_f (volatile immap_t * im) #endif #ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */ (CONFIG_SYS_SCCR_SATACM << SCCR_SATACM_SHIFT) | -#endif - 0; - __be32 lcrr_mask = -#ifdef CONFIG_SYS_LCRR_DBYP /* PLL bypass */ - LCRR_DBYP | -#endif -#ifdef CONFIG_SYS_LCRR_EADC /* external address delay */ - LCRR_EADC | -#endif -#ifdef CONFIG_SYS_LCRR_CLKDIV /* system clock divider */ - LCRR_CLKDIV | -#endif - 0; - __be32 lcrr_val = -#ifdef CONFIG_SYS_LCRR_DBYP /* PLL bypass */ - CONFIG_SYS_LCRR_DBYP | -#endif -#ifdef CONFIG_SYS_LCRR_EADC - CONFIG_SYS_LCRR_EADC | -#endif -#ifdef CONFIG_SYS_LCRR_CLKDIV /* system clock divider */ - CONFIG_SYS_LCRR_CLKDIV | #endif 0; diff --git a/arch/powerpc/cpu/mpc83xx/initreg/Kconfig b/arch/powerpc/cpu/mpc83xx/initreg/Kconfig index 82c2489178..a6b42a29af 100644 --- a/arch/powerpc/cpu/mpc83xx/initreg/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/initreg/Kconfig @@ -1,5 +1,6 @@ menu "Initial register configuration" source "arch/powerpc/cpu/mpc83xx/initreg/Kconfig.spcr" +source "arch/powerpc/cpu/mpc83xx/initreg/Kconfig.lcrr" endmenu diff --git a/arch/powerpc/cpu/mpc83xx/initreg/Kconfig.lcrr b/arch/powerpc/cpu/mpc83xx/initreg/Kconfig.lcrr new file mode 100644 index 0000000000..e6b6130de2 --- /dev/null +++ b/arch/powerpc/cpu/mpc83xx/initreg/Kconfig.lcrr @@ -0,0 +1,139 @@ +menu "LCRR - Clock Ratio Register register" + +if !ARCH_MPC8309 && !ARCH_MPC831X && !ARCH_MPC832X + +choice + prompt "DLL bypass" + +config LCRR_DBYP_UNSET + bool "Don't set value" + +config LCRR_DBYP_PLL_ENABLED + bool "PLL enabled" + +config LCRR_DBYP_PLL_BYPASSED + bool "PLL bypassed" + +endchoice + +endif + +if ARCH_MPC834X || ARCH_MPC8360 + +choice + prompt "Additional delay cycles for SDRAM control signals" + +config LCRR_BUFCMDC_UNSET + bool "Don't set value" + +config LCRR_BUFCMDC_4 + bool "4" + +config LCRR_BUFCMDC_1 + bool "1" + +config LCRR_BUFCMDC_2 + bool "2" + +config LCRR_BUFCMDC_3 + bool "3" + +endchoice + +choice + prompt "Extended CAS latency" + +config LCRR_ECL_UNSET + bool "Don't set value" + +config LCRR_ECL_4 + bool "4" + +config LCRR_ECL_5 + bool "5" + +config LCRR_ECL_6 + bool "6" + +config LCRR_ECL_7 + bool "7" + +endchoice + +endif # ARCH_MPC834X || ARCH_MPC8360 + +if !ARCH_MPC8308 + +choice + prompt "External address delay cycles" + +config LCRR_EADC_UNSET + bool "Don't set value" + +config LCRR_EADC_4 + bool "4" + +config LCRR_EADC_1 + bool "1" + +config LCRR_EADC_2 + bool "2" + +config LCRR_EADC_3 + bool "3" + +endchoice + +endif # !ARCH_MPC8308 + +choice + prompt "System clock divider" + +config LCRR_CLKDIV_UNSET + bool "Don't set value" + +config LCRR_CLKDIV_2 + bool "2" + +config LCRR_CLKDIV_4 + bool "4" + +config LCRR_CLKDIV_8 + bool "8" + +endchoice + +config LCRR_DBYP + hex + default 0x0 if LCRR_DBYP_UNSET || LCRR_DBYP_PLL_ENABLED + default 0x80000000 if LCRR_DBYP_PLL_BYPASSED + +config LCRR_BUFCMDC + hex + default 0x0 if LCRR_BUFCMDC_4 || LCRR_BUFCMDC_UNSET + default 0x10000000 if LCRR_BUFCMDC_1 + default 0x20000000 if LCRR_BUFCMDC_2 + default 0x30000000 if LCRR_BUFCMDC_3 + +config LCRR_ECL + hex + default 0x0 if LCRR_ECL_4 || LCRR_ECL_UNSET + default 0x1000000 if LCRR_ECL_5 + default 0x2000000 if LCRR_ECL_6 + default 0x3000000 if LCRR_ECL_7 + +config LCRR_EADC + hex + default 0x0 if LCRR_EADC_4 || LCRR_EADC_UNSET + default 0x10000 if LCRR_EADC_1 + default 0x20000 if LCRR_EADC_2 + default 0x30000 if LCRR_EADC_3 + +config LCRR_CLKDIV + hex + default 0x0 if LCRR_CLKDIV_UNSET + default 0x2 if LCRR_CLKDIV_2 + default 0x4 if LCRR_CLKDIV_4 + default 0x8 if LCRR_CLKDIV_8 + +endmenu diff --git a/arch/powerpc/cpu/mpc83xx/initreg/initreg.h b/arch/powerpc/cpu/mpc83xx/initreg/initreg.h index d61c70f1fa..63aa5c9466 100644 --- a/arch/powerpc/cpu/mpc83xx/initreg/initreg.h +++ b/arch/powerpc/cpu/mpc83xx/initreg/initreg.h @@ -39,5 +39,41 @@ #endif #if defined(CONFIG_SPCR_TSEC2EP) && !defined(CONFIG_SPCR_TSEC2EP_UNSET) CONFIG_SPCR_TSEC2EP | +#endif + 0; + + const __be32 lcrr_mask = +#if defined(CONFIG_LCRR_DBYP) && !defined(CONFIG_LCRR_DBYP_UNSET) + LCRR_DBYP | +#endif +#if defined(CONFIG_LCRR_BUFCMDC) && !defined(CONFIG_LCRR_BUFCMDC_UNSET) + LCRR_BUFCMDC | +#endif +#if defined(CONFIG_LCRR_ECL) && !defined(CONFIG_LCRR_ECL_UNSET) + LCRR_ECL | +#endif +#if defined(CONFIG_LCRR_EADC) && !defined(CONFIG_LCRR_EADC_UNSET) + LCRR_EADC | +#endif +#if defined(CONFIG_LCRR_CLKDIV) && !defined(CONFIG_LCRR_CLKDIV_UNSET) + LCRR_CLKDIV | +#endif + 0; + + const __be32 lcrr_val = +#if defined(CONFIG_LCRR_DBYP) && !defined(CONFIG_LCRR_DBYP_UNSET) + CONFIG_LCRR_DBYP | +#endif +#if defined(CONFIG_LCRR_BUFCMDC) && !defined(CONFIG_LCRR_BUFCMDC_UNSET) + CONFIG_LCRR_BUFCMDC | +#endif +#if defined(CONFIG_LCRR_ECL) && !defined(CONFIG_LCRR_ECL_UNSET) + CONFIG_LCRR_ECL | +#endif +#if defined(CONFIG_LCRR_EADC) && !defined(CONFIG_LCRR_EADC_UNSET) + CONFIG_LCRR_EADC | +#endif +#if defined(CONFIG_LCRR_CLKDIV) && !defined(CONFIG_LCRR_CLKDIV_UNSET) + CONFIG_LCRR_CLKDIV | #endif 0; diff --git a/configs/MPC8308RDB_defconfig b/configs/MPC8308RDB_defconfig index a01ff8920b..1a38ebd549 100644 --- a/configs/MPC8308RDB_defconfig +++ b/configs/MPC8308RDB_defconfig @@ -73,6 +73,8 @@ CONFIG_SICR_TMSOBI2_2_5_V=y CONFIG_ACR_PIPE_DEP_4=y CONFIG_ACR_RPTCNT_4=y CONFIG_SPCR_TSECEP_3=y +CONFIG_LCRR_DBYP_PLL_BYPASSED=y +CONFIG_LCRR_CLKDIV_2=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/MPC8313ERDB_33_defconfig b/configs/MPC8313ERDB_33_defconfig index b368aee966..04eb29ab9e 100644 --- a/configs/MPC8313ERDB_33_defconfig +++ b/configs/MPC8313ERDB_33_defconfig @@ -159,3 +159,5 @@ CONFIG_OR2_SETA_EXTERNAL=y CONFIG_OR2_XACS_EXTENDED=y CONFIG_OR2_TRLX_RELAXED=y CONFIG_OR2_EHTR_8_CYCLE=y +CONFIG_LCRR_EADC_1=y +CONFIG_LCRR_CLKDIV_4=y diff --git a/configs/MPC8313ERDB_66_defconfig b/configs/MPC8313ERDB_66_defconfig index ddf9060df4..8bbeb97778 100644 --- a/configs/MPC8313ERDB_66_defconfig +++ b/configs/MPC8313ERDB_66_defconfig @@ -158,3 +158,5 @@ CONFIG_OR2_SETA_EXTERNAL=y CONFIG_OR2_XACS_EXTENDED=y CONFIG_OR2_TRLX_RELAXED=y CONFIG_OR2_EHTR_8_CYCLE=y +CONFIG_LCRR_EADC_1=y +CONFIG_LCRR_CLKDIV_4=y diff --git a/configs/MPC8313ERDB_NAND_33_defconfig b/configs/MPC8313ERDB_NAND_33_defconfig index 7c16364d3f..29b12d0040 100644 --- a/configs/MPC8313ERDB_NAND_33_defconfig +++ b/configs/MPC8313ERDB_NAND_33_defconfig @@ -167,3 +167,5 @@ CONFIG_OR2_SETA_EXTERNAL=y CONFIG_OR2_XACS_EXTENDED=y CONFIG_OR2_TRLX_RELAXED=y CONFIG_OR2_EHTR_8_CYCLE=y +CONFIG_LCRR_EADC_1=y +CONFIG_LCRR_CLKDIV_4=y diff --git a/configs/MPC8313ERDB_NAND_66_defconfig b/configs/MPC8313ERDB_NAND_66_defconfig index ab8e315e0d..2dc31edccb 100644 --- a/configs/MPC8313ERDB_NAND_66_defconfig +++ b/configs/MPC8313ERDB_NAND_66_defconfig @@ -166,3 +166,5 @@ CONFIG_OR2_SETA_EXTERNAL=y CONFIG_OR2_XACS_EXTENDED=y CONFIG_OR2_TRLX_RELAXED=y CONFIG_OR2_EHTR_8_CYCLE=y +CONFIG_LCRR_EADC_1=y +CONFIG_LCRR_CLKDIV_4=y diff --git a/configs/MPC8315ERDB_defconfig b/configs/MPC8315ERDB_defconfig index e5e1b7a29d..08b5cc5086 100644 --- a/configs/MPC8315ERDB_defconfig +++ b/configs/MPC8315ERDB_defconfig @@ -143,3 +143,5 @@ CONFIG_OR1_CHT_TWO_CLOCK=y CONFIG_OR1_CSCT_8_CYCLE=y CONFIG_OR1_CST_ONE_CLOCK=y CONFIG_OR1_EHTR_8_CYCLE=y +CONFIG_LCRR_DBYP_PLL_BYPASSED=y +CONFIG_LCRR_CLKDIV_2=y diff --git a/configs/MPC8323ERDB_defconfig b/configs/MPC8323ERDB_defconfig index 08486f81a7..8ea942d7d9 100644 --- a/configs/MPC8323ERDB_defconfig +++ b/configs/MPC8323ERDB_defconfig @@ -108,3 +108,5 @@ CONFIG_OR0_XACS_EXTENDED=y CONFIG_OR0_XAM_SET=y CONFIG_OR0_TRLX_RELAXED=y CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_LCRR_DBYP_PLL_BYPASSED=y +CONFIG_LCRR_CLKDIV_2=y diff --git a/configs/MPC832XEMDS_ATM_defconfig b/configs/MPC832XEMDS_ATM_defconfig index 807d3e391a..c39f449da9 100644 --- a/configs/MPC832XEMDS_ATM_defconfig +++ b/configs/MPC832XEMDS_ATM_defconfig @@ -143,3 +143,5 @@ CONFIG_OR3_XACS_EXTENDED=y CONFIG_OR3_XAM_SET=y CONFIG_OR3_TRLX_RELAXED=y CONFIG_OR3_EHTR_8_CYCLE=y +CONFIG_LCRR_DBYP_PLL_BYPASSED=y +CONFIG_LCRR_CLKDIV_2=y diff --git a/configs/MPC832XEMDS_HOST_33_defconfig b/configs/MPC832XEMDS_HOST_33_defconfig index e328deb9fe..0e65d21bdb 100644 --- a/configs/MPC832XEMDS_HOST_33_defconfig +++ b/configs/MPC832XEMDS_HOST_33_defconfig @@ -163,3 +163,5 @@ CONFIG_OR3_XACS_EXTENDED=y CONFIG_OR3_XAM_SET=y CONFIG_OR3_TRLX_RELAXED=y CONFIG_OR3_EHTR_8_CYCLE=y +CONFIG_LCRR_DBYP_PLL_BYPASSED=y +CONFIG_LCRR_CLKDIV_2=y diff --git a/configs/MPC832XEMDS_HOST_66_defconfig b/configs/MPC832XEMDS_HOST_66_defconfig index d5bf354eec..472384fa14 100644 --- a/configs/MPC832XEMDS_HOST_66_defconfig +++ b/configs/MPC832XEMDS_HOST_66_defconfig @@ -163,3 +163,5 @@ CONFIG_OR3_XACS_EXTENDED=y CONFIG_OR3_XAM_SET=y CONFIG_OR3_TRLX_RELAXED=y CONFIG_OR3_EHTR_8_CYCLE=y +CONFIG_LCRR_DBYP_PLL_BYPASSED=y +CONFIG_LCRR_CLKDIV_2=y diff --git a/configs/MPC832XEMDS_SLAVE_defconfig b/configs/MPC832XEMDS_SLAVE_defconfig index 9d9d905118..ec8a94cd2a 100644 --- a/configs/MPC832XEMDS_SLAVE_defconfig +++ b/configs/MPC832XEMDS_SLAVE_defconfig @@ -160,3 +160,5 @@ CONFIG_OR3_XACS_EXTENDED=y CONFIG_OR3_XAM_SET=y CONFIG_OR3_TRLX_RELAXED=y CONFIG_OR3_EHTR_8_CYCLE=y +CONFIG_LCRR_DBYP_PLL_BYPASSED=y +CONFIG_LCRR_CLKDIV_2=y diff --git a/configs/MPC832XEMDS_defconfig b/configs/MPC832XEMDS_defconfig index 518f7114d7..8a26001f7f 100644 --- a/configs/MPC832XEMDS_defconfig +++ b/configs/MPC832XEMDS_defconfig @@ -142,3 +142,5 @@ CONFIG_OR3_XACS_EXTENDED=y CONFIG_OR3_XAM_SET=y CONFIG_OR3_TRLX_RELAXED=y CONFIG_OR3_EHTR_8_CYCLE=y +CONFIG_LCRR_DBYP_PLL_BYPASSED=y +CONFIG_LCRR_CLKDIV_2=y diff --git a/configs/MPC8349EMDS_PCI64_defconfig b/configs/MPC8349EMDS_PCI64_defconfig index fa646f543f..35b394ba6a 100644 --- a/configs/MPC8349EMDS_PCI64_defconfig +++ b/configs/MPC8349EMDS_PCI64_defconfig @@ -104,3 +104,5 @@ CONFIG_OR1_CSNT_EARLIER=y CONFIG_OR1_SCY_15=y CONFIG_OR1_XAM_SET=y CONFIG_OR1_EHTR_NORMAL=y +CONFIG_LCRR_DBYP_PLL_BYPASSED=y +CONFIG_LCRR_CLKDIV_4=y diff --git a/configs/MPC8349EMDS_SDRAM_defconfig b/configs/MPC8349EMDS_SDRAM_defconfig index 8589470b2e..936458a441 100644 --- a/configs/MPC8349EMDS_SDRAM_defconfig +++ b/configs/MPC8349EMDS_SDRAM_defconfig @@ -113,3 +113,5 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_MPC8XXX_SPI=y CONFIG_OF_LIBFDT=y +CONFIG_LCRR_DBYP_PLL_BYPASSED=y +CONFIG_LCRR_CLKDIV_4=y diff --git a/configs/MPC8349EMDS_SLAVE_defconfig b/configs/MPC8349EMDS_SLAVE_defconfig index 8af1a3d3b2..9649967bf0 100644 --- a/configs/MPC8349EMDS_SLAVE_defconfig +++ b/configs/MPC8349EMDS_SLAVE_defconfig @@ -104,3 +104,5 @@ CONFIG_OR1_CSNT_EARLIER=y CONFIG_OR1_SCY_15=y CONFIG_OR1_XAM_SET=y CONFIG_OR1_EHTR_NORMAL=y +CONFIG_LCRR_DBYP_PLL_BYPASSED=y +CONFIG_LCRR_CLKDIV_4=y diff --git a/configs/MPC8349EMDS_defconfig b/configs/MPC8349EMDS_defconfig index b2b944a30d..bb0d166e4d 100644 --- a/configs/MPC8349EMDS_defconfig +++ b/configs/MPC8349EMDS_defconfig @@ -107,3 +107,5 @@ CONFIG_OR1_CSNT_EARLIER=y CONFIG_OR1_SCY_15=y CONFIG_OR1_XAM_SET=y CONFIG_OR1_EHTR_NORMAL=y +CONFIG_LCRR_DBYP_PLL_BYPASSED=y +CONFIG_LCRR_CLKDIV_4=y diff --git a/configs/MPC8349ITXGP_defconfig b/configs/MPC8349ITXGP_defconfig index fcd78338c9..eddb72b1e0 100644 --- a/configs/MPC8349ITXGP_defconfig +++ b/configs/MPC8349ITXGP_defconfig @@ -178,3 +178,5 @@ CONFIG_BR3_MACHINE_UPMA=y CONFIG_BR3_PORTSIZE_16BIT=y CONFIG_OR3_AM_32_KBYTES=y CONFIG_OR3_BI_BURSTINHIBIT=y +CONFIG_LCRR_DBYP_PLL_BYPASSED=y +CONFIG_LCRR_CLKDIV_4=y diff --git a/configs/MPC8349ITX_LOWBOOT_defconfig b/configs/MPC8349ITX_LOWBOOT_defconfig index 319b8d8c40..b394da3a05 100644 --- a/configs/MPC8349ITX_LOWBOOT_defconfig +++ b/configs/MPC8349ITX_LOWBOOT_defconfig @@ -186,3 +186,5 @@ CONFIG_BR3_MACHINE_UPMA=y CONFIG_BR3_PORTSIZE_16BIT=y CONFIG_OR3_AM_32_KBYTES=y CONFIG_OR3_BI_BURSTINHIBIT=y +CONFIG_LCRR_DBYP_PLL_BYPASSED=y +CONFIG_LCRR_CLKDIV_4=y diff --git a/configs/MPC8349ITX_defconfig b/configs/MPC8349ITX_defconfig index f60527b361..274fbddf99 100644 --- a/configs/MPC8349ITX_defconfig +++ b/configs/MPC8349ITX_defconfig @@ -185,3 +185,5 @@ CONFIG_BR3_MACHINE_UPMA=y CONFIG_BR3_PORTSIZE_16BIT=y CONFIG_OR3_AM_32_KBYTES=y CONFIG_OR3_BI_BURSTINHIBIT=y +CONFIG_LCRR_DBYP_PLL_BYPASSED=y +CONFIG_LCRR_CLKDIV_4=y diff --git a/configs/MPC837XEMDS_HOST_defconfig b/configs/MPC837XEMDS_HOST_defconfig index 33e536ce18..6e6fc54d51 100644 --- a/configs/MPC837XEMDS_HOST_defconfig +++ b/configs/MPC837XEMDS_HOST_defconfig @@ -178,3 +178,5 @@ CONFIG_OR3_TRLX_RELAXED=y CONFIG_OR3_CHT_TWO_CLOCK=y CONFIG_OR3_CST_ONE_CLOCK=y CONFIG_OR3_EHTR_8_CYCLE=y +CONFIG_LCRR_DBYP_PLL_BYPASSED=y +CONFIG_LCRR_CLKDIV_8=y diff --git a/configs/MPC837XEMDS_SLAVE_defconfig b/configs/MPC837XEMDS_SLAVE_defconfig index 7d1f405171..421e176226 100644 --- a/configs/MPC837XEMDS_SLAVE_defconfig +++ b/configs/MPC837XEMDS_SLAVE_defconfig @@ -131,3 +131,5 @@ CONFIG_OR3_TRLX_RELAXED=y CONFIG_OR3_CHT_TWO_CLOCK=y CONFIG_OR3_CST_ONE_CLOCK=y CONFIG_OR3_EHTR_8_CYCLE=y +CONFIG_LCRR_DBYP_PLL_BYPASSED=y +CONFIG_LCRR_CLKDIV_8=y diff --git a/configs/MPC837XEMDS_defconfig b/configs/MPC837XEMDS_defconfig index d4515cbb8c..cd03f3ff9e 100644 --- a/configs/MPC837XEMDS_defconfig +++ b/configs/MPC837XEMDS_defconfig @@ -154,3 +154,5 @@ CONFIG_OR3_TRLX_RELAXED=y CONFIG_OR3_CHT_TWO_CLOCK=y CONFIG_OR3_CST_ONE_CLOCK=y CONFIG_OR3_EHTR_8_CYCLE=y +CONFIG_LCRR_DBYP_PLL_BYPASSED=y +CONFIG_LCRR_CLKDIV_8=y diff --git a/configs/MPC837XERDB_SLAVE_defconfig b/configs/MPC837XERDB_SLAVE_defconfig index 9730aefd54..c90ebc8d7e 100644 --- a/configs/MPC837XERDB_SLAVE_defconfig +++ b/configs/MPC837XERDB_SLAVE_defconfig @@ -132,3 +132,5 @@ CONFIG_OR2_SETA_EXTERNAL=y CONFIG_OR2_XACS_EXTENDED=y CONFIG_OR2_TRLX_RELAXED=y CONFIG_OR2_EHTR_8_CYCLE=y +CONFIG_LCRR_DBYP_PLL_BYPASSED=y +CONFIG_LCRR_CLKDIV_8=y diff --git a/configs/MPC837XERDB_defconfig b/configs/MPC837XERDB_defconfig index 7bf081a20b..95f4796281 100644 --- a/configs/MPC837XERDB_defconfig +++ b/configs/MPC837XERDB_defconfig @@ -175,3 +175,5 @@ CONFIG_OR2_SETA_EXTERNAL=y CONFIG_OR2_XACS_EXTENDED=y CONFIG_OR2_TRLX_RELAXED=y CONFIG_OR2_EHTR_8_CYCLE=y +CONFIG_LCRR_DBYP_PLL_BYPASSED=y +CONFIG_LCRR_CLKDIV_8=y diff --git a/configs/TQM834x_defconfig b/configs/TQM834x_defconfig index f5746cfad7..9d9f105f75 100644 --- a/configs/TQM834x_defconfig +++ b/configs/TQM834x_defconfig @@ -147,3 +147,5 @@ CONFIG_OR0_ACS_QUARTER_CYCLE_EARLIER=y CONFIG_OR0_CSNT_EARLIER=y CONFIG_OR0_SCY_5=y CONFIG_OR0_TRLX_RELAXED=y +CONFIG_LCRR_DBYP_PLL_BYPASSED=y +CONFIG_LCRR_CLKDIV_8=y diff --git a/configs/hrcon_defconfig b/configs/hrcon_defconfig index 9c1ab75e00..bc4c2a91fb 100644 --- a/configs/hrcon_defconfig +++ b/configs/hrcon_defconfig @@ -131,3 +131,5 @@ CONFIG_OR1_XACS_EXTENDED=y CONFIG_OR1_XAM_SET=y CONFIG_OR1_TRLX_RELAXED=y CONFIG_OR1_EHTR_8_CYCLE=y +CONFIG_LCRR_DBYP_PLL_BYPASSED=y +CONFIG_LCRR_CLKDIV_2=y diff --git a/configs/hrcon_dh_defconfig b/configs/hrcon_dh_defconfig index 0f1cc637cf..af93aef1be 100644 --- a/configs/hrcon_dh_defconfig +++ b/configs/hrcon_dh_defconfig @@ -129,3 +129,5 @@ CONFIG_OR1_XACS_EXTENDED=y CONFIG_OR1_XAM_SET=y CONFIG_OR1_TRLX_RELAXED=y CONFIG_OR1_EHTR_8_CYCLE=y +CONFIG_LCRR_DBYP_PLL_BYPASSED=y +CONFIG_LCRR_CLKDIV_2=y diff --git a/configs/ids8313_defconfig b/configs/ids8313_defconfig index f835868209..d9b1642671 100644 --- a/configs/ids8313_defconfig +++ b/configs/ids8313_defconfig @@ -170,3 +170,5 @@ CONFIG_OR3_AM_32_KBYTES=y CONFIG_OR3_CSNT_EARLIER=y CONFIG_OR3_SCY_1=y CONFIG_OR3_TRLX_RELAXED=y +CONFIG_LCRR_EADC_1=y +CONFIG_LCRR_CLKDIV_2=y diff --git a/configs/kmcoge5ne_defconfig b/configs/kmcoge5ne_defconfig index 7751e5a898..941efcdf9a 100644 --- a/configs/kmcoge5ne_defconfig +++ b/configs/kmcoge5ne_defconfig @@ -192,3 +192,6 @@ CONFIG_OR4_CSNT_EARLIER=y CONFIG_OR4_EAD_EXTRA=y CONFIG_OR4_SCY_2=y CONFIG_OR4_TRLX_RELAXED=y +CONFIG_LCRR_DBYP_PLL_BYPASSED=y +CONFIG_LCRR_CLKDIV_4=y +CONFIG_LCRR_EADC_2=y diff --git a/configs/kmeter1_defconfig b/configs/kmeter1_defconfig index 2bb3158873..4929a6039b 100644 --- a/configs/kmeter1_defconfig +++ b/configs/kmeter1_defconfig @@ -154,3 +154,6 @@ CONFIG_OR3_CSNT_EARLIER=y CONFIG_OR3_EAD_EXTRA=y CONFIG_OR3_SCY_2=y CONFIG_OR3_TRLX_RELAXED=y +CONFIG_LCRR_DBYP_PLL_BYPASSED=y +CONFIG_LCRR_CLKDIV_4=y +CONFIG_LCRR_EADC_2=y diff --git a/configs/kmopti2_defconfig b/configs/kmopti2_defconfig index 5eb5c939eb..afe424b8df 100644 --- a/configs/kmopti2_defconfig +++ b/configs/kmopti2_defconfig @@ -179,3 +179,6 @@ CONFIG_BR3_PORTSIZE_16BIT=y CONFIG_OR3_AM_256_MBYTES=y CONFIG_OR3_SCY_4=y CONFIG_OR3_EHTR_NORMAL=y +CONFIG_LCRR_DBYP_PLL_BYPASSED=y +CONFIG_LCRR_EADC_1=y +CONFIG_LCRR_CLKDIV_2=y diff --git a/configs/kmsupx5_defconfig b/configs/kmsupx5_defconfig index 0ad8801df9..1a78680bd0 100644 --- a/configs/kmsupx5_defconfig +++ b/configs/kmsupx5_defconfig @@ -157,3 +157,6 @@ CONFIG_OR2_EAD_EXTRA=y CONFIG_OR2_SCY_2=y CONFIG_OR2_TRLX_RELAXED=y CONFIG_OR2_EHTR_4_CYCLE=y +CONFIG_LCRR_DBYP_PLL_BYPASSED=y +CONFIG_LCRR_EADC_1=y +CONFIG_LCRR_CLKDIV_2=y diff --git a/configs/kmtegr1_defconfig b/configs/kmtegr1_defconfig index 8dfc4438ad..d874149fe3 100644 --- a/configs/kmtegr1_defconfig +++ b/configs/kmtegr1_defconfig @@ -157,3 +157,6 @@ CONFIG_BR3_PORTSIZE_16BIT=y CONFIG_OR3_AM_256_MBYTES=y CONFIG_OR3_SCY_5=y CONFIG_OR3_EHTR_NORMAL=y +CONFIG_LCRR_DBYP_PLL_BYPASSED=y +CONFIG_LCRR_EADC_1=y +CONFIG_LCRR_CLKDIV_2=y diff --git a/configs/kmtepr2_defconfig b/configs/kmtepr2_defconfig index 1a84ff5e0b..32d098028a 100644 --- a/configs/kmtepr2_defconfig +++ b/configs/kmtepr2_defconfig @@ -179,3 +179,6 @@ CONFIG_BR3_PORTSIZE_16BIT=y CONFIG_OR3_AM_256_MBYTES=y CONFIG_OR3_SCY_4=y CONFIG_OR3_EHTR_NORMAL=y +CONFIG_LCRR_DBYP_PLL_BYPASSED=y +CONFIG_LCRR_EADC_1=y +CONFIG_LCRR_CLKDIV_2=y diff --git a/configs/kmvect1_defconfig b/configs/kmvect1_defconfig index a746f195e6..26d9a7cf7a 100644 --- a/configs/kmvect1_defconfig +++ b/configs/kmvect1_defconfig @@ -177,3 +177,6 @@ CONFIG_OR3_ACS_QUARTER_CYCLE_EARLIER=y CONFIG_OR3_CSNT_EARLIER=y CONFIG_OR3_SCY_3=y CONFIG_OR3_TRLX_RELAXED=y +CONFIG_LCRR_DBYP_PLL_BYPASSED=y +CONFIG_LCRR_EADC_1=y +CONFIG_LCRR_CLKDIV_2=y diff --git a/configs/mpc8308_p1m_defconfig b/configs/mpc8308_p1m_defconfig index f1559bef54..0789ecd586 100644 --- a/configs/mpc8308_p1m_defconfig +++ b/configs/mpc8308_p1m_defconfig @@ -122,3 +122,5 @@ CONFIG_BR2_PORTSIZE_8BIT=y CONFIG_OR2_AM_32_KBYTES=y CONFIG_OR2_SCY_4=y CONFIG_OR2_EHTR_1_CYCLE=y +CONFIG_LCRR_DBYP_PLL_BYPASSED=y +CONFIG_LCRR_CLKDIV_2=y diff --git a/configs/sbc8349_PCI_33_defconfig b/configs/sbc8349_PCI_33_defconfig index a213f038ee..a363070dd8 100644 --- a/configs/sbc8349_PCI_33_defconfig +++ b/configs/sbc8349_PCI_33_defconfig @@ -106,3 +106,5 @@ CONFIG_OR0_XACS_EXTENDED=y CONFIG_OR0_XAM_SET=y CONFIG_OR0_TRLX_RELAXED=y CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_LCRR_DBYP_PLL_BYPASSED=y +CONFIG_LCRR_CLKDIV_4=y diff --git a/configs/sbc8349_PCI_66_defconfig b/configs/sbc8349_PCI_66_defconfig index 321c3d4073..215f31df28 100644 --- a/configs/sbc8349_PCI_66_defconfig +++ b/configs/sbc8349_PCI_66_defconfig @@ -106,3 +106,5 @@ CONFIG_OR0_XACS_EXTENDED=y CONFIG_OR0_XAM_SET=y CONFIG_OR0_TRLX_RELAXED=y CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_LCRR_DBYP_PLL_BYPASSED=y +CONFIG_LCRR_CLKDIV_4=y diff --git a/configs/sbc8349_defconfig b/configs/sbc8349_defconfig index 865a3ef74a..d492b861d5 100644 --- a/configs/sbc8349_defconfig +++ b/configs/sbc8349_defconfig @@ -84,3 +84,5 @@ CONFIG_OR0_XACS_EXTENDED=y CONFIG_OR0_XAM_SET=y CONFIG_OR0_TRLX_RELAXED=y CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_LCRR_DBYP_PLL_BYPASSED=y +CONFIG_LCRR_CLKDIV_4=y diff --git a/configs/strider_con_defconfig b/configs/strider_con_defconfig index b11a26c2fc..9f05b5693f 100644 --- a/configs/strider_con_defconfig +++ b/configs/strider_con_defconfig @@ -130,3 +130,5 @@ CONFIG_OR1_CSNT_EARLIER=y CONFIG_OR1_SCY_5=y CONFIG_OR1_XAM_SET=y CONFIG_OR1_EHTR_NORMAL=y +CONFIG_LCRR_DBYP_PLL_BYPASSED=y +CONFIG_LCRR_CLKDIV_2=y diff --git a/configs/strider_con_dp_defconfig b/configs/strider_con_dp_defconfig index 72cb274348..a1f9662518 100644 --- a/configs/strider_con_dp_defconfig +++ b/configs/strider_con_dp_defconfig @@ -130,3 +130,5 @@ CONFIG_OR1_CSNT_EARLIER=y CONFIG_OR1_SCY_5=y CONFIG_OR1_XAM_SET=y CONFIG_OR1_EHTR_NORMAL=y +CONFIG_LCRR_DBYP_PLL_BYPASSED=y +CONFIG_LCRR_CLKDIV_2=y diff --git a/configs/strider_cpu_defconfig b/configs/strider_cpu_defconfig index f36404deb4..2477ee5ca4 100644 --- a/configs/strider_cpu_defconfig +++ b/configs/strider_cpu_defconfig @@ -130,3 +130,5 @@ CONFIG_OR1_CSNT_EARLIER=y CONFIG_OR1_SCY_5=y CONFIG_OR1_XAM_SET=y CONFIG_OR1_EHTR_NORMAL=y +CONFIG_LCRR_DBYP_PLL_BYPASSED=y +CONFIG_LCRR_CLKDIV_2=y diff --git a/configs/strider_cpu_dp_defconfig b/configs/strider_cpu_dp_defconfig index 0ade98545a..da16d5dbfa 100644 --- a/configs/strider_cpu_dp_defconfig +++ b/configs/strider_cpu_dp_defconfig @@ -130,3 +130,5 @@ CONFIG_OR1_CSNT_EARLIER=y CONFIG_OR1_SCY_5=y CONFIG_OR1_XAM_SET=y CONFIG_OR1_EHTR_NORMAL=y +CONFIG_LCRR_DBYP_PLL_BYPASSED=y +CONFIG_LCRR_CLKDIV_2=y diff --git a/configs/suvd3_defconfig b/configs/suvd3_defconfig index 28e386db24..c970cde05e 100644 --- a/configs/suvd3_defconfig +++ b/configs/suvd3_defconfig @@ -175,3 +175,6 @@ CONFIG_OR3_ACS_QUARTER_CYCLE_EARLIER=y CONFIG_OR3_CSNT_EARLIER=y CONFIG_OR3_SCY_3=y CONFIG_OR3_TRLX_RELAXED=y +CONFIG_LCRR_DBYP_PLL_BYPASSED=y +CONFIG_LCRR_EADC_1=y +CONFIG_LCRR_CLKDIV_2=y diff --git a/configs/tuge1_defconfig b/configs/tuge1_defconfig index fb18a46ec6..550f524a3c 100644 --- a/configs/tuge1_defconfig +++ b/configs/tuge1_defconfig @@ -157,3 +157,6 @@ CONFIG_OR2_EAD_EXTRA=y CONFIG_OR2_SCY_2=y CONFIG_OR2_TRLX_RELAXED=y CONFIG_OR2_EHTR_4_CYCLE=y +CONFIG_LCRR_DBYP_PLL_BYPASSED=y +CONFIG_LCRR_EADC_1=y +CONFIG_LCRR_CLKDIV_2=y diff --git a/configs/tuxx1_defconfig b/configs/tuxx1_defconfig index a034f302b2..d5ec8e5bf2 100644 --- a/configs/tuxx1_defconfig +++ b/configs/tuxx1_defconfig @@ -182,3 +182,6 @@ CONFIG_OR3_CSNT_EARLIER=y CONFIG_OR3_SCY_2=y CONFIG_OR3_TRLX_RELAXED=y CONFIG_OR3_EHTR_4_CYCLE=y +CONFIG_LCRR_DBYP_PLL_BYPASSED=y +CONFIG_LCRR_EADC_1=y +CONFIG_LCRR_CLKDIV_2=y diff --git a/configs/ve8313_defconfig b/configs/ve8313_defconfig index 79f6430f91..0a9521b251 100644 --- a/configs/ve8313_defconfig +++ b/configs/ve8313_defconfig @@ -145,3 +145,5 @@ CONFIG_OR3_SCY_15=y CONFIG_OR3_XACS_EXTENDED=y CONFIG_OR3_TRLX_RELAXED=y CONFIG_OR3_EHTR_8_CYCLE=y +CONFIG_LCRR_EADC_3=y +CONFIG_LCRR_CLKDIV_2=y diff --git a/configs/vme8349_defconfig b/configs/vme8349_defconfig index 9ac88c0a4b..24bbba1aa7 100644 --- a/configs/vme8349_defconfig +++ b/configs/vme8349_defconfig @@ -118,3 +118,4 @@ CONFIG_BR1_MACHINE_GPCM=y CONFIG_BR1_PORTSIZE_32BIT=y CONFIG_OR1_AM_256_KBYTES=y CONFIG_OR1_SETA_EXTERNAL=y +CONFIG_LCRR_CLKDIV_4=y diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h index c4b604cc0d..e625f8709c 100644 --- a/include/configs/MPC8308RDB.h +++ b/include/configs/MPC8308RDB.h @@ -126,8 +126,6 @@ /* * Local Bus Configuration & Clock Setup */ -#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP -#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 #define CONFIG_SYS_LBC_LBCR 0x00040000 /* diff --git a/include/configs/MPC8313ERDB_NAND.h b/include/configs/MPC8313ERDB_NAND.h index aaf92fe37a..08c5b56da7 100644 --- a/include/configs/MPC8313ERDB_NAND.h +++ b/include/configs/MPC8313ERDB_NAND.h @@ -191,8 +191,6 @@ /* * Local Bus LCRR and LBCR regs */ -#define CONFIG_SYS_LCRR_EADC LCRR_EADC_1 -#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 #define CONFIG_SYS_LBC_LBCR (0x00040000 /* TODO */ \ | (0xFF << LBCR_BMT_SHIFT) \ | 0xF) /* 0x0004ff0f */ diff --git a/include/configs/MPC8313ERDB_NOR.h b/include/configs/MPC8313ERDB_NOR.h index 608565a139..2a39ffa6c2 100644 --- a/include/configs/MPC8313ERDB_NOR.h +++ b/include/configs/MPC8313ERDB_NOR.h @@ -164,8 +164,6 @@ /* * Local Bus LCRR and LBCR regs */ -#define CONFIG_SYS_LCRR_EADC LCRR_EADC_1 -#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 #define CONFIG_SYS_LBC_LBCR (0x00040000 /* TODO */ \ | (0xFF << LBCR_BMT_SHIFT) \ | 0xF) /* 0x0004ff0f */ diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index 10742ae312..b49022b916 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -121,8 +121,6 @@ /* * Local Bus Configuration & Clock Setup */ -#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP -#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 #define CONFIG_SYS_LBC_LBCR 0x00040000 #define CONFIG_FSL_ELBC 1 diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index 2ef16e543d..497c60bcda 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -118,8 +118,6 @@ /* * Local Bus Configuration & Clock Setup */ -#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP -#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index 195d62ce50..520f01f177 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -118,8 +118,6 @@ /* * Local Bus Configuration & Clock Setup */ -#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP -#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index b64a911838..2043344524 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -161,8 +161,6 @@ * External Local Bus rate is * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV */ -#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP -#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* diff --git a/include/configs/MPC8349EMDS_SDRAM.h b/include/configs/MPC8349EMDS_SDRAM.h index 35210ccfd2..70fc29e8ad 100644 --- a/include/configs/MPC8349EMDS_SDRAM.h +++ b/include/configs/MPC8349EMDS_SDRAM.h @@ -158,8 +158,6 @@ * External Local Bus rate is * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV */ -#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP -#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index d8e86f21ea..6f040a3d6d 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -258,8 +258,6 @@ boards, we say we have two, but don't display a message if we find only one. */ * External Local Bus rate is * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV */ -#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP -#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB sdram refresh timer, about 6us */ diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index 5d46907331..5f0050a97d 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -139,8 +139,6 @@ /* * Local Bus Configuration & Clock Setup */ -#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP -#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8 #define CONFIG_SYS_LBC_LBCR 0x00000000 #define CONFIG_FSL_ELBC 1 diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index b6756c3794..ef23d00408 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -163,8 +163,6 @@ /* * Local Bus Configuration & Clock Setup */ -#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP -#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8 #define CONFIG_SYS_LBC_LBCR 0x00000000 #define CONFIG_FSL_ELBC 1 diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index d713c695f7..8171f8531b 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -16,18 +16,6 @@ */ #define CONFIG_E300 1 /* E300 Family */ -/* - * Local Bus LCRR - * LCRR: DLL bypass, Clock divider is 8 - * - * for CSB = 266 MHz it gives LCB clock frequency = 33 MHz - * - * External Local Bus rate is - * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV - */ -#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP -#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8 - /* board pre init: do not call, nothing to do */ /* detect the number of flash banks */ diff --git a/include/configs/caddy2.h b/include/configs/caddy2.h index b4516267f1..a0642aef11 100644 --- a/include/configs/caddy2.h +++ b/include/configs/caddy2.h @@ -104,7 +104,6 @@ * External Local Bus rate is * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV */ -#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 #define CONFIG_SYS_LBC_LBCR 0x00000000 #undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */ diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h index 9cb5df4a72..0919bb544d 100644 --- a/include/configs/hrcon.h +++ b/include/configs/hrcon.h @@ -115,8 +115,6 @@ /* * Local Bus Configuration & Clock Setup */ -#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP -#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 #define CONFIG_SYS_LBC_LBCR 0x00040000 /* diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h index bd8f786a58..174c181ffa 100644 --- a/include/configs/ids8313.h +++ b/include/configs/ids8313.h @@ -39,8 +39,6 @@ /* * Local Bus LCRR and LBCR regs */ -#define CONFIG_SYS_LCRR_EADC LCRR_EADC_1 -#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 #define CONFIG_SYS_LBC_LBCR (0x00040000 |\ (0xFF << LBCR_BMT_SHIFT) |\ 0xF) diff --git a/include/configs/kmcoge5ne.h b/include/configs/kmcoge5ne.h index 08185894b8..7034c7033f 100644 --- a/include/configs/kmcoge5ne.h +++ b/include/configs/kmcoge5ne.h @@ -296,13 +296,6 @@ /* EEprom support */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -/* - * Local Bus Configuration & Clock Setup - */ -#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP -#define CONFIG_SYS_LCRR_EADC LCRR_EADC_2 -#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 - /* * PAXE on the local bus CS3 */ diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h index e0c3065ac6..bbf3783ef9 100644 --- a/include/configs/kmeter1.h +++ b/include/configs/kmeter1.h @@ -276,13 +276,6 @@ /* EEprom support */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -/* - * Local Bus Configuration & Clock Setup - */ -#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP -#define CONFIG_SYS_LCRR_EADC LCRR_EADC_2 -#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 - /* * PAXE on the local bus CS3 */ diff --git a/include/configs/kmopti2.h b/include/configs/kmopti2.h index c2f4188a22..77dc6a93b1 100644 --- a/include/configs/kmopti2.h +++ b/include/configs/kmopti2.h @@ -294,10 +294,6 @@ /* * Local Bus Configuration & Clock Setup */ -#define CONFIG_SYS_LCRR_DBYP 0x80000000 -#define CONFIG_SYS_LCRR_EADC 0x00010000 -#define CONFIG_SYS_LCRR_CLKDIV 0x00000002 - #define CONFIG_SYS_LBC_LBCR 0x00000000 #define CONFIG_SYS_APP1_BASE 0xA0000000 /* PAXG */ diff --git a/include/configs/kmsupx5.h b/include/configs/kmsupx5.h index b1ba474e78..561ae7a148 100644 --- a/include/configs/kmsupx5.h +++ b/include/configs/kmsupx5.h @@ -294,10 +294,6 @@ /* * Local Bus Configuration & Clock Setup */ -#define CONFIG_SYS_LCRR_DBYP 0x80000000 -#define CONFIG_SYS_LCRR_EADC 0x00010000 -#define CONFIG_SYS_LCRR_CLKDIV 0x00000002 - #define CONFIG_SYS_LBC_LBCR 0x00000000 #define CONFIG_SYS_APP1_BASE 0xA0000000 /* PAXG */ diff --git a/include/configs/kmtegr1.h b/include/configs/kmtegr1.h index d3f7c2c4d3..b4ebde8ba5 100644 --- a/include/configs/kmtegr1.h +++ b/include/configs/kmtegr1.h @@ -346,10 +346,6 @@ /* * Local Bus Configuration & Clock Setup */ -#define CONFIG_SYS_LCRR_DBYP 0x80000000 -#define CONFIG_SYS_LCRR_EADC 0x00010000 -#define CONFIG_SYS_LCRR_CLKDIV 0x00000002 - #define CONFIG_SYS_LBC_LBCR 0x00000000 /* must be after the include because KMBEC_FPGA is otherwise undefined */ diff --git a/include/configs/kmtepr2.h b/include/configs/kmtepr2.h index 796040995d..80f6f4daa4 100644 --- a/include/configs/kmtepr2.h +++ b/include/configs/kmtepr2.h @@ -294,10 +294,6 @@ /* * Local Bus Configuration & Clock Setup */ -#define CONFIG_SYS_LCRR_DBYP 0x80000000 -#define CONFIG_SYS_LCRR_EADC 0x00010000 -#define CONFIG_SYS_LCRR_CLKDIV 0x00000002 - #define CONFIG_SYS_LBC_LBCR 0x00000000 #define CONFIG_SYS_APP1_BASE 0xA0000000 /* PAXG */ diff --git a/include/configs/kmvect1.h b/include/configs/kmvect1.h index cfbf150b11..9e301a9728 100644 --- a/include/configs/kmvect1.h +++ b/include/configs/kmvect1.h @@ -338,10 +338,6 @@ /* * Local Bus Configuration & Clock Setup */ -#define CONFIG_SYS_LCRR_DBYP 0x80000000 -#define CONFIG_SYS_LCRR_EADC 0x00010000 -#define CONFIG_SYS_LCRR_CLKDIV 0x00000002 - #define CONFIG_SYS_LBC_LBCR 0x00000000 #define CONFIG_SYS_APP1_BASE 0xA0000000 diff --git a/include/configs/mpc8308_p1m.h b/include/configs/mpc8308_p1m.h index ce3a899480..aca4a655e0 100644 --- a/include/configs/mpc8308_p1m.h +++ b/include/configs/mpc8308_p1m.h @@ -130,8 +130,6 @@ /* * Local Bus Configuration & Clock Setup */ -#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP -#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 #define CONFIG_SYS_LBC_LBCR 0x00040000 /* diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index 775bbe417a..6bad651133 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -131,8 +131,6 @@ * External Local Bus rate is * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV */ -#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP -#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 #define CONFIG_SYS_LBC_LBCR 0x00000000 #undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */ diff --git a/include/configs/strider.h b/include/configs/strider.h index e4584db7d5..69e22fb141 100644 --- a/include/configs/strider.h +++ b/include/configs/strider.h @@ -115,8 +115,6 @@ /* * Local Bus Configuration & Clock Setup */ -#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP -#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 #define CONFIG_SYS_LBC_LBCR 0x00040000 /* diff --git a/include/configs/suvd3.h b/include/configs/suvd3.h index e3653ea924..ad3323fd0e 100644 --- a/include/configs/suvd3.h +++ b/include/configs/suvd3.h @@ -291,10 +291,6 @@ /* * Local Bus Configuration & Clock Setup */ -#define CONFIG_SYS_LCRR_DBYP 0x80000000 -#define CONFIG_SYS_LCRR_EADC 0x00010000 -#define CONFIG_SYS_LCRR_CLKDIV 0x00000002 - #define CONFIG_SYS_LBC_LBCR 0x00000000 #define CONFIG_SYS_APP1_BASE 0xA0000000 diff --git a/include/configs/tuge1.h b/include/configs/tuge1.h index 81e11d2236..466f75a44e 100644 --- a/include/configs/tuge1.h +++ b/include/configs/tuge1.h @@ -294,10 +294,6 @@ /* * Local Bus Configuration & Clock Setup */ -#define CONFIG_SYS_LCRR_DBYP 0x80000000 -#define CONFIG_SYS_LCRR_EADC 0x00010000 -#define CONFIG_SYS_LCRR_CLKDIV 0x00000002 - #define CONFIG_SYS_LBC_LBCR 0x00000000 #define CONFIG_SYS_APP1_BASE 0xA0000000 /* PAXG */ diff --git a/include/configs/tuxx1.h b/include/configs/tuxx1.h index 28416af225..02e24f002a 100644 --- a/include/configs/tuxx1.h +++ b/include/configs/tuxx1.h @@ -294,10 +294,6 @@ /* * Local Bus Configuration & Clock Setup */ -#define CONFIG_SYS_LCRR_DBYP 0x80000000 -#define CONFIG_SYS_LCRR_EADC 0x00010000 -#define CONFIG_SYS_LCRR_CLKDIV 0x00000002 - #define CONFIG_SYS_LBC_LBCR 0x00000000 #define CONFIG_SYS_APP1_BASE 0xA0000000 /* PAXG */ diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h index 76fe3be446..8b20bfd100 100644 --- a/include/configs/ve8313.h +++ b/include/configs/ve8313.h @@ -133,9 +133,6 @@ /* * Local Bus LCRR and LBCR regs */ -#define CONFIG_SYS_LCRR_EADC LCRR_EADC_3 -#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 - #define CONFIG_SYS_LBC_LBCR 0x00040000 #define CONFIG_SYS_LBC_MRTPR 0x20000000 diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h index 1a3a55b707..d50a5263a7 100644 --- a/include/configs/vme8349.h +++ b/include/configs/vme8349.h @@ -104,7 +104,6 @@ * External Local Bus rate is * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV */ -#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 #define CONFIG_SYS_LBC_LBCR 0x00000000 #undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */ diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 30b8b55132..c6c4689a2f 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -3203,9 +3203,6 @@ CONFIG_SYS_LBC_SDRAM_BASE_PHYS CONFIG_SYS_LBC_SDRAM_SIZE CONFIG_SYS_LB_SDRAM CONFIG_SYS_LCD_BASE -CONFIG_SYS_LCRR_CLKDIV -CONFIG_SYS_LCRR_DBYP -CONFIG_SYS_LCRR_EADC CONFIG_SYS_LDB_CLOCK CONFIG_SYS_LDSCRIPT CONFIG_SYS_LED_BASE From 8a81bfd271f9122933c865c790780024f5e2d576 Mon Sep 17 00:00:00 2001 From: Mario Six Date: Mon, 21 Jan 2019 09:18:15 +0100 Subject: [PATCH 52/86] mpc83xx: Get rid of CONFIG_SYS_DDR_BASE CONFIG_SYS_DDR_BASE is specific to mpc83xx an is always set to the same value as CONFIG_SYS_SDRAM_BASE. Just use CONFIG_SYS_SDRAM_BASE instead. Signed-off-by: Mario Six --- board/esd/vme8349/vme8349.c | 2 +- board/freescale/mpc8323erdb/mpc8323erdb.c | 2 +- board/freescale/mpc832xemds/mpc832xemds.c | 2 +- board/freescale/mpc8349emds/mpc8349emds.c | 2 +- board/freescale/mpc8349itx/mpc8349itx.c | 2 +- board/ids/ids8313/ids8313.c | 2 +- board/keymile/km83xx/km83xx.c | 4 ++-- board/sbc8349/sbc8349.c | 2 +- board/tqc/tqm834x/tqm834x.c | 6 +++--- board/ve8313/ve8313.c | 2 +- include/configs/MPC8308RDB.h | 5 ++--- include/configs/MPC8313ERDB_NAND.h | 5 ++--- include/configs/MPC8313ERDB_NOR.h | 5 ++--- include/configs/MPC8315ERDB.h | 5 ++--- include/configs/MPC8323ERDB.h | 5 ++--- include/configs/MPC832XEMDS.h | 5 ++--- include/configs/MPC8349EMDS.h | 5 ++--- include/configs/MPC8349EMDS_SDRAM.h | 5 ++--- include/configs/MPC8349ITX.h | 5 ++--- include/configs/MPC837XEMDS.h | 5 ++--- include/configs/MPC837XERDB.h | 5 ++--- include/configs/TQM834x.h | 5 ++--- include/configs/caddy2.h | 5 ++--- include/configs/hrcon.h | 5 ++--- include/configs/ids8313.h | 5 ++--- include/configs/kmcoge5ne.h | 5 ++--- include/configs/kmeter1.h | 5 ++--- include/configs/kmopti2.h | 5 ++--- include/configs/kmsupx5.h | 5 ++--- include/configs/kmtegr1.h | 5 ++--- include/configs/kmtepr2.h | 5 ++--- include/configs/kmvect1.h | 5 ++--- include/configs/mpc8308_p1m.h | 5 ++--- include/configs/sbc8349.h | 5 ++--- include/configs/strider.h | 5 ++--- include/configs/suvd3.h | 5 ++--- include/configs/tuge1.h | 5 ++--- include/configs/tuxx1.h | 5 ++--- include/configs/ve8313.h | 5 ++--- include/configs/vme8349.h | 5 ++--- scripts/config_whitelist.txt | 1 - 41 files changed, 73 insertions(+), 104 deletions(-) diff --git a/board/esd/vme8349/vme8349.c b/board/esd/vme8349/vme8349.c index a46d0b6da6..4c220fa8e1 100644 --- a/board/esd/vme8349/vme8349.c +++ b/board/esd/vme8349/vme8349.c @@ -38,7 +38,7 @@ int dram_init(void) return -ENXIO; /* DDR SDRAM - Main memory */ - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR; + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR; msize = spd_sdram(); diff --git a/board/freescale/mpc8323erdb/mpc8323erdb.c b/board/freescale/mpc8323erdb/mpc8323erdb.c index 772688186b..2dc6d7f5f5 100644 --- a/board/freescale/mpc8323erdb/mpc8323erdb.c +++ b/board/freescale/mpc8323erdb/mpc8323erdb.c @@ -79,7 +79,7 @@ int dram_init(void) return -ENXIO; /* DDR SDRAM - Main SODIMM */ - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR; + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR; msize = fixed_sdram(); diff --git a/board/freescale/mpc832xemds/mpc832xemds.c b/board/freescale/mpc832xemds/mpc832xemds.c index 869538feb9..61b95c601e 100644 --- a/board/freescale/mpc832xemds/mpc832xemds.c +++ b/board/freescale/mpc832xemds/mpc832xemds.c @@ -98,7 +98,7 @@ int dram_init(void) return -ENXIO; /* DDR SDRAM - Main SODIMM */ - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR; + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR; msize = fixed_sdram(); diff --git a/board/freescale/mpc8349emds/mpc8349emds.c b/board/freescale/mpc8349emds/mpc8349emds.c index d40ed3742e..ea018e5d20 100644 --- a/board/freescale/mpc8349emds/mpc8349emds.c +++ b/board/freescale/mpc8349emds/mpc8349emds.c @@ -56,7 +56,7 @@ int dram_init(void) return -ENXIO; /* DDR SDRAM - Main SODIMM */ - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR; + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR; #if defined(CONFIG_SPD_EEPROM) #ifndef CONFIG_SYS_FSL_DDR2 msize = spd_sdram() * 1024 * 1024; diff --git a/board/freescale/mpc8349itx/mpc8349itx.c b/board/freescale/mpc8349itx/mpc8349itx.c index 62bcf23571..aaaea7ce89 100644 --- a/board/freescale/mpc8349itx/mpc8349itx.c +++ b/board/freescale/mpc8349itx/mpc8349itx.c @@ -132,7 +132,7 @@ int dram_init(void) return -ENXIO; /* DDR SDRAM - Main SODIMM */ - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR; + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR; #ifdef CONFIG_SPD_EEPROM msize = spd_sdram(); #else diff --git a/board/ids/ids8313/ids8313.c b/board/ids/ids8313/ids8313.c index d547af4b05..a37ca8a2f4 100644 --- a/board/ids/ids8313/ids8313.c +++ b/board/ids/ids8313/ids8313.c @@ -96,7 +96,7 @@ int fixed_sdram(unsigned long config) setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN); /* now check the real size */ disable_addr_trans(); - msize = get_ram_size(CONFIG_SYS_DDR_BASE, msize); + msize = get_ram_size(CONFIG_SYS_SDRAM_BASE, msize); enable_addr_trans(); #endif return msize; diff --git a/board/keymile/km83xx/km83xx.c b/board/keymile/km83xx/km83xx.c index 1fd6f91901..880ce67fa6 100644 --- a/board/keymile/km83xx/km83xx.c +++ b/board/keymile/km83xx/km83xx.c @@ -311,7 +311,7 @@ static int fixed_sdram(void) msize = CONFIG_SYS_DDR_SIZE << 20; disable_addr_trans(); - msize = get_ram_size(CONFIG_SYS_DDR_BASE, msize); + msize = get_ram_size(CONFIG_SYS_SDRAM_BASE, msize); enable_addr_trans(); msize /= (1024 * 1024); if (CONFIG_SYS_DDR_SIZE != msize) { @@ -338,7 +338,7 @@ int dram_init(void) return -ENXIO; out_be32(&im->sysconf.ddrlaw[0].bar, - CONFIG_SYS_DDR_BASE & LAWBAR_BAR); + CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR); msize = fixed_sdram(); #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) diff --git a/board/sbc8349/sbc8349.c b/board/sbc8349/sbc8349.c index b8ba29ac6d..5584b3d179 100644 --- a/board/sbc8349/sbc8349.c +++ b/board/sbc8349/sbc8349.c @@ -45,7 +45,7 @@ int dram_init(void) return -1; /* DDR SDRAM - Main SODIMM */ - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR; + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR; #if defined(CONFIG_SPD_EEPROM) msize = spd_sdram(); #else diff --git a/board/tqc/tqm834x/tqm834x.c b/board/tqc/tqm834x/tqm834x.c index c75251e132..04941b26be 100644 --- a/board/tqc/tqm834x/tqm834x.c +++ b/board/tqc/tqm834x/tqm834x.c @@ -72,13 +72,13 @@ int dram_init(void) int cs; /* during size detection, set up the max DDRLAW size */ - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE; + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE; im->sysconf.ddrlaw[0].ar = (LAWAR_EN | LAWAR_SIZE_2G); /* set CS bounds to maximum size */ for(cs = 0; cs < 4; ++cs) { set_cs_bounds(cs, - CONFIG_SYS_DDR_BASE + (cs * DDR_MAX_SIZE_PER_CS), + CONFIG_SYS_SDRAM_BASE + (cs * DDR_MAX_SIZE_PER_CS), DDR_MAX_SIZE_PER_CS); set_cs_config(cs, INITIAL_CS_CONFIG); @@ -102,7 +102,7 @@ int dram_init(void) debug("\nDetecting Bank%d\n", cs); bank_size = get_ddr_bank_size(cs, - (long *)(CONFIG_SYS_DDR_BASE + size)); + (long *)(CONFIG_SYS_SDRAM_BASE + size)); size += bank_size; debug("DDR Bank%d size: %ld MiB\n\n", cs, bank_size >> 20); diff --git a/board/ve8313/ve8313.c b/board/ve8313/ve8313.c index f0fc1fe3b3..609585bc65 100644 --- a/board/ve8313/ve8313.c +++ b/board/ve8313/ve8313.c @@ -80,7 +80,7 @@ static long fixed_sdram(void) /* now check the real size */ disable_addr_trans (); - msize = get_ram_size (CONFIG_SYS_DDR_BASE, msize); + msize = get_ram_size (CONFIG_SYS_SDRAM_BASE, msize); enable_addr_trans (); #endif diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h index e625f8709c..d9361fd8a0 100644 --- a/include/configs/MPC8308RDB.h +++ b/include/configs/MPC8308RDB.h @@ -36,9 +36,8 @@ /* * DDR Setup */ -#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ | DDRCDR_PZ_LOZ \ diff --git a/include/configs/MPC8313ERDB_NAND.h b/include/configs/MPC8313ERDB_NAND.h index 08c5b56da7..08c83996c7 100644 --- a/include/configs/MPC8313ERDB_NAND.h +++ b/include/configs/MPC8313ERDB_NAND.h @@ -86,9 +86,8 @@ /* * DDR Setup */ -#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/ +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE /* * Manually set up DDR parameters, as this board does not diff --git a/include/configs/MPC8313ERDB_NOR.h b/include/configs/MPC8313ERDB_NOR.h index 2a39ffa6c2..169cc09d06 100644 --- a/include/configs/MPC8313ERDB_NOR.h +++ b/include/configs/MPC8313ERDB_NOR.h @@ -58,9 +58,8 @@ /* * DDR Setup */ -#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/ +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE /* * Manually set up DDR parameters, as this board does not diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index b49022b916..c5a229deb4 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -34,9 +34,8 @@ /* * DDR Setup */ -#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ | DDRCDR_PZ_LOZ \ diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index 497c60bcda..3e6febfc9d 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -23,9 +23,8 @@ /* * DDR Setup */ -#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #undef CONFIG_SPD_EEPROM #if defined(CONFIG_SPD_EEPROM) diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index 520f01f177..4b3f70c916 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -20,9 +20,8 @@ /* * DDR Setup */ -#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDRCDR 0x73000002 /* DDR II voltage is 1.8V */ #undef CONFIG_SPD_EEPROM diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 2043344524..1a96be0895 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -52,9 +52,8 @@ */ #undef CONFIG_DDR_32BIT -#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/ +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) #undef CONFIG_DDR_2T_TIMING diff --git a/include/configs/MPC8349EMDS_SDRAM.h b/include/configs/MPC8349EMDS_SDRAM.h index 70fc29e8ad..311f87b5b3 100644 --- a/include/configs/MPC8349EMDS_SDRAM.h +++ b/include/configs/MPC8349EMDS_SDRAM.h @@ -52,9 +52,8 @@ */ #undef CONFIG_DDR_32BIT -#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/ +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) #undef CONFIG_DDR_2T_TIMING diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index 6f040a3d6d..bb3bcfcc44 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -142,9 +142,8 @@ /* * DDR Setup */ -#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/ +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_83XX_DDR_USES_CS0 #define CONFIG_SYS_MEMTEST_START 0x1000 /* memtest region */ #define CONFIG_SYS_MEMTEST_END 0x2000 diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index 5f0050a97d..e34a36cadd 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -35,9 +35,8 @@ /* * DDR Setup */ -#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 #define CONFIG_SYS_83XX_DDR_USES_CS0 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN \ diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index ef23d00408..33d4ced92f 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -58,9 +58,8 @@ /* * DDR Setup */ -#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x03000000 #define CONFIG_SYS_83XX_DDR_USES_CS0 diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index 8171f8531b..53fac4d675 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -24,9 +24,8 @@ * DDR Setup */ /* DDR is system memory*/ -#define CONFIG_SYS_DDR_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define DDR_CASLAT_25 /* CASLAT set to 2.5 */ #undef CONFIG_DDR_ECC /* only for ECC DDR module */ #undef CONFIG_SPD_EEPROM /* do not use SPD EEPROM for DDR setup */ diff --git a/include/configs/caddy2.h b/include/configs/caddy2.h index a0642aef11..f14e5faafa 100644 --- a/include/configs/caddy2.h +++ b/include/configs/caddy2.h @@ -51,9 +51,8 @@ */ #undef CONFIG_DDR_32BIT -#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is sys memory*/ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is sys memory*/ +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) #define CONFIG_DDR_2T_TIMING diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h index 0919bb544d..ae3fcfd3d7 100644 --- a/include/configs/hrcon.h +++ b/include/configs/hrcon.h @@ -24,9 +24,8 @@ /* * DDR Setup */ -#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ | DDRCDR_PZ_LOZ \ diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h index 174c181ffa..504a136daa 100644 --- a/include/configs/ids8313.h +++ b/include/configs/ids8313.h @@ -51,9 +51,8 @@ /* * DDR Setup */ -#define CONFIG_SYS_DDR_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE /* * Manually set up DDR parameters, diff --git a/include/configs/kmcoge5ne.h b/include/configs/kmcoge5ne.h index 7034c7033f..5c4df18ca6 100644 --- a/include/configs/kmcoge5ne.h +++ b/include/configs/kmcoge5ne.h @@ -43,11 +43,10 @@ /* * DDR Setup */ -#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h index bbf3783ef9..2e8affb618 100644 --- a/include/configs/kmeter1.h +++ b/include/configs/kmeter1.h @@ -28,11 +28,10 @@ /* * DDR Setup */ -#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) diff --git a/include/configs/kmopti2.h b/include/configs/kmopti2.h index 77dc6a93b1..3be53285db 100644 --- a/include/configs/kmopti2.h +++ b/include/configs/kmopti2.h @@ -48,11 +48,10 @@ /* * DDR Setup */ -#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) diff --git a/include/configs/kmsupx5.h b/include/configs/kmsupx5.h index 561ae7a148..74e719cc79 100644 --- a/include/configs/kmsupx5.h +++ b/include/configs/kmsupx5.h @@ -48,11 +48,10 @@ /* * DDR Setup */ -#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) diff --git a/include/configs/kmtegr1.h b/include/configs/kmtegr1.h index b4ebde8ba5..c6913838ce 100644 --- a/include/configs/kmtegr1.h +++ b/include/configs/kmtegr1.h @@ -55,11 +55,10 @@ /* * DDR Setup */ -#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) diff --git a/include/configs/kmtepr2.h b/include/configs/kmtepr2.h index 80f6f4daa4..4af86195c5 100644 --- a/include/configs/kmtepr2.h +++ b/include/configs/kmtepr2.h @@ -48,11 +48,10 @@ /* * DDR Setup */ -#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) diff --git a/include/configs/kmvect1.h b/include/configs/kmvect1.h index 9e301a9728..d8f4d269ed 100644 --- a/include/configs/kmvect1.h +++ b/include/configs/kmvect1.h @@ -47,11 +47,10 @@ /* * DDR Setup */ -#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) diff --git a/include/configs/mpc8308_p1m.h b/include/configs/mpc8308_p1m.h index aca4a655e0..8836b70b76 100644 --- a/include/configs/mpc8308_p1m.h +++ b/include/configs/mpc8308_p1m.h @@ -39,9 +39,8 @@ /* * DDR Setup */ -#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ | DDRCDR_PZ_LOZ \ diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index 6bad651133..709387ecf7 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -46,9 +46,8 @@ */ #undef CONFIG_DDR_32BIT -#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/ +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) #define CONFIG_DDR_2T_TIMING diff --git a/include/configs/strider.h b/include/configs/strider.h index 69e22fb141..c01531c3ca 100644 --- a/include/configs/strider.h +++ b/include/configs/strider.h @@ -24,9 +24,8 @@ /* * DDR Setup */ -#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ | DDRCDR_PZ_LOZ \ diff --git a/include/configs/suvd3.h b/include/configs/suvd3.h index ad3323fd0e..3521de8d2e 100644 --- a/include/configs/suvd3.h +++ b/include/configs/suvd3.h @@ -45,11 +45,10 @@ /* * DDR Setup */ -#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) diff --git a/include/configs/tuge1.h b/include/configs/tuge1.h index 466f75a44e..86e402ae23 100644 --- a/include/configs/tuge1.h +++ b/include/configs/tuge1.h @@ -48,11 +48,10 @@ /* * DDR Setup */ -#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) diff --git a/include/configs/tuxx1.h b/include/configs/tuxx1.h index 02e24f002a..ec1ac399a0 100644 --- a/include/configs/tuxx1.h +++ b/include/configs/tuxx1.h @@ -48,11 +48,10 @@ /* * DDR Setup */ -#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h index 8b20bfd100..cd6c686b89 100644 --- a/include/configs/ve8313.h +++ b/include/configs/ve8313.h @@ -34,9 +34,8 @@ /* * DDR Setup */ -#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/ +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE /* * Manually set up DDR parameters, as this board does not diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h index d50a5263a7..14a84fabc9 100644 --- a/include/configs/vme8349.h +++ b/include/configs/vme8349.h @@ -51,9 +51,8 @@ */ #undef CONFIG_DDR_32BIT -#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is sys memory*/ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is sys memory*/ +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) #define CONFIG_DDR_2T_TIMING diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index c6c4689a2f..992bcc3d8f 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -2254,7 +2254,6 @@ CONFIG_SYS_DDRCDR_VALUE CONFIG_SYS_DDRD CONFIG_SYS_DDRTC CONFIG_SYS_DDRUA -CONFIG_SYS_DDR_BASE CONFIG_SYS_DDR_BLOCK1_SIZE CONFIG_SYS_DDR_BLOCK2_BASE CONFIG_SYS_DDR_CDR_1 From 133ec602846d28a7915a7b3149d05d1c8a270873 Mon Sep 17 00:00:00 2001 From: Mario Six Date: Mon, 21 Jan 2019 09:18:16 +0100 Subject: [PATCH 53/86] mpc83xx: Get rid of CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE is set to the same value as CONFIG_SYS_SDRAM_BASE on all existing boards. Just use CONFIG_SYS_SDRAM_BASE instead. Signed-off-by: Mario Six --- arch/powerpc/cpu/mpc83xx/spd_sdram.c | 2 +- board/freescale/mpc8308rdb/sdram.c | 4 ++-- board/freescale/mpc8313erdb/sdram.c | 8 ++++---- board/freescale/mpc8315erdb/sdram.c | 2 +- board/freescale/mpc8349emds/mpc8349emds.c | 8 ++++---- board/freescale/mpc8349itx/mpc8349itx.c | 8 ++++---- board/freescale/mpc837xemds/mpc837xemds.c | 2 +- board/freescale/mpc837xerdb/mpc837xerdb.c | 2 +- board/gdsys/mpc8308/sdram.c | 4 ++-- board/ids/ids8313/ids8313.c | 2 +- board/mpc8308_p1m/sdram.c | 4 ++-- board/sbc8349/sbc8349.c | 8 ++++---- board/ve8313/ve8313.c | 8 ++++---- drivers/ddr/fsl/main.c | 4 ++++ include/configs/MPC8308RDB.h | 1 - include/configs/MPC8313ERDB_NAND.h | 1 - include/configs/MPC8313ERDB_NOR.h | 1 - include/configs/MPC8315ERDB.h | 1 - include/configs/MPC8323ERDB.h | 1 - include/configs/MPC832XEMDS.h | 1 - include/configs/MPC8349EMDS.h | 1 - include/configs/MPC8349EMDS_SDRAM.h | 1 - include/configs/MPC8349ITX.h | 1 - include/configs/MPC837XEMDS.h | 1 - include/configs/MPC837XERDB.h | 1 - include/configs/TQM834x.h | 1 - include/configs/caddy2.h | 1 - include/configs/hrcon.h | 1 - include/configs/ids8313.h | 1 - include/configs/kmcoge5ne.h | 1 - include/configs/kmeter1.h | 1 - include/configs/kmopti2.h | 1 - include/configs/kmsupx5.h | 1 - include/configs/kmtegr1.h | 1 - include/configs/kmtepr2.h | 1 - include/configs/kmvect1.h | 1 - include/configs/mpc8308_p1m.h | 1 - include/configs/sbc8349.h | 1 - include/configs/strider.h | 1 - include/configs/suvd3.h | 1 - include/configs/tuge1.h | 1 - include/configs/tuxx1.h | 1 - include/configs/ve8313.h | 1 - include/configs/vme8349.h | 1 - 44 files changed, 35 insertions(+), 61 deletions(-) diff --git a/arch/powerpc/cpu/mpc83xx/spd_sdram.c b/arch/powerpc/cpu/mpc83xx/spd_sdram.c index b3cbf9f882..5ca307ca58 100644 --- a/arch/powerpc/cpu/mpc83xx/spd_sdram.c +++ b/arch/powerpc/cpu/mpc83xx/spd_sdram.c @@ -281,7 +281,7 @@ long int spd_sdram() /* * Set up LAWBAR for all of DDR. */ - ecm->bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; + ecm->bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000; ecm->ar = (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & law_size)); debug("DDR:bar=0x%08x\n", ecm->bar); debug("DDR:ar=0x%08x\n", ecm->ar); diff --git a/board/freescale/mpc8308rdb/sdram.c b/board/freescale/mpc8308rdb/sdram.c index e64b3107b5..317e63ea6a 100644 --- a/board/freescale/mpc8308rdb/sdram.c +++ b/board/freescale/mpc8308rdb/sdram.c @@ -33,7 +33,7 @@ static long fixed_sdram(void) u32 msize_log2 = __ilog2(msize); out_be32(&im->sysconf.ddrlaw[0].bar, - CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000); + CONFIG_SYS_SDRAM_BASE & 0xfffff000); out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1)); out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE); @@ -61,7 +61,7 @@ static long fixed_sdram(void) setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN); sync(); - return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize); + return get_ram_size(CONFIG_SYS_SDRAM_BASE, msize); } int dram_init(void) diff --git a/board/freescale/mpc8313erdb/sdram.c b/board/freescale/mpc8313erdb/sdram.c index 5e074e3d87..090412d4b6 100644 --- a/board/freescale/mpc8313erdb/sdram.c +++ b/board/freescale/mpc8313erdb/sdram.c @@ -47,7 +47,7 @@ static long fixed_sdram(void) volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; u32 msize_log2 = __ilog2(msize); - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000; im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1); im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE; @@ -57,12 +57,12 @@ static long fixed_sdram(void) */ __udelay(50000); -#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0) +#if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0) #warning Chip select bounds is only configurable in 16MB increments #endif im->ddr.csbnds[0].csbnds = - ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | - (((CONFIG_SYS_DDR_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) & + ((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | + (((CONFIG_SYS_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) & CSBNDS_EA); im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; diff --git a/board/freescale/mpc8315erdb/sdram.c b/board/freescale/mpc8315erdb/sdram.c index b9f94c8332..2f0f29a0e5 100644 --- a/board/freescale/mpc8315erdb/sdram.c +++ b/board/freescale/mpc8315erdb/sdram.c @@ -44,7 +44,7 @@ static long fixed_sdram(void) u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024; u32 msize_log2 = __ilog2(msize); - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000; im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1); im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE; diff --git a/board/freescale/mpc8349emds/mpc8349emds.c b/board/freescale/mpc8349emds/mpc8349emds.c index ea018e5d20..f14276f6a8 100644 --- a/board/freescale/mpc8349emds/mpc8349emds.c +++ b/board/freescale/mpc8349emds/mpc8349emds.c @@ -91,7 +91,7 @@ int fixed_sdram(void) u32 ddr_size = msize << 20; /* DDR size in bytes */ u32 ddr_size_log2 = __ilog2(ddr_size); - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000; im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); #if (CONFIG_SYS_DDR_SIZE != 256) @@ -112,12 +112,12 @@ int fixed_sdram(void) im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL; #else -#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0) +#if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0) #warning Chip select bounds is only configurable in 16MB increments #endif im->ddr.csbnds[2].csbnds = - ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | - (((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >> + ((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | + (((CONFIG_SYS_SDRAM_BASE + ddr_size - 1) >> CSBNDS_EA_SHIFT) & CSBNDS_EA); im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG; diff --git a/board/freescale/mpc8349itx/mpc8349itx.c b/board/freescale/mpc8349itx/mpc8349itx.c index aaaea7ce89..81b3f00b56 100644 --- a/board/freescale/mpc8349itx/mpc8349itx.c +++ b/board/freescale/mpc8349itx/mpc8349itx.c @@ -37,14 +37,14 @@ int fixed_sdram(void) im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000; -#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0) +#if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0) #warning Chip select bounds is only configurable in 16MB increments #endif im->ddr.csbnds[0].csbnds = - ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | - (((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >> + ((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | + (((CONFIG_SYS_SDRAM_BASE + ddr_size - 1) >> CSBNDS_EA_SHIFT) & CSBNDS_EA); im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; diff --git a/board/freescale/mpc837xemds/mpc837xemds.c b/board/freescale/mpc837xemds/mpc837xemds.c index 09a046dff8..16922087c0 100644 --- a/board/freescale/mpc837xemds/mpc837xemds.c +++ b/board/freescale/mpc837xemds/mpc837xemds.c @@ -252,7 +252,7 @@ int fixed_sdram(void) u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024; u32 msize_log2 = __ilog2(msize); - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000; im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1); #if (CONFIG_SYS_DDR_SIZE != 512) diff --git a/board/freescale/mpc837xerdb/mpc837xerdb.c b/board/freescale/mpc837xerdb/mpc837xerdb.c index d9a47b90b2..18f396aac8 100644 --- a/board/freescale/mpc837xerdb/mpc837xerdb.c +++ b/board/freescale/mpc837xerdb/mpc837xerdb.c @@ -95,7 +95,7 @@ int fixed_sdram(void) u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024; u32 msize_log2 = __ilog2(msize); - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000; im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1); im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE; diff --git a/board/gdsys/mpc8308/sdram.c b/board/gdsys/mpc8308/sdram.c index 5ced8eb081..3eb0e37b7b 100644 --- a/board/gdsys/mpc8308/sdram.c +++ b/board/gdsys/mpc8308/sdram.c @@ -34,7 +34,7 @@ static long fixed_sdram(void) u32 msize_log2 = __ilog2(msize); out_be32(&im->sysconf.ddrlaw[0].bar, - CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000); + CONFIG_SYS_SDRAM_BASE & 0xfffff000); out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1)); out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE); @@ -62,7 +62,7 @@ static long fixed_sdram(void) setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN); sync(); - return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize); + return get_ram_size(CONFIG_SYS_SDRAM_BASE, msize); } int dram_init(void) diff --git a/board/ids/ids8313/ids8313.c b/board/ids/ids8313/ids8313.c index a37ca8a2f4..a66234aa85 100644 --- a/board/ids/ids8313/ids8313.c +++ b/board/ids/ids8313/ids8313.c @@ -57,7 +57,7 @@ int fixed_sdram(unsigned long config) u32 msize_log2 = __ilog2(msize); out_be32(&im->sysconf.ddrlaw[0].bar, - (CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000)); + (CONFIG_SYS_SDRAM_BASE & 0xfffff000)); out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1)); out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE); sync(); diff --git a/board/mpc8308_p1m/sdram.c b/board/mpc8308_p1m/sdram.c index 4118c019cc..baf70d8807 100644 --- a/board/mpc8308_p1m/sdram.c +++ b/board/mpc8308_p1m/sdram.c @@ -29,7 +29,7 @@ static long fixed_sdram(void) u32 msize_log2 = __ilog2(msize); out_be32(&im->sysconf.ddrlaw[0].bar, - CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000); + CONFIG_SYS_SDRAM_BASE & 0xfffff000); out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1)); out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE); @@ -57,7 +57,7 @@ static long fixed_sdram(void) setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN); sync(); - return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize); + return get_ram_size(CONFIG_SYS_SDRAM_BASE, msize); } int dram_init(void) diff --git a/board/sbc8349/sbc8349.c b/board/sbc8349/sbc8349.c index 5584b3d179..e51eeae065 100644 --- a/board/sbc8349/sbc8349.c +++ b/board/sbc8349/sbc8349.c @@ -79,19 +79,19 @@ int fixed_sdram(void) u32 ddr_size = msize << 20; /* DDR size in bytes */ u32 ddr_size_log2 = __ilog2(msize); - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000; im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); #if (CONFIG_SYS_DDR_SIZE != 256) #warning Currently any ddr size other than 256 is not supported #endif -#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0) +#if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0) #warning Chip select bounds is only configurable in 16MB increments #endif im->ddr.csbnds[2].csbnds = - ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | - (((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >> + ((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | + (((CONFIG_SYS_SDRAM_BASE + ddr_size - 1) >> CSBNDS_EA_SHIFT) & CSBNDS_EA); im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG; diff --git a/board/ve8313/ve8313.c b/board/ve8313/ve8313.c index 609585bc65..f4148a21e3 100644 --- a/board/ve8313/ve8313.c +++ b/board/ve8313/ve8313.c @@ -38,7 +38,7 @@ static long fixed_sdram(void) u32 msize_log2 = __ilog2(msize); out_be32(&im->sysconf.ddrlaw[0].bar, - (CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000)); + (CONFIG_SYS_SDRAM_BASE & 0xfffff000)); out_be32(&im->sysconf.ddrlaw[0].ar, (LBLAWAR_EN | (msize_log2 - 1))); out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE); @@ -48,12 +48,12 @@ static long fixed_sdram(void) */ __udelay(50000); -#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0) +#if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0) #warning Chip select bounds is only configurable in 16MB increments #endif out_be32(&im->ddr.csbnds[0].csbnds, - ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | - (((CONFIG_SYS_DDR_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) & + ((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | + (((CONFIG_SYS_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) & CSBNDS_EA)); out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG); diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c index 6d018fde2b..e1f69a1d25 100644 --- a/drivers/ddr/fsl/main.c +++ b/drivers/ddr/fsl/main.c @@ -23,8 +23,12 @@ * 0x80_8000_0000 ~ 0xff_ffff_ffff */ #ifndef CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY +#ifdef CONFIG_MPC83xx +#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_SDRAM_BASE +#else #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_DDR_SDRAM_BASE #endif +#endif #ifdef CONFIG_PPC #include diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h index d9361fd8a0..5d31d4a0b6 100644 --- a/include/configs/MPC8308RDB.h +++ b/include/configs/MPC8308RDB.h @@ -37,7 +37,6 @@ * DDR Setup */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ | DDRCDR_PZ_LOZ \ diff --git a/include/configs/MPC8313ERDB_NAND.h b/include/configs/MPC8313ERDB_NAND.h index 08c83996c7..6f100fc7e7 100644 --- a/include/configs/MPC8313ERDB_NAND.h +++ b/include/configs/MPC8313ERDB_NAND.h @@ -87,7 +87,6 @@ * DDR Setup */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE /* * Manually set up DDR parameters, as this board does not diff --git a/include/configs/MPC8313ERDB_NOR.h b/include/configs/MPC8313ERDB_NOR.h index 169cc09d06..0f246dc518 100644 --- a/include/configs/MPC8313ERDB_NOR.h +++ b/include/configs/MPC8313ERDB_NOR.h @@ -59,7 +59,6 @@ * DDR Setup */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE /* * Manually set up DDR parameters, as this board does not diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index c5a229deb4..0b94b0c5cf 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -35,7 +35,6 @@ * DDR Setup */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ | DDRCDR_PZ_LOZ \ diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index 3e6febfc9d..a90a9a86f8 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -24,7 +24,6 @@ * DDR Setup */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #undef CONFIG_SPD_EEPROM #if defined(CONFIG_SPD_EEPROM) diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index 4b3f70c916..88b6f87397 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -21,7 +21,6 @@ * DDR Setup */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDRCDR 0x73000002 /* DDR II voltage is 1.8V */ #undef CONFIG_SPD_EEPROM diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 1a96be0895..fdbd15ea93 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -53,7 +53,6 @@ #undef CONFIG_DDR_32BIT #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) #undef CONFIG_DDR_2T_TIMING diff --git a/include/configs/MPC8349EMDS_SDRAM.h b/include/configs/MPC8349EMDS_SDRAM.h index 311f87b5b3..1e0e297351 100644 --- a/include/configs/MPC8349EMDS_SDRAM.h +++ b/include/configs/MPC8349EMDS_SDRAM.h @@ -53,7 +53,6 @@ #undef CONFIG_DDR_32BIT #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) #undef CONFIG_DDR_2T_TIMING diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index bb3bcfcc44..388910ac38 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -143,7 +143,6 @@ * DDR Setup */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_83XX_DDR_USES_CS0 #define CONFIG_SYS_MEMTEST_START 0x1000 /* memtest region */ #define CONFIG_SYS_MEMTEST_END 0x2000 diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index e34a36cadd..61f9eaf715 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -36,7 +36,6 @@ * DDR Setup */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 #define CONFIG_SYS_83XX_DDR_USES_CS0 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN \ diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index 33d4ced92f..07b206ff9f 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -59,7 +59,6 @@ * DDR Setup */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x03000000 #define CONFIG_SYS_83XX_DDR_USES_CS0 diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index 53fac4d675..0da34d05af 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -25,7 +25,6 @@ */ /* DDR is system memory*/ #define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define DDR_CASLAT_25 /* CASLAT set to 2.5 */ #undef CONFIG_DDR_ECC /* only for ECC DDR module */ #undef CONFIG_SPD_EEPROM /* do not use SPD EEPROM for DDR setup */ diff --git a/include/configs/caddy2.h b/include/configs/caddy2.h index f14e5faafa..928136f325 100644 --- a/include/configs/caddy2.h +++ b/include/configs/caddy2.h @@ -52,7 +52,6 @@ #undef CONFIG_DDR_32BIT #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is sys memory*/ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) #define CONFIG_DDR_2T_TIMING diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h index ae3fcfd3d7..d73e848b0c 100644 --- a/include/configs/hrcon.h +++ b/include/configs/hrcon.h @@ -25,7 +25,6 @@ * DDR Setup */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ | DDRCDR_PZ_LOZ \ diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h index 504a136daa..155815a881 100644 --- a/include/configs/ids8313.h +++ b/include/configs/ids8313.h @@ -52,7 +52,6 @@ * DDR Setup */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE /* * Manually set up DDR parameters, diff --git a/include/configs/kmcoge5ne.h b/include/configs/kmcoge5ne.h index 5c4df18ca6..847996f9a4 100644 --- a/include/configs/kmcoge5ne.h +++ b/include/configs/kmcoge5ne.h @@ -46,7 +46,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h index 2e8affb618..290108d4fc 100644 --- a/include/configs/kmeter1.h +++ b/include/configs/kmeter1.h @@ -31,7 +31,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) diff --git a/include/configs/kmopti2.h b/include/configs/kmopti2.h index 3be53285db..0759604810 100644 --- a/include/configs/kmopti2.h +++ b/include/configs/kmopti2.h @@ -51,7 +51,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) diff --git a/include/configs/kmsupx5.h b/include/configs/kmsupx5.h index 74e719cc79..319e3bc1ec 100644 --- a/include/configs/kmsupx5.h +++ b/include/configs/kmsupx5.h @@ -51,7 +51,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) diff --git a/include/configs/kmtegr1.h b/include/configs/kmtegr1.h index c6913838ce..85e9101b05 100644 --- a/include/configs/kmtegr1.h +++ b/include/configs/kmtegr1.h @@ -58,7 +58,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) diff --git a/include/configs/kmtepr2.h b/include/configs/kmtepr2.h index 4af86195c5..6ec944f942 100644 --- a/include/configs/kmtepr2.h +++ b/include/configs/kmtepr2.h @@ -51,7 +51,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) diff --git a/include/configs/kmvect1.h b/include/configs/kmvect1.h index d8f4d269ed..d7cbdde215 100644 --- a/include/configs/kmvect1.h +++ b/include/configs/kmvect1.h @@ -50,7 +50,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) diff --git a/include/configs/mpc8308_p1m.h b/include/configs/mpc8308_p1m.h index 8836b70b76..0392c3e8b4 100644 --- a/include/configs/mpc8308_p1m.h +++ b/include/configs/mpc8308_p1m.h @@ -40,7 +40,6 @@ * DDR Setup */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ | DDRCDR_PZ_LOZ \ diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index 709387ecf7..b4ae7b7554 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -47,7 +47,6 @@ #undef CONFIG_DDR_32BIT #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) #define CONFIG_DDR_2T_TIMING diff --git a/include/configs/strider.h b/include/configs/strider.h index c01531c3ca..e92bd1e8f1 100644 --- a/include/configs/strider.h +++ b/include/configs/strider.h @@ -25,7 +25,6 @@ * DDR Setup */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ | DDRCDR_PZ_LOZ \ diff --git a/include/configs/suvd3.h b/include/configs/suvd3.h index 3521de8d2e..8b3b45416d 100644 --- a/include/configs/suvd3.h +++ b/include/configs/suvd3.h @@ -48,7 +48,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) diff --git a/include/configs/tuge1.h b/include/configs/tuge1.h index 86e402ae23..5dc9e8997e 100644 --- a/include/configs/tuge1.h +++ b/include/configs/tuge1.h @@ -51,7 +51,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) diff --git a/include/configs/tuxx1.h b/include/configs/tuxx1.h index ec1ac399a0..9f8c855fb8 100644 --- a/include/configs/tuxx1.h +++ b/include/configs/tuxx1.h @@ -51,7 +51,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h index cd6c686b89..2116d6bbcf 100644 --- a/include/configs/ve8313.h +++ b/include/configs/ve8313.h @@ -35,7 +35,6 @@ * DDR Setup */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE /* * Manually set up DDR parameters, as this board does not diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h index 14a84fabc9..1bce6c732d 100644 --- a/include/configs/vme8349.h +++ b/include/configs/vme8349.h @@ -52,7 +52,6 @@ #undef CONFIG_DDR_32BIT #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is sys memory*/ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) #define CONFIG_DDR_2T_TIMING From 42c9a494f1659db6043f980d5f4fdee86fdf9dfb Mon Sep 17 00:00:00 2001 From: Mario Six Date: Mon, 21 Jan 2019 09:18:17 +0100 Subject: [PATCH 54/86] mpc83xx: Get rid of CONFIG_SYS_LBC_* Except for one counter example, CONFIG_SYS_LBC_LBCR always has a value of either 0x00040000 or 0x00000000. CONFIG_SYS_LBC_MRTPR always has the value 0x20000000. CONFIG_SYS_LBC_LSDMR_{1,2,4,5} are not set for any mpc83xx board. CONFIG_SYS_LBC_LSRT is set by one board (to 0x32000000). To simplify the configuration files, hardcode the setting of these values for mpc83xx. Signed-off-by: Mario Six --- board/freescale/mpc8313erdb/sdram.c | 5 +++-- board/freescale/mpc8349emds/mpc8349emds.c | 27 +++++++++++++++-------- board/ids/ids8313/ids8313.c | 4 ++-- board/sbc8349/sbc8349.c | 25 ++++++++++++++------- board/ve8313/ve8313.c | 4 ++-- include/configs/MPC8308RDB.h | 5 ----- include/configs/MPC8313ERDB_NAND.h | 10 --------- include/configs/MPC8313ERDB_NOR.h | 10 --------- include/configs/MPC8315ERDB.h | 6 +---- include/configs/MPC8323ERDB.h | 5 ----- include/configs/MPC832XEMDS.h | 5 ----- include/configs/MPC8349EMDS.h | 8 ------- include/configs/MPC8349EMDS_SDRAM.h | 8 ------- include/configs/MPC8349ITX.h | 13 ----------- include/configs/MPC837XEMDS.h | 4 ---- include/configs/MPC837XERDB.h | 4 ---- include/configs/caddy2.h | 8 ------- include/configs/hrcon.h | 5 ----- include/configs/ids8313.h | 9 -------- include/configs/kmopti2.h | 5 ----- include/configs/kmsupx5.h | 5 ----- include/configs/kmtegr1.h | 5 ----- include/configs/kmtepr2.h | 5 ----- include/configs/kmvect1.h | 5 ----- include/configs/mpc8308_p1m.h | 5 ----- include/configs/sbc8349.h | 8 ------- include/configs/strider.h | 5 ----- include/configs/suvd3.h | 5 ----- include/configs/tuge1.h | 5 ----- include/configs/tuxx1.h | 5 ----- include/configs/ve8313.h | 7 ------ include/configs/vme8349.h | 8 ------- 32 files changed, 43 insertions(+), 195 deletions(-) diff --git a/board/freescale/mpc8313erdb/sdram.c b/board/freescale/mpc8313erdb/sdram.c index 090412d4b6..c8e30a0947 100644 --- a/board/freescale/mpc8313erdb/sdram.c +++ b/board/freescale/mpc8313erdb/sdram.c @@ -109,8 +109,9 @@ int dram_init(void) msize = fixed_sdram(); /* Local Bus setup lbcr and mrtpr */ - lbc->lbcr = CONFIG_SYS_LBC_LBCR; - lbc->mrtpr = CONFIG_SYS_LBC_MRTPR; + lbc->lbcr = (0x00040000 | (0xFF << LBCR_BMT_SHIFT) | 0xF); + /* LB refresh timer prescal, 266MHz/32 */ + lbc->mrtpr = 0x20000000; sync(); #ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC diff --git a/board/freescale/mpc8349emds/mpc8349emds.c b/board/freescale/mpc8349emds/mpc8349emds.c index f14276f6a8..913b5843e9 100644 --- a/board/freescale/mpc8349emds/mpc8349emds.c +++ b/board/freescale/mpc8349emds/mpc8349emds.c @@ -183,28 +183,36 @@ void sdram_init(void) volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile fsl_lbc_t *lbc = &immap->im_lbc; uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; - + const u32 lsdmr_common = LSDMR_RFEN | LSDMR_BSMA1516 | LSDMR_RFCR8 | + LSDMR_PRETOACT6 | LSDMR_ACTTORW3 | LSDMR_BL8 | + LSDMR_WRC3 | LSDMR_CL3; /* * Setup SDRAM Base and Option Registers, already done in cpu_init.c */ /* setup mtrpt, lsrt and lbcr for LB bus */ - lbc->lbcr = CONFIG_SYS_LBC_LBCR; - lbc->mrtpr = CONFIG_SYS_LBC_MRTPR; - lbc->lsrt = CONFIG_SYS_LBC_LSRT; + lbc->lbcr = 0x00000000; + /* LB refresh timer prescal, 266MHz/32 */ + lbc->mrtpr = 0x20000000; + /* LB sdram refresh timer, about 6us */ + lbc->lsrt = 0x32000000; asm("sync"); /* * Configure the SDRAM controller Machine Mode Register. */ - lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */ - lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */ + /* 0x40636733; normal operation */ + lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL; + + /* 0x68636733; precharge all the banks */ + lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL; asm("sync"); *sdram_addr = 0xff; udelay(100); - lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2; /* 0x48636733; auto refresh */ + /* 0x48636733; auto refresh */ + lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH; asm("sync"); /*1 times*/ *sdram_addr = 0xff; @@ -232,12 +240,13 @@ void sdram_init(void) udelay(100); /* 0x58636733; mode register write operation */ - lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4; + lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW; asm("sync"); *sdram_addr = 0xff; udelay(100); - lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */ + /* 0x40636733; normal operation */ + lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL; asm("sync"); *sdram_addr = 0xff; udelay(100); diff --git a/board/ids/ids8313/ids8313.c b/board/ids/ids8313/ids8313.c index a66234aa85..caa36064f0 100644 --- a/board/ids/ids8313/ids8313.c +++ b/board/ids/ids8313/ids8313.c @@ -129,8 +129,8 @@ int dram_init(void) msize = setup_sdram(); - out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR); - out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR); + out_be32(&lbc->lbcr, (0x00040000 | (0xFF << LBCR_BMT_SHIFT) | 0xF)); + out_be32(&lbc->mrtpr, 0x20000000); sync(); gd->ram_size = msize; diff --git a/board/sbc8349/sbc8349.c b/board/sbc8349/sbc8349.c index e51eeae065..a647de6b11 100644 --- a/board/sbc8349/sbc8349.c +++ b/board/sbc8349/sbc8349.c @@ -147,6 +147,9 @@ void sdram_init(void) volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile fsl_lbc_t *lbc = &immap->im_lbc; uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; + const u32 lsdmr_common = LSDMR_RFEN | LSDMR_BSMA1516 | LSDMR_RFCR8 | + LSDMR_PRETOACT6 | LSDMR_ACTTORW3 | LSDMR_BL8 | + LSDMR_WRC3 | LSDMR_CL3; puts("\n SDRAM on Local Bus: "); print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); @@ -156,22 +159,27 @@ void sdram_init(void) */ /* setup mtrpt, lsrt and lbcr for LB bus */ - lbc->lbcr = CONFIG_SYS_LBC_LBCR; - lbc->mrtpr = CONFIG_SYS_LBC_MRTPR; - lbc->lsrt = CONFIG_SYS_LBC_LSRT; + lbc->lbcr = 0x00000000; + /* LB refresh timer prescal, 266MHz/32 */ + lbc->mrtpr = 0x20000000; + /* LB sdram refresh timer, about 6us */ + lbc->lsrt = 0x32000000; asm("sync"); /* * Configure the SDRAM controller Machine Mode Register. */ - lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */ + /* 0x40636733; normal operation */ + lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL; - lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */ + /* 0x68636733; precharge all the banks */ + lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL; asm("sync"); *sdram_addr = 0xff; udelay(100); - lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2; /* 0x48636733; auto refresh */ + /* 0x48636733; auto refresh */ + lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH; asm("sync"); /*1 times*/ *sdram_addr = 0xff; @@ -199,12 +207,13 @@ void sdram_init(void) udelay(100); /* 0x58636733; mode register write operation */ - lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4; + lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW; asm("sync"); *sdram_addr = 0xff; udelay(100); - lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */ + /* 0x40636733; normal operation */ + lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL; asm("sync"); *sdram_addr = 0xff; udelay(100); diff --git a/board/ve8313/ve8313.c b/board/ve8313/ve8313.c index f4148a21e3..1559ff210d 100644 --- a/board/ve8313/ve8313.c +++ b/board/ve8313/ve8313.c @@ -100,8 +100,8 @@ int dram_init(void) msize = fixed_sdram(); /* Local Bus setup lbcr and mrtpr */ - out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR); - out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR); + out_be32(&lbc->lbcr, 0x00040000); + out_be32(&lbc->mrtpr, 0x20000000); sync(); /* return total bus SDRAM size(bytes) -- DDR */ diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h index 5d31d4a0b6..85d7ff6c52 100644 --- a/include/configs/MPC8308RDB.h +++ b/include/configs/MPC8308RDB.h @@ -121,11 +121,6 @@ #define CONFIG_SYS_GBL_DATA_OFFSET \ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -/* - * Local Bus Configuration & Clock Setup - */ -#define CONFIG_SYS_LBC_LBCR 0x00040000 - /* * FLASH on the Local Bus */ diff --git a/include/configs/MPC8313ERDB_NAND.h b/include/configs/MPC8313ERDB_NAND.h index 6f100fc7e7..4153d609be 100644 --- a/include/configs/MPC8313ERDB_NAND.h +++ b/include/configs/MPC8313ERDB_NAND.h @@ -186,16 +186,6 @@ #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ -/* - * Local Bus LCRR and LBCR regs - */ -#define CONFIG_SYS_LBC_LBCR (0x00040000 /* TODO */ \ - | (0xFF << LBCR_BMT_SHIFT) \ - | 0xF) /* 0x0004ff0f */ - - /* LB refresh timer prescal, 266MHz/32 */ -#define CONFIG_SYS_LBC_MRTPR 0x20000000 /*TODO */ - /* drivers/mtd/nand/raw/nand.c */ #if defined(CONFIG_SPL_BUILD) #define CONFIG_SYS_NAND_BASE 0xFFF00000 diff --git a/include/configs/MPC8313ERDB_NOR.h b/include/configs/MPC8313ERDB_NOR.h index 0f246dc518..ff8dedf03e 100644 --- a/include/configs/MPC8313ERDB_NOR.h +++ b/include/configs/MPC8313ERDB_NOR.h @@ -159,16 +159,6 @@ #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ -/* - * Local Bus LCRR and LBCR regs - */ -#define CONFIG_SYS_LBC_LBCR (0x00040000 /* TODO */ \ - | (0xFF << LBCR_BMT_SHIFT) \ - | 0xF) /* 0x0004ff0f */ - - /* LB refresh timer prescal, 266MHz/32 */ -#define CONFIG_SYS_LBC_MRTPR 0x20000000 /*TODO */ - /* drivers/mtd/nand/nand.c */ #define CONFIG_SYS_NAND_BASE 0xE2800000 diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index 0b94b0c5cf..521c5ca6ee 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -116,11 +116,7 @@ #define CONFIG_SYS_GBL_DATA_OFFSET \ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -/* - * Local Bus Configuration & Clock Setup - */ -#define CONFIG_SYS_LBC_LBCR 0x00040000 -#define CONFIG_FSL_ELBC 1 +#define CONFIG_FSL_ELBC /* * FLASH on the Local Bus diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index a90a9a86f8..418c6729e1 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -113,11 +113,6 @@ #define CONFIG_SYS_GBL_DATA_OFFSET \ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -/* - * Local Bus Configuration & Clock Setup - */ -#define CONFIG_SYS_LBC_LBCR 0x00000000 - /* * FLASH on the Local Bus */ diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index 88b6f87397..df9cc48417 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -113,11 +113,6 @@ #define CONFIG_SYS_GBL_DATA_OFFSET \ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -/* - * Local Bus Configuration & Clock Setup - */ -#define CONFIG_SYS_LBC_LBCR 0x00000000 - /* * FLASH on the Local Bus */ diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index fdbd15ea93..7640d7610d 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -153,14 +153,6 @@ #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ -/* - * Local Bus LCRR and LBCR regs - * LCRR: DLL bypass, Clock divider is 4 - * External Local Bus rate is - * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV - */ -#define CONFIG_SYS_LBC_LBCR 0x00000000 - /* * Serial Port */ diff --git a/include/configs/MPC8349EMDS_SDRAM.h b/include/configs/MPC8349EMDS_SDRAM.h index 1e0e297351..493f6df187 100644 --- a/include/configs/MPC8349EMDS_SDRAM.h +++ b/include/configs/MPC8349EMDS_SDRAM.h @@ -150,14 +150,6 @@ #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ -/* - * Local Bus LCRR and LBCR regs - * LCRR: DLL bypass, Clock divider is 4 - * External Local Bus rate is - * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV - */ -#define CONFIG_SYS_LBC_LBCR 0x00000000 - /* * The MPC834xEA MDS for 834xE rev3.1 may not be assembled SDRAM memory. */ diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index 388910ac38..a3f704c73b 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -250,19 +250,6 @@ boards, we say we have two, but don't display a message if we find only one. */ #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ -/* - * Local Bus LCRR and LBCR regs - * LCRR: DLL bypass, Clock divider is 4 - * External Local Bus rate is - * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV - */ -#define CONFIG_SYS_LBC_LBCR 0x00000000 - - /* LB sdram refresh timer, about 6us */ -#define CONFIG_SYS_LBC_LSRT 0x32000000 - /* LB refresh timer prescal, 266MHz/32*/ -#define CONFIG_SYS_LBC_MRTPR 0x20000000 - /* * Serial Port */ diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index 61f9eaf715..724f8afb76 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -134,10 +134,6 @@ #define CONFIG_SYS_GBL_DATA_OFFSET \ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -/* - * Local Bus Configuration & Clock Setup - */ -#define CONFIG_SYS_LBC_LBCR 0x00000000 #define CONFIG_FSL_ELBC 1 /* diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index 07b206ff9f..13a7682958 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -158,10 +158,6 @@ #define CONFIG_SYS_GBL_DATA_OFFSET \ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -/* - * Local Bus Configuration & Clock Setup - */ -#define CONFIG_SYS_LBC_LBCR 0x00000000 #define CONFIG_FSL_ELBC 1 /* diff --git a/include/configs/caddy2.h b/include/configs/caddy2.h index 928136f325..15ac17985f 100644 --- a/include/configs/caddy2.h +++ b/include/configs/caddy2.h @@ -96,14 +96,6 @@ #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB */ #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Malloc size */ -/* - * Local Bus LCRR and LBCR regs - * LCRR: no DLL bypass, Clock divider is 4 - * External Local Bus rate is - * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV - */ -#define CONFIG_SYS_LBC_LBCR 0x00000000 - #undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */ /* diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h index d73e848b0c..8029ae9dd7 100644 --- a/include/configs/hrcon.h +++ b/include/configs/hrcon.h @@ -110,11 +110,6 @@ #define CONFIG_SYS_GBL_DATA_OFFSET \ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -/* - * Local Bus Configuration & Clock Setup - */ -#define CONFIG_SYS_LBC_LBCR 0x00040000 - /* * FLASH on the Local Bus */ diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h index 155815a881..b1d01c58f9 100644 --- a/include/configs/ids8313.h +++ b/include/configs/ids8313.h @@ -36,15 +36,6 @@ - CONFIG_SYS_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET -/* - * Local Bus LCRR and LBCR regs - */ -#define CONFIG_SYS_LBC_LBCR (0x00040000 |\ - (0xFF << LBCR_BMT_SHIFT) |\ - 0xF) - -#define CONFIG_SYS_LBC_MRTPR 0x20000000 - /* * Internal Definitions */ diff --git a/include/configs/kmopti2.h b/include/configs/kmopti2.h index 0759604810..0094f34ef1 100644 --- a/include/configs/kmopti2.h +++ b/include/configs/kmopti2.h @@ -289,11 +289,6 @@ /* EEprom support */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -/* - * Local Bus Configuration & Clock Setup - */ -#define CONFIG_SYS_LBC_LBCR 0x00000000 - #define CONFIG_SYS_APP1_BASE 0xA0000000 /* PAXG */ #define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ #define CONFIG_SYS_APP2_BASE 0xB0000000 /* PINC3 */ diff --git a/include/configs/kmsupx5.h b/include/configs/kmsupx5.h index 319e3bc1ec..5afb969379 100644 --- a/include/configs/kmsupx5.h +++ b/include/configs/kmsupx5.h @@ -289,11 +289,6 @@ /* EEprom support */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -/* - * Local Bus Configuration & Clock Setup - */ -#define CONFIG_SYS_LBC_LBCR 0x00000000 - #define CONFIG_SYS_APP1_BASE 0xA0000000 /* PAXG */ #define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ diff --git a/include/configs/kmtegr1.h b/include/configs/kmtegr1.h index 85e9101b05..4f61ed0346 100644 --- a/include/configs/kmtegr1.h +++ b/include/configs/kmtegr1.h @@ -341,11 +341,6 @@ /* EEprom support */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -/* - * Local Bus Configuration & Clock Setup - */ -#define CONFIG_SYS_LBC_LBCR 0x00000000 - /* must be after the include because KMBEC_FPGA is otherwise undefined */ #define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */ diff --git a/include/configs/kmtepr2.h b/include/configs/kmtepr2.h index 6ec944f942..862fdb7e2d 100644 --- a/include/configs/kmtepr2.h +++ b/include/configs/kmtepr2.h @@ -289,11 +289,6 @@ /* EEprom support */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -/* - * Local Bus Configuration & Clock Setup - */ -#define CONFIG_SYS_LBC_LBCR 0x00000000 - #define CONFIG_SYS_APP1_BASE 0xA0000000 /* PAXG */ #define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ #define CONFIG_SYS_APP2_BASE 0xB0000000 /* PINC3 */ diff --git a/include/configs/kmvect1.h b/include/configs/kmvect1.h index d7cbdde215..802ab9c934 100644 --- a/include/configs/kmvect1.h +++ b/include/configs/kmvect1.h @@ -333,11 +333,6 @@ /* EEprom support */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -/* - * Local Bus Configuration & Clock Setup - */ -#define CONFIG_SYS_LBC_LBCR 0x00000000 - #define CONFIG_SYS_APP1_BASE 0xA0000000 #define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ #define CONFIG_SYS_APP2_BASE 0xB0000000 diff --git a/include/configs/mpc8308_p1m.h b/include/configs/mpc8308_p1m.h index 0392c3e8b4..3ce4b705b7 100644 --- a/include/configs/mpc8308_p1m.h +++ b/include/configs/mpc8308_p1m.h @@ -125,11 +125,6 @@ #define CONFIG_SYS_GBL_DATA_OFFSET \ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -/* - * Local Bus Configuration & Clock Setup - */ -#define CONFIG_SYS_LBC_LBCR 0x00040000 - /* * FLASH on the Local Bus */ diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index b4ae7b7554..d2053cc059 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -123,14 +123,6 @@ #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ -/* - * Local Bus LCRR and LBCR regs - * LCRR: DLL bypass, Clock divider is 4 - * External Local Bus rate is - * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV - */ -#define CONFIG_SYS_LBC_LBCR 0x00000000 - #undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */ /* diff --git a/include/configs/strider.h b/include/configs/strider.h index e92bd1e8f1..22d255aabb 100644 --- a/include/configs/strider.h +++ b/include/configs/strider.h @@ -110,11 +110,6 @@ #define CONFIG_SYS_GBL_DATA_OFFSET \ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -/* - * Local Bus Configuration & Clock Setup - */ -#define CONFIG_SYS_LBC_LBCR 0x00040000 - /* * FLASH on the Local Bus */ diff --git a/include/configs/suvd3.h b/include/configs/suvd3.h index 8b3b45416d..9421204f2c 100644 --- a/include/configs/suvd3.h +++ b/include/configs/suvd3.h @@ -286,11 +286,6 @@ /* EEprom support */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -/* - * Local Bus Configuration & Clock Setup - */ -#define CONFIG_SYS_LBC_LBCR 0x00000000 - #define CONFIG_SYS_APP1_BASE 0xA0000000 #define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ #define CONFIG_SYS_APP2_BASE 0xB0000000 diff --git a/include/configs/tuge1.h b/include/configs/tuge1.h index 5dc9e8997e..3364b5379e 100644 --- a/include/configs/tuge1.h +++ b/include/configs/tuge1.h @@ -289,11 +289,6 @@ /* EEprom support */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -/* - * Local Bus Configuration & Clock Setup - */ -#define CONFIG_SYS_LBC_LBCR 0x00000000 - #define CONFIG_SYS_APP1_BASE 0xA0000000 /* PAXG */ #define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ diff --git a/include/configs/tuxx1.h b/include/configs/tuxx1.h index 9f8c855fb8..db22fe50db 100644 --- a/include/configs/tuxx1.h +++ b/include/configs/tuxx1.h @@ -289,11 +289,6 @@ /* EEprom support */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -/* - * Local Bus Configuration & Clock Setup - */ -#define CONFIG_SYS_LBC_LBCR 0x00000000 - #define CONFIG_SYS_APP1_BASE 0xA0000000 /* PAXG */ #define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ #define CONFIG_SYS_APP2_BASE 0xB0000000 /* PINC3 */ diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h index 2116d6bbcf..66f771d818 100644 --- a/include/configs/ve8313.h +++ b/include/configs/ve8313.h @@ -128,13 +128,6 @@ #define CONFIG_SYS_MONITOR_LEN (384 * 1024) #define CONFIG_SYS_MALLOC_LEN (512 * 1024) -/* - * Local Bus LCRR and LBCR regs - */ -#define CONFIG_SYS_LBC_LBCR 0x00040000 - -#define CONFIG_SYS_LBC_MRTPR 0x20000000 - /* * NAND settings */ diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h index 1bce6c732d..1c3430d849 100644 --- a/include/configs/vme8349.h +++ b/include/configs/vme8349.h @@ -96,14 +96,6 @@ #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB */ #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Malloc size */ -/* - * Local Bus LCRR and LBCR regs - * LCRR: no DLL bypass, Clock divider is 4 - * External Local Bus rate is - * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV - */ -#define CONFIG_SYS_LBC_LBCR 0x00000000 - #undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */ /* From 9fc148ebc413a3eda720d9f74f9a102afacf0fc4 Mon Sep 17 00:00:00 2001 From: Mario Six Date: Mon, 21 Jan 2019 09:18:18 +0100 Subject: [PATCH 55/86] mpc83xx: Add arch clock.h to make SDHC work The fsl-esdhc driver can be used for the SDHC functionality on MPC83xx, but it needs some additional definitions. Add a clock.h file, so we can use the driver for MPC83xx. Signed-off-by: Mario Six --- arch/powerpc/include/asm/arch-mpc83xx/clock.h | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 arch/powerpc/include/asm/arch-mpc83xx/clock.h diff --git a/arch/powerpc/include/asm/arch-mpc83xx/clock.h b/arch/powerpc/include/asm/arch-mpc83xx/clock.h new file mode 100644 index 0000000000..d57e93c2df --- /dev/null +++ b/arch/powerpc/include/asm/arch-mpc83xx/clock.h @@ -0,0 +1,22 @@ +/* + * (C) Copyright 2018 + * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_POWERPC_CLOCK_H +#define __ASM_POWERPC_CLOCK_H + +/* Make fsl_esdhc driver happy */ +enum mxc_clock { + MXC_ESDHC_CLK, +}; + +DECLARE_GLOBAL_DATA_PTR; + +uint mxc_get_clock(int clk) +{ + return gd->arch.sdhc_clk; +} +#endif /* __ASM_POWERPC_CLOCK_H */ From 8835836ae74d1b340f079ce49c3f1cc810452d0d Mon Sep 17 00:00:00 2001 From: Mario Six Date: Mon, 21 Jan 2019 09:18:19 +0100 Subject: [PATCH 56/86] mpc83xx: Don't define cpu_eth_init for DM eth Don't use the legacy method of initializing the ethernet controller on MPC83xx when DM is active. Signed-off-by: Mario Six --- arch/powerpc/cpu/mpc83xx/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/powerpc/cpu/mpc83xx/cpu.c b/arch/powerpc/cpu/mpc83xx/cpu.c index 8a88068fdb..4ea4249aff 100644 --- a/arch/powerpc/cpu/mpc83xx/cpu.c +++ b/arch/powerpc/cpu/mpc83xx/cpu.c @@ -199,6 +199,7 @@ void watchdog_reset (void) } #endif +#ifndef CONFIG_DM_ETH /* * Initializes on-chip ethernet controllers. * to override, implement board_eth_init() @@ -214,6 +215,7 @@ int cpu_eth_init(bd_t *bis) #endif return 0; } +#endif /* !CONFIG_DM_ETH */ /* * Initializes on-chip MMC controllers. From 1e718f43de1bee73fe727597101865f81ff873f5 Mon Sep 17 00:00:00 2001 From: Mario Six Date: Mon, 21 Jan 2019 09:18:20 +0100 Subject: [PATCH 57/86] mpc83xx: Replace ppcDWstore with inline assembly ppcDWstore/ppcDWload are hardly used by any board, but since they're implemented in start.S, they're always present in every U-Boot image, even if they're not needed. Re-implement these fuctions in C with inline assembly, so that the compiler can decide when to actually include them. Signed-off-by: Mario Six --- arch/powerpc/cpu/mpc83xx/cpu.c | 18 ++++++++++++++++++ arch/powerpc/cpu/mpc83xx/start.S | 12 ------------ 2 files changed, 18 insertions(+), 12 deletions(-) diff --git a/arch/powerpc/cpu/mpc83xx/cpu.c b/arch/powerpc/cpu/mpc83xx/cpu.c index 4ea4249aff..9c67099a17 100644 --- a/arch/powerpc/cpu/mpc83xx/cpu.c +++ b/arch/powerpc/cpu/mpc83xx/cpu.c @@ -229,3 +229,21 @@ int cpu_mmc_init(bd_t *bis) return 0; #endif } + +void ppcDWstore(unsigned int *addr, unsigned int *value) +{ + asm("lfd 1, 0(%1)\n\t" + "stfd 1, 0(%0)" + : + : "r" (addr), "r" (value) + : "memory"); +} + +void ppcDWload(unsigned int *addr, unsigned int *ret) +{ + asm("lfd 1, 0(%0)\n\t" + "stfd 1, 0(%1)" + : + : "r" (addr), "r" (ret) + : "memory"); +} diff --git a/arch/powerpc/cpu/mpc83xx/start.S b/arch/powerpc/cpu/mpc83xx/start.S index 9fbbf59ce2..f4a8a766c3 100644 --- a/arch/powerpc/cpu/mpc83xx/start.S +++ b/arch/powerpc/cpu/mpc83xx/start.S @@ -119,18 +119,6 @@ disable_addr_trans: mtspr SRR1, r3 rfi - .globl ppcDWstore -ppcDWstore: - lfd 1, 0(r4) - stfd 1, 0(r3) - blr - - .globl ppcDWload -ppcDWload: - lfd 1, 0(r3) - stfd 1, 0(r4) - blr - #ifndef CONFIG_DEFAULT_IMMR #error CONFIG_DEFAULT_IMMR must be defined #endif /* CONFIG_DEFAULT_IMMR */ From 5c2299850390b31d3262893b407bd26572f04c4e Mon Sep 17 00:00:00 2001 From: Mario Six Date: Mon, 21 Jan 2019 09:18:21 +0100 Subject: [PATCH 58/86] mpc83xx: Use pre-defined asm functions For a lot of inline assembly calls in the mpc8xxx and mpc83xx directories, we already have convenient pre-defined helper functions, but they're not used, resulting in hard-to-read code. Use these helper functions where ever possible and useful. Signed-off-by: Mario Six --- arch/powerpc/cpu/mpc83xx/cpu.c | 19 +++++++-------- arch/powerpc/cpu/mpc83xx/ecc.c | 36 ++++++++++++++-------------- arch/powerpc/cpu/mpc83xx/spd_sdram.c | 36 +++++++++++++++++++++------- arch/powerpc/cpu/mpc8xxx/fsl_pamu.c | 12 +++++----- 4 files changed, 60 insertions(+), 43 deletions(-) diff --git a/arch/powerpc/cpu/mpc83xx/cpu.c b/arch/powerpc/cpu/mpc83xx/cpu.c index 9c67099a17..3048ecf34a 100644 --- a/arch/powerpc/cpu/mpc83xx/cpu.c +++ b/arch/powerpc/cpu/mpc83xx/cpu.c @@ -133,18 +133,18 @@ do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) #ifdef MPC83xx_RESET /* Interrupts and MMU off */ - __asm__ __volatile__ ("mfmsr %0":"=r" (msr):); - - msr &= ~( MSR_EE | MSR_IR | MSR_DR); - __asm__ __volatile__ ("mtmsr %0"::"r" (msr)); + msr = mfmsr(); + msr &= ~(MSR_EE | MSR_IR | MSR_DR); + mtmsr(msr); /* enable Reset Control Reg */ immap->reset.rpr = 0x52535445; - __asm__ __volatile__ ("sync"); - __asm__ __volatile__ ("isync"); + sync(); + isync(); /* confirm Reset Control Reg is enabled */ - while(!((immap->reset.rcer) & RCER_CRE)); + while(!((immap->reset.rcer) & RCER_CRE)) + ; udelay(200); @@ -156,10 +156,9 @@ do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) immap->reset.rmr = RMR_CSRE; /* Checkstop Reset enable */ /* Interrupts and MMU off */ - __asm__ __volatile__ ("mfmsr %0":"=r" (msr):); - + msr = mfmsr(); msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR); - __asm__ __volatile__ ("mtmsr %0"::"r" (msr)); + mtmsr(msr); /* * Trying to execute the next instruction at a non-existing address diff --git a/arch/powerpc/cpu/mpc83xx/ecc.c b/arch/powerpc/cpu/mpc83xx/ecc.c index 73f0be2a30..10e9b96add 100644 --- a/arch/powerpc/cpu/mpc83xx/ecc.c +++ b/arch/powerpc/cpu/mpc83xx/ecc.c @@ -191,8 +191,8 @@ int do_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) } ddr->err_disable = val; - __asm__ __volatile__("sync"); - __asm__ __volatile__("isync"); + sync(); + isync(); return 0; } else if (strcmp(argv[1], "errdetectclr") == 0) { val = ddr->err_detect; @@ -249,8 +249,8 @@ int do_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) printf("Incorrect command\n"); ddr->ecc_err_inject = val; - __asm__ __volatile__("sync"); - __asm__ __volatile__("isync"); + sync(); + isync(); return 0; } else if (strcmp(argv[1], "mirror") == 0) { val = ddr->ecc_err_inject; @@ -282,26 +282,26 @@ int do_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) /* enable injects */ ddr->ecc_err_inject |= ECC_ERR_INJECT_EIEN; - __asm__ __volatile__("sync"); - __asm__ __volatile__("isync"); + sync(); + isync(); /* write memory location injecting errors */ ppcDWstore((u32 *) i, pattern); - __asm__ __volatile__("sync"); + sync(); /* disable injects */ ddr->ecc_err_inject &= ~ECC_ERR_INJECT_EIEN; - __asm__ __volatile__("sync"); - __asm__ __volatile__("isync"); + sync(); + isync(); /* read data, this generates ECC error */ ppcDWload((u32 *) i, ret); - __asm__ __volatile__("sync"); + sync(); /* re-initialize memory, double word write the location again, * generates new ECC code this time */ ppcDWstore((u32 *) i, writeback); - __asm__ __volatile__("sync"); + sync(); } enable_interrupts(); return 0; @@ -321,29 +321,29 @@ int do_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) /* enable injects */ ddr->ecc_err_inject |= ECC_ERR_INJECT_EIEN; - __asm__ __volatile__("sync"); - __asm__ __volatile__("isync"); + sync(); + isync(); /* write memory location injecting errors */ *(u32 *) i = 0xfedcba98UL; - __asm__ __volatile__("sync"); + sync(); /* sub double word write, * bus will read-modify-write, * generates ECC error */ *((u32 *) i + 1) = 0x76543210UL; - __asm__ __volatile__("sync"); + sync(); /* disable injects */ ddr->ecc_err_inject &= ~ECC_ERR_INJECT_EIEN; - __asm__ __volatile__("sync"); - __asm__ __volatile__("isync"); + sync(); + isync(); /* re-initialize memory, * double word write the location again, * generates new ECC code this time */ ppcDWstore((u32 *) i, writeback); - __asm__ __volatile__("sync"); + sync(); } enable_interrupts(); return 0; diff --git a/arch/powerpc/cpu/mpc83xx/spd_sdram.c b/arch/powerpc/cpu/mpc83xx/spd_sdram.c index 5ca307ca58..8b5ecdb9ad 100644 --- a/arch/powerpc/cpu/mpc83xx/spd_sdram.c +++ b/arch/powerpc/cpu/mpc83xx/spd_sdram.c @@ -436,7 +436,7 @@ long int spd_sdram() else if (caslat == 4) ddr->debug_reg = 0x202c0000; /* CL=3.0 */ - __asm__ __volatile__ ("sync"); + sync(); debug("Errata DDR6 (debug_reg=0x%08x)\n", ddr->debug_reg); } @@ -765,7 +765,8 @@ long int spd_sdram() #endif debug("DDR:sdram_clk_cntl=0x%08x\n", ddr->sdram_clk_cntl); - asm("sync;isync"); + sync(); + isync(); udelay(600); @@ -834,7 +835,8 @@ long int spd_sdram() #endif /* Enable controller, and GO! */ ddr->sdram_cfg = sdram_cfg; - asm("sync;isync"); + sync(); + isync(); udelay(500); debug("DDR:sdram_cfg=0x%08x\n", ddr->sdram_cfg); @@ -843,6 +845,22 @@ long int spd_sdram() #endif /* CONFIG_SPD_EEPROM */ #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) +static inline u32 mftbu(void) +{ + u32 rval; + + asm volatile("mftbu %0" : "=r" (rval)); + return rval; +} + +static inline u32 mftb(void) +{ + u32 rval; + + asm volatile("mftb %0" : "=r" (rval)); + return rval; +} + /* * Use timebase counter, get_timer() is not available * at this point of initialization yet. @@ -858,9 +876,9 @@ static __inline__ unsigned long get_tbms (void) /* get the timebase ticks */ do { - asm volatile ("mftbu %0":"=r" (tbu1):); - asm volatile ("mftb %0":"=r" (tbl):); - asm volatile ("mftbu %0":"=r" (tbu2):); + tbu1 = mftbu(); + tbl = mftb(); + tbu2 = mftbu(); } while (tbu1 != tbu2); /* convert ticks to ms */ @@ -897,7 +915,7 @@ void ddr_enable_ecc(unsigned int dram_size) for (p = 0; p < (u64*)(size); p++) { ppcDWstore((u32*)p, pattern); } - __asm__ __volatile__ ("sync"); + sync(); #endif t_end = get_tbms(); @@ -922,8 +940,8 @@ void ddr_enable_ecc(unsigned int dram_size) /* Enable errors for ECC */ ddr->err_disable &= ECC_ERROR_ENABLE; - __asm__ __volatile__ ("sync"); - __asm__ __volatile__ ("isync"); + sync(); + isync(); } #endif /* CONFIG_DDR_ECC */ diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c b/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c index 23cc5a32ac..d81af70f44 100644 --- a/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c +++ b/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c @@ -131,10 +131,10 @@ static int pamu_config_ppaace(uint32_t liodn, uint64_t win_addr, set_bf(ppaace->addr_bitfields, PAACE_AF_AP, PAACE_AP_PERMS_ALL); } - asm volatile("sync" : : : "memory"); + sync(); /* Mark the ppace entry valid */ ppaace->addr_bitfields |= PAACE_V_VALID; - asm volatile("sync" : : : "memory"); + sync(); return 0; } @@ -279,7 +279,7 @@ int pamu_init(void) out_be32(®s->splah, spaact_lim >> 32); out_be32(®s->splal, (uint32_t)spaact_lim); } - asm volatile("sync" : : : "memory"); + sync(); base_addr += PAMU_OFFSET; } @@ -294,7 +294,7 @@ void pamu_enable(void) for (i = 0; i < CONFIG_NUM_PAMU; i++) { setbits_be32((void *)base_addr + PAMU_PCR_OFFSET, PAMU_PCR_PE); - asm volatile("sync" : : : "memory"); + sync(); base_addr += PAMU_OFFSET; } } @@ -318,7 +318,7 @@ void pamu_reset(void) out_be32(®s->splal, 0); clrbits_be32((void *)regs + PAMU_PCR_OFFSET, PAMU_PCR_PE); - asm volatile("sync" : : : "memory"); + sync(); base_addr += PAMU_OFFSET; } } @@ -331,7 +331,7 @@ void pamu_disable(void) for (i = 0; i < CONFIG_NUM_PAMU; i++) { clrbits_be32((void *)base_addr + PAMU_PCR_OFFSET, PAMU_PCR_PE); - asm volatile("sync" : : : "memory"); + sync(); base_addr += PAMU_OFFSET; } } From 8ed9876bf27340971b60d6fc0ca66c052164cacd Mon Sep 17 00:00:00 2001 From: Mario Six Date: Mon, 21 Jan 2019 09:18:22 +0100 Subject: [PATCH 59/86] keymile: Remove CONFIG_SYS_APP{1, 2}_{BASE, SIZE} CONFIG_SYS_APP1_BASE, CONFIG_SYS_APP2_BASE, CONFIG_SYS_APP1_SIZE, and CONFIG_SYS_APP2_SIZE are no longer used in the keymile config files (they were used for setting values, which were converted to Kconfig earlier in the series). Remove them from the configs and the whitelist. Signed-off-by: Mario Six --- include/configs/kmopti2.h | 5 ----- include/configs/kmsupx5.h | 3 --- include/configs/kmtegr1.h | 5 ----- include/configs/kmtepr2.h | 5 ----- include/configs/kmvect1.h | 5 ----- include/configs/suvd3.h | 5 ----- include/configs/tuge1.h | 3 --- include/configs/tuxx1.h | 5 ----- scripts/config_whitelist.txt | 4 ---- 9 files changed, 40 deletions(-) diff --git a/include/configs/kmopti2.h b/include/configs/kmopti2.h index 0094f34ef1..f1b7c2f02e 100644 --- a/include/configs/kmopti2.h +++ b/include/configs/kmopti2.h @@ -289,11 +289,6 @@ /* EEprom support */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_APP1_BASE 0xA0000000 /* PAXG */ -#define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ -#define CONFIG_SYS_APP2_BASE 0xB0000000 /* PINC3 */ -#define CONFIG_SYS_APP2_SIZE 256 /* Megabytes */ - /* * Init Local Bus Memory Controller: * Device on board diff --git a/include/configs/kmsupx5.h b/include/configs/kmsupx5.h index 5afb969379..0dd7420e8c 100644 --- a/include/configs/kmsupx5.h +++ b/include/configs/kmsupx5.h @@ -289,9 +289,6 @@ /* EEprom support */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_APP1_BASE 0xA0000000 /* PAXG */ -#define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ - /* * Init Local Bus Memory Controller: * Device on board diff --git a/include/configs/kmtegr1.h b/include/configs/kmtegr1.h index 4f61ed0346..8f9bbefa7f 100644 --- a/include/configs/kmtegr1.h +++ b/include/configs/kmtegr1.h @@ -344,11 +344,6 @@ /* must be after the include because KMBEC_FPGA is otherwise undefined */ #define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */ -#define CONFIG_SYS_APP1_BASE 0xA0000000 -#define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ -#define CONFIG_SYS_APP2_BASE 0xB0000000 -#define CONFIG_SYS_APP2_SIZE 256 /* Megabytes */ - /* EEprom support */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 diff --git a/include/configs/kmtepr2.h b/include/configs/kmtepr2.h index 862fdb7e2d..b77219f72c 100644 --- a/include/configs/kmtepr2.h +++ b/include/configs/kmtepr2.h @@ -289,11 +289,6 @@ /* EEprom support */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_APP1_BASE 0xA0000000 /* PAXG */ -#define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ -#define CONFIG_SYS_APP2_BASE 0xB0000000 /* PINC3 */ -#define CONFIG_SYS_APP2_SIZE 256 /* Megabytes */ - /* * Init Local Bus Memory Controller: * Device on board diff --git a/include/configs/kmvect1.h b/include/configs/kmvect1.h index 802ab9c934..785475ef45 100644 --- a/include/configs/kmvect1.h +++ b/include/configs/kmvect1.h @@ -333,11 +333,6 @@ /* EEprom support */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_APP1_BASE 0xA0000000 -#define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ -#define CONFIG_SYS_APP2_BASE 0xB0000000 -#define CONFIG_SYS_APP2_SIZE 256 /* Megabytes */ - /* EEprom support */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 diff --git a/include/configs/suvd3.h b/include/configs/suvd3.h index 9421204f2c..456cd9dd70 100644 --- a/include/configs/suvd3.h +++ b/include/configs/suvd3.h @@ -286,11 +286,6 @@ /* EEprom support */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_APP1_BASE 0xA0000000 -#define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ -#define CONFIG_SYS_APP2_BASE 0xB0000000 -#define CONFIG_SYS_APP2_SIZE 256 /* Megabytes */ - /* EEprom support */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 diff --git a/include/configs/tuge1.h b/include/configs/tuge1.h index 3364b5379e..01d8d6b303 100644 --- a/include/configs/tuge1.h +++ b/include/configs/tuge1.h @@ -289,9 +289,6 @@ /* EEprom support */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_APP1_BASE 0xA0000000 /* PAXG */ -#define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ - /* * Init Local Bus Memory Controller: * Device on board diff --git a/include/configs/tuxx1.h b/include/configs/tuxx1.h index db22fe50db..15a69ceca7 100644 --- a/include/configs/tuxx1.h +++ b/include/configs/tuxx1.h @@ -289,11 +289,6 @@ /* EEprom support */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_APP1_BASE 0xA0000000 /* PAXG */ -#define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ -#define CONFIG_SYS_APP2_BASE 0xB0000000 /* PINC3 */ -#define CONFIG_SYS_APP2_SIZE 256 /* Megabytes */ - /* * Init Local Bus Memory Controller: * Device on board diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 992bcc3d8f..5ec4ffbeae 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -1935,10 +1935,6 @@ CONFIG_SYS_AMASK4 CONFIG_SYS_AMASK5 CONFIG_SYS_AMASK6 CONFIG_SYS_AMASK7 -CONFIG_SYS_APP1_BASE -CONFIG_SYS_APP1_SIZE -CONFIG_SYS_APP2_BASE -CONFIG_SYS_APP2_SIZE CONFIG_SYS_ARM_CACHE_WRITETHROUGH CONFIG_SYS_AT91_CPU_NAME CONFIG_SYS_AT91_MAIN_CLOCK From aed7d0e399c8cf1c0f70d28a22144b4c94ff45ad Mon Sep 17 00:00:00 2001 From: Mario Six Date: Mon, 21 Jan 2019 09:18:23 +0100 Subject: [PATCH 60/86] keymile: Factor out common includes again Not that the Kconfig conversion of a lot of variables is done, we can factor out the common include files for the keymile boards again (which now contain hardly any #ifdef logic at all). Signed-off-by: Mario Six --- include/configs/km/km-mpc8309.h | 137 +++++++++++++ include/configs/km/km-mpc832x.h | 91 +++++++++ include/configs/km/km-mpc8360.h | 91 +++++++++ include/configs/km/km-mpc83xx.h | 160 +++++++++++++++ include/configs/kmcoge5ne.h | 262 +------------------------ include/configs/kmeter1.h | 258 +------------------------ include/configs/kmopti2.h | 286 +-------------------------- include/configs/kmsupx5.h | 277 +------------------------- include/configs/kmtegr1.h | 331 +------------------------------ include/configs/kmtepr2.h | 278 +------------------------- include/configs/kmvect1.h | 332 +------------------------------- include/configs/suvd3.h | 278 +------------------------- include/configs/tuge1.h | 277 +------------------------- include/configs/tuxx1.h | 278 +------------------------- 14 files changed, 500 insertions(+), 2836 deletions(-) create mode 100644 include/configs/km/km-mpc8309.h create mode 100644 include/configs/km/km-mpc832x.h create mode 100644 include/configs/km/km-mpc8360.h create mode 100644 include/configs/km/km-mpc83xx.h diff --git a/include/configs/km/km-mpc8309.h b/include/configs/km/km-mpc8309.h new file mode 100644 index 0000000000..e89b7af061 --- /dev/null +++ b/include/configs/km/km-mpc8309.h @@ -0,0 +1,137 @@ +/* + * High Level Configuration Options + */ +#define CONFIG_E300 1 /* E300 family */ +#define CONFIG_QE 1 /* Has QE */ + +#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" + +/* + * System Clock Setup + */ +#define CONFIG_83XX_CLKIN 66000000 +#define CONFIG_SYS_CLK_FREQ 66000000 +#define CONFIG_83XX_PCICLK 66000000 + +/* QE microcode/firmware address */ +#define CONFIG_SYS_QE_FMAN_FW_IN_NOR +/* between the u-boot partition and env */ +#ifndef CONFIG_SYS_QE_FW_ADDR +#define CONFIG_SYS_QE_FW_ADDR 0xF00C0000 +#endif + +/* + * System IO Config + */ +/* 0x14000180 SICR_1 */ +#define CONFIG_SYS_SICRL (0 \ + | SICR_1_UART1_UART1RTS \ + | SICR_1_I2C_CKSTOP \ + | SICR_1_IRQ_A_IRQ \ + | SICR_1_IRQ_B_IRQ \ + | SICR_1_GPIO_A_GPIO \ + | SICR_1_GPIO_B_GPIO \ + | SICR_1_GPIO_C_GPIO \ + | SICR_1_GPIO_D_GPIO \ + | SICR_1_GPIO_E_GPIO \ + | SICR_1_GPIO_F_GPIO \ + | SICR_1_USB_A_UART2S \ + | SICR_1_USB_B_UART2RTS \ + | SICR_1_FEC1_FEC1 \ + | SICR_1_FEC2_FEC2 \ + ) + +/* 0x00080400 SICR_2 */ +#define CONFIG_SYS_SICRH (0 \ + | SICR_2_FEC3_FEC3 \ + | SICR_2_HDLC1_A_HDLC1 \ + | SICR_2_ELBC_A_LA \ + | SICR_2_ELBC_B_LCLK \ + | SICR_2_HDLC2_A_HDLC2 \ + | SICR_2_USB_D_GPIO \ + | SICR_2_PCI_PCI \ + | SICR_2_HDLC1_B_HDLC1 \ + | SICR_2_HDLC1_C_HDLC1 \ + | SICR_2_HDLC2_B_GPIO \ + | SICR_2_HDLC2_C_HDLC2 \ + | SICR_2_QUIESCE_B \ + ) + +/* GPR_1 */ +#define CONFIG_SYS_GPR1 0x50008060 + +#define CONFIG_SYS_GP1DIR 0x00000000 +#define CONFIG_SYS_GP1ODR 0x00000000 +#define CONFIG_SYS_GP2DIR 0xFF000000 +#define CONFIG_SYS_GP2ODR 0x00000000 + +#define CONFIG_SYS_DDRCDR (\ + DDRCDR_EN | \ + DDRCDR_PZ_MAXZ | \ + DDRCDR_NZ_MAXZ | \ + DDRCDR_M_ODR) + +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f +#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ + SDRAM_CFG_32_BE | \ + SDRAM_CFG_SREN | \ + SDRAM_CFG_HSE) + +#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 +#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) +#define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ + (0x200 << SDRAM_INTERVAL_REFINT_SHIFT)) + +#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ + CSCONFIG_ODT_RD_NEVER | \ + CSCONFIG_ODT_WR_ONLY_CURRENT | \ + CSCONFIG_ROW_BIT_13 | \ + CSCONFIG_COL_BIT_10) + +#define CONFIG_SYS_DDR_MODE 0x47860242 +#define CONFIG_SYS_DDR_MODE2 0x8080c000 + +#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ + (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ + (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ + (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ + (0 << TIMING_CFG0_WWT_SHIFT) | \ + (0 << TIMING_CFG0_RRT_SHIFT) | \ + (0 << TIMING_CFG0_WRT_SHIFT) | \ + (0 << TIMING_CFG0_RWT_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \ + (2 << TIMING_CFG1_WRTORD_SHIFT) | \ + (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ + (3 << TIMING_CFG1_WRREC_SHIFT) | \ + (7 << TIMING_CFG1_REFREC_SHIFT) | \ + (3 << TIMING_CFG1_ACTTORW_SHIFT) | \ + (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ + (3 << TIMING_CFG1_PRETOACT_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ + (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ + (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ + (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ + (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ + (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \ + (5 << TIMING_CFG2_CPO_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_3 0x00000000 + +#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000 +#define CONFIG_SYS_KMBEC_FPGA_SIZE 128 + +/* EEprom support */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 + +/* ethernet port connected to piggy (UEC2) */ +#define CONFIG_HAS_ETH1 +#define CONFIG_UEC_ETH2 +#define CONFIG_SYS_UEC2_UCC_NUM 2 /* UCC3 */ +#define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ +#define CONFIG_SYS_UEC2_TX_CLK QE_CLK12 +#define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH +#define CONFIG_SYS_UEC2_PHY_ADDR 0 +#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII +#define CONFIG_SYS_UEC2_INTERFACE_SPEED 100 diff --git a/include/configs/km/km-mpc832x.h b/include/configs/km/km-mpc832x.h new file mode 100644 index 0000000000..3c2173d364 --- /dev/null +++ b/include/configs/km/km-mpc832x.h @@ -0,0 +1,91 @@ +/* + * High Level Configuration Options + */ +#define CONFIG_QE /* Has QE */ +#define CONFIG_KM8321 /* Keymile PBEC8321 board specific */ + +/* + * System Clock Setup + */ +#define CONFIG_83XX_CLKIN 66000000 +#define CONFIG_SYS_CLK_FREQ 66000000 +#define CONFIG_83XX_PCICLK 66000000 + +/* + * QE UEC ethernet configuration + */ +#define CONFIG_UEC_ETH1 /* GETH1 */ +#define UEC_VERBOSE_DEBUG 1 + +#define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */ +#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ +#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17 +#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH +#define CONFIG_SYS_UEC1_PHY_ADDR 0 +#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII +#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 + +/* + * System IO Config + */ +#define CONFIG_SYS_SICRL SICRL_IRQ_CKS + +#define CONFIG_SYS_DDRCDR (\ + DDRCDR_EN | \ + DDRCDR_PZ_MAXZ | \ + DDRCDR_NZ_MAXZ | \ + DDRCDR_M_ODR) + +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f +#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ + SDRAM_CFG_32_BE | \ + SDRAM_CFG_SREN | \ + SDRAM_CFG_HSE) + +#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 +#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) +#define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ + (0x200 << SDRAM_INTERVAL_REFINT_SHIFT)) + +#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ + CSCONFIG_ODT_WR_CFG | \ + CSCONFIG_ROW_BIT_13 | \ + CSCONFIG_COL_BIT_10) + +#define CONFIG_SYS_DDR_MODE 0x47860242 +#define CONFIG_SYS_DDR_MODE2 0x8080c000 + +#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ + (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ + (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ + (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ + (0 << TIMING_CFG0_WWT_SHIFT) | \ + (0 << TIMING_CFG0_RRT_SHIFT) | \ + (0 << TIMING_CFG0_WRT_SHIFT) | \ + (0 << TIMING_CFG0_RWT_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \ + (2 << TIMING_CFG1_WRTORD_SHIFT) | \ + (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ + (3 << TIMING_CFG1_WRREC_SHIFT) | \ + (7 << TIMING_CFG1_REFREC_SHIFT) | \ + (3 << TIMING_CFG1_ACTTORW_SHIFT) | \ + (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ + (3 << TIMING_CFG1_PRETOACT_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ + (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ + (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ + (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ + (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ + (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \ + (5 << TIMING_CFG2_CPO_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_3 0x00000000 + +#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000 +#define CONFIG_SYS_KMBEC_FPGA_SIZE 128 + +/* EEprom support */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 + diff --git a/include/configs/km/km-mpc8360.h b/include/configs/km/km-mpc8360.h new file mode 100644 index 0000000000..8f26e059e9 --- /dev/null +++ b/include/configs/km/km-mpc8360.h @@ -0,0 +1,91 @@ +/* KMBEC FPGA (PRIO) */ +#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000 +#define CONFIG_SYS_KMBEC_FPGA_SIZE 64 + +/* + * High Level Configuration Options + */ +#define CONFIG_QE /* Has QE */ + +/* + * QE UEC ethernet configuration + */ +#define CONFIG_UEC_ETH1 /* GETH1 */ +#define UEC_VERBOSE_DEBUG 1 + +#define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */ +#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ +#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17 +#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH +#define CONFIG_SYS_UEC1_PHY_ADDR 0 +#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII +#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 + +/* + * System IO Setup + */ +#define CONFIG_SYS_SICRH (SICRH_UC1EOBI | SICRH_UC2E1OBI) + +/** + * DDR RAM settings + */ +#define CONFIG_SYS_DDR_SDRAM_CFG (\ + SDRAM_CFG_SDRAM_TYPE_DDR2 | \ + SDRAM_CFG_SREN | \ + SDRAM_CFG_HSE) + +#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 + +#define CONFIG_SYS_DDR_CLK_CNTL (\ + DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) + +#define CONFIG_SYS_DDR_INTERVAL (\ + (0x080 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ + (0x203 << SDRAM_INTERVAL_REFINT_SHIFT)) + +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f + +#define CONFIG_SYS_DDRCDR (\ + DDRCDR_EN | \ + DDRCDR_Q_DRN) +#define CONFIG_SYS_DDR_MODE 0x47860452 +#define CONFIG_SYS_DDR_MODE2 0x8080c000 + +#define CONFIG_SYS_DDR_TIMING_0 (\ + (2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ + (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ + (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ + (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ + (0 << TIMING_CFG0_WWT_SHIFT) | \ + (0 << TIMING_CFG0_RRT_SHIFT) | \ + (0 << TIMING_CFG0_WRT_SHIFT) | \ + (0 << TIMING_CFG0_RWT_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \ + (2 << TIMING_CFG1_WRTORD_SHIFT) | \ + (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ + (3 << TIMING_CFG1_WRREC_SHIFT) | \ + (7 << TIMING_CFG1_REFREC_SHIFT) | \ + (3 << TIMING_CFG1_ACTTORW_SHIFT) | \ + (8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ + (3 << TIMING_CFG1_PRETOACT_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_2 (\ + (0xa << TIMING_CFG2_FOUR_ACT_SHIFT) | \ + (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ + (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ + (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ + (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ + (5 << TIMING_CFG2_CPO_SHIFT) | \ + (0 << TIMING_CFG2_ADD_LAT_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_3 0x00000000 + +/* EEprom support */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 + +/* + * PAXE on the local bus CS3 + */ +#define CONFIG_SYS_PAXE_BASE 0xA0000000 +#define CONFIG_SYS_PAXE_SIZE 256 diff --git a/include/configs/km/km-mpc83xx.h b/include/configs/km/km-mpc83xx.h new file mode 100644 index 0000000000..455e5236de --- /dev/null +++ b/include/configs/km/km-mpc83xx.h @@ -0,0 +1,160 @@ +/* + * Internal Definitions + */ +#define BOOTFLASH_START 0xF0000000 + +#define CONFIG_KM_CONSOLE_TTY "ttyS0" + +/* + * DDR Setup + */ +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ +#define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */ + +#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ + DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) + +#define CFG_83XX_DDR_USES_CS0 + +/* + * Manually set up DDR parameters + */ +#define CONFIG_DDR_II +#define CONFIG_SYS_DDR_SIZE 2048 /* MB */ + +/* + * The reserved memory + */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#define CONFIG_SYS_FLASH_BASE 0xF0000000 + +#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) +#define CONFIG_SYS_RAMBOOT +#endif + +/* Reserve 768 kB for Mon */ +#define CONFIG_SYS_MONITOR_LEN (768 * 1024) + +/* + * Initial RAM Base Address Setup + */ +#define CONFIG_SYS_INIT_RAM_LOCK +#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +/* + * Init Local Bus Memory Controller: + * + * Bank Bus Machine PortSz Size Device + * ---- --- ------- ------ ----- ------ + * 0 Local GPCM 16 bit 256MB FLASH + * 1 Local GPCM 8 bit 128MB GPIO/PIGGY + * + */ + +/* + * FLASH on the Local Bus + */ +#define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } + +/* + * Serial Port + */ +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_NUM_I2C_BUSES 4 +#define CONFIG_SYS_I2C_MAX_HOPS 1 +#define CONFIG_SYS_I2C_FSL +#define CONFIG_SYS_FSL_I2C_SPEED 200000 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C_OFFSET 0x3000 +#define CONFIG_SYS_FSL_I2C2_SPEED 200000 +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 +#define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \ + {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \ + {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \ + {1, {I2C_NULL_HOP} } } + +#define CONFIG_KM_IVM_BUS 2 /* I2C2 (Mux-Port 1)*/ + +#if defined(CONFIG_CMD_NAND) +#define CONFIG_NAND_KMETER1 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE +#endif + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) + +/* + * Environment + */ + +#ifndef CONFIG_SYS_RAMBOOT +#ifndef CONFIG_ENV_ADDR +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ + CONFIG_SYS_MONITOR_LEN) +#endif +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ +#ifndef CONFIG_ENV_OFFSET +#define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN) +#endif + +/* Address and size of Redundant Environment Sector */ +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ + CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) + +#else /* CFG_SYS_RAMBOOT */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) +#define CONFIG_ENV_SIZE 0x2000 +#endif /* CFG_SYS_RAMBOOT */ + +/* + * Environment Configuration + */ +#define CONFIG_ENV_OVERWRITE +#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ +#define CONFIG_KM_DEF_ENV "km-common=empty\0" +#endif + +#ifndef CONFIG_KM_DEF_ARCH +#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_KM_DEF_ENV \ + CONFIG_KM_DEF_ARCH \ + "newenv=" \ + "prot off " __stringify(CONFIG_ENV_ADDR) " +0x40000 && " \ + "era " __stringify(CONFIG_ENV_ADDR) " +0x40000\0" \ + "unlock=yes\0" \ + "" + +#if defined(CONFIG_UEC_ETH) +#define CONFIG_HAS_ETH0 +#endif + +/* + * QE UEC ethernet configuration + */ +#define CONFIG_UEC_ETH +#define CONFIG_ETHPRIME "UEC0" diff --git a/include/configs/kmcoge5ne.h b/include/configs/kmcoge5ne.h index 847996f9a4..fc78b27cbb 100644 --- a/include/configs/kmcoge5ne.h +++ b/include/configs/kmcoge5ne.h @@ -8,10 +8,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -/* KMBEC FPGA (PRIO) */ -#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000 -#define CONFIG_SYS_KMBEC_FPGA_SIZE 64 - #define CONFIG_HOSTNAME "kmcoge5ne" #define CONFIG_KM_BOARD_NAME "kmcoge5ne" #define CONFIG_KM_DEF_NETDEV "netdev=eth1\0" @@ -24,14 +20,11 @@ #define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0" #define CONFIG_KM_UBI_PARTITION_NAME_APP "ubi1" -/* - * High Level Configuration Options - */ -#define CONFIG_QE /* Has QE */ - /* include common defines/options for all Keymile boards */ #include "km/keymile-common.h" #include "km/km-powerpc.h" +#include "km/km-mpc83xx.h" +#include "km/km-mpc8360.h" /* * System Clock Setup @@ -40,201 +33,6 @@ #define CONFIG_SYS_CLK_FREQ 66000000 #define CONFIG_83XX_PCICLK 66000000 -/* - * DDR Setup - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */ - -#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ - DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) - -#define CFG_83XX_DDR_USES_CS0 - -/* - * Manually set up DDR parameters - */ -#define CONFIG_DDR_II -#define CONFIG_SYS_DDR_SIZE 2048 /* MB */ - -/* - * The reserved memory - */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ -#define CONFIG_SYS_FLASH_BASE 0xF0000000 - -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT -#endif - -/* Reserve 768 kB for Mon */ -#define CONFIG_SYS_MONITOR_LEN (768 * 1024) - -/* - * Initial RAM Base Address Setup - */ -#define CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) - -/* - * Init Local Bus Memory Controller: - * - * Bank Bus Machine PortSz Size Device - * ---- --- ------- ------ ----- ------ - * 0 Local GPCM 16 bit 256MB FLASH - * 1 Local GPCM 8 bit 128MB GPIO/PIGGY - * - */ -/* - * FLASH on the Local Bus - */ -#define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ - - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } - -/* - * PRIO1/PIGGY on the local bus CS1 - */ - - -/* - * Serial Port - */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) - -/* - * QE UEC ethernet configuration - */ -#define CONFIG_UEC_ETH -#define CONFIG_ETHPRIME "UEC0" - -#define CONFIG_UEC_ETH1 /* GETH1 */ -#define UEC_VERBOSE_DEBUG 1 - -#ifdef CONFIG_UEC_ETH1 -#define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */ -#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ -#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17 -#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH -#define CONFIG_SYS_UEC1_PHY_ADDR 0 -#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII -#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 -#endif - -/* - * Environment - */ - -#ifndef CONFIG_SYS_RAMBOOT -#ifndef CONFIG_ENV_ADDR -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ - CONFIG_SYS_MONITOR_LEN) -#endif -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ -#ifndef CONFIG_ENV_OFFSET -#define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN) -#endif - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#else /* CFG_SYS_RAMBOOT */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) -#define CONFIG_ENV_SIZE 0x2000 -#endif /* CFG_SYS_RAMBOOT */ - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_NUM_I2C_BUSES 4 -#define CONFIG_SYS_I2C_MAX_HOPS 1 -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 200000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_I2C_OFFSET 0x3000 -#define CONFIG_SYS_FSL_I2C2_SPEED 200000 -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 -#define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \ - {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \ - {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \ - {1, {I2C_NULL_HOP} } } - -#define CONFIG_KM_IVM_BUS 2 /* I2C2 (Mux-Port 1)*/ - -#if defined(CONFIG_CMD_NAND) -#define CONFIG_NAND_KMETER1 -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE -#endif - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) - -/* - * Internal Definitions - */ -#define BOOTFLASH_START 0xF0000000 - -#define CONFIG_KM_CONSOLE_TTY "ttyS0" - -/* - * Environment Configuration - */ -#define CONFIG_ENV_OVERWRITE -#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ -#define CONFIG_KM_DEF_ENV "km-common=empty\0" -#endif - -#ifndef CONFIG_KM_DEF_ARCH -#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" -#endif - -#define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_KM_DEF_ENV \ - CONFIG_KM_DEF_ARCH \ - "newenv=" \ - "prot off "__stringify(CONFIG_ENV_ADDR)" +0x40000 && " \ - "era "__stringify(CONFIG_ENV_ADDR)" +0x40000\0" \ - "unlock=yes\0" \ - "" - -#if defined(CONFIG_UEC_ETH) -#define CONFIG_HAS_ETH0 -#endif - -/* - * System IO Setup - */ -#define CONFIG_SYS_SICRH (SICRH_UC1EOBI | SICRH_UC2E1OBI) - -/** - * DDR RAM settings - */ -#define CONFIG_SYS_DDR_SDRAM_CFG (\ - SDRAM_CFG_SDRAM_TYPE_DDR2 | \ - SDRAM_CFG_SREN | \ - SDRAM_CFG_HSE) - -#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 - /** * KMCOGE5NE has 512 MB RAM */ @@ -246,68 +44,12 @@ CSCONFIG_ROW_BIT_13 | \ CSCONFIG_COL_BIT_10) -#define CONFIG_SYS_DDR_CLK_CNTL (\ - DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) - -#define CONFIG_SYS_DDR_INTERVAL (\ - (0x080 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ - (0x203 << SDRAM_INTERVAL_REFINT_SHIFT)) - -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f - -#define CONFIG_SYS_DDRCDR (\ - DDRCDR_EN | \ - DDRCDR_Q_DRN) -#define CONFIG_SYS_DDR_MODE 0x47860452 -#define CONFIG_SYS_DDR_MODE2 0x8080c000 - -#define CONFIG_SYS_DDR_TIMING_0 (\ - (2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ - (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ - (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ - (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ - (0 << TIMING_CFG0_WWT_SHIFT) | \ - (0 << TIMING_CFG0_RRT_SHIFT) | \ - (0 << TIMING_CFG0_WRT_SHIFT) | \ - (0 << TIMING_CFG0_RWT_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \ - (2 << TIMING_CFG1_WRTORD_SHIFT) | \ - (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ - (3 << TIMING_CFG1_WRREC_SHIFT) | \ - (7 << TIMING_CFG1_REFREC_SHIFT) | \ - (3 << TIMING_CFG1_ACTTORW_SHIFT) | \ - (8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ - (3 << TIMING_CFG1_PRETOACT_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_2 (\ - (0xa << TIMING_CFG2_FOUR_ACT_SHIFT) | \ - (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ - (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ - (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ - (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ - (5 << TIMING_CFG2_CPO_SHIFT) | \ - (0 << TIMING_CFG2_ADD_LAT_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_3 0x00000000 - -/* EEprom support */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 - -/* - * PAXE on the local bus CS3 - */ -#define CONFIG_SYS_PAXE_BASE 0xA0000000 -#define CONFIG_SYS_PAXE_SIZE 256 - - /* * BFTIC3 on the local bus CS4 */ #define CONFIG_SYS_BFTIC3_BASE 0xB0000000 #define CONFIG_SYS_BFTIC3_SIZE 256 - /* enable POST tests */ #define CONFIG_POST (CONFIG_SYS_POST_MEMORY|CONFIG_SYS_POST_MEM_REGIONS) #define CONFIG_POST_EXTERNAL_WORD_FUNCS /* use own functions, not generic */ diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h index 290108d4fc..bfa7ca27c7 100644 --- a/include/configs/kmeter1.h +++ b/include/configs/kmeter1.h @@ -8,277 +8,23 @@ #ifndef __CONFIG_H #define __CONFIG_H -/* KMBEC FPGA (PRIO) */ -#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000 -#define CONFIG_SYS_KMBEC_FPGA_SIZE 64 - #define CONFIG_HOSTNAME "kmeter1" #define CONFIG_KM_BOARD_NAME "kmeter1" #define CONFIG_KM_DEF_NETDEV "netdev=eth2\0" -/* - * High Level Configuration Options - */ -#define CONFIG_QE /* Has QE */ - /* include common defines/options for all Keymile boards */ #include "km/keymile-common.h" #include "km/km-powerpc.h" - -/* - * DDR Setup - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */ - -#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ - DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) - -#define CFG_83XX_DDR_USES_CS0 - -/* - * Manually set up DDR parameters - */ -#define CONFIG_DDR_II -#define CONFIG_SYS_DDR_SIZE 2048 /* MB */ - -/* - * The reserved memory - */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ -#define CONFIG_SYS_FLASH_BASE 0xF0000000 - -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT -#endif - -/* Reserve 768 kB for Mon */ -#define CONFIG_SYS_MONITOR_LEN (768 * 1024) - -/* - * Initial RAM Base Address Setup - */ -#define CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) - -/* - * Init Local Bus Memory Controller: - * - * Bank Bus Machine PortSz Size Device - * ---- --- ------- ------ ----- ------ - * 0 Local GPCM 16 bit 256MB FLASH - * 1 Local GPCM 8 bit 128MB GPIO/PIGGY - * - */ -/* - * FLASH on the Local Bus - */ -#define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ - - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } - -/* - * PRIO1/PIGGY on the local bus CS1 - */ - +#include "km/km-mpc83xx.h" +#include "km/km-mpc8360.h" /* * Serial Port */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) - -/* - * QE UEC ethernet configuration - */ -#define CONFIG_UEC_ETH -#define CONFIG_ETHPRIME "UEC0" - -#define CONFIG_UEC_ETH1 /* GETH1 */ -#define UEC_VERBOSE_DEBUG 1 - -#ifdef CONFIG_UEC_ETH1 -#define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */ -#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ -#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17 -#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH -#define CONFIG_SYS_UEC1_PHY_ADDR 0 -#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII -#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 -#endif - -/* - * Environment - */ - -#ifndef CONFIG_SYS_RAMBOOT -#ifndef CONFIG_ENV_ADDR -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ - CONFIG_SYS_MONITOR_LEN) -#endif -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ -#ifndef CONFIG_ENV_OFFSET -#define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN) -#endif - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#else /* CFG_SYS_RAMBOOT */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) -#define CONFIG_ENV_SIZE 0x2000 -#endif /* CFG_SYS_RAMBOOT */ - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_NUM_I2C_BUSES 4 -#define CONFIG_SYS_I2C_MAX_HOPS 1 -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 200000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_I2C_OFFSET 0x3000 -#define CONFIG_SYS_FSL_I2C2_SPEED 200000 -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 -#define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \ - {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \ - {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \ - {1, {I2C_NULL_HOP} } } - -#define CONFIG_KM_IVM_BUS 2 /* I2C2 (Mux-Port 1)*/ - -#if defined(CONFIG_CMD_NAND) -#define CONFIG_NAND_KMETER1 -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE -#endif - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) - -/* - * Internal Definitions - */ -#define BOOTFLASH_START 0xF0000000 - -#define CONFIG_KM_CONSOLE_TTY "ttyS0" - -/* - * Environment Configuration - */ -#define CONFIG_ENV_OVERWRITE -#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ -#define CONFIG_KM_DEF_ENV "km-common=empty\0" -#endif - -#ifndef CONFIG_KM_DEF_ARCH -#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" -#endif - -#define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_KM_DEF_ENV \ - CONFIG_KM_DEF_ARCH \ - "newenv=" \ - "prot off "__stringify(CONFIG_ENV_ADDR)" +0x40000 && " \ - "era "__stringify(CONFIG_ENV_ADDR)" +0x40000\0" \ - "unlock=yes\0" \ - "" - -#if defined(CONFIG_UEC_ETH) -#define CONFIG_HAS_ETH0 -#endif - -/* - * System IO Setup - */ -#define CONFIG_SYS_SICRH (SICRH_UC1EOBI | SICRH_UC2E1OBI) - -/** - * DDR RAM settings - */ -#define CONFIG_SYS_DDR_SDRAM_CFG (\ - SDRAM_CFG_SDRAM_TYPE_DDR2 | \ - SDRAM_CFG_SREN | \ - SDRAM_CFG_HSE) - -#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ CSCONFIG_ROW_BIT_13 | \ CSCONFIG_COL_BIT_10 | \ CSCONFIG_ODT_WR_ONLY_CURRENT) - -#define CONFIG_SYS_DDR_CLK_CNTL (\ - DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) - -#define CONFIG_SYS_DDR_INTERVAL (\ - (0x080 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ - (0x203 << SDRAM_INTERVAL_REFINT_SHIFT)) - -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f - -#define CONFIG_SYS_DDRCDR (\ - DDRCDR_EN | \ - DDRCDR_Q_DRN) -#define CONFIG_SYS_DDR_MODE 0x47860452 -#define CONFIG_SYS_DDR_MODE2 0x8080c000 - -#define CONFIG_SYS_DDR_TIMING_0 (\ - (2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ - (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ - (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ - (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ - (0 << TIMING_CFG0_WWT_SHIFT) | \ - (0 << TIMING_CFG0_RRT_SHIFT) | \ - (0 << TIMING_CFG0_WRT_SHIFT) | \ - (0 << TIMING_CFG0_RWT_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \ - (2 << TIMING_CFG1_WRTORD_SHIFT) | \ - (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ - (3 << TIMING_CFG1_WRREC_SHIFT) | \ - (7 << TIMING_CFG1_REFREC_SHIFT) | \ - (3 << TIMING_CFG1_ACTTORW_SHIFT) | \ - (8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ - (3 << TIMING_CFG1_PRETOACT_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_2 (\ - (0xa << TIMING_CFG2_FOUR_ACT_SHIFT) | \ - (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ - (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ - (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ - (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ - (5 << TIMING_CFG2_CPO_SHIFT) | \ - (0 << TIMING_CFG2_ADD_LAT_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_3 0x00000000 - -/* EEprom support */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 - -/* - * PAXE on the local bus CS3 - */ -#define CONFIG_SYS_PAXE_BASE 0xA0000000 -#define CONFIG_SYS_PAXE_SIZE 256 - - #endif /* CONFIG */ diff --git a/include/configs/kmopti2.h b/include/configs/kmopti2.h index f1b7c2f02e..67e864fc98 100644 --- a/include/configs/kmopti2.h +++ b/include/configs/kmopti2.h @@ -26,292 +26,10 @@ #define CONFIG_KM_BOARD_NAME "kmopti2" #define CONFIG_HOSTNAME "kmopti2" -/* - * High Level Configuration Options - */ -#define CONFIG_QE /* Has QE */ -#define CONFIG_KM8321 /* Keymile PBEC8321 board specific */ - -#define CONFIG_KM_DEF_ARCH "arch=ppc_8xx\0" - /* include common defines/options for all Keymile boards */ #include "km/keymile-common.h" #include "km/km-powerpc.h" - -/* - * System Clock Setup - */ -#define CONFIG_83XX_CLKIN 66000000 -#define CONFIG_SYS_CLK_FREQ 66000000 -#define CONFIG_83XX_PCICLK 66000000 - -/* - * DDR Setup - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */ - -#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ - DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) - -#define CFG_83XX_DDR_USES_CS0 - -/* - * Manually set up DDR parameters - */ -#define CONFIG_DDR_II -#define CONFIG_SYS_DDR_SIZE 2048 /* MB */ - -/* - * The reserved memory - */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ -#define CONFIG_SYS_FLASH_BASE 0xF0000000 - -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT -#endif - -/* Reserve 768 kB for Mon */ -#define CONFIG_SYS_MONITOR_LEN (768 * 1024) - -/* - * Initial RAM Base Address Setup - */ -#define CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) - -/* - * Init Local Bus Memory Controller: - * - * Bank Bus Machine PortSz Size Device - * ---- --- ------- ------ ----- ------ - * 0 Local GPCM 16 bit 256MB FLASH - * 1 Local GPCM 8 bit 128MB GPIO/PIGGY - * - */ -/* - * FLASH on the Local Bus - */ -#define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ - - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } - -/* - * PRIO1/PIGGY on the local bus CS1 - */ - - -/* - * Serial Port - */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) - -/* - * QE UEC ethernet configuration - */ -#define CONFIG_UEC_ETH -#define CONFIG_ETHPRIME "UEC0" - -#define CONFIG_UEC_ETH1 /* GETH1 */ -#define UEC_VERBOSE_DEBUG 1 - -#ifdef CONFIG_UEC_ETH1 -#define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */ -#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ -#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17 -#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH -#define CONFIG_SYS_UEC1_PHY_ADDR 0 -#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII -#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 -#endif - -/* - * Environment - */ - -#ifndef CONFIG_SYS_RAMBOOT -#ifndef CONFIG_ENV_ADDR -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ - CONFIG_SYS_MONITOR_LEN) -#endif -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ -#ifndef CONFIG_ENV_OFFSET -#define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN) -#endif - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#else /* CFG_SYS_RAMBOOT */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) -#define CONFIG_ENV_SIZE 0x2000 -#endif /* CFG_SYS_RAMBOOT */ - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_NUM_I2C_BUSES 4 -#define CONFIG_SYS_I2C_MAX_HOPS 1 -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 200000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_I2C_OFFSET 0x3000 -#define CONFIG_SYS_FSL_I2C2_SPEED 200000 -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 -#define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \ - {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \ - {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \ - {1, {I2C_NULL_HOP} } } - -#define CONFIG_KM_IVM_BUS 2 /* I2C2 (Mux-Port 1)*/ - -#if defined(CONFIG_CMD_NAND) -#define CONFIG_NAND_KMETER1 -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE -#endif - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) - -/* - * Internal Definitions - */ -#define BOOTFLASH_START 0xF0000000 - -#define CONFIG_KM_CONSOLE_TTY "ttyS0" - -/* - * Environment Configuration - */ -#define CONFIG_ENV_OVERWRITE -#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ -#define CONFIG_KM_DEF_ENV "km-common=empty\0" -#endif - -#ifndef CONFIG_KM_DEF_ARCH -#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" -#endif - -#define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_KM_DEF_ENV \ - CONFIG_KM_DEF_ARCH \ - "newenv=" \ - "prot off "__stringify(CONFIG_ENV_ADDR)" +0x40000 && " \ - "era "__stringify(CONFIG_ENV_ADDR)" +0x40000\0" \ - "unlock=yes\0" \ - "" - -#if defined(CONFIG_UEC_ETH) -#define CONFIG_HAS_ETH0 -#endif - -/* - * System IO Config - */ -#define CONFIG_SYS_SICRL SICRL_IRQ_CKS - -#define CONFIG_SYS_DDRCDR (\ - DDRCDR_EN | \ - DDRCDR_PZ_MAXZ | \ - DDRCDR_NZ_MAXZ | \ - DDRCDR_M_ODR) - -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f -#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ - SDRAM_CFG_32_BE | \ - SDRAM_CFG_SREN | \ - SDRAM_CFG_HSE) - -#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 -#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) -#define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ - (0x200 << SDRAM_INTERVAL_REFINT_SHIFT)) - -#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ - CSCONFIG_ODT_WR_CFG | \ - CSCONFIG_ROW_BIT_13 | \ - CSCONFIG_COL_BIT_10) - -#define CONFIG_SYS_DDR_MODE 0x47860242 -#define CONFIG_SYS_DDR_MODE2 0x8080c000 - -#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ - (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ - (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ - (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ - (0 << TIMING_CFG0_WWT_SHIFT) | \ - (0 << TIMING_CFG0_RRT_SHIFT) | \ - (0 << TIMING_CFG0_WRT_SHIFT) | \ - (0 << TIMING_CFG0_RWT_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \ - (2 << TIMING_CFG1_WRTORD_SHIFT) | \ - (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ - (3 << TIMING_CFG1_WRREC_SHIFT) | \ - (7 << TIMING_CFG1_REFREC_SHIFT) | \ - (3 << TIMING_CFG1_ACTTORW_SHIFT) | \ - (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ - (3 << TIMING_CFG1_PRETOACT_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ - (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ - (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ - (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ - (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ - (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \ - (5 << TIMING_CFG2_CPO_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_3 0x00000000 - -#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000 -#define CONFIG_SYS_KMBEC_FPGA_SIZE 128 - -/* EEprom support */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 - -/* - * Init Local Bus Memory Controller: - * Device on board - * Bank Bus Machine PortSz Size TUDA1 TUXA1 TUGE1 KMSUPX4 KMOPTI2 - * ----------------------------------------------------------------------------- - * 2 Local GPCM 8 bit 256MB PAXG LPXF PAXI LPXF PAXE - * 3 Local GPCM 8 bit 256MB PINC3 PINC2 unused unused OPI2(16 bit) - * - * Device on board (continued) - * Bank Bus Machine PortSz Size KMTEPR2 - * ----------------------------------------------------------------------------- - * 2 Local GPCM 8 bit 256MB NVRAM - * 3 Local GPCM 8 bit 256MB TEP2 (16 bit) - */ - -/* - * Configuration for C2 on the local bus - */ - - -/* - * Configuration for C3 on the local bus - */ - +#include "km/km-mpc83xx.h" +#include "km/km-mpc832x.h" #endif /* __CONFIG_H */ diff --git a/include/configs/kmsupx5.h b/include/configs/kmsupx5.h index 0dd7420e8c..ba33e6074b 100644 --- a/include/configs/kmsupx5.h +++ b/include/configs/kmsupx5.h @@ -26,283 +26,10 @@ #define CONFIG_KM_BOARD_NAME "kmsupx5" #define CONFIG_HOSTNAME "kmsupx5" -/* - * High Level Configuration Options - */ -#define CONFIG_QE /* Has QE */ -#define CONFIG_KM8321 /* Keymile PBEC8321 board specific */ - -#define CONFIG_KM_DEF_ARCH "arch=ppc_8xx\0" - /* include common defines/options for all Keymile boards */ #include "km/keymile-common.h" #include "km/km-powerpc.h" - -/* - * System Clock Setup - */ -#define CONFIG_83XX_CLKIN 66000000 -#define CONFIG_SYS_CLK_FREQ 66000000 -#define CONFIG_83XX_PCICLK 66000000 - -/* - * DDR Setup - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */ - -#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ - DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) - -#define CFG_83XX_DDR_USES_CS0 - -/* - * Manually set up DDR parameters - */ -#define CONFIG_DDR_II -#define CONFIG_SYS_DDR_SIZE 2048 /* MB */ - -/* - * The reserved memory - */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ -#define CONFIG_SYS_FLASH_BASE 0xF0000000 - -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT -#endif - -/* Reserve 768 kB for Mon */ -#define CONFIG_SYS_MONITOR_LEN (768 * 1024) - -/* - * Initial RAM Base Address Setup - */ -#define CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) - -/* - * Init Local Bus Memory Controller: - * - * Bank Bus Machine PortSz Size Device - * ---- --- ------- ------ ----- ------ - * 0 Local GPCM 16 bit 256MB FLASH - * 1 Local GPCM 8 bit 128MB GPIO/PIGGY - * - */ -/* - * FLASH on the Local Bus - */ -#define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ - - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } - -/* - * PRIO1/PIGGY on the local bus CS1 - */ - - -/* - * Serial Port - */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) - -/* - * QE UEC ethernet configuration - */ -#define CONFIG_UEC_ETH -#define CONFIG_ETHPRIME "UEC0" - -#define CONFIG_UEC_ETH1 /* GETH1 */ -#define UEC_VERBOSE_DEBUG 1 - -#ifdef CONFIG_UEC_ETH1 -#define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */ -#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ -#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17 -#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH -#define CONFIG_SYS_UEC1_PHY_ADDR 0 -#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII -#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 -#endif - -/* - * Environment - */ - -#ifndef CONFIG_SYS_RAMBOOT -#ifndef CONFIG_ENV_ADDR -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ - CONFIG_SYS_MONITOR_LEN) -#endif -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ -#ifndef CONFIG_ENV_OFFSET -#define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN) -#endif - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#else /* CFG_SYS_RAMBOOT */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) -#define CONFIG_ENV_SIZE 0x2000 -#endif /* CFG_SYS_RAMBOOT */ - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_NUM_I2C_BUSES 4 -#define CONFIG_SYS_I2C_MAX_HOPS 1 -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 200000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_I2C_OFFSET 0x3000 -#define CONFIG_SYS_FSL_I2C2_SPEED 200000 -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 -#define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \ - {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \ - {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \ - {1, {I2C_NULL_HOP} } } - -#define CONFIG_KM_IVM_BUS 2 /* I2C2 (Mux-Port 1)*/ - -#if defined(CONFIG_CMD_NAND) -#define CONFIG_NAND_KMETER1 -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE -#endif - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) - -/* - * Internal Definitions - */ -#define BOOTFLASH_START 0xF0000000 - -#define CONFIG_KM_CONSOLE_TTY "ttyS0" - -/* - * Environment Configuration - */ -#define CONFIG_ENV_OVERWRITE -#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ -#define CONFIG_KM_DEF_ENV "km-common=empty\0" -#endif - -#ifndef CONFIG_KM_DEF_ARCH -#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" -#endif - -#define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_KM_DEF_ENV \ - CONFIG_KM_DEF_ARCH \ - "newenv=" \ - "prot off "__stringify(CONFIG_ENV_ADDR)" +0x40000 && " \ - "era "__stringify(CONFIG_ENV_ADDR)" +0x40000\0" \ - "unlock=yes\0" \ - "" - -#if defined(CONFIG_UEC_ETH) -#define CONFIG_HAS_ETH0 -#endif - -/* - * System IO Config - */ -#define CONFIG_SYS_SICRL SICRL_IRQ_CKS - -#define CONFIG_SYS_DDRCDR (\ - DDRCDR_EN | \ - DDRCDR_PZ_MAXZ | \ - DDRCDR_NZ_MAXZ | \ - DDRCDR_M_ODR) - -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f -#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ - SDRAM_CFG_32_BE | \ - SDRAM_CFG_SREN | \ - SDRAM_CFG_HSE) - -#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 -#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) -#define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ - (0x200 << SDRAM_INTERVAL_REFINT_SHIFT)) - -#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ - CSCONFIG_ODT_WR_CFG | \ - CSCONFIG_ROW_BIT_13 | \ - CSCONFIG_COL_BIT_10) - -#define CONFIG_SYS_DDR_MODE 0x47860242 -#define CONFIG_SYS_DDR_MODE2 0x8080c000 - -#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ - (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ - (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ - (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ - (0 << TIMING_CFG0_WWT_SHIFT) | \ - (0 << TIMING_CFG0_RRT_SHIFT) | \ - (0 << TIMING_CFG0_WRT_SHIFT) | \ - (0 << TIMING_CFG0_RWT_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \ - (2 << TIMING_CFG1_WRTORD_SHIFT) | \ - (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ - (3 << TIMING_CFG1_WRREC_SHIFT) | \ - (7 << TIMING_CFG1_REFREC_SHIFT) | \ - (3 << TIMING_CFG1_ACTTORW_SHIFT) | \ - (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ - (3 << TIMING_CFG1_PRETOACT_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ - (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ - (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ - (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ - (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ - (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \ - (5 << TIMING_CFG2_CPO_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_3 0x00000000 - -#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000 -#define CONFIG_SYS_KMBEC_FPGA_SIZE 128 - -/* EEprom support */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 - -/* - * Init Local Bus Memory Controller: - * Device on board - * Bank Bus Machine PortSz Size TUDA1 TUXA1 TUGE1 KMSUPX4 KMOPTI2 - * ----------------------------------------------------------------------------- - * 2 Local GPCM 8 bit 256MB PAXG LPXF PAXI LPXF PAXE - * 3 Local GPCM 8 bit 256MB PINC3 PINC2 unused unused OPI2(16 bit) - * - * Device on board (continued) - * Bank Bus Machine PortSz Size KMTEPR2 - * ----------------------------------------------------------------------------- - * 2 Local GPCM 8 bit 256MB NVRAM - * 3 Local GPCM 8 bit 256MB TEP2 (16 bit) - */ - +#include "km/km-mpc83xx.h" +#include "km/km-mpc832x.h" #endif /* __CONFIG_H */ diff --git a/include/configs/kmtegr1.h b/include/configs/kmtegr1.h index 8f9bbefa7f..701eb53f63 100644 --- a/include/configs/kmtegr1.h +++ b/include/configs/kmtegr1.h @@ -33,340 +33,13 @@ #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define NAND_MAX_CHIPS 1 -/* - * High Level Configuration Options - */ -#define CONFIG_E300 1 /* E300 family */ -#define CONFIG_QE 1 /* Has QE */ - -#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" - /* include common defines/options for all Keymile boards */ #include "km/keymile-common.h" #include "km/km-powerpc.h" - -/* - * System Clock Setup - */ -#define CONFIG_83XX_CLKIN 66000000 -#define CONFIG_SYS_CLK_FREQ 66000000 -#define CONFIG_83XX_PCICLK 66000000 - -/* - * DDR Setup - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */ - -#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ - DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) - -#define CFG_83XX_DDR_USES_CS0 - -/* - * Manually set up DDR parameters - */ -#define CONFIG_DDR_II -#define CONFIG_SYS_DDR_SIZE 2048 /* MB */ - -/* - * The reserved memory - */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ -#define CONFIG_SYS_FLASH_BASE 0xF0000000 - -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT -#endif - -/* Reserve 768 kB for Mon */ -#define CONFIG_SYS_MONITOR_LEN (768 * 1024) - -/* - * Initial RAM Base Address Setup - */ -#define CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) - -/* - * Init Local Bus Memory Controller: - * - * Bank Bus Machine PortSz Size Device - * ---- --- ------- ------ ----- ------ - * 0 Local GPCM 16 bit 256MB FLASH - * 1 Local GPCM 8 bit 128MB GPIO/PIGGY - * - */ -/* - * FLASH on the Local Bus - */ -#define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ - - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } - -/* - * PRIO1/PIGGY on the local bus CS1 - */ - - -/* - * Serial Port - */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) - -/* - * QE UEC ethernet configuration - */ -#define CONFIG_UEC_ETH -#define CONFIG_ETHPRIME "UEC0" - -#ifdef CONFIG_UEC_ETH1 -#define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */ -#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ -#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17 -#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH -#define CONFIG_SYS_UEC1_PHY_ADDR 0 -#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII -#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 -#endif - -/* - * Environment - */ - -#ifndef CONFIG_SYS_RAMBOOT -#ifndef CONFIG_ENV_ADDR -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ - CONFIG_SYS_MONITOR_LEN) -#endif -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ -#ifndef CONFIG_ENV_OFFSET -#define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN) -#endif - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#else /* CFG_SYS_RAMBOOT */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) -#define CONFIG_ENV_SIZE 0x2000 -#endif /* CFG_SYS_RAMBOOT */ - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_NUM_I2C_BUSES 4 -#define CONFIG_SYS_I2C_MAX_HOPS 1 -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 200000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_I2C_OFFSET 0x3000 -#define CONFIG_SYS_FSL_I2C2_SPEED 200000 -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 -#define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \ - {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \ - {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \ - {1, {I2C_NULL_HOP} } } - -#define CONFIG_KM_IVM_BUS 2 /* I2C2 (Mux-Port 1)*/ - -#if defined(CONFIG_CMD_NAND) -#define CONFIG_NAND_KMETER1 -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE -#endif - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) - -/* - * Internal Definitions - */ -#define BOOTFLASH_START 0xF0000000 - -#define CONFIG_KM_CONSOLE_TTY "ttyS0" - -/* - * Environment Configuration - */ -#define CONFIG_ENV_OVERWRITE -#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ -#define CONFIG_KM_DEF_ENV "km-common=empty\0" -#endif - -#ifndef CONFIG_KM_DEF_ARCH -#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" -#endif - -#define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_KM_DEF_ENV \ - CONFIG_KM_DEF_ARCH \ - "newenv=" \ - "prot off "__stringify(CONFIG_ENV_ADDR)" +0x40000 && " \ - "era "__stringify(CONFIG_ENV_ADDR)" +0x40000\0" \ - "unlock=yes\0" \ - "" - -#if defined(CONFIG_UEC_ETH) -#define CONFIG_HAS_ETH0 -#endif - -/* QE microcode/firmware address */ -#define CONFIG_SYS_QE_FMAN_FW_IN_NOR -/* between the u-boot partition and env */ -#ifndef CONFIG_SYS_QE_FW_ADDR -#define CONFIG_SYS_QE_FW_ADDR 0xF00C0000 -#endif - -/* - * System IO Config - */ -/* 0x14000180 SICR_1 */ -#define CONFIG_SYS_SICRL (0 \ - | SICR_1_UART1_UART1RTS \ - | SICR_1_I2C_CKSTOP \ - | SICR_1_IRQ_A_IRQ \ - | SICR_1_IRQ_B_IRQ \ - | SICR_1_GPIO_A_GPIO \ - | SICR_1_GPIO_B_GPIO \ - | SICR_1_GPIO_C_GPIO \ - | SICR_1_GPIO_D_GPIO \ - | SICR_1_GPIO_E_GPIO \ - | SICR_1_GPIO_F_GPIO \ - | SICR_1_USB_A_UART2S \ - | SICR_1_USB_B_UART2RTS \ - | SICR_1_FEC1_FEC1 \ - | SICR_1_FEC2_FEC2 \ - ) - -/* 0x00080400 SICR_2 */ -#define CONFIG_SYS_SICRH (0 \ - | SICR_2_FEC3_FEC3 \ - | SICR_2_HDLC1_A_HDLC1 \ - | SICR_2_ELBC_A_LA \ - | SICR_2_ELBC_B_LCLK \ - | SICR_2_HDLC2_A_HDLC2 \ - | SICR_2_USB_D_GPIO \ - | SICR_2_PCI_PCI \ - | SICR_2_HDLC1_B_HDLC1 \ - | SICR_2_HDLC1_C_HDLC1 \ - | SICR_2_HDLC2_B_GPIO \ - | SICR_2_HDLC2_C_HDLC2 \ - | SICR_2_QUIESCE_B \ - ) - -/* GPR_1 */ -#define CONFIG_SYS_GPR1 0x50008060 - -#define CONFIG_SYS_GP1DIR 0x00000000 -#define CONFIG_SYS_GP1ODR 0x00000000 -#define CONFIG_SYS_GP2DIR 0xFF000000 -#define CONFIG_SYS_GP2ODR 0x00000000 - -#define CONFIG_SYS_DDRCDR (\ - DDRCDR_EN | \ - DDRCDR_PZ_MAXZ | \ - DDRCDR_NZ_MAXZ | \ - DDRCDR_M_ODR) - -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f -#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ - SDRAM_CFG_32_BE | \ - SDRAM_CFG_SREN | \ - SDRAM_CFG_HSE) - -#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 -#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) -#define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ - (0x200 << SDRAM_INTERVAL_REFINT_SHIFT)) - -#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ - CSCONFIG_ODT_RD_NEVER | \ - CSCONFIG_ODT_WR_ONLY_CURRENT | \ - CSCONFIG_ROW_BIT_13 | \ - CSCONFIG_COL_BIT_10) - -#define CONFIG_SYS_DDR_MODE 0x47860242 -#define CONFIG_SYS_DDR_MODE2 0x8080c000 - -#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ - (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ - (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ - (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ - (0 << TIMING_CFG0_WWT_SHIFT) | \ - (0 << TIMING_CFG0_RRT_SHIFT) | \ - (0 << TIMING_CFG0_WRT_SHIFT) | \ - (0 << TIMING_CFG0_RWT_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \ - (2 << TIMING_CFG1_WRTORD_SHIFT) | \ - (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ - (3 << TIMING_CFG1_WRREC_SHIFT) | \ - (7 << TIMING_CFG1_REFREC_SHIFT) | \ - (3 << TIMING_CFG1_ACTTORW_SHIFT) | \ - (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ - (3 << TIMING_CFG1_PRETOACT_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ - (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ - (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ - (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ - (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ - (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \ - (5 << TIMING_CFG2_CPO_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_3 0x00000000 - -#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000 -#define CONFIG_SYS_KMBEC_FPGA_SIZE 128 - -/* EEprom support */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#include "km/km-mpc83xx.h" +#include "km/km-mpc8309.h" /* must be after the include because KMBEC_FPGA is otherwise undefined */ #define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */ -/* EEprom support */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 - -/* - * Init Local Bus Memory Controller: - * - * Bank Bus Machine PortSz Size Device - * ---- --- ------- ------ ----- ------ - * 2 Local UPMA 16 bit 256MB APP1 - * 3 Local GPCM 16 bit 256MB APP2 - * - */ - - -/* ethernet port connected to piggy (UEC2) */ -#define CONFIG_HAS_ETH1 -#define CONFIG_UEC_ETH2 -#define CONFIG_SYS_UEC2_UCC_NUM 2 /* UCC3 */ -#define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ -#define CONFIG_SYS_UEC2_TX_CLK QE_CLK12 -#define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH -#define CONFIG_SYS_UEC2_PHY_ADDR 0 -#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII -#define CONFIG_SYS_UEC2_INTERFACE_SPEED 100 - #endif /* __CONFIG_H */ diff --git a/include/configs/kmtepr2.h b/include/configs/kmtepr2.h index b77219f72c..e0c907d11a 100644 --- a/include/configs/kmtepr2.h +++ b/include/configs/kmtepr2.h @@ -26,284 +26,10 @@ #define CONFIG_KM_BOARD_NAME "kmtepr2" #define CONFIG_HOSTNAME "kmtepr2" -/* - * High Level Configuration Options - */ -#define CONFIG_QE /* Has QE */ -#define CONFIG_KM8321 /* Keymile PBEC8321 board specific */ - -#define CONFIG_KM_DEF_ARCH "arch=ppc_8xx\0" - /* include common defines/options for all Keymile boards */ #include "km/keymile-common.h" #include "km/km-powerpc.h" - -/* - * System Clock Setup - */ -#define CONFIG_83XX_CLKIN 66000000 -#define CONFIG_SYS_CLK_FREQ 66000000 -#define CONFIG_83XX_PCICLK 66000000 - -/* - * DDR Setup - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */ - -#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ - DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) - -#define CFG_83XX_DDR_USES_CS0 - -/* - * Manually set up DDR parameters - */ -#define CONFIG_DDR_II -#define CONFIG_SYS_DDR_SIZE 2048 /* MB */ - -/* - * The reserved memory - */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ -#define CONFIG_SYS_FLASH_BASE 0xF0000000 - -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT -#endif - -/* Reserve 768 kB for Mon */ -#define CONFIG_SYS_MONITOR_LEN (768 * 1024) - -/* - * Initial RAM Base Address Setup - */ -#define CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) - -/* - * Init Local Bus Memory Controller: - * - * Bank Bus Machine PortSz Size Device - * ---- --- ------- ------ ----- ------ - * 0 Local GPCM 16 bit 256MB FLASH - * 1 Local GPCM 8 bit 128MB GPIO/PIGGY - * - */ -/* - * FLASH on the Local Bus - */ -#define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ - - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } - -/* - * PRIO1/PIGGY on the local bus CS1 - */ - - -/* - * Serial Port - */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) - -/* - * QE UEC ethernet configuration - */ -#define CONFIG_UEC_ETH -#define CONFIG_ETHPRIME "UEC0" - -#define CONFIG_UEC_ETH1 /* GETH1 */ -#define UEC_VERBOSE_DEBUG 1 - -#ifdef CONFIG_UEC_ETH1 -#define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */ -#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ -#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17 -#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH -#define CONFIG_SYS_UEC1_PHY_ADDR 0 -#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII -#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 -#endif - -/* - * Environment - */ - -#ifndef CONFIG_SYS_RAMBOOT -#ifndef CONFIG_ENV_ADDR -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ - CONFIG_SYS_MONITOR_LEN) -#endif -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ -#ifndef CONFIG_ENV_OFFSET -#define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN) -#endif - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#else /* CFG_SYS_RAMBOOT */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) -#define CONFIG_ENV_SIZE 0x2000 -#endif /* CFG_SYS_RAMBOOT */ - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_NUM_I2C_BUSES 4 -#define CONFIG_SYS_I2C_MAX_HOPS 1 -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 200000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_I2C_OFFSET 0x3000 -#define CONFIG_SYS_FSL_I2C2_SPEED 200000 -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 -#define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \ - {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \ - {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \ - {1, {I2C_NULL_HOP} } } - -#define CONFIG_KM_IVM_BUS 2 /* I2C2 (Mux-Port 1)*/ - -#if defined(CONFIG_CMD_NAND) -#define CONFIG_NAND_KMETER1 -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE -#endif - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) - -/* - * Internal Definitions - */ -#define BOOTFLASH_START 0xF0000000 - -#define CONFIG_KM_CONSOLE_TTY "ttyS0" - -/* - * Environment Configuration - */ -#define CONFIG_ENV_OVERWRITE -#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ -#define CONFIG_KM_DEF_ENV "km-common=empty\0" -#endif - -#ifndef CONFIG_KM_DEF_ARCH -#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" -#endif - -#define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_KM_DEF_ENV \ - CONFIG_KM_DEF_ARCH \ - "newenv=" \ - "prot off "__stringify(CONFIG_ENV_ADDR)" +0x40000 && " \ - "era "__stringify(CONFIG_ENV_ADDR)" +0x40000\0" \ - "unlock=yes\0" \ - "" - -#if defined(CONFIG_UEC_ETH) -#define CONFIG_HAS_ETH0 -#endif - -/* - * System IO Config - */ -#define CONFIG_SYS_SICRL SICRL_IRQ_CKS - -#define CONFIG_SYS_DDRCDR (\ - DDRCDR_EN | \ - DDRCDR_PZ_MAXZ | \ - DDRCDR_NZ_MAXZ | \ - DDRCDR_M_ODR) - -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f -#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ - SDRAM_CFG_32_BE | \ - SDRAM_CFG_SREN | \ - SDRAM_CFG_HSE) - -#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 -#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) -#define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ - (0x200 << SDRAM_INTERVAL_REFINT_SHIFT)) - -#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ - CSCONFIG_ODT_WR_CFG | \ - CSCONFIG_ROW_BIT_13 | \ - CSCONFIG_COL_BIT_10) - -#define CONFIG_SYS_DDR_MODE 0x47860242 -#define CONFIG_SYS_DDR_MODE2 0x8080c000 - -#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ - (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ - (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ - (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ - (0 << TIMING_CFG0_WWT_SHIFT) | \ - (0 << TIMING_CFG0_RRT_SHIFT) | \ - (0 << TIMING_CFG0_WRT_SHIFT) | \ - (0 << TIMING_CFG0_RWT_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \ - (2 << TIMING_CFG1_WRTORD_SHIFT) | \ - (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ - (3 << TIMING_CFG1_WRREC_SHIFT) | \ - (7 << TIMING_CFG1_REFREC_SHIFT) | \ - (3 << TIMING_CFG1_ACTTORW_SHIFT) | \ - (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ - (3 << TIMING_CFG1_PRETOACT_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ - (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ - (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ - (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ - (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ - (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \ - (5 << TIMING_CFG2_CPO_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_3 0x00000000 - -#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000 -#define CONFIG_SYS_KMBEC_FPGA_SIZE 128 - -/* EEprom support */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 - -/* - * Init Local Bus Memory Controller: - * Device on board - * Bank Bus Machine PortSz Size TUDA1 TUXA1 TUGE1 KMSUPX4 KMOPTI2 - * ----------------------------------------------------------------------------- - * 2 Local GPCM 8 bit 256MB PAXG LPXF PAXI LPXF PAXE - * 3 Local GPCM 8 bit 256MB PINC3 PINC2 unused unused OPI2(16 bit) - * - * Device on board (continued) - * Bank Bus Machine PortSz Size KMTEPR2 - * ----------------------------------------------------------------------------- - * 2 Local GPCM 8 bit 256MB NVRAM - * 3 Local GPCM 8 bit 256MB TEP2 (16 bit) - */ - - +#include "km/km-mpc83xx.h" +#include "km/km-mpc832x.h" #endif /* __CONFIG_H */ diff --git a/include/configs/kmvect1.h b/include/configs/kmvect1.h index 785475ef45..6e5d50700c 100644 --- a/include/configs/kmvect1.h +++ b/include/configs/kmvect1.h @@ -25,328 +25,11 @@ /* at end of uboot partition, before env */ #define CONFIG_SYS_QE_FW_ADDR 0xF00B0000 -/* - * High Level Configuration Options - */ -#define CONFIG_E300 1 /* E300 family */ -#define CONFIG_QE 1 /* Has QE */ - -#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" - /* include common defines/options for all Keymile boards */ #include "km/keymile-common.h" #include "km/km-powerpc.h" - -/* - * System Clock Setup - */ -#define CONFIG_83XX_CLKIN 66000000 -#define CONFIG_SYS_CLK_FREQ 66000000 -#define CONFIG_83XX_PCICLK 66000000 - -/* - * DDR Setup - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */ - -#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ - DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) - -#define CFG_83XX_DDR_USES_CS0 - -/* - * Manually set up DDR parameters - */ -#define CONFIG_DDR_II -#define CONFIG_SYS_DDR_SIZE 2048 /* MB */ - -/* - * The reserved memory - */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ -#define CONFIG_SYS_FLASH_BASE 0xF0000000 - -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT -#endif - -/* Reserve 768 kB for Mon */ -#define CONFIG_SYS_MONITOR_LEN (768 * 1024) - -/* - * Initial RAM Base Address Setup - */ -#define CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) - -/* - * Init Local Bus Memory Controller: - * - * Bank Bus Machine PortSz Size Device - * ---- --- ------- ------ ----- ------ - * 0 Local GPCM 16 bit 256MB FLASH - * 1 Local GPCM 8 bit 128MB GPIO/PIGGY - * - */ -/* - * FLASH on the Local Bus - */ -#define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ - - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } - -/* - * PRIO1/PIGGY on the local bus CS1 - */ - - -/* - * Serial Port - */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) - -/* - * QE UEC ethernet configuration - */ -#define CONFIG_UEC_ETH -#define CONFIG_ETHPRIME "UEC0" - -#ifdef CONFIG_UEC_ETH1 -#define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */ -#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ -#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17 -#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH -#define CONFIG_SYS_UEC1_PHY_ADDR 0 -#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII -#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 -#endif - -/* - * Environment - */ - -#ifndef CONFIG_SYS_RAMBOOT -#ifndef CONFIG_ENV_ADDR -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ - CONFIG_SYS_MONITOR_LEN) -#endif -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ -#ifndef CONFIG_ENV_OFFSET -#define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN) -#endif - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#else /* CFG_SYS_RAMBOOT */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) -#define CONFIG_ENV_SIZE 0x2000 -#endif /* CFG_SYS_RAMBOOT */ - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_NUM_I2C_BUSES 4 -#define CONFIG_SYS_I2C_MAX_HOPS 1 -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 200000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_I2C_OFFSET 0x3000 -#define CONFIG_SYS_FSL_I2C2_SPEED 200000 -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 -#define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \ - {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \ - {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \ - {1, {I2C_NULL_HOP} } } - -#define CONFIG_KM_IVM_BUS 2 /* I2C2 (Mux-Port 1)*/ - -#if defined(CONFIG_CMD_NAND) -#define CONFIG_NAND_KMETER1 -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE -#endif - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) - -/* - * Internal Definitions - */ -#define BOOTFLASH_START 0xF0000000 - -#define CONFIG_KM_CONSOLE_TTY "ttyS0" - -/* - * Environment Configuration - */ -#define CONFIG_ENV_OVERWRITE -#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ -#define CONFIG_KM_DEF_ENV "km-common=empty\0" -#endif - -#ifndef CONFIG_KM_DEF_ARCH -#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" -#endif - -#define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_KM_DEF_ENV \ - CONFIG_KM_DEF_ARCH \ - "newenv=" \ - "prot off "__stringify(CONFIG_ENV_ADDR)" +0x40000 && " \ - "era "__stringify(CONFIG_ENV_ADDR)" +0x40000\0" \ - "unlock=yes\0" \ - "" - -#if defined(CONFIG_UEC_ETH) -#define CONFIG_HAS_ETH0 -#endif - -/* QE microcode/firmware address */ -#define CONFIG_SYS_QE_FMAN_FW_IN_NOR -/* between the u-boot partition and env */ -#ifndef CONFIG_SYS_QE_FW_ADDR -#define CONFIG_SYS_QE_FW_ADDR 0xF00C0000 -#endif - -/* - * System IO Config - */ -/* 0x14000180 SICR_1 */ -#define CONFIG_SYS_SICRL (0 \ - | SICR_1_UART1_UART1RTS \ - | SICR_1_I2C_CKSTOP \ - | SICR_1_IRQ_A_IRQ \ - | SICR_1_IRQ_B_IRQ \ - | SICR_1_GPIO_A_GPIO \ - | SICR_1_GPIO_B_GPIO \ - | SICR_1_GPIO_C_GPIO \ - | SICR_1_GPIO_D_GPIO \ - | SICR_1_GPIO_E_GPIO \ - | SICR_1_GPIO_F_GPIO \ - | SICR_1_USB_A_UART2S \ - | SICR_1_USB_B_UART2RTS \ - | SICR_1_FEC1_FEC1 \ - | SICR_1_FEC2_FEC2 \ - ) - -/* 0x00080400 SICR_2 */ -#define CONFIG_SYS_SICRH (0 \ - | SICR_2_FEC3_FEC3 \ - | SICR_2_HDLC1_A_HDLC1 \ - | SICR_2_ELBC_A_LA \ - | SICR_2_ELBC_B_LCLK \ - | SICR_2_HDLC2_A_HDLC2 \ - | SICR_2_USB_D_GPIO \ - | SICR_2_PCI_PCI \ - | SICR_2_HDLC1_B_HDLC1 \ - | SICR_2_HDLC1_C_HDLC1 \ - | SICR_2_HDLC2_B_GPIO \ - | SICR_2_HDLC2_C_HDLC2 \ - | SICR_2_QUIESCE_B \ - ) - -/* GPR_1 */ -#define CONFIG_SYS_GPR1 0x50008060 - -#define CONFIG_SYS_GP1DIR 0x00000000 -#define CONFIG_SYS_GP1ODR 0x00000000 -#define CONFIG_SYS_GP2DIR 0xFF000000 -#define CONFIG_SYS_GP2ODR 0x00000000 - -#define CONFIG_SYS_DDRCDR (\ - DDRCDR_EN | \ - DDRCDR_PZ_MAXZ | \ - DDRCDR_NZ_MAXZ | \ - DDRCDR_M_ODR) - -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f -#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ - SDRAM_CFG_32_BE | \ - SDRAM_CFG_SREN | \ - SDRAM_CFG_HSE) - -#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 -#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) -#define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ - (0x200 << SDRAM_INTERVAL_REFINT_SHIFT)) - -#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ - CSCONFIG_ODT_RD_NEVER | \ - CSCONFIG_ODT_WR_ONLY_CURRENT | \ - CSCONFIG_ROW_BIT_13 | \ - CSCONFIG_COL_BIT_10) - -#define CONFIG_SYS_DDR_MODE 0x47860242 -#define CONFIG_SYS_DDR_MODE2 0x8080c000 - -#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ - (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ - (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ - (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ - (0 << TIMING_CFG0_WWT_SHIFT) | \ - (0 << TIMING_CFG0_RRT_SHIFT) | \ - (0 << TIMING_CFG0_WRT_SHIFT) | \ - (0 << TIMING_CFG0_RWT_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \ - (2 << TIMING_CFG1_WRTORD_SHIFT) | \ - (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ - (3 << TIMING_CFG1_WRREC_SHIFT) | \ - (7 << TIMING_CFG1_REFREC_SHIFT) | \ - (3 << TIMING_CFG1_ACTTORW_SHIFT) | \ - (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ - (3 << TIMING_CFG1_PRETOACT_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ - (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ - (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ - (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ - (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ - (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \ - (5 << TIMING_CFG2_CPO_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_3 0x00000000 - -#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000 -#define CONFIG_SYS_KMBEC_FPGA_SIZE 128 - -/* EEprom support */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 - -/* EEprom support */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 - -/* - * Init Local Bus Memory Controller: - * - * Bank Bus Machine PortSz Size Device - * ---- --- ------- ------ ----- ------ - * 2 Local UPMA 16 bit 256MB APP1 - * 3 Local GPCM 16 bit 256MB APP2 - * - */ - - +#include "km/km-mpc83xx.h" +#include "km/km-mpc8309.h" #define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \ 0x0000c000 | \ @@ -375,15 +58,4 @@ #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 -/* ethernet port connected to piggy (UEC2) */ -#define CONFIG_HAS_ETH1 -#define CONFIG_UEC_ETH2 -#define CONFIG_SYS_UEC2_UCC_NUM 2 /* UCC3 */ -#define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ -#define CONFIG_SYS_UEC2_TX_CLK QE_CLK12 -#define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH -#define CONFIG_SYS_UEC2_PHY_ADDR 0 -#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII -#define CONFIG_SYS_UEC2_INTERFACE_SPEED 100 - #endif /* __CONFIG_H */ diff --git a/include/configs/suvd3.h b/include/configs/suvd3.h index 456cd9dd70..1705f9cafb 100644 --- a/include/configs/suvd3.h +++ b/include/configs/suvd3.h @@ -21,285 +21,13 @@ */ #define CONFIG_HOSTNAME "suvd3" -#define CONFIG_KM_BOARD_NAME "suvd3" - -/* - * High Level Configuration Options - */ -#define CONFIG_QE /* Has QE */ -#define CONFIG_KM8321 /* Keymile PBEC8321 board specific */ - -#define CONFIG_KM_DEF_ARCH "arch=ppc_8xx\0" +#define CONFIG_KM_BOARD_NAME "suvd3" /* include common defines/options for all Keymile boards */ #include "km/keymile-common.h" #include "km/km-powerpc.h" - -/* - * System Clock Setup - */ -#define CONFIG_83XX_CLKIN 66000000 -#define CONFIG_SYS_CLK_FREQ 66000000 -#define CONFIG_83XX_PCICLK 66000000 - -/* - * DDR Setup - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */ - -#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ - DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) - -#define CFG_83XX_DDR_USES_CS0 - -/* - * Manually set up DDR parameters - */ -#define CONFIG_DDR_II -#define CONFIG_SYS_DDR_SIZE 2048 /* MB */ - -/* - * The reserved memory - */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ -#define CONFIG_SYS_FLASH_BASE 0xF0000000 - -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT -#endif - -/* Reserve 768 kB for Mon */ -#define CONFIG_SYS_MONITOR_LEN (768 * 1024) - -/* - * Initial RAM Base Address Setup - */ -#define CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) - -/* - * Init Local Bus Memory Controller: - * - * Bank Bus Machine PortSz Size Device - * ---- --- ------- ------ ----- ------ - * 0 Local GPCM 16 bit 256MB FLASH - * 1 Local GPCM 8 bit 128MB GPIO/PIGGY - * - */ -/* - * FLASH on the Local Bus - */ -#define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ - - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } - -/* - * PRIO1/PIGGY on the local bus CS1 - */ - - -/* - * Serial Port - */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) - -/* - * QE UEC ethernet configuration - */ -#define CONFIG_UEC_ETH -#define CONFIG_ETHPRIME "UEC0" - -#define CONFIG_UEC_ETH1 /* GETH1 */ -#define UEC_VERBOSE_DEBUG 1 - -#ifdef CONFIG_UEC_ETH1 -#define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */ -#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ -#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17 -#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH -#define CONFIG_SYS_UEC1_PHY_ADDR 0 -#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII -#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 -#endif - -/* - * Environment - */ - -#ifndef CONFIG_SYS_RAMBOOT -#ifndef CONFIG_ENV_ADDR -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ - CONFIG_SYS_MONITOR_LEN) -#endif -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ -#ifndef CONFIG_ENV_OFFSET -#define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN) -#endif - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#else /* CFG_SYS_RAMBOOT */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) -#define CONFIG_ENV_SIZE 0x2000 -#endif /* CFG_SYS_RAMBOOT */ - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_NUM_I2C_BUSES 4 -#define CONFIG_SYS_I2C_MAX_HOPS 1 -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 200000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_I2C_OFFSET 0x3000 -#define CONFIG_SYS_FSL_I2C2_SPEED 200000 -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 -#define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \ - {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \ - {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \ - {1, {I2C_NULL_HOP} } } - -#define CONFIG_KM_IVM_BUS 2 /* I2C2 (Mux-Port 1)*/ - -#if defined(CONFIG_CMD_NAND) -#define CONFIG_NAND_KMETER1 -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE -#endif - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) - -/* - * Internal Definitions - */ -#define BOOTFLASH_START 0xF0000000 - -#define CONFIG_KM_CONSOLE_TTY "ttyS0" - -/* - * Environment Configuration - */ -#define CONFIG_ENV_OVERWRITE -#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ -#define CONFIG_KM_DEF_ENV "km-common=empty\0" -#endif - -#ifndef CONFIG_KM_DEF_ARCH -#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" -#endif - -#define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_KM_DEF_ENV \ - CONFIG_KM_DEF_ARCH \ - "newenv=" \ - "prot off "__stringify(CONFIG_ENV_ADDR)" +0x40000 && " \ - "era "__stringify(CONFIG_ENV_ADDR)" +0x40000\0" \ - "unlock=yes\0" \ - "" - -#if defined(CONFIG_UEC_ETH) -#define CONFIG_HAS_ETH0 -#endif - -/* - * System IO Config - */ -#define CONFIG_SYS_SICRL SICRL_IRQ_CKS - -#define CONFIG_SYS_DDRCDR (\ - DDRCDR_EN | \ - DDRCDR_PZ_MAXZ | \ - DDRCDR_NZ_MAXZ | \ - DDRCDR_M_ODR) - -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f -#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ - SDRAM_CFG_32_BE | \ - SDRAM_CFG_SREN | \ - SDRAM_CFG_HSE) - -#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 -#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) -#define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ - (0x200 << SDRAM_INTERVAL_REFINT_SHIFT)) - -#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ - CSCONFIG_ODT_WR_CFG | \ - CSCONFIG_ROW_BIT_13 | \ - CSCONFIG_COL_BIT_10) - -#define CONFIG_SYS_DDR_MODE 0x47860242 -#define CONFIG_SYS_DDR_MODE2 0x8080c000 - -#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ - (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ - (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ - (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ - (0 << TIMING_CFG0_WWT_SHIFT) | \ - (0 << TIMING_CFG0_RRT_SHIFT) | \ - (0 << TIMING_CFG0_WRT_SHIFT) | \ - (0 << TIMING_CFG0_RWT_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \ - (2 << TIMING_CFG1_WRTORD_SHIFT) | \ - (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ - (3 << TIMING_CFG1_WRREC_SHIFT) | \ - (7 << TIMING_CFG1_REFREC_SHIFT) | \ - (3 << TIMING_CFG1_ACTTORW_SHIFT) | \ - (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ - (3 << TIMING_CFG1_PRETOACT_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ - (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ - (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ - (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ - (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ - (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \ - (5 << TIMING_CFG2_CPO_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_3 0x00000000 - -#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000 -#define CONFIG_SYS_KMBEC_FPGA_SIZE 128 - -/* EEprom support */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 - -/* EEprom support */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 - -/* - * Init Local Bus Memory Controller: - * - * Bank Bus Machine PortSz Size Device - * ---- --- ------- ------ ----- ------ - * 2 Local UPMA 16 bit 256MB APP1 - * 3 Local GPCM 16 bit 256MB APP2 - * - */ - - +#include "km/km-mpc83xx.h" +#include "km/km-mpc832x.h" #define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \ 0x0000c000 | \ diff --git a/include/configs/tuge1.h b/include/configs/tuge1.h index 01d8d6b303..808538ef9d 100644 --- a/include/configs/tuge1.h +++ b/include/configs/tuge1.h @@ -26,283 +26,10 @@ #define CONFIG_KM_BOARD_NAME "tuge1" #define CONFIG_HOSTNAME "tuge1" -/* - * High Level Configuration Options - */ -#define CONFIG_QE /* Has QE */ -#define CONFIG_KM8321 /* Keymile PBEC8321 board specific */ - -#define CONFIG_KM_DEF_ARCH "arch=ppc_8xx\0" - /* include common defines/options for all Keymile boards */ #include "km/keymile-common.h" #include "km/km-powerpc.h" - -/* - * System Clock Setup - */ -#define CONFIG_83XX_CLKIN 66000000 -#define CONFIG_SYS_CLK_FREQ 66000000 -#define CONFIG_83XX_PCICLK 66000000 - -/* - * DDR Setup - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */ - -#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ - DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) - -#define CFG_83XX_DDR_USES_CS0 - -/* - * Manually set up DDR parameters - */ -#define CONFIG_DDR_II -#define CONFIG_SYS_DDR_SIZE 2048 /* MB */ - -/* - * The reserved memory - */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ -#define CONFIG_SYS_FLASH_BASE 0xF0000000 - -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT -#endif - -/* Reserve 768 kB for Mon */ -#define CONFIG_SYS_MONITOR_LEN (768 * 1024) - -/* - * Initial RAM Base Address Setup - */ -#define CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) - -/* - * Init Local Bus Memory Controller: - * - * Bank Bus Machine PortSz Size Device - * ---- --- ------- ------ ----- ------ - * 0 Local GPCM 16 bit 256MB FLASH - * 1 Local GPCM 8 bit 128MB GPIO/PIGGY - * - */ -/* - * FLASH on the Local Bus - */ -#define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ - - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } - -/* - * PRIO1/PIGGY on the local bus CS1 - */ - - -/* - * Serial Port - */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) - -/* - * QE UEC ethernet configuration - */ -#define CONFIG_UEC_ETH -#define CONFIG_ETHPRIME "UEC0" - -#define CONFIG_UEC_ETH1 /* GETH1 */ -#define UEC_VERBOSE_DEBUG 1 - -#ifdef CONFIG_UEC_ETH1 -#define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */ -#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ -#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17 -#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH -#define CONFIG_SYS_UEC1_PHY_ADDR 0 -#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII -#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 -#endif - -/* - * Environment - */ - -#ifndef CONFIG_SYS_RAMBOOT -#ifndef CONFIG_ENV_ADDR -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ - CONFIG_SYS_MONITOR_LEN) -#endif -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ -#ifndef CONFIG_ENV_OFFSET -#define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN) -#endif - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#else /* CFG_SYS_RAMBOOT */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) -#define CONFIG_ENV_SIZE 0x2000 -#endif /* CFG_SYS_RAMBOOT */ - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_NUM_I2C_BUSES 4 -#define CONFIG_SYS_I2C_MAX_HOPS 1 -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 200000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_I2C_OFFSET 0x3000 -#define CONFIG_SYS_FSL_I2C2_SPEED 200000 -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 -#define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \ - {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \ - {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \ - {1, {I2C_NULL_HOP} } } - -#define CONFIG_KM_IVM_BUS 2 /* I2C2 (Mux-Port 1)*/ - -#if defined(CONFIG_CMD_NAND) -#define CONFIG_NAND_KMETER1 -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE -#endif - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) - -/* - * Internal Definitions - */ -#define BOOTFLASH_START 0xF0000000 - -#define CONFIG_KM_CONSOLE_TTY "ttyS0" - -/* - * Environment Configuration - */ -#define CONFIG_ENV_OVERWRITE -#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ -#define CONFIG_KM_DEF_ENV "km-common=empty\0" -#endif - -#ifndef CONFIG_KM_DEF_ARCH -#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" -#endif - -#define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_KM_DEF_ENV \ - CONFIG_KM_DEF_ARCH \ - "newenv=" \ - "prot off "__stringify(CONFIG_ENV_ADDR)" +0x40000 && " \ - "era "__stringify(CONFIG_ENV_ADDR)" +0x40000\0" \ - "unlock=yes\0" \ - "" - -#if defined(CONFIG_UEC_ETH) -#define CONFIG_HAS_ETH0 -#endif - -/* - * System IO Config - */ -#define CONFIG_SYS_SICRL SICRL_IRQ_CKS - -#define CONFIG_SYS_DDRCDR (\ - DDRCDR_EN | \ - DDRCDR_PZ_MAXZ | \ - DDRCDR_NZ_MAXZ | \ - DDRCDR_M_ODR) - -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f -#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ - SDRAM_CFG_32_BE | \ - SDRAM_CFG_SREN | \ - SDRAM_CFG_HSE) - -#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 -#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) -#define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ - (0x200 << SDRAM_INTERVAL_REFINT_SHIFT)) - -#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ - CSCONFIG_ODT_WR_CFG | \ - CSCONFIG_ROW_BIT_13 | \ - CSCONFIG_COL_BIT_10) - -#define CONFIG_SYS_DDR_MODE 0x47860242 -#define CONFIG_SYS_DDR_MODE2 0x8080c000 - -#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ - (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ - (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ - (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ - (0 << TIMING_CFG0_WWT_SHIFT) | \ - (0 << TIMING_CFG0_RRT_SHIFT) | \ - (0 << TIMING_CFG0_WRT_SHIFT) | \ - (0 << TIMING_CFG0_RWT_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \ - (2 << TIMING_CFG1_WRTORD_SHIFT) | \ - (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ - (3 << TIMING_CFG1_WRREC_SHIFT) | \ - (7 << TIMING_CFG1_REFREC_SHIFT) | \ - (3 << TIMING_CFG1_ACTTORW_SHIFT) | \ - (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ - (3 << TIMING_CFG1_PRETOACT_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ - (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ - (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ - (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ - (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ - (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \ - (5 << TIMING_CFG2_CPO_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_3 0x00000000 - -#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000 -#define CONFIG_SYS_KMBEC_FPGA_SIZE 128 - -/* EEprom support */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 - -/* - * Init Local Bus Memory Controller: - * Device on board - * Bank Bus Machine PortSz Size TUDA1 TUXA1 TUGE1 KMSUPX4 KMOPTI2 - * ----------------------------------------------------------------------------- - * 2 Local GPCM 8 bit 256MB PAXG LPXF PAXI LPXF PAXE - * 3 Local GPCM 8 bit 256MB PINC3 PINC2 unused unused OPI2(16 bit) - * - * Device on board (continued) - * Bank Bus Machine PortSz Size KMTEPR2 - * ----------------------------------------------------------------------------- - * 2 Local GPCM 8 bit 256MB NVRAM - * 3 Local GPCM 8 bit 256MB TEP2 (16 bit) - */ - +#include "km/km-mpc83xx.h" +#include "km/km-mpc832x.h" #endif /* __CONFIG_H */ diff --git a/include/configs/tuxx1.h b/include/configs/tuxx1.h index 15a69ceca7..0eb673a947 100644 --- a/include/configs/tuxx1.h +++ b/include/configs/tuxx1.h @@ -26,285 +26,11 @@ #define CONFIG_KM_BOARD_NAME "tuxx1" #define CONFIG_HOSTNAME "tuxx1" -/* - * High Level Configuration Options - */ -#define CONFIG_QE /* Has QE */ -#define CONFIG_KM8321 /* Keymile PBEC8321 board specific */ - -#define CONFIG_KM_DEF_ARCH "arch=ppc_8xx\0" - /* include common defines/options for all Keymile boards */ #include "km/keymile-common.h" #include "km/km-powerpc.h" - -/* - * System Clock Setup - */ -#define CONFIG_83XX_CLKIN 66000000 -#define CONFIG_SYS_CLK_FREQ 66000000 -#define CONFIG_83XX_PCICLK 66000000 - -/* - * DDR Setup - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */ - -#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ - DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) - -#define CFG_83XX_DDR_USES_CS0 - -/* - * Manually set up DDR parameters - */ -#define CONFIG_DDR_II -#define CONFIG_SYS_DDR_SIZE 2048 /* MB */ - -/* - * The reserved memory - */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ -#define CONFIG_SYS_FLASH_BASE 0xF0000000 - -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT -#endif - -/* Reserve 768 kB for Mon */ -#define CONFIG_SYS_MONITOR_LEN (768 * 1024) - -/* - * Initial RAM Base Address Setup - */ -#define CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) - -/* - * Init Local Bus Memory Controller: - * - * Bank Bus Machine PortSz Size Device - * ---- --- ------- ------ ----- ------ - * 0 Local GPCM 16 bit 256MB FLASH - * 1 Local GPCM 8 bit 128MB GPIO/PIGGY - * - */ -/* - * FLASH on the Local Bus - */ -#define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ - - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } - -/* - * PRIO1/PIGGY on the local bus CS1 - */ - - -/* - * Serial Port - */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) - -/* - * QE UEC ethernet configuration - */ -#define CONFIG_UEC_ETH -#define CONFIG_ETHPRIME "UEC0" - -#define CONFIG_UEC_ETH1 /* GETH1 */ -#define UEC_VERBOSE_DEBUG 1 - -#ifdef CONFIG_UEC_ETH1 -#define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */ -#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ -#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17 -#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH -#define CONFIG_SYS_UEC1_PHY_ADDR 0 -#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII -#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 -#endif - -/* - * Environment - */ - -#ifndef CONFIG_SYS_RAMBOOT -#ifndef CONFIG_ENV_ADDR -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ - CONFIG_SYS_MONITOR_LEN) -#endif -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ -#ifndef CONFIG_ENV_OFFSET -#define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN) -#endif - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#else /* CFG_SYS_RAMBOOT */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) -#define CONFIG_ENV_SIZE 0x2000 -#endif /* CFG_SYS_RAMBOOT */ - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_NUM_I2C_BUSES 4 -#define CONFIG_SYS_I2C_MAX_HOPS 1 -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 200000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_I2C_OFFSET 0x3000 -#define CONFIG_SYS_FSL_I2C2_SPEED 200000 -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 -#define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \ - {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \ - {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \ - {1, {I2C_NULL_HOP} } } - -#define CONFIG_KM_IVM_BUS 2 /* I2C2 (Mux-Port 1)*/ - -#if defined(CONFIG_CMD_NAND) -#define CONFIG_NAND_KMETER1 -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE -#endif - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) - -/* - * Internal Definitions - */ -#define BOOTFLASH_START 0xF0000000 - -#define CONFIG_KM_CONSOLE_TTY "ttyS0" - -/* - * Environment Configuration - */ -#define CONFIG_ENV_OVERWRITE -#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ -#define CONFIG_KM_DEF_ENV "km-common=empty\0" -#endif - -#ifndef CONFIG_KM_DEF_ARCH -#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" -#endif - -#define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_KM_DEF_ENV \ - CONFIG_KM_DEF_ARCH \ - "newenv=" \ - "prot off "__stringify(CONFIG_ENV_ADDR)" +0x40000 && " \ - "era "__stringify(CONFIG_ENV_ADDR)" +0x40000\0" \ - "unlock=yes\0" \ - "" - -#if defined(CONFIG_UEC_ETH) -#define CONFIG_HAS_ETH0 -#endif - -/* - * System IO Config - */ -#define CONFIG_SYS_SICRL SICRL_IRQ_CKS - -#define CONFIG_SYS_DDRCDR (\ - DDRCDR_EN | \ - DDRCDR_PZ_MAXZ | \ - DDRCDR_NZ_MAXZ | \ - DDRCDR_M_ODR) - -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f -#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ - SDRAM_CFG_32_BE | \ - SDRAM_CFG_SREN | \ - SDRAM_CFG_HSE) - -#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 -#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) -#define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ - (0x200 << SDRAM_INTERVAL_REFINT_SHIFT)) - -#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ - CSCONFIG_ODT_WR_CFG | \ - CSCONFIG_ROW_BIT_13 | \ - CSCONFIG_COL_BIT_10) - -#define CONFIG_SYS_DDR_MODE 0x47860242 -#define CONFIG_SYS_DDR_MODE2 0x8080c000 - -#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ - (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ - (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ - (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ - (0 << TIMING_CFG0_WWT_SHIFT) | \ - (0 << TIMING_CFG0_RRT_SHIFT) | \ - (0 << TIMING_CFG0_WRT_SHIFT) | \ - (0 << TIMING_CFG0_RWT_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \ - (2 << TIMING_CFG1_WRTORD_SHIFT) | \ - (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ - (3 << TIMING_CFG1_WRREC_SHIFT) | \ - (7 << TIMING_CFG1_REFREC_SHIFT) | \ - (3 << TIMING_CFG1_ACTTORW_SHIFT) | \ - (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ - (3 << TIMING_CFG1_PRETOACT_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ - (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ - (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ - (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ - (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ - (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \ - (5 << TIMING_CFG2_CPO_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_3 0x00000000 - -#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000 -#define CONFIG_SYS_KMBEC_FPGA_SIZE 128 - -/* EEprom support */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 - -/* - * Init Local Bus Memory Controller: - * Device on board - * Bank Bus Machine PortSz Size TUDA1 TUXA1 TUGE1 KMSUPX4 KMOPTI2 - * ----------------------------------------------------------------------------- - * 2 Local GPCM 8 bit 256MB PAXG LPXF PAXI LPXF PAXE - * 3 Local GPCM 8 bit 256MB PINC3 PINC2 unused unused OPI2(16 bit) - * - * Device on board (continued) - * Bank Bus Machine PortSz Size KMTEPR2 - * ----------------------------------------------------------------------------- - * 2 Local GPCM 8 bit 256MB NVRAM - * 3 Local GPCM 8 bit 256MB TEP2 (16 bit) - */ - - +#include "km/km-mpc83xx.h" +#include "km/km-mpc832x.h" #define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \ 0x0000c000 | \ From 6fffab74cd42009ed7189f3c0b00fa19dfb8051a Mon Sep 17 00:00:00 2001 From: Mario Six Date: Mon, 28 Jan 2019 09:33:39 +0100 Subject: [PATCH 61/86] powerpc: Simplify processor.h Lots of stuff in processor.h was taken verbatim from the Linux kernel. It was never synced, so most of it was removed or changed in the kernel since it was imported. Remove all the stuff that is unused in the current U-Boot sources; should anybody feel the need to re-sync with the kernel, they can do it later on. Signed-off-by: Mario Six --- arch/powerpc/include/asm/processor.h | 120 --------------------------- 1 file changed, 120 deletions(-) diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h index f97ce48cc2..e03ab21f59 100644 --- a/arch/powerpc/include/asm/processor.h +++ b/arch/powerpc/include/asm/processor.h @@ -1203,127 +1203,7 @@ int fsl_qoriq_dsp_core_to_cluster(unsigned int core); #endif #endif - -/* what kind of prep workstation we are */ -extern int _prep_type; -/* - * This is used to identify the board type from a given PReP board - * vendor. Board revision is also made available. - */ -extern unsigned char ucSystemType; -extern unsigned char ucBoardRev; -extern unsigned char ucBoardRevMaj, ucBoardRevMin; - struct task_struct; -void start_thread(struct pt_regs *regs, unsigned long nip, unsigned long sp); -void release_thread(struct task_struct *); - -/* - * Create a new kernel thread. - */ -extern long kernel_thread(int (*fn)(void *), void *arg, unsigned long flags); - -/* - * Bus types - */ -#define EISA_bus 0 -#define EISA_bus__is_a_macro /* for versions in ksyms.c */ -#define MCA_bus 0 -#define MCA_bus__is_a_macro /* for versions in ksyms.c */ - -/* Lazy FPU handling on uni-processor */ -extern struct task_struct *last_task_used_math; -extern struct task_struct *last_task_used_altivec; - -/* - * this is the minimum allowable io space due to the location - * of the io areas on prep (first one at 0x80000000) but - * as soon as I get around to remapping the io areas with the BATs - * to match the mac we can raise this. -- Cort - */ -#define TASK_SIZE (0x80000000UL) - -/* This decides where the kernel will search for a free chunk of vm - * space during mmap's. - */ -#define TASK_UNMAPPED_BASE (TASK_SIZE / 8 * 3) - -typedef struct { - unsigned long seg; -} mm_segment_t; - -struct thread_struct { - unsigned long ksp; /* Kernel stack pointer */ - unsigned long wchan; /* Event task is sleeping on */ - struct pt_regs *regs; /* Pointer to saved register state */ - mm_segment_t fs; /* for get_fs() validation */ - void *pgdir; /* root of page-table tree */ - signed long last_syscall; - double fpr[32]; /* Complete floating point set */ - unsigned long fpscr_pad; /* fpr ... fpscr must be contiguous */ - unsigned long fpscr; /* Floating point status */ -#ifdef CONFIG_ALTIVEC - vector128 vr[32]; /* Complete AltiVec set */ - vector128 vscr; /* AltiVec status */ - unsigned long vrsave; -#endif /* CONFIG_ALTIVEC */ -}; - -#define INIT_SP (sizeof(init_stack) + (unsigned long) &init_stack) - -#define INIT_THREAD { \ - INIT_SP, /* ksp */ \ - 0, /* wchan */ \ - (struct pt_regs *)INIT_SP - 1, /* regs */ \ - KERNEL_DS, /*fs*/ \ - swapper_pg_dir, /* pgdir */ \ - 0, /* last_syscall */ \ - {0}, 0, 0 \ -} - -/* - * Note: the vm_start and vm_end fields here should *not* - * be in kernel space. (Could vm_end == vm_start perhaps?) - */ -#define INIT_MMAP { &init_mm, 0, 0x1000, NULL, \ - PAGE_SHARED, VM_READ | VM_WRITE | VM_EXEC, \ - 1, NULL, NULL } - -/* - * Return saved PC of a blocked thread. For now, this is the "user" PC - */ -static inline unsigned long thread_saved_pc(struct thread_struct *t) -{ - return (t->regs) ? t->regs->nip : 0; -} - -#define copy_segments(tsk, mm) do { } while (0) -#define release_segments(mm) do { } while (0) -#define forget_segments() do { } while (0) - -unsigned long get_wchan(struct task_struct *p); - -#define KSTK_EIP(tsk) ((tsk)->thread.regs->nip) -#define KSTK_ESP(tsk) ((tsk)->thread.regs->gpr[1]) - -/* - * NOTE! The task struct and the stack go together - */ -#define THREAD_SIZE (2*PAGE_SIZE) -#define alloc_task_struct() \ - ((struct task_struct *) __get_free_pages(GFP_KERNEL,1)) -#define free_task_struct(p) free_pages((unsigned long)(p),1) -#define get_task_struct(tsk) atomic_inc(&mem_map[MAP_NR(tsk)].count) - -/* in process.c - for early bootup debug -- Cort */ -int ll_printk(const char *, ...); -void ll_puts(const char *); - -#define init_task (init_task_union.task) -#define init_stack (init_task_union.stack) - -/* In misc.c */ -void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val); #ifndef CONFIG_CPU_MPC83XX int prt_83xx_rsr(void); From 7e3974e1f404cf69cc37de408453bd7ddf6b4845 Mon Sep 17 00:00:00 2001 From: Mario Six Date: Mon, 28 Jan 2019 09:36:23 +0100 Subject: [PATCH 62/86] mpc83xx: Define _end symbol To support OF_EMBED, the MPC83xx architecture has to define the "_end" symbol to correctly access the appended DT. Fortunately, MPC8xx already defines the symbol, and the linker script is quite similar to that of MPC83xx, so copy this approach for MPC83xx. Signed-off-by: Mario Six --- arch/powerpc/cpu/mpc83xx/u-boot.lds | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/powerpc/cpu/mpc83xx/u-boot.lds b/arch/powerpc/cpu/mpc83xx/u-boot.lds index 37a13fd8c2..d10f528da4 100644 --- a/arch/powerpc/cpu/mpc83xx/u-boot.lds +++ b/arch/powerpc/cpu/mpc83xx/u-boot.lds @@ -52,6 +52,12 @@ SECTIONS __ex_table : { *(__ex_table) } __stop___ex_table = .; + /* + * _end - This is end of u-boot.bin image. + * dtb will be appended here to make u-boot-dtb.bin + */ + _end = .; + . = ALIGN(4096); __init_begin = .; .text.init : { *(.text.init) } From 487bb2bc85a51ce14bb27c183c9ab51090b632d0 Mon Sep 17 00:00:00 2001 From: Mario Six Date: Mon, 28 Jan 2019 09:40:36 +0100 Subject: [PATCH 63/86] mpc83xx_clk: Add enable method Some DM drivers have hardcoded clk_enable calls when handling clocks (for example the fsl_esdhc driver). To work with these drivers, add an enable method to the MCP83xx clock driver (which does nothing, because the clocks are always enabled). Signed-off-by: Mario Six --- drivers/clk/mpc83xx_clk.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/clk/mpc83xx_clk.c b/drivers/clk/mpc83xx_clk.c index 489004190e..32d2db9eda 100644 --- a/drivers/clk/mpc83xx_clk.c +++ b/drivers/clk/mpc83xx_clk.c @@ -275,6 +275,12 @@ static ulong mpc83xx_clk_get_rate(struct clk *clk) return priv->speed[clk->id]; } +static int mpc83xx_clk_enable(struct clk *clk) +{ + /* MPC83xx clocks are always enabled */ + return 0; +} + int get_clocks(void) { /* Empty implementation to keep the prototype in common.h happy */ @@ -301,6 +307,7 @@ int get_serial_clock(void) const struct clk_ops mpc83xx_clk_ops = { .request = mpc83xx_clk_request, .get_rate = mpc83xx_clk_get_rate, + .enable = mpc83xx_clk_enable, }; static const struct udevice_id mpc83xx_clk_match[] = { From 29dada9c2e1637aede9985ded2959342e2d4a458 Mon Sep 17 00:00:00 2001 From: Mario Six Date: Mon, 28 Jan 2019 09:43:42 +0100 Subject: [PATCH 64/86] cmd: binop: Use new environment api Since the binop command was introduced, the environment API was changed. Use the new API to make the command work again. Signed-off-by: Mario Six Reviewed-by: Simon Glass --- cmd/binop.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/cmd/binop.c b/cmd/binop.c index 787f7a26ea..be780bffd7 100644 --- a/cmd/binop.c +++ b/cmd/binop.c @@ -26,7 +26,7 @@ void write_to_env_var(char *varname, u8 *result, ulong len) str_ptr += 2; } *str_ptr = '\0'; - setenv(varname, str_output); + env_set(varname, str_output); free(str_output); } @@ -58,7 +58,7 @@ void read_from_env_var(char *varname, u8 *result) { char *str_value; - str_value = getenv(varname); + str_value = env_get(varname); if (str_value) decode_hexstring(str_value, result); else From 32dbe8c58a28ea4cd1c9370be9e99fd644b9d5a7 Mon Sep 17 00:00:00 2001 From: Mario Six Date: Mon, 28 Jan 2019 09:43:43 +0100 Subject: [PATCH 65/86] cmd: binop: Use hex2bin Use the new hex2bin function in the binop command instead of converting the data manually. Signed-off-by: Mario Six Reviewed-by: Simon Glass --- cmd/binop.c | 28 +++------------------------- 1 file changed, 3 insertions(+), 25 deletions(-) diff --git a/cmd/binop.c b/cmd/binop.c index be780bffd7..116a2c0d55 100644 --- a/cmd/binop.c +++ b/cmd/binop.c @@ -2,6 +2,7 @@ #include #include +#include #include #include #include @@ -31,38 +32,15 @@ void write_to_env_var(char *varname, u8 *result, ulong len) free(str_output); } -void decode_hexstring(char *hexstr, u8 *result) -{ - int i; - int acc = 0; - - for (i = 0; i < strlen(hexstr); ++i) { - char d = hexstr[i]; - int value; - - if (isdigit(d)) - value = (d - '0'); - else - value = (islower(d) ? toupper(d) : d) - 'A' + 10; - - if (i % 2 == 0) { - acc = value * 16; - } else { - result[i / 2] = acc + value; - acc = 0; - } - } -} - void read_from_env_var(char *varname, u8 *result) { char *str_value; str_value = env_get(varname); if (str_value) - decode_hexstring(str_value, result); + hex2bin(result, str_value, strlen(str_value) / 2); else - decode_hexstring(varname, result); + hex2bin(result, varname, strlen(varname) / 2); } void read_from_mem(ulong addr, u8 *result, ulong len) From 98e4249f97ab5784c5f9e281519c7277c0b7588c Mon Sep 17 00:00:00 2001 From: Mario Six Date: Mon, 28 Jan 2019 09:45:57 +0100 Subject: [PATCH 66/86] i2c: ihs: Get rid of fpgamap Since the IHS I2C driver want upstream, the surrounding infrastructure has changed quite a bit (notably, the fpgamap driver was replaced with a regmap driver). Update the driver to work with these changes. Signed-off-by: Mario Six Reviewed-by: Heiko Schocher --- drivers/i2c/ihs_i2c.c | 57 +++++++++++++++++-------------------------- 1 file changed, 23 insertions(+), 34 deletions(-) diff --git a/drivers/i2c/ihs_i2c.c b/drivers/i2c/ihs_i2c.c index 0922fe9bb1..5313490bf3 100644 --- a/drivers/i2c/ihs_i2c.c +++ b/drivers/i2c/ihs_i2c.c @@ -8,8 +8,7 @@ #include #ifdef CONFIG_DM_I2C #include -#include -#include "../misc/gdsys_soc.h" +#include #else #include #endif @@ -18,18 +17,24 @@ #ifdef CONFIG_DM_I2C struct ihs_i2c_priv { uint speed; - phys_addr_t addr; + struct regmap *map; }; -enum { - REG_INTERRUPT_STATUS = 0x00, - REG_INTERRUPT_ENABLE_CONTROL = 0x02, - REG_WRITE_MAILBOX_EXT = 0x04, - REG_WRITE_MAILBOX = 0x06, - REG_READ_MAILBOX_EXT = 0x08, - REG_READ_MAILBOX = 0x0A, +struct ihs_i2c_regs { + u16 interrupt_status; + u16 interrupt_enable_control; + u16 write_mailbox_ext; + u16 write_mailbox; + u16 read_mailbox_ext; + u16 read_mailbox; }; +#define ihs_i2c_set(map, member, val) \ + regmap_set(map, struct ihs_i2c_regs, member, val) + +#define ihs_i2c_get(map, member, valp) \ + regmap_get(map, struct ihs_i2c_regs, member, valp) + #else /* !CONFIG_DM_I2C */ DECLARE_GLOBAL_DATA_PTR; @@ -92,14 +97,10 @@ static int wait_for_int(bool read) uint ctr = 0; #ifdef CONFIG_DM_I2C struct ihs_i2c_priv *priv = dev_get_priv(dev); - struct udevice *fpga; - - gdsys_soc_get_fpga(dev, &fpga); #endif #ifdef CONFIG_DM_I2C - fpgamap_read(fpga, priv->addr + REG_INTERRUPT_STATUS, &val, - FPGAMAP_SIZE_16); + ihs_i2c_get(priv->map, interrupt_status, &val); #else I2C_GET_REG(interrupt_status, &val); #endif @@ -110,8 +111,7 @@ static int wait_for_int(bool read) if (ctr++ > 5000) return 1; #ifdef CONFIG_DM_I2C - fpgamap_read(fpga, priv->addr + REG_INTERRUPT_STATUS, &val, - FPGAMAP_SIZE_16); + ihs_i2c_get(priv->map, interrupt_status, &val); #else I2C_GET_REG(interrupt_status, &val); #endif @@ -132,18 +132,13 @@ static int ihs_i2c_transfer(uchar chip, uchar *buffer, int len, bool read, u16 data; #ifdef CONFIG_DM_I2C struct ihs_i2c_priv *priv = dev_get_priv(dev); - struct udevice *fpga; - - gdsys_soc_get_fpga(dev, &fpga); #endif /* Clear interrupt status */ data = I2CINT_ERROR_EV | I2CINT_RECEIVE_EV | I2CINT_TRANSMIT_EV; #ifdef CONFIG_DM_I2C - fpgamap_write(fpga, priv->addr + REG_INTERRUPT_STATUS, &data, - FPGAMAP_SIZE_16); - fpgamap_read(fpga, priv->addr + REG_INTERRUPT_STATUS, &val, - FPGAMAP_SIZE_16); + ihs_i2c_set(priv->map, interrupt_status, data); + ihs_i2c_get(priv->map, interrupt_status, &val); #else I2C_SET_REG(interrupt_status, data); I2C_GET_REG(interrupt_status, &val); @@ -156,8 +151,7 @@ static int ihs_i2c_transfer(uchar chip, uchar *buffer, int len, bool read, if (len > 1) val |= buffer[1] << 8; #ifdef CONFIG_DM_I2C - fpgamap_write(fpga, priv->addr + REG_WRITE_MAILBOX_EXT, &val, - FPGAMAP_SIZE_16); + ihs_i2c_set(priv->map, write_mailbox_ext, val); #else I2C_SET_REG(write_mailbox_ext, val); #endif @@ -170,8 +164,7 @@ static int ihs_i2c_transfer(uchar chip, uchar *buffer, int len, bool read, | (is_last ? 0 : I2CMB_HOLD_BUS); #ifdef CONFIG_DM_I2C - fpgamap_write(fpga, priv->addr + REG_WRITE_MAILBOX, &data, - FPGAMAP_SIZE_16); + ihs_i2c_set(priv->map, write_mailbox, data); #else I2C_SET_REG(write_mailbox, data); #endif @@ -186,8 +179,7 @@ static int ihs_i2c_transfer(uchar chip, uchar *buffer, int len, bool read, /* If we want to read, get the bytes from the mailbox */ if (read) { #ifdef CONFIG_DM_I2C - fpgamap_read(fpga, priv->addr + REG_READ_MAILBOX_EXT, &val, - FPGAMAP_SIZE_16); + ihs_i2c_get(priv->map, read_mailbox_ext, &val); #else I2C_GET_REG(read_mailbox_ext, &val); #endif @@ -270,11 +262,8 @@ static int ihs_i2c_access(struct i2c_adapter *adap, uchar chip, u8 *addr, int ihs_i2c_probe(struct udevice *bus) { struct ihs_i2c_priv *priv = dev_get_priv(bus); - int addr; - addr = dev_read_u32_default(bus, "reg", -1); - - priv->addr = addr; + regmap_init_mem(dev_ofnode(bus), &priv->map); return 0; } From 482c76e7c386da683e2fc5b6f939fc8d80a0f186 Mon Sep 17 00:00:00 2001 From: Mario Six Date: Mon, 28 Jan 2019 09:45:58 +0100 Subject: [PATCH 67/86] i2c: ihs: Improve error handling Improve the error handling and reporting of the IHS I2C driver. Signed-off-by: Mario Six Reviewed-by: Heiko Schocher --- drivers/i2c/ihs_i2c.c | 67 +++++++++++++++++++++++++++---------------- 1 file changed, 43 insertions(+), 24 deletions(-) diff --git a/drivers/i2c/ihs_i2c.c b/drivers/i2c/ihs_i2c.c index 5313490bf3..f7b59d36f9 100644 --- a/drivers/i2c/ihs_i2c.c +++ b/drivers/i2c/ihs_i2c.c @@ -108,8 +108,10 @@ static int wait_for_int(bool read) while (!(val & (I2CINT_ERROR_EV | (read ? I2CINT_RECEIVE_EV : I2CINT_TRANSMIT_EV)))) { udelay(10); - if (ctr++ > 5000) - return 1; + if (ctr++ > 5000) { + debug("%s: timed out\n", __func__); + return -ETIMEDOUT; + } #ifdef CONFIG_DM_I2C ihs_i2c_get(priv->map, interrupt_status, &val); #else @@ -117,7 +119,7 @@ static int wait_for_int(bool read) #endif } - return (val & I2CINT_ERROR_EV) ? 1 : 0; + return (val & I2CINT_ERROR_EV) ? -EIO : 0; } #ifdef CONFIG_DM_I2C @@ -130,6 +132,7 @@ static int ihs_i2c_transfer(uchar chip, uchar *buffer, int len, bool read, { u16 val; u16 data; + int res; #ifdef CONFIG_DM_I2C struct ihs_i2c_priv *priv = dev_get_priv(dev); #endif @@ -170,11 +173,16 @@ static int ihs_i2c_transfer(uchar chip, uchar *buffer, int len, bool read, #endif #ifdef CONFIG_DM_I2C - if (wait_for_int(dev, read)) + res = wait_for_int(dev, read); #else - if (wait_for_int(read)) + res = wait_for_int(read); #endif - return 1; + if (res) { + if (res == -ETIMEDOUT) + debug("%s: time out while waiting for event\n", __func__); + + return res; + } /* If we want to read, get the bytes from the mailbox */ if (read) { @@ -198,19 +206,21 @@ static int ihs_i2c_send_buffer(uchar chip, u8 *data, int len, bool hold_bus, int read) #endif { + int res; + while (len) { int transfer = min(len, 2); bool is_last = len <= transfer; #ifdef CONFIG_DM_I2C - if (ihs_i2c_transfer(dev, chip, data, transfer, read, - hold_bus ? false : is_last)) - return 1; + res = ihs_i2c_transfer(dev, chip, data, transfer, read, + hold_bus ? false : is_last); #else - if (ihs_i2c_transfer(chip, data, transfer, read, - hold_bus ? false : is_last)) - return 1; + res = ihs_i2c_transfer(chip, data, transfer, read, + hold_bus ? false : is_last); #endif + if (res) + return res; data += transfer; len -= transfer; @@ -241,14 +251,19 @@ static int ihs_i2c_access(struct i2c_adapter *adap, uchar chip, u8 *addr, int alen, uchar *buffer, int len, int read) #endif { + int res; + /* Don't hold the bus if length of data to send/receive is zero */ + if (len <= 0) + return -EINVAL; + #ifdef CONFIG_DM_I2C - if (len <= 0 || ihs_i2c_address(dev, chip, addr, alen, len)) - return 1; + res = ihs_i2c_address(dev, chip, addr, alen, len); #else - if (len <= 0 || ihs_i2c_address(chip, addr, alen, len)) - return 1; + res = ihs_i2c_address(chip, addr, alen, len); #endif + if (res) + return res; #ifdef CONFIG_DM_I2C return ihs_i2c_send_buffer(dev, chip, buffer, len, false, read); @@ -273,7 +288,7 @@ static int ihs_i2c_set_bus_speed(struct udevice *bus, uint speed) struct ihs_i2c_priv *priv = dev_get_priv(bus); if (speed != priv->speed && priv->speed != 0) - return 1; + return -EINVAL; priv->speed = speed; @@ -290,8 +305,8 @@ static int ihs_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs) * actucal data) or one message (just data) */ if (nmsgs > 2 || nmsgs == 0) { - debug("%s: Only one or two messages are supported.", __func__); - return -1; + debug("%s: Only one or two messages are supported\n", __func__); + return -ENOTSUPP; } omsg = nmsgs == 1 ? &dummy : msg; @@ -311,9 +326,11 @@ static int ihs_i2c_probe_chip(struct udevice *bus, u32 chip_addr, u32 chip_flags) { uchar buffer[2]; + int res; - if (ihs_i2c_transfer(bus, chip_addr, buffer, 0, I2COP_READ, true)) - return 1; + res = ihs_i2c_transfer(bus, chip_addr, buffer, 0, I2COP_READ, true); + if (res) + return res; return 0; } @@ -355,9 +372,11 @@ static void ihs_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr) static int ihs_i2c_probe(struct i2c_adapter *adap, uchar chip) { uchar buffer[2]; + int res; - if (ihs_i2c_transfer(chip, buffer, 0, I2COP_READ, true)) - return 1; + res = ihs_i2c_transfer(chip, buffer, 0, I2COP_READ, true); + if (res) + return res; return 0; } @@ -388,7 +407,7 @@ static unsigned int ihs_i2c_set_bus_speed(struct i2c_adapter *adap, unsigned int speed) { if (speed != adap->speed) - return 1; + return -EINVAL; return speed; } From ca0eab2dcfe5e742a2e663dc10829679879f7b98 Mon Sep 17 00:00:00 2001 From: Mario Six Date: Mon, 28 Jan 2019 09:47:41 +0100 Subject: [PATCH 68/86] gdsys_rxaui_ctrl: Return old state Make the gdsys_rxaui_ctrl polarity setting function return the old state to comply with the API requirements. Signed-off-by: Mario Six --- drivers/misc/gdsys_rxaui_ctrl.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/misc/gdsys_rxaui_ctrl.c b/drivers/misc/gdsys_rxaui_ctrl.c index 9a63c329bc..f2c955b13d 100644 --- a/drivers/misc/gdsys_rxaui_ctrl.c +++ b/drivers/misc/gdsys_rxaui_ctrl.c @@ -29,6 +29,7 @@ struct gdsys_rxaui_ctrl_regs { struct gdsys_rxaui_ctrl_priv { struct regmap *map; + bool state; }; int gdsys_rxaui_set_polarity_inversion(struct udevice *dev, bool val) @@ -36,6 +37,8 @@ int gdsys_rxaui_set_polarity_inversion(struct udevice *dev, bool val) struct gdsys_rxaui_ctrl_priv *priv = dev_get_priv(dev); u16 state; + priv->state = !priv->state; + rxaui_ctrl_get(priv->map, ctrl_1, &state); if (val) @@ -45,7 +48,7 @@ int gdsys_rxaui_set_polarity_inversion(struct udevice *dev, bool val) rxaui_ctrl_set(priv->map, ctrl_1, state); - return 0; + return !priv->state; } static const struct misc_ops gdsys_rxaui_ctrl_ops = { @@ -58,6 +61,8 @@ int gdsys_rxaui_ctrl_probe(struct udevice *dev) regmap_init_mem(dev, &priv->map); + priv->state = false; + return 0; } From 935a89241c97cdd671326c98c43f3833dba96a5b Mon Sep 17 00:00:00 2001 From: Mario Six Date: Mon, 28 Jan 2019 09:47:42 +0100 Subject: [PATCH 69/86] gdsys_rxaui_ctrl: Use new regmap interface For the DM case, use the proper parameter for the regmap_init_mem call (which is the ofnode, not the udevice). Signed-off-by: Mario Six --- drivers/misc/gdsys_rxaui_ctrl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/misc/gdsys_rxaui_ctrl.c b/drivers/misc/gdsys_rxaui_ctrl.c index f2c955b13d..c56abce4d4 100644 --- a/drivers/misc/gdsys_rxaui_ctrl.c +++ b/drivers/misc/gdsys_rxaui_ctrl.c @@ -59,7 +59,7 @@ int gdsys_rxaui_ctrl_probe(struct udevice *dev) { struct gdsys_rxaui_ctrl_priv *priv = dev_get_priv(dev); - regmap_init_mem(dev, &priv->map); + regmap_init_mem(dev_ofnode(dev), &priv->map); priv->state = false; From e29dfce06cddc9cbc67f69c4a2fa9732caf73b26 Mon Sep 17 00:00:00 2001 From: Mario Six Date: Mon, 28 Jan 2019 09:49:33 +0100 Subject: [PATCH 70/86] ihs_mdio: Use new regmap interface For the DM case, use the proper parameter for the regmap_init_mem call (which is the ofnode, not the udevice). Signed-off-by: Mario Six Reviewed-by: Simon Glass --- board/gdsys/common/ihs_mdio.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/board/gdsys/common/ihs_mdio.c b/board/gdsys/common/ihs_mdio.c index b17e8db91b..f160a57cc2 100644 --- a/board/gdsys/common/ihs_mdio.c +++ b/board/gdsys/common/ihs_mdio.c @@ -11,6 +11,7 @@ #include #else #include +#include #include #endif @@ -28,7 +29,7 @@ static inline u16 read_reg(struct udevice *fpga, uint base, uint addr) struct regmap *map; u8 *ptr; - regmap_init_mem(fpga, &map); + regmap_init_mem(dev_ofnode(fpga), &map); ptr = regmap_get_range(map, 0); return in_le16((u16 *)(ptr + base + addr)); @@ -40,7 +41,7 @@ static inline void write_reg(struct udevice *fpga, uint base, uint addr, struct regmap *map; u8 *ptr; - regmap_init_mem(fpga, &map); + regmap_init_mem(dev_ofnode(fpga), &map); ptr = regmap_get_range(map, 0); out_le16((u16 *)(ptr + base + addr), val); From 6717d664d719a4675041a837f7e51ae2d8255592 Mon Sep 17 00:00:00 2001 From: Dirk Eibach Date: Fri, 29 Mar 2019 10:18:04 +0100 Subject: [PATCH 71/86] gdsys: phy: Adapt fixup_88e1518() to latest Release Notes The initialization sequence in the newest release notes of the 88e1518 phy omits two commands. Remove them from the sequence. Signed-off-by: Dirk Eibach --- board/gdsys/common/phy.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/board/gdsys/common/phy.c b/board/gdsys/common/phy.c index c4b2256da3..d40c08d9e9 100644 --- a/board/gdsys/common/phy.c +++ b/board/gdsys/common/phy.c @@ -45,8 +45,6 @@ struct mii_setupcmd fixup_88e1518[] = { { MIICMD_SET, 16, 0x214d }, { MIICMD_SET, 17, 0xcc0c }, { MIICMD_SET, 16, 0x2159 }, - { MIICMD_SET, 22, 0x00fb }, - { MIICMD_SET, 7, 0xc00d }, { MIICMD_SET, 22, 0x0000 }, }; From 3f902185f0c6d1179bf24c8e2749b94588e98fb3 Mon Sep 17 00:00:00 2001 From: Mario Six Date: Fri, 29 Mar 2019 10:18:05 +0100 Subject: [PATCH 72/86] gdsys: Post ppc4xx removal cleanup The ppc4xx architecture was removed, and with it several old gdsys 44x boards, but some "debris" from these purged boards was left over. This patch removes these remnants (mostly entries in Makefiles, some now superfluous data structures and some now obsolete config variables from the whitelist). Signed-off-by: Mario Six --- board/gdsys/common/Makefile | 4 -- board/gdsys/common/miiphybb.c | 127 ---------------------------------- include/gdsys_fpga.h | 96 ------------------------- 3 files changed, 227 deletions(-) delete mode 100644 board/gdsys/common/miiphybb.c diff --git a/board/gdsys/common/Makefile b/board/gdsys/common/Makefile index 9090933e34..ff8d6f4966 100644 --- a/board/gdsys/common/Makefile +++ b/board/gdsys/common/Makefile @@ -5,10 +5,6 @@ obj-$(CONFIG_SYS_FPGA_COMMON) += fpga.o obj-$(CONFIG_CMD_IOLOOP) += cmd_ioloop.o -obj-$(CONFIG_IO) += miiphybb.o -obj-$(CONFIG_IO64) += miiphybb.o -obj-$(CONFIG_IOCON) += osd.o mclink.o dp501.o phy.o ch7301.o -obj-$(CONFIG_DLVISION_10G) += osd.o dp501.o obj-$(CONFIG_CONTROLCENTERD) += dp501.o obj-$(CONFIG_TARGET_HRCON) += osd.o mclink.o dp501.o phy.o ioep-fpga.o fanctrl.o obj-$(CONFIG_TARGET_STRIDER) += mclink.o dp501.o phy.o ioep-fpga.o adv7611.o ch7301.o diff --git a/board/gdsys/common/miiphybb.c b/board/gdsys/common/miiphybb.c deleted file mode 100644 index 042835d6af..0000000000 --- a/board/gdsys/common/miiphybb.c +++ /dev/null @@ -1,127 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2010 - * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc - */ - -#include -#include - -#include - -struct io_bb_pinset { - int mdio; - int mdc; -}; - -static int io_bb_mii_init(struct bb_miiphy_bus *bus) -{ - return 0; -} - -static int io_bb_mdio_active(struct bb_miiphy_bus *bus) -{ - struct io_bb_pinset *pins = bus->priv; - - out_be32((void *)GPIO0_TCR, - in_be32((void *)GPIO0_TCR) | pins->mdio); - - return 0; -} - -static int io_bb_mdio_tristate(struct bb_miiphy_bus *bus) -{ - struct io_bb_pinset *pins = bus->priv; - - out_be32((void *)GPIO0_TCR, - in_be32((void *)GPIO0_TCR) & ~pins->mdio); - - return 0; -} - -static int io_bb_set_mdio(struct bb_miiphy_bus *bus, int v) -{ - struct io_bb_pinset *pins = bus->priv; - - if (v) - out_be32((void *)GPIO0_OR, - in_be32((void *)GPIO0_OR) | pins->mdio); - else - out_be32((void *)GPIO0_OR, - in_be32((void *)GPIO0_OR) & ~pins->mdio); - - return 0; -} - -static int io_bb_get_mdio(struct bb_miiphy_bus *bus, int *v) -{ - struct io_bb_pinset *pins = bus->priv; - - *v = ((in_be32((void *)GPIO0_IR) & pins->mdio) != 0); - - return 0; -} - -static int io_bb_set_mdc(struct bb_miiphy_bus *bus, int v) -{ - struct io_bb_pinset *pins = bus->priv; - - if (v) - out_be32((void *)GPIO0_OR, - in_be32((void *)GPIO0_OR) | pins->mdc); - else - out_be32((void *)GPIO0_OR, - in_be32((void *)GPIO0_OR) & ~pins->mdc); - - return 0; -} - -static int io_bb_delay(struct bb_miiphy_bus *bus) -{ - udelay(1); - - return 0; -} - -struct io_bb_pinset io_bb_pinsets[] = { - { - .mdio = CONFIG_SYS_MDIO_PIN, - .mdc = CONFIG_SYS_MDC_PIN, - }, -#ifdef CONFIG_SYS_GBIT_MII1_BUSNAME - { - .mdio = CONFIG_SYS_MDIO1_PIN, - .mdc = CONFIG_SYS_MDC1_PIN, - }, -#endif -}; - -struct bb_miiphy_bus bb_miiphy_buses[] = { - { - .name = CONFIG_SYS_GBIT_MII_BUSNAME, - .init = io_bb_mii_init, - .mdio_active = io_bb_mdio_active, - .mdio_tristate = io_bb_mdio_tristate, - .set_mdio = io_bb_set_mdio, - .get_mdio = io_bb_get_mdio, - .set_mdc = io_bb_set_mdc, - .delay = io_bb_delay, - .priv = &io_bb_pinsets[0], - }, -#ifdef CONFIG_SYS_GBIT_MII1_BUSNAME - { - .name = CONFIG_SYS_GBIT_MII1_BUSNAME, - .init = io_bb_mii_init, - .mdio_active = io_bb_mdio_active, - .mdio_tristate = io_bb_mdio_tristate, - .set_mdio = io_bb_set_mdio, - .get_mdio = io_bb_get_mdio, - .set_mdc = io_bb_set_mdc, - .delay = io_bb_delay, - .priv = &io_bb_pinsets[1], - }, -#endif -}; - -int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) / - sizeof(bb_miiphy_buses[0]); diff --git a/include/gdsys_fpga.h b/include/gdsys_fpga.h index e9fb4b88b5..eae6701262 100644 --- a/include/gdsys_fpga.h +++ b/include/gdsys_fpga.h @@ -86,81 +86,6 @@ struct ihs_fpga { }; #endif -#ifdef CONFIG_IO -struct ihs_fpga { - u16 reflection_low; /* 0x0000 */ - u16 versions; /* 0x0002 */ - u16 fpga_features; /* 0x0004 */ - u16 fpga_version; /* 0x0006 */ - u16 reserved_0[5]; /* 0x0008 */ - u16 quad_serdes_reset; /* 0x0012 */ - u16 reserved_1[8181]; /* 0x0014 */ - u16 reflection_high; /* 0x3ffe */ -}; -#endif - -#ifdef CONFIG_IO64 -struct ihs_fpga_channel { - u16 status_int; - u16 config_int; - u16 switch_connect_config; - u16 tx_destination; -}; - -struct ihs_fpga_hicb { - u16 status_int; - u16 config_int; -}; - -struct ihs_fpga { - u16 reflection_low; /* 0x0000 */ - u16 versions; /* 0x0002 */ - u16 fpga_features; /* 0x0004 */ - u16 fpga_version; /* 0x0006 */ - u16 reserved_0[5]; /* 0x0008 */ - u16 quad_serdes_reset; /* 0x0012 */ - u16 reserved_1[502]; /* 0x0014 */ - struct ihs_fpga_channel ch[32]; /* 0x0400 */ - struct ihs_fpga_channel hicb_ch[32]; /* 0x0500 */ - u16 reserved_2[7487]; /* 0x0580 */ - u16 reflection_high; /* 0x3ffe */ -}; -#endif - -#ifdef CONFIG_IOCON -struct ihs_fpga { - u16 reflection_low; /* 0x0000 */ - u16 versions; /* 0x0002 */ - u16 fpga_version; /* 0x0004 */ - u16 fpga_features; /* 0x0006 */ - u16 reserved_0[1]; /* 0x0008 */ - u16 top_interrupt; /* 0x000a */ - u16 reserved_1[4]; /* 0x000c */ - struct ihs_gpio gpio; /* 0x0014 */ - u16 mpc3w_control; /* 0x001a */ - u16 reserved_2[2]; /* 0x001c */ - struct ihs_io_ep ep; /* 0x0020 */ - u16 reserved_3[9]; /* 0x002e */ - struct ihs_i2c i2c0; /* 0x0040 */ - u16 reserved_4[10]; /* 0x004c */ - u16 mc_int; /* 0x0060 */ - u16 mc_int_en; /* 0x0062 */ - u16 mc_status; /* 0x0064 */ - u16 mc_control; /* 0x0066 */ - u16 mc_tx_data; /* 0x0068 */ - u16 mc_tx_address; /* 0x006a */ - u16 mc_tx_cmd; /* 0x006c */ - u16 mc_res; /* 0x006e */ - u16 mc_rx_cmd_status; /* 0x0070 */ - u16 mc_rx_data; /* 0x0072 */ - u16 reserved_5[69]; /* 0x0074 */ - u16 reflection_high; /* 0x00fe */ - struct ihs_osd osd0; /* 0x0100 */ - u16 reserved_6[889]; /* 0x010e */ - u16 videomem0[2048]; /* 0x0800 */ -}; -#endif - #if defined(CONFIG_TARGET_HRCON) || defined(CONFIG_STRIDER_CON_DP) struct ihs_fpga { u16 reflection_low; /* 0x0000 */ @@ -270,25 +195,4 @@ struct ihs_fpga { }; #endif -#ifdef CONFIG_DLVISION_10G -struct ihs_fpga { - u16 reflection_low; /* 0x0000 */ - u16 versions; /* 0x0002 */ - u16 fpga_version; /* 0x0004 */ - u16 fpga_features; /* 0x0006 */ - u16 reserved_0[10]; /* 0x0008 */ - u16 extended_interrupt; /* 0x001c */ - u16 reserved_1[29]; /* 0x001e */ - u16 mpc3w_control; /* 0x0058 */ - u16 reserved_2[3]; /* 0x005a */ - struct ihs_i2c i2c0; /* 0x0060 */ - u16 reserved_3[2]; /* 0x006c */ - struct ihs_i2c i2c1; /* 0x0070 */ - u16 reserved_4[194]; /* 0x007c */ - struct ihs_osd osd0; /* 0x0200 */ - u16 reserved_5[761]; /* 0x020e */ - u16 videomem0[2048]; /* 0x0800 */ -}; -#endif - #endif From 9c454827f1d1939032ea2b7811a8e674655d58fb Mon Sep 17 00:00:00 2001 From: Mario Six Date: Fri, 29 Mar 2019 10:18:06 +0100 Subject: [PATCH 73/86] gdsys: mpc8308: Fix style violations Fix some style violations in the gdsys MPC8308 board files, and make the code more readable. Signed-off-by: Mario Six --- board/gdsys/mpc8308/hrcon.c | 55 ++++++++++++++++++----------------- board/gdsys/mpc8308/mpc8308.c | 12 ++++---- board/gdsys/mpc8308/strider.c | 49 ++++++++++++++++--------------- 3 files changed, 59 insertions(+), 57 deletions(-) diff --git a/board/gdsys/mpc8308/hrcon.c b/board/gdsys/mpc8308/hrcon.c index 2d709dee94..79e3b25de8 100644 --- a/board/gdsys/mpc8308/hrcon.c +++ b/board/gdsys/mpc8308/hrcon.c @@ -35,11 +35,11 @@ #define MAX_MUX_CHANNELS 2 enum { - MCFPGA_DONE = 1 << 0, - MCFPGA_INIT_N = 1 << 1, - MCFPGA_PROGRAM_N = 1 << 2, - MCFPGA_UPDATE_ENABLE_N = 1 << 3, - MCFPGA_RESET_N = 1 << 4, + MCFPGA_DONE = BIT(0), + MCFPGA_INIT_N = BIT(1), + MCFPGA_PROGRAM_N = BIT(2), + MCFPGA_UPDATE_ENABLE_N = BIT(3), + MCFPGA_RESET_N = BIT(4), }; enum { @@ -47,7 +47,7 @@ enum { GPIO_MDIO = 1 << 15, }; -unsigned int mclink_fpgacount; +uint mclink_fpgacount; struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR; struct { @@ -107,7 +107,7 @@ int checkboard(void) printf("HRCon %s", hw_type_cat ? "CAT" : "Fiber"); - if (s != NULL) { + if (s) { puts(", serial# "); puts(s); } @@ -120,12 +120,11 @@ int checkboard(void) int last_stage_init(void) { int slaves; - unsigned int k; - unsigned int mux_ch; - unsigned char mclink_controllers[] = { 0x3c, 0x3d, 0x3e }; + uint k; + uchar mclink_controllers[] = { 0x3c, 0x3d, 0x3e }; u16 fpga_features; bool hw_type_cat = pca9698_get_value(0x20, 20); - bool ch0_rgmii2_present = false; + bool ch0_rgmii2_present; FPGA_GET_REG(0, fpga_features, &fpga_features); @@ -137,16 +136,16 @@ int last_stage_init(void) /* wait for FPGA done, then reset FPGA */ for (k = 0; k < ARRAY_SIZE(mclink_controllers); ++k) { - unsigned int ctr = 0; + uint ctr = 0; if (i2c_probe(mclink_controllers[k])) continue; while (!(pca953x_get_val(mclink_controllers[k]) & MCFPGA_DONE)) { - udelay(100000); + mdelay(100); if (ctr++ > 5) { - printf("no done for mclink_controller %d\n", k); + printf("no done for mclink_controller %u\n", k); break; } } @@ -159,8 +158,10 @@ int last_stage_init(void) } if (hw_type_cat) { + uint mux_ch; int retval; struct mii_dev *mdiodev = mdio_alloc(); + if (!mdiodev) return -ENOMEM; strncpy(mdiodev->name, bb_miiphy_buses[0].name, MDIO_NAME_LEN); @@ -179,7 +180,7 @@ int last_stage_init(void) } /* give slave-PLLs and Parade DP501 some time to be up and running */ - udelay(500000); + mdelay(500); mclink_fpgacount = CONFIG_SYS_MCLINK_MAX; slaves = mclink_probe(); @@ -207,6 +208,7 @@ int last_stage_init(void) if (hw_type_cat) { int retval; struct mii_dev *mdiodev = mdio_alloc(); + if (!mdiodev) return -ENOMEM; strncpy(mdiodev->name, bb_miiphy_buses[k].name, @@ -233,17 +235,17 @@ int last_stage_init(void) * provide access to fpga gpios and controls (for I2C bitbang) * (these may look all too simple but make iocon.h much more readable) */ -void fpga_gpio_set(unsigned int bus, int pin) +void fpga_gpio_set(uint bus, int pin) { FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, gpio.set, pin); } -void fpga_gpio_clear(unsigned int bus, int pin) +void fpga_gpio_clear(uint bus, int pin) { FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, gpio.clear, pin); } -int fpga_gpio_get(unsigned int bus, int pin) +int fpga_gpio_get(uint bus, int pin) { u16 val; @@ -252,7 +254,7 @@ int fpga_gpio_get(unsigned int bus, int pin) return val & pin; } -void fpga_control_set(unsigned int bus, int pin) +void fpga_control_set(uint bus, int pin) { u16 val; @@ -260,7 +262,7 @@ void fpga_control_set(unsigned int bus, int pin) FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, control, val | pin); } -void fpga_control_clear(unsigned int bus, int pin) +void fpga_control_clear(uint bus, int pin) { u16 val; @@ -273,7 +275,7 @@ void mpc8308_init(void) pca9698_direction_output(0x20, 4, 1); } -void mpc8308_set_fpga_reset(unsigned state) +void mpc8308_set_fpga_reset(uint state) { pca9698_set_value(0x20, 4, state ? 0 : 1); } @@ -285,11 +287,11 @@ void mpc8308_setup_hw(void) /* * set "startup-finished"-gpios */ - setbits_be32(&immr->gpio[0].dir, (1 << (31-11)) | (1 << (31-12))); - setbits_be32(&immr->gpio[0].dat, 1 << (31-12)); + setbits_be32(&immr->gpio[0].dir, (BIT(31 - 11) | BIT(31 - 12))); + setbits_be32(&immr->gpio[0].dat, BIT(31 - 12)); } -int mpc8308_get_fpga_done(unsigned fpga) +int mpc8308_get_fpga_done(uint fpga) { return pca9698_get_value(0x20, 19); } @@ -367,7 +369,7 @@ int ft_board_setup(void *blob, bd_t *bd) */ struct fpga_mii { - unsigned fpga; + uint fpga; int mdio; } fpga_mii[] = { { 0, 1}, @@ -494,5 +496,4 @@ struct bb_miiphy_bus bb_miiphy_buses[] = { }, }; -int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) / - sizeof(bb_miiphy_buses[0]); +int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses); diff --git a/board/gdsys/mpc8308/mpc8308.c b/board/gdsys/mpc8308/mpc8308.c index 0112244fc7..9fe1d66c60 100644 --- a/board/gdsys/mpc8308/mpc8308.c +++ b/board/gdsys/mpc8308/mpc8308.c @@ -24,14 +24,14 @@ DECLARE_GLOBAL_DATA_PTR; -int get_fpga_state(unsigned dev) +int get_fpga_state(uint dev) { return gd->arch.fpga_state[dev]; } int board_early_init_f(void) { - unsigned k; + uint k; for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) gd->arch.fpga_state[k] = 0; @@ -41,8 +41,8 @@ int board_early_init_f(void) int board_early_init_r(void) { - unsigned k; - unsigned ctr; + uint k; + uint ctr; for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) gd->arch.fpga_state[k] = 0; @@ -59,7 +59,7 @@ int board_early_init_r(void) for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) { ctr = 0; while (!mpc8308_get_fpga_done(k)) { - udelay(100000); + mdelay(100); if (ctr++ > 5) { gd->arch.fpga_state[k] |= FPGA_STATE_DONE_FAILED; @@ -86,7 +86,7 @@ int board_early_init_r(void) if (val == REFLECTION_TESTPATTERN_INV) break; - udelay(100000); + mdelay(100); if (ctr++ > 5) { gd->arch.fpga_state[k] |= FPGA_STATE_REFLECTION_FAILED; diff --git a/board/gdsys/mpc8308/strider.c b/board/gdsys/mpc8308/strider.c index fa26585296..b1997f453a 100644 --- a/board/gdsys/mpc8308/strider.c +++ b/board/gdsys/mpc8308/strider.c @@ -50,7 +50,7 @@ enum { GPIO_MDIO = 1 << 15, }; -unsigned int mclink_fpgacount; +uint mclink_fpgacount; struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR; struct { @@ -110,7 +110,7 @@ int checkboard(void) printf("Strider %s", hw_type_cat ? "CAT" : "Fiber"); - if (s != NULL) { + if (s) { puts(", serial# "); puts(s); } @@ -123,17 +123,17 @@ int checkboard(void) int last_stage_init(void) { int slaves; - unsigned int k; - unsigned int mux_ch; - unsigned char mclink_controllers_dvi[] = { 0x3c, 0x3d, 0x3e }; + uint k; + uint mux_ch; + uchar mclink_controllers_dvi[] = { 0x3c, 0x3d, 0x3e }; #ifdef CONFIG_STRIDER_CPU - unsigned char mclink_controllers_dp[] = { 0x24, 0x25, 0x26 }; + uchar mclink_controllers_dp[] = { 0x24, 0x25, 0x26 }; #endif bool hw_type_cat = pca9698_get_value(0x20, 18); #ifdef CONFIG_STRIDER_CON_DP bool is_dh = pca9698_get_value(0x20, 25); #endif - bool ch0_sgmii2_present = false; + bool ch0_sgmii2_present; /* Turn on Analog Devices ADV7611 */ pca9698_direction_output(0x20, 8, 0); @@ -146,8 +146,8 @@ int last_stage_init(void) /* wait for FPGA done, then reset FPGA */ for (k = 0; k < ARRAY_SIZE(mclink_controllers_dvi); ++k) { - unsigned int ctr = 0; - unsigned char *mclink_controllers = mclink_controllers_dvi; + uint ctr = 0; + uchar *mclink_controllers = mclink_controllers_dvi; #ifdef CONFIG_STRIDER_CPU if (i2c_probe(mclink_controllers[k])) { @@ -161,7 +161,7 @@ int last_stage_init(void) #endif while (!(pca953x_get_val(mclink_controllers[k]) & MCFPGA_DONE)) { - udelay(100000); + mdelay(100); if (ctr++ > 5) { printf("no done for mclink_controller %d\n", k); break; @@ -178,6 +178,7 @@ int last_stage_init(void) if (hw_type_cat) { int retval; struct mii_dev *mdiodev = mdio_alloc(); + if (!mdiodev) return -ENOMEM; strncpy(mdiodev->name, bb_miiphy_buses[0].name, MDIO_NAME_LEN); @@ -196,7 +197,7 @@ int last_stage_init(void) } /* give slave-PLLs and Parade DP501 some time to be up and running */ - udelay(500000); + mdelay(500); mclink_fpgacount = CONFIG_SYS_MCLINK_MAX; slaves = mclink_probe(); @@ -235,7 +236,7 @@ int last_stage_init(void) for (k = 1; k <= slaves; ++k) FPGA_SET_REG(k, extended_control, 0x10); /* enable video */ - udelay(500000); + mdelay(500); #endif for (k = 1; k <= slaves; ++k) { @@ -260,6 +261,7 @@ int last_stage_init(void) if (hw_type_cat) { int retval; struct mii_dev *mdiodev = mdio_alloc(); + if (!mdiodev) return -ENOMEM; strncpy(mdiodev->name, bb_miiphy_buses[k].name, @@ -286,17 +288,17 @@ int last_stage_init(void) * provide access to fpga gpios (for I2C bitbang) * (these may look all too simple but make iocon.h much more readable) */ -void fpga_gpio_set(unsigned int bus, int pin) +void fpga_gpio_set(uint bus, int pin) { FPGA_SET_REG(bus, gpio.set, pin); } -void fpga_gpio_clear(unsigned int bus, int pin) +void fpga_gpio_clear(uint bus, int pin) { FPGA_SET_REG(bus, gpio.clear, pin); } -int fpga_gpio_get(unsigned int bus, int pin) +int fpga_gpio_get(uint bus, int pin) { u16 val; @@ -306,7 +308,7 @@ int fpga_gpio_get(unsigned int bus, int pin) } #ifdef CONFIG_STRIDER_CON_DP -void fpga_control_set(unsigned int bus, int pin) +void fpga_control_set(uint bus, int pin) { u16 val; @@ -314,7 +316,7 @@ void fpga_control_set(unsigned int bus, int pin) FPGA_SET_REG(bus, control, val | pin); } -void fpga_control_clear(unsigned int bus, int pin) +void fpga_control_clear(uint bus, int pin) { u16 val; @@ -328,7 +330,7 @@ void mpc8308_init(void) pca9698_direction_output(0x20, 26, 1); } -void mpc8308_set_fpga_reset(unsigned state) +void mpc8308_set_fpga_reset(uint state) { pca9698_set_value(0x20, 26, state ? 0 : 1); } @@ -340,11 +342,11 @@ void mpc8308_setup_hw(void) /* * set "startup-finished"-gpios */ - setbits_be32(&immr->gpio[0].dir, (1 << (31-11)) | (1 << (31-12))); - setbits_be32(&immr->gpio[0].dat, 1 << (31-12)); + setbits_be32(&immr->gpio[0].dir, BIT(31 - 11) | BIT(31 - 12)); + setbits_be32(&immr->gpio[0].dat, BIT(31 - 12)); } -int mpc8308_get_fpga_done(unsigned fpga) +int mpc8308_get_fpga_done(uint fpga) { return pca9698_get_value(0x20, 20); } @@ -422,7 +424,7 @@ int ft_board_setup(void *blob, bd_t *bd) */ struct fpga_mii { - unsigned fpga; + uint fpga; int mdio; } fpga_mii[] = { { 0, 1}, @@ -549,5 +551,4 @@ struct bb_miiphy_bus bb_miiphy_buses[] = { }, }; -int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) / - sizeof(bb_miiphy_buses[0]); +int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses); From b12b545836746217e9f417bd5c3b13557a201a34 Mon Sep 17 00:00:00 2001 From: Mario Six Date: Fri, 29 Mar 2019 10:18:07 +0100 Subject: [PATCH 74/86] gdsys: mpc8308: Use shadow register for output GPIO values Since the gpio output status on MPC8xxx cannot be read back, it has to be buffered locally. Signed-off-by: Dirk Eibach Signed-off-by: Mario Six --- board/gdsys/mpc8308/hrcon.c | 4 ++-- board/gdsys/mpc8308/mpc8308.c | 19 +++++++++++++++++++ board/gdsys/mpc8308/mpc8308.h | 3 +++ board/gdsys/mpc8308/strider.c | 2 +- 4 files changed, 25 insertions(+), 3 deletions(-) diff --git a/board/gdsys/mpc8308/hrcon.c b/board/gdsys/mpc8308/hrcon.c index 79e3b25de8..d14a28ec94 100644 --- a/board/gdsys/mpc8308/hrcon.c +++ b/board/gdsys/mpc8308/hrcon.c @@ -287,8 +287,8 @@ void mpc8308_setup_hw(void) /* * set "startup-finished"-gpios */ - setbits_be32(&immr->gpio[0].dir, (BIT(31 - 11) | BIT(31 - 12))); - setbits_be32(&immr->gpio[0].dat, BIT(31 - 12)); + setbits_be32(&immr->gpio[0].dir, BIT(31 - 11) | BIT(31 - 12)); + setbits_gpio0_out(BIT(31 - 12)); } int mpc8308_get_fpga_done(uint fpga) diff --git a/board/gdsys/mpc8308/mpc8308.c b/board/gdsys/mpc8308/mpc8308.c index 9fe1d66c60..a53135b8fd 100644 --- a/board/gdsys/mpc8308/mpc8308.c +++ b/board/gdsys/mpc8308/mpc8308.c @@ -24,6 +24,25 @@ DECLARE_GLOBAL_DATA_PTR; +/* as gpio output status cannot be read back, we have to buffer it locally */ +u32 gpio0_out; + +void setbits_gpio0_out(u32 mask) +{ + immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; + + gpio0_out |= mask; + out_be32(&immr->gpio[0].dat, gpio0_out); +} + +void clrbits_gpio0_out(u32 mask) +{ + immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; + + gpio0_out &= ~mask; + out_be32(&immr->gpio[0].dat, gpio0_out); +} + int get_fpga_state(uint dev) { return gd->arch.fpga_state[dev]; diff --git a/board/gdsys/mpc8308/mpc8308.h b/board/gdsys/mpc8308/mpc8308.h index dc07d564eb..1e4f24fb2a 100644 --- a/board/gdsys/mpc8308/mpc8308.h +++ b/board/gdsys/mpc8308/mpc8308.h @@ -1,6 +1,9 @@ #ifndef __MPC8308_H_ #define __MPC8308_H_ +void setbits_gpio0_out(u32 mask); +void clrbits_gpio0_out(u32 mask); + /* functions to be provided by board implementation */ void mpc8308_init(void); void mpc8308_set_fpga_reset(unsigned state); diff --git a/board/gdsys/mpc8308/strider.c b/board/gdsys/mpc8308/strider.c index b1997f453a..1fdea675bd 100644 --- a/board/gdsys/mpc8308/strider.c +++ b/board/gdsys/mpc8308/strider.c @@ -343,7 +343,7 @@ void mpc8308_setup_hw(void) * set "startup-finished"-gpios */ setbits_be32(&immr->gpio[0].dir, BIT(31 - 11) | BIT(31 - 12)); - setbits_be32(&immr->gpio[0].dat, BIT(31 - 12)); + setbits_gpio0_out(BIT(31 - 12)); } int mpc8308_get_fpga_done(uint fpga) From b335fb6d8c7796edce58db5c4743e6de891ec1fe Mon Sep 17 00:00:00 2001 From: Mario Six Date: Fri, 29 Mar 2019 10:18:08 +0100 Subject: [PATCH 75/86] gdsys: mpc8308: Migrate SYS_FPGA{0, 1}_{BASE, SIZE} to Kconfig Move CONFIG_SYS_FPGA0_BASE, CONFIG_SYS_FPGA0_SIZE, CONFIG_SYS_FPGA1_BASE, and CONFIG_SYS_FPGA1_SIZE to Kconfig. Signed-off-by: Mario Six --- board/gdsys/mpc8308/Kconfig | 22 ++++++++++++++++++++++ include/configs/hrcon.h | 8 -------- include/configs/strider.h | 8 -------- 3 files changed, 22 insertions(+), 16 deletions(-) diff --git a/board/gdsys/mpc8308/Kconfig b/board/gdsys/mpc8308/Kconfig index 9d99f68692..cad458ac71 100644 --- a/board/gdsys/mpc8308/Kconfig +++ b/board/gdsys/mpc8308/Kconfig @@ -4,6 +4,28 @@ config GDSYS_LEGACY_OSD_CMDS Use the 'osdw', 'osdp', and 'osdsize' legacy commands required by gdsys devices. +config SYS_FPGA0_BASE + hex + default E0600000 + help + The base address of the first FPGA's register map. + +config SYS_FPGA0_SIZE + hex + default 1 + help + The base address of the first FPGA's register map. + +config SYS_FPGA1_BASE + hex + help + The base address of the second FPGA's register map. + +config SYS_FPGA1_SIZE + hex + help + The base address of the second FPGA's register map. + if TARGET_HRCON config SYS_BOARD diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h index 8029ae9dd7..6e6c1714ce 100644 --- a/include/configs/hrcon.h +++ b/include/configs/hrcon.h @@ -129,14 +129,6 @@ #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ -/* - * FPGA - */ -#define CONFIG_SYS_FPGA0_BASE 0xE0600000 -#define CONFIG_SYS_FPGA0_SIZE 1 /* FPGA size is 1M */ - - -#define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE #define CONFIG_SYS_FPGA_DONE(k) 0x0010 #define CONFIG_SYS_FPGA_COUNT 1 diff --git a/include/configs/strider.h b/include/configs/strider.h index 22d255aabb..8b942e3446 100644 --- a/include/configs/strider.h +++ b/include/configs/strider.h @@ -127,14 +127,6 @@ #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ -/* - * FPGA - */ -#define CONFIG_SYS_FPGA0_BASE 0xE0600000 -#define CONFIG_SYS_FPGA0_SIZE 1 /* FPGA size is 1M */ - - -#define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE #define CONFIG_SYS_FPGA_DONE(k) 0x0010 #define CONFIG_SYS_FPGA_COUNT 1 From edba2b29f57efdff0ee087a0686ef11efbd6f9b8 Mon Sep 17 00:00:00 2001 From: Mario Six Date: Fri, 29 Mar 2019 10:18:09 +0100 Subject: [PATCH 76/86] gdsys: mpc8308: Don't use manual RAM config if RAM driver is active The "manual" RAM configuration should not be used if the DM RAM driver is active, hence, disable the code if the CONFIG_MPC83XX_SDRAM config variable is defined. Signed-off-by: Mario Six --- board/gdsys/mpc8308/sdram.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/board/gdsys/mpc8308/sdram.c b/board/gdsys/mpc8308/sdram.c index 3eb0e37b7b..2a77fed270 100644 --- a/board/gdsys/mpc8308/sdram.c +++ b/board/gdsys/mpc8308/sdram.c @@ -11,6 +11,8 @@ * board\freescale\mpc8315erdb\sdram.c */ +#ifndef CONFIG_MPC83XX_SDRAM + #include #include #include @@ -81,3 +83,5 @@ int dram_init(void) return 0; } + +#endif /* !CONFIG_MPC83XX_SDRAM */ From fe4a9675758e8fe7dce0b0064cac03c81a649f0a Mon Sep 17 00:00:00 2001 From: Mario Six Date: Fri, 29 Mar 2019 10:18:10 +0100 Subject: [PATCH 77/86] gdsys: Introduce GDSYS_LEGACY_DRIVERS Future gdsys boards will switch from the legacy drivers in board/gdsys/common to DM-based drivers. Define a Kconfig option that disables the legacy drivers. Signed-off-by: Mario Six --- board/gdsys/common/adv7611.c | 4 ++++ board/gdsys/common/ch7301.c | 4 ++++ board/gdsys/common/dp501.c | 4 ++++ board/gdsys/common/fanctrl.c | 4 ++++ board/gdsys/common/fpga.c | 4 ++++ board/gdsys/common/ioep-fpga.c | 4 ++++ board/gdsys/common/mclink.c | 4 ++++ board/gdsys/common/osd.c | 4 ++++ board/gdsys/mpc8308/Kconfig | 14 ++++++++++++++ board/gdsys/mpc8308/mpc8308.c | 2 ++ board/gdsys/p1022/Kconfig | 10 ++++++++++ include/gdsys_fpga.h | 2 ++ 12 files changed, 60 insertions(+) diff --git a/board/gdsys/common/adv7611.c b/board/gdsys/common/adv7611.c index c416bf1dc4..06cdc05825 100644 --- a/board/gdsys/common/adv7611.c +++ b/board/gdsys/common/adv7611.c @@ -4,6 +4,8 @@ * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc */ +#ifdef CONFIG_GDSYS_LEGACY_DRIVERS + #include #include @@ -174,3 +176,5 @@ out: return res; } + +#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */ diff --git a/board/gdsys/common/ch7301.c b/board/gdsys/common/ch7301.c index 1234149f42..5e42467651 100644 --- a/board/gdsys/common/ch7301.c +++ b/board/gdsys/common/ch7301.c @@ -6,6 +6,8 @@ /* Chrontel CH7301C DVI Transmitter */ +#ifdef CONFIG_GDSYS_LEGACY_DRIVERS + #include #include #include @@ -61,3 +63,5 @@ int ch7301_probe(unsigned screen, bool power) return 0; } + +#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */ diff --git a/board/gdsys/common/dp501.c b/board/gdsys/common/dp501.c index 69d4b8c333..9ca69ebcbb 100644 --- a/board/gdsys/common/dp501.c +++ b/board/gdsys/common/dp501.c @@ -6,6 +6,8 @@ /* Parade Technologies Inc. DP501 DisplayPort DVI/HDMI Transmitter */ +#ifdef CONFIG_GDSYS_LEGACY_DRIVERS + #include #include #include @@ -155,3 +157,5 @@ int dp501_probe(unsigned screen, bool power) return 0; } + +#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */ diff --git a/board/gdsys/common/fanctrl.c b/board/gdsys/common/fanctrl.c index 5e776831db..27c875cbec 100644 --- a/board/gdsys/common/fanctrl.c +++ b/board/gdsys/common/fanctrl.c @@ -4,6 +4,8 @@ * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc */ +#ifdef CONFIG_GDSYS_LEGACY_DRIVERS + #include #include @@ -29,3 +31,5 @@ void init_fan_controller(u8 addr) val = i2c_reg_read(addr, FAN_CONFIG) | 0x04; i2c_reg_write(addr, FAN_CONFIG, val); } + +#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */ diff --git a/board/gdsys/common/fpga.c b/board/gdsys/common/fpga.c index f189e5fbd1..5ba6613ed5 100644 --- a/board/gdsys/common/fpga.c +++ b/board/gdsys/common/fpga.c @@ -4,6 +4,8 @@ * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc */ +#ifdef CONFIG_GDSYS_LEGACY_DRIVERS + #include #include @@ -22,3 +24,5 @@ int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data) return 0; } + +#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */ diff --git a/board/gdsys/common/ioep-fpga.c b/board/gdsys/common/ioep-fpga.c index 8e10501247..91eec3ac7c 100644 --- a/board/gdsys/common/ioep-fpga.c +++ b/board/gdsys/common/ioep-fpga.c @@ -4,6 +4,8 @@ * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc */ +#ifdef CONFIG_GDSYS_LEGACY_DRIVERS + #include #include @@ -234,3 +236,5 @@ void ioep_fpga_print_info(unsigned int fpga) printf(", %d video channel(s)\n", feature_video_channels); } + +#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */ diff --git a/board/gdsys/common/mclink.c b/board/gdsys/common/mclink.c index bf89d4e292..c43d24b26d 100644 --- a/board/gdsys/common/mclink.c +++ b/board/gdsys/common/mclink.c @@ -4,6 +4,8 @@ * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc */ +#ifdef CONFIG_GDSYS_LEGACY_DRIVERS + #include #include #include @@ -134,3 +136,5 @@ int mclink_receive(u8 slave, u16 addr, u16 *data) return 0; } + +#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */ diff --git a/board/gdsys/common/osd.c b/board/gdsys/common/osd.c index 392d0059da..10c4329146 100644 --- a/board/gdsys/common/osd.c +++ b/board/gdsys/common/osd.c @@ -4,6 +4,8 @@ * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc */ +#ifdef CONFIG_GDSYS_LEGACY_DRIVERS + #include #include #include @@ -497,3 +499,5 @@ U_BOOT_CMD( "size_x(max. " __stringify(MAX_X_CHARS) ") size_y(max. " __stringify(MAX_Y_CHARS) ")\n" ); + +#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */ \ No newline at end of file diff --git a/board/gdsys/mpc8308/Kconfig b/board/gdsys/mpc8308/Kconfig index cad458ac71..222ab0d20a 100644 --- a/board/gdsys/mpc8308/Kconfig +++ b/board/gdsys/mpc8308/Kconfig @@ -4,6 +4,13 @@ config GDSYS_LEGACY_OSD_CMDS Use the 'osdw', 'osdp', and 'osdsize' legacy commands required by gdsys devices. +config GDSYS_LEGACY_DRIVERS + bool + help + Enable the gdsys legacy drivers under board/gdsys/common. If this + option is not set, all relevant DM drivers must be configured for the + device in question. + config SYS_FPGA0_BASE hex default E0600000 @@ -40,6 +47,9 @@ config SYS_CONFIG_NAME config GDSYS_LEGACY_OSD_CMDS default y +config GDSYS_LEGACY_DRIVERS + default y + endif if TARGET_STRIDER @@ -55,6 +65,10 @@ config SYS_CONFIG_NAME config GDSYS_LEGACY_OSD_CMDS default y + +config GDSYS_LEGACY_DRIVERS + default y + endif config CMD_IOLOOP diff --git a/board/gdsys/mpc8308/mpc8308.c b/board/gdsys/mpc8308/mpc8308.c index a53135b8fd..ae77fc2fd1 100644 --- a/board/gdsys/mpc8308/mpc8308.c +++ b/board/gdsys/mpc8308/mpc8308.c @@ -24,6 +24,7 @@ DECLARE_GLOBAL_DATA_PTR; +#ifdef CONFIG_GDSYS_LEGACY_DRIVERS /* as gpio output status cannot be read back, we have to buffer it locally */ u32 gpio0_out; @@ -116,3 +117,4 @@ int board_early_init_r(void) return 0; } +#endif diff --git a/board/gdsys/p1022/Kconfig b/board/gdsys/p1022/Kconfig index 8514d086b9..f5154271d1 100644 --- a/board/gdsys/p1022/Kconfig +++ b/board/gdsys/p1022/Kconfig @@ -1,3 +1,10 @@ +config GDSYS_LEGACY_DRIVERS + bool + help + Enable the gdsys legacy drivers under board/gdsys/common. If this + option is not set, all relevant DM drivers must be configured for the + device in question. + if TARGET_CONTROLCENTERD config SYS_BOARD @@ -9,4 +16,7 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "controlcenterd" +config GDSYS_LEGACY_DRIVERS + default y + endif diff --git a/include/gdsys_fpga.h b/include/gdsys_fpga.h index eae6701262..6d38a83d90 100644 --- a/include/gdsys_fpga.h +++ b/include/gdsys_fpga.h @@ -7,6 +7,7 @@ #ifndef __GDSYS_FPGA_H #define __GDSYS_FPGA_H +#ifdef CONFIG_GDSYS_LEGACY_DRIVERS int init_func_fpga(void); enum { @@ -33,6 +34,7 @@ extern struct ihs_fpga *fpga_ptr[]; &fpga_ptr[ix]->fld, \ offsetof(struct ihs_fpga, fld), \ val) +#endif struct ihs_gpio { u16 read; From cda8e1f6ca514effb229cad74719fa7b5bf8cd7b Mon Sep 17 00:00:00 2001 From: Mario Six Date: Fri, 29 Mar 2019 10:18:11 +0100 Subject: [PATCH 78/86] gdsys: mpc8308: Add FPGA flavor option More recent versions of IHS FPGAs feature a different memory layout. Add a Kconfig option to differentiate between the legacy layout, and the new layout (which is used on the upcoming "Gazerbeam" and later boards). Signed-off-by: Mario Six --- board/gdsys/mpc8308/Kconfig | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/board/gdsys/mpc8308/Kconfig b/board/gdsys/mpc8308/Kconfig index 222ab0d20a..e6a4796054 100644 --- a/board/gdsys/mpc8308/Kconfig +++ b/board/gdsys/mpc8308/Kconfig @@ -71,7 +71,27 @@ config GDSYS_LEGACY_DRIVERS endif +if TARGET_HRCON || TARGET_STRIDER + +choice + prompt "FPGA flavor selection" + +config SYS_FPGA_FLAVOR_LEGACY + bool "Legacy flavor" + help + This enables support for the gdsys pre-Gazerbeam FPGA memory layout. + +config SYS_FPGA_FLAVOR_GAZERBEAM + bool "Gazerbeam flavor" + help + This enables support for the gdsys FPGA memory layout of the + Gazerbeam board. + +endchoice + config CMD_IOLOOP bool "Enable 'ioloop' and 'ioreflect' commands" help These commands provide FPGA tests. + +endif From db1d03a299811267bcd0f38fe9cd0f833ab29cd9 Mon Sep 17 00:00:00 2001 From: Mario Six Date: Fri, 29 Mar 2019 10:18:12 +0100 Subject: [PATCH 79/86] gdsys: cmd_ioloop: Fix style violations Fix some style violations in the ioloop command, and make the code more readable where possible. Signed-off-by: Mario Six --- board/gdsys/common/cmd_ioloop.c | 78 ++++++++++++++++----------------- 1 file changed, 38 insertions(+), 40 deletions(-) diff --git a/board/gdsys/common/cmd_ioloop.c b/board/gdsys/common/cmd_ioloop.c index 8e2f4071ef..a53c80c0ad 100644 --- a/board/gdsys/common/cmd_ioloop.c +++ b/board/gdsys/common/cmd_ioloop.c @@ -11,33 +11,33 @@ #include enum { - STATE_TX_PACKET_BUILDING = 1<<0, - STATE_TX_TRANSMITTING = 1<<1, - STATE_TX_BUFFER_FULL = 1<<2, - STATE_TX_ERR = 1<<3, - STATE_RECEIVE_TIMEOUT = 1<<4, - STATE_PROC_RX_STORE_TIMEOUT = 1<<5, - STATE_PROC_RX_RECEIVE_TIMEOUT = 1<<6, - STATE_RX_DIST_ERR = 1<<7, - STATE_RX_LENGTH_ERR = 1<<8, - STATE_RX_FRAME_CTR_ERR = 1<<9, - STATE_RX_FCS_ERR = 1<<10, - STATE_RX_PACKET_DROPPED = 1<<11, - STATE_RX_DATA_LAST = 1<<12, - STATE_RX_DATA_FIRST = 1<<13, - STATE_RX_DATA_AVAILABLE = 1<<15, + STATE_TX_PACKET_BUILDING = BIT(0), + STATE_TX_TRANSMITTING = BIT(1), + STATE_TX_BUFFER_FULL = BIT(2), + STATE_TX_ERR = BIT(3), + STATE_RECEIVE_TIMEOUT = BIT(4), + STATE_PROC_RX_STORE_TIMEOUT = BIT(5), + STATE_PROC_RX_RECEIVE_TIMEOUT = BIT(6), + STATE_RX_DIST_ERR = BIT(7), + STATE_RX_LENGTH_ERR = BIT(8), + STATE_RX_FRAME_CTR_ERR = BIT(9), + STATE_RX_FCS_ERR = BIT(10), + STATE_RX_PACKET_DROPPED = BIT(11), + STATE_RX_DATA_LAST = BIT(12), + STATE_RX_DATA_FIRST = BIT(13), + STATE_RX_DATA_AVAILABLE = BIT(15), }; enum { - CTRL_PROC_RECEIVE_ENABLE = 1<<12, - CTRL_FLUSH_TRANSMIT_BUFFER = 1<<15, + CTRL_PROC_RECEIVE_ENABLE = BIT(12), + CTRL_FLUSH_TRANSMIT_BUFFER = BIT(15), }; enum { - IRQ_CPU_TRANSMITBUFFER_FREE_STATUS = 1<<5, - IRQ_CPU_PACKET_TRANSMITTED_EVENT = 1<<6, - IRQ_NEW_CPU_PACKET_RECEIVED_EVENT = 1<<7, - IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS = 1<<8, + IRQ_CPU_TRANSMITBUFFER_FREE_STATUS = BIT(5), + IRQ_CPU_PACKET_TRANSMITTED_EVENT = BIT(6), + IRQ_NEW_CPU_PACKET_RECEIVED_EVENT = BIT(7), + IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS = BIT(8), }; struct io_generic_packet { @@ -52,7 +52,7 @@ unsigned long long rx_ctr; unsigned long long tx_ctr; unsigned long long err_ctr; -static void io_check_status(unsigned int fpga, u16 status, bool silent) +static void io_check_status(uint fpga, u16 status, bool silent) { u16 mask = STATE_RX_DIST_ERR | STATE_RX_LENGTH_ERR | STATE_RX_FRAME_CTR_ERR | STATE_RX_FCS_ERR | @@ -85,9 +85,9 @@ static void io_check_status(unsigned int fpga, u16 status, bool silent) printf("TX_ERR\n"); } -static void io_send(unsigned int fpga, unsigned int size) +static void io_send(uint fpga, uint size) { - unsigned int k; + uint k; struct io_generic_packet packet = { .source_address = 1, .packet_type = 1, @@ -107,9 +107,8 @@ static void io_send(unsigned int fpga, unsigned int size) tx_ctr++; } -static void io_receive(unsigned int fpga) +static void io_receive(uint fpga) { - unsigned int k = 0; u16 rx_tx_status; FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status); @@ -123,17 +122,15 @@ static void io_receive(unsigned int fpga) FPGA_GET_REG(fpga, ep.receive_data, &rx); FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status); - - ++k; } } -static void io_reflect(unsigned int fpga) +static void io_reflect(uint fpga) { u16 buffer[128]; - unsigned int k = 0; - unsigned int n; + uint k = 0; + uint n; u16 rx_tx_status; FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status); @@ -166,8 +163,8 @@ static void io_reflect(unsigned int fpga) */ int do_ioreflect(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - unsigned int fpga; - unsigned int rate = 0; + uint fpga; + uint rate = 0; unsigned long long last_seen = 0; if (argc < 2) @@ -181,10 +178,10 @@ int do_ioreflect(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) if (argc > 2) rate = simple_strtoul(argv[2], NULL, 10); - /* enable receive path */ + /* Enable receive path */ FPGA_SET_REG(fpga, ep.rx_tx_control, CTRL_PROC_RECEIVE_ENABLE); - /* set device address to dummy 1*/ + /* Set device address to dummy 1*/ FPGA_SET_REG(fpga, ep.device_address, 1); rx_ctr = 0; tx_ctr = 0; err_ctr = 0; @@ -215,18 +212,19 @@ int do_ioreflect(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 0; } +#define DISP_LINE_LEN 16 + /* * FPGA io-endpoint looptest * * Syntax: * ioloop {fpga} {size} {rate} */ -#define DISP_LINE_LEN 16 int do_ioloop(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - unsigned int fpga; - unsigned int size; - unsigned int rate = 0; + uint fpga; + uint size; + uint rate = 0; if (argc < 3) return CMD_RET_USAGE; @@ -273,7 +271,7 @@ int do_ioloop(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) break; udelay(1000000 / rate); if (!(tx_ctr % rate)) - printf("d %lld, tx %llu, rx %llu, err %llu\n", + printf("d %llu, tx %llu, rx %llu, err %llu\n", tx_ctr - rx_ctr, tx_ctr, rx_ctr, err_ctr); } From ba75772fcbf32194db81c1907898657f84aa5182 Mon Sep 17 00:00:00 2001 From: Mario Six Date: Fri, 29 Mar 2019 10:18:13 +0100 Subject: [PATCH 80/86] gdsys: cmd_ioloop: Introduce commenting enum Replace the boolean parameter of io_check_status that controls whether the status is printed or not with a documenting enum. Signed-off-by: Mario Six --- board/gdsys/common/cmd_ioloop.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/board/gdsys/common/cmd_ioloop.c b/board/gdsys/common/cmd_ioloop.c index a53c80c0ad..8f70c1eda2 100644 --- a/board/gdsys/common/cmd_ioloop.c +++ b/board/gdsys/common/cmd_ioloop.c @@ -10,6 +10,11 @@ #include +enum status_print_type { + STATUS_LOUD = 0, + STATUS_SILENT = 1, +}; + enum { STATE_TX_PACKET_BUILDING = BIT(0), STATE_TX_TRANSMITTING = BIT(1), @@ -52,7 +57,7 @@ unsigned long long rx_ctr; unsigned long long tx_ctr; unsigned long long err_ctr; -static void io_check_status(uint fpga, u16 status, bool silent) +static void io_check_status(uint fpga, u16 status, enum status_print_type type) { u16 mask = STATE_RX_DIST_ERR | STATE_RX_LENGTH_ERR | STATE_RX_FRAME_CTR_ERR | STATE_RX_FCS_ERR | @@ -66,7 +71,7 @@ static void io_check_status(uint fpga, u16 status, bool silent) err_ctr++; FPGA_SET_REG(fpga, ep.rx_tx_status, status); - if (silent) + if (type == STATUS_SILENT) return; if (status & STATE_RX_PACKET_DROPPED) @@ -193,7 +198,7 @@ int do_ioreflect(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) FPGA_GET_REG(fpga, top_interrupt, &top_int); FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status); - io_check_status(fpga, rx_tx_status, true); + io_check_status(fpga, rx_tx_status, STATUS_SILENT); if ((top_int & IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS) && (top_int & IRQ_CPU_TRANSMITBUFFER_FREE_STATUS)) io_reflect(fpga); @@ -260,7 +265,7 @@ int do_ioloop(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) FPGA_GET_REG(fpga, top_interrupt, &top_int); FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status); - io_check_status(fpga, rx_tx_status, false); + io_check_status(fpga, rx_tx_status, STATUS_LOUD); if (top_int & IRQ_CPU_TRANSMITBUFFER_FREE_STATUS) io_send(fpga, size); if (top_int & IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS) From df8e5fb343c27c58cfe90def4dd4928a7de36d69 Mon Sep 17 00:00:00 2001 From: Mario Six Date: Fri, 29 Mar 2019 10:18:14 +0100 Subject: [PATCH 81/86] gdsys: cmd_ioloop: Make DM compatible Make the ioloop command DM compatible, while keeping the old functionality for not-yet-converted boards. Signed-off-by: Mario Six --- board/gdsys/common/cmd_ioloop.c | 293 +++++++++++++++++++++++++++++++- 1 file changed, 288 insertions(+), 5 deletions(-) diff --git a/board/gdsys/common/cmd_ioloop.c b/board/gdsys/common/cmd_ioloop.c index 8f70c1eda2..05a14ff103 100644 --- a/board/gdsys/common/cmd_ioloop.c +++ b/board/gdsys/common/cmd_ioloop.c @@ -10,11 +10,25 @@ #include +#ifndef CONFIG_GDSYS_LEGACY_DRIVERS +#include +#include +#include +#include + +#include "../../../drivers/misc/gdsys_soc.h" +#include "../../../drivers/misc/gdsys_ioep.h" +#include "../../../drivers/misc/ihs_fpga.h" + +const int HEADER_WORDS = sizeof(struct io_generic_packet) / 2; +#endif /* !CONFIG_GDSYS_LEGACY_DRIVERS */ + enum status_print_type { STATUS_LOUD = 0, STATUS_SILENT = 1, }; +#ifdef CONFIG_GDSYS_LEGACY_DRIVERS enum { STATE_TX_PACKET_BUILDING = BIT(0), STATE_TX_TRANSMITTING = BIT(1), @@ -33,11 +47,6 @@ enum { STATE_RX_DATA_AVAILABLE = BIT(15), }; -enum { - CTRL_PROC_RECEIVE_ENABLE = BIT(12), - CTRL_FLUSH_TRANSMIT_BUFFER = BIT(15), -}; - enum { IRQ_CPU_TRANSMITBUFFER_FREE_STATUS = BIT(5), IRQ_CPU_PACKET_TRANSMITTED_EVENT = BIT(6), @@ -45,6 +54,11 @@ enum { IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS = BIT(8), }; +enum { + CTRL_PROC_RECEIVE_ENABLE = BIT(12), + CTRL_FLUSH_TRANSMIT_BUFFER = BIT(15), +}; + struct io_generic_packet { u16 target_address; u16 source_address; @@ -52,11 +66,16 @@ struct io_generic_packet { u8 bc; u16 packet_length; } __attribute__((__packed__)); +#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */ unsigned long long rx_ctr; unsigned long long tx_ctr; unsigned long long err_ctr; +#ifndef CONFIG_GDSYS_LEGACY_DRIVERS +struct udevice *dev; +#endif /* !CONFIG_GDSYS_LEGACY_DRIVERS */ +#ifdef CONFIG_GDSYS_LEGACY_DRIVERS static void io_check_status(uint fpga, u16 status, enum status_print_type type) { u16 mask = STATE_RX_DIST_ERR | STATE_RX_LENGTH_ERR | @@ -89,7 +108,39 @@ static void io_check_status(uint fpga, u16 status, enum status_print_type type) if (status & STATE_TX_ERR) printf("TX_ERR\n"); } +#else +static void io_check_status(struct udevice *dev, enum status_print_type type) +{ + u16 status = 0; + int ret; + ret = misc_call(dev, 0, NULL, 0, &status, 0); + if (!ret) + return; + + err_ctr++; + + if (type != STATUS_LOUD) + return; + + if (status & STATE_RX_PACKET_DROPPED) + printf("RX_PACKET_DROPPED, status %04x\n", status); + + if (status & STATE_RX_DIST_ERR) + printf("RX_DIST_ERR\n"); + if (status & STATE_RX_LENGTH_ERR) + printf("RX_LENGTH_ERR\n"); + if (status & STATE_RX_FRAME_CTR_ERR) + printf("RX_FRAME_CTR_ERR\n"); + if (status & STATE_RX_FCS_ERR) + printf("RX_FCS_ERR\n"); + + if (status & STATE_TX_ERR) + printf("TX_ERR\n"); +} +#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */ + +#ifdef CONFIG_GDSYS_LEGACY_DRIVERS static void io_send(uint fpga, uint size) { uint k; @@ -111,7 +162,29 @@ static void io_send(uint fpga, uint size) tx_ctr++; } +#else +static void io_send(struct udevice *dev, uint size) +{ + uint k; + u16 buffer[HEADER_WORDS + 128]; + struct io_generic_packet header = { + .source_address = 1, + .packet_type = 1, + .packet_length = size, + }; + const uint words = (size + 1) / 2; + memcpy(buffer, &header, 2 * HEADER_WORDS); + for (k = 0; k < words; ++k) + buffer[k + HEADER_WORDS] = (2 * k + 1) + ((2 * k) << 8); + + misc_write(dev, 0, buffer, HEADER_WORDS + words); + + tx_ctr++; +} +#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */ + +#ifdef CONFIG_GDSYS_LEGACY_DRIVERS static void io_receive(uint fpga) { u16 rx_tx_status; @@ -129,7 +202,17 @@ static void io_receive(uint fpga) FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status); } } +#else +static void io_receive(struct udevice *dev) +{ + u16 buffer[HEADER_WORDS + 128]; + if (!misc_read(dev, 0, buffer, 0)) + rx_ctr++; +} +#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */ + +#ifdef CONFIG_GDSYS_LEGACY_DRIVERS static void io_reflect(uint fpga) { u16 buffer[128]; @@ -159,7 +242,22 @@ static void io_reflect(uint fpga) tx_ctr++; } +#else +static void io_reflect(struct udevice *dev) +{ + u16 buffer[HEADER_WORDS + 128]; + struct io_generic_packet *header; + if (misc_read(dev, 0, buffer, 0)) + return; + + header = (struct io_generic_packet *)&buffer; + + misc_write(dev, 0, buffer, HEADER_WORDS + header->packet_length); +} +#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */ + +#ifdef CONFIG_GDSYS_LEGACY_DRIVERS /* * FPGA io-endpoint reflector * @@ -216,9 +314,60 @@ int do_ioreflect(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 0; } +#else +/* + * FPGA io-endpoint reflector + * + * Syntax: + * ioreflect {reportrate} + */ +int do_ioreflect(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + struct udevice *fpga; + struct regmap *map; + uint rate = 0; + unsigned long long last_seen = 0; + + if (!dev) { + printf("No device selected\n"); + return 1; + } + + gdsys_soc_get_fpga(dev, &fpga); + regmap_init_mem(dev_ofnode(dev), &map); + + /* Enable receive path */ + misc_set_enabled(dev, true); + + rx_ctr = 0; tx_ctr = 0; err_ctr = 0; + + while (1) { + uint top_int; + + ihs_fpga_get(map, top_interrupt, &top_int); + io_check_status(dev, STATUS_SILENT); + if ((top_int & IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS) && + (top_int & IRQ_CPU_TRANSMITBUFFER_FREE_STATUS)) + io_reflect(dev); + + if (rate) { + if (!(tx_ctr % rate) && (tx_ctr != last_seen)) + printf("refl %llu, err %llu\n", tx_ctr, + err_ctr); + last_seen = tx_ctr; + } + + if (ctrlc()) + break; + } + + return 0; +} +#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */ #define DISP_LINE_LEN 16 +#ifdef CONFIG_GDSYS_LEGACY_DRIVERS /* * FPGA io-endpoint looptest * @@ -284,7 +433,122 @@ int do_ioloop(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 0; } +#else +/* + * FPGA io-endpoint looptest + * + * Syntax: + * ioloop {size} {rate} + */ +int do_ioloop(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + uint size; + uint rate = 0; + struct udevice *fpga; + struct regmap *map; + if (!dev) { + printf("No device selected\n"); + return 1; + } + + gdsys_soc_get_fpga(dev, &fpga); + regmap_init_mem(dev_ofnode(dev), &map); + + if (argc < 2) + return CMD_RET_USAGE; + + /* + * packet size is specified since argc > 1 + */ + size = simple_strtoul(argv[2], NULL, 10); + + /* + * If another parameter, it is the test rate in packets per second. + */ + if (argc > 2) + rate = simple_strtoul(argv[3], NULL, 10); + + /* Enable receive path */ + misc_set_enabled(dev, true); + + rx_ctr = 0; tx_ctr = 0; err_ctr = 0; + + while (1) { + uint top_int; + + if (ctrlc()) + break; + + ihs_fpga_get(map, top_interrupt, &top_int); + + io_check_status(dev, STATUS_LOUD); + if (top_int & IRQ_CPU_TRANSMITBUFFER_FREE_STATUS) + io_send(dev, size); + if (top_int & IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS) + io_receive(dev); + + if (rate) { + udelay(1000000 / rate); + if (!(tx_ctr % rate)) + printf("d %llu, tx %llu, rx %llu, err %llu\n", + tx_ctr - rx_ctr, tx_ctr, rx_ctr, + err_ctr); + } + } + return 0; +} +#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */ + +#ifndef CONFIG_GDSYS_LEGACY_DRIVERS +int do_iodev(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + struct udevice *ioep = NULL; + struct udevice *board; + char name[8]; + int ret; + + if (board_get(&board)) + return CMD_RET_FAILURE; + + if (argc > 1) { + int i = simple_strtoul(argv[1], NULL, 10); + + snprintf(name, sizeof(name), "ioep%d", i); + + ret = uclass_get_device_by_phandle(UCLASS_MISC, board, name, &ioep); + + if (ret || !ioep) { + printf("Invalid IOEP %d\n", i); + return CMD_RET_FAILURE; + } + + dev = ioep; + } else { + int i = 0; + + while (1) { + snprintf(name, sizeof(name), "ioep%d", i); + + ret = uclass_get_device_by_phandle(UCLASS_MISC, board, name, &ioep); + + if (ret || !ioep) + break; + + printf("IOEP %d:\t%s\n", i++, ioep->name); + } + + if (dev) + printf("\nSelected IOEP: %s\n", dev->name); + else + puts("\nNo IOEP selected.\n"); + } + + return 0; +} +#endif /* !CONFIG_GDSYS_LEGACY_DRIVERS */ + +#ifdef CONFIG_GDSYS_LEGACY_DRIVERS U_BOOT_CMD( ioloop, 4, 0, do_ioloop, "fpga io-endpoint looptest", @@ -296,3 +560,22 @@ U_BOOT_CMD( "fpga io-endpoint reflector", "fpga reportrate" ); +#else +U_BOOT_CMD( + ioloop, 3, 0, do_ioloop, + "fpga io-endpoint looptest", + "packetsize [packets/sec]" +); + +U_BOOT_CMD( + ioreflect, 2, 0, do_ioreflect, + "fpga io-endpoint reflector", + "reportrate" +); + +U_BOOT_CMD( + iodev, 2, 0, do_iodev, + "fpga io-endpoint listing/selection", + "[ioep device to select]" +); +#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */ From 33534526ec89e4f886d17503ecbc0646045f4da9 Mon Sep 17 00:00:00 2001 From: Mario Six Date: Fri, 29 Mar 2019 10:18:15 +0100 Subject: [PATCH 82/86] gdsys: ioep-fpga: Switch to gazerbeam-style reporting Use a more extensive FPGA feature reporting style in the gdsys ioep-fpga driver. Signed-off-by: Mario Six --- board/gdsys/common/ioep-fpga.c | 659 +++++++++++++++++++++++++-------- 1 file changed, 504 insertions(+), 155 deletions(-) diff --git a/board/gdsys/common/ioep-fpga.c b/board/gdsys/common/ioep-fpga.c index 91eec3ac7c..066222c563 100644 --- a/board/gdsys/common/ioep-fpga.c +++ b/board/gdsys/common/ioep-fpga.c @@ -10,231 +10,580 @@ #include -enum { - UNITTYPE_MAIN_SERVER = 0, - UNITTYPE_MAIN_USER = 1, - UNITTYPE_VIDEO_SERVER = 2, - UNITTYPE_VIDEO_USER = 3, +enum pcb_video_type { + PCB_DVI_SL, + PCB_DP_165MPIX, + PCB_DP_300MPIX, + PCB_HDMI, + PCB_DP_1_2, + PCB_HDMI_2_0, }; -enum { - UNITTYPEPCB_DVI = 0, - UNITTYPEPCB_DP_165 = 1, - UNITTYPEPCB_DP_300 = 2, - UNITTYPEPCB_HDMI = 3, +enum pcb_transmission_type { + PCB_CAT_1G, + PCB_FIBER_3G, + PCB_CAT_10G, + PCB_FIBER_10G, }; -enum { - COMPRESSION_NONE = 0, - COMPRESSION_TYPE_1 = 1, - COMPRESSION_TYPE_1_2 = 3, - COMPRESSION_TYPE_1_2_3 = 7, +enum carrier_speed { + CARRIER_SPEED_1G, + CARRIER_SPEED_3G, + CARRIER_SPEED_2_5G = CARRIER_SPEED_3G, + CARRIER_SPEED_10G, }; -enum { - AUDIO_NONE = 0, - AUDIO_TX = 1, - AUDIO_RX = 2, - AUDIO_RXTX = 3, +enum ram_config { + RAM_DDR2_32BIT_295MBPS, + RAM_DDR3_32BIT_590MBPS, + RAM_DDR3_48BIT_590MBPS, + RAM_DDR3_64BIT_1800MBPS, + RAM_DDR3_48BIT_1800MBPS, }; -enum { - SYSCLK_147456 = 0, +enum sysclock { + SYSCLK_147456, }; -enum { - RAM_DDR2_32 = 0, - RAM_DDR3_32 = 1, - RAM_DDR3_48 = 2, +struct fpga_versions { + bool video_channel; + bool con_side; + enum pcb_video_type pcb_video_type; + enum pcb_transmission_type pcb_transmission_type; + unsigned int hw_version; }; -enum { - CARRIER_SPEED_1G = 0, - CARRIER_SPEED_2_5G = 1, +struct fpga_features { + u8 video_channels; + u8 carriers; + enum carrier_speed carrier_speed; + enum ram_config ram_config; + enum sysclock sysclock; + + bool pcm_tx; + bool pcm_rx; + bool spdif_tx; + bool spdif_rx; + bool usb2; + bool rs232; + bool compression_type1; + bool compression_type2; + bool compression_type3; + bool interlace; + bool osd; + bool compression_pipes; }; +#ifdef CONFIG_SYS_FPGA_FLAVOR_GAZERBEAM + +static int get_versions(unsigned int fpga, struct fpga_versions *versions) +{ + enum { + VERSIONS_FPGA_VIDEO_CHANNEL = BIT(12), + VERSIONS_FPGA_CON_SIDE = BIT(13), + VERSIONS_FPGA_SC = BIT(14), + VERSIONS_PCB_CON = BIT(9), + VERSIONS_PCB_SC = BIT(8), + VERSIONS_PCB_VIDEO_MASK = 0x3 << 6, + VERSIONS_PCB_VIDEO_DP_1_2 = 0x0 << 6, + VERSIONS_PCB_VIDEO_HDMI_2_0 = 0x1 << 6, + VERSIONS_PCB_TRANSMISSION_MASK = 0x3 << 4, + VERSIONS_PCB_TRANSMISSION_FIBER_10G = 0x0 << 4, + VERSIONS_PCB_TRANSMISSION_CAT_10G = 0x1 << 4, + VERSIONS_PCB_TRANSMISSION_FIBER_3G = 0x2 << 4, + VERSIONS_PCB_TRANSMISSION_CAT_1G = 0x3 << 4, + VERSIONS_HW_VER_MASK = 0xf << 0, + }; + u16 raw_versions; + + memset(versions, 0, sizeof(struct fpga_versions)); + + FPGA_GET_REG(fpga, versions, &raw_versions); + + versions->video_channel = raw_versions & VERSIONS_FPGA_VIDEO_CHANNEL; + versions->con_side = raw_versions & VERSIONS_FPGA_CON_SIDE; + + switch (raw_versions & VERSIONS_PCB_VIDEO_MASK) { + case VERSIONS_PCB_VIDEO_DP_1_2: + versions->pcb_video_type = PCB_DP_1_2; + break; + + case VERSIONS_PCB_VIDEO_HDMI_2_0: + versions->pcb_video_type = PCB_HDMI_2_0; + break; + } + + switch (raw_versions & VERSIONS_PCB_TRANSMISSION_MASK) { + case VERSIONS_PCB_TRANSMISSION_FIBER_10G: + versions->pcb_transmission_type = PCB_FIBER_10G; + break; + + case VERSIONS_PCB_TRANSMISSION_CAT_10G: + versions->pcb_transmission_type = PCB_CAT_10G; + break; + + case VERSIONS_PCB_TRANSMISSION_FIBER_3G: + versions->pcb_transmission_type = PCB_FIBER_3G; + break; + + case VERSIONS_PCB_TRANSMISSION_CAT_1G: + versions->pcb_transmission_type = PCB_CAT_1G; + break; + + } + + versions->hw_version = raw_versions & VERSIONS_HW_VER_MASK; + + return 0; +} + +static int get_features(unsigned int fpga, struct fpga_features *features) +{ + enum { + FEATURE_SPDIF_RX = BIT(15), + FEATURE_SPDIF_TX = BIT(14), + FEATURE_PCM_RX = BIT(13), + FEATURE_PCM_TX = BIT(12), + FEATURE_RAM_MASK = GENMASK(11, 8), + FEATURE_RAM_DDR2_32BIT_295MBPS = 0x0 << 8, + FEATURE_RAM_DDR3_32BIT_590MBPS = 0x1 << 8, + FEATURE_RAM_DDR3_48BIT_590MBPS = 0x2 << 8, + FEATURE_RAM_DDR3_64BIT_1800MBPS = 0x3 << 8, + FEATURE_RAM_DDR3_48BIT_1800MBPS = 0x4 << 8, + FEATURE_CARRIER_SPEED_MASK = GENMASK(7, 6), + FEATURE_CARRIER_SPEED_1G = 0x0 << 6, + FEATURE_CARRIER_SPEED_2_5G = 0x1 << 6, + FEATURE_CARRIER_SPEED_10G = 0x2 << 6, + FEATURE_CARRIERS_MASK = GENMASK(5, 4), + FEATURE_CARRIERS_0 = 0x0 << 4, + FEATURE_CARRIERS_1 = 0x1 << 4, + FEATURE_CARRIERS_2 = 0x2 << 4, + FEATURE_CARRIERS_4 = 0x3 << 4, + FEATURE_USB2 = BIT(3), + FEATURE_VIDEOCHANNELS_MASK = GENMASK(2, 0), + FEATURE_VIDEOCHANNELS_0 = 0x0 << 0, + FEATURE_VIDEOCHANNELS_1 = 0x1 << 0, + FEATURE_VIDEOCHANNELS_1_1 = 0x2 << 0, + FEATURE_VIDEOCHANNELS_2 = 0x3 << 0, + }; + + enum { + EXT_FEATURE_OSD = BIT(15), + EXT_FEATURE_ETHERNET = BIT(9), + EXT_FEATURE_INTERLACE = BIT(8), + EXT_FEATURE_RS232 = BIT(7), + EXT_FEATURE_COMPRESSION_PERF_MASK = GENMASK(6, 4), + EXT_FEATURE_COMPRESSION_PERF_1X = 0x0 << 4, + EXT_FEATURE_COMPRESSION_PERF_2X = 0x1 << 4, + EXT_FEATURE_COMPRESSION_PERF_4X = 0x2 << 4, + EXT_FEATURE_COMPRESSION_TYPE1 = BIT(0), + EXT_FEATURE_COMPRESSION_TYPE2 = BIT(1), + EXT_FEATURE_COMPRESSION_TYPE3 = BIT(2), + }; + + u16 raw_features; + u16 raw_extended_features; + + memset(features, 0, sizeof(struct fpga_features)); + + FPGA_GET_REG(fpga, fpga_features, &raw_features); + FPGA_GET_REG(fpga, fpga_ext_features, &raw_extended_features); + + switch (raw_features & FEATURE_VIDEOCHANNELS_MASK) { + case FEATURE_VIDEOCHANNELS_0: + features->video_channels = 0; + break; + + case FEATURE_VIDEOCHANNELS_1: + features->video_channels = 1; + break; + + case FEATURE_VIDEOCHANNELS_1_1: + case FEATURE_VIDEOCHANNELS_2: + features->video_channels = 2; + break; + }; + + switch (raw_features & FEATURE_CARRIERS_MASK) { + case FEATURE_CARRIERS_0: + features->carriers = 0; + break; + + case FEATURE_CARRIERS_1: + features->carriers = 1; + break; + + case FEATURE_CARRIERS_2: + features->carriers = 2; + break; + + case FEATURE_CARRIERS_4: + features->carriers = 4; + break; + } + + switch (raw_features & FEATURE_CARRIER_SPEED_MASK) { + case FEATURE_CARRIER_SPEED_1G: + features->carrier_speed = CARRIER_SPEED_1G; + break; + case FEATURE_CARRIER_SPEED_2_5G: + features->carrier_speed = CARRIER_SPEED_2_5G; + break; + case FEATURE_CARRIER_SPEED_10G: + features->carrier_speed = CARRIER_SPEED_10G; + break; + } + + switch (raw_features & FEATURE_RAM_MASK) { + case FEATURE_RAM_DDR2_32BIT_295MBPS: + features->ram_config = RAM_DDR2_32BIT_295MBPS; + break; + + case FEATURE_RAM_DDR3_32BIT_590MBPS: + features->ram_config = RAM_DDR3_32BIT_590MBPS; + break; + + case FEATURE_RAM_DDR3_48BIT_590MBPS: + features->ram_config = RAM_DDR3_48BIT_590MBPS; + break; + + case FEATURE_RAM_DDR3_64BIT_1800MBPS: + features->ram_config = RAM_DDR3_64BIT_1800MBPS; + break; + + case FEATURE_RAM_DDR3_48BIT_1800MBPS: + features->ram_config = RAM_DDR3_48BIT_1800MBPS; + break; + } + + features->pcm_tx = raw_features & FEATURE_PCM_TX; + features->pcm_rx = raw_features & FEATURE_PCM_RX; + features->spdif_tx = raw_features & FEATURE_SPDIF_TX; + features->spdif_rx = raw_features & FEATURE_SPDIF_RX; + features->usb2 = raw_features & FEATURE_USB2; + features->rs232 = raw_extended_features & EXT_FEATURE_RS232; + features->compression_type1 = raw_extended_features & EXT_FEATURE_COMPRESSION_TYPE1; + features->compression_type2 = raw_extended_features & EXT_FEATURE_COMPRESSION_TYPE2; + features->compression_type3 = raw_extended_features & EXT_FEATURE_COMPRESSION_TYPE3; + features->interlace = raw_extended_features & EXT_FEATURE_INTERLACE; + features->osd = raw_extended_features & EXT_FEATURE_OSD; + features->compression_pipes = raw_extended_features & EXT_FEATURE_COMPRESSION_PERF_MASK; + + return 0; +} + +#else + +static int get_versions(unsigned int fpga, struct fpga_versions *versions) +{ + enum { + /* HW version encoding is a mess, leave it for the moment */ + VERSIONS_HW_VER_MASK = 0xf << 0, + VERSIONS_PIX_CLOCK_GEN_IDT8N3QV01 = BIT(4), + VERSIONS_SFP = BIT(5), + VERSIONS_VIDEO_MASK = 0x7 << 6, + VERSIONS_VIDEO_DVI = 0x0 << 6, + VERSIONS_VIDEO_DP_165 = 0x1 << 6, + VERSIONS_VIDEO_DP_300 = 0x2 << 6, + VERSIONS_VIDEO_HDMI = 0x3 << 6, + VERSIONS_UT_MASK = 0xf << 12, + VERSIONS_UT_MAIN_SERVER = 0x0 << 12, + VERSIONS_UT_MAIN_USER = 0x1 << 12, + VERSIONS_UT_VIDEO_SERVER = 0x2 << 12, + VERSIONS_UT_VIDEO_USER = 0x3 << 12, + }; + u16 raw_versions; + + memset(versions, 0, sizeof(struct fpga_versions)); + + FPGA_GET_REG(fpga, versions, &raw_versions); + + switch (raw_versions & VERSIONS_UT_MASK) { + case VERSIONS_UT_MAIN_SERVER: + versions->video_channel = false; + versions->con_side = false; + break; + + case VERSIONS_UT_MAIN_USER: + versions->video_channel = false; + versions->con_side = true; + break; + + case VERSIONS_UT_VIDEO_SERVER: + versions->video_channel = true; + versions->con_side = false; + break; + + case VERSIONS_UT_VIDEO_USER: + versions->video_channel = true; + versions->con_side = true; + break; + + } + + switch (raw_versions & VERSIONS_VIDEO_MASK) { + case VERSIONS_VIDEO_DVI: + versions->pcb_video_type = PCB_DVI_SL; + break; + + case VERSIONS_VIDEO_DP_165: + versions->pcb_video_type = PCB_DP_165MPIX; + break; + + case VERSIONS_VIDEO_DP_300: + versions->pcb_video_type = PCB_DP_300MPIX; + break; + + case VERSIONS_VIDEO_HDMI: + versions->pcb_video_type = PCB_HDMI; + break; + } + + versions->hw_version = raw_versions & VERSIONS_HW_VER_MASK; + + if (raw_versions & VERSIONS_SFP) + versions->pcb_transmission_type = PCB_FIBER_3G; + else + versions->pcb_transmission_type = PCB_CAT_1G; + + return 0; +} + +static int get_features(unsigned int fpga, struct fpga_features *features) +{ + enum { + FEATURE_CARRIER_SPEED_2_5 = BIT(4), + FEATURE_RAM_MASK = 0x7 << 5, + FEATURE_RAM_DDR2_32BIT = 0x0 << 5, + FEATURE_RAM_DDR3_32BIT = 0x1 << 5, + FEATURE_RAM_DDR3_48BIT = 0x2 << 5, + FEATURE_PCM_AUDIO_TX = BIT(9), + FEATURE_PCM_AUDIO_RX = BIT(10), + FEATURE_OSD = BIT(11), + FEATURE_USB20 = BIT(12), + FEATURE_COMPRESSION_MASK = 7 << 13, + FEATURE_COMPRESSION_TYPE1 = 0x1 << 13, + FEATURE_COMPRESSION_TYPE1_TYPE2 = 0x3 << 13, + FEATURE_COMPRESSION_TYPE1_TYPE2_TYPE3 = 0x7 << 13, + }; + + enum { + EXTENDED_FEATURE_SPDIF_AUDIO_TX = BIT(0), + EXTENDED_FEATURE_SPDIF_AUDIO_RX = BIT(1), + EXTENDED_FEATURE_RS232 = BIT(2), + EXTENDED_FEATURE_COMPRESSION_PIPES = BIT(3), + EXTENDED_FEATURE_INTERLACE = BIT(4), + }; + + u16 raw_features; +#ifdef GDSYS_LEGACY_DRIVERS + u16 raw_extended_features; +#endif + + memset(features, 0, sizeof(struct fpga_features)); + + FPGA_GET_REG(fpga, fpga_features, &raw_features); +#ifdef GDSYS_LEGACY_DRIVERS + FPGA_GET_REG(fpga, fpga_ext_features, &raw_extended_features); +#endif + + features->video_channels = raw_features & 0x3; + features->carriers = (raw_features >> 2) & 0x3; + + features->carrier_speed = (raw_features & FEATURE_CARRIER_SPEED_2_5) + ? CARRIER_SPEED_2_5G : CARRIER_SPEED_1G; + + switch (raw_features & FEATURE_RAM_MASK) { + case FEATURE_RAM_DDR2_32BIT: + features->ram_config = RAM_DDR2_32BIT_295MBPS; + break; + + case FEATURE_RAM_DDR3_32BIT: + features->ram_config = RAM_DDR3_32BIT_590MBPS; + break; + + case FEATURE_RAM_DDR3_48BIT: + features->ram_config = RAM_DDR3_48BIT_590MBPS; + break; + } + + features->pcm_tx = raw_features & FEATURE_PCM_AUDIO_TX; + features->pcm_rx = raw_features & FEATURE_PCM_AUDIO_RX; +#ifdef GDSYS_LEGACY_DRIVERS + features->spdif_tx = raw_extended_features & EXTENDED_FEATURE_SPDIF_AUDIO_TX; + features->spdif_rx = raw_extended_features & EXTENDED_FEATURE_SPDIF_AUDIO_RX; +#endif + + features->usb2 = raw_features & FEATURE_USB20; +#ifdef GDSYS_LEGACY_DRIVERS + features->rs232 = raw_extended_features & EXTENDED_FEATURE_RS232; +#endif + + features->compression_type1 = false; + features->compression_type2 = false; + features->compression_type3 = false; + switch (raw_features & FEATURE_COMPRESSION_MASK) { + case FEATURE_COMPRESSION_TYPE1_TYPE2_TYPE3: + features->compression_type3 = true; + case FEATURE_COMPRESSION_TYPE1_TYPE2: + features->compression_type2 = true; + case FEATURE_COMPRESSION_TYPE1: + features->compression_type1 = true; + break; + } + +#ifdef GDSYS_LEGACY_DRIVERS + features->interlace = raw_extended_features & EXTENDED_FEATURE_INTERLACE; +#endif + features->osd = raw_features & FEATURE_OSD; +#ifdef GDSYS_LEGACY_DRIVERS + features->compression_pipes = raw_extended_features & EXTENDED_FEATURE_COMPRESSION_PIPES; +#endif + + return 0; +} + +#endif + bool ioep_fpga_has_osd(unsigned int fpga) { - u16 fpga_features; - unsigned feature_osd; + struct fpga_features features; - FPGA_GET_REG(0, fpga_features, &fpga_features); - feature_osd = fpga_features & (1<<11); + get_features(fpga, &features); - return feature_osd; + return features.osd; } void ioep_fpga_print_info(unsigned int fpga) { - u16 versions; u16 fpga_version; - u16 fpga_features; - unsigned unit_type; - unsigned unit_type_pcb_video; - unsigned feature_compression; - unsigned feature_osd; - unsigned feature_audio; - unsigned feature_sysclock; - unsigned feature_ramconfig; - unsigned feature_carrier_speed; - unsigned feature_carriers; - unsigned feature_video_channels; + struct fpga_versions versions; + struct fpga_features features; - FPGA_GET_REG(fpga, versions, &versions); FPGA_GET_REG(fpga, fpga_version, &fpga_version); - FPGA_GET_REG(fpga, fpga_features, &fpga_features); + get_versions(fpga, &versions); + get_features(fpga, &features); - unit_type = (versions & 0xf000) >> 12; - unit_type_pcb_video = (versions & 0x01c0) >> 6; - feature_compression = (fpga_features & 0xe000) >> 13; - feature_osd = fpga_features & (1<<11); - feature_audio = (fpga_features & 0x0600) >> 9; - feature_sysclock = (fpga_features & 0x0180) >> 7; - feature_ramconfig = (fpga_features & 0x0060) >> 5; - feature_carrier_speed = fpga_features & (1<<4); - feature_carriers = (fpga_features & 0x000c) >> 2; - feature_video_channels = fpga_features & 0x0003; - - switch (unit_type) { - case UNITTYPE_MAIN_SERVER: - case UNITTYPE_MAIN_USER: - printf("Mainchannel"); - break; - - case UNITTYPE_VIDEO_SERVER: - case UNITTYPE_VIDEO_USER: + if (versions.video_channel) printf("Videochannel"); - break; + else + printf("Mainchannel"); - default: - printf("UnitType %d(not supported)", unit_type); - break; - } - - switch (unit_type) { - case UNITTYPE_MAIN_SERVER: - case UNITTYPE_VIDEO_SERVER: + if (versions.con_side) + printf(" User"); + else printf(" Server"); + +// FIXME +#if 0 if (versions & (1<<4)) printf(" UC"); - break; +#endif - case UNITTYPE_MAIN_USER: - case UNITTYPE_VIDEO_USER: - printf(" User"); - break; - - default: - break; - } - - if (versions & (1<<5)) - printf(" Fiber"); - else + switch(versions.pcb_transmission_type) { + case PCB_CAT_1G: + case PCB_CAT_10G: printf(" CAT"); + break; + case PCB_FIBER_3G: + case PCB_FIBER_10G: + printf(" Fiber"); + break; + }; - switch (unit_type_pcb_video) { - case UNITTYPEPCB_DVI: + switch (versions.pcb_video_type) { + case PCB_DVI_SL: printf(" DVI,"); break; - - case UNITTYPEPCB_DP_165: + case PCB_DP_165MPIX: printf(" DP 165MPix/s,"); break; - - case UNITTYPEPCB_DP_300: + case PCB_DP_300MPIX: printf(" DP 300MPix/s,"); break; - - case UNITTYPEPCB_HDMI: + case PCB_HDMI: printf(" HDMI,"); break; + case PCB_DP_1_2: + printf(" DP 1.2,"); + break; + case PCB_HDMI_2_0: + printf(" HDMI 2.0,"); + break; } - printf(" FPGA V %d.%02d\n features:", + printf(" FPGA V %d.%02d\n features: ", fpga_version / 100, fpga_version % 100); + if (!features.compression_type1 && + !features.compression_type2 && + !features.compression_type3) + printf("no compression, "); - switch (feature_compression) { - case COMPRESSION_NONE: - printf(" no compression"); - break; + if (features.compression_type1) + printf("type1, "); - case COMPRESSION_TYPE_1: - printf(" compression type1(delta)"); - break; + if (features.compression_type2) + printf("type2, "); - case COMPRESSION_TYPE_1_2: - printf(" compression type1(delta), type2(inline)"); - break; + if (features.compression_type3) + printf("type3, "); - case COMPRESSION_TYPE_1_2_3: - printf(" compression type1(delta), type2(inline), type3(intempo)"); - break; + printf("%sosd", features.osd ? "" : "no "); - default: - printf(" compression %d(not supported)", feature_compression); - break; - } + if (features.pcm_rx && features.pcm_tx) + printf(", pcm rx+tx"); + else if(features.pcm_rx) + printf(", pcm rx"); + else if(features.pcm_tx) + printf(", pcm tx"); - printf(", %sosd", feature_osd ? "" : "no "); - - switch (feature_audio) { - case AUDIO_NONE: - printf(", no audio"); - break; - - case AUDIO_TX: - printf(", audio tx"); - break; - - case AUDIO_RX: - printf(", audio rx"); - break; - - case AUDIO_RXTX: - printf(", audio rx+tx"); - break; - - default: - printf(", audio %d(not supported)", feature_audio); - break; - } + if (features.spdif_rx && features.spdif_tx) + printf(", spdif rx+tx"); + else if(features.spdif_rx) + printf(", spdif rx"); + else if(features.spdif_tx) + printf(", spdif tx"); puts(",\n "); - switch (feature_sysclock) { + switch (features.sysclock) { case SYSCLK_147456: printf("clock 147.456 MHz"); break; - - default: - printf("clock %d(not supported)", feature_sysclock); - break; } - switch (feature_ramconfig) { - case RAM_DDR2_32: + switch (features.ram_config) { + case RAM_DDR2_32BIT_295MBPS: printf(", RAM 32 bit DDR2"); break; - - case RAM_DDR3_32: + case RAM_DDR3_32BIT_590MBPS: printf(", RAM 32 bit DDR3"); break; - - case RAM_DDR3_48: + case RAM_DDR3_48BIT_590MBPS: + case RAM_DDR3_48BIT_1800MBPS: printf(", RAM 48 bit DDR3"); break; - - default: - printf(", RAM %d(not supported)", feature_ramconfig); + case RAM_DDR3_64BIT_1800MBPS: + printf(", RAM 64 bit DDR3"); break; } - printf(", %d carrier(s) %s", feature_carriers, - feature_carrier_speed ? "2.5Gbit/s" : "1Gbit/s"); + printf(", %d carrier(s)", features.carriers); - printf(", %d video channel(s)\n", feature_video_channels); + switch(features.carrier_speed) { + case CARRIER_SPEED_1G: + printf(", 1Gbit/s"); + break; + case CARRIER_SPEED_3G: + printf(", 3Gbit/s"); + break; + case CARRIER_SPEED_10G: + printf(", 10Gbit/s"); + break; + } + + printf(", %d video channel(s)\n", features.video_channels); } #endif /* CONFIG_GDSYS_LEGACY_DRIVERS */ From 9638879cba99a3736bbae5ba5987e526b7a430d4 Mon Sep 17 00:00:00 2001 From: Mario Six Date: Fri, 29 Mar 2019 10:18:16 +0100 Subject: [PATCH 83/86] board: gazerbeam: Fix SC detection The single channel detection in the gazerbeam board driver was not implemented correctly. Fix the detection. Signed-off-by: Mario Six --- drivers/board/gazerbeam.c | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/drivers/board/gazerbeam.c b/drivers/board/gazerbeam.c index 481cce8e80..85de4e440c 100644 --- a/drivers/board/gazerbeam.c +++ b/drivers/board/gazerbeam.c @@ -61,7 +61,7 @@ static int _read_board_variant_data(struct udevice *dev) struct udevice *i2c_bus; struct udevice *dummy; char *listname; - int mc4, mc2, sc, con; + int mc4, mc2, sc, mc2_sc, con; int gpio_num; int res; @@ -78,16 +78,16 @@ static int _read_board_variant_data(struct udevice *dev) return -EIO; } - mc2 = !dm_i2c_probe(i2c_bus, MC2_EXPANDER_ADDR, 0, &dummy); + mc2_sc = !dm_i2c_probe(i2c_bus, MC2_EXPANDER_ADDR, 0, &dummy); mc4 = !dm_i2c_probe(i2c_bus, MC4_EXPANDER_ADDR, 0, &dummy); - if (mc2 && mc4) { + if (mc2_sc && mc4) { debug("%s: Board hardware configuration inconsistent.\n", dev->name); return -EINVAL; } - listname = mc2 ? "var-gpios-mc2" : "var-gpios-mc4"; + listname = mc2_sc ? "var-gpios-mc2" : "var-gpios-mc4"; gpio_num = gpio_request_list_by_name(dev, listname, priv->var_gpios, ARRAY_SIZE(priv->var_gpios), @@ -105,12 +105,7 @@ static int _read_board_variant_data(struct udevice *dev) return sc; } - con = dm_gpio_get_value(&priv->var_gpios[CON_GPIO_NO]); - if (con < 0) { - debug("%s: Error while reading 'con' GPIO (err = %d)", - dev->name, con); - return con; - } + mc2 = mc2_sc ? (sc ? 0 : 1) : 0; if ((sc && mc2) || (sc && mc4) || (!sc && !mc2 && !mc4)) { debug("%s: Board hardware configuration inconsistent.\n", @@ -118,6 +113,13 @@ static int _read_board_variant_data(struct udevice *dev) return -EINVAL; } + con = dm_gpio_get_value(&priv->var_gpios[CON_GPIO_NO]); + if (con < 0) { + debug("%s: Error while reading 'con' GPIO (err = %d)", + dev->name, con); + return con; + } + priv->variant = con ? VAR_CON : VAR_CPU; priv->multichannel = mc4 ? 4 : (mc2 ? 2 : (sc ? 1 : 0)); From 96373c1d91ab7ec4d781d5b73828abda1419ca25 Mon Sep 17 00:00:00 2001 From: Mario Six Date: Fri, 29 Mar 2019 10:18:17 +0100 Subject: [PATCH 84/86] gazerbeam: Import Linux DT Import the Linux device tree for the Gazerbeam board. Signed-off-by: Mario Six --- arch/powerpc/dts/.gitignore | 1 + arch/powerpc/dts/Makefile | 1 + arch/powerpc/dts/gazerbeam.dts | 600 ++++++++++++++++++ arch/powerpc/dts/gdsys/gazerbeam-base.dtsi | 185 ++++++ arch/powerpc/dts/gdsys/mpc8308.dtsi | 354 +++++++++++ .../dts/gdsys/soc/i2c/cirrus-audio-codec.dtsi | 6 + .../powerpc/dts/gdsys/soc/i2c/dallas-rtc.dtsi | 6 + arch/powerpc/dts/gdsys/soc/lbc/gazerbeam.dtsi | 5 + .../gdsys/soc/nor/flash-80k-partition.dtsi | 20 + 9 files changed, 1178 insertions(+) create mode 100644 arch/powerpc/dts/.gitignore create mode 100644 arch/powerpc/dts/gazerbeam.dts create mode 100644 arch/powerpc/dts/gdsys/gazerbeam-base.dtsi create mode 100644 arch/powerpc/dts/gdsys/mpc8308.dtsi create mode 100644 arch/powerpc/dts/gdsys/soc/i2c/cirrus-audio-codec.dtsi create mode 100644 arch/powerpc/dts/gdsys/soc/i2c/dallas-rtc.dtsi create mode 100644 arch/powerpc/dts/gdsys/soc/lbc/gazerbeam.dtsi create mode 100644 arch/powerpc/dts/gdsys/soc/nor/flash-80k-partition.dtsi diff --git a/arch/powerpc/dts/.gitignore b/arch/powerpc/dts/.gitignore new file mode 100644 index 0000000000..b60ed208c7 --- /dev/null +++ b/arch/powerpc/dts/.gitignore @@ -0,0 +1 @@ +*.dtb diff --git a/arch/powerpc/dts/Makefile b/arch/powerpc/dts/Makefile index f080a96891..6a28f802c2 100644 --- a/arch/powerpc/dts/Makefile +++ b/arch/powerpc/dts/Makefile @@ -2,6 +2,7 @@ dtb-$(CONFIG_TARGET_T2080QDS) += t2080qds.dtb dtb-$(CONFIG_TARGET_MCR3000) += mcr3000.dtb +dtb-$(CONFIG_TARGET_GAZERBEAM) += gazerbeam.dtb targets += $(dtb-y) diff --git a/arch/powerpc/dts/gazerbeam.dts b/arch/powerpc/dts/gazerbeam.dts new file mode 100644 index 0000000000..a4408c496c --- /dev/null +++ b/arch/powerpc/dts/gazerbeam.dts @@ -0,0 +1,600 @@ +/* + * Gazerbeam CON Device Tree Source + * + * (C) Copyright 2015 + * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +/include/ "gdsys/mpc8308.dtsi" + +/include/ "gdsys/gazerbeam-base.dtsi" + +/include/ "gdsys/soc/i2c/cirrus-audio-codec.dtsi" +/include/ "gdsys/soc/i2c/dallas-rtc.dtsi" +/include/ "gdsys/soc/lbc/gazerbeam.dtsi" +/include/ "gdsys/soc/nor/flash-80k-partition.dtsi" + +&board_lbc { + FPGA0:iocon_uart@1,0 { + reg = <0x1 0x0 0x100000>; + little-endian; + interrupts = <48 0x8>; + interrupt-parent = <&ipic>; + }; + + FPGA1:iocon_uart@2,0 { + reg = <0x2 0x0 0x100000>; + little-endian; + interrupts = <17 0x8>; + interrupt-parent = <&ipic>; + }; +}; + +&FPGA0 { + compatible = "gdsys,iocon_fpga"; + #gpio-cells = <2>; + gpio-controller; + bus = <&FPGA0BUS>; + unit_id = <0>; + fpga-type = <1>; + usb_base = <0x0080>; + audio_base = <0x0040>; + timebase_base = <0x013c>; + + /* + * for every interrupt source there must be a dataset specifying + * 1. type (1: standard) + * 2. status register offset + * 3. mask register offset + * 4. default mask + */ + fpga_interrupt_sources = + <1 0x000a 0x000c 0x4000>, /* 0: TOP_INTERRUPT */ + <1 0x001c 0x001e 0x0000>; /* 1: EXTENDED_INTERRUPT */ + /* + * for every interrupt there must be a dataset specifying + * 1. type (1: status, 2: event) + * 2. interrupt source index + * 3. interrupt register bit + * 4. mask register bit + */ + #fpga_interrupt_map-cells = <4>; + fpga_interrupt_map = + <1 0 14 14>, /* 0: EXTENDED_INTERRUPT */ + <1 0 0 0>, /* 1: VIDEO 0 */ + <1 0 1 1>, /* 2: VIDEO 1 */ + <1 0 2 2>, /* 3: VIDEO IC 0 */ + <1 0 3 3>, /* 4: VIDEO IC 1 */ + <1 0 4 4>, /* 5: IIC MAIN */ + <1 0 6 6>, /* 6: IIC VIDEO 0 */ + <1 0 7 7>, /* 7: IIC VIDEO 1 */ + <1 1 0 0>, /* 8: OSD 0 */ + <1 1 1 1>, /* 9: OSD 1 */ + <1 1 2 2>, /* 10: SPDIF 0 */ + <1 1 3 3>, /* 11: SPDIF 1 */ + <1 0 12 12>, /* 12: COMM 0 */ + <1 0 13 13>, /* 13: COMM 1 */ + <1 0 10 10>, /* 14: COMM 2 */ + <1 0 11 11>, /* 15: COMM 3 */ + <2 0 5 5>, /* 16: MDIO */ + <1 0 8 8>, /* 17: PHY */ + <1 1 4 4>, /* 18: RS232 */ + <1 1 5 5>, /* 19: AUDIO */ + <1 1 8 8>, /* 20: PROC_AUDIO */ + <1 1 7 7>, /* 21: USB/ETH-UART INT */ + <2 1 10 10>, /* 22: AXI Bridge 0 */ + <2 1 11 11>, /* 23: AXI Bridge 1 */ + <2 1 9 9>, /* 24: USB/ETH-Secondary IIC */ + <>; +}; + +&FPGA1 { + compatible = "gdsys,iocon_fpga"; + #gpio-cells = <2>; + gpio-controller; + bus = <&FPGA1BUS>; + unit_id = <1>; + fpga-type = <1>; + usb_base = <0x0070>; + audio_base = <0x0040>; + timebase_base = <0x013c>; + + /* + * for every interrupt source there must be a dataset specifying + * 1. type (1: standard) + * 2. status register offset + * 3. mask register offset + * 4. default mask + */ + fpga_interrupt_sources = + <1 0x000a 0x000c 0x4000>, /* 0: TOP_INTERRUPT */ + <1 0x001c 0x001e 0x0000>; /* 1: EXTENDED_INTERRUPT */ + /* + * for every interrupt there must be a dataset specifying + * 1. type (1: status, 2: event) + * 2. interrupt source index + * 3. interrupt register bit + * 4. mask register bit + */ + #fpga_interrupt_map-cells = <4>; + fpga_interrupt_map = + <1 0 14 14>, /* 0: EXTENDED_INTERRUPT */ + <1 0 0 0>, /* 1: VIDEO 0 */ + <1 0 1 1>, /* 2: VIDEO 1 */ + <1 0 2 2>, /* 3: VIDEO IC 0 */ + <1 0 3 3>, /* 4: VIDEO IC 1 */ + <1 0 4 4>, /* 5: IIC MAIN */ + <1 0 6 6>, /* 6: IIC VIDEO 0 */ + <1 0 7 7>, /* 7: IIC VIDEO 1 */ + <1 1 0 0>, /* 8: OSD 0 */ + <1 1 1 1>, /* 9: OSD 1 */ + <1 1 2 2>, /* 10: SPDIF 0 */ + <1 1 3 3>, /* 11: SPDIF 1 */ + <1 0 12 12>, /* 12: COMM 0 */ + <1 0 13 13>, /* 13: COMM 1 */ + <1 0 10 10>, /* 14: COMM 2 */ + <1 0 11 11>, /* 15: COMM 3 */ + <2 0 5 5>, /* 16: MDIO */ + <1 0 8 8>, /* 17: PHY */ + <1 1 4 4>, /* 18: RS232 */ + <1 1 5 5>, /* 19: AUDIO */ + <1 1 8 8>, /* 20: PROC_AUDIO */ + <1 1 7 7>, /* 21: USB/ETH-UART INT */ + <2 1 10 10>, /* 22: AXI Bridge 0 */ + <2 1 11 11>, /* 23: AXI Bridge 1 */ + <2 1 9 9>, /* 24: USB/ETH-Secondary IIC */ + <>; +}; + +/ { + FPGA0BUS: fpga0bus { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x00002000>; + + compatible = "gdsys,soc"; + + fpga0_rs232 { + compatible = "gdsys,ihs_trans_rs232"; + reg = <0x50 0x08>; + little-endian; + }; + + fpga0_uart_usb { + compatible = "gdsys,ihs_simple_uart"; + reg = <0xa0 0x08>; + little-endian; + fpga_interrupts = <21>; + line = <0>; + }; + + fpga0_iic_main { + compatible = "gdsys,ihs_i2cmaster"; + reg = <0x60 0x10>; + little-endian; + fpga_interrupts = <5>; + #address-cells = <1>; + #size-cells = <0>; + + fpga0_dp_video0_redriver: fpga0_dp_video0_redriver { + compatible = "ti,sn75dp130"; + reg = <0x2c>; + eq-i2c-enable = <3 2 1 0 + 3 2 1 0 + 3 2 1 0 + 3 2 1 0>; /* 3.5 dB for all pe values for all lanes */ + }; + fpga0_dp_video1_redriver: fpga0_dp_video1_redriver { + compatible = "ti,sn75dp130"; + reg = <0x2e>; + eq-i2c-enable = <3 2 1 0 + 3 2 1 0 + 3 2 1 0 + 3 2 1 0>; /* 3.5 dB for all pe values for all lanes */ + }; + lm77@48 { + compatible = "national,lm77"; + reg = <0x48>; + }; + ads1015@49 { + compatible = "ti,ads1015"; + reg = <0x49>; + }; + ads1015@4b { + compatible = "ti,ads1015"; + reg = <0x4b>; + }; + }; + + fpga0_video0 { + compatible = "gdsys,ihs_video_out"; + reg = <0x100 0x40>; + little-endian; + fpga_interrupts = <1 8>; /* VIDEO OSD */ + osd_base = <0x180>; + osd_buffer_base = <0x1000>; + spdif_audio_base = <0x1e0>; + video_index = <0>; + video_id = <0>; + fpga-force-pos-pol; + sync-source; + fpga-pb-pixels = <2730>; /* 8192 / 3 */ + fpga-ra-lines = <2>; + video_tx = <&fpga0_dp_video0>; + clk_gen = <&fpga0_video0_clkgen>; + ddc_ci = <&fpga0_dp_video0>; + }; + + fpga0_iic_video0 { + compatible = "gdsys,ihs_i2cmaster"; + reg = <0x1c0 0x10>; + little-endian; + fpga_interrupts = <6>; + #address-cells = <1>; + #size-cells = <0>; + + fpga0_video0_clkgen: fpga0_video0_clkgen { + compatible = "idt,ics8n3qv01"; + reg = <0x6e>; + channel = <0>; + }; + }; + + fpga0_axi_video0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "gdsys,ihs_axi"; + reg = <0x170 0x10>; + little-endian; + fpga_interrupts = <22>; + + fpga0_dp_video0: fpga0_dp_video0 { + compatible = "gdsys,logicore_dp_tx"; + reg = <0x44a10000 0x1000>; + little-endian; + redriver = <&fpga0_dp_video0_redriver>; + video_id = <0>; + }; + }; + + fpga0_video1 { + compatible = "gdsys,ihs_video_out"; + reg = <0x200 0x40>; + little-endian; + fpga_interrupts = <2 9>; /* VIDEO OSD */ + osd_base = <0x280>; + osd_buffer_base = <0x2000>; + spdif_audio_base = <0x2e0>; + video_index = <1>; + video_id = <1>; + fpga-force-pos-pol; + sync-source; + fpga-pb-pixels = <2730>; /* 8192 / 3 */ + fpga-ra-lines = <2>; + video_tx = <&fpga0_dp_video1>; + clk_gen = <&fpga0_video1_clkgen>; + ddc_ci = <&fpga0_dp_video1>; + }; + + fpga0_iic_video1 { + compatible = "gdsys,ihs_i2cmaster"; + reg = <0x2c0 0x10>; + little-endian; + fpga_interrupts = <7>; + #address-cells = <1>; + #size-cells = <0>; + + fpga0_video1_clkgen: fpga0_video1_clkgen { + compatible = "idt,ics8n3qv01"; + reg = <0x6e>; + channel = <1>; + }; + }; + + fpga0_axi_video1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "gdsys,ihs_axi"; + reg = <0x270 0x10>; + little-endian; + fpga_interrupts = <23>; + + fpga0_dp_video1: fpga0_dp_video1 { + compatible = "gdsys,logicore_dp_tx"; + reg = <0x44a10000 0x1000>; + little-endian; + redriver = <&fpga0_dp_video1_redriver>; + video_id = <1>; + }; + }; + + fpga0_iic_usb { + compatible = "gdsys,ihs_i2cmaster"; + reg = <0xb0 0x10>; + little-endian; + fpga_interrupts = <24>; + #address-cells = <1>; + #size-cells = <0>; + + pca9555@20 { + compatible = "nxp,pca9555"; + reg = <0x20>; + #gpio-cells = <2>; + gpio-controller; + }; + }; + + fpga0_ep0 { + compatible = "gdsys,io-endpoint"; + reg = < 0x020 0x10 + 0x320 0x10 + 0x340 0x10 + 0x360 0x10>; + little-endian; + irq-model-local; + fpga_interrupts = <12 13 14 15>; + pollcycle = <200>; + nprot_channel = <16>; + uart_line = <0>; + ep_index = <0>; + line_protocol = <1>; + }; + + fpga0_mdio { + compatible = "gdsys,ihs_mdiomaster"; + reg = <0x0058 0x10>; + little-endian; + fpga_interrupts = <16>; + #address-cells = <1>; + #size-cells = <0>; + + fpga0_phy0 { + compatible = "ethernet-phy-ieee802.3-c45"; + device_type ="ethernet-phy"; + reg = <0>; + }; + fpga0_phy1 { + compatible = "ethernet-phy-ieee802.3-c45"; + device_type ="ethernet-phy"; + reg = <1>; + }; + fpga0_phy2 { + compatible = "ethernet-phy-ieee802.3-c45"; + device_type ="ethernet-phy"; + reg = <2>; + }; + fpga0_phy3 { + compatible = "ethernet-phy-ieee802.3-c45"; + device_type ="ethernet-phy"; + reg = <3>; + }; + }; + + }; + + + FPGA1BUS: fpga1bus { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x00002000>; + + compatible = "gdsys,soc"; + + fpga1_uart_usb { + compatible = "gdsys,ihs_simple_uart"; + reg = <0xa0 0x08>; + little-endian; + fpga_interrupts = <21>; + line = <4>; /* TODO check and FIX */ + }; + + fpga1_iic_main { + compatible = "gdsys,ihs_i2cmaster"; + reg = <0x60 0x10>; + little-endian; + fpga_interrupts = <5>; + #address-cells = <1>; + #size-cells = <0>; + + fpga1_dp_video0_redriver: fpga1_dp_video0_redriver { + compatible = "ti,sn75dp130"; + reg = <0x2c>; + eq-i2c-enable = <3 2 1 0 + 3 2 1 0 + 3 2 1 0 + 3 2 1 0>; /* 3.5 dB for all pe values for all lanes */ + }; + fpga1_dp_video1_redriver: fpga1_dp_video1_redriver { + compatible = "ti,sn75dp130"; + reg = <0x2e>; + eq-i2c-enable = <3 2 1 0 + 3 2 1 0 + 3 2 1 0 + 3 2 1 0>; /* 3.5 dB for all pe values for all lanes */ + }; + lm77@48 { + compatible = "national,lm77"; + reg = <0x48>; + }; + ads1015@49 { + compatible = "ti,ads1015"; + reg = <0x49>; + }; + ads1015@4b { + compatible = "ti,ads1015"; + reg = <0x4b>; + }; + }; + + fpga1_video0 { + compatible = "gdsys,ihs_video_out"; + reg = <0x100 0x40>; + little-endian; + fpga_interrupts = <1 8>; /* VIDEO OSD */ + osd_base = <0x180>; + osd_buffer_base = <0x1000>; + spdif_audio_base = <0x1e0>; + video_index = <0>; + video_id = <4>; + fpga-force-pos-pol; + sync-source; + fpga-pb-pixels = <2730>; /* 8192 / 3 */ + fpga-ra-lines = <2>; + video_tx = <&fpga1_dp_video0>; + clk_gen = <&fpga1_video0_clkgen>; + ddc_ci = <&fpga1_dp_video0>; + }; + + fpga1_iic_video0 { + compatible = "gdsys,ihs_i2cmaster"; + reg = <0x1c0 0x10>; + little-endian; + fpga_interrupts = <6>; + #address-cells = <1>; + #size-cells = <0>; + + fpga1_video0_clkgen: fpga1_video0_clkgen { + compatible = "idt,ics8n3qv01"; + reg = <0x6e>; + channel = <4>; + }; + }; + + fpga1_axi_video0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "gdsys,ihs_axi"; + reg = <0x170 0x10>; + little-endian; + fpga_interrupts = <22>; + + fpga1_dp_video0: fpga1_dp_video0 { + compatible = "gdsys,logicore_dp_tx"; + reg = <0x44a10000 0x1000>; + little-endian; + redriver = <&fpga1_dp_video0_redriver>; + video_id = <4>; + }; + }; + + fpga1_video1 { + compatible = "gdsys,ihs_video_out"; + reg = <0x200 0x40>; + little-endian; + fpga_interrupts = <2 9>; /* VIDEO OSD */ + osd_base = <0x280>; + osd_buffer_base = <0x2000>; + spdif_audio_base = <0x2e0>; + video_index = <1>; + video_id = <5>; + fpga-force-pos-pol; + sync-source; + fpga-pb-pixels = <2730>; /* 8192 / 3 */ + fpga-ra-lines = <2>; + video_tx = <&fpga1_dp_video1>; + clk_gen = <&fpga1_video1_clkgen>; + ddc_ci = <&fpga1_dp_video1>; + }; + + fpga1_iic_video1 { + compatible = "gdsys,ihs_i2cmaster"; + reg = <0x2c0 0x10>; + little-endian; + fpga_interrupts = <7>; + #address-cells = <1>; + #size-cells = <0>; + + fpga1_video1_clkgen: fpga1_video1_clkgen { + compatible = "idt,ics8n3qv01"; + reg = <0x6e>; + channel = <5>; + }; + }; + + fpga1_axi_video1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "gdsys,ihs_axi"; + reg = <0x270 0x10>; + little-endian; + fpga_interrupts = <23>; + + fpga1_dp_video1: fpga1_dp_video1 { + compatible = "gdsys,logicore_dp_tx"; + reg = <0x44a10000 0x1000>; + little-endian; + redriver = <&fpga1_dp_video1_redriver>; + video_id = <5>; + }; + }; + + fpga1_iic_usb { + compatible = "gdsys,ihs_i2cmaster"; + reg = <0xb0 0x10>; + little-endian; + fpga_interrupts = <24>; + #address-cells = <1>; + #size-cells = <0>; + + pca9555@20 { + compatible = "nxp,pca9555"; + reg = <0x20>; + #gpio-cells = <2>; + gpio-controller; + }; + }; + + fpga1_ep0 { + compatible = "gdsys,io-endpoint"; + reg = < 0x020 0x10 + 0x320 0x10 + 0x340 0x10 + 0x360 0x10>; + little-endian; + irq-model-local; + fpga_interrupts = <12 13 14 15>; + pollcycle = <200>; + nprot_channel = <17>; + uart_line = <1>; + ep_index = <0>; + line_protocol = <1>; + }; + + fpga1_mdio { + compatible = "gdsys,ihs_mdiomaster"; + reg = <0x0058 0x10>; + little-endian; + fpga_interrupts = <16>; + #address-cells = <1>; + #size-cells = <0>; + + fpga1_phy0 { + compatible = "ethernet-phy-ieee802.3-c45"; + device_type ="ethernet-phy"; + reg = <0>; + }; + fpga1_phy1 { + compatible = "ethernet-phy-ieee802.3-c45"; + device_type ="ethernet-phy"; + reg = <1>; + }; + fpga1_phy2 { + compatible = "ethernet-phy-ieee802.3-c45"; + device_type ="ethernet-phy"; + reg = <2>; + }; + fpga1_phy3 { + compatible = "ethernet-phy-ieee802.3-c45"; + device_type ="ethernet-phy"; + reg = <3>; + }; + }; + + }; + +}; diff --git a/arch/powerpc/dts/gdsys/gazerbeam-base.dtsi b/arch/powerpc/dts/gdsys/gazerbeam-base.dtsi new file mode 100644 index 0000000000..aca05f2cd0 --- /dev/null +++ b/arch/powerpc/dts/gdsys/gazerbeam-base.dtsi @@ -0,0 +1,185 @@ +/* + * Gazerbeam Device Tree Source + * + * (C) Copyright 2015 + * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +/ { + model = "gdsys,gazerbeam"; + compatible = "fsl,mpc8308rdb"; + + aliases { + ethernet0 = &enet0; + ethernet1 = &enet1; + }; + + memory { + device_type = "memory"; + }; +}; + +&enet1 { + status = "okay"; +}; + +&IIC { + fsl,preserve-clocking; + + at97sc3205t@29 { + compatible = "atmel,at97sc3204t"; + reg = <0x29>; + }; + + lm77@48 { + compatible = "national,lm77"; + reg = <0x48>; + }; + + ads1015@49 { + compatible = "ti,ads1015"; + reg = <0x49>; + }; + + lm77@4a { + compatible = "national,lm77"; + reg = <0x4a>; + }; + + emc2305@2e { + compatible = "smsc,emc2305"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2e>; + fan@0 { + reg = <0>; + }; + fan@1 { + reg = <1>; + }; + fan@2 { + reg = <2>; + }; + fan@3 { + reg = <3>; + }; + fan@4 { + reg = <4>; + }; + }; + + emc2305@4c { + compatible = "smsc,emc2305"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x4c>; + fan@0 { + reg = <0>; + }; + fan@1 { + reg = <1>; + }; + fan@2 { + reg = <2>; + }; + fan@3 { + reg = <3>; + }; + fan@4 { + reg = <4>; + }; + }; + + at24c512@54 { + compatible = "atmel,24c512"; + reg = <0x54>; + }; + + /* PPC-Board */ + pca9698@22 { + compatible = "nxp,pca9698"; + reg = <0x22>; + #gpio-cells = <2>; + gpio-controller; + }; + + /* IO-Board */ + pca9698@20 { + compatible = "nxp,pca9698"; + reg = <0x20>; + #gpio-cells = <2>; + gpio-controller; + }; +}; + +&IIC2 { + fsl,preserve-clocking; + + status = "okay"; + + /* MC2/SC-Board */ + GPIO_VB0: pca9698@20 { + compatible = "nxp,pca9698"; + reg = <0x20>; + #gpio-cells = <2>; + gpio-controller; + }; + + /* MC4-Board */ + GPIO_VB1: pca9698@22 { + compatible = "nxp,pca9698"; + reg = <0x22>; + #gpio-cells = <2>; + gpio-controller; + }; +}; + +&SPI { + gpios = < /*SPI-CSS-FPGA-U-FLASH#*/ &gpio0 8 0 + /*SPI-CSS-FPGA-O-FLASH#*/ &gpio0 6 0 + /*SPI-CSS-STDP1_U-FLASH#*/ &gpio0 12 0 + /*SPI-CSS-STDP2_U-FLASH#*/ &gpio0 11 0 + /*SPI-CSS-STDP1_O-FLASH#*/ &gpio0 15 0 + /*SPI-CSS-STDP2_O-FLASH#*/ &gpio0 3 0>; + + m25p16@0 { + compatible = "st,n25q128a11"; + reg = <0x0>; + spi-max-frequency = <20000000>; + }; + + m25p16@1 { + compatible = "st,n25q128a11"; + reg = <0x1>; + spi-max-frequency = <20000000>; + }; + + m25p16@2 { + compatible = "st,m25p40"; + reg = <0x2>; + spi-max-frequency = <20000000>; + }; + + m25p16@3 { + compatible = "st,m25p40"; + reg = <0x3>; + spi-max-frequency = <20000000>; + }; + + m25p16@4 { + compatible = "st,m25p40"; + reg = <0x4>; + spi-max-frequency = <20000000>; + }; + + m25p16@5 { + compatible = "st,m25p40"; + reg = <0x5>; + spi-max-frequency = <20000000>; + }; +}; diff --git a/arch/powerpc/dts/gdsys/mpc8308.dtsi b/arch/powerpc/dts/gdsys/mpc8308.dtsi new file mode 100644 index 0000000000..23e7403d91 --- /dev/null +++ b/arch/powerpc/dts/gdsys/mpc8308.dtsi @@ -0,0 +1,354 @@ +/* + * Basic platform for gdsys mpc8308 based devices + * + * (C) Copyright 2014 + * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de + * + * based on mpc8308rdb + * Copyright 2009 Freescale Semiconductor Inc. + * Copyright 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +/dts-v1/; + +#include + +/ { + compatible = "fsl,mpc8308rdb"; + + #address-cells = <1>; + #size-cells = <1>; + + aliases { + serial0 = &serial0; + serial1 = &serial1; + }; + + memory { + device_type = "memory"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + PowerPC,8308@0 { + device_type = "cpu"; + reg = <0x0>; + d-cache-line-size = <32>; + i-cache-line-size = <32>; + d-cache-size = <16384>; + i-cache-size = <16384>; + timebase-frequency = <0>; // from bootloader + bus-frequency = <0>; // from bootloader + clock-frequency = <0>; // from bootloader + }; + }; + + board_lbc: localbus@e0005000 { + #address-cells = <2>; + #size-cells = <1>; + compatible = "fsl,mpc8315-elbc", "fsl,elbc", "simple-bus"; + reg = <0xe0005000 0x1000>; + interrupts = <77 0x8>; + interrupt-parent = <&ipic>; + }; + + board_soc: immr@e0000000 { + #address-cells = <1>; + #size-cells = <1>; + device_type = "soc"; + compatible = "fsl,mpc8308-immr", "simple-bus"; + ranges = <0 0xe0000000 0x00100000>; + reg = <0xe0000000 0x00000200>; + bus-frequency = <0>; + + wdt@200 { + device_type = "watchdog"; + compatible = "mpc83xx_wdt"; + reg = <0x200 0x100>; + }; + + memory@2000 { + #address-cells = <2>; + #size-cells = <1>; + compatible = "fsl,mpc83xx-mem-controller"; + reg = <0x2000 0x1000>; + device_type = "memory"; + + driver_software_override = ; + p_impedance_override = ; + n_impedance_override = ; + odt_termination_value = ; + ddr_type = ; + + clock_adjust = ; + + read_to_write = <0>; + write_to_read = <0>; + read_to_read = <0>; + write_to_write = <0>; + active_powerdown_exit = <2>; + precharge_powerdown_exit = <6>; + odt_powerdown_exit = <8>; + mode_reg_set_cycle = <2>; + + precharge_to_activate = <2>; + activate_to_precharge = <6>; + activate_to_readwrite = <2>; + mcas_latency = ; + refresh_recovery = <17>; + last_data_to_precharge = <2>; + activate_to_activate = <2>; + last_write_data_to_read = <2>; + + additive_latency = <0>; + mcas_to_preamble_override = ; + write_latency = <3>; + read_to_precharge = <2>; + write_cmd_to_write_data = ; + minimum_cke_pulse_width = <3>; + four_activates_window = <5>; + + self_refresh = ; + sdram_type = ; + databus_width = ; + + force_self_refresh = ; + dll_reset = ; + dqs_config = ; + odt_config = ; + posted_refreshes = <1>; + + refresh_interval = <2084>; + precharge_interval = <256>; + + sdmode = <0x0242>; + esdmode = <0x0440>; + + ram@0 { + reg = <0x0 0x0 0x8000000>; + compatible = "nanya,nt5tu64m16hg"; + + odt_rd_cfg = ; + odt_wr_cfg = ; + bank_bits = <3>; + row_bits = <13>; + col_bits = <10>; + }; + }; + + IIC:i2c@3000 { + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + compatible = "fsl-i2c"; + reg = <0x3000 0x100>; + interrupts = <14 0x8>; + interrupt-parent = <&ipic>; + dfsrr; + }; + + IIC2: i2c@3100 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl-i2c"; + reg = <0x3100 0x100>; + interrupts = <15 0x8>; + interrupt-parent = <&ipic>; + dfsrr; + status = "disabled"; + }; + + SPI:spi@7000 { + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + compatible = "fsl,spi"; + reg = <0x7000 0x1000>; + interrupts = <16 0x8>; + interrupt-parent = <&ipic>; + mode = "cpu"; + }; + + sdhc@2e000 { + compatible = "fsl,esdhc", "fsl,mpc8308-esdhc"; + reg = <0x2e000 0x1000>; + interrupts = <42 0x8>; + interrupt-parent = <&ipic>; + sdhci,auto-cmd12; + /* Filled in by U-Boot */ + clock-frequency = <0>; + }; + + serial0: serial@4500 { + cell-index = <0>; + device_type = "serial"; + compatible = "fsl,ns16550", "ns16550"; + reg = <0x4500 0x100>; + clock-frequency = <133333333>; + interrupts = <9 0x8>; + interrupt-parent = <&ipic>; + }; + + serial1: serial@4600 { + cell-index = <1>; + device_type = "serial"; + compatible = "fsl,ns16550", "ns16550"; + reg = <0x4600 0x100>; + clock-frequency = <133333333>; + interrupts = <10 0x8>; + interrupt-parent = <&ipic>; + }; + + gpio0: gpio@c00 { + #gpio-cells = <2>; + device_type = "gpio"; + compatible = "fsl,mpc8308-gpio", "fsl,mpc8349-gpio"; + reg = <0xc00 0x18>; + interrupts = <74 0x8>; + interrupt-parent = <&ipic>; + gpio-controller; + }; + + /* IPIC + * interrupts cell = + * sense values match linux IORESOURCE_IRQ_* defines: + * sense == 8: Level, low assertion + * sense == 2: Edge, high-to-low change + */ + ipic: interrupt-controller@700 { + compatible = "fsl,ipic"; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <2>; + reg = <0x700 0x100>; + device_type = "ipic"; + }; + + ipic-msi@7c0 { + compatible = "fsl,ipic-msi"; + reg = <0x7c0 0x40>; + msi-available-ranges = <0x0 0x100>; + interrupts = < 0x43 0x8 + 0x4 0x8 + 0x51 0x8 + 0x52 0x8 + 0x56 0x8 + 0x57 0x8 + 0x58 0x8 + 0x59 0x8 >; + interrupt-parent = < &ipic >; + }; + + dma@2c000 { + compatible = "fsl,mpc8308-dma", "fsl,mpc5121-dma"; + reg = <0x2c000 0x1800>; + interrupts = <3 0x8 + 94 0x8>; + interrupt-parent = < &ipic >; + }; + + enet0: ethernet@24000 { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x24000 0x1000>; + + cell-index = <0>; + device_type = "network"; + model = "eTSEC"; + compatible = "gianfar", "fsl,tsec"; + reg = <0x24000 0x1000>; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <32 0x8 33 0x8 34 0x8>; + interrupt-parent = <&ipic>; + tbi-handle = < &tbi0 >; + phy-handle = < &phy1 >; + fsl,magic-packet; + + mdio@520 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,gianfar-mdio"; + reg = <0x520 0x20>; + phy1: ethernet-phy@1 { + reg = <0x1>; + }; + phy2: ethernet-phy@0 { + reg = <0x0>; + device_type = "ethernet-phy"; + }; + tbi0: tbi-phy@11 { + reg = <0x11>; + device_type = "tbi-phy"; + }; + }; + }; + + enet1: ethernet@25000 { + #address-cells = <1>; + #size-cells = <1>; + cell-index = <1>; + device_type = "network"; + model = "eTSEC"; + compatible = "gianfar", "fsl,tsec"; + reg = <0x25000 0x1000>; + ranges = <0x0 0x25000 0x1000>; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <35 0x8 36 0x8 37 0x8>; + interrupt-parent = <&ipic>; + phy-handle = < &phy2 >; + status = "disabled"; + + mdio@520 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,gianfar-tbi"; + reg = <0x520 0x20>; + tbi1: tbi-phy@11 { + reg = <0x11>; + device_type = "tbi-phy"; + }; + }; + }; + }; + + pci0: pcie@e0009000 { + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + device_type = "pci"; + compatible = "fsl,mpc8308-pcie", "fsl,mpc8314-pcie"; + reg = <0xe0009000 0x00001000 + 0xb0000000 0x01000000>; + ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x10000000 + 0x01000000 0 0x00000000 0xb1000000 0 0x00800000>; + bus-range = <0 0>; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = <0 0 0 1 &ipic 1 8 + 0 0 0 2 &ipic 1 8 + 0 0 0 3 &ipic 1 8 + 0 0 0 4 &ipic 1 8>; + interrupts = <0x1 0x8>; + interrupt-parent = <&ipic>; + clock-frequency = <0>; + + pcie@0 { + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + reg = <0 0 0 0 0>; + ranges = <0x02000000 0 0xa0000000 + 0x02000000 0 0xa0000000 + 0 0x10000000 + 0x01000000 0 0x00000000 + 0x01000000 0 0x00000000 + 0 0x00800000>; + }; + }; +}; diff --git a/arch/powerpc/dts/gdsys/soc/i2c/cirrus-audio-codec.dtsi b/arch/powerpc/dts/gdsys/soc/i2c/cirrus-audio-codec.dtsi new file mode 100644 index 0000000000..9787e09648 --- /dev/null +++ b/arch/powerpc/dts/gdsys/soc/i2c/cirrus-audio-codec.dtsi @@ -0,0 +1,6 @@ +&IIC { + cs4265@4f { + compatible = "cirrus,cs4265"; + reg = <0x0000004f>; + }; +}; diff --git a/arch/powerpc/dts/gdsys/soc/i2c/dallas-rtc.dtsi b/arch/powerpc/dts/gdsys/soc/i2c/dallas-rtc.dtsi new file mode 100644 index 0000000000..336bdcaf2e --- /dev/null +++ b/arch/powerpc/dts/gdsys/soc/i2c/dallas-rtc.dtsi @@ -0,0 +1,6 @@ +&IIC { + ds1339@68 { + compatible = "dallas,ds1339"; + reg = <0x68>; + }; +}; diff --git a/arch/powerpc/dts/gdsys/soc/lbc/gazerbeam.dtsi b/arch/powerpc/dts/gdsys/soc/lbc/gazerbeam.dtsi new file mode 100644 index 0000000000..5ff58c28e5 --- /dev/null +++ b/arch/powerpc/dts/gdsys/soc/lbc/gazerbeam.dtsi @@ -0,0 +1,5 @@ +&board_lbc { + ranges = <0x0 0x0 0xfe000000 0x00800000 + 0x1 0x0 0xe0600000 0x00003000 + 0x2 0x0 0xe0700000 0x00003000>; +}; diff --git a/arch/powerpc/dts/gdsys/soc/nor/flash-80k-partition.dtsi b/arch/powerpc/dts/gdsys/soc/nor/flash-80k-partition.dtsi new file mode 100644 index 0000000000..c6cc1409e0 --- /dev/null +++ b/arch/powerpc/dts/gdsys/soc/nor/flash-80k-partition.dtsi @@ -0,0 +1,20 @@ +&board_lbc { + flash@0,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "cfi-flash"; + reg = <0x0 0x0 0x100000>; + bank-width = <2>; + device-width = <1>; + + u-boot@0 { + reg = <0x0 0x80000>; + }; + env@80000 { + reg = <0x80000 0x10000>; + }; + env1@90000 { + reg = <0x90000 0x10000>; + }; + }; +}; From d85c385332b7f9bf0491c7fc201ef6abf0b66938 Mon Sep 17 00:00:00 2001 From: Mario Six Date: Fri, 29 Mar 2019 10:18:18 +0100 Subject: [PATCH 85/86] gazerbeam: Add u-boot specific dts include file Add a U-Boot specific dts file, which encapsulates the needed modifications to the Gazerbeam Linux device tree. Signed-off-by: Mario Six --- arch/powerpc/dts/gazerbeam.dts | 2 + arch/powerpc/dts/gdsys/gazerbeam-uboot.dtsi | 250 ++++++++++++++++++++ 2 files changed, 252 insertions(+) create mode 100644 arch/powerpc/dts/gdsys/gazerbeam-uboot.dtsi diff --git a/arch/powerpc/dts/gazerbeam.dts b/arch/powerpc/dts/gazerbeam.dts index a4408c496c..5d171519e0 100644 --- a/arch/powerpc/dts/gazerbeam.dts +++ b/arch/powerpc/dts/gazerbeam.dts @@ -598,3 +598,5 @@ }; }; + +#include "gdsys/gazerbeam-uboot.dtsi" diff --git a/arch/powerpc/dts/gdsys/gazerbeam-uboot.dtsi b/arch/powerpc/dts/gdsys/gazerbeam-uboot.dtsi new file mode 100644 index 0000000000..1c4977f20f --- /dev/null +++ b/arch/powerpc/dts/gdsys/gazerbeam-uboot.dtsi @@ -0,0 +1,250 @@ +#include +#include + +/ { + aliases { + i2c0 = &IIC; + i2c1 = &IIC2; + i2c2 = "/fpga0bus/fpga0_iic_main"; + i2c3 = "/fpga0bus/fpga0_iic_video0"; + i2c4 = "/fpga0bus/fpga0_iic_video1"; + i2c5 = "/fpga0bus/fpga0_iic_usb"; + gdsys_soc0 = "/fpga0bus"; + gdsys_soc1 = "/fpga1bus"; + ioep0 = "/fpga0bus/fpga0_ep0"; + ioep1 = "/fpga0bus/fpga1_ep0"; + }; + + chosen { + stdout-path = &serial1; + }; + + cpus { + compatible = "cpu_bus"; + u-boot,dm-pre-reloc; + + PowerPC,8308@0 { + compatible = "fsl,mpc8308"; + clocks = <&socclocks MPC83XX_CLK_CORE + &socclocks MPC83XX_CLK_CSB>; + u-boot,dm-pre-reloc; + }; + }; + + board { + compatible = "gdsys,board_gazerbeam"; + csb = <&board_soc>; + serdes = <&SERDES>; + rxaui0 = <&RXAUI0_0>; + rxaui1 = <&RXAUI0_1>; + rxaui2 = <&RXAUI0_2>; + rxaui3 = <&RXAUI0_3>; + rxaui4 = <&RXAUI1_0>; + rxaui5 = <&RXAUI1_1>; + rxaui6 = <&RXAUI1_2>; + rxaui7 = <&RXAUI1_3>; + fpga0 = <&FPGA0>; + fpga1 = <&FPGA1>; + ioep0 = <&IOEP0>; + ioep1 = <&IOEP1>; + + ver-gpios = <&PPCPCA 12 0 + &PPCPCA 13 0 + &PPCPCA 14 0 + &PPCPCA 15 0>; + + /* MC2/SC-Board */ + var-gpios-mc2 = <&GPIO_VB0 0 0 /* VAR-MC_SC */ + &GPIO_VB0 11 0>; /* VAR-CON */ + /* MC4-Board */ + var-gpios-mc4 = <&GPIO_VB1 0 0 /* VAR-MC_SC */ + &GPIO_VB1 11 0>; /* VAR-CON */ + + reset-gpios = <&gpio0 1 0 &gpio0 2 1>; + }; + + socclocks: clocks { + compatible = "fsl,mpc8308-clk"; + #clock-cells = <1>; + u-boot,dm-pre-reloc; + }; + + timer { + compatible = "fsl,mpc83xx-timer"; + clocks = <&socclocks MPC83XX_CLK_CSB>; + }; +}; + +&FPGA0 { + reset-gpios = <&PPCPCA 26 0>; + done-gpios = <&GPIO_VB0 19 0>; +}; + +&FPGA1 { + status = "disable"; +}; + +&FPGA0BUS { + ranges = <0x0 0xe0600000 0x00004000>; + fpga = <&FPGA0>; + + fpga0_video0 { + mode = "640_480_60"; + + status = "disabled"; + }; + + RXAUI0_0: fpga0_rxaui@fc0 { + compatible = "gdsys,rxaui_ctrl"; + reg = <0x0fc0 0x10>; + }; + + fpga0_iic_video0 { + status = "disabled"; + }; + + fpga0_axi_video0 { + status = "disabled"; + }; + + fpga0_video1 { + mode = "640_480_60"; + status = "disabled"; + }; + + fpga0_iic_video1 { + status = "disabled"; + }; + + fpga0_axi_video1 { + status = "disabled"; + }; + + IOEP0: fpga0_ep0 { + }; + + RXAUI0_1: fpga0_rxaui@fd0 { + compatible = "gdsys,rxaui_ctrl"; + reg = <0x0fd0 0x10>; + }; + + RXAUI0_2: fpga0_rxaui@fe0 { + compatible = "gdsys,rxaui_ctrl"; + reg = <0x0fe0 0x10>; + }; + + RXAUI0_3: fpga0_rxaui@ff0 { + compatible = "gdsys,rxaui_ctrl"; + reg = <0x0ff0 0x10>; + }; +}; + +&FPGA1BUS { + ranges = <0x0 0xe0700000 0x00004000>; + fpga = <&FPGA1>; + + status = "disable"; + + fpga1_video0 { + mode = "640_480_60"; + }; + + RXAUI1_0: fpga0_rxaui@fc0 { + compatible = "gdsys,rxaui_ctrl"; + reg = <0x0fc0 0x10>; + }; + + fpga1_video1 { + mode = "640_480_60"; + }; + + IOEP1: fpga1_ep0 { + }; + + RXAUI1_1: fpga0_rxaui@fd0 { + compatible = "gdsys,rxaui_ctrl"; + reg = <0x0fd0 0x10>; + }; + + RXAUI1_2: fpga0_rxaui@fe0 { + compatible = "gdsys,rxaui_ctrl"; + reg = <0x0fe0 0x10>; + }; + + RXAUI1_3: fpga0_rxaui@ff0 { + compatible = "gdsys,rxaui_ctrl"; + reg = <0x0ff0 0x10>; + }; +}; + +&board_soc { + u-boot,dm-pre-reloc; + clocks = <&socclocks MPC83XX_CLK_CSB>; + + memory@2000 { + u-boot,dm-pre-reloc; + }; + + sdhc@2e000 { + clocks = <&socclocks MPC83XX_CLK_SDHC>; + clock-names = "per"; + }; + + SERDES: serdes@e3000 { + reg = <0xe3000 0x200>; + compatible = "fsl,mpc83xx-serdes"; + proto = "pex"; + serdes-clk = <100>; + vdd; + }; +}; + +&IIC { + clocks = <&socclocks MPC83XX_CLK_I2C1>; + + PPCPCA: pca9698@20 { + label = "ppc"; + }; + + IOPCA: pca9698@22 { + label = "io"; + }; + + at97sc3205t@29 { + u-boot,i2c-offset-len = <0>; + }; +}; + +&IIC2 { + clocks = <&socclocks MPC83XX_CLK_I2C2>; + + GPIO_VB0: pca9698@20 { + label = "mc2-sc"; + }; + + GPIO_VB1: pca9698@22 { + label = "mc4"; + }; +}; + +&board_soc { + u-boot,dm-pre-reloc; +}; + +&GPIO_VB0 { + u-boot,dm-pre-reloc; +}; + +&serial0 { + clocks = <&socclocks MPC83XX_CLK_CSB>; + u-boot,dm-pre-reloc; +}; + +&serial1 { + clocks = <&socclocks MPC83XX_CLK_CSB>; + u-boot,dm-pre-reloc; +}; + +&pci0 { + clocks = <&socclocks MPC83XX_CLK_PCIEXP1>; +}; From d494cdb97e18a30214d0414376d4eacdf82224fe Mon Sep 17 00:00:00 2001 From: Dirk Eibach Date: Fri, 29 Mar 2019 10:18:19 +0100 Subject: [PATCH 86/86] mpc83xx: Add gazerbeam board The gdsys gazerbeam board is based on a Freescale MPC8308 SOC. It boots from NOR-Flash, kernel and rootfs are stored on SD-Card. On board peripherals include: - 2x 10/100 Mbit/s Ethernet (optional) Signed-off-by: Dirk Eibach Signed-off-by: Mario Six --- arch/powerpc/cpu/mpc83xx/Kconfig | 19 +++ arch/powerpc/dts/gazerbeam.dts | 2 +- board/gdsys/common/Makefile | 1 + board/gdsys/mpc8308/Kconfig | 29 ++++- board/gdsys/mpc8308/MAINTAINERS | 2 + board/gdsys/mpc8308/Makefile | 1 + board/gdsys/mpc8308/gazerbeam.c | 179 ++++++++++++++++++++++++++++ configs/gazerbeam_defconfig | 196 +++++++++++++++++++++++++++++++ include/configs/gazerbeam.h | 137 +++++++++++++++++++++ 9 files changed, 564 insertions(+), 2 deletions(-) create mode 100644 board/gdsys/mpc8308/gazerbeam.c create mode 100644 configs/gazerbeam_defconfig create mode 100644 include/configs/gazerbeam.h diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index fe20e85086..b99288aa83 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -175,6 +175,25 @@ config TARGET_STRIDER select SYS_FSL_ERRATUM_ESDHC111 imply CMD_PCA953X +config TARGET_GAZERBEAM + bool "Support gazerbeam" + select ARCH_MPC8308 + select SYS_FSL_ERRATUM_ESDHC111 + imply ENV_IS_IN_FLASH + help + The "Gazerbeam" is a modular system by Guntermann & Drunck GmbH + Systementwicklung based on the NXP MPC8308 SoC for usage in KVM + appliances. + + Features include: + * Two gigabit ethernet ports + * Multiple USB ports (depending on variant) + * Several gigabit ethernet or optical fiber ports (depending on + variant) + * Several display port inputs and outputs, and supporting redrivers + (depending on variant) + * Several FPGAs with custom logic (depending on variant) + endchoice config MPC83XX_QUICC_ENGINE diff --git a/arch/powerpc/dts/gazerbeam.dts b/arch/powerpc/dts/gazerbeam.dts index 5d171519e0..96c03c77ae 100644 --- a/arch/powerpc/dts/gazerbeam.dts +++ b/arch/powerpc/dts/gazerbeam.dts @@ -10,7 +10,7 @@ * option) any later version. */ -/include/ "gdsys/mpc8308.dtsi" +#include "gdsys/mpc8308.dtsi" /include/ "gdsys/gazerbeam-base.dtsi" diff --git a/board/gdsys/common/Makefile b/board/gdsys/common/Makefile index ff8d6f4966..7dfe104561 100644 --- a/board/gdsys/common/Makefile +++ b/board/gdsys/common/Makefile @@ -11,6 +11,7 @@ obj-$(CONFIG_TARGET_STRIDER) += mclink.o dp501.o phy.o ioep-fpga.o adv7611.o ch7 obj-$(CONFIG_TARGET_STRIDER) += fanctrl.o obj-$(CONFIG_STRIDER_CON) += osd.o obj-$(CONFIG_STRIDER_CON_DP) += osd.o +obj-$(CONFIG_TARGET_GAZERBEAM) += osd.o ihs_mdio.o ioep-fpga.o ifdef CONFIG_OSD obj-$(CONFIG_GDSYS_LEGACY_OSD_CMDS) += osd_cmd.o diff --git a/board/gdsys/mpc8308/Kconfig b/board/gdsys/mpc8308/Kconfig index e6a4796054..30811889fb 100644 --- a/board/gdsys/mpc8308/Kconfig +++ b/board/gdsys/mpc8308/Kconfig @@ -71,7 +71,28 @@ config GDSYS_LEGACY_DRIVERS endif -if TARGET_HRCON || TARGET_STRIDER +if TARGET_GAZERBEAM + +config SYS_BOARD + default "mpc8308" + +config SYS_VENDOR + default "gdsys" + +config SYS_CONFIG_NAME + default "gazerbeam" + +config SYS_FPGA1_BASE + default E0700000 + +config SYS_FPGA1_SIZE + default 1 + +config GDSYS_LEGACY_OSD_CMDS + default y +endif + +if TARGET_HRCON || TARGET_STRIDER || TARGET_GAZERBEAM choice prompt "FPGA flavor selection" @@ -89,6 +110,12 @@ config SYS_FPGA_FLAVOR_GAZERBEAM endchoice +config EXTENDED_FEATURES + bool "FPGA extended features" + depends on GDSYS_LEGACY_DRIVERS + help + Enable support for the extended features field of the IHS FPGA. + config CMD_IOLOOP bool "Enable 'ioloop' and 'ioreflect' commands" help diff --git a/board/gdsys/mpc8308/MAINTAINERS b/board/gdsys/mpc8308/MAINTAINERS index 755b9a2385..ed1b6fa106 100644 --- a/board/gdsys/mpc8308/MAINTAINERS +++ b/board/gdsys/mpc8308/MAINTAINERS @@ -6,7 +6,9 @@ F: include/configs/hrcon.h F: configs/hrcon_defconfig F: configs/hrcon_dh_defconfig F: include/configs/strider.h +F: configs/strider_defconfig F: configs/strider_cpu_defconfig F: configs/strider_cpu_dp_defconfig F: configs/strider_con_defconfig F: configs/strider_con_dp_defconfig +F: configs/gazerbeam_defconfig diff --git a/board/gdsys/mpc8308/Makefile b/board/gdsys/mpc8308/Makefile index dc579479f9..9af5fe04d1 100644 --- a/board/gdsys/mpc8308/Makefile +++ b/board/gdsys/mpc8308/Makefile @@ -6,3 +6,4 @@ obj-y := mpc8308.o sdram.o obj-$(CONFIG_TARGET_HRCON) += hrcon.o obj-$(CONFIG_TARGET_STRIDER) += strider.o +obj-$(CONFIG_TARGET_GAZERBEAM) += gazerbeam.o diff --git a/board/gdsys/mpc8308/gazerbeam.c b/board/gdsys/mpc8308/gazerbeam.c new file mode 100644 index 0000000000..cd621744d2 --- /dev/null +++ b/board/gdsys/mpc8308/gazerbeam.c @@ -0,0 +1,179 @@ +/* + * (C) Copyright 2015 + * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../common/ihs_mdio.h" +#include "../../../drivers/board/gazerbeam.h" + +DECLARE_GLOBAL_DATA_PTR; + +struct ihs_mdio_info ihs_mdio_info[] = { + { .fpga = NULL, .name = "ihs0", .base = 0x58 }, + { .fpga = NULL, .name = "ihs1", .base = 0x58 }, +}; + +static int get_tpm(struct udevice **devp) +{ + int rc; + + rc = uclass_first_device_err(UCLASS_TPM, devp); + if (rc) { + printf("Could not find TPM (ret=%d)\n", rc); + return CMD_RET_FAILURE; + } + + return 0; +} + +int board_early_init_r(void) +{ + struct udevice *board; + struct udevice *serdes; + int mc = 0; + int con = 0; + + if (board_get(&board)) + puts("Could not find board information device.\n"); + + /* Initialize serdes */ + uclass_get_device_by_phandle(UCLASS_MISC, board, "serdes", &serdes); + + if (board_detect(board)) + puts("Device information detection failed.\n"); + + board_get_int(board, BOARD_MULTICHANNEL, &mc); + board_get_int(board, BOARD_VARIANT, &con); + + if (mc == 2 || mc == 1) + dev_disable_by_path("/immr@e0000000/i2c@3100/pca9698@22"); + + if (mc == 4) { + dev_disable_by_path("/immr@e0000000/i2c@3100/pca9698@20"); + dev_enable_by_path("/localbus@e0005000/iocon_uart@2,0"); + dev_enable_by_path("/fpga1bus"); + } + + if (mc == 2 || con == VAR_CON) { + dev_enable_by_path("/fpga0bus/fpga0_video1"); + dev_enable_by_path("/fpga0bus/fpga0_iic_video1"); + dev_enable_by_path("/fpga0bus/fpga0_axi_video1"); + } + + if (con == VAR_CON) { + dev_enable_by_path("/fpga0bus/fpga0_video0"); + dev_enable_by_path("/fpga0bus/fpga0_iic_video0"); + dev_enable_by_path("/fpga0bus/fpga0_axi_video0"); + } + + return 0; +} + +int checkboard(void) +{ + struct udevice *board; + char *s = env_get("serial#"); + int mc = 0; + int con = 0; + + if (board_get(&board)) + puts("Could not find board information device.\n"); + + board_get_int(board, BOARD_MULTICHANNEL, &mc); + board_get_int(board, BOARD_VARIANT, &con); + + puts("Board: Gazerbeam "); + printf("%s ", mc == 4 ? "MC4" : mc == 2 ? "MC2" : "SC"); + printf("%s", con == VAR_CON ? "CON" : "CPU"); + + if (s) { + puts(", serial# "); + puts(s); + } + + puts("\n"); + + return 0; +} + +static void display_osd_info(struct udevice *osd, + struct video_osd_info *osd_info) +{ + printf("OSD-%s: Digital-OSD version %01d.%02d, %d x %d characters\n", + osd->name, osd_info->major_version, osd_info->minor_version, + osd_info->width, osd_info->height); +} + +int last_stage_init(void) +{ + int fpga_hw_rev = 0; + int i; + struct udevice *board; + struct udevice *osd; + struct video_osd_info osd_info; + struct udevice *tpm; + int ret; + + if (board_get(&board)) + puts("Could not find board information device.\n"); + + if (board) { + int res = board_get_int(board, BOARD_HWVERSION, &fpga_hw_rev); + + if (res) + printf("Could not determind FPGA HW revision (res = %d)\n", res); + } + + env_set_ulong("fpga_hw_rev", fpga_hw_rev); + + ret = get_tpm(&tpm); + if (ret || tpm_init(tpm) || tpm_startup(tpm, TPM_ST_CLEAR) || + tpm_continue_self_test(tpm)) { + printf("TPM init failed\n"); + } + + if (fpga_hw_rev >= 4) { + for (i = 0; i < 4; i++) { + struct udevice *rxaui; + char name[8]; + + snprintf(name, sizeof(name), "rxaui%d", i); + /* Disable RXAUI polarity inversion */ + ret = uclass_get_device_by_phandle(UCLASS_MISC, board, name, &rxaui); + if (!ret) + misc_set_enabled(rxaui, false); + } + } + + for (uclass_first_device(UCLASS_VIDEO_OSD, &osd); + osd; + uclass_next_device(&osd)) { + video_osd_get_info(osd, &osd_info); + display_osd_info(osd, &osd_info); + } + + return 0; +} + +#if defined(CONFIG_OF_BOARD_SETUP) +int ft_board_setup(void *blob, bd_t *bd) +{ + ft_cpu_setup(blob, bd); + fsl_fdt_fixup_dr_usb(blob, bd); + fdt_fixup_esdhc(blob, bd); + + return 0; +} +#endif diff --git a/configs/gazerbeam_defconfig b/configs/gazerbeam_defconfig new file mode 100644 index 0000000000..346b1b2eaa --- /dev/null +++ b/configs/gazerbeam_defconfig @@ -0,0 +1,196 @@ +CONFIG_PPC=y +CONFIG_SYS_TEXT_BASE=0xFE000000 +CONFIG_SYS_MALLOC_F_LEN=0x600 +CONFIG_IDENT_STRING=" gazerbeam 0.01" +CONFIG_SYS_CLK_FREQ=33333333 +CONFIG_MPC83xx=y +CONFIG_TARGET_GAZERBEAM=y +CONFIG_SYSTEM_PLL_VCO_DIV_2=y +CONFIG_SYSTEM_PLL_FACTOR_4_1=y +CONFIG_CORE_PLL_RATIO_3_1=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_TSEC1_MODE_RGMII=y +CONFIG_TSEC2_MODE_RGMII=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="SDRAM" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_128_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT1=y +CONFIG_BAT1_NAME="IMMR" +CONFIG_BAT1_BASE=0xE0000000 +CONFIG_BAT1_LENGTH_8_MBYTES=y +CONFIG_BAT1_ACCESS_RW=y +CONFIG_BAT1_ICACHE_INHIBITED=y +CONFIG_BAT1_ICACHE_GUARDED=y +CONFIG_BAT1_DCACHE_INHIBITED=y +CONFIG_BAT1_DCACHE_GUARDED=y +CONFIG_BAT1_USER_MODE_VALID=y +CONFIG_BAT1_SUPERVISOR_MODE_VALID=y +CONFIG_BAT2=y +CONFIG_BAT2_NAME="FLASH" +CONFIG_BAT2_BASE=0xFE000000 +CONFIG_BAT2_LENGTH_8_MBYTES=y +CONFIG_BAT2_ACCESS_RW=y +CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT2_DCACHE_INHIBITED=y +CONFIG_BAT2_DCACHE_GUARDED=y +CONFIG_BAT2_USER_MODE_VALID=y +CONFIG_BAT2_SUPERVISOR_MODE_VALID=y +CONFIG_BAT3=y +CONFIG_BAT3_NAME="INIT_RAM" +CONFIG_BAT3_BASE=0xE6000000 +CONFIG_BAT3_ACCESS_RW=y +CONFIG_BAT3_USER_MODE_VALID=y +CONFIG_BAT3_SUPERVISOR_MODE_VALID=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xFE000000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_8_MBYTES=y +CONFIG_LBLAW1=y +CONFIG_LBLAW1_BASE=0xE0600000 +CONFIG_LBLAW1_NAME="FPGA0" +CONFIG_LBLAW1_LENGTH_1_MBYTES=y +CONFIG_LBLAW2=y +CONFIG_LBLAW2_BASE=0xE0700000 +CONFIG_LBLAW2_NAME="FPGA1" +CONFIG_LBLAW2_LENGTH_1_MBYTES=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_8_MBYTES=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="FPGA0" +CONFIG_BR1_OR1_BASE=0xE0600000 +CONFIG_BR1_PORTSIZE_16BIT=y +CONFIG_OR1_AM_1_MBYTES=y +CONFIG_OR1_SCY_5=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="FPGA1" +CONFIG_BR2_OR2_BASE=0xE0700000 +CONFIG_BR2_PORTSIZE_16BIT=y +CONFIG_OR2_AM_1_MBYTES=y +CONFIG_OR2_SCY_5=y +CONFIG_OR2_CSNT_EARLIER=y +CONFIG_HID0_FINAL_EMCP=y +CONFIG_HID0_FINAL_DPM=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y +CONFIG_SICR_ETSEC1_A_TSEC_GTX_CLK125=y +CONFIG_SICR_GPIO_A_TSEC2=y +CONFIG_SICR_GPIO_B_TSEC_GTX_CLK125=y +CONFIG_SICR_IEEE1588_A_GPIO=y +CONFIG_SICR_GTM_GPIO=y +CONFIG_SICR_ETSEC2_GPIO=y +CONFIG_SICR_GPIOSEL_IEEE1588=y +CONFIG_SICR_TMSOBI1_2_5_V=y +CONFIG_SICR_TMSOBI2_2_5_V=y +CONFIG_ACR_PIPE_DEP_4=y +CONFIG_ACR_RPTCNT_4=y +CONFIG_SPCR_TSECEP_3=y +CONFIG_LCRR_DBYP_PLL_BYPASSED=y +CONFIG_LCRR_CLKDIV_2=y +CONFIG_SYS_FPGA_FLAVOR_GAZERBEAM=y +CONFIG_CMD_IOLOOP=y +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_BOOTDELAY=5 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_INFO_QUIET=y +CONFIG_DISPLAY_CPUINFO=y +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_BOARD_EARLY_INIT_R=y +CONFIG_LAST_STAGE_INIT=y +CONFIG_HUSH_PARSER=y +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_STOP_STR=" " +CONFIG_CMD_CPU=y +CONFIG_CMD_BINOP=y +CONFIG_CMD_MEMTEST=y +CONFIG_SYS_ALT_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_AXI=y +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_NFS is not set +CONFIG_CMD_MII=y +CONFIG_CMD_MII_DRIVER=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_HASH=y +CONFIG_CMD_TPM=y +CONFIG_CMD_EXT2=y +CONFIG_DOS_PARTITION=y +CONFIG_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_DEFAULT_DEVICE_TREE="gazerbeam" +CONFIG_DM=y +CONFIG_REGMAP=y +CONFIG_AXI=y +CONFIG_IHS_AXI=y +CONFIG_CLK=y +CONFIG_ICS8N3QV01=y +CONFIG_CPU=y +CONFIG_CPU_MPC83XX=y +CONFIG_BOARD=y +CONFIG_BOARD_GAZERBEAM=y +CONFIG_DM_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_MPC8XXX_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_I2C_IHS=y +CONFIG_MISC=y +CONFIG_GDSYS_RXAUI_CTRL=y +CONFIG_GDSYS_IOEP=y +CONFIG_MPC83XX_SERDES=y +CONFIG_GDSYS_SOC=y +CONFIG_IHS_FPGA=y +CONFIG_DM_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_MTD=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_CFI_DRIVER=y +CONFIG_CFI_FLASH=y +CONFIG_SYS_FLASH_PROTECTION=y +CONFIG_SYS_FLASH_CFI=y +CONFIG_PHYLIB_10G=y +CONFIG_PHY_MARVELL=y +CONFIG_DM_ETH=y +CONFIG_TSEC_ENET=y +# CONFIG_PCI is not set +CONFIG_RAM=y +CONFIG_MPC83XX_SDRAM=y +CONFIG_DM_RESET=y +CONFIG_DM_SERIAL=y +CONFIG_SYS_NS16550=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_MCP83XX=y +CONFIG_TIMER=y +CONFIG_MPC83XX_TIMER=y +CONFIG_TPM_ATMEL_TWI=y +CONFIG_TPM_AUTH_SESSIONS=y +# CONFIG_TPM_V2 is not set +CONFIG_DM_VIDEO=y +CONFIG_DISPLAY=y +CONFIG_LOGICORE_DP_TX=y +CONFIG_OSD=y +CONFIG_IHS_VIDEO_OUT=y +CONFIG_TPM=y diff --git a/include/configs/gazerbeam.h b/include/configs/gazerbeam.h new file mode 100644 index 0000000000..11d367a151 --- /dev/null +++ b/include/configs/gazerbeam.h @@ -0,0 +1,137 @@ +/* + * (C) Copyright 2015 + * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de + * + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * DDR Setup + */ +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ +/* TODO: Check: Can this be unified with CONFIG_SYS_SDRAM_BASE? */ +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE + +/* + * Memory test + * TODO: Migrate! + */ +#define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */ +#define CONFIG_SYS_MEMTEST_END 0x07e00000 + +/* + * The reserved memory + */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ + +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ +#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ + +/* + * Initial RAM Base Address Setup + */ +#define CONFIG_SYS_INIT_RAM_LOCK +#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ +#define CONFIG_SYS_GBL_DATA_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) + +/* + * FLASH on the Local Bus + */ +#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ +#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */ + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 135 + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +/* + * Environment + */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ + CONFIG_SYS_MONITOR_LEN) +#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE + +#define CONFIG_LOADS_ECHO /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ + +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +/* + * For booting Linux, the board info and command line data + * have to be in the first 256 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ + +/* + * Environment Configuration + */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_HAS_ETH0 +#define CONFIG_HAS_ETH1 + +#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ + +/* TODO: Turn into string option and migrate to Kconfig */ +#define CONFIG_HOSTNAME "gazerbeam" +#define CONFIG_ROOTPATH "/opt/nfsroot" +#define CONFIG_BOOTFILE "uImage" + +#define CONFIG_PREBOOT /* enable preboot variable */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "consoledev=ttyS1\0" \ + "u-boot=u-boot.bin\0" \ + "kernel_addr=1000000\0" \ + "fdt_addr=C00000\0" \ + "fdtfile=hrcon.dtb\0" \ + "load=tftp ${loadaddr} ${u-boot}\0" \ + "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \ + " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\ + " +${filesize};cp.b ${fileaddr} " \ + __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \ + "upd=run load update\0" \ + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp ${kernel_addr} $bootfile;" \ + "tftp ${fdt_addr} $fdtfile;" \ + "bootm ${kernel_addr} - ${fdt_addr}" + +#define CONFIG_MMCBOOTCOMMAND \ + "setenv bootargs root=/dev/mmcblk0p3 rw rootwait " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "ext2load mmc 0:2 ${kernel_addr} $bootfile;" \ + "ext2load mmc 0:2 ${fdt_addr} $fdtfile;" \ + "bootm ${kernel_addr} - ${fdt_addr}" + +#define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND + +#endif /* __CONFIG_H */