From 8439219ca5313f2fabf13fcf4cb69a8852b8d4a2 Mon Sep 17 00:00:00 2001 From: Tony Dinh Date: Thu, 12 Aug 2021 14:33:34 -0700 Subject: [PATCH 01/10] arm: kirkwood: Sheevaplug: Update board maintainer Change maintainer to me. Prafulla is no longer active in U-Boot community. Signed-off-by: Tony Dinh Reviewed-by: Stefan Roese --- board/Marvell/sheevaplug/MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/Marvell/sheevaplug/MAINTAINERS b/board/Marvell/sheevaplug/MAINTAINERS index 2b0103d07d..282f046667 100644 --- a/board/Marvell/sheevaplug/MAINTAINERS +++ b/board/Marvell/sheevaplug/MAINTAINERS @@ -1,5 +1,5 @@ SHEEVAPLUG BOARD -M: Prafulla Wadaskar +M: Tony Dinh S: Maintained F: board/Marvell/sheevaplug/ F: include/configs/sheevaplug.h From 88426bd6b08e42ce3ca2b1b9c3e11e5c390c3020 Mon Sep 17 00:00:00 2001 From: Sven Auhagen Date: Tue, 24 Aug 2021 10:14:25 +0200 Subject: [PATCH 02/10] arm: mvebu: dts: Armada8k enable mdio Since mvpp2 is using the new mdio driver and the cp110 has been synced with the linux upstream, the mdio has to enabled in the device tree file. This is missing for some device tree files and therefore the network cards do not come online. Signed-off-by: Sven Auhagen Reviewed-by: Stefan Roese --- arch/arm/dts/armada-7040-db.dts | 1 + arch/arm/dts/armada-8040-clearfog-gt-8k.dts | 1 + arch/arm/dts/armada-8040-db.dts | 1 + arch/arm/dts/armada-8040-mcbin.dts | 1 + 4 files changed, 4 insertions(+) diff --git a/arch/arm/dts/armada-7040-db.dts b/arch/arm/dts/armada-7040-db.dts index b158f92349..9104042359 100644 --- a/arch/arm/dts/armada-7040-db.dts +++ b/arch/arm/dts/armada-7040-db.dts @@ -175,6 +175,7 @@ }; &cp0_mdio { + status = "okay"; phy0: ethernet-phy@0 { reg = <0>; }; diff --git a/arch/arm/dts/armada-8040-clearfog-gt-8k.dts b/arch/arm/dts/armada-8040-clearfog-gt-8k.dts index 6a586dbbba..79ee871c5a 100644 --- a/arch/arm/dts/armada-8040-clearfog-gt-8k.dts +++ b/arch/arm/dts/armada-8040-clearfog-gt-8k.dts @@ -295,6 +295,7 @@ }; &cp1_mdio { + status = "okay"; phy0: ethernet-phy@0 { reg = <0>; }; diff --git a/arch/arm/dts/armada-8040-db.dts b/arch/arm/dts/armada-8040-db.dts index 51c2f23f4d..2686e00242 100644 --- a/arch/arm/dts/armada-8040-db.dts +++ b/arch/arm/dts/armada-8040-db.dts @@ -270,6 +270,7 @@ }; &cp0_mdio { + status = "okay"; phy1: ethernet-phy@1 { reg = <1>; }; diff --git a/arch/arm/dts/armada-8040-mcbin.dts b/arch/arm/dts/armada-8040-mcbin.dts index 2184648318..b0bed77ae6 100644 --- a/arch/arm/dts/armada-8040-mcbin.dts +++ b/arch/arm/dts/armada-8040-mcbin.dts @@ -155,6 +155,7 @@ }; &cp0_mdio { + status = "okay"; ge_phy: ethernet-phy@0 { reg = <0>; }; From 758262bc266aa65cfbfd74033c3ac1e4e67c92ec Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Fri, 27 Aug 2021 14:14:43 +0200 Subject: [PATCH 03/10] arm: a37xx: pci: Disable returning CRS response MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit There was mistake in commit 4cd61c43fd51 ("arm: a37xx: pci: Fix handling PIO config error responses"). U-Boot does not support handling of CRS return value for PCI_VENDOR_ID config read request and also does not set CRSSVE bit. Therefore disable returning CRS response for now. Signed-off-by: Pali Rohár Fixes: 4cd61c43fd51 ("arm: a37xx: pci: Fix handling PIO config error responses") Reviewed-by: Stefan Roese --- drivers/pci/pci-aardvark.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/pci/pci-aardvark.c b/drivers/pci/pci-aardvark.c index 815b26162f..d3ef8f203d 100644 --- a/drivers/pci/pci-aardvark.c +++ b/drivers/pci/pci-aardvark.c @@ -358,7 +358,18 @@ static int pcie_advk_read_config(const struct udevice *bus, pci_dev_t bdf, return 0; } - allow_crs = (offset == PCI_VENDOR_ID) && (size == 4); + /* + * Returning fabricated CRS value (0xFFFF0001) by PCIe Root Complex to + * OS is allowed only for 4-byte PCI_VENDOR_ID config read request and + * only when CRSSVE bit in Root Port PCIe device is enabled. In all + * other error PCIe Root Complex must return all-ones. + * Aardvark HW does not have Root Port PCIe device and U-Boot does not + * implement emulation of this device. + * U-Boot currently does not support handling of CRS return value for + * PCI_VENDOR_ID config read request and also does not set CRSSVE bit. + * Therefore disable returning CRS response for now. + */ + allow_crs = false; if (advk_readl(pcie, PIO_START)) { dev_err(pcie->dev, From d9ac6e28afae08f4d0c2116db4279fa59ea7c838 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Fri, 27 Aug 2021 14:14:44 +0200 Subject: [PATCH 04/10] arm: a37xx: pci: Implement re-issuing config requests on CRS response MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit According to PCIe base specification, if CRS Software Visibility is not enabled, the Root Complex must re-issue the Configuration Request as a new Request. Normally this part of Root Complex is implemented in hardware but aardvark is somehow special and does not implement it in hardware and expect that handling of config requests are fully implemented in software. This re-issuing functionality is required also because U-Boot does not support CRS Software Visibility feature and therefore expects that Root Complex re-issues requests as is specified in PCIe base specification. Retry / re-issue config request up to the PIO_MAX_RETRIES, to prevent infinite loop. After retry count exceed PIO_MAX_RETRIES, returns failure. Signed-off-by: Pali Rohár Reviewed-by: Stefan Roese --- drivers/pci/pci-aardvark.c | 58 ++++++++++++++++++++++++++++---------- 1 file changed, 43 insertions(+), 15 deletions(-) diff --git a/drivers/pci/pci-aardvark.c b/drivers/pci/pci-aardvark.c index d3ef8f203d..74797e984c 100644 --- a/drivers/pci/pci-aardvark.c +++ b/drivers/pci/pci-aardvark.c @@ -234,19 +234,19 @@ static int pcie_advk_addr_valid(pci_dev_t bdf, int first_busno) * * Wait up to 1.5 seconds for PIO access to be accomplished. * - * Return 1 (true) if PIO access is accomplished. - * Return 0 (false) if PIO access is timed out. + * Return positive - retry count if PIO access is accomplished. + * Return negative - error if PIO access is timed out. */ static int pcie_advk_wait_pio(struct pcie_advk *pcie) { uint start, isr; uint count; - for (count = 0; count < PIO_MAX_RETRIES; count++) { + for (count = 1; count <= PIO_MAX_RETRIES; count++) { start = advk_readl(pcie, PIO_START); isr = advk_readl(pcie, PIO_ISR); if (!start && isr) - return 1; + return count; /* * Do not check the PIO state too frequently, * 100us delay is appropriate. @@ -255,7 +255,7 @@ static int pcie_advk_wait_pio(struct pcie_advk *pcie) } dev_err(pcie->dev, "PIO read/write transfer time out\n"); - return 0; + return -ETIMEDOUT; } /** @@ -265,11 +265,13 @@ static int pcie_advk_wait_pio(struct pcie_advk *pcie) * @allow_crs: Only for read requests, if CRS response is allowed * @read_val: Pointer to the read result * + * Return: 0 on success */ static int pcie_advk_check_pio_status(struct pcie_advk *pcie, bool allow_crs, uint *read_val) { + int ret; uint reg; unsigned int status; char *strcomp_status, *str_posted; @@ -282,6 +284,7 @@ static int pcie_advk_check_pio_status(struct pcie_advk *pcie, case PIO_COMPLETION_STATUS_OK: if (reg & PIO_ERR_STATUS) { strcomp_status = "COMP_ERR"; + ret = -EFAULT; break; } /* Get the read result */ @@ -289,29 +292,35 @@ static int pcie_advk_check_pio_status(struct pcie_advk *pcie, *read_val = advk_readl(pcie, PIO_RD_DATA); /* No error */ strcomp_status = NULL; + ret = 0; break; case PIO_COMPLETION_STATUS_UR: strcomp_status = "UR"; + ret = -EOPNOTSUPP; break; case PIO_COMPLETION_STATUS_CRS: if (allow_crs && read_val) { /* For reading, CRS is not an error status. */ *read_val = CFG_RD_CRS_VAL; strcomp_status = NULL; + ret = 0; } else { strcomp_status = "CRS"; + ret = -EAGAIN; } break; case PIO_COMPLETION_STATUS_CA: strcomp_status = "CA"; + ret = -ECANCELED; break; default: strcomp_status = "Unknown"; + ret = -EINVAL; break; } if (!strcomp_status) - return 0; + return ret; if (reg & PIO_NON_POSTED_REQ) str_posted = "Non-posted"; @@ -322,7 +331,7 @@ static int pcie_advk_check_pio_status(struct pcie_advk *pcie, str_posted, strcomp_status, reg, advk_readl(pcie, PIO_ADDR_LS)); - return -EFAULT; + return ret; } /** @@ -345,6 +354,7 @@ static int pcie_advk_read_config(const struct udevice *bus, pci_dev_t bdf, enum pci_size_t size) { struct pcie_advk *pcie = dev_get_priv(bus); + int retry_count; bool allow_crs; uint reg; int ret; @@ -379,7 +389,7 @@ static int pcie_advk_read_config(const struct udevice *bus, pci_dev_t bdf, return 0; } *valuep = pci_get_ff(size); - return -EINVAL; + return -EAGAIN; } /* Program the control register */ @@ -396,21 +406,29 @@ static int pcie_advk_read_config(const struct udevice *bus, pci_dev_t bdf, advk_writel(pcie, reg, PIO_ADDR_LS); advk_writel(pcie, 0, PIO_ADDR_MS); + retry_count = 0; + +retry: /* Start the transfer */ advk_writel(pcie, 1, PIO_ISR); advk_writel(pcie, 1, PIO_START); - if (!pcie_advk_wait_pio(pcie)) { + ret = pcie_advk_wait_pio(pcie); + if (ret < 0) { if (allow_crs) { *valuep = CFG_RD_CRS_VAL; return 0; } *valuep = pci_get_ff(size); - return -EINVAL; + return ret; } + retry_count += ret; + /* Check PIO status and get the read result */ ret = pcie_advk_check_pio_status(pcie, allow_crs, ®); + if (ret == -EAGAIN && retry_count < PIO_MAX_RETRIES) + goto retry; if (ret) { *valuep = pci_get_ff(size); return ret; @@ -472,7 +490,9 @@ static int pcie_advk_write_config(struct udevice *bus, pci_dev_t bdf, enum pci_size_t size) { struct pcie_advk *pcie = dev_get_priv(bus); + int retry_count; uint reg; + int ret; dev_dbg(pcie->dev, "PCIE CFG write: (b,d,f)=(%2d,%2d,%2d) ", PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf)); @@ -487,7 +507,7 @@ static int pcie_advk_write_config(struct udevice *bus, pci_dev_t bdf, if (advk_readl(pcie, PIO_START)) { dev_err(pcie->dev, "Previous PIO read/write transfer is still running\n"); - return -EINVAL; + return -EAGAIN; } /* Program the control register */ @@ -515,16 +535,24 @@ static int pcie_advk_write_config(struct udevice *bus, pci_dev_t bdf, advk_writel(pcie, reg, PIO_WR_DATA_STRB); dev_dbg(pcie->dev, "\tPIO req. - strb = 0x%02x\n", reg); + retry_count = 0; + +retry: /* Start the transfer */ advk_writel(pcie, 1, PIO_ISR); advk_writel(pcie, 1, PIO_START); - if (!pcie_advk_wait_pio(pcie)) { - return -EINVAL; - } + ret = pcie_advk_wait_pio(pcie); + if (ret < 0) + return ret; + + retry_count += ret; /* Check PIO status */ - return pcie_advk_check_pio_status(pcie, false, NULL); + ret = pcie_advk_check_pio_status(pcie, false, NULL); + if (ret == -EAGAIN && retry_count < PIO_MAX_RETRIES) + goto retry; + return ret; } /** From f4ce28ab740d8728f3f580febbc3598a1498df18 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Thu, 2 Sep 2021 10:34:00 +0200 Subject: [PATCH 05/10] arm: mvebu: turris_{omnia, mox}: GPT partition support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This allows U-Boot to access filesystems on GPT partitioned disks. Signed-off-by: Pali Rohár Reviewed-by: Stefan Roese --- configs/turris_mox_defconfig | 1 + configs/turris_omnia_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/configs/turris_mox_defconfig b/configs/turris_mox_defconfig index 40f975ead3..9a9102430e 100644 --- a/configs/turris_mox_defconfig +++ b/configs/turris_mox_defconfig @@ -29,6 +29,7 @@ CONFIG_CMD_SHA1SUM=y CONFIG_CMD_CLK=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_MTD=y diff --git a/configs/turris_omnia_defconfig b/configs/turris_omnia_defconfig index b2bbbd1469..a724a1baa1 100644 --- a/configs/turris_omnia_defconfig +++ b/configs/turris_omnia_defconfig @@ -40,6 +40,7 @@ CONFIG_SYS_ALT_MEMTEST=y CONFIG_CMD_SHA1SUM=y CONFIG_CMD_LZMADEC=y CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_MTD=y From 5a8bd463a6703e2fbb877e11873ae5622965f724 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Thu, 2 Sep 2021 10:46:37 +0200 Subject: [PATCH 06/10] arm: mvebu: espressobin: Enable GPT partition support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Pali Rohár Reviewed-by: Stefan Roese --- configs/mvebu_espressobin-88f3720_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/mvebu_espressobin-88f3720_defconfig b/configs/mvebu_espressobin-88f3720_defconfig index 9641c02d93..761187479f 100644 --- a/configs/mvebu_espressobin-88f3720_defconfig +++ b/configs/mvebu_espressobin-88f3720_defconfig @@ -26,6 +26,7 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_LATE_INIT=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_MTD=y From a4a06a180d622b86183b0825891d2bdd37f3b4db Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Thu, 2 Sep 2021 12:00:51 +0200 Subject: [PATCH 07/10] arm: mvebu: a38x: Fix 5200000 baudrate MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fix baudrate value 5150000 which was added in commit ead4864fa6cc ("arm: mvebu: a38x: Define supported UART baudrates"). Exact value for divisor 3 with 250 MHz TCLK is 5208333 baudrate. In above commit I incorrectly rounded it to 5150000 value due to testing with USB-UART hw which incorrectly reported exact value and divisor configured on other other end of UART link. Fix this value to 520000 baudrate which is more close to the exact hardware value and also has less fraction parts. Signed-off-by: Pali Rohár Fixes: ead4864fa6cc ("arm: mvebu: a38x: Define supported UART baudrates") Reviewed-by: Stefan Roese --- include/configs/mv-common.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/mv-common.h b/include/configs/mv-common.h index 53d7acbb10..6036bf4fa5 100644 --- a/include/configs/mv-common.h +++ b/include/configs/mv-common.h @@ -45,7 +45,7 @@ 230400, 460800, 500000, 576000, \ 921600, 1000000, 1152000, 1500000, \ 2000000, 2500000, 3125000, 4000000, \ - 5150000 } + 5200000 } #endif /* auto boot */ From 5df1ee459452e29d39cf717cd0719146427709d9 Mon Sep 17 00:00:00 2001 From: Tony Dinh Date: Sun, 5 Sep 2021 14:48:25 -0700 Subject: [PATCH 08/10] arm: mvebu : sata_mv should probe all ports While a board could have multiple SATA ports, some of the ports might not have a disk attached to them. So while probing for disks, sata_mv_probe() should continue probing all ports, and skip one with no disk attached. Tests with: - Seagate Goflex Net (Marvell Kirkwood 88F6281) out-of-tree u-boot. - Zyxel NSA325 (Marvell Kirkwood 88F6282 out-of-tree u-boot. Observation: If a board has 2 or more SATA ports, and there is only one disk attached to one of the ports, sata_mv_probe() does not return a successful probe status. And if only one disk is attached to the 2nd port (i.e. port 1), it is not probed at all. Patch Description: Let sata_mv_probe() continues probing all ports, even if there is error in probing a given port, and then return a successful status if there is at least one port was probed successfully. Signed-off-by: Tony Dinh Reviewed-by: Stefan Roese --- drivers/ata/sata_mv.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/drivers/ata/sata_mv.c b/drivers/ata/sata_mv.c index dadb2c7c2e..003222d47b 100644 --- a/drivers/ata/sata_mv.c +++ b/drivers/ata/sata_mv.c @@ -1068,6 +1068,7 @@ static int sata_mv_probe(struct udevice *dev) int nr_ports; int ret; int i; + int status = -ENODEV; /* If the probe fails to detected any SATA port */ /* Get number of ports of this SATA controller */ nr_ports = min(fdtdec_get_int(blob, node, "nr-ports", -1), @@ -1078,7 +1079,7 @@ static int sata_mv_probe(struct udevice *dev) IF_TYPE_SATA, -1, 512, 0, &blk); if (ret) { debug("Can't create device\n"); - return ret; + continue; } priv = dev_get_plat(blk); @@ -1088,18 +1089,23 @@ static int sata_mv_probe(struct udevice *dev) ret = sata_mv_init_sata(blk, i); if (ret) { debug("%s: Failed to init bus\n", __func__); - return ret; + continue; } /* Scan SATA port */ ret = sata_mv_scan_sata(blk, i); if (ret) { debug("%s: Failed to scan bus\n", __func__); - return ret; + continue; } + + /* If we got here, the current SATA port was probed + * successfully, so set the probe status to successful. + */ + status = 0; } - return 0; + return status; } static int sata_mv_scan(struct udevice *dev) From 47d893138603ef7facf6e6b91128927b8c5a839b Mon Sep 17 00:00:00 2001 From: Tony Dinh Date: Mon, 6 Sep 2021 16:28:35 -0700 Subject: [PATCH 09/10] arm: marvell: Dreamplug: fix typo in eth1 name Ethernet 1 should be ethernet-controller@76000. Signed-off-by: Tony Dinh Reviewed-by: Stefan Roese --- board/Marvell/dreamplug/dreamplug.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/Marvell/dreamplug/dreamplug.c b/board/Marvell/dreamplug/dreamplug.c index d5b6b22ddf..7ba14021b2 100644 --- a/board/Marvell/dreamplug/dreamplug.c +++ b/board/Marvell/dreamplug/dreamplug.c @@ -163,7 +163,7 @@ void reset_phy(void) char *eth0_name = "ethernet-controller@72000"; char *eth0_path = "/ocp@f1000000/ethernet-controller@72000/ethernet0-port@0"; char *eth1_name = "ethernet-controller@76000"; - char *eth1_path = "/ocp@f1000000/ethernet-controller@72000/ethernet1-port@0"; + char *eth1_path = "/ocp@f1000000/ethernet-controller@76000/ethernet1-port@0"; /* configure and initialize both PHY's */ mv_phy_88e1116_init(eth0_name, eth0_path); From 157bc52b0fa9d75611aeca9668c5227d6e64e05e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Beh=C3=BAn?= Date: Tue, 7 Sep 2021 17:27:08 +0200 Subject: [PATCH 10/10] arm: a37xx: pci: Don't spam about PIO Response Status MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use dev_dbg() instead of dev_err() in pcie_advk_check_pio_status(). For example CRS is not an error status, it just says that the request should be retried. Without this, U-Boot spams the terminal with pcie_advk pcie@d0070000: Non-posted PIO Response Status: UR, 0xc80 @ 0x100000 pcie_advk pcie@d0070000: Non-posted PIO Response Status: UR, 0xc80 @ 0x108000 pcie_advk pcie@d0070000: Non-posted PIO Response Status: UR, 0xc80 @ 0x110000 pcie_advk pcie@d0070000: Non-posted PIO Response Status: UR, 0xc80 @ 0x120000 pcie_advk pcie@d0070000: Non-posted PIO Response Status: UR, 0xc80 @ 0x128000 pcie_advk pcie@d0070000: Non-posted PIO Response Status: UR, 0xc80 @ 0x130000 ... when a device is not connected to a PCIe switch (Unsupported Request from the switch). Signed-off-by: Marek Behún Reviewed-by: Pali Rohár Reviewed-by: Stefan Roese --- drivers/pci/pci-aardvark.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/pci-aardvark.c b/drivers/pci/pci-aardvark.c index 74797e984c..cf6e30f936 100644 --- a/drivers/pci/pci-aardvark.c +++ b/drivers/pci/pci-aardvark.c @@ -327,7 +327,7 @@ static int pcie_advk_check_pio_status(struct pcie_advk *pcie, else str_posted = "Posted"; - dev_err(pcie->dev, "%s PIO Response Status: %s, %#x @ %#x\n", + dev_dbg(pcie->dev, "%s PIO Response Status: %s, %#x @ %#x\n", str_posted, strcomp_status, reg, advk_readl(pcie, PIO_ADDR_LS));