From 446cf811c58733c4b68149a0b83f4a258e1719ba Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 20 Nov 2019 22:34:30 +0100 Subject: [PATCH 1/5] ARM: socfpga: Actually put bridges into reset on Gen5 in bridge disable On Gen5, the 'bridge disable' command write 0x0 to brgmodrst register, which releases all bridges from reset, instead of putting all bridges into reset. Fix this by inverting the mask and actually putting the bridges into reset. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dalon Westergreen Cc: Dinh Nguyen Cc: Ley Foon Tan Cc: Simon Goldschmidt Cc: Tien Fong Chee Reviewed-by: Ley Foon Tan Reviewed-by: Simon Goldschmidt --- arch/arm/mach-socfpga/misc_gen5.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c index 31681b799d..36f00aee31 100644 --- a/arch/arm/mach-socfpga/misc_gen5.c +++ b/arch/arm/mach-socfpga/misc_gen5.c @@ -231,7 +231,7 @@ void do_bridge_reset(int enable, unsigned int mask) } else { writel(0, &sysmgr_regs->fpgaintfgrp_module); writel(0, &sdr_ctrl->fpgaport_rst); - writel(0, &reset_manager_base->brg_mod_reset); + writel(0x7, &reset_manager_base->brg_mod_reset); writel(1, &nic301_regs->remap); } } From 97a72bc28613733572b9632a51ab9c8680d45406 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 20 Nov 2019 22:34:31 +0100 Subject: [PATCH 2/5] ARM: socfpga: Purge pending transactions upon enabling bridges on Gen5 On Gen5, when the FPGA is loaded and there was some prior interaction between the HPS and the FPGA via bridges (e.g. Linux was running and using some of the IPs in the FPGA) followed by warm reset, it has been observed that there might be outstanding unfinished transactions. This leads to an obscure misbehavior of the bridge. When the bridge is enabled again in U-Boot and there are outstanding transactions, a read from within the bridge address range would return a result of the previous read instead. Example: => bridge enable ; md 0xff200000 1 ff200000: 1234abcd => bridge enable ; md 0xff200010 1 ff200010: 5678dcba <------- this is in fact a value which is stored in a memory at 0xff200000 => bridge enable ; md 0xff200000 1 ff200000: 90effe09 <------- this is in fact a value which is stored in a memory at 0xff200010 and so it continues. Issuing a write does lock the system up completely. This patch opens the FPGA bridges in 'bridge enable' command, the tears them down again, and then opens them again. This allows these outstanding transactions to complete and makes this misbehavior go away. However, it is not entirely clear whether this is the correct solution. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dalon Westergreen Cc: Dinh Nguyen Cc: Ley Foon Tan Cc: Simon Goldschmidt Cc: Tien Fong Chee Reviewed-by: Ley Foon Tan --- arch/arm/mach-socfpga/misc_gen5.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c index 36f00aee31..65d3485bc5 100644 --- a/arch/arm/mach-socfpga/misc_gen5.c +++ b/arch/arm/mach-socfpga/misc_gen5.c @@ -228,6 +228,9 @@ void do_bridge_reset(int enable, unsigned int mask) writel(iswgrp_handoff[3], &sdr_ctrl->fpgaport_rst); writel(iswgrp_handoff[0], &reset_manager_base->brg_mod_reset); writel(iswgrp_handoff[1], &nic301_regs->remap); + + writel(0x7, &reset_manager_base->brg_mod_reset); + writel(iswgrp_handoff[0], &reset_manager_base->brg_mod_reset); } else { writel(0, &sysmgr_regs->fpgaintfgrp_module); writel(0, &sdr_ctrl->fpgaport_rst); From 2007a730eef83421cc6ca3c1875fa0e0b4d4712e Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 20 Nov 2019 22:40:19 +0100 Subject: [PATCH 3/5] ARM: socfpga: Add ArriaV ST/SX ID Add new FPGA ID for ArriaV ST/D3 or SX/B3 . Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dalon Westergreen Cc: Dinh Nguyen Cc: Ley Foon Tan Cc: Simon Goldschmidt Cc: Tien Fong Chee Reviewed-by: Ley Foon Tan --- arch/arm/mach-socfpga/misc_gen5.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c index 65d3485bc5..22042d0de0 100644 --- a/arch/arm/mach-socfpga/misc_gen5.c +++ b/arch/arm/mach-socfpga/misc_gen5.c @@ -79,6 +79,8 @@ static const struct { { 0x2d02, "Cyclone V, SE/A6 or SX/C6 or ST/D6", "cv_se_a6" }, /* Arria V */ { 0x2d03, "Arria V, D5", "av_d5" }, + /* Arria V ST/SX */ + { 0x2d13, "Arria V, ST/D3 or SX/B3", "av_st_d3" }, }; static int socfpga_fpga_id(const bool print_id) From 533832c6a47b5f7463f3b1d20337d2746f568b24 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 20 Nov 2019 22:36:45 +0100 Subject: [PATCH 4/5] ARM: socfpga: Introduce u-boot-with-nand-spl.sfp target The NAND devices with 128 kiB erase blocks require extra 64 kiB padding between each SPL image. Generate U-Boot image with such a padding using this new target. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dalon Westergreen Cc: Dinh Nguyen Cc: Ley Foon Tan Cc: Simon Goldschmidt Cc: Tien Fong Chee Reviewed-by: Ley Foon Tan --- Makefile | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/Makefile b/Makefile index 7485bc2594..d3038cf665 100644 --- a/Makefile +++ b/Makefile @@ -1476,6 +1476,17 @@ cmd_socboot = cat spl/u-boot-spl.sfp spl/u-boot-spl.sfp \ u-boot.img > $@ || rm -f $@ u-boot-with-spl.sfp: spl/u-boot-spl.sfp u-boot.img FORCE $(call if_changed,socboot) + +quiet_cmd_socnandboot = SOCNANDBOOT $@ +cmd_socnandboot = dd if=/dev/zero of=spl/u-boot-spl.pad bs=64 count=1024 ; \ + cat spl/u-boot-spl.sfp spl/u-boot-spl.pad \ + spl/u-boot-spl.sfp spl/u-boot-spl.pad \ + spl/u-boot-spl.sfp spl/u-boot-spl.pad \ + spl/u-boot-spl.sfp spl/u-boot-spl.pad \ + u-boot.img > $@ || rm -f $@ spl/u-boot-spl.pad +u-boot-with-nand-spl.sfp: spl/u-boot-spl.sfp u-boot.img FORCE + $(call if_changed,socnandboot) + endif ifeq ($(CONFIG_MPC85xx)$(CONFIG_OF_SEPARATE),yy) From a1a9843a29672be49a5bbb3a07fea8dbc88369ba Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 20 Nov 2019 22:36:24 +0100 Subject: [PATCH 5/5] ARM: socfpga: Unreset NAND in SPL on Gen5 In case the SPL on Gen5 loads U-Boot from NAND, unreset the NAND IP explicitly in the platform code as the denali-spl driver is not aware of DM at all. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dalon Westergreen Cc: Dinh Nguyen Cc: Ley Foon Tan Cc: Simon Goldschmidt Cc: Tien Fong Chee Reviewed-by: Ley Foon Tan --- arch/arm/mach-socfpga/spl_gen5.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c index 47e63709ad..408e409375 100644 --- a/arch/arm/mach-socfpga/spl_gen5.c +++ b/arch/arm/mach-socfpga/spl_gen5.c @@ -138,6 +138,13 @@ void board_init_f(ulong dummy) if (ret) debug("Reset init failed: %d\n", ret); +#ifdef CONFIG_SPL_NAND_DENALI + struct socfpga_reset_manager *reset_manager_base = + (struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS; + + clrbits_le32(&reset_manager_base->per_mod_reset, BIT(4)); +#endif + /* enable console uart printing */ preloader_console_init();