From 992bcf4f27794a7f578e0145ef1c933a87a1d83c Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 11 Jan 2019 23:45:54 +0100 Subject: [PATCH 1/4] mmc: tmio: Make DMA transfer end bit configurable Different versions of the SDHI core use either bit 17 or bit 20 for the DTRAEND indication, which can differ even between SoC revisions. Make the DTRAEND bit position part of the driver private data, so that the probe function can set this accordingly. Set this to 20 on Socionext SoCs and either 17 or 20 on Renesas SoCs, depending on the SoC. Signed-off-by: Marek Vasut Cc: Masahiro Yamada --- drivers/mmc/renesas-sdhi.c | 10 ++++++++++ drivers/mmc/tmio-common.c | 8 +++----- drivers/mmc/tmio-common.h | 1 + drivers/mmc/uniphier-sd.c | 1 + 4 files changed, 15 insertions(+), 5 deletions(-) diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c index 733b6d62f5..a556acd5cb 100644 --- a/drivers/mmc/renesas-sdhi.c +++ b/drivers/mmc/renesas-sdhi.c @@ -462,6 +462,16 @@ static void renesas_sdhi_filter_caps(struct udevice *dev) priv->nrtaps = 4; else priv->nrtaps = 8; + + /* H3 ES1.x and M3W ES1.0 uses bit 17 for DTRAEND */ + if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) && + (rmobile_get_cpu_rev_integer() <= 1)) || + ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) && + (rmobile_get_cpu_rev_integer() == 1) && + (rmobile_get_cpu_rev_fraction() == 0))) + priv->read_poll_flag = TMIO_SD_DMA_INFO1_END_RD; + else + priv->read_poll_flag = TMIO_SD_DMA_INFO1_END_RD2; } static int renesas_sdhi_probe(struct udevice *dev) diff --git a/drivers/mmc/tmio-common.c b/drivers/mmc/tmio-common.c index 201492001f..0b6a284f2e 100644 --- a/drivers/mmc/tmio-common.c +++ b/drivers/mmc/tmio-common.c @@ -347,12 +347,10 @@ static int tmio_sd_dma_xfer(struct udevice *dev, struct mmc_data *data) /* * The DMA READ completion flag position differs on Socionext * and Renesas SoCs. It is bit 20 on Socionext SoCs and using - * bit 17 is a hardware bug and forbidden. It is bit 17 on - * Renesas SoCs and bit 20 does not work on them. + * bit 17 is a hardware bug and forbidden. It is either bit 17 + * or bit 20 on Renesas SoCs, depending on SoC. */ - poll_flag = (priv->caps & TMIO_SD_CAP_RCAR) ? - TMIO_SD_DMA_INFO1_END_RD : - TMIO_SD_DMA_INFO1_END_RD2; + poll_flag = priv->read_poll_flag; tmp |= TMIO_SD_DMA_MODE_DIR_RD; } else { buf = (void *)data->src; diff --git a/drivers/mmc/tmio-common.h b/drivers/mmc/tmio-common.h index 192026ce3e..58ce3d65b0 100644 --- a/drivers/mmc/tmio-common.h +++ b/drivers/mmc/tmio-common.h @@ -119,6 +119,7 @@ struct tmio_sd_priv { void __iomem *regbase; unsigned int version; u32 caps; + u32 read_poll_flag; #define TMIO_SD_CAP_NONREMOVABLE BIT(0) /* Nonremovable e.g. eMMC */ #define TMIO_SD_CAP_DMA_INTERNAL BIT(1) /* have internal DMA engine */ #define TMIO_SD_CAP_DIV1024 BIT(2) /* divisor 1024 is available */ diff --git a/drivers/mmc/uniphier-sd.c b/drivers/mmc/uniphier-sd.c index 6539880ab5..8f89bda233 100644 --- a/drivers/mmc/uniphier-sd.c +++ b/drivers/mmc/uniphier-sd.c @@ -47,6 +47,7 @@ static int uniphier_sd_probe(struct udevice *dev) struct tmio_sd_priv *priv = dev_get_priv(dev); priv->clk_get_rate = uniphier_sd_clk_get_rate; + priv->read_poll_flag = TMIO_SD_DMA_INFO1_END_RD2; #ifndef CONFIG_SPL_BUILD int ret; From cbbe69483ec823105903bac890fab9af087c36c9 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 11 Jan 2019 23:38:07 +0100 Subject: [PATCH 2/4] mmc: tmio: renesas: Add 1uS delay after DMA completion on older IPs The internal DMAC asserts DMA transfer end bit too early on older version of the TMIO IPs which use bit 17 for DTRAEND. Add 1uS delay after the completion of DMA transfer and before invalidating the cache to let the DMAC fully complete the transfer. Otherwise, it could happen that the last few bytes of a transferred data are not available. A test case to trigger this behavior is the following command, ran on the U-Boot command line, with Sandisk 16 GiB UHS-I card inserted into SDHI slot 0 and with first partition being of type FAT: => while true ; do mmc rescan ; fstype mmc 0:1 ; done Signed-off-by: Marek Vasut Cc: Masahiro Yamada --- drivers/mmc/tmio-common.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/mmc/tmio-common.c b/drivers/mmc/tmio-common.c index 0b6a284f2e..2421915a07 100644 --- a/drivers/mmc/tmio-common.c +++ b/drivers/mmc/tmio-common.c @@ -367,6 +367,9 @@ static int tmio_sd_dma_xfer(struct udevice *dev, struct mmc_data *data) ret = tmio_sd_dma_wait_for_irq(dev, poll_flag, data->blocks); + if (poll_flag == TMIO_SD_DMA_INFO1_END_RD) + udelay(1); + __dma_unmap_single(dma_addr, len, dir); return ret; From 6892550c4aea4e9fcbee3cdb6947ac78085981ae Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 6 Feb 2019 11:34:27 +0100 Subject: [PATCH 3/4] mmc: Do not poll using CMD13 when changing timing When using CMD6 to switch eMMC card timing from HS200/HS400 to HS/legacy, do not poll for the completion status using CMD13, but rather wait 50mS. Once the card receives the CMD6 and starts executing it, the bus is in undefined state until both the card finishes executing the command and until the controller switches the bus to matching timing configuration. During this time, it is not possible to transport any commands or data across the bus, which includes the CMD13. Signed-off-by: Marek Vasut Cc: Jaehoon Chung --- drivers/mmc/mmc.c | 28 ++++++++++++++++++++-------- 1 file changed, 20 insertions(+), 8 deletions(-) diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index 84d157ff40..b04345a1e1 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -724,7 +724,8 @@ static int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd) return err; } -int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value) +static int __mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value, + bool send_status) { struct mmc_cmd cmd; int timeout = 1000; @@ -740,19 +741,29 @@ int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value) while (retries > 0) { ret = mmc_send_cmd(mmc, &cmd, NULL); - /* Waiting for the ready status */ - if (!ret) { - ret = mmc_send_status(mmc, timeout); - return ret; + if (ret) { + retries--; + continue; } - retries--; + if (!send_status) { + mdelay(50); + return 0; + } + + /* Waiting for the ready status */ + return mmc_send_status(mmc, timeout); } return ret; } +int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value) +{ + return __mmc_switch(mmc, set, index, value, true); +} + #if !CONFIG_IS_ENABLED(MMC_TINY) static int mmc_set_card_speed(struct mmc *mmc, enum bus_mode mode, bool hsdowngrade) @@ -784,8 +795,9 @@ static int mmc_set_card_speed(struct mmc *mmc, enum bus_mode mode, default: return -EINVAL; } - err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, - speed_bits); + + err = __mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, + speed_bits, !hsdowngrade); if (err) return err; From e531c6731b697fc524b54697caebf235a4a69e8d Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 6 Feb 2019 13:19:29 +0100 Subject: [PATCH 4/4] fs: ext4: Unmount FS in do_fs_type() Unlike other generic FS accessors, fs_get_info() does not call fs_close() at the end of it's operation. Thus, using fs_get_info() in do_fs_type() without calling fs_close() causes potential memory leak by creating new filesystem structures on each call of do_fs_type(). The test case to trigger this problem is as follows. It is required to have ext4 filesystem on the first partition of the SDMMC device, since ext4 requires stateful mount and causes memory allocation. => while true ; do mmc rescan ; fstype mmc 1 ; done Eventually, the mounting of ext4 will fail due to malloc failures and the filesystem will not be correctly detected. This patch fixes the problem by adding the missing fs_close(). Signed-off-by: Marek Vasut Cc: Simon Glass Cc: Tom Rini --- fs/fs.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/fs/fs.c b/fs/fs.c index 0e9c2f1062..c5c35ebf5f 100644 --- a/fs/fs.c +++ b/fs/fs.c @@ -801,6 +801,8 @@ int do_fs_type(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) else printf("%s\n", info->name); + fs_close(); + return CMD_RET_SUCCESS; }