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Merge branch 'master' of git://git.denx.de/u-boot-arm

Browse Source
This commit is contained in:
Tom Rini
2012-12-22 05:55:19 -07:00
parent ba6d4b64b3 96764df1b4
commit da77a0e593
163 changed files with 8453 additions and 1096 deletions
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4
include/configs/harmony.h
View File

@@ -58,14 +58,16 @@
#define CONFIG_DOS_PARTITION
#define CONFIG_EFI_PARTITION
#define CONFIG_FS_EXT4
#define CONFIG_FS_FAT
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#define CONFIG_CMD_FS_GENERIC
/* NAND support */
#define CONFIG_CMD_NAND
#define CONFIG_TEGRA_NAND
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE NV_PA_NAND_BASE
/* Environment in NAND (which is 512M), aligned to start of last sector */
#define CONFIG_ENV_IS_IN_NAND

43
include/configs/mx25pdk.h
View File

@@ -19,8 +19,10 @@
/* High Level Configuration Options */
#define CONFIG_MX25
#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_TEXT_BASE 0x81200000
#define CONFIG_MXC_GPIO
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
@@ -41,6 +43,7 @@
#define PHYS_SDRAM_1_SIZE (64 * 1024 * 1024)
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_LATE_INIT
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR IMX_RAM_BASE
@@ -64,9 +67,10 @@
/* No NOR flash present */
#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
#define CONFIG_ENV_SIZE (8 * 1024)
#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_SYS_NO_FLASH
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
/* U-Boot general configuration */
#define CONFIG_SYS_PROMPT "MX25PDK U-Boot > "
@@ -83,7 +87,12 @@
/* U-Boot commands */
#include <config_cmd_default.h>
#define CONFIG_OF_LIBFDT
#define CONFIG_CMD_BOOTZ
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_MMC
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
/* Ethernet */
#define CONFIG_FEC_MXC
@@ -92,7 +101,37 @@
#define CONFIG_CMD_NET
#define CONFIG_ENV_OVERWRITE
#define CONFIG_BOOTDELAY 3
/* ESDHC driver */
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_ESDHC_NUM 1
/* PMIC Configs */
#define CONFIG_POWER
#define CONFIG_POWER_I2C
#define CONFIG_POWER_FSL
#define CONFIG_PMIC_FSL_MC34704
#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x54
#define CONFIG_DOS_PARTITION
/* I2C Configs */
#define CONFIG_CMD_I2C
#define CONFIG_HARD_I2C
#define CONFIG_I2C_MXC
#define CONFIG_SYS_I2C_BASE IMX_I2C_BASE
#define CONFIG_SYS_I2C_SPEED 100000
/* Ethernet Configs */
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_MII
#define CONFIG_CMD_NET
#define CONFIG_BOOTDELAY 1
#define CONFIG_LOADADDR 0x81000000 /* loadaddr env var */
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR

2
include/configs/mx28evk.h
View File

@@ -238,7 +238,7 @@
*/
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTDELAY 1
#define CONFIG_BOOTFILE "uImage"
#define CONFIG_LOADADDR 0x42000000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR

2
include/configs/mx31pdk.h
View File

@@ -106,7 +106,7 @@
#define CONFIG_BOARD_LATE_INIT
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTDELAY 1
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootargs_base=setenv bootargs console=ttymxc0,115200\0" \

18
include/configs/mx35pdk.h
View File

@@ -68,6 +68,7 @@
#define CONFIG_POWER
#define CONFIG_POWER_I2C
#define CONFIG_POWER_FSL
#define CONFIG_PMIC_FSL_MC13892
#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x08
#define CONFIG_RTC_MC13XXX
@@ -94,6 +95,7 @@
#include <config_cmd_default.h>
#define CONFIG_CMD_BOOTZ
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#define CONFIG_BOOTP_SUBNETMASK
@@ -110,13 +112,15 @@
#define CONFIG_NET_RETRY_COUNT 100
#define CONFIG_CMD_DATE
#define CONFIG_CMD_USB
#define CONFIG_USB_STORAGE
#define CONFIG_CMD_MMC
#define CONFIG_DOS_PARTITION
#define CONFIG_EFI_PARTITION
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTDELAY 1
#define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */
@@ -242,6 +246,18 @@
#define CONFIG_MXC_NAND_HWECC
#define CONFIG_SYS_NAND_LARGEPAGE
/* EHCI driver */
#define CONFIG_USB_EHCI
#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
#define CONFIG_EHCI_IS_TDI
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_USB_EHCI_MXC
#define CONFIG_MXC_USB_PORT 0
#define CONFIG_MXC_USB_FLAGS (MXC_EHCI_INTERFACE_DIFF_UNI | \
MXC_EHCI_POWER_PINS_ENABLED | \
MXC_EHCI_OC_PIN_ACTIVE_LOW)
#define CONFIG_MXC_USB_PORTSC (MXC_EHCI_UTMI_16BIT | MXC_EHCI_MODE_UTMI)
/* mmc driver */
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC

1
include/configs/mx51_efikamx.h
View File

@@ -261,5 +261,6 @@
#define CONFIG_SYS_DDR_CLKSEL 0
#define CONFIG_SYS_CLKTL_CBCDR 0x59E35145
#define CONFIG_SYS_MAIN_PWR_ON
#endif

5
include/configs/mx51evk.h
View File

@@ -144,12 +144,12 @@
***********************************************************/
#include <config_cmd_default.h>
#define CONFIG_CMD_BOOTZ
#undef CONFIG_CMD_IMLS
#define CONFIG_CMD_DATE
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTDELAY 1
#define CONFIG_ETHPRIME "FEC0"
@@ -235,6 +235,7 @@
#define CONFIG_SYS_DDR_CLKSEL 0
#define CONFIG_SYS_CLKTL_CBCDR 0x59E35100
#define CONFIG_SYS_MAIN_PWR_ON
/*-----------------------------------------------------------------------
* FLASH and environment organization

1
include/configs/mx53evk.h
View File

@@ -59,6 +59,7 @@
#define CONFIG_POWER_I2C
#define CONFIG_POWER_FSL
#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 8
#define CONFIG_PMIC_FSL_MC13892
#define CONFIG_RTC_MC13XXX
/* MMC Configs */

4
include/configs/mx53loco.h
View File

@@ -93,6 +93,7 @@
#define CONFIG_POWER_I2C
#define CONFIG_DIALOG_POWER
#define CONFIG_POWER_FSL
#define CONFIG_PMIC_FSL_MC13892
#define CONFIG_SYS_DIALOG_PMIC_I2C_ADDR 0x48
#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x8
@@ -103,10 +104,11 @@
/* Command definition */
#include <config_cmd_default.h>
#define CONFIG_CMD_BOOTZ
#undef CONFIG_CMD_IMLS
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTDELAY 1
#define CONFIG_ETHPRIME "FEC0"

1
include/configs/mx6qarm2.h
View File

@@ -22,6 +22,7 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_MX6
#define CONFIG_MX6Q
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO

4
include/configs/mx6qsabre_common.h
View File

@@ -17,6 +17,7 @@
#ifndef __MX6QSABRE_COMMON_CONFIG_H
#define __MX6QSABRE_COMMON_CONFIG_H
#define CONFIG_MX6
#define CONFIG_MX6Q
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
@@ -72,9 +73,10 @@
/* Command definition */
#include <config_cmd_default.h>
#define CONFIG_CMD_BOOTZ
#undef CONFIG_CMD_IMLS
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTDELAY 1
#define CONFIG_LOADADDR 0x10800000
#define CONFIG_SYS_TEXT_BASE 0x17800000

3
include/configs/mx6qsabrelite.h
View File

@@ -22,6 +22,7 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_MX6
#define CONFIG_MX6Q
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
@@ -143,7 +144,7 @@
#undef CONFIG_CMD_IMLS
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTDELAY 1
#define CONFIG_PREBOOT ""

3
include/configs/palmld.h
View File

@@ -28,6 +28,9 @@
#define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */
#define CONFIG_PALMLD 1 /* Palm LifeDrive board */
/* we will never enable dcache, because we have to setup MMU first */
#define CONFIG_SYS_DCACHE_OFF
/*
* Environment settings
*/

3
include/configs/palmtc.h
View File

@@ -30,6 +30,9 @@
#define CONFIG_CPU_PXA25X 1 /* Intel PXA255 CPU */
#define CONFIG_PALMTC 1 /* Palm Tungsten|C board */
/* we will never enable dcache, because we have to setup MMU first */
#define CONFIG_SYS_DCACHE_OFF
/*
* Environment settings
*/

3
include/configs/paz00.h
View File

@@ -45,8 +45,11 @@
#define CONFIG_DOS_PARTITION
#define CONFIG_EFI_PARTITION
#define CONFIG_FS_EXT4
#define CONFIG_FS_FAT
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#define CONFIG_CMD_FS_GENERIC
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_ENV_IS_IN_MMC

36
include/configs/s5pc210_universal.h
View File

@@ -34,6 +34,7 @@
#define CONFIG_S5P 1 /* which is in a S5P Family */
#define CONFIG_EXYNOS4210 1 /* which is in a EXYNOS4210 */
#define CONFIG_UNIVERSAL 1 /* working with Universal */
#define CONFIG_TIZEN 1 /* TIZEN lib */
#include <asm/arch/cpu.h> /* get chip and board defs */
@@ -56,6 +57,8 @@
#define CONFIG_INITRD_TAG
#define CONFIG_REVISION_TAG
#define CONFIG_CMDLINE_EDITING
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_BOARD_EARLY_INIT_F
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20))
@@ -261,4 +264,37 @@
#define CONFIG_USB_GADGET_S3C_UDC_OTG
#define CONFIG_USB_GADGET_DUALSPEED
/*
* SPI Settings
*/
#define CONFIG_SOFT_SPI
#define CONFIG_SOFT_SPI_MODE SPI_MODE_3
#define CONFIG_SOFT_SPI_GPIO_SCLK exynos4_gpio_part2_get_nr(y3, 1)
#define CONFIG_SOFT_SPI_GPIO_MOSI exynos4_gpio_part2_get_nr(y3, 3)
#define CONFIG_SOFT_SPI_GPIO_MISO exynos4_gpio_part2_get_nr(y3, 0)
#define CONFIG_SOFT_SPI_GPIO_CS exynos4_gpio_part2_get_nr(y4, 3)
#define SPI_DELAY udelay(1)
#undef SPI_INIT
#define SPI_SCL(bit) universal_spi_scl(bit)
#define SPI_SDA(bit) universal_spi_sda(bit)
#define SPI_READ universal_spi_read()
#ifndef __ASSEMBLY__
void universal_spi_scl(int bit);
void universal_spi_sda(int bit);
int universal_spi_read(void);
#endif
/*
* LCD Settings
*/
#define CONFIG_EXYNOS_FB
#define CONFIG_LCD
#define CONFIG_CMD_BMP
#define CONFIG_BMP_32BPP
#define CONFIG_LD9040
#define CONFIG_EXYNOS_MIPI_DSIM
#define CONFIG_VIDEO_BMP_GZIP
#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((520 * 120 * 4) + (1 << 12))
#endif /* __CONFIG_H */

16
include/configs/seaboard.h
View File

@@ -54,6 +54,7 @@
#define CONFIG_MACH_TYPE MACH_TYPE_SEABOARD
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_LATE_INIT /* Make sure LCD init is complete */
/* I2C */
#define CONFIG_TEGRA_I2C
@@ -71,8 +72,11 @@
#define CONFIG_DOS_PARTITION
#define CONFIG_EFI_PARTITION
#define CONFIG_FS_EXT4
#define CONFIG_FS_FAT
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#define CONFIG_CMD_FS_GENERIC
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_ENV_IS_IN_MMC
@@ -102,7 +106,13 @@
/* USB keyboard */
#define CONFIG_USB_KEYBOARD
#include "tegra-common-post.h"
/* LCD support */
#define CONFIG_LCD
#define CONFIG_PWM_TEGRA
#define CONFIG_VIDEO_TEGRA
#define LCD_BPP LCD_COLOR16
#define CONFIG_SYS_WHITE_ON_BLACK
#define CONFIG_CONSOLE_SCROLL_LINES 10
/* NAND support */
#define CONFIG_CMD_NAND
@@ -111,6 +121,6 @@
/* Max number of NAND devices */
#define CONFIG_SYS_MAX_NAND_DEVICE 1
/* Somewhat oddly, the NAND base address must be a config option */
#define CONFIG_SYS_NAND_BASE NV_PA_NAND_BASE
#include "tegra-common-post.h"
#endif /* __CONFIG_H */

74
include/configs/smdk5250.h
View File

@@ -65,7 +65,7 @@
#define INFORM1_OFFSET 0x804
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20))
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (4 << 20))
/* select serial console configuration */
#define CONFIG_SERIAL3 /* use SERIAL 3 */
@@ -163,7 +163,6 @@
#undef CONFIG_CMD_IMLS
#define CONFIG_IDENT_STRING " for SMDK5250"
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_SECURE_BL1_ONLY
@@ -188,6 +187,11 @@
/* U-boot copy size from boot Media to DRAM.*/
#define BL2_START_OFFSET (CONFIG_BL2_OFFSET/512)
#define BL2_SIZE_BLOC_COUNT (CONFIG_BL2_SIZE/512)
#define OM_STAT (0x1f << 1)
#define EXYNOS_COPY_SPI_FNPTR_ADDR 0x02020058
#define SPI_FLASH_UBOOT_POS (CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE)
#define CONFIG_DOS_PARTITION
#define CONFIG_IRAM_STACK 0x02050000
@@ -205,6 +209,58 @@
#define CONFIG_SYS_I2C_SLAVE 0x0
#define CONFIG_I2C_EDID
/* PMIC */
#define CONFIG_PMIC
#define CONFIG_PMIC_I2C
#define CONFIG_PMIC_MAX77686
/* SPI */
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_SPI_FLASH
#ifdef CONFIG_SPI_FLASH
#define CONFIG_EXYNOS_SPI
#define CONFIG_CMD_SF
#define CONFIG_CMD_SPI
#define CONFIG_SPI_FLASH_WINBOND
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
#define CONFIG_SF_DEFAULT_SPEED 50000000
#define EXYNOS5_SPI_NUM_CONTROLLERS 5
#endif
#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SPI_MODE SPI_MODE_0
#define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
#define CONFIG_ENV_SPI_BUS 1
#define CONFIG_ENV_SPI_MAX_HZ 50000000
#endif
/* PMIC */
#define CONFIG_POWER
#define CONFIG_POWER_I2C
#define CONFIG_POWER_MAX77686
/* SPI */
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_SPI_FLASH
#ifdef CONFIG_SPI_FLASH
#define CONFIG_EXYNOS_SPI
#define CONFIG_CMD_SF
#define CONFIG_CMD_SPI
#define CONFIG_SPI_FLASH_WINBOND
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
#define CONFIG_SF_DEFAULT_SPEED 50000000
#define EXYNOS5_SPI_NUM_CONTROLLERS 5
#endif
#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SPI_MODE SPI_MODE_0
#define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
#define CONFIG_ENV_SPI_BUS 1
#define CONFIG_ENV_SPI_MAX_HZ 50000000
#endif
/* Ethernet Controllor Driver */
#ifdef CONFIG_CMD_NET
#define CONFIG_SMC911X
@@ -213,6 +269,20 @@
#define CONFIG_ENV_SROM_BANK 1
#endif /*CONFIG_CMD_NET*/
/* Enable PXE Support */
#ifdef CONFIG_CMD_NET
#define CONFIG_CMD_PXE
#define CONFIG_MENU
#endif
/* Sound */
#define CONFIG_CMD_SOUND
#ifdef CONFIG_CMD_SOUND
#define CONFIG_SOUND
#define CONFIG_I2S
#define CONFIG_SOUND_WM8994
#endif
/* Enable devicetree support */
#define CONFIG_OF_LIBFDT

1
include/configs/tec.h
View File

@@ -54,7 +54,6 @@
#define CONFIG_CMD_NAND
#define CONFIG_TEGRA_NAND
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE NV_PA_NAND_BASE
/* Environment in NAND, aligned to start of last sector */
#define CONFIG_ENV_IS_IN_NAND

43
include/configs/tegra-common-post.h
View File

@@ -30,18 +30,6 @@
#else
#ifdef CONFIG_CMD_EXT2
#define BOOT_FSTYPE_EXT2 "ext2 "
#else
#define BOOT_FSTYPE_EXT2 ""
#endif
#ifdef CONFIG_CMD_FAT
#define BOOT_FSTYPE_FAT "fat"
#else
#define BOOT_FSTYPE_FAT ""
#endif
#ifdef CONFIG_CMD_MMC
#define BOOTCMDS_MMC \
"mmc_boot=" \
@@ -98,7 +86,7 @@
"rootpart=1\0" \
\
"script_boot=" \
"if ${fs}load ${devtype} ${devnum}:${rootpart} " \
"if load ${devtype} ${devnum}:${rootpart} " \
"${scriptaddr} ${prefix}${script}; then " \
"echo ${script} found! Executing ...;" \
"source ${scriptaddr};" \
@@ -106,11 +94,9 @@
\
"scan_boot=" \
"echo Scanning ${devtype} ${devnum}...; " \
"for fs in ${boot_fstypes}; do " \
"for prefix in ${boot_prefixes}; do " \
"for script in ${boot_scripts}; do " \
"run script_boot; " \
"done; " \
"for prefix in ${boot_prefixes}; do " \
"for script in ${boot_scripts}; do " \
"run script_boot; " \
"done; " \
"done;\0" \
\
@@ -120,11 +106,6 @@
BOOT_TARGETS_DHCP " " \
"\0" \
\
"boot_fstypes=" \
BOOT_FSTYPE_EXT2 " " \
BOOT_FSTYPE_FAT " " \
"\0" \
\
"boot_prefixes=/ /boot/\0" \
\
"boot_scripts=boot.scr.uimg boot.scr\0" \
@@ -181,8 +162,8 @@
#define TEGRA_DEVICE_SETTINGS \
"stdin=serial" STDIN_KBD_KBC STDIN_KBD_USB "\0" \
"stdout=serial\0" \
"stderr=serial\0" \
"stdout=serial,lcd\0" \
"stderr=serial,lcd\0" \
#define CONFIG_EXTRA_ENV_SETTINGS \
TEGRA_DEVICE_SETTINGS \
@@ -226,12 +207,24 @@
#ifdef CONFIG_EFI_PARTITION
#undef CONFIG_EFI_PARTITION
#endif
#ifdef CONFIG_CMD_FS_GENERIC
#undef CONFIG_CMD_FS_GENERIC
#endif
#ifdef CONFIG_CMD_EXT4
#undef CONFIG_CMD_EXT4
#endif
#ifdef CONFIG_CMD_EXT2
#undef CONFIG_CMD_EXT2
#endif
#ifdef CONFIG_CMD_FAT
#undef CONFIG_CMD_FAT
#endif
#ifdef CONFIG_FS_EXT4
#undef CONFIG_FS_EXT4
#endif
#ifdef CONFIG_FS_FAT
#undef CONFIG_FS_FAT
#endif
/* remove USB */
#ifdef CONFIG_USB_EHCI

3
include/configs/tegra20-common.h
View File

@@ -38,6 +38,9 @@
#include <asm/arch/tegra.h> /* get chip and board defs */
/* Align LCD to 1MB boundary */
#define CONFIG_LCD_ALIGNMENT MMU_SECTION_SIZE
/*
* Display CPU and Board information
*/

17
include/configs/trats.h
View File

@@ -211,12 +211,17 @@
#define CONFIG_SYS_HZ 1000
/* TRATS has 2 banks of DRAM */
#define CONFIG_NR_DRAM_BANKS 2
#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* LDDDR2 DMC 0 */
#define PHYS_SDRAM_1_SIZE (512 << 20) /* 512 MB in CS 0 */
#define PHYS_SDRAM_2 0x50000000 /* LPDDR2 DMC 1 */
#define PHYS_SDRAM_2_SIZE (512 << 20) /* 512 MB in CS 0 */
/* TRATS has 4 banks of DRAM */
#define CONFIG_NR_DRAM_BANKS 4
#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */
#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE
#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE
#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE
#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE
#define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */

4
include/configs/trimslice.h
View File

@@ -69,8 +69,11 @@
#define CONFIG_DOS_PARTITION
#define CONFIG_EFI_PARTITION
#define CONFIG_FS_EXT4
#define CONFIG_FS_FAT
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#define CONFIG_CMD_FS_GENERIC
/* Environment in SPI */
#define CONFIG_ENV_IS_IN_SPI_FLASH
@@ -80,6 +83,7 @@
#define CONFIG_ENV_OFFSET (512 * 1024)
/* USB Host support */
#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_TEGRA
#define CONFIG_USB_STORAGE

3
include/configs/ventana.h
View File

@@ -52,8 +52,11 @@
#define CONFIG_DOS_PARTITION
#define CONFIG_EFI_PARTITION
#define CONFIG_FS_EXT4
#define CONFIG_FS_FAT
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#define CONFIG_CMD_FS_GENERIC
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_ENV_IS_IN_MMC

1
include/configs/vision2.h
View File

@@ -196,6 +196,7 @@
/* 166 MHz DDR RAM */
#define CONFIG_SYS_DDR_CLKSEL 0
#define CONFIG_SYS_CLKTL_CBCDR 0x19239100
#define CONFIG_SYS_MAIN_PWR_ON
#define CONFIG_SYS_NO_FLASH

3
include/configs/whistler.h
View File

@@ -61,8 +61,11 @@
#define CONFIG_DOS_PARTITION
#define CONFIG_EFI_PARTITION
#define CONFIG_FS_EXT4
#define CONFIG_FS_FAT
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#define CONFIG_CMD_FS_GENERIC
/*
* Environment in eMMC, at the end of 2nd "boot sector". Note: This assumes

34
include/configs/woodburn.h Normal file
View File

@@ -0,0 +1,34 @@
/*
* (C) Copyright 2011, Stefano Babic <sbabic@denx.de>
*
* (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
*
* Configuration for the woodburn board.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#include <asm/arch/imx-regs.h>
#include "woodburn_common.h"
/* Set TEXT at the beginning of the NOR flash */
#define CONFIG_SYS_TEXT_BASE 0xA0000000
#define CONFIG_BOARD_EARLY_INIT_F
#endif /* __CONFIG_H */

313
include/configs/woodburn_common.h Normal file
View File

@@ -0,0 +1,313 @@
/*
* (C) Copyright 2011, Stefano Babic <sbabic@denx.de>
*
* (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
*
* Configuration for the woodburn board.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __WOODBURN_COMMON_CONFIG_H
#define __WOODBURN_COMMON_CONFIG_H
#include <asm/arch/imx-regs.h>
/* High Level Configuration Options */
#define CONFIG_ARM1136 /* This is an arm1136 CPU core */
#define CONFIG_MX35
#define CONFIG_MX35_HCLK_FREQ 24000000
#define CONFIG_SYS_DCACHE_OFF
#define CONFIG_SYS_CACHELINE_SIZE 32
#define CONFIG_DISPLAY_CPUINFO
/* Only in case the value is not present in mach-types.h */
#ifndef MACH_TYPE_FLEA3
#define MACH_TYPE_FLEA3 3668
#endif
#define CONFIG_MACH_TYPE MACH_TYPE_FLEA3
/* This is required to setup the ESDC controller */
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
#define CONFIG_REVISION_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
/*
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
/*
* Hardware drivers
*/
#define CONFIG_HARD_I2C
#define CONFIG_I2C_MXC
#define CONFIG_SYS_I2C_BASE I2C1_BASE_ADDR
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_MXC_SPI
#define CONFIG_MXC_GPIO
/* PMIC Controller */
#define CONFIG_POWER
#define CONFIG_POWER_I2C
#define CONFIG_POWER_FSL
#define CONFIG_PMIC_FSL_MC13892
#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x8
#define CONFIG_RTC_MC13XXX
/* mmc driver */
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_ESDHC_NUM 1
/*
* UART (console)
*/
#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE UART1_BASE
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_CONS_INDEX 1
#define CONFIG_BAUDRATE 115200
/*
* Command definition
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_PING
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_DNS
#define CONFIG_CMD_NAND
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_I2C
#define CONFIG_CMD_SPI
#define CONFIG_CMD_MII
#define CONFIG_CMD_NET
#define CONFIG_CMD_MMC
#define CONFIG_DOS_PARTITION
#define CONFIG_EFI_PARTITION
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#define CONFIG_CMD_GPIO
#define CONFIG_MXC_GPIO
#define CONFIG_NET_RETRY_COUNT 100
#define CONFIG_BOOTDELAY 3
#define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */
/*
* Ethernet on SOC (FEC)
*/
#define CONFIG_FEC_MXC
#define IMX_FEC_BASE FEC_BASE_ADDR
#define CONFIG_PHYLIB
#define CONFIG_PHY_MICREL
#define CONFIG_FEC_MXC_PHYADDR 0x1
#define CONFIG_MII
#define CONFIG_DISCOVER_PHY
#define CONFIG_ARP_TIMEOUT 200UL
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_PROMPT "woodburn U-Boot > "
#define CONFIG_CMDLINE_EDITING
#define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x10000
#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_SYS_HZ 1000
/*
* Stack sizes
*
* The stack sizes are set up in start.S using the settings below
*/
#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
/*
* Physical Memory Map
*/
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM_1 CSD0_BASE_ADDR
#define PHYS_SDRAM_1_SIZE (256 * 1024 * 1024)
#define CONFIG_SYS_SDRAM_BASE CSD0_BASE_ADDR
#define CONFIG_SYS_GBL_DATA_OFFSET (LOW_LEVEL_SRAM_STACK - \
IRAM_BASE_ADDR - \
GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR (IRAM_BASE_ADDR + \
CONFIG_SYS_GBL_DATA_OFFSET)
/*
* MTD Command for mtdparts
*/
#define CONFIG_CMD_MTDPARTS
#define CONFIG_MTD_DEVICE
#define CONFIG_FLASH_CFI_MTD
#define CONFIG_MTD_PARTITIONS
#define MTDIDS_DEFAULT "nand0=mxc_nand,nor0=physmap-flash.0"
#define MTDPARTS_DEFAULT "mtdparts=mxc_nand:50m(root1)," \
"32m(rootfb)," \
"64m(pcache)," \
"64m(app1)," \
"10m(app2),-(spool);" \
"physmap-flash.0:512k(u-boot),64k(env1)," \
"64k(env2),3776k(kernel1),3776k(kernel2)"
/*
* FLASH and environment organization
*/
#define CONFIG_SYS_FLASH_BASE CS0_BASE_ADDR
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
/* Monitor at beginning of flash */
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
#define CONFIG_ENV_SECT_SIZE (128 * 1024)
#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
/* Address and size of Redundant Environment Sector */
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
CONFIG_SYS_MONITOR_LEN)
#define CONFIG_ENV_IS_IN_FLASH
/*
* CFI FLASH driver setup
*/
#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */
#define CONFIG_FLASH_CFI_DRIVER
/* A non-standard buffered write algorithm */
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* faster */
#define CONFIG_SYS_FLASH_PROTECTION /* Use hardware sector protection */
/*
* NAND FLASH driver setup
*/
#define CONFIG_NAND_MXC
#define CONFIG_NAND_MXC_V1_1
#define CONFIG_MXC_NAND_REGS_BASE (NFC_BASE_ADDR)
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE (NFC_BASE_ADDR)
#define CONFIG_MXC_NAND_HWECC
#define CONFIG_SYS_NAND_LARGEPAGE
#if 0
#define CONFIG_MTD_DEBUG
#define CONFIG_MTD_DEBUG_VERBOSE 7
#endif
#define CONFIG_SYS_NAND_ONFI_DETECTION
/*
* Default environment and default scripts
* to update uboot and load kernel
*/
#define xstr(s) str(s)
#define str(s) #s
#define CONFIG_HOSTNAME woodburn
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
"addip_sta=setenv bootargs ${bootargs} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
":${hostname}:${netdev}:off panic=1\0" \
"addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \
"addip=if test -n ${ipdyn};then run addip_dyn;" \
"else run addip_sta;fi\0" \
"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
"addtty=setenv bootargs ${bootargs}" \
" console=ttymxc0,${baudrate}\0" \
"addmisc=setenv bootargs ${bootargs} ${misc}\0" \
"loadaddr=80800000\0" \
"kernel_addr_r=80800000\0" \
"hostname=" xstr(CONFIG_HOSTNAME) "\0" \
"bootfile=" xstr(CONFIG_HOSTNAME) "/uImage\0" \
"ramdisk_file=" xstr(CONFIG_HOSTNAME) "/uRamdisk\0" \
"flash_self=run ramargs addip addtty addmtd addmisc;" \
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
"bootm ${kernel_addr}\0" \
"net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
"run nfsargs addip addtty addmtd addmisc;" \
"bootm ${kernel_addr_r}\0" \
"net_self_load=tftp ${kernel_addr_r} ${bootfile};" \
"tftp ${ramdisk_addr_r} ${ramdisk_file};\0" \
"net_self=if run net_self_load;then " \
"run ramargs addip addtty addmtd addmisc;" \
"bootm ${kernel_addr_r} ${ramdisk_addr_r};" \
"else echo Images not loades;fi\0" \
"u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.bin\0" \
"load=tftp ${loadaddr} ${u-boot}\0" \
"uboot_addr=" xstr(CONFIG_SYS_MONITOR_BASE) "\0" \
"update=protect off ${uboot_addr} +80000;" \
"erase ${uboot_addr} +80000;" \
"cp.b ${loadaddr} ${uboot_addr} ${filesize}\0" \
"upd=if run load;then echo Updating u-boot;if run update;" \
"then echo U-Boot updated;" \
"else echo Error updating u-boot !;" \
"echo Board without bootloader !!;" \
"fi;" \
"else echo U-Boot not downloaded..exiting;fi\0" \
"bootcmd=run net_nfs\0"
#endif /* __CONFIG_H */

60
include/configs/woodburn_sd.h Normal file
View File

@@ -0,0 +1,60 @@
/*
* (C) Copyright 2011, Stefano Babic <sbabic@denx.de>
*
* (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
*
* Configuration for the woodburn board.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#include <asm/arch/imx-regs.h>
#include "woodburn_common.h"
/* Set TEXT in RAM */
#define CONFIG_SYS_TEXT_BASE 0x82000000
#define CONFIG_BOOT_INTERNAL
/*
* SPL
*/
#define CONFIG_SPL
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm1136/u-boot-spl.lds"
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_LIBDISK_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x100 /* address 0x60000 */
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400 /* 512 KB */
#define CONFIG_SPL_GPIO_SUPPORT
#define CONFIG_SPL_TEXT_BASE 0x10002300
#define CONFIG_SPL_MAX_SIZE (64 * 1024) /* 8 KB for stack */
#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
#define CONFIG_SYS_SPL_MALLOC_START 0x8f000000
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
#define CONFIG_SPL_BSS_START_ADDR 0x8f080000 /* end of RAM */
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
#endif /* __CONFIG_H */

3
include/configs/zipitz2.h
View File

@@ -41,6 +41,9 @@
#define CONFIG_ENV_ADDR 0x40000
#define CONFIG_ENV_SIZE 0x20000
/* we will never enable dcache, because we have to setup MMU first */
#define CONFIG_SYS_DCACHE_OFF
#define CONFIG_SYS_MALLOC_LEN (128*1024)
#define CONFIG_ARCH_CPU_INIT

6
include/configs/zmx25.h
View File

@@ -109,9 +109,9 @@
#define CONFIG_USB_EHCI /* Enable EHCI USB support */
#define CONFIG_USB_EHCI_MXC
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_MXC_USB_PORT 2
#define CONFIG_MXC_USB_PORTSC 0xC0000000
#define CONFIG_MXC_USB_FLAGS 0
#define CONFIG_MXC_USB_PORT 1
#define CONFIG_MXC_USB_PORTSC MXC_EHCI_MODE_SERIAL
#define CONFIG_MXC_USB_FLAGS (MXC_EHCI_INTERNAL_PHY | MXC_EHCI_IPPUE_DOWN)
#define CONFIG_EHCI_IS_TDI
#define CONFIG_USB_STORAGE
#define CONFIG_DOS_PARTITION

2
include/fdtdec.h
View File

@@ -68,6 +68,8 @@ enum fdt_compat_id {
COMPAT_NVIDIA_TEGRA20_EMC_TABLE, /* Tegra20 memory timing table */
COMPAT_NVIDIA_TEGRA20_KBC, /* Tegra20 Keyboard */
COMPAT_NVIDIA_TEGRA20_NAND, /* Tegra2 NAND controller */
COMPAT_NVIDIA_TEGRA20_PWM, /* Tegra 2 PWM controller */
COMPAT_NVIDIA_TEGRA20_DC, /* Tegra 2 Display controller */
COMPAT_COUNT,
};

127
include/i2s.h Normal file
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@@ -0,0 +1,127 @@
/*
* Copyright (C) 2012 Samsung Electronics
* R. Chandrasekar <rcsekar@samsung.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __I2S_H__
#define __I2S_H__
/*
* DAI hardware audio formats.
*
* Describes the physical PCM data formating and clocking. Add new formats
* to the end.
*/
#define SND_SOC_DAIFMT_I2S 1 /* I2S mode */
#define SND_SOC_DAIFMT_RIGHT_J 2 /* Right Justified mode */
#define SND_SOC_DAIFMT_LEFT_J 3 /* Left Justified mode */
#define SND_SOC_DAIFMT_DSP_A 4 /* L data MSB after FRM LRC */
#define SND_SOC_DAIFMT_DSP_B 5 /* L data MSB during FRM LRC */
#define SND_SOC_DAIFMT_AC97 6 /* AC97 */
#define SND_SOC_DAIFMT_PDM 7 /* Pulse density modulation */
/* left and right justified also known as MSB and LSB respectively */
#define SND_SOC_DAIFMT_MSB SND_SOC_DAIFMT_LEFT_J
#define SND_SOC_DAIFMT_LSB SND_SOC_DAIFMT_RIGHT_J
/*
* DAI hardware signal inversions.
*
* Specifies whether the DAI can also support inverted clocks for the specified
* format.
*/
#define SND_SOC_DAIFMT_NB_NF (1 << 8) /* normal bit clock + frame */
#define SND_SOC_DAIFMT_NB_IF (2 << 8) /* normal BCLK + inv FRM */
#define SND_SOC_DAIFMT_IB_NF (3 << 8) /* invert BCLK + nor FRM */
#define SND_SOC_DAIFMT_IB_IF (4 << 8) /* invert BCLK + FRM */
/*
* DAI hardware clock masters.
*
* This is wrt the codec, the inverse is true for the interface
* i.e. if the codec is clk and FRM master then the interface is
* clk and frame slave.
*/
#define SND_SOC_DAIFMT_CBM_CFM (1 << 12) /* codec clk & FRM master */
#define SND_SOC_DAIFMT_CBS_CFM (2 << 12) /* codec clk slave & FRM master */
#define SND_SOC_DAIFMT_CBM_CFS (3 << 12) /* codec clk master & frame slave */
#define SND_SOC_DAIFMT_CBS_CFS (4 << 12) /* codec clk & FRM slave */
#define SND_SOC_DAIFMT_FORMAT_MASK 0x000f
#define SND_SOC_DAIFMT_CLOCK_MASK 0x00f0
#define SND_SOC_DAIFMT_INV_MASK 0x0f00
#define SND_SOC_DAIFMT_MASTER_MASK 0xf000
/*
* Master Clock Directions
*/
#define SND_SOC_CLOCK_IN 0
#define SND_SOC_CLOCK_OUT 1
/* I2S Tx Control */
#define I2S_TX_ON 1
#define I2S_TX_OFF 0
#define FIFO_LENGTH 64
/* I2s Registers */
struct i2s_reg {
unsigned int con; /* base + 0 , Control register */
unsigned int mod; /* Mode register */
unsigned int fic; /* FIFO control register */
unsigned int psr; /* Reserved */
unsigned int txd; /* Transmit data register */
unsigned int rxd; /* Receive Data Register */
};
/* This structure stores the i2s related information */
struct i2stx_info {
unsigned int rfs; /* LR clock frame size */
unsigned int bfs; /* Bit slock frame size */
unsigned int audio_pll_clk; /* Audio pll frequency in Hz */
unsigned int samplingrate; /* sampling rate */
unsigned int bitspersample; /* bits per sample */
unsigned int channels; /* audio channels */
unsigned int base_address; /* I2S Register Base */
};
/*
* Sends the given data through i2s tx
*
* @param pi2s_tx pointer of i2s transmitter parameter structure.
* @param data address of the data buffer
* @param data_size array size of the int buffer (total size / size of int)
*
* @return int value 0 for success, -1 in case of error
*/
int i2s_transfer_tx_data(struct i2stx_info *pi2s_tx, unsigned *data,
unsigned long data_size);
/*
* Initialise i2s transmiter
*
* @param pi2s_tx pointer of i2s transmitter parameter structure.
*
* @return int value 0 for success, -1 in case of error
*/
int i2s_tx_init(struct i2stx_info *pi2s_tx);
#endif /* __I2S_H__ */

11
include/lcd.h
View File

@@ -57,6 +57,14 @@ extern void lcd_initcolregs (void);
extern struct bmp_image *gunzip_bmp(unsigned long addr, unsigned long *lenp);
extern int bmp_display(ulong addr, int x, int y);
/**
* Set whether we need to flush the dcache when changing the LCD image. This
* defaults to off.
*
* @param flush non-zero to flush cache after update, 0 to skip
*/
void lcd_set_flush_dcache(int flush);
#if defined CONFIG_MPC823
/*
* LCD controller stucture for MPC823 CPU
@@ -333,6 +341,9 @@ void lcd_position_cursor(unsigned col, unsigned row);
/* Allow boards to customize the information displayed */
void lcd_show_board_info(void);
/* Return the size of the LCD frame buffer, and the line length */
int lcd_get_size(int *line_length);
/************************************************************************/
/* ** BITMAP DISPLAY SUPPORT */
/************************************************************************/

32
include/ld9040.h Normal file
View File

@@ -0,0 +1,32 @@
/*
* ld9040 AMOLED LCD panel driver.
*
* Copyright (C) 2012 Samsung Electronics
* Donghwa Lee <dh09.lee@samsung.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __LD9040_H_
#define __LD9040_H_
void ld9040_cfg_ldo(void);
void ld9040_enable_ldo(unsigned int onoff);
#endif /* __LD9040_H_ */

49
include/mc34704.h Normal file
View File

@@ -0,0 +1,49 @@
/*
* (C) Copyright 2012 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
*/
#ifndef __MC34704_H__
#define __MC34704_H__
enum {
MC34704_RESERVED0_REG = 0, /* 0x00 */
MC34704_GENERAL1_REG, /* 0x01 */
MC34704_GENERAL2_REG, /* 0x02 */
MC34704_GENERAL3_REG, /* 0x03 */
MC34704_RESERVED4_REG, /* 0x04 */
MC34704_VGSET2_REG, /* 0x05 */
MC34704_REG2SET1_REG, /* 0x06 */
MC34704_REG2SET2_REG, /* 0x07 */
MC34704_REG3SET1_REG, /* 0x08 */
MC34704_REG3SET2_REG, /* 0x09 */
MC34704_REG4SET1_REG, /* 0x0a */
MC34704_REG4SET2_REG, /* 0x0b */
MC34704_REG5SET1_REG, /* 0x0c */
MC34704_REG5SET2_REG, /* 0x0d */
MC34704_REG5SET3_REG, /* 0x0e */
MC34704_RESERVEDF_REG, /* 0x0f */
MC34704_RESERVED10_REG, /* 0x10 */
MC34704_RESERVED11_REG, /* 0x11 */
MC34704_RESERVED12_REG, /* 0x12 */
MC34704_FSW2SET_REG, /* 0x13 */
MC34704_RESERVED14_REG, /* 0x14 */
MC34704_REG8SET1_REG, /* 0x15 */
MC34704_REG8SET2_REG, /* 0x16 */
MC34704_REG8SET3_REG, /* 0x17 */
MC34704_FAULTS_REG, /* 0x18 */
MC34704_I2CSET1, /* 0x19 */
MC34704_NUM_OF_REGS,
};
/* GENERAL2 register fields */
#define ONOFFE (1 << 0)
#define ONOFFD (1 << 1)
#define ALLOFF (1 << 4)
#endif /* __MC34704_H__ */

158
include/power/max77686_pmic.h Normal file
View File

@@ -0,0 +1,158 @@
/*
* Copyright (C) 2012 Samsung Electronics
* Rajeshwari Shinde <rajeshwari.s@samsung.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __MAX77686_H_
#define __MAX77686_H_
enum {
MAX77686_REG_PMIC_ID = 0x0,
MAX77686_REG_PMIC_INTSRC,
MAX77686_REG_PMIC_INT1,
MAX77686_REG_PMIC_INT2,
MAX77686_REG_PMIC_INT1MSK,
MAX77686_REG_PMIC_INT2MSK,
MAX77686_REG_PMIC_STATUS1,
MAX77686_REG_PMIC_STATUS2,
MAX77686_REG_PMIC_PWRON,
MAX77686_REG_PMIC_ONOFFDELAY,
MAX77686_REG_PMIC_MRSTB,
MAX77686_REG_PMIC_BUCK1CRTL = 0x10,
MAX77686_REG_PMIC_BUCK1OUT,
MAX77686_REG_PMIC_BUCK2CTRL1,
MAX77686_REG_PMIC_BUCK234FREQ,
MAX77686_REG_PMIC_BUCK2DVS1,
MAX77686_REG_PMIC_BUCK2DVS2,
MAX77686_REG_PMIC_BUCK2DVS3,
MAX77686_REG_PMIC_BUCK2DVS4,
MAX77686_REG_PMIC_BUCK2DVS5,
MAX77686_REG_PMIC_BUCK2DVS6,
MAX77686_REG_PMIC_BUCK2DVS7,
MAX77686_REG_PMIC_BUCK2DVS8,
MAX77686_REG_PMIC_BUCK3CTRL,
MAX77686_REG_PMIC_BUCK3DVS1,
MAX77686_REG_PMIC_BUCK3DVS2,
MAX77686_REG_PMIC_BUCK3DVS3,
MAX77686_REG_PMIC_BUCK3DVS4,
MAX77686_REG_PMIC_BUCK3DVS5,
MAX77686_REG_PMIC_BUCK3DVS6,
MAX77686_REG_PMIC_BUCK3DVS7,
MAX77686_REG_PMIC_BUCK3DVS8,
MAX77686_REG_PMIC_BUCK4CTRL1,
MAX77686_REG_PMIC_BUCK4DVS1 = 0x28,
MAX77686_REG_PMIC_BUCK4DVS2,
MAX77686_REG_PMIC_BUCK4DVS3,
MAX77686_REG_PMIC_BUCK4DVS4,
MAX77686_REG_PMIC_BUCK4DVS5,
MAX77686_REG_PMIC_BUCK4DVS6,
MAX77686_REG_PMIC_BUCK4DVS7,
MAX77686_REG_PMIC_BUCK4DVS8,
MAX77686_REG_PMIC_BUCK5CTRL,
MAX77686_REG_PMIC_BUCK5OUT,
MAX77686_REG_PMIC_BUCK6CRTL,
MAX77686_REG_PMIC_BUCK6OUT,
MAX77686_REG_PMIC_BUCK7CRTL,
MAX77686_REG_PMIC_BUCK7OUT,
MAX77686_REG_PMIC_BUCK8CRTL,
MAX77686_REG_PMIC_BUCK8OUT,
MAX77686_REG_PMIC_BUCK9CRTL,
MAX77686_REG_PMIC_BUCK9OUT,
MAX77686_REG_PMIC_LDO1CTRL1 = 0x40,
MAX77686_REG_PMIC_LDO2CTRL1,
MAX77686_REG_PMIC_LDO3CTRL1,
MAX77686_REG_PMIC_LDO4CTRL1,
MAX77686_REG_PMIC_LDO5CTRL1,
MAX77686_REG_PMIC_LDO6CTRL1,
MAX77686_REG_PMIC_LDO7CTRL1,
MAX77686_REG_PMIC_LDO8CTRL1,
MAX77686_REG_PMIC_LDO9CTRL1,
MAX77686_REG_PMIC_LDO10CTRL1,
MAX77686_REG_PMIC_LDO11CTRL1,
MAX77686_REG_PMIC_LDO12CTRL1,
MAX77686_REG_PMIC_LDO13CTRL1,
MAX77686_REG_PMIC_LDO14CTRL1,
MAX77686_REG_PMIC_LDO15CTRL1,
MAX77686_REG_PMIC_LDO16CTRL1,
MAX77686_REG_PMIC_LDO17CTRL1,
MAX77686_REG_PMIC_LDO18CTRL1,
MAX77686_REG_PMIC_LDO19CTRL1,
MAX77686_REG_PMIC_LDO20CTRL1,
MAX77686_REG_PMIC_LDO21CTRL1,
MAX77686_REG_PMIC_LDO22CTRL1,
MAX77686_REG_PMIC_LDO23CTRL1,
MAX77686_REG_PMIC_LDO24CTRL1,
MAX77686_REG_PMIC_LDO25CTRL1,
MAX77686_REG_PMIC_LDO26CTRL1,
MAX77686_REG_PMIC_LDO1CTRL2,
MAX77686_REG_PMIC_LDO2CTRL2,
MAX77686_REG_PMIC_LDO3CTRL2,
MAX77686_REG_PMIC_LDO4CTRL2,
MAX77686_REG_PMIC_LDO5CTRL2,
MAX77686_REG_PMIC_LDO6CTRL2,
MAX77686_REG_PMIC_LDO7CTRL2,
MAX77686_REG_PMIC_LDO8CTRL2,
MAX77686_REG_PMIC_LDO9CTRL2,
MAX77686_REG_PMIC_LDO10CTRL2,
MAX77686_REG_PMIC_LDO11CTRL2,
MAX77686_REG_PMIC_LDO12CTRL2,
MAX77686_REG_PMIC_LDO13CTRL2,
MAX77686_REG_PMIC_LDO14CTRL2,
MAX77686_REG_PMIC_LDO15CTRL2,
MAX77686_REG_PMIC_LDO16CTRL2,
MAX77686_REG_PMIC_LDO17CTRL2,
MAX77686_REG_PMIC_LDO18CTRL2,
MAX77686_REG_PMIC_LDO19CTRL2,
MAX77686_REG_PMIC_LDO20CTRL2,
MAX77686_REG_PMIC_LDO21CTRL2,
MAX77686_REG_PMIC_LDO22CTRL2,
MAX77686_REG_PMIC_LDO23CTRL2,
MAX77686_REG_PMIC_LDO24CTRL2,
MAX77686_REG_PMIC_LDO25CTRL2,
MAX77686_REG_PMIC_LDO26CTRL2,
MAX77686_REG_PMIC_BBAT = 0x7e,
MAX77686_REG_PMIC_32KHZ,
PMIC_NUM_OF_REGS,
};
/* I2C device address for pmic max77686 */
#define MAX77686_I2C_ADDR (0x12 >> 1)
enum {
REG_DISABLE = 0,
REG_ENABLE
};
enum {
LDO_OFF = 0,
LDO_ON,
DIS_LDO = (0x00 << 6),
EN_LDO = (0x3 << 6),
};
#endif /* __MAX77686_PMIC_H_ */

2
include/power/max8998_pmic.h
View File

@@ -76,7 +76,9 @@ enum {
#define MAX8998_LDO3 (1 << 2)
#define MAX8998_LDO4 (1 << 1)
#define MAX8998_LDO7 (1 << 6)
#define MAX8998_LDO8 (1 << 5)
#define MAX8998_LDO17 (1 << 4)
#define MAX8998_SAFEOUT1 (1 << 4)
#define MAX8998_I2C_ADDR (0xCC >> 1)

62
include/sound.h Normal file
View File

@@ -0,0 +1,62 @@
/*
* Copyright (C) 2012 Samsung Electronics
* R. Chandrasekar < rcsekar@samsung.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __SOUND_H__
#define __SOUND_H__
/* sound codec enum */
enum en_sound_codec {
CODEC_WM_8994,
CODEC_WM_8995,
CODEC_MAX
};
/* sound codec enum */
enum sound_compat {
AUDIO_COMPAT_SPI,
AUDIO_COMPAT_I2C,
};
/* Codec information structure to store the info from device tree */
struct sound_codec_info {
int i2c_bus;
int i2c_dev_addr;
enum en_sound_codec codec_type;
};
/*
* Initialises audio sub system
*
* @return int value 0 for success, -1 for error
*/
int sound_init(void);
/*
* plays the pcm data buffer in pcm_data.h through i2s1 to make the
* sine wave sound
*
* @return int 0 for success, -1 for error
*/
int sound_play(uint32_t msec, uint32_t frequency);
#endif /* __SOUND__H__ */

28
include/usb/ehci-fsl.h
View File

@@ -246,9 +246,33 @@ struct usb_ehci {
/*
* For MXC SOCs
*/
/* values for portsc field */
#define MXC_EHCI_PHY_LOW_POWER_SUSPEND (1 << 23)
#define MXC_EHCI_FORCE_FS (1 << 24)
#define MXC_EHCI_UTMI_8BIT (0 << 28)
#define MXC_EHCI_UTMI_16BIT (1 << 28)
#define MXC_EHCI_SERIAL (1 << 29)
#define MXC_EHCI_MODE_UTMI (0 << 30)
#define MXC_EHCI_MODE_PHILIPS (1 << 30)
#define MXC_EHCI_MODE_ULPI (2 << 30)
#define MXC_EHCI_MODE_SERIAL (3 << 30)
/* values for flags field */
#define MXC_EHCI_INTERFACE_DIFF_UNI (0 << 0)
#define MXC_EHCI_INTERFACE_DIFF_BI (1 << 0)
#define MXC_EHCI_INTERFACE_SINGLE_UNI (2 << 0)
#define MXC_EHCI_INTERFACE_SINGLE_BI (3 << 0)
#define MXC_EHCI_INTERFACE_MASK (0xf)
#define MXC_EHCI_POWER_PINS_ENABLED (1 << 5)
#define MXC_EHCI_TTL_ENABLED (1 << 6)
#define MXC_EHCI_INTERNAL_PHY (1 << 7)
#define MXC_EHCI_PWR_PIN_ACTIVE_HIGH (1 << 6)
#define MXC_EHCI_OC_PIN_ACTIVE_LOW (1 << 7)
#define MXC_EHCI_TTL_ENABLED (1 << 8)
#define MXC_EHCI_INTERNAL_PHY (1 << 9)
#define MXC_EHCI_IPPUE_DOWN (1 << 10)
#define MXC_EHCI_IPPUE_UP (1 << 11)
/* Board-specific initialization */
int board_ehci_hcd_init(int port);