* Patch by Jon Loeliger, 2005-05-05

Implemented support for MPC8548CDS board. Added DDR II support based on SPD values for MPC85xx boards. This roll-up patch also includes bugfies for the previously published patches: DDRII CPO, pre eTSEC, 8548 LBIU, Andy's TSEC, eTSEC 3&4 I/O
2005-07-25 14:05:07 -05:00
parent 288693abe1
commit d9b94f28a4
36 changed files with 2612 additions and 392 deletions
--- a/include/asm-ppc/immap_85xx.h
+++ b/include/asm-ppc/immap_85xx.h
@@ -81,21 +81,27 @@ typedef struct ccsr_ddr {
 	uint	cs1_config;		/* 0x2084 - DDR Chip Select Configuration */
 	uint	cs2_config;		/* 0x2088 - DDR Chip Select Configuration */
 	uint	cs3_config;		/* 0x208c - DDR Chip Select Configuration */
-	char	res5[120];
+	char	res5[112];
+	uint	ext_refrec;		/* 0x2100 - DDR SDRAM Extended Refresh Recovery */
+	uint	timing_cfg_0;		/* 0x2104 - DDR SDRAM Timing Configuration Register 0 */
 	uint	timing_cfg_1;		/* 0x2108 - DDR SDRAM Timing Configuration Register 1 */
 	uint	timing_cfg_2;		/* 0x210c - DDR SDRAM Timing Configuration Register 2 */
 	uint	sdram_cfg;		/* 0x2110 - DDR SDRAM Control Configuration */
-	char	res6[4];
+	uint	sdram_cfg_2;		/* 0x2114 - DDR SDRAM Control Configuration 2 */
 	uint	sdram_mode;		/* 0x2118 - DDR SDRAM Mode Configuration */
-	char	res7[8];
+	uint	sdram_mode_2;		/* 0x211c - DDR SDRAM Mode Configuration 2*/
+	uint	sdram_md_cntl;		/* 0x2120 - DDR SDRAM Mode Control */
 	uint	sdram_interval;		/* 0x2124 - DDR SDRAM Interval Configuration */
-#ifdef MPC85xx_DDR_SDRAM_CLK_CNTL
-	char	res7_5[8];
+	uint	sdram_data_init;	/* 0x2128 - DDR SDRAM Data initialization */
+	char	res6[4];
 	uint	sdram_clk_cntl;		/* 0x2130 - DDR SDRAM Clock Control */
-	char	res8[3276];
-#else
-	char	res8[3288];
-#endif
+	char	res7[20];
+	uint	init_address;		/* 0x2148 - DDR training initialization address */
+	uint	init_ext_address;	/* 0x214C - DDR training initialization extended address */
+	char	res8_1[2728];
+	uint	ip_rev1;		/* 0x2BF8 - DDR IP Block Revision 1 */
+	uint	ip_rev2;		/* 0x2BFC - DDR IP Block Revision 2 */
+	char	res8_2[512];
 	uint	data_err_inject_hi;	/* 0x2e00 - DDR Memory Data Path Error Injection Mask High */
 	uint	data_err_inject_lo;	/* 0x2e04 - DDR Memory Data Path Error Injection Mask Low */
 	uint	ecc_err_inject;		/* 0x2e08 - DDR Memory Data Path Error Injection Mask ECC */
@@ -120,6 +126,8 @@ typedef struct ccsr_ddr {
 } ccsr_ddr_t;


+
+
 /* I2C Registers(0x3000-0x4000) */

 typedef struct ccsr_i2c {
@@ -158,6 +166,7 @@ typedef struct ccsr_i2c {

 #if defined(CONFIG_MPC8540) \
 	|| defined(CONFIG_MPC8541) \
+	|| defined(CONFIG_MPC8548) \
 	|| defined(CONFIG_MPC8555)
 /* DUART Registers(0x4000-0x5000) */
 typedef struct ccsr_duart {
@@ -1547,7 +1556,13 @@ typedef struct ccsr_gur {
 	uint	ddrdllcr;	/* 0xe0e10 - DDR DLL control register */
 	char	res12[12];
 	uint	lbcdllcr;	/* 0xe0e20 - LBC DLL control register */
-	char	res13[61915];
+	char	res13[248];
+	uint	lbiuiplldcr0;	/* 0xe0f1c -- LBIU PLL Debug Reg 0 */
+	uint	lbiuiplldcr1;	/* 0xe0f20 -- LBIU PLL Debug Reg 1 */
+	uint	ddrioovcr;	/* 0xe0f24 - DDR IO Override Control */
+	uint	res14;		/* 0xe0f28 */
+	uint	tsec34ioovcr;	/* 0xe0f2c - eTSEC 3/4 IO override control */
+	char	res15[61651];
 } ccsr_gur_t;

 typedef struct immap {
--- a/include/asm-ppc/processor.h
+++ b/include/asm-ppc/processor.h
@@ -420,6 +420,7 @@
 #define SPRN_MAS4       0x274   /* MMU Assist Register 4 */
 #define SPRN_MAS5       0x275   /* MMU Assist Register 5 */
 #define SPRN_MAS6       0x276   /* MMU Assist Register 6 */
+#define SPRN_MAS7	0x3B0	/* MMU Assist Register 7 */

 #define SPRN_IVOR32     0x210   /* Interrupt Vector Offset Register 32 */
 #define SPRN_IVOR33     0x211   /* Interrupt Vector Offset Register 33 */
@@ -584,6 +585,7 @@
 #define MAS4	SPRN_MAS4
 #define MAS5	SPRN_MAS5
 #define MAS6	SPRN_MAS6
+#define MAS7	SPRN_MAS7

 /* Device Control Registers */

@@ -792,6 +794,8 @@
 #define SVR_8560	0x8070
 #define SVR_8555	0x8079
 #define SVR_8541	0x807A
+#define SVR_8548	0x8031
+#define SVR_8548_E	0x8039


 /* I am just adding a single entry for 8260 boards.  I think we may be
--- a/include/configs/MPC8540ADS.h
+++ b/include/configs/MPC8540ADS.h
@@ -49,10 +49,12 @@
 #define CONFIG_TSEC_ENET 		/* tsec ethernet support */
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
-#define CONFIG_DDR_ECC			/* only for ECC DDR module */
 #define CONFIG_DDR_DLL			/* possible DLL fix needed */
 #define CONFIG_DDR_2T_TIMING		/* Sets the 2T timing bit */

+#define CONFIG_DDR_ECC			/* only for ECC DDR module */
+#define CONFIG_MEM_INIT_VALUE		0xDeadBeef
+

 /*
 * sysclk for MPC85xx
@@ -342,7 +344,9 @@

 #define CONFIG_MII		1	/* MII PHY management */
 #define CONFIG_MPC85XX_TSEC1	1
+#define CONFIG_MPC85XX_TSEC1_NAME	"TSEC0"
 #define CONFIG_MPC85XX_TSEC2	1
+#define CONFIG_MPC85XX_TSEC2_NAME	"TSEC1"
 #define TSEC1_PHY_ADDR		0
 #define TSEC2_PHY_ADDR		1
 #define TSEC1_PHYIDX		0
@@ -351,11 +355,13 @@

 #if CONFIG_HAS_FEC
 #define CONFIG_MPC85XX_FEC	1
+#define CONFIG_MPC85XX_FEC_NAME		"FEC"
 #define FEC_PHY_ADDR		3
 #define FEC_PHYIDX		0
 #endif

-#define CONFIG_ETHPRIME		"MOTO ENET0"
+/* Options are: TSEC[0-1], FEC */
+#define CONFIG_ETHPRIME		"TSEC0"

 #endif	/* CONFIG_TSEC_ENET */

--- a/include/configs/MPC8541CDS.h
+++ b/include/configs/MPC8541CDS.h
@@ -41,9 +41,12 @@
 #define CONFIG_TSEC_ENET 		/* tsec ethernet support */
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
-#define CONFIG_DDR_ECC			/* only for ECC DDR module */
 #define CONFIG_DDR_DLL			/* possible DLL fix needed */
-#define CONFIG_DDR_2T_TIMING		/* Sets the 2T timing bit */
+#undef CONFIG_DDR_2T_TIMING		/* Sets the 2T timing bit */
+
+#define CONFIG_DDR_ECC			/* only for ECC DDR module */
+#define CONFIG_MEM_INIT_VALUE		0xDeadBeef
+

 /*
 * When initializing flash, if we cannot find the manufacturer ID,
@@ -360,7 +363,9 @@ extern unsigned long get_clock_freq(void);

 #define CONFIG_MII		1	/* MII PHY management */
 #define CONFIG_MPC85XX_TSEC1	1
+#define CONFIG_MPC85XX_TSEC1_NAME	"TSEC0"
 #define CONFIG_MPC85XX_TSEC2	1
+#define CONFIG_MPC85XX_TSEC2_NAME	"TSEC1"
 #undef CONFIG_MPC85XX_FEC
 #define TSEC1_PHY_ADDR		0
 #define TSEC2_PHY_ADDR		1
@@ -368,7 +373,9 @@ extern unsigned long get_clock_freq(void);
 #define TSEC1_PHYIDX		0
 #define TSEC2_PHYIDX		0
 #define FEC_PHYIDX		0
-#define CONFIG_ETHPRIME		"MOTO ENET0"
+
+/* Options are: TSEC[0-1] */
+#define CONFIG_ETHPRIME		"TSEC0"

 #endif	/* CONFIG_TSEC_ENET */

--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -0,0 +1,521 @@
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * mpc8548cds board configuration file
+ *
+ * Please refer to doc/README.mpc85xxcds for more info.
+ *
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE		1	/* BOOKE */
+#define CONFIG_E500		1	/* BOOKE e500 family */
+#define CONFIG_MPC85xx		1	/* MPC8540/60/55/41/48 */
+#define CONFIG_MPC8548		1	/* MPC8548 specific */
+#define CONFIG_MPC8548CDS	1	/* MPC8548CDS board specific */
+
+#undef CONFIG_PCI
+#define CONFIG_TSEC_ENET 		/* tsec ethernet support */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
+#define CONFIG_DDR_DLL			/* possible DLL fix needed */
+#define CONFIG_DDR_2T_TIMING		/* Sets the 2T timing bit */
+
+#define CONFIG_DDR_ECC			/* only for ECC DDR module */
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
+#define CONFIG_MEM_INIT_VALUE		0xDeadBeef
+
+
+/*
+ * When initializing flash, if we cannot find the manufacturer ID,
+ * assume this is the AMD flash associated with the CDS board.
+ * This allows booting from a promjet.
+ */
+#define CONFIG_ASSUME_AMD_FLASH
+
+#define MPC85xx_DDR_SDRAM_CLK_CNTL	/* 85xx has clock control reg */
+
+#ifndef __ASSEMBLY__
+extern unsigned long get_clock_freq(void);
+#endif
+#define CONFIG_SYS_CLK_FREQ	get_clock_freq() /* sysclk for MPC85xx */
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE		    	    /* toggle L2 cache 	*/
+#define CONFIG_BTB			    /* toggle branch predition */
+#define CONFIG_ADDR_STREAMING		    /* toggle addr streaming   */
+
+/*
+ * Only possible on E500 Version 2 or newer cores.
+ */
+#define CONFIG_ENABLE_36BIT_PHYS	1
+
+
+#define CONFIG_BOARD_EARLY_INIT_F	1	/* Call board_pre_init */
+
+#undef	CFG_DRAM_TEST			/* memory test, takes time */
+#define CFG_MEMTEST_START	0x00200000	/* memtest works on */
+#define CFG_MEMTEST_END		0x00400000
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CFG_CCSRBAR_DEFAULT 	0xff700000	/* CCSRBAR Default */
+#define CFG_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
+#define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */
+
+/*
+ * DDR Setup
+ */
+#define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
+#define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
+
+#define SPD_EEPROM_ADDRESS	0x51		/* DDR DIMM */
+
+/*
+ * Make sure required options are set
+ */
+#ifndef CONFIG_SPD_EEPROM
+#error ("CONFIG_SPD_EEPROM is required")
+#endif
+
+#undef CONFIG_CLOCKS_IN_MHZ
+
+
+/*
+ * Local Bus Definitions
+ */
+
+/*
+ * FLASH on the Local Bus
+ * Two banks, 8M each, using the CFI driver.
+ * Boot from BR0/OR0 bank at 0xff00_0000
+ * Alternate BR1/OR1 bank at 0xff80_0000
+ *
+ * BR0, BR1:
+ *    Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
+ *    Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
+ *    Port Size = 16 bits = BRx[19:20] = 10
+ *    Use GPCM = BRx[24:26] = 000
+ *    Valid = BRx[31] = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001    BR0
+ * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001    BR1
+ *
+ * OR0, OR1:
+ *    Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
+ *    Reserved ORx[17:18] = 11, confusion here?
+ *    CSNT = ORx[20] = 1
+ *    ACS = half cycle delay = ORx[21:22] = 11
+ *    SCY = 6 = ORx[24:27] = 0110
+ *    TRLX = use relaxed timing = ORx[29] = 1
+ *    EAD = use external address latch delay = OR[31] = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65    ORx
+ */
+
+#define CFG_FLASH_BASE		0xff000000	/* start of FLASH 8M */
+
+#define CFG_BR0_PRELIM		0xff801001
+#define CFG_BR1_PRELIM		0xff001001
+
+#define	CFG_OR0_PRELIM		0xff806e65
+#define	CFG_OR1_PRELIM		0xff806e65
+
+#define CFG_FLASH_BANKS_LIST	{0xff800000, CFG_FLASH_BASE}
+#define CFG_MAX_FLASH_BANKS	2		/* number of banks */
+#define CFG_MAX_FLASH_SECT	128		/* sectors per device */
+#undef	CFG_FLASH_CHECKSUM
+#define CFG_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#define CFG_MONITOR_BASE    	TEXT_BASE	/* start of monitor */
+
+#define CFG_FLASH_CFI_DRIVER
+#define CFG_FLASH_CFI
+#define CFG_FLASH_EMPTY_INFO
+
+
+/*
+ * SDRAM on the Local Bus
+ */
+#define CFG_LBC_SDRAM_BASE	0xf0000000	/* Localbus SDRAM */
+#define CFG_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */
+
+/*
+ * Base Register 2 and Option Register 2 configure SDRAM.
+ * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000.
+ *
+ * For BR2, need:
+ *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
+ *    port-size = 32-bits = BR2[19:20] = 11
+ *    no parity checking = BR2[21:22] = 00
+ *    SDRAM for MSEL = BR2[24:26] = 011
+ *    Valid = BR[31] = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
+ *
+ * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into
+ * FIXME: the top 17 bits of BR2.
+ */
+
+#define CFG_BR2_PRELIM          0xf0001861
+
+/*
+ * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
+ *
+ * For OR2, need:
+ *    64MB mask for AM, OR2[0:7] = 1111 1100
+ *		   XAM, OR2[17:18] = 11
+ *    9 columns OR2[19-21] = 010
+ *    13 rows   OR2[23-25] = 100
+ *    EAD set for extra time OR[31] = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
+ */
+
+#define CFG_OR2_PRELIM		0xfc006901
+
+#define CFG_LBC_LCRR		0x00030004    /* LB clock ratio reg */
+#define CFG_LBC_LBCR		0x00000000    /* LB config reg */
+#define CFG_LBC_LSRT		0x20000000  /* LB sdram refresh timer */
+#define CFG_LBC_MRTPR		0x00000000  /* LB refresh timer prescal*/
+
+/*
+ * LSDMR masks
+ */
+#define CFG_LBC_LSDMR_RFEN	(1 << (31 -  1))
+#define CFG_LBC_LSDMR_BSMA1516	(3 << (31 - 10))
+#define CFG_LBC_LSDMR_BSMA1617	(4 << (31 - 10))
+#define CFG_LBC_LSDMR_RFCR16	(7 << (31 - 16))
+#define CFG_LBC_LSDMR_PRETOACT7	(7 << (31 - 19))
+#define CFG_LBC_LSDMR_ACTTORW7	(7 << (31 - 22))
+#define CFG_LBC_LSDMR_ACTTORW6	(6 << (31 - 22))
+#define CFG_LBC_LSDMR_BL8	(1 << (31 - 23))
+#define CFG_LBC_LSDMR_WRC4	(0 << (31 - 27))
+#define CFG_LBC_LSDMR_CL3	(3 << (31 - 31))
+
+#define CFG_LBC_LSDMR_OP_NORMAL	(0 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_ARFRSH	(1 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_SRFRSH	(2 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_MRW	(3 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_PRECH	(4 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_PCHALL	(5 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_ACTBNK	(6 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_RWINV	(7 << (31 - 4))
+
+/*
+ * Common settings for all Local Bus SDRAM commands.
+ * At run time, either BSMA1516 (for CPU 1.1)
+ *                  or BSMA1617 (for CPU 1.0) (old)
+ * is OR'ed in too.
+ */
+#define CFG_LBC_LSDMR_COMMON	( CFG_LBC_LSDMR_RFCR16		\
+				| CFG_LBC_LSDMR_PRETOACT7	\
+				| CFG_LBC_LSDMR_ACTTORW7	\
+				| CFG_LBC_LSDMR_BL8		\
+				| CFG_LBC_LSDMR_WRC4		\
+				| CFG_LBC_LSDMR_CL3		\
+				| CFG_LBC_LSDMR_RFEN		\
+				)
+
+/*
+ * The CADMUS registers are connected to CS3 on CDS.
+ * The new memory map places CADMUS at 0xf8000000.
+ *
+ * For BR3, need:
+ *    Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
+ *    port-size = 8-bits  = BR[19:20] = 01
+ *    no parity checking  = BR[21:22] = 00
+ *    GPMC for MSEL       = BR[24:26] = 000
+ *    Valid               = BR[31]    = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
+ *
+ * For OR3, need:
+ *    1 MB mask for AM,   OR[0:16]  = 1111 1111 1111 0000 0
+ *    disable buffer ctrl OR[19]    = 0
+ *    CSNT                OR[20]    = 1
+ *    ACS                 OR[21:22] = 11
+ *    XACS                OR[23]    = 1
+ *    SCY 15 wait states  OR[24:27] = 1111	max is suboptimal but safe
+ *    SETA                OR[28]    = 0
+ *    TRLX                OR[29]    = 1
+ *    EHTR                OR[30]    = 1
+ *    EAD extra time      OR[31]    = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
+ */
+
+#define CADMUS_BASE_ADDR 0xf8000000
+#define CFG_BR3_PRELIM   0xf8000801
+#define CFG_OR3_PRELIM   0xfff00ff7
+
+#define CONFIG_L1_INIT_RAM
+#define CFG_INIT_RAM_LOCK 	1
+#define CFG_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
+#define CFG_INIT_RAM_END    	0x4000	    /* End of used area in RAM */
+
+#define CFG_GBL_DATA_SIZE  	128	    /* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_LEN	    	(256 * 1024) /* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN	    	(128 * 1024)	/* Reserved for malloc */
+
+/* Serial Port */
+#define CONFIG_CONS_INDEX     2
+#undef	CONFIG_SERIAL_SOFTWARE_FIFO
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE    1
+#define CFG_NS16550_CLK		get_bus_freq(0)
+
+#define CFG_BAUDRATE_TABLE  \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+#define CFG_NS16550_COM1        (CFG_CCSRBAR+0x4500)
+#define CFG_NS16550_COM2        (CFG_CCSRBAR+0x4600)
+
+/* Use the HUSH parser */
+#define CFG_HUSH_PARSER
+#ifdef  CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+/* I2C */
+#define CONFIG_HARD_I2C			/* I2C with hardware support */
+#undef	CONFIG_SOFT_I2C			/* I2C bit-banged */
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CFG_I2C_EEPROM_ADDR	0x57
+#define CFG_I2C_SLAVE		0x7F
+#define CFG_I2C_NOPROBES        {0x69}	/* Don't probe these addrs */
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CFG_PCI1_MEM_BASE	0x80000000
+#define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
+#define CFG_PCI1_MEM_SIZE	0x20000000	/* 512M */
+#define CFG_PCI1_IO_BASE	0xe2000000
+#define CFG_PCI1_IO_PHYS	CFG_PCI1_IO_BASE
+#define CFG_PCI1_IO_SIZE	0x1000000	/* 16M */
+
+#define CFG_PCI2_MEM_BASE	0xa0000000
+#define CFG_PCI2_MEM_PHYS	CFG_PCI2_MEM_BASE
+#define CFG_PCI2_MEM_SIZE	0x20000000	/* 512M */
+#define CFG_PCI2_IO_BASE	0xe3000000
+#define CFG_PCI2_IO_PHYS	CFG_PCI2_IO_BASE
+#define CFG_PCI2_IO_SIZE	0x1000000	/* 16M */
+
+
+#if defined(CONFIG_PCI)
+
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP	               	/* do pci plug-and-play */
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_TULIP
+
+#if !defined(CONFIG_PCI_PNP)
+    #define PCI_ENET0_IOADDR      0xe0000000
+    #define PCI_ENET0_MEMADDR     0xe0000000
+    #define PCI_IDSEL_NUMBER      0x0c 	/*slot0->3(IDSEL)=12->15*/
+#endif
+
+#undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+#define CFG_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
+
+#endif	/* CONFIG_PCI */
+
+
+#if defined(CONFIG_TSEC_ENET)
+
+#ifndef CONFIG_NET_MULTI
+#define CONFIG_NET_MULTI 	1
+#endif
+
+#define CONFIG_MII		1	/* MII PHY management */
+#define CONFIG_MPC85XX_TSEC1	1
+#define CONFIG_MPC85XX_TSEC1_NAME	"eTSEC0"
+#define CONFIG_MPC85XX_TSEC2	1
+#define CONFIG_MPC85XX_TSEC2_NAME	"eTSEC1"
+#define CONFIG_MPC85XX_TSEC3	1
+#define CONFIG_MPC85XX_TSEC3_NAME	"eTSEC2"
+#define CONFIG_MPC85XX_TSEC4	1
+#define CONFIG_MPC85XX_TSEC4_NAME	"eTSEC3"
+#undef CONFIG_MPC85XX_FEC
+
+#define TSEC1_PHY_ADDR		0
+#define TSEC2_PHY_ADDR		1
+#define TSEC3_PHY_ADDR		2
+#define TSEC4_PHY_ADDR		3
+#define FEC_PHY_ADDR		3
+
+#define TSEC1_PHYIDX		0
+#define TSEC2_PHYIDX		0
+#define TSEC3_PHYIDX		0
+#define TSEC4_PHYIDX		0
+#define FEC_PHYIDX		0
+
+/* Options are: eTSEC[0-3] */
+#define CONFIG_ETHPRIME		"eTSEC0"
+
+#endif	/* CONFIG_TSEC_ENET */
+
+/*
+ * Environment
+ */
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_ADDR		(CFG_MONITOR_BASE + 0x40000)
+#define CFG_ENV_SECT_SIZE	0x40000	/* 256K(one sector) for env */
+#define CFG_ENV_SIZE		0x2000
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+#if defined(CONFIG_PCI)
+#define  CONFIG_COMMANDS	(CONFIG_CMD_DFL \
+				| CFG_CMD_PCI \
+				| CFG_CMD_PING \
+				| CFG_CMD_I2C \
+				| CFG_CMD_MII)
+#else
+#define  CONFIG_COMMANDS	(CONFIG_CMD_DFL \
+				| CFG_CMD_PING \
+				| CFG_CMD_I2C \
+				| CFG_CMD_MII)
+#endif
+#include <cmd_confdefs.h>
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory	*/
+#define CFG_LOAD_ADDR	0x2000000	/* default load address */
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args */
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
+#define CFG_HZ		1000		/* decrementer freq: 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ	(8 << 20) 	/* Initial Memory map for Linux*/
+
+/* Cache Configuration */
+#define CFG_DCACHE_SIZE	32768
+#define CFG_CACHELINE_SIZE	32
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/*log base 2 of the above value*/
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM	0x02		/* Software reboot */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+
+/* The mac addresses for all ethernet interface */
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_ETHADDR   00:E0:0C:00:00:FD
+#define CONFIG_HAS_ETH1
+#define CONFIG_ETH1ADDR  00:E0:0C:00:01:FD
+#define CONFIG_HAS_ETH2
+#define CONFIG_ETH2ADDR  00:E0:0C:00:02:FD
+#endif
+
+#define CONFIG_IPADDR    192.168.1.253
+
+#define CONFIG_HOSTNAME  unknown
+#define CONFIG_ROOTPATH  /nfsroot
+#define CONFIG_BOOTFILE  your.uImage
+
+#define CONFIG_SERVERIP  192.168.1.1
+#define CONFIG_GATEWAYIP 192.168.1.1
+#define CONFIG_NETMASK   255.255.255.0
+
+#define CONFIG_LOADADDR  200000   /*default location for tftp and bootm*/
+
+#define CONFIG_BOOTDELAY 10       /* -1 disables auto-boot */
+#undef  CONFIG_BOOTARGS           /* the boot command will set bootargs*/
+
+#define CONFIG_BAUDRATE	115200
+
+#define	CONFIG_EXTRA_ENV_SETTINGS				        \
+   "netdev=eth0\0"                                                      \
+   "consoledev=ttyS1\0"                                                 \
+   "ramdiskaddr=400000\0"                                               \
+   "ramdiskfile=your.ramdisk.u-boot\0"
+
+#define CONFIG_NFSBOOTCOMMAND	                                        \
+   "setenv bootargs root=/dev/nfs rw "                                  \
+      "nfsroot=$serverip:$rootpath "                                    \
+      "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+      "console=$consoledev,$baudrate $othbootargs;"                     \
+   "tftp $loadaddr $bootfile;"                                          \
+   "bootm $loadaddr"
+
+#define CONFIG_RAMBOOTCOMMAND \
+   "setenv bootargs root=/dev/ram rw "                                  \
+      "console=$consoledev,$baudrate $othbootargs;"                     \
+   "tftp $ramdiskaddr $ramdiskfile;"                                    \
+   "tftp $loadaddr $bootfile;"                                          \
+   "bootm $loadaddr $ramdiskaddr"
+
+#define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
+
+#endif	/* __CONFIG_H */
--- a/include/configs/MPC8555CDS.h
+++ b/include/configs/MPC8555CDS.h
@@ -41,9 +41,12 @@
 #define CONFIG_TSEC_ENET 		/* tsec ethernet support */
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
-#define CONFIG_DDR_ECC			/* only for ECC DDR module */
 #define CONFIG_DDR_DLL			/* possible DLL fix needed */
-#define CONFIG_DDR_2T_TIMING		/* Sets the 2T timing bit */
+#undef CONFIG_DDR_2T_TIMING		/* Sets the 2T timing bit */
+
+#define CONFIG_DDR_ECC			/* only for ECC DDR module */
+#define CONFIG_MEM_INIT_VALUE		0xDeadBeef
+

 /*
 * When initializing flash, if we cannot find the manufacturer ID,
@@ -360,7 +363,9 @@ extern unsigned long get_clock_freq(void);

 #define CONFIG_MII		1	/* MII PHY management */
 #define CONFIG_MPC85XX_TSEC1	1
+#define CONFIG_MPC85XX_TSEC1_NAME	"TSEC0"
 #define CONFIG_MPC85XX_TSEC2	1
+#define CONFIG_MPC85XX_TSEC2_NAME	"TSEC1"
 #undef CONFIG_MPC85XX_FEC
 #define TSEC1_PHY_ADDR		0
 #define TSEC2_PHY_ADDR		1
@@ -368,7 +373,9 @@ extern unsigned long get_clock_freq(void);
 #define TSEC1_PHYIDX		0
 #define TSEC2_PHYIDX		0
 #define FEC_PHYIDX		0
-#define CONFIG_ETHPRIME		"MOTO ENET0"
+
+/* Options are: TSEC[0-1] */
+#define CONFIG_ETHPRIME		"TSEC0"

 #endif	/* CONFIG_TSEC_ENET */

--- a/include/configs/MPC8560ADS.h
+++ b/include/configs/MPC8560ADS.h
@@ -46,10 +46,12 @@
 #undef  CONFIG_ETHER_ON_FCC             /* cpm FCC ethernet support */
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
-#define CONFIG_DDR_ECC			/* only for ECC DDR module */
 #define CONFIG_DDR_DLL			/* possible DLL fix needed */
 #define CONFIG_DDR_2T_TIMING		/* Sets the 2T timing bit */

+#define CONFIG_DDR_ECC			/* only for ECC DDR module */
+#define CONFIG_MEM_INIT_VALUE		0xDeadBeef
+

 /*
 * sysclk for MPC85xx
@@ -337,13 +339,17 @@

 #define CONFIG_MII		1	/* MII PHY management */
 #define CONFIG_MPC85XX_TSEC1	1
+#define CONFIG_MPC85XX_TSEC1_NAME	"TSEC0"
 #define CONFIG_MPC85XX_TSEC2	1
+#define CONFIG_MPC85XX_TSEC2_NAME	"TSEC1"
 #undef CONFIG_MPC85XX_FEC
 #define TSEC1_PHY_ADDR		0
 #define TSEC2_PHY_ADDR		1
 #define TSEC1_PHYIDX		0
 #define TSEC2_PHYIDX		0
-#define CONFIG_ETHPRIME		"MOTO ENET0"
+
+/* Options are: TSEC[0-1] */
+#define CONFIG_ETHPRIME		"TSEC0"

 #elif defined(CONFIG_ETHER_ON_FCC)	/* CPM FCC Ethernet */

--- a/include/configs/PM854.h
+++ b/include/configs/PM854.h
@@ -45,10 +45,12 @@
 #define CONFIG_TSEC_ENET		/* tsec ethernet support */
 #define CONFIG_ENV_OVERWRITE
 #undef	CONFIG_SPD_EEPROM		/* do not use SPD EEPROM for DDR setup*/
-#define CONFIG_DDR_ECC			/* only for ECC DDR module */
 #define CONFIG_DDR_DLL			/* possible DLL fix needed */
 #define CONFIG_DDR_2T_TIMING		/* Sets the 2T timing bit */

+#define CONFIG_DDR_ECC			/* only for ECC DDR module */
+#define CONFIG_MEM_INIT_VALUE		0xDeadBeef
+

 /*
 * sysclk for MPC85xx
@@ -250,17 +252,21 @@

 #define CONFIG_MII		1	/* MII PHY management */
 #define CONFIG_MPC85XX_TSEC1	1
+#define CONFIG_MPC85XX_TSEC1_NAME	"TSEC0"
 #define CONFIG_MPC85XX_TSEC2	1
+#define CONFIG_MPC85XX_TSEC2_NAME	"TSEC1"
 #define TSEC1_PHY_ADDR		2
 #define TSEC2_PHY_ADDR		3
 #define TSEC1_PHYIDX		0
 #define TSEC2_PHYIDX		0

 #define CONFIG_MPC85XX_FEC	1
+#define CONFIG_MPC85XX_FEC_NAME		"FEC"
 #define FEC_PHY_ADDR		1
 #define FEC_PHYIDX		0

-#define CONFIG_ETHPRIME		"MOTO ENET0"
+/* Options are: TSEC[0-1] */
+#define CONFIG_ETHPRIME		"TSEC0"

 #define	CONFIG_HAS_ETH1		1
 #define	CONFIG_HAS_ETH2		1
--- a/include/configs/SBC8540.h
+++ b/include/configs/SBC8540.h
@@ -227,10 +227,14 @@

 #if defined(CONFIG_TSEC_ENET)		/* TSEC Ethernet port */

-  #define CONFIG_NET_MULTI	1
-  #define CONFIG_PHY_BCM5421S		/* GigaBit Ether PHY	     */
-  #define CONFIG_MII		1	/* MII PHY management		*/
-  #define CONFIG_PHY_ADDR	25	/* PHY address			*/
+#  define CONFIG_NET_MULTI	1
+#  define CONFIG_MPC85xx_TSEC1
+#  define CONFIG_MPC85xx_TSEC1_NAME	"TSEC0"
+#  define CONFIG_MII		1	/* MII PHY management		*/
+#  define TSEC1_PHY_ADDR	25
+#  define TSEC1_PHYIDX		0
+/* Options are: TSEC0 */
+#  define CONFIG_ETHPRIME		"TSEC0"


 #elif defined(CONFIG_ETHER_ON_FCC)	/* CPM FCC Ethernet */
--- a/include/configs/SBC8560.h
+++ b/include/configs/SBC8560.h
@@ -215,10 +215,14 @@

 #if defined(CONFIG_TSEC_ENET)		/* TSEC Ethernet port */

-  #define CONFIG_NET_MULTI	1
-  #define CONFIG_PHY_BCM5421S		/* GigaBit Ether PHY	     */
-  #define CONFIG_MII		1	/* MII PHY management		*/
-  #define CONFIG_PHY_ADDR	25	/* PHY address			*/
+#  define CONFIG_NET_MULTI	1
+#  define CONFIG_MII		1	/* MII PHY management		*/
+#  define CONFIG_MPC85xx_TSEC1
+#  define CONFIG_MPC85xx_TSEC1_NAME	"TSEC0"
+#  define TSEC1_PHY_ADDR	25
+#  define TSEC1_PHYIDX		0
+/* Options are: TSEC0 */
+#  define CONFIG_ETHPRIME		"TSEC0"


 #elif defined(CONFIG_ETHER_ON_FCC)	/* CPM FCC Ethernet */
--- a/include/configs/TQM8540.h
+++ b/include/configs/TQM8540.h
@@ -280,20 +280,24 @@

 #define CONFIG_MII		1	/* MII PHY management */
 #define CONFIG_MPC85XX_TSEC1	1
+#define CONFIG_MPC85XX_TSEC1_NAME	"TSEC0"
 #define CONFIG_MPC85XX_TSEC2	1
+#define CONFIG_MPC85XX_TSEC2_NAME	"TSEC1"
 #define TSEC1_PHY_ADDR		0
 #define TSEC2_PHY_ADDR		1
 #define TSEC1_PHYIDX		0
 #define TSEC2_PHYIDX		0

 #define CONFIG_MPC85XX_FEC	1
+#define CONFIG_MPC85XX_FEC_NAME	"FEC"
 #define FEC_PHY_ADDR		2
 #define FEC_PHYIDX		0

 #define CONFIG_HAS_ETH1
 #define CONFIG_HAS_ETH2

-#define CONFIG_ETHPRIME		"ENET1"
+/* Options are TSEC[0-1], FEC */
+#define CONFIG_ETHPRIME		"TSEC1"

 #endif	/* CONFIG_TSEC_ENET */

--- a/include/configs/TQM8560.h
+++ b/include/configs/TQM8560.h
@@ -276,6 +276,7 @@

 #define CONFIG_MII		1	/* MII PHY management */
 #define CONFIG_MPC85XX_TSEC2	1
+#define CONFIG_MPC85XX_TSEC2_NAME	"TSEC1"
 #define TSEC2_PHY_ADDR		1
 #define TSEC2_PHYIDX		0

@@ -288,7 +289,7 @@
 #define CFG_CPMFCR_RAMTYPE    0
 #define CFG_FCC_PSMR          (FCC_PSMR_FDE | FCC_PSMR_LPB)

-#define CONFIG_ETHPRIME		"ENET1"
+#define CONFIG_ETHPRIME		"TSEC1"

 /*
 * Environment
--- a/include/configs/sbc8560.h
+++ b/include/configs/sbc8560.h
@@ -210,10 +210,14 @@

 #if defined(CONFIG_TSEC_ENET)		/* TSEC Ethernet port */

-  #define CONFIG_NET_MULTI	1
-  #define CONFIG_PHY_BCM5421S	1	/* GigaBit Ether PHY	     */
-  #define CONFIG_MII		1	/* MII PHY management		*/
-  #define CONFIG_PHY_ADDR	25	/* PHY address			*/
+#  define CONFIG_NET_MULTI	1
+#  define CONFIG_MII		1	/* MII PHY management		*/
+#  define CONFIG_MPC85xx_TSEC1
+#  define CONFIG_MPC85xx_TSEC1_NAME	"TSEC0"
+#  define TSEC1_PHY_ADDR	25
+#  define TSEC1_PHYIDX		0
+/* Options are: TSEC0 */
+#  define CONFIG_ETHPRIME		"TSEC0"

 #elif defined(CONFIG_ETHER_ON_FCC)	/* CPM FCC Ethernet */

--- a/include/configs/stxgp3.h
+++ b/include/configs/stxgp3.h
@@ -227,14 +227,16 @@
 #define CONFIG_MII		1	/* MII PHY management		*/

 #define CONFIG_MPC85XX_TSEC1	1
+#define CONFIG_MPC85XX_TSEC1_NAME	"TSEC0"
 #define CONFIG_MPC85XX_TSEC2	1
+#define CONFIG_MPC85XX_TSEC2_NAME	"TSEC1"
 #undef CONFIG_MPS85XX_FEC

 #define TSEC1_PHY_ADDR		2
 #define TSEC2_PHY_ADDR		4
 #define TSEC1_PHYIDX		0
 #define TSEC2_PHYIDX		0
-#define CONFIG_ETHPRIME		"MOTO ENET0"
+#define CONFIG_ETHPRIME		"TSEC0"

 #elif defined(CONFIG_ETHER_ON_FCC)	/* CPM FCC Ethernet */

--- a/include/spd.h
+++ b/include/spd.h
@@ -25,54 +25,84 @@
 #define _SPD_H_

 typedef struct spd_eeprom_s {
-   unsigned char info_size;   /* # of bytes written into serial memory           */
-   unsigned char chip_size;   /* Total # of bytes of SPD memory device           */
-   unsigned char mem_type;    /* Fundamental memory type (FPM, EDO, SDRAM...)    */
-   unsigned char nrow_addr;   /* # of Row Addresses on this assembly             */
-   unsigned char ncol_addr;   /* # of Column Addresses on this assembly          */
-   unsigned char nrows;       /* # of Module Rows on this assembly               */
-   unsigned char dataw_lsb;   /* Data Width of this assembly                     */
-   unsigned char dataw_msb;   /* ... Data Width continuation                     */
-   unsigned char voltage;     /* Voltage interface standard of this assembly     */
-   unsigned char clk_cycle;   /* SDRAM Cycle time at CL=X                        */
-   unsigned char clk_access;  /* SDRAM Access from Clock at CL=X                 */
-   unsigned char config;      /* DIMM Configuration type (non-parity, ECC)       */
-   unsigned char refresh;     /* Refresh Rate/Type                               */
-   unsigned char primw;       /* Primary SDRAM Width                             */
-   unsigned char ecw;         /* Error Checking SDRAM width                      */
-   unsigned char min_delay;   /* Min Clock Delay for Back to Back Random Address */
-   unsigned char burstl;      /* Burst Lengths Supported                         */
-   unsigned char nbanks;      /* # of Banks on Each SDRAM Device                 */
-   unsigned char cas_lat;     /* CAS# Latencies Supported                        */
-   unsigned char cs_lat;      /* CS# Latency                                     */
-   unsigned char write_lat;   /* Write Latency (also called Write Recovery time) */
-   unsigned char mod_attr;    /* SDRAM Module Attributes                         */
-   unsigned char dev_attr;    /* SDRAM Device Attributes                         */
-   unsigned char clk_cycle2;  /* Min SDRAM Cycle time at CL=X-1                  */
-   unsigned char clk_access2; /* SDRAM Access from Clock at CL=X-1               */
-   unsigned char clk_cycle3;  /* Min SDRAM Cycle time at CL=X-2                  */
-   unsigned char clk_access3; /* Max SDRAM Access from Clock at CL=X-2           */
-   unsigned char trp;         /* Min Row Precharge Time (tRP)                    */
-   unsigned char trrd;        /* Min Row Active to Row Active (tRRD)             */
-   unsigned char trcd;        /* Min RAS to CAS Delay (tRCD)                     */
-   unsigned char tras;        /* Minimum RAS Pulse Width (tRAS)                  */
-   unsigned char row_dens;    /* Density of each row on module                   */
-   unsigned char ca_setup;    /* Command and Address signal input setup time     */
-   unsigned char ca_hold;     /* Command and Address signal input hold time      */
-   unsigned char data_setup;  /* Data signal input setup time                    */
-   unsigned char data_hold;   /* Data signal input hold time                     */
-   unsigned char sset[26];    /* Superset Information (may be used in future)    */
-   unsigned char spd_rev;     /* SPD Data Revision Code                          */
-   unsigned char cksum;       /* Checksum for bytes 0-62                         */
-   unsigned char mid[8];      /* Manufacturer's JEDEC ID code per JEP-108E       */
-   unsigned char mloc;        /* Manufacturing Location                          */
-   unsigned char mpart[18];   /* Manufacturer's Part Number                      */
-   unsigned char rev[2];      /* Revision Code                                   */
-   unsigned char mdate[2];    /* Manufacturing Date                              */
-   unsigned char sernum[4];   /* Assembly Serial Number                          */
-   unsigned char mspec[27];   /* Manufacturer Specific Data                      */
-   unsigned char freq;        /* Intel specification frequency                   */
-   unsigned char intel_cas;   /* Intel Specification CAS# Latency support        */
+	unsigned char info_size;   /*  0 # bytes written into serial memory */
+	unsigned char chip_size;   /*  1 Total # bytes of SPD memory device */
+	unsigned char mem_type;    /*  2 Fundamental memory type */
+	unsigned char nrow_addr;   /*  3 # of Row Addresses on this assembly */
+	unsigned char ncol_addr;   /*  4 # of Column Addrs on this assembly */
+	unsigned char nrows;       /*  5 # of Module Rows on this assembly */
+	unsigned char dataw_lsb;   /*  6 Data Width of this assembly */
+	unsigned char dataw_msb;   /*  7 ... Data Width continuation */
+	unsigned char voltage;     /*  8 Voltage intf std of this assembly */
+	unsigned char clk_cycle;   /*  9 SDRAM Cycle time at CL=X */
+	unsigned char clk_access;  /* 10 SDRAM Access from Clock at CL=X */
+	unsigned char config;      /* 11 DIMM Configuration type */
+	unsigned char refresh;     /* 12 Refresh Rate/Type */
+	unsigned char primw;       /* 13 Primary SDRAM Width */
+	unsigned char ecw;         /* 14 Error Checking SDRAM width */
+	unsigned char min_delay;   /* 15 for Back to Back Random Address */
+	unsigned char burstl;      /* 16 Burst Lengths Supported */
+	unsigned char nbanks;      /* 17 # of Banks on Each SDRAM Device */
+	unsigned char cas_lat;     /* 18 CAS# Latencies Supported */
+	unsigned char cs_lat;      /* 19 CS# Latency */
+	unsigned char write_lat;   /* 20 Write Latency (aka Write Recovery) */
+	unsigned char mod_attr;    /* 21 SDRAM Module Attributes */
+	unsigned char dev_attr;    /* 22 SDRAM Device Attributes */
+	unsigned char clk_cycle2;  /* 23 Min SDRAM Cycle time at CL=X-1 */
+	unsigned char clk_access2; /* 24 SDRAM Access from Clock at CL=X-1 */
+	unsigned char clk_cycle3;  /* 25 Min SDRAM Cycle time at CL=X-2 */
+	unsigned char clk_access3; /* 26 Max Access from Clock at CL=X-2 */
+	unsigned char trp;         /* 27 Min Row Precharge Time (tRP)*/
+	unsigned char trrd;        /* 28 Min Row Active to Row Active (tRRD) */
+	unsigned char trcd;        /* 29 Min RAS to CAS Delay (tRCD) */
+	unsigned char tras;        /* 30 Minimum RAS Pulse Width (tRAS) */
+	unsigned char row_dens;    /* 31 Density of each row on module */
+	unsigned char ca_setup;    /* 32 Cmd + Addr signal input setup time */
+	unsigned char ca_hold;     /* 33 Cmd and Addr signal input hold time */
+	unsigned char data_setup;  /* 34 Data signal input setup time */
+	unsigned char data_hold;   /* 35 Data signal input hold time */
+	unsigned char twr;         /* 36 Write Recovery time tWR */
+	unsigned char twtr;        /* 37 Int write to read delay tWTR */
+	unsigned char trtp;        /* 38 Int read to precharge delay tRTP */
+	unsigned char mem_probe;   /* 39 Mem analysis probe characteristics */
+	unsigned char trctrfc_ext; /* 40 Extensions to trc and trfc */
+	unsigned char trc;         /* 41 Min Active to Auto refresh time tRC */
+	unsigned char trfc;        /* 42 Min Auto to Active period tRFC */
+	unsigned char tckmax;      /* 43 Max device cycle time tCKmax */
+	unsigned char tdqsq;       /* 44 Max DQS to DQ skew */
+	unsigned char tqhs;        /* 45 Max Read DataHold skew tQHS */
+	unsigned char pll_relock;  /* 46 PLL Relock time */
+	unsigned char res[15];     /* 47-xx IDD in SPD and Reserved space */
+	unsigned char spd_rev;     /* 62 SPD Data Revision Code */
+	unsigned char cksum;       /* 63 Checksum for bytes 0-62 */
+	unsigned char mid[8];      /* 64 Mfr's JEDEC ID code per JEP-108E */
+	unsigned char mloc;        /* 72 Manufacturing Location */
+	unsigned char mpart[18];   /* 73 Manufacturer's Part Number */
+	unsigned char rev[2];      /* 91 Revision Code */
+	unsigned char mdate[2];    /* 93 Manufacturing Date */
+	unsigned char sernum[4];   /* 95 Assembly Serial Number */
+	unsigned char mspec[27];   /* 99 Manufacturer Specific Data */
+
+	/*
+	 * Open for Customer Use starting with byte 128.
+	 */
+	unsigned char freq;        /* 128 Intel spec: frequency */
+	unsigned char intel_cas;   /* 129 Intel spec: CAS# Latency support */
 } spd_eeprom_t;

+
+/*
+ * Byte 2 Fundamental Memory Types.
+ */
+#define SPD_MEMTYPE_FPM		(0x01)
+#define SPD_MEMTYPE_EDO		(0x02)
+#define SPD_MEMTYPE_PIPE_NIBBLE	(0x03)
+#define SPD_MEMTYPE_SDRAM	(0x04)
+#define SPD_MEMTYPE_ROM		(0x05)
+#define SPD_MEMTYPE_SGRAM	(0x06)
+#define SPD_MEMTYPE_DDR		(0x07)
+#define SPD_MEMTYPE_DDR2	(0x08)
+
+
 #endif /* _SPD_H_ */
+