eaw/u-boot
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Merge tag 'u-boot-rockchip-20191118' of https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip

Browse Source 
- Add support for rockchip SoC: PX30, RK3308
- Add and migrate to use common dram driver: PX30, RK3328, RK3399
- Add rk3399 board Tinker-s support
- Board config update for Rock960, Rockpro64
This commit is contained in:
Tom Rini
2019-11-17 21:15:57 -05:00
parent fd8adc33b8 59b01eb7a1
commit d64efd920e
168 changed files with 16846 additions and 1815 deletions
Download Patch File Download Diff File Expand all files Collapse all files

19
include/configs/evb_px30.h Normal file
View File

@@ -0,0 +1,19 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2017 Rockchip Electronics Co., Ltd
*/
#ifndef __EVB_PX30_H
#define __EVB_PX30_H
#include <configs/px30_common.h>
#define CONFIG_SYS_MMC_ENV_DEV 0
#define ROCKCHIP_DEVICE_SETTINGS \
"stdout=serial,vidconsole\0" \
"stderr=serial,vidconsole\0"
#define CONFIG_SUPPORT_EMMC_RPMB
#endif

20
include/configs/evb_rk3308.h Normal file
View File

@@ -0,0 +1,20 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* (C) Copyright 2018 Rockchip Electronics Co., Ltd
*/
#ifndef __EVB_RK3308_H
#define __EVB_RK3308_H
#include <configs/rk3308_common.h>
#define CONFIG_SUPPORT_EMMC_RPMB
#define CONFIG_SYS_MMC_ENV_DEV 0
#define ROCKCHIP_DEVICE_SETTINGS \
"stdout=serial,vidconsole\0" \
"stderr=serial,vidconsole\0"
#undef CONFIG_CONSOLE_SCROLL_LINES
#define CONFIG_CONSOLE_SCROLL_LINES 10
#endif

20
include/configs/firefly_rk3308.h Normal file
View File

@@ -0,0 +1,20 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2019 Rockchip Electronics Co., Ltd
*/
#ifndef __FIREFLY_RK3308_H
#define __FIREFLY_RK3308_H
#include <configs/rk3308_common.h>
#define CONFIG_SUPPORT_EMMC_RPMB
#define CONFIG_SYS_MMC_ENV_DEV 0
#define ROCKCHIP_DEVICE_SETTINGS \
"stdout=serial,vidconsole\0" \
"stderr=serial,vidconsole\0"
#undef CONFIG_CONSOLE_SCROLL_LINES
#define CONFIG_CONSOLE_SCROLL_LINES 10
#endif

62
include/configs/px30_common.h Normal file
View File

@@ -0,0 +1,62 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2017 Rockchip Electronics Co., Ltd
*/
#ifndef __CONFIG_PX30_COMMON_H
#define __CONFIG_PX30_COMMON_H
#include "rockchip-common.h"
#define CONFIG_SYS_CBSIZE 1024
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SYS_NS16550_MEM32
#define CONFIG_ROCKCHIP_STIMER_BASE 0xff220020
#define COUNTER_FREQUENCY 24000000
/* FIXME: ff020000 is pmu_mem (10k), while ff0e0000 is regular int_mem */
#define CONFIG_IRAM_BASE 0xff020000
#define CONFIG_SYS_INIT_SP_ADDR 0x00400000
#define CONFIG_SYS_LOAD_ADDR 0x00800800
#define CONFIG_SPL_STACK 0x00400000
#define CONFIG_SPL_MAX_SIZE 0x20000
#define CONFIG_SPL_BSS_START_ADDR 0x4000000
#define CONFIG_SPL_BSS_MAX_SIZE 0x4000
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
#define GICD_BASE 0xff131000
#define GICC_BASE 0xff132000
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
/* MMC/SD IP block */
//#define CONFIG_BOUNCE_BUFFER
#define CONFIG_SYS_SDRAM_BASE 0
#define SDRAM_MAX_SIZE 0xff000000
#define SDRAM_BANK_SIZE (2UL << 30)
#ifndef CONFIG_SPL_BUILD
#define ENV_MEM_LAYOUT_SETTINGS \
"scriptaddr=0x00500000\0" \
"pxefile_addr_r=0x00600000\0" \
"fdt_addr_r=0x08300000\0" \
"kernel_addr_r=0x00280000\0" \
"kernel_addr_c=0x03e80000\0" \
"ramdisk_addr_r=0x0a200000\0"
#include <config_distro_bootcmd.h>
#define CONFIG_EXTRA_ENV_SETTINGS \
ENV_MEM_LAYOUT_SETTINGS \
"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
"partitions=" PARTS_DEFAULT \
ROCKCHIP_DEVICE_SETTINGS \
BOOTENV
#endif
#endif

58
include/configs/rk3308_common.h Normal file
View File

@@ -0,0 +1,58 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2017 Rockchip Electronics Co., Ltd
*/
#ifndef __CONFIG_RK3308_COMMON_H
#define __CONFIG_RK3308_COMMON_H
#include "rockchip-common.h"
#define CONFIG_SYS_CBSIZE 1024
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_ONFI_DETECTION
#define CONFIG_SYS_NAND_PAGE_SIZE 2048
#define CONFIG_SYS_NAND_PAGE_COUNT 64
#define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024)
#define CONFIG_SPL_MAX_SIZE 0x20000
#define CONFIG_SPL_BSS_START_ADDR 0x00400000
#define CONFIG_SPL_BSS_MAX_SIZE 0x2000
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000
#define CONFIG_SYS_NS16550_MEM32
#define CONFIG_ROCKCHIP_STIMER_BASE 0xff1b00a0
#define CONFIG_IRAM_BASE 0xfff80000
#define CONFIG_SYS_INIT_SP_ADDR 0x00800000
#define CONFIG_SYS_LOAD_ADDR 0x00C00800
#define CONFIG_SPL_STACK 0x00400000
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
#define COUNTER_FREQUENCY 24000000
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
#define CONFIG_SYS_SDRAM_BASE 0
#define SDRAM_MAX_SIZE 0xff000000
#define SDRAM_BANK_SIZE (2UL << 30)
#ifndef CONFIG_SPL_BUILD
#define ENV_MEM_LAYOUT_SETTINGS \
"scriptaddr=0x00500000\0" \
"pxefile_addr_r=0x00600000\0" \
"fdt_addr_r=0x01f00000\0" \
"kernel_addr_r=0x00680000\0" \
"ramdisk_addr_r=0x04000000\0"
#include <config_distro_bootcmd.h>
#define CONFIG_EXTRA_ENV_SETTINGS \
ENV_MEM_LAYOUT_SETTINGS \
"partitions=" PARTS_DEFAULT \
ROCKCHIP_DEVICE_SETTINGS \
BOOTENV
#endif
#endif

15
include/configs/rockpro64_rk3399.h Normal file
View File

@@ -0,0 +1,15 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2019 Vasily Khoruzhick <anarsoul@gmail.com>
*/
#ifndef __ROCKPRO64_RK3399_H
#define __ROCKPRO64_RK3399_H
#include <configs/rk3399_common.h>
#define CONFIG_SYS_MMC_ENV_DEV 0
#define SDRAM_BANK_SIZE (2UL << 30)
#endif

1
include/configs/tinker_rk3288.h
View File

@@ -12,6 +12,7 @@
#undef BOOT_TARGET_DEVICES
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 0) \
func(MMC, mmc, 1) \
func(USB, usb, 0) \
func(PXE, pxe, na) \

389
include/dt-bindings/clock/px30-cru.h Normal file
View File

@@ -0,0 +1,389 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2017 Rockchip Electronics Co. Ltd.
* Author: Elaine <zhangqing@rock-chips.com>
*/
#ifndef _DT_BINDINGS_CLK_ROCKCHIP_PX30_H
#define _DT_BINDINGS_CLK_ROCKCHIP_PX30_H
/* core clocks */
#define PLL_APLL 1
#define PLL_DPLL 2
#define PLL_CPLL 3
#define PLL_NPLL 4
#define APLL_BOOST_H 5
#define APLL_BOOST_L 6
#define ARMCLK 7
/* sclk gates (special clocks) */
#define USB480M 14
#define SCLK_PDM 15
#define SCLK_I2S0_TX 16
#define SCLK_I2S0_TX_OUT 17
#define SCLK_I2S0_RX 18
#define SCLK_I2S0_RX_OUT 19
#define SCLK_I2S1 20
#define SCLK_I2S1_OUT 21
#define SCLK_I2S2 22
#define SCLK_I2S2_OUT 23
#define SCLK_UART1 24
#define SCLK_UART2 25
#define SCLK_UART3 26
#define SCLK_UART4 27
#define SCLK_UART5 28
#define SCLK_I2C0 29
#define SCLK_I2C1 30
#define SCLK_I2C2 31
#define SCLK_I2C3 32
#define SCLK_I2C4 33
#define SCLK_PWM0 34
#define SCLK_PWM1 35
#define SCLK_SPI0 36
#define SCLK_SPI1 37
#define SCLK_TIMER0 38
#define SCLK_TIMER1 39
#define SCLK_TIMER2 40
#define SCLK_TIMER3 41
#define SCLK_TIMER4 42
#define SCLK_TIMER5 43
#define SCLK_TSADC 44
#define SCLK_SARADC 45
#define SCLK_OTP 46
#define SCLK_OTP_USR 47
#define SCLK_CRYPTO 48
#define SCLK_CRYPTO_APK 49
#define SCLK_DDRC 50
#define SCLK_ISP 51
#define SCLK_CIF_OUT 52
#define SCLK_RGA_CORE 53
#define SCLK_VOPB_PWM 54
#define SCLK_NANDC 55
#define SCLK_SDIO 56
#define SCLK_EMMC 57
#define SCLK_SFC 58
#define SCLK_SDMMC 59
#define SCLK_OTG_ADP 60
#define SCLK_GMAC_SRC 61
#define SCLK_GMAC 62
#define SCLK_GMAC_RX_TX 63
#define SCLK_MAC_REF 64
#define SCLK_MAC_REFOUT 65
#define SCLK_MAC_OUT 66
#define SCLK_SDMMC_DRV 67
#define SCLK_SDMMC_SAMPLE 68
#define SCLK_SDIO_DRV 69
#define SCLK_SDIO_SAMPLE 70
#define SCLK_EMMC_DRV 71
#define SCLK_EMMC_SAMPLE 72
#define SCLK_GPU 73
#define SCLK_PVTM 74
#define SCLK_CORE_VPU 75
#define SCLK_GMAC_RMII 76
#define SCLK_UART2_SRC 77
#define SCLK_NANDC_DIV 78
#define SCLK_NANDC_DIV50 79
#define SCLK_SDIO_DIV 80
#define SCLK_SDIO_DIV50 81
#define SCLK_EMMC_DIV 82
#define SCLK_EMMC_DIV50 83
/* dclk gates */
#define DCLK_VOPB 150
#define DCLK_VOPL 151
/* aclk gates */
#define ACLK_GPU 170
#define ACLK_BUS_PRE 171
#define ACLK_CRYPTO 172
#define ACLK_VI_PRE 173
#define ACLK_VO_PRE 174
#define ACLK_VPU 175
#define ACLK_PERI_PRE 176
#define ACLK_GMAC 178
#define ACLK_CIF 179
#define ACLK_ISP 180
#define ACLK_VOPB 181
#define ACLK_VOPL 182
#define ACLK_RGA 183
#define ACLK_GIC 184
#define ACLK_DCF 186
#define ACLK_DMAC 187
/* hclk gates */
#define HCLK_BUS_PRE 240
#define HCLK_CRYPTO 241
#define HCLK_VI_PRE 242
#define HCLK_VO_PRE 243
#define HCLK_VPU 244
#define HCLK_PERI_PRE 245
#define HCLK_MMC_NAND 246
#define HCLK_SDMMC 247
#define HCLK_USB 248
#define HCLK_CIF 249
#define HCLK_ISP 250
#define HCLK_VOPB 251
#define HCLK_VOPL 252
#define HCLK_RGA 253
#define HCLK_NANDC 254
#define HCLK_SDIO 255
#define HCLK_EMMC 256
#define HCLK_SFC 257
#define HCLK_OTG 258
#define HCLK_HOST 259
#define HCLK_HOST_ARB 260
#define HCLK_PDM 261
#define HCLK_I2S0 262
#define HCLK_I2S1 263
#define HCLK_I2S2 264
/* pclk gates */
#define PCLK_BUS_PRE 320
#define PCLK_DDR 321
#define PCLK_VO_PRE 322
#define PCLK_GMAC 323
#define PCLK_MIPI_DSI 324
#define PCLK_MIPIDSIPHY 325
#define PCLK_MIPICSIPHY 326
#define PCLK_USB_GRF 327
#define PCLK_DCF 328
#define PCLK_UART1 329
#define PCLK_UART2 330
#define PCLK_UART3 331
#define PCLK_UART4 332
#define PCLK_UART5 333
#define PCLK_I2C0 334
#define PCLK_I2C1 335
#define PCLK_I2C2 336
#define PCLK_I2C3 337
#define PCLK_I2C4 338
#define PCLK_PWM0 339
#define PCLK_PWM1 340
#define PCLK_SPI0 341
#define PCLK_SPI1 342
#define PCLK_SARADC 343
#define PCLK_TSADC 344
#define PCLK_TIMER 345
#define PCLK_OTP_NS 346
#define PCLK_WDT_NS 347
#define PCLK_GPIO1 348
#define PCLK_GPIO2 349
#define PCLK_GPIO3 350
#define PCLK_ISP 351
#define PCLK_CIF 352
#define PCLK_OTP_PHY 353
#define CLK_NR_CLKS (PCLK_OTP_PHY + 1)
/* pmu-clocks indices */
#define PLL_GPLL 1
#define SCLK_RTC32K_PMU 4
#define SCLK_WIFI_PMU 5
#define SCLK_UART0_PMU 6
#define SCLK_PVTM_PMU 7
#define PCLK_PMU_PRE 8
#define SCLK_REF24M_PMU 9
#define SCLK_USBPHY_REF 10
#define SCLK_MIPIDSIPHY_REF 11
#define XIN24M_DIV 12
#define PCLK_GPIO0_PMU 20
#define PCLK_UART0_PMU 21
#define CLKPMU_NR_CLKS (PCLK_UART0_PMU + 1)
/* soft-reset indices */
#define SRST_CORE0_PO 0
#define SRST_CORE1_PO 1
#define SRST_CORE2_PO 2
#define SRST_CORE3_PO 3
#define SRST_CORE0 4
#define SRST_CORE1 5
#define SRST_CORE2 6
#define SRST_CORE3 7
#define SRST_CORE0_DBG 8
#define SRST_CORE1_DBG 9
#define SRST_CORE2_DBG 10
#define SRST_CORE3_DBG 11
#define SRST_TOPDBG 12
#define SRST_CORE_NOC 13
#define SRST_STRC_A 14
#define SRST_L2C 15
#define SRST_DAP 16
#define SRST_CORE_PVTM 17
#define SRST_GPU 18
#define SRST_GPU_NIU 19
#define SRST_UPCTL2 20
#define SRST_UPCTL2_A 21
#define SRST_UPCTL2_P 22
#define SRST_MSCH 23
#define SRST_MSCH_P 24
#define SRST_DDRMON_P 25
#define SRST_DDRSTDBY_P 26
#define SRST_DDRSTDBY 27
#define SRST_DDRGRF_p 28
#define SRST_AXI_SPLIT_A 29
#define SRST_AXI_CMD_A 30
#define SRST_AXI_CMD_P 31
#define SRST_DDRPHY 32
#define SRST_DDRPHYDIV 33
#define SRST_DDRPHY_P 34
#define SRST_VPU_A 36
#define SRST_VPU_NIU_A 37
#define SRST_VPU_H 38
#define SRST_VPU_NIU_H 39
#define SRST_VI_NIU_A 40
#define SRST_VI_NIU_H 41
#define SRST_ISP_H 42
#define SRST_ISP 43
#define SRST_CIF_A 44
#define SRST_CIF_H 45
#define SRST_CIF_PCLKIN 46
#define SRST_MIPICSIPHY_P 47
#define SRST_VO_NIU_A 48
#define SRST_VO_NIU_H 49
#define SRST_VO_NIU_P 50
#define SRST_VOPB_A 51
#define SRST_VOPB_H 52
#define SRST_VOPB 53
#define SRST_PWM_VOPB 54
#define SRST_VOPL_A 55
#define SRST_VOPL_H 56
#define SRST_VOPL 57
#define SRST_RGA_A 58
#define SRST_RGA_H 59
#define SRST_RGA 60
#define SRST_MIPIDSI_HOST_P 61
#define SRST_MIPIDSIPHY_P 62
#define SRST_VPU_CORE 63
#define SRST_PERI_NIU_A 64
#define SRST_USB_NIU_H 65
#define SRST_USB2OTG_H 66
#define SRST_USB2OTG 67
#define SRST_USB2OTG_ADP 68
#define SRST_USB2HOST_H 69
#define SRST_USB2HOST_ARB_H 70
#define SRST_USB2HOST_AUX_H 71
#define SRST_USB2HOST_EHCI 72
#define SRST_USB2HOST 73
#define SRST_USBPHYPOR 74
#define SRST_USBPHY_OTG_PORT 75
#define SRST_USBPHY_HOST_PORT 76
#define SRST_USBPHY_GRF 77
#define SRST_CPU_BOOST_P 78
#define SRST_CPU_BOOST 79
#define SRST_MMC_NAND_NIU_H 80
#define SRST_SDIO_H 81
#define SRST_EMMC_H 82
#define SRST_SFC_H 83
#define SRST_SFC 84
#define SRST_SDCARD_NIU_H 85
#define SRST_SDMMC_H 86
#define SRST_NANDC_H 89
#define SRST_NANDC 90
#define SRST_GMAC_NIU_A 92
#define SRST_GMAC_NIU_P 93
#define SRST_GMAC_A 94
#define SRST_PMU_NIU_P 96
#define SRST_PMU_SGRF_P 97
#define SRST_PMU_GRF_P 98
#define SRST_PMU 99
#define SRST_PMU_MEM_P 100
#define SRST_PMU_GPIO0_P 101
#define SRST_PMU_UART0_P 102
#define SRST_PMU_CRU_P 103
#define SRST_PMU_PVTM 104
#define SRST_PMU_UART 105
#define SRST_PMU_NIU_H 106
#define SRST_PMU_DDR_FAIL_SAVE 107
#define SRST_PMU_CORE_PERF_A 108
#define SRST_PMU_CORE_GRF_P 109
#define SRST_PMU_GPU_PERF_A 110
#define SRST_PMU_GPU_GRF_P 111
#define SRST_CRYPTO_NIU_A 112
#define SRST_CRYPTO_NIU_H 113
#define SRST_CRYPTO_A 114
#define SRST_CRYPTO_H 115
#define SRST_CRYPTO 116
#define SRST_CRYPTO_APK 117
#define SRST_BUS_NIU_H 120
#define SRST_USB_NIU_P 121
#define SRST_BUS_TOP_NIU_P 122
#define SRST_INTMEM_A 123
#define SRST_GIC_A 124
#define SRST_ROM_H 126
#define SRST_DCF_A 127
#define SRST_DCF_P 128
#define SRST_PDM_H 129
#define SRST_PDM 130
#define SRST_I2S0_H 131
#define SRST_I2S0_TX 132
#define SRST_I2S1_H 133
#define SRST_I2S1 134
#define SRST_I2S2_H 135
#define SRST_I2S2 136
#define SRST_UART1_P 137
#define SRST_UART1 138
#define SRST_UART2_P 139
#define SRST_UART2 140
#define SRST_UART3_P 141
#define SRST_UART3 142
#define SRST_UART4_P 143
#define SRST_UART4 144
#define SRST_UART5_P 145
#define SRST_UART5 146
#define SRST_I2C0_P 147
#define SRST_I2C0 148
#define SRST_I2C1_P 149
#define SRST_I2C1 150
#define SRST_I2C2_P 151
#define SRST_I2C2 152
#define SRST_I2C3_P 153
#define SRST_I2C3 154
#define SRST_PWM0_P 157
#define SRST_PWM0 158
#define SRST_PWM1_P 159
#define SRST_PWM1 160
#define SRST_SPI0_P 161
#define SRST_SPI0 162
#define SRST_SPI1_P 163
#define SRST_SPI1 164
#define SRST_SARADC_P 165
#define SRST_SARADC 166
#define SRST_TSADC_P 167
#define SRST_TSADC 168
#define SRST_TIMER_P 169
#define SRST_TIMER0 170
#define SRST_TIMER1 171
#define SRST_TIMER2 172
#define SRST_TIMER3 173
#define SRST_TIMER4 174
#define SRST_TIMER5 175
#define SRST_OTP_NS_P 176
#define SRST_OTP_NS_SBPI 177
#define SRST_OTP_NS_USR 178
#define SRST_OTP_PHY_P 179
#define SRST_OTP_PHY 180
#define SRST_WDT_NS_P 181
#define SRST_GPIO1_P 182
#define SRST_GPIO2_P 183
#define SRST_GPIO3_P 184
#define SRST_SGRF_P 185
#define SRST_GRF_P 186
#define SRST_I2S0_RX 191
#endif

387
include/dt-bindings/clock/rk3308-cru.h Normal file
View File

@@ -0,0 +1,387 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2019 Rockchip Electronics Co. Ltd.
* Author: Finley Xiao <finley.xiao@rock-chips.com>
*/
#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3308_H
#define _DT_BINDINGS_CLK_ROCKCHIP_RK3308_H
/* core clocks */
#define PLL_APLL 1
#define PLL_DPLL 2
#define PLL_VPLL0 3
#define PLL_VPLL1 4
#define ARMCLK 5
/* sclk (special clocks) */
#define USB480M 14
#define SCLK_RTC32K 15
#define SCLK_PVTM_CORE 16
#define SCLK_UART0 17
#define SCLK_UART1 18
#define SCLK_UART2 19
#define SCLK_UART3 20
#define SCLK_UART4 21
#define SCLK_I2C0 22
#define SCLK_I2C1 23
#define SCLK_I2C2 24
#define SCLK_I2C3 25
#define SCLK_PWM0 26
#define SCLK_SPI0 27
#define SCLK_SPI1 28
#define SCLK_SPI2 29
#define SCLK_TIMER0 30
#define SCLK_TIMER1 31
#define SCLK_TIMER2 32
#define SCLK_TIMER3 33
#define SCLK_TIMER4 34
#define SCLK_TIMER5 35
#define SCLK_TSADC 36
#define SCLK_SARADC 37
#define SCLK_OTP 38
#define SCLK_OTP_USR 39
#define SCLK_CPU_BOOST 40
#define SCLK_CRYPTO 41
#define SCLK_CRYPTO_APK 42
#define SCLK_NANDC_DIV 43
#define SCLK_NANDC_DIV50 44
#define SCLK_NANDC 45
#define SCLK_SDMMC_DIV 46
#define SCLK_SDMMC_DIV50 47
#define SCLK_SDMMC 48
#define SCLK_SDMMC_DRV 49
#define SCLK_SDMMC_SAMPLE 50
#define SCLK_SDIO_DIV 51
#define SCLK_SDIO_DIV50 52
#define SCLK_SDIO 53
#define SCLK_SDIO_DRV 54
#define SCLK_SDIO_SAMPLE 55
#define SCLK_EMMC_DIV 56
#define SCLK_EMMC_DIV50 57
#define SCLK_EMMC 58
#define SCLK_EMMC_DRV 59
#define SCLK_EMMC_SAMPLE 60
#define SCLK_SFC 61
#define SCLK_OTG_ADP 62
#define SCLK_MAC_SRC 63
#define SCLK_MAC 64
#define SCLK_MAC_REF 65
#define SCLK_MAC_RX_TX 66
#define SCLK_MAC_RMII 67
#define SCLK_DDR_MON_TIMER 68
#define SCLK_DDR_MON 69
#define SCLK_DDRCLK 70
#define SCLK_PMU 71
#define SCLK_USBPHY_REF 72
#define SCLK_WIFI 73
#define SCLK_PVTM_PMU 74
#define SCLK_PDM 75
#define SCLK_I2S0_8CH_TX 76
#define SCLK_I2S0_8CH_TX_OUT 77
#define SCLK_I2S0_8CH_RX 78
#define SCLK_I2S0_8CH_RX_OUT 79
#define SCLK_I2S1_8CH_TX 80
#define SCLK_I2S1_8CH_TX_OUT 81
#define SCLK_I2S1_8CH_RX 82
#define SCLK_I2S1_8CH_RX_OUT 83
#define SCLK_I2S2_8CH_TX 84
#define SCLK_I2S2_8CH_TX_OUT 85
#define SCLK_I2S2_8CH_RX 86
#define SCLK_I2S2_8CH_RX_OUT 87
#define SCLK_I2S3_8CH_TX 88
#define SCLK_I2S3_8CH_TX_OUT 89
#define SCLK_I2S3_8CH_RX 90
#define SCLK_I2S3_8CH_RX_OUT 91
#define SCLK_I2S0_2CH 92
#define SCLK_I2S0_2CH_OUT 93
#define SCLK_I2S1_2CH 94
#define SCLK_I2S1_2CH_OUT 95
#define SCLK_SPDIF_TX_DIV 96
#define SCLK_SPDIF_TX_DIV50 97
#define SCLK_SPDIF_TX 98
#define SCLK_SPDIF_RX_DIV 99
#define SCLK_SPDIF_RX_DIV50 100
#define SCLK_SPDIF_RX 101
#define SCLK_I2S0_8CH_TX_MUX 102
#define SCLK_I2S0_8CH_RX_MUX 103
#define SCLK_I2S1_8CH_TX_MUX 104
#define SCLK_I2S1_8CH_RX_MUX 105
#define SCLK_I2S2_8CH_TX_MUX 106
#define SCLK_I2S2_8CH_RX_MUX 107
#define SCLK_I2S3_8CH_TX_MUX 108
#define SCLK_I2S3_8CH_RX_MUX 109
#define SCLK_I2S0_8CH_TX_SRC 110
#define SCLK_I2S0_8CH_RX_SRC 111
#define SCLK_I2S1_8CH_TX_SRC 112
#define SCLK_I2S1_8CH_RX_SRC 113
#define SCLK_I2S2_8CH_TX_SRC 114
#define SCLK_I2S2_8CH_RX_SRC 115
#define SCLK_I2S3_8CH_TX_SRC 116
#define SCLK_I2S3_8CH_RX_SRC 117
#define SCLK_I2S0_2CH_SRC 118
#define SCLK_I2S1_2CH_SRC 119
#define SCLK_PWM1 120
#define SCLK_PWM2 121
#define SCLK_OWIRE 122
/* dclk */
#define DCLK_VOP 125
/* aclk */
#define ACLK_BUS_SRC 130
#define ACLK_BUS 131
#define ACLK_PERI_SRC 132
#define ACLK_PERI 133
#define ACLK_MAC 134
#define ACLK_CRYPTO 135
#define ACLK_VOP 136
#define ACLK_GIC 137
#define ACLK_DMAC0 138
#define ACLK_DMAC1 139
/* hclk */
#define HCLK_BUS 150
#define HCLK_PERI 151
#define HCLK_AUDIO 152
#define HCLK_NANDC 153
#define HCLK_SDMMC 154
#define HCLK_SDIO 155
#define HCLK_EMMC 156
#define HCLK_SFC 157
#define HCLK_OTG 158
#define HCLK_HOST 159
#define HCLK_HOST_ARB 160
#define HCLK_PDM 161
#define HCLK_SPDIFTX 162
#define HCLK_SPDIFRX 163
#define HCLK_I2S0_8CH 164
#define HCLK_I2S1_8CH 165
#define HCLK_I2S2_8CH 166
#define HCLK_I2S3_8CH 167
#define HCLK_I2S0_2CH 168
#define HCLK_I2S1_2CH 169
#define HCLK_VAD 170
#define HCLK_CRYPTO 171
#define HCLK_VOP 172
/* pclk */
#define PCLK_BUS 190
#define PCLK_DDR 191
#define PCLK_PERI 192
#define PCLK_PMU 193
#define PCLK_AUDIO 194
#define PCLK_MAC 195
#define PCLK_ACODEC 196
#define PCLK_UART0 197
#define PCLK_UART1 198
#define PCLK_UART2 199
#define PCLK_UART3 200
#define PCLK_UART4 201
#define PCLK_I2C0 202
#define PCLK_I2C1 203
#define PCLK_I2C2 204
#define PCLK_I2C3 205
#define PCLK_PWM0 206
#define PCLK_SPI0 207
#define PCLK_SPI1 208
#define PCLK_SPI2 209
#define PCLK_SARADC 210
#define PCLK_TSADC 211
#define PCLK_TIMER 212
#define PCLK_OTP_NS 213
#define PCLK_WDT 214
#define PCLK_GPIO0 215
#define PCLK_GPIO1 216
#define PCLK_GPIO2 217
#define PCLK_GPIO3 218
#define PCLK_GPIO4 219
#define PCLK_SGRF 220
#define PCLK_GRF 221
#define PCLK_USBSD_DET 222
#define PCLK_DDR_UPCTL 223
#define PCLK_DDR_MON 224
#define PCLK_DDRPHY 225
#define PCLK_DDR_STDBY 226
#define PCLK_USB_GRF 227
#define PCLK_CRU 228
#define PCLK_OTP_PHY 229
#define PCLK_CPU_BOOST 230
#define PCLK_PWM1 231
#define PCLK_PWM2 232
#define PCLK_CAN 233
#define PCLK_OWIRE 234
#define CLK_NR_CLKS (PCLK_OWIRE + 1)
/* soft-reset indices */
/* cru_softrst_con0 */
#define SRST_CORE0_PO 0
#define SRST_CORE1_PO 1
#define SRST_CORE2_PO 2
#define SRST_CORE3_PO 3
#define SRST_CORE0 4
#define SRST_CORE1 5
#define SRST_CORE2 6
#define SRST_CORE3 7
#define SRST_CORE0_DBG 8
#define SRST_CORE1_DBG 9
#define SRST_CORE2_DBG 10
#define SRST_CORE3_DBG 11
#define SRST_TOPDBG 12
#define SRST_CORE_NOC 13
#define SRST_STRC_A 14
#define SRST_L2C 15
/* cru_softrst_con1 */
#define SRST_DAP 16
#define SRST_CORE_PVTM 17
#define SRST_CORE_PRF 18
#define SRST_CORE_GRF 19
#define SRST_DDRUPCTL 20
#define SRST_DDRUPCTL_P 22
#define SRST_MSCH 23
#define SRST_DDRMON_P 25
#define SRST_DDRSTDBY_P 26
#define SRST_DDRSTDBY 27
#define SRST_DDRPHY 28
#define SRST_DDRPHY_DIV 29
#define SRST_DDRPHY_P 30
/* cru_softrst_con2 */
#define SRST_BUS_NIU_H 32
#define SRST_USB_NIU_P 33
#define SRST_CRYPTO_A 34
#define SRST_CRYPTO_H 35
#define SRST_CRYPTO 36
#define SRST_CRYPTO_APK 37
#define SRST_VOP_A 38
#define SRST_VOP_H 39
#define SRST_VOP_D 40
#define SRST_INTMEM_A 41
#define SRST_ROM_H 42
#define SRST_GIC_A 43
#define SRST_UART0_P 44
#define SRST_UART0 45
#define SRST_UART1_P 46
#define SRST_UART1 47
/* cru_softrst_con3 */
#define SRST_UART2_P 48
#define SRST_UART2 49
#define SRST_UART3_P 50
#define SRST_UART3 51
#define SRST_UART4_P 52
#define SRST_UART4 53
#define SRST_I2C0_P 54
#define SRST_I2C0 55
#define SRST_I2C1_P 56
#define SRST_I2C1 57
#define SRST_I2C2_P 58
#define SRST_I2C2 59
#define SRST_I2C3_P 60
#define SRST_I2C3 61
#define SRST_PWM0_P 62
#define SRST_PWM0 63
/* cru_softrst_con4 */
#define SRST_SPI0_P 64
#define SRST_SPI0 65
#define SRST_SPI1_P 66
#define SRST_SPI1 67
#define SRST_SPI2_P 68
#define SRST_SPI2 69
#define SRST_SARADC_P 70
#define SRST_TSADC_P 71
#define SRST_TSADC 72
#define SRST_TIMER0_P 73
#define SRST_TIMER0 74
#define SRST_TIMER1 75
#define SRST_TIMER2 76
#define SRST_TIMER3 77
#define SRST_TIMER4 78
#define SRST_TIMER5 79
/* cru_softrst_con5 */
#define SRST_OTP_NS_P 80
#define SRST_OTP_NS_SBPI 81
#define SRST_OTP_NS_USR 82
#define SRST_OTP_PHY_P 83
#define SRST_OTP_PHY 84
#define SRST_GPIO0_P 86
#define SRST_GPIO1_P 87
#define SRST_GPIO2_P 88
#define SRST_GPIO3_P 89
#define SRST_GPIO4_P 90
#define SRST_GRF_P 91
#define SRST_USBSD_DET_P 92
#define SRST_PMU 93
#define SRST_PMU_PVTM 94
#define SRST_USB_GRF_P 95
/* cru_softrst_con6 */
#define SRST_CPU_BOOST 96
#define SRST_CPU_BOOST_P 97
#define SRST_PWM1_P 98
#define SRST_PWM1 99
#define SRST_PWM2_P 100
#define SRST_PWM2 101
#define SRST_PERI_NIU_A 104
#define SRST_PERI_NIU_H 105
#define SRST_PERI_NIU_p 106
#define SRST_USB2OTG_H 107
#define SRST_USB2OTG 108
#define SRST_USB2OTG_ADP 109
#define SRST_USB2HOST_H 110
#define SRST_USB2HOST_ARB_H 111
/* cru_softrst_con7 */
#define SRST_USB2HOST_AUX_H 112
#define SRST_USB2HOST_EHCI 113
#define SRST_USB2HOST 114
#define SRST_USBPHYPOR 115
#define SRST_UTMI0 116
#define SRST_UTMI1 117
#define SRST_SDIO_H 118
#define SRST_EMMC_H 119
#define SRST_SFC_H 120
#define SRST_SFC 121
#define SRST_SD_H 122
#define SRST_NANDC_H 123
#define SRST_NANDC_N 124
#define SRST_MAC_A 125
#define SRST_CAN_P 126
#define SRST_OWIRE_P 127
/* cru_softrst_con8 */
#define SRST_AUDIO_NIU_H 128
#define SRST_AUDIO_NIU_P 129
#define SRST_PDM_H 130
#define SRST_PDM_M 131
#define SRST_SPDIFTX_H 132
#define SRST_SPDIFTX_M 133
#define SRST_SPDIFRX_H 134
#define SRST_SPDIFRX_M 135
#define SRST_I2S0_8CH_H 136
#define SRST_I2S0_8CH_TX_M 137
#define SRST_I2S0_8CH_RX_M 138
#define SRST_I2S1_8CH_H 139
#define SRST_I2S1_8CH_TX_M 140
#define SRST_I2S1_8CH_RX_M 141
#define SRST_I2S2_8CH_H 142
#define SRST_I2S2_8CH_TX_M 143
/* cru_softrst_con9 */
#define SRST_I2S2_8CH_RX_M 144
#define SRST_I2S3_8CH_H 145
#define SRST_I2S3_8CH_TX_M 146
#define SRST_I2S3_8CH_RX_M 147
#define SRST_I2S0_2CH_H 148
#define SRST_I2S0_2CH_M 149
#define SRST_I2S1_2CH_H 150
#define SRST_I2S1_2CH_M 151
#define SRST_VAD_H 152
#define SRST_ACODEC_P 153
#endif

27
include/dt-bindings/power/px30-power.h Normal file
View File

@@ -0,0 +1,27 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __DT_BINDINGS_POWER_PX30_POWER_H__
#define __DT_BINDINGS_POWER_PX30_POWER_H__
/* VD_CORE */
#define PX30_PD_A35_0 0
#define PX30_PD_A35_1 1
#define PX30_PD_A35_2 2
#define PX30_PD_A35_3 3
#define PX30_PD_SCU 4
/* VD_LOGIC */
#define PX30_PD_USB 5
#define PX30_PD_DDR 6
#define PX30_PD_SDCARD 7
#define PX30_PD_CRYPTO 8
#define PX30_PD_GMAC 9
#define PX30_PD_MMC_NAND 10
#define PX30_PD_VPU 11
#define PX30_PD_VO 12
#define PX30_PD_VI 13
#define PX30_PD_GPU 14
/* VD_PMU */
#define PX30_PD_PMU 15
#endif

16
include/dt-bindings/soc/rockchip,boot-mode.h Normal file
View File

@@ -0,0 +1,16 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __ROCKCHIP_BOOT_MODE_H
#define __ROCKCHIP_BOOT_MODE_H
/*high 24 bits is tag, low 8 bits is type*/
#define REBOOT_FLAG 0x5242C300
/* normal boot */
#define BOOT_NORMAL (REBOOT_FLAG + 0)
/* enter bootloader rockusb mode */
#define BOOT_BL_DOWNLOAD (REBOOT_FLAG + 1)
/* enter recovery */
#define BOOT_RECOVERY (REBOOT_FLAG + 3)
/* enter fastboot mode */
#define BOOT_FASTBOOT (REBOOT_FLAG + 9)
#endif

4
include/usb/dwc2_udc.h
View File

@@ -8,12 +8,14 @@
#ifndef __DWC2_USB_GADGET
#define __DWC2_USB_GADGET
#include <dm/ofnode.h>
#define PHY0_SLEEP (1 << 5)
#define DWC2_MAX_HW_ENDPOINTS 16
struct dwc2_plat_otg_data {
void *priv;
int phy_of_node;
ofnode phy_of_node;
int (*phy_control)(int on);
uintptr_t regs_phy;
uintptr_t regs_otg;