Merge https://source.denx.de/u-boot/custodians/u-boot-x86

- x86: various improvements made in getting Chromium OS verified boot
  running on top of coreboot, booting into U-Boot.

arch/x86/cpu/coreboot/Kconfig

@@ -1,4 +1,4 @@
-if TARGET_COREBOOT
+if VENDOR_COREBOOT
 
 config SYS_COREBOOT
 	bool

arch/x86/cpu/i386/cpu.c

@@ -423,7 +423,7 @@ static void setup_mtrr(void)
 	u64 mtrr_cap;
 
 	/* Configure fixed range MTRRs for some legacy regions */
-	if (!gd->arch.has_mtrr)
+	if (!gd->arch.has_mtrr || !ll_boot_init())
 		return;
 
 	mtrr_cap = native_read_msr(MTRR_CAP_MSR);

arch/x86/dts/chromebook_coral.dts

@@ -10,7 +10,7 @@
 /include/ "rtc.dtsi"
 /include/ "tsc_timer.dtsi"
 
-#ifdef CONFIG_CHROMEOS_VBOOT
+#if defined(CONFIG_CHROMEOS_VBOOT) && defined(CONFIG_ROM_SIZE)
 #include "chromeos-x86.dtsi"
 #include "flashmap-x86-ro.dtsi"
 #include "flashmap-16mb-rw.dtsi"

arch/x86/dts/chromebook_samus.dts

@@ -11,7 +11,7 @@
 
 #include "smbios.dtsi"
 
-#ifdef CONFIG_CHROMEOS_VBOOT
+#if defined(CONFIG_CHROMEOS_VBOOT) && defined(CONFIG_ROM_SIZE)
 #include "chromeos-x86.dtsi"
 #include "flashmap-x86-ro.dtsi"
 #include "flashmap-8mb-rw.dtsi"

arch/x86/include/asm/cb_sysinfo.h

@@ -215,6 +215,22 @@ struct sysinfo_t {
 
 extern struct sysinfo_t lib_sysinfo;
 
+/**
+ * get_coreboot_info() - parse the coreboot sysinfo table
+ *
+ * Parses the coreboot table if found, setting the GD_FLG_SKIP_LL_INIT flag if
+ * so.
+ *
+ * @info: Place to put the parsed information
+ * @return 0 if OK, -ENOENT if no table found
+ */
 int get_coreboot_info(struct sysinfo_t *info);
 
+/**
+ * cb_get_sysinfo() - get a pointer to the parsed coreboot sysinfo
+ *
+ * @return pointer to sysinfo, or NULL if not available
+ */
+const struct sysinfo_t *cb_get_sysinfo(void);
+
 #endif

arch/x86/include/asm/mp.h

@@ -10,18 +10,22 @@
 
 #include <asm/atomic.h>
 #include <asm/cache.h>
+#include <linux/bitops.h>
 
 struct udevice;
 
 enum {
-	/* Indicates that the function should run on all CPUs */
-	MP_SELECT_ALL	= -1,
+	/*
+	 * Indicates that the function should run on all CPUs. We use a large
+	 * number, above the number of real CPUs we expect to find.
+	 */
+	MP_SELECT_ALL	= BIT(16),
 
 	/* Run on boot CPUs */
-	MP_SELECT_BSP	= -2,
+	MP_SELECT_BSP,
 
 	/* Run on non-boot CPUs */
-	MP_SELECT_APS	= -3,
+	MP_SELECT_APS,
 };
 
 typedef int (*mp_callback_t)(struct udevice *cpu, void *arg);

arch/x86/lib/init_helpers.c

@@ -18,10 +18,20 @@ int init_cache_f_r(void)
 		 IS_ENABLED(CONFIG_FSP_VERSION2);
 	int ret;
 
-	if (!ll_boot_init())
-		return 0;
-
-	do_mtrr &= !IS_ENABLED(CONFIG_FSP_VERSION1) &&
+	/*
+	 * Supported configurations:
+	 *
+	 * booting from slimbootloader - in that case the MTRRs are already set
+	 *	up
+	 * booting with FSPv1 - MTRRs are already set up
+	 * booting with FSPv2 - MTRRs must be set here
+	 * booting from coreboot - in this case there is no SPL, so we set up
+	 *	the MTRRs here
+	 * Note: if there is an SPL, then it has already set up MTRRs so we
+	 *	don't need to do that here
+	 */
+	do_mtrr &= !IS_ENABLED(CONFIG_SPL) &&
+		!IS_ENABLED(CONFIG_FSP_VERSION1) &&
 		!IS_ENABLED(CONFIG_SYS_SLIMBOOTLOADER);
 
 	if (do_mtrr) {

arch/x86/lib/zimage.c

@@ -313,12 +313,12 @@ int setup_zimage(struct boot_params *setup_base, char *cmd_line, int auto_boot,
 	int bootproto = get_boot_protocol(hdr, false);
 
 	log_debug("Setup E820 entries\n");
-	if (ll_boot_init()) {
-		setup_base->e820_entries = install_e820_map(
-			ARRAY_SIZE(setup_base->e820_map), setup_base->e820_map);
-	} else if (IS_ENABLED(CONFIG_COREBOOT_SYSINFO)) {
+	if (IS_ENABLED(CONFIG_COREBOOT_SYSINFO)) {
 		setup_base->e820_entries = cb_install_e820_map(
 			ARRAY_SIZE(setup_base->e820_map), setup_base->e820_map);
+	} else {
+		setup_base->e820_entries = install_e820_map(
+			ARRAY_SIZE(setup_base->e820_map), setup_base->e820_map);
 	}
 
 	if (bootproto == 0x0100) {