Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx
This commit is contained in:
@@ -146,8 +146,6 @@
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#define MEM_LAYOUT_ENV_SETTINGS \
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"bootm_size=0x20000000\0" \
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"fdt_addr_r=0x12100000\0" \
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"fdt_high=0xffffffff\0" \
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"initrd_high=0xffffffff\0" \
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"kernel_addr_r=0x11000000\0" \
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"pxefile_addr_r=0x17100000\0" \
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"ramdisk_addr_r=0x12200000\0" \
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@@ -40,8 +40,6 @@
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#define MEM_LAYOUT_ENV_SETTINGS \
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"bootm_size=0x10000000\0" \
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"fdt_addr_r=0x82100000\0" \
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"fdt_high=0xffffffff\0" \
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"initrd_high=0xffffffff\0" \
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"kernel_addr_r=0x81000000\0" \
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"pxefile_addr_r=0x87100000\0" \
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"ramdisk_addr_r=0x82200000\0" \
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@@ -134,8 +134,6 @@
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#define MEM_LAYOUT_ENV_SETTINGS \
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"bootm_size=0x10000000\0" \
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"fdt_addr_r=0x12100000\0" \
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"fdt_high=0xffffffff\0" \
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"initrd_high=0xffffffff\0" \
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"kernel_addr_r=0x11000000\0" \
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"pxefile_addr_r=0x17100000\0" \
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"ramdisk_addr_r=0x12200000\0" \
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@@ -108,8 +108,6 @@
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#define MEM_LAYOUT_ENV_SETTINGS \
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"bootm_size=0x10000000\0" \
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"fdt_addr_r=0x82000000\0" \
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"fdt_high=0xffffffff\0" \
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"initrd_high=0xffffffff\0" \
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"kernel_addr_r=0x81000000\0" \
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"ramdisk_addr_r=0x82100000\0" \
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"scriptaddr=0x82500000\0"
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@@ -51,8 +51,6 @@
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#define MEM_LAYOUT_ENV_SETTINGS \
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"bootm_size=0x10000000\0" \
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"fdt_addr_r=0x82000000\0" \
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"fdt_high=0xffffffff\0" \
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"initrd_high=0xffffffff\0" \
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"kernel_addr_r=0x81000000\0" \
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"pxefile_addr_r=0x87100000\0" \
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"ramdisk_addr_r=0x82100000\0" \
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46
include/configs/imxrt1020-evk.h
Normal file
46
include/configs/imxrt1020-evk.h
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@@ -0,0 +1,46 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2020
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* Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
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*/
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#ifndef __IMXRT1020_EVK_H
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#define __IMXRT1020_EVK_H
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#include <asm/arch/imx-regs.h>
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#define CONFIG_SYS_INIT_SP_ADDR 0x20240000
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#ifdef CONFIG_SUPPORT_SPL
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#define CONFIG_SYS_LOAD_ADDR 0x20209000
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#else
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#define CONFIG_SYS_LOAD_ADDR 0x80000000
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#define CONFIG_LOADADDR 0x80000000
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#endif
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#define CONFIG_SYS_FSL_ERRATUM_ESDHC135 1
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#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 1
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#define PHYS_SDRAM 0x80000000
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#define PHYS_SDRAM_SIZE (32 * 1024 * 1024)
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#define DMAMEM_SZ_ALL (1 * 1024 * 1024)
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#define DMAMEM_BASE (PHYS_SDRAM + PHYS_SDRAM_SIZE - \
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DMAMEM_SZ_ALL)
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#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */
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/*
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* Configuration of the external SDRAM memory
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*/
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#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024)
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/* For SPL */
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#ifdef CONFIG_SUPPORT_SPL
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#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
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#define CONFIG_SYS_SPL_LEN 0x00008000
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#define CONFIG_SYS_UBOOT_START 0x800023FD
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#endif
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/* For SPL ends */
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#endif /* __IMXRT1020_EVK_H */
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@@ -30,6 +30,21 @@
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#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */
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#ifdef CONFIG_DM_VIDEO
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#define CONFIG_VIDEO_MXS
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#define CONFIG_VIDEO_LOGO
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#define CONFIG_SPLASH_SCREEN
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#define CONFIG_SPLASH_SCREEN_ALIGN
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#define CONFIG_BMP_16BPP
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#define CONFIG_VIDEO_BMP_RLE8
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#define CONFIG_VIDEO_BMP_LOGO
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"stdin=serial\0" \
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"stdout=serial,vidconsole\0" \
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"stderr=serial,vidconsole\0"
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#endif
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/*
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* Configuration of the external SDRAM memory
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*/
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@@ -172,7 +172,6 @@
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#endif
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#ifdef CONFIG_CMD_NET
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#define CONFIG_FEC_MXC
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#define CONFIG_FEC_ENET_DEV 1
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#if (CONFIG_FEC_ENET_DEV == 0)
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@@ -166,4 +166,13 @@
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#define FSL_QSPI_FLASH_SIZE SZ_32M
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#endif
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#ifdef CONFIG_CMD_NET
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#define CONFIG_FEC_ENET_DEV 1
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#if (CONFIG_FEC_ENET_DEV == 0)
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#define CONFIG_ETHPRIME "eth0"
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#elif (CONFIG_FEC_ENET_DEV == 1)
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#define CONFIG_ETHPRIME "eth1"
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#endif
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#endif
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#endif
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@@ -28,18 +28,11 @@
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#define PHYS_SDRAM_SIZE (SZ_1G)
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#endif
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#define CONFIG_MXC_UART
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/* SPI Flash */
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#define TQMA6_SPI_FLASH_SECTOR_SIZE SZ_64K
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/* I2C Configs */
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_MXC
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#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
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#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
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#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
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#define CONFIG_I2C_MULTI_BUS
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#define CONFIG_SYS_I2C_SPEED 100000
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@@ -49,11 +42,13 @@
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#define CONFIG_SYS_I2C_EEPROM_PAGE_WRITE_BITS 5 /* 32 Bytes */
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#define CONFIG_SYS_I2C_EEPROM_PAGE_WRITE_DELAY_MS 20
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#if !defined(CONFIG_DM_PMIC)
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#define CONFIG_POWER
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#define CONFIG_POWER_I2C
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#define CONFIG_POWER_PFUZE100
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#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
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#define TQMA6_PFUZE100_I2C_BUS 2
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#endif
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/* MMC Configs */
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#define CONFIG_SYS_FSL_ESDHC_ADDR 0
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@@ -30,4 +30,7 @@
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/* Bootcounter */
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#define CONFIG_SYS_BOOTCOUNT_BE
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/* I2C */
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#define CONFIG_SYS_I2C
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#endif /* __CONFIG_TQMA6_WRU4_H */
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@@ -66,6 +66,12 @@
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"initrd_addr=0x43800000\0" \
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"initrd_high=0xffffffffffffffff\0" \
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"kernel_image=Image\0" \
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"netargs=setenv bootargs console=${console},${baudrate} " \
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"root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp" \
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"\0" \
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"nfsboot=run netargs; dhcp ${loadaddr} ${kernel_image}; " \
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"tftp ${fdt_addr} verdin/${fdtfile}; " \
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"booti ${loadaddr} - ${fdt_addr}\0" \
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"setup=setenv setupargs console=${console},${baudrate} " \
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"console=tty1 consoleblank=0 earlycon\0" \
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"update_uboot=askenv confirm Did you load flash.bin (y/N)?; " \
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