This commit is contained in:
Tom Rini
2020-04-20 08:45:27 -04:00
92 changed files with 3152 additions and 491 deletions

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@@ -146,8 +146,6 @@
#define MEM_LAYOUT_ENV_SETTINGS \
"bootm_size=0x20000000\0" \
"fdt_addr_r=0x12100000\0" \
"fdt_high=0xffffffff\0" \
"initrd_high=0xffffffff\0" \
"kernel_addr_r=0x11000000\0" \
"pxefile_addr_r=0x17100000\0" \
"ramdisk_addr_r=0x12200000\0" \

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@@ -40,8 +40,6 @@
#define MEM_LAYOUT_ENV_SETTINGS \
"bootm_size=0x10000000\0" \
"fdt_addr_r=0x82100000\0" \
"fdt_high=0xffffffff\0" \
"initrd_high=0xffffffff\0" \
"kernel_addr_r=0x81000000\0" \
"pxefile_addr_r=0x87100000\0" \
"ramdisk_addr_r=0x82200000\0" \

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@@ -134,8 +134,6 @@
#define MEM_LAYOUT_ENV_SETTINGS \
"bootm_size=0x10000000\0" \
"fdt_addr_r=0x12100000\0" \
"fdt_high=0xffffffff\0" \
"initrd_high=0xffffffff\0" \
"kernel_addr_r=0x11000000\0" \
"pxefile_addr_r=0x17100000\0" \
"ramdisk_addr_r=0x12200000\0" \

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@@ -108,8 +108,6 @@
#define MEM_LAYOUT_ENV_SETTINGS \
"bootm_size=0x10000000\0" \
"fdt_addr_r=0x82000000\0" \
"fdt_high=0xffffffff\0" \
"initrd_high=0xffffffff\0" \
"kernel_addr_r=0x81000000\0" \
"ramdisk_addr_r=0x82100000\0" \
"scriptaddr=0x82500000\0"

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@@ -51,8 +51,6 @@
#define MEM_LAYOUT_ENV_SETTINGS \
"bootm_size=0x10000000\0" \
"fdt_addr_r=0x82000000\0" \
"fdt_high=0xffffffff\0" \
"initrd_high=0xffffffff\0" \
"kernel_addr_r=0x81000000\0" \
"pxefile_addr_r=0x87100000\0" \
"ramdisk_addr_r=0x82100000\0" \

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@@ -0,0 +1,46 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2020
* Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
*/
#ifndef __IMXRT1020_EVK_H
#define __IMXRT1020_EVK_H
#include <asm/arch/imx-regs.h>
#define CONFIG_SYS_INIT_SP_ADDR 0x20240000
#ifdef CONFIG_SUPPORT_SPL
#define CONFIG_SYS_LOAD_ADDR 0x20209000
#else
#define CONFIG_SYS_LOAD_ADDR 0x80000000
#define CONFIG_LOADADDR 0x80000000
#endif
#define CONFIG_SYS_FSL_ERRATUM_ESDHC135 1
#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 1
#define PHYS_SDRAM 0x80000000
#define PHYS_SDRAM_SIZE (32 * 1024 * 1024)
#define DMAMEM_SZ_ALL (1 * 1024 * 1024)
#define DMAMEM_BASE (PHYS_SDRAM + PHYS_SDRAM_SIZE - \
DMAMEM_SZ_ALL)
#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */
/*
* Configuration of the external SDRAM memory
*/
#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024)
/* For SPL */
#ifdef CONFIG_SUPPORT_SPL
#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
#define CONFIG_SYS_SPL_LEN 0x00008000
#define CONFIG_SYS_UBOOT_START 0x800023FD
#endif
/* For SPL ends */
#endif /* __IMXRT1020_EVK_H */

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@@ -30,6 +30,21 @@
#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */
#ifdef CONFIG_DM_VIDEO
#define CONFIG_VIDEO_MXS
#define CONFIG_VIDEO_LOGO
#define CONFIG_SPLASH_SCREEN
#define CONFIG_SPLASH_SCREEN_ALIGN
#define CONFIG_BMP_16BPP
#define CONFIG_VIDEO_BMP_RLE8
#define CONFIG_VIDEO_BMP_LOGO
#define CONFIG_EXTRA_ENV_SETTINGS \
"stdin=serial\0" \
"stdout=serial,vidconsole\0" \
"stderr=serial,vidconsole\0"
#endif
/*
* Configuration of the external SDRAM memory
*/

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@@ -172,7 +172,6 @@
#endif
#ifdef CONFIG_CMD_NET
#define CONFIG_FEC_MXC
#define CONFIG_FEC_ENET_DEV 1
#if (CONFIG_FEC_ENET_DEV == 0)

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@@ -166,4 +166,13 @@
#define FSL_QSPI_FLASH_SIZE SZ_32M
#endif
#ifdef CONFIG_CMD_NET
#define CONFIG_FEC_ENET_DEV 1
#if (CONFIG_FEC_ENET_DEV == 0)
#define CONFIG_ETHPRIME "eth0"
#elif (CONFIG_FEC_ENET_DEV == 1)
#define CONFIG_ETHPRIME "eth1"
#endif
#endif
#endif

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@@ -28,18 +28,11 @@
#define PHYS_SDRAM_SIZE (SZ_1G)
#endif
#define CONFIG_MXC_UART
/* SPI Flash */
#define TQMA6_SPI_FLASH_SECTOR_SIZE SZ_64K
/* I2C Configs */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
#define CONFIG_I2C_MULTI_BUS
#define CONFIG_SYS_I2C_SPEED 100000
@@ -49,11 +42,13 @@
#define CONFIG_SYS_I2C_EEPROM_PAGE_WRITE_BITS 5 /* 32 Bytes */
#define CONFIG_SYS_I2C_EEPROM_PAGE_WRITE_DELAY_MS 20
#if !defined(CONFIG_DM_PMIC)
#define CONFIG_POWER
#define CONFIG_POWER_I2C
#define CONFIG_POWER_PFUZE100
#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
#define TQMA6_PFUZE100_I2C_BUS 2
#endif
/* MMC Configs */
#define CONFIG_SYS_FSL_ESDHC_ADDR 0

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@@ -30,4 +30,7 @@
/* Bootcounter */
#define CONFIG_SYS_BOOTCOUNT_BE
/* I2C */
#define CONFIG_SYS_I2C
#endif /* __CONFIG_TQMA6_WRU4_H */

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@@ -66,6 +66,12 @@
"initrd_addr=0x43800000\0" \
"initrd_high=0xffffffffffffffff\0" \
"kernel_image=Image\0" \
"netargs=setenv bootargs console=${console},${baudrate} " \
"root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp" \
"\0" \
"nfsboot=run netargs; dhcp ${loadaddr} ${kernel_image}; " \
"tftp ${fdt_addr} verdin/${fdtfile}; " \
"booti ${loadaddr} - ${fdt_addr}\0" \
"setup=setenv setupargs console=${console},${baudrate} " \
"console=tty1 consoleblank=0 earlycon\0" \
"update_uboot=askenv confirm Did you load flash.bin (y/N)?; " \