Merge tag 'u-boot-imx-20181025' of git://git.denx.de/u-boot-imx
Merged imx8 architecture, fix build for imx8 + warnings
This commit is contained in:
Tom Rini
@@ -192,9 +192,6 @@
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/* UBI support */
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#define CONFIG_HW_WATCHDOG
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#define CONFIG_IMX_WATCHDOG
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/* Framebuffer */
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#define CONFIG_VIDEO_IPUV3
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/* check this console not needed, after test remove it */
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@@ -10,8 +10,6 @@
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#include "mx7_common.h"
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#define CONFIG_DBG_MONITOR
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#define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR
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/* Size of malloc() pool */
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@@ -13,7 +13,6 @@
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#include "mx6_common.h"
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#define CONFIG_IOMUX_LPSR
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/* #define CONFIG_DBG_MONITOR*/
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#define PHYS_SDRAM_SIZE SZ_512M
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/* Size of malloc() pool */
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@@ -13,9 +13,6 @@
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#include "mx7_common.h"
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/*#define CONFIG_DBG_MONITOR*/
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#define PHYS_SDRAM_SIZE SZ_1G
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/* Size of malloc() pool */
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#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M)
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@@ -109,8 +109,6 @@
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#endif
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/* Watchdog */
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#define CONFIG_HW_WATCHDOG
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#define CONFIG_IMX_WATCHDOG
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#define CONFIG_WATCHDOG_TIMEOUT_MSECS 60000
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/* allow to overwrite serial and ethaddr */
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@@ -368,8 +368,6 @@
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/* Commands */
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/* Watchdog */
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#define CONFIG_HW_WATCHDOG
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#define CONFIG_IMX_WATCHDOG
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#define CONFIG_WATCHDOG_TIMEOUT_MSECS 15000
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/* ENV config */
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@@ -31,8 +31,6 @@
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#define CONFIG_REVISION_TAG
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#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M)
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#define CONFIG_HW_WATCHDOG
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#define CONFIG_IMX_WATCHDOG
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#define CONFIG_WATCHDOG_TIMEOUT_MSECS 6000
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#define CONFIG_MXC_UART
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157
include/configs/imx8qxp_mek.h
Normal file
157
include/configs/imx8qxp_mek.h
Normal file
@@ -0,0 +1,157 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2018 NXP
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*/
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#ifndef __IMX8QXP_MEK_H
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#define __IMX8QXP_MEK_H
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#include <linux/sizes.h>
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#include <asm/arch/imx-regs.h>
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#define CONFIG_REMAKE_ELF
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#define CONFIG_BOARD_EARLY_INIT_F
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/* Flat Device Tree Definitions */
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#define CONFIG_OF_BOARD_SETUP
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#undef CONFIG_CMD_EXPORTENV
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#undef CONFIG_CMD_IMPORTENV
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#undef CONFIG_CMD_IMLS
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#undef CONFIG_CMD_CRC32
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#undef CONFIG_BOOTM_NETBSD
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#define CONFIG_FSL_ESDHC
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#define CONFIG_FSL_USDHC
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#define CONFIG_SYS_FSL_ESDHC_ADDR 0
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#define USDHC1_BASE_ADDR 0x5B010000
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#define USDHC2_BASE_ADDR 0x5B020000
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#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
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/* Initial environment variables */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"script=boot.scr\0" \
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"image=Image\0" \
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"panel=NULL\0" \
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"console=ttyLP0,${baudrate} earlycon=lpuart32,0x5a060000,${baudrate}\0" \
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"fdt_addr=0x83000000\0" \
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"fdt_high=0xffffffffffffffff\0" \
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"boot_fdt=try\0" \
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"fdt_file=fsl-imx8qxp-mek.dtb\0" \
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"initrd_addr=0x83800000\0" \
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"initrd_high=0xffffffffffffffff\0" \
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"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
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"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
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"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
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"mmcautodetect=yes\0" \
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"mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \
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"loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
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"bootscript=echo Running bootscript from mmc ...; " \
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"source\0" \
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"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
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"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
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"mmcboot=echo Booting from mmc ...; " \
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"run mmcargs; " \
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"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
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"if run loadfdt; then " \
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"booti ${loadaddr} - ${fdt_addr}; " \
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"else " \
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"echo WARN: Cannot load the DT; " \
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"fi; " \
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"else " \
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"echo wait for boot; " \
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"fi;\0" \
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"netargs=setenv bootargs console=${console} " \
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"root=/dev/nfs " \
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"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
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"netboot=echo Booting from net ...; " \
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"run netargs; " \
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"if test ${ip_dyn} = yes; then " \
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"setenv get_cmd dhcp; " \
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"else " \
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"setenv get_cmd tftp; " \
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"fi; " \
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"${get_cmd} ${loadaddr} ${image}; " \
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"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
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"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
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"booti ${loadaddr} - ${fdt_addr}; " \
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"else " \
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"echo WARN: Cannot load the DT; " \
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"fi; " \
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"else " \
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"booti; " \
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"fi;\0"
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#define CONFIG_BOOTCOMMAND \
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"mmc dev ${mmcdev}; if mmc rescan; then " \
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"if run loadbootscript; then " \
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"run bootscript; " \
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"else " \
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"if run loadimage; then " \
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"run mmcboot; " \
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"else run netboot; " \
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"fi; " \
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"fi; " \
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"else booti ${loadaddr} - ${fdt_addr}; fi"
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/* Link Definitions */
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#define CONFIG_LOADADDR 0x80280000
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#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
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#define CONFIG_SYS_INIT_SP_ADDR 0x80200000
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/* Default environment is in SD */
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#define CONFIG_ENV_SIZE 0x1000
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#define CONFIG_ENV_OFFSET (64 * SZ_64K)
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#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */
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#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
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/* On LPDDR4 board, USDHC1 is for eMMC, USDHC2 is for SD on CPU board */
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#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */
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#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
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#define CONFIG_SYS_FSL_USDHC_NUM 2
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/* Size of malloc() pool */
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#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32 * 1024)) * 1024)
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#define CONFIG_SYS_SDRAM_BASE 0x80000000
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#define PHYS_SDRAM_1 0x80000000
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#define PHYS_SDRAM_2 0x880000000
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#define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */
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/* LPDDR4 board total DDR is 3GB */
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#define PHYS_SDRAM_2_SIZE 0x40000000 /* 1 GB */
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/* Serial */
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#define CONFIG_BAUDRATE 115200
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/* Monitor Command Prompt */
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#define CONFIG_HUSH_PARSER
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#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
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#define CONFIG_SYS_CBSIZE 2048
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#define CONFIG_SYS_MAXARGS 64
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
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sizeof(CONFIG_SYS_PROMPT) + 16)
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/* Generic Timer Definitions */
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#define COUNTER_FREQUENCY 8000000 /* 8MHz */
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#ifndef CONFIG_DM_PCA953X
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#define CONFIG_PCA953X
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#define CONFIG_CMD_PCA953X
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#define CONFIG_CMD_PCA953X_INFO
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#endif
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/* Networking */
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#define CONFIG_FEC_XCV_TYPE RGMII
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#define FEC_QUIRK_ENET_MAC
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#endif /* __IMX8QXP_MEK_H */
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@@ -67,8 +67,6 @@
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#endif
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/* Watchdog */
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#define CONFIG_HW_WATCHDOG
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#define CONFIG_IMX_WATCHDOG
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#define CONFIG_WATCHDOG_TIMEOUT_MSECS 60000
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/* allow to overwrite serial and ethaddr */
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246
include/configs/m53menlo.h
Normal file
246
include/configs/m53menlo.h
Normal file
@@ -0,0 +1,246 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Menlosystems M53Menlo configuration
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* Copyright (C) 2012-2017 Marek Vasut <marex@denx.de>
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* Copyright (C) 2014-2017 Olaf Mandel <o.mandel@menlosystems.com>
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*/
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#ifndef __M53MENLO_CONFIG_H__
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#define __M53MENLO_CONFIG_H__
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#include <asm/arch/imx-regs.h>
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#define CONFIG_REVISION_TAG
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#define CONFIG_SYS_FSL_CLK
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#define CONFIG_TIMESTAMP /* Print image info with timestamp */
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/*
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* Memory configurations
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*/
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#define PHYS_SDRAM_1 CSD0_BASE_ADDR
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#define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size)
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#define PHYS_SDRAM_2 CSD1_BASE_ADDR
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#define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size)
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#define PHYS_SDRAM_SIZE (gd->ram_size)
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#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
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#define CONFIG_SYS_MEMTEST_START 0x70000000
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#define CONFIG_SYS_MEMTEST_END 0x8ff00000
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#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
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#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
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#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET \
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(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_ADDR \
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(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
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/*
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* U-Boot general configurations
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*/
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
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#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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/* Boot argument buffer size */
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|
||||
/*
|
||||
* Serial Driver
|
||||
*/
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||||
#define CONFIG_MXC_UART
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||||
#define CONFIG_MXC_UART_BASE UART1_BASE
|
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|
||||
/*
|
||||
* MMC Driver
|
||||
*/
|
||||
#ifdef CONFIG_CMD_MMC
|
||||
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
|
||||
#define CONFIG_SYS_FSL_ESDHC_NUM 1
|
||||
#endif
|
||||
|
||||
/*
|
||||
* NAND
|
||||
*/
|
||||
#define CONFIG_ENV_SIZE (16 * 1024)
|
||||
#ifdef CONFIG_CMD_NAND
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1
|
||||
#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR_AXI
|
||||
#define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR_AXI
|
||||
#define CONFIG_MXC_NAND_IP_REGS_BASE NFC_BASE_ADDR
|
||||
#define CONFIG_SYS_NAND_LARGEPAGE
|
||||
#define CONFIG_MXC_NAND_HWECC
|
||||
#define CONFIG_SYS_NAND_USE_FLASH_BBT
|
||||
|
||||
/* Environment is in NAND */
|
||||
#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
|
||||
#define CONFIG_ENV_SECT_SIZE (128 * 1024)
|
||||
#define CONFIG_ENV_RANGE (4 * CONFIG_ENV_SECT_SIZE)
|
||||
#define CONFIG_ENV_OFFSET (8 * CONFIG_ENV_SECT_SIZE) /* 1 MiB */
|
||||
#define CONFIG_ENV_OFFSET_REDUND \
|
||||
(CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Ethernet on SOC (FEC)
|
||||
*/
|
||||
#ifdef CONFIG_CMD_NET
|
||||
#define CONFIG_FEC_MXC
|
||||
#define IMX_FEC_BASE FEC_BASE_ADDR
|
||||
#define CONFIG_FEC_MXC_PHYADDR 0x0
|
||||
#define CONFIG_MII
|
||||
#define CONFIG_DISCOVER_PHY
|
||||
#define CONFIG_FEC_XCV_TYPE RMII
|
||||
#define CONFIG_ETHPRIME "FEC0"
|
||||
#endif
|
||||
|
||||
/*
|
||||
* I2C
|
||||
*/
|
||||
#ifdef CONFIG_CMD_I2C
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_MXC
|
||||
#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
|
||||
#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
|
||||
#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
|
||||
#define CONFIG_SYS_RTC_BUS_NUM 1 /* I2C2 */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* RTC
|
||||
*/
|
||||
#ifdef CONFIG_CMD_DATE
|
||||
#define CONFIG_RTC_M41T62
|
||||
#define CONFIG_SYS_I2C_RTC_ADDR 0x68
|
||||
#define CONFIG_SYS_M41T11_BASE_YEAR 2000
|
||||
#endif
|
||||
|
||||
/*
|
||||
* USB
|
||||
*/
|
||||
#ifdef CONFIG_CMD_USB
|
||||
#define CONFIG_USB_EHCI_MX5
|
||||
#define CONFIG_MXC_USB_PORT 1
|
||||
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
|
||||
#define CONFIG_MXC_USB_FLAGS 0
|
||||
#endif
|
||||
|
||||
/*
|
||||
* SATA
|
||||
*/
|
||||
#ifdef CONFIG_CMD_SATA
|
||||
#define CONFIG_SYS_SATA_MAX_DEVICE 1
|
||||
#define CONFIG_DWC_AHSATA_PORT_ID 0
|
||||
#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_BASE_ADDR
|
||||
#define CONFIG_LBA48
|
||||
#endif
|
||||
|
||||
/*
|
||||
* LCD
|
||||
*/
|
||||
#ifdef CONFIG_VIDEO
|
||||
#define CONFIG_VIDEO_IPUV3
|
||||
#define CONFIG_VIDEO_BMP_RLE8
|
||||
#define CONFIG_VIDEO_BMP_GZIP
|
||||
#define CONFIG_SPLASH_SCREEN
|
||||
#define CONFIG_SPLASHIMAGE_GUARD
|
||||
#define CONFIG_SPLASH_SCREEN_ALIGN
|
||||
#define CONFIG_BMP_16BPP
|
||||
#define CONFIG_VIDEO_LOGO
|
||||
#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20)
|
||||
#endif
|
||||
|
||||
/* LVDS display */
|
||||
#define CONFIG_SYS_LDB_CLOCK 33260000
|
||||
#define CONFIG_IMX_VIDEO_SKIP
|
||||
#define CONFIG_SPLASH_SOURCE
|
||||
|
||||
/* IIM Fuses */
|
||||
#define CONFIG_FSL_IIM
|
||||
|
||||
/*
|
||||
* Boot Linux
|
||||
*/
|
||||
#define CONFIG_CMDLINE_TAG
|
||||
#define CONFIG_INITRD_TAG
|
||||
#define CONFIG_REVISION_TAG
|
||||
#define CONFIG_SETUP_MEMORY_TAGS
|
||||
#define CONFIG_BOOTFILE "boot/fitImage"
|
||||
#define CONFIG_LOADADDR 0x70800000
|
||||
#define CONFIG_BOOTCOMMAND "run mmc_mmc"
|
||||
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
|
||||
|
||||
/*
|
||||
* NAND SPL
|
||||
*/
|
||||
#define CONFIG_SPL_TARGET "u-boot-with-nand-spl.imx"
|
||||
#define CONFIG_SPL_TEXT_BASE 0x70008000
|
||||
#define CONFIG_SPL_PAD_TO 0x8000
|
||||
#define CONFIG_SPL_STACK 0x70004000
|
||||
|
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
|
||||
#define CONFIG_SYS_NAND_PAGE_SIZE 2048
|
||||
#define CONFIG_SYS_NAND_OOBSIZE 64
|
||||
#define CONFIG_SYS_NAND_PAGE_COUNT 64
|
||||
#define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024)
|
||||
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
|
||||
|
||||
/*
|
||||
* Extra Environments
|
||||
*/
|
||||
#define CONFIG_PREBOOT "run try_bootscript"
|
||||
#define CONFIG_HOSTNAME "m53menlo"
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"consdev=ttymxc0\0" \
|
||||
"baudrate=115200\0" \
|
||||
"bootscript=boot.scr\0" \
|
||||
"mmcdev=0\0" \
|
||||
"mmcpart=1\0" \
|
||||
"rootpath=/srv/\0" \
|
||||
"kernel_addr_r=0x72000000\0" \
|
||||
"mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
|
||||
"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
|
||||
"netdev=eth0\0" \
|
||||
"splashsource=mmc_fs\0" \
|
||||
"splashfile=usplash.bmp.gz\0" \
|
||||
"splashimage=0x88000000\0" \
|
||||
"splashpos=m,m\0" \
|
||||
"addcons=" \
|
||||
"setenv bootargs ${bootargs} " \
|
||||
"console=${consdev},${baudrate}\0" \
|
||||
"addip=" \
|
||||
"setenv bootargs ${bootargs} " \
|
||||
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
|
||||
":${hostname}:${netdev}:off\0" \
|
||||
"addmtd=setenv bootargs ${bootargs} mtdparts=${mtdparts}\0" \
|
||||
"addmisc=" \
|
||||
"setenv bootargs ${bootargs} ${miscargs}\0" \
|
||||
"addargs=run addcons addmisc addmtd\0" \
|
||||
"mmcload=" \
|
||||
"mmc rescan ; load mmc ${mmcdev}:${mmcpart} " \
|
||||
"${kernel_addr_r} ${bootfile}\0" \
|
||||
"miscargs=nohlt panic=1\0" \
|
||||
"mmcargs=setenv bootargs root=/dev/mmcblk0p${mmcpart} rw " \
|
||||
"rootwait\0" \
|
||||
"mmc_mmc=" \
|
||||
"run mmcload mmcargs addargs ; " \
|
||||
"bootm ${kernel_addr_r}\0" \
|
||||
"netload=tftp ${kernel_addr_r} ${hostname}/${bootfile}\0" \
|
||||
"net_nfs=" \
|
||||
"run netload nfsargs addip addargs ; " \
|
||||
"bootm ${kernel_addr_r}\0" \
|
||||
"nfsargs=" \
|
||||
"setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=${serverip}:${rootpath}${hostname},v3,tcp\0" \
|
||||
"try_bootscript=" \
|
||||
"mmc rescan;" \
|
||||
"if test -e mmc 0:1 ${bootscript} ; then " \
|
||||
"if load mmc 0:1 ${kernel_addr_r} ${bootscript};" \
|
||||
"then ; " \
|
||||
"echo Running bootscript... ; " \
|
||||
"source ${kernel_addr_r} ; " \
|
||||
"fi ; " \
|
||||
"fi\0"
|
||||
|
||||
#endif /* __M53MENLO_CONFIG_H__ */
|
||||
@@ -22,8 +22,6 @@
|
||||
/* Size of malloc() pool */
|
||||
#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
|
||||
|
||||
#define CONFIG_HW_WATCHDOG
|
||||
#define CONFIG_IMX_WATCHDOG
|
||||
#define CONFIG_WATCHDOG_TIMEOUT_MSECS 8000
|
||||
|
||||
#define CONFIG_BOARD_LATE_INIT
|
||||
|
||||
@@ -10,7 +10,6 @@
|
||||
|
||||
#include "mx7_common.h"
|
||||
|
||||
#define CONFIG_DBG_MONITOR
|
||||
#define PHYS_SDRAM_SIZE SZ_1G
|
||||
|
||||
#define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR
|
||||
|
||||
@@ -56,8 +56,8 @@
|
||||
|
||||
#define CONFIG_DFU_ENV_SETTINGS \
|
||||
"dfu_alt_info=" \
|
||||
"spl raw 0x2 0x400 mmcpart 1;" \
|
||||
"u-boot raw 0x8a 0x400 mmcpart 1;" \
|
||||
"spl raw 0x2 0x400;" \
|
||||
"u-boot raw 0x8a 0x400;" \
|
||||
"/boot/zImage ext4 0 1;" \
|
||||
"/boot/imx6ul-pico-hobbit.dtb ext4 0 1;" \
|
||||
"/boot/imx6ul-pico-pi.dtb ext4 0 1;" \
|
||||
@@ -103,6 +103,8 @@
|
||||
|
||||
#define BOOT_TARGET_DEVICES(func) \
|
||||
func(MMC, mmc, 0) \
|
||||
func(USB, usb, 0) \
|
||||
func(PXE, pxe, na) \
|
||||
func(DHCP, dhcp, na)
|
||||
|
||||
#include <config_distro_bootcmd.h>
|
||||
|
||||
@@ -45,8 +45,8 @@
|
||||
|
||||
#define CONFIG_DFU_ENV_SETTINGS \
|
||||
"dfu_alt_info=" \
|
||||
"spl raw 0x2 0x400 mmcpart 1;" \
|
||||
"u-boot raw 0x8a 0x400 mmcpart 1;" \
|
||||
"spl raw 0x2 0x400;" \
|
||||
"u-boot raw 0x8a 0x400;" \
|
||||
"/boot/zImage ext4 0 1;" \
|
||||
"/boot/imx7d-pico-hobbit.dtb ext4 0 1;" \
|
||||
"/boot/imx7d-pico-pi.dtb ext4 0 1;" \
|
||||
@@ -92,6 +92,8 @@
|
||||
|
||||
#define BOOT_TARGET_DEVICES(func) \
|
||||
func(MMC, mmc, 0) \
|
||||
func(USB, usb, 0) \
|
||||
func(PXE, pxe, na) \
|
||||
func(DHCP, dhcp, na)
|
||||
|
||||
#include <config_distro_bootcmd.h>
|
||||
|
||||
@@ -17,8 +17,6 @@
|
||||
#define CONSOLE_DEV "ttymxc3"
|
||||
|
||||
/* Watchdog */
|
||||
#define CONFIG_HW_WATCHDOG
|
||||
#define CONFIG_IMX_WATCHDOG
|
||||
#define CONFIG_WATCHDOG_TIMEOUT_MSECS 60000
|
||||
|
||||
/* Config on-board RTC */
|
||||
|
||||
@@ -26,8 +26,6 @@
|
||||
#define CONFIG_SUPPORT_EMMC_BOOT
|
||||
|
||||
/* Watchdog */
|
||||
#define CONFIG_HW_WATCHDOG
|
||||
#define CONFIG_IMX_WATCHDOG
|
||||
#define CONFIG_WATCHDOG_TIMEOUT_MSECS 30000 /* 30s */
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x80000000
|
||||
|
||||
@@ -13,6 +13,17 @@
|
||||
|
||||
#define PHYS_SDRAM_SIZE SZ_512M
|
||||
|
||||
/*
|
||||
* If we have defined the OPTEE ram size and not OPTEE it means that we were
|
||||
* launched by OPTEE, because of that we shall skip all the low level
|
||||
* initialization since it was already done by ATF or OPTEE
|
||||
*/
|
||||
#ifdef CONFIG_OPTEE_TZDRAM_SIZE
|
||||
#ifndef CONFIG_OPTEE
|
||||
#define CONFIG_SKIP_LOWLEVEL_INIT
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR
|
||||
|
||||
/* Size of malloc() pool */
|
||||
|
||||
583
include/dt-bindings/clock/imx8qxp-clock.h
Normal file
583
include/dt-bindings/clock/imx8qxp-clock.h
Normal file
@@ -0,0 +1,583 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2018 NXP
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_CLOCK_IMX8QXP_H
|
||||
#define __DT_BINDINGS_CLOCK_IMX8QXP_H
|
||||
|
||||
#define IMX8QXP_CLK_DUMMY 0
|
||||
|
||||
#define IMX8QXP_UART0_IPG_CLK 1
|
||||
#define IMX8QXP_UART0_DIV 2
|
||||
#define IMX8QXP_UART0_CLK 3
|
||||
|
||||
#define IMX8QXP_IPG_DMA_CLK_ROOT 4
|
||||
|
||||
/* GPU Clocks. */
|
||||
#define IMX8QXP_GPU0_CORE_DIV 5
|
||||
#define IMX8QXP_GPU0_CORE_CLK 6
|
||||
#define IMX8QXP_GPU0_SHADER_DIV 7
|
||||
#define IMX8QXP_GPU0_SHADER_CLK 8
|
||||
|
||||
#define IMX8QXP_24MHZ 9
|
||||
#define IMX8QXP_GPT_3M 10
|
||||
#define IMX8QXP_32KHZ 11
|
||||
|
||||
/* LSIO SS */
|
||||
#define IMX8QXP_LSIO_MEM_CLK 12
|
||||
#define IMX8QXP_LSIO_BUS_CLK 13
|
||||
#define IMX8QXP_LSIO_PWM0_DIV 14
|
||||
#define IMX8QXP_LSIO_PWM0_IPG_S_CLK 15
|
||||
#define IMX8QXP_LSIO_PWM0_IPG_SLV_CLK 16
|
||||
#define IMX8QXP_LSIO_PWM0_IPG_MSTR_CLK 17
|
||||
#define IMX8QXP_LSIO_PWM0_HF_CLK 18
|
||||
#define IMX8QXP_LSIO_PWM0_CLK 19
|
||||
#define IMX8QXP_LSIO_PWM1_DIV 20
|
||||
#define IMX8QXP_LSIO_PWM1_IPG_S_CLK 21
|
||||
#define IMX8QXP_LSIO_PWM1_IPG_SLV_CLK 22
|
||||
#define IMX8QXP_LSIO_PWM1_IPG_MSTR_CLK 23
|
||||
#define IMX8QXP_LSIO_PWM1_HF_CLK 24
|
||||
#define IMX8QXP_LSIO_PWM1_CLK 25
|
||||
#define IMX8QXP_LSIO_PWM2_DIV 26
|
||||
#define IMX8QXP_LSIO_PWM2_IPG_S_CLK 27
|
||||
#define IMX8QXP_LSIO_PWM2_IPG_SLV_CLK 28
|
||||
#define IMX8QXP_LSIO_PWM2_IPG_MSTR_CLK 29
|
||||
#define IMX8QXP_LSIO_PWM2_HF_CLK 30
|
||||
#define IMX8QXP_LSIO_PWM2_CLK 31
|
||||
#define IMX8QXP_LSIO_PWM3_DIV 32
|
||||
#define IMX8QXP_LSIO_PWM3_IPG_S_CLK 33
|
||||
#define IMX8QXP_LSIO_PWM3_IPG_SLV_CLK 34
|
||||
#define IMX8QXP_LSIO_PWM3_IPG_MSTR_CLK 35
|
||||
#define IMX8QXP_LSIO_PWM3_HF_CLK 36
|
||||
#define IMX8QXP_LSIO_PWM3_CLK 37
|
||||
#define IMX8QXP_LSIO_PWM4_DIV 38
|
||||
#define IMX8QXP_LSIO_PWM4_IPG_S_CLK 39
|
||||
#define IMX8QXP_LSIO_PWM4_IPG_SLV_CLK 40
|
||||
#define IMX8QXP_LSIO_PWM4_IPG_MSTR_CLK 42
|
||||
#define IMX8QXP_LSIO_PWM4_HF_CLK 43
|
||||
#define IMX8QXP_LSIO_PWM4_CLK 44
|
||||
#define IMX8QXP_LSIO_PWM5_DIV 45
|
||||
#define IMX8QXP_LSIO_PWM5_IPG_S_CLK 46
|
||||
#define IMX8QXP_LSIO_PWM5_IPG_SLV_CLK 47
|
||||
#define IMX8QXP_LSIO_PWM5_IPG_MSTR_CLK 48
|
||||
#define IMX8QXP_LSIO_PWM5_HF_CLK 49
|
||||
#define IMX8QXP_LSIO_PWM5_CLK 50
|
||||
#define IMX8QXP_LSIO_PWM6_DIV 51
|
||||
#define IMX8QXP_LSIO_PWM6_IPG_S_CLK 52
|
||||
#define IMX8QXP_LSIO_PWM6_IPG_SLV_CLK 53
|
||||
#define IMX8QXP_LSIO_PWM6_IPG_MSTR_CLK 54
|
||||
#define IMX8QXP_LSIO_PWM6_HF_CLK 55
|
||||
#define IMX8QXP_LSIO_PWM6_CLK 56
|
||||
#define IMX8QXP_LSIO_PWM7_DIV 57
|
||||
#define IMX8QXP_LSIO_PWM7_IPG_S_CLK 58
|
||||
#define IMX8QXP_LSIO_PWM7_IPG_SLV_CLK 59
|
||||
#define IMX8QXP_LSIO_PWM7_IPG_MSTR_CLK 60
|
||||
#define IMX8QXP_LSIO_PWM7_HF_CLK 61
|
||||
#define IMX8QXP_LSIO_PWM7_CLK 62
|
||||
#define IMX8QXP_LSIO_GPT0_DIV 63
|
||||
#define IMX8QXP_LSIO_GPT0_IPG_S_CLK 64
|
||||
#define IMX8QXP_LSIO_GPT0_IPG_SLV_CLK 65
|
||||
#define IMX8QXP_LSIO_GPT0_IPG_MSTR_CLK 66
|
||||
#define IMX8QXP_LSIO_GPT0_HF_CLK 67
|
||||
#define IMX8QXP_LSIO_GPT0_CLK 68
|
||||
#define IMX8QXP_LSIO_GPT1_DIV 69
|
||||
#define IMX8QXP_LSIO_GPT1_IPG_S_CLK 70
|
||||
#define IMX8QXP_LSIO_GPT1_IPG_SLV_CLK 71
|
||||
#define IMX8QXP_LSIO_GPT1_IPG_MSTR_CLK 72
|
||||
#define IMX8QXP_LSIO_GPT1_HF_CLK 73
|
||||
#define IMX8QXP_LSIO_GPT1_CLK 74
|
||||
#define IMX8QXP_LSIO_GPT2_DIV 75
|
||||
#define IMX8QXP_LSIO_GPT2_IPG_S_CLK 76
|
||||
#define IMX8QXP_LSIO_GPT2_IPG_SLV_CLK 77
|
||||
#define IMX8QXP_LSIO_GPT2_IPG_MSTR_CLK 78
|
||||
#define IMX8QXP_LSIO_GPT2_HF_CLK 79
|
||||
#define IMX8QXP_LSIO_GPT2_CLK 80
|
||||
#define IMX8QXP_LSIO_GPT3_DIV 81
|
||||
#define IMX8QXP_LSIO_GPT3_IPG_S_CLK 82
|
||||
#define IMX8QXP_LSIO_GPT3_IPG_SLV_CLK 83
|
||||
#define IMX8QXP_LSIO_GPT3_IPG_MSTR_CLK 84
|
||||
#define IMX8QXP_LSIO_GPT3_HF_CLK 85
|
||||
#define IMX8QXP_LSIO_GPT3_CLK 86
|
||||
#define IMX8QXP_LSIO_GPT4_DIV 87
|
||||
#define IMX8QXP_LSIO_GPT4_IPG_S_CLK 88
|
||||
#define IMX8QXP_LSIO_GPT4_IPG_SLV_CLK 89
|
||||
#define IMX8QXP_LSIO_GPT4_IPG_MSTR_CLK 90
|
||||
#define IMX8QXP_LSIO_GPT4_HF_CLK 91
|
||||
#define IMX8QXP_LSIO_GPT4_CLK 92
|
||||
#define IMX8QXP_LSIO_FSPI0_DIV 93
|
||||
#define IMX8QXP_LSIO_FSPI0_HCLK 94
|
||||
#define IMX8QXP_LSIO_FSPI0_IPG_S_CLK 95
|
||||
#define IMX8QXP_LSIO_FSPI0_IPG_CLK 96
|
||||
#define IMX8QXP_LSIO_FSPI0_CLK 97
|
||||
#define IMX8QXP_LSIO_FSPI1_DIV 98
|
||||
#define IMX8QXP_LSIO_FSPI1_HCLK 99
|
||||
#define IMX8QXP_LSIO_FSPI1_IPG_S_CLK 100
|
||||
#define IMX8QXP_LSIO_FSPI1_IPG_CLK 101
|
||||
#define IMX8QXP_LSIO_FSPI1_CLK 102
|
||||
#define IMX8QXP_LSIO_GPIO0_IPG_S_CLK 103
|
||||
#define IMX8QXP_LSIO_GPIO1_IPG_S_CLK 104
|
||||
#define IMX8QXP_LSIO_GPIO2_IPG_S_CLK 105
|
||||
#define IMX8QXP_LSIO_GPIO3_IPG_S_CLK 106
|
||||
#define IMX8QXP_LSIO_GPIO4_IPG_S_CLK 107
|
||||
#define IMX8QXP_LSIO_GPIO5_IPG_S_CLK 108
|
||||
#define IMX8QXP_LSIO_GPIO6_IPG_S_CLK 109
|
||||
#define IMX8QXP_LSIO_GPIO7_IPG_S_CLK 110
|
||||
#define IMX8QXP_LSIO_ROMCP_REG_CLK 111
|
||||
#define IMX8QXP_LSIO_ROMCP_CLK 112
|
||||
#define IMX8QXP_LSIO_96KROM_CLK 113
|
||||
#define IMX8QXP_LSIO_OCRAM_MEM_CLK 114
|
||||
#define IMX8QXP_LSIO_OCRAM_CTRL_CLK 115
|
||||
|
||||
/* ADMA SS */
|
||||
#define IMX8QXP_UART1_IPG_CLK 116
|
||||
#define IMX8QXP_UART2_IPG_CLK 117
|
||||
#define IMX8QXP_UART3_IPG_CLK 118
|
||||
#define IMX8QXP_UART1_DIV 119
|
||||
#define IMX8QXP_UART2_DIV 120
|
||||
#define IMX8QXP_UART3_DIV 121
|
||||
#define IMX8QXP_UART1_CLK 122
|
||||
#define IMX8QXP_UART2_CLK 123
|
||||
#define IMX8QXP_UART3_CLK 124
|
||||
#define IMX8QXP_SPI0_IPG_CLK 125
|
||||
#define IMX8QXP_SPI1_IPG_CLK 126
|
||||
#define IMX8QXP_SPI2_IPG_CLK 127
|
||||
#define IMX8QXP_SPI3_IPG_CLK 128
|
||||
#define IMX8QXP_SPI0_DIV 129
|
||||
#define IMX8QXP_SPI1_DIV 130
|
||||
#define IMX8QXP_SPI2_DIV 131
|
||||
#define IMX8QXP_SPI3_DIV 132
|
||||
#define IMX8QXP_SPI0_CLK 133
|
||||
#define IMX8QXP_SPI1_CLK 134
|
||||
#define IMX8QXP_SPI2_CLK 135
|
||||
#define IMX8QXP_SPI3_CLK 136
|
||||
#define IMX8QXP_CAN0_IPG_CHI_CLK 137
|
||||
#define IMX8QXP_CAN1_IPG_CHI_CLK 138
|
||||
#define IMX8QXP_CAN2_IPG_CHI_CLK 139
|
||||
#define IMX8QXP_CAN0_IPG_CLK 140
|
||||
#define IMX8QXP_CAN1_IPG_CLK 141
|
||||
#define IMX8QXP_CAN2_IPG_CLK 142
|
||||
#define IMX8QXP_CAN0_DIV 143
|
||||
#define IMX8QXP_CAN1_DIV 144
|
||||
#define IMX8QXP_CAN2_DIV 145
|
||||
#define IMX8QXP_CAN0_CLK 146
|
||||
#define IMX8QXP_CAN1_CLK 147
|
||||
#define IMX8QXP_CAN2_CLK 148
|
||||
#define IMX8QXP_I2C0_IPG_CLK 149
|
||||
#define IMX8QXP_I2C1_IPG_CLK 150
|
||||
#define IMX8QXP_I2C2_IPG_CLK 151
|
||||
#define IMX8QXP_I2C3_IPG_CLK 152
|
||||
#define IMX8QXP_I2C0_DIV 153
|
||||
#define IMX8QXP_I2C1_DIV 154
|
||||
#define IMX8QXP_I2C2_DIV 155
|
||||
#define IMX8QXP_I2C3_DIV 156
|
||||
#define IMX8QXP_I2C0_CLK 157
|
||||
#define IMX8QXP_I2C1_CLK 158
|
||||
#define IMX8QXP_I2C2_CLK 159
|
||||
#define IMX8QXP_I2C3_CLK 160
|
||||
#define IMX8QXP_FTM0_IPG_CLK 161
|
||||
#define IMX8QXP_FTM1_IPG_CLK 162
|
||||
#define IMX8QXP_FTM0_DIV 163
|
||||
#define IMX8QXP_FTM1_DIV 164
|
||||
#define IMX8QXP_FTM0_CLK 165
|
||||
#define IMX8QXP_FTM1_CLK 166
|
||||
#define IMX8QXP_ADC0_IPG_CLK 167
|
||||
#define IMX8QXP_ADC0_DIV 168
|
||||
#define IMX8QXP_ADC0_CLK 169
|
||||
#define IMX8QXP_PWM_IPG_CLK 170
|
||||
#define IMX8QXP_PWM_DIV 171
|
||||
#define IMX8QXP_PWM_CLK 172
|
||||
#define IMX8QXP_LCD_IPG_CLK 173
|
||||
#define IMX8QXP_LCD_DIV 174
|
||||
#define IMX8QXP_LCD_CLK 175
|
||||
|
||||
/* Connectivity SS */
|
||||
#define IMX8QXP_AXI_CONN_CLK_ROOT 176
|
||||
#define IMX8QXP_AHB_CONN_CLK_ROOT 177
|
||||
#define IMX8QXP_IPG_CONN_CLK_ROOT 178
|
||||
#define IMX8QXP_SDHC0_IPG_CLK 179
|
||||
#define IMX8QXP_SDHC1_IPG_CLK 180
|
||||
#define IMX8QXP_SDHC2_IPG_CLK 181
|
||||
#define IMX8QXP_SDHC0_DIV 182
|
||||
#define IMX8QXP_SDHC1_DIV 183
|
||||
#define IMX8QXP_SDHC2_DIV 184
|
||||
#define IMX8QXP_SDHC0_CLK 185
|
||||
#define IMX8QXP_SDHC1_CLK 186
|
||||
#define IMX8QXP_SDHC2_CLK 187
|
||||
#define IMX8QXP_ENET0_ROOT_DIV 188
|
||||
#define IMX8QXP_ENET0_REF_DIV 189
|
||||
#define IMX8QXP_ENET1_REF_DIV 190
|
||||
#define IMX8QXP_ENET0_BYPASS_DIV 191
|
||||
#define IMX8QXP_ENET0_RGMII_DIV 192
|
||||
#define IMX8QXP_ENET1_ROOT_DIV 193
|
||||
#define IMX8QXP_ENET1_BYPASS_DIV 194
|
||||
#define IMX8QXP_ENET1_RGMII_DIV 195
|
||||
#define IMX8QXP_ENET0_AHB_CLK 196
|
||||
#define IMX8QXP_ENET0_IPG_S_CLK 197
|
||||
#define IMX8QXP_ENET0_IPG_CLK 198
|
||||
#define IMX8QXP_ENET1_AHB_CLK 199
|
||||
#define IMX8QXP_ENET1_IPG_S_CLK 200
|
||||
#define IMX8QXP_ENET1_IPG_CLK 201
|
||||
#define IMX8QXP_ENET0_ROOT_CLK 202
|
||||
#define IMX8QXP_ENET1_ROOT_CLK 203
|
||||
#define IMX8QXP_ENET0_TX_CLK 204
|
||||
#define IMX8QXP_ENET1_TX_CLK 205
|
||||
#define IMX8QXP_ENET0_PTP_CLK 206
|
||||
#define IMX8QXP_ENET1_PTP_CLK 207
|
||||
#define IMX8QXP_ENET0_REF_25MHZ_125MHZ_SEL 208
|
||||
#define IMX8QXP_ENET1_REF_25MHZ_125MHZ_SEL 209
|
||||
#define IMX8QXP_ENET0_RMII_TX_SEL 210
|
||||
#define IMX8QXP_ENET1_RMII_TX_SEL 211
|
||||
#define IMX8QXP_ENET0_RGMII_TX_CLK 212
|
||||
#define IMX8QXP_ENET1_RGMII_TX_CLK 213
|
||||
#define IMX8QXP_ENET0_RMII_RX_CLK 214
|
||||
#define IMX8QXP_ENET1_RMII_RX_CLK 215
|
||||
#define IMX8QXP_ENET0_REF_25MHZ_125MHZ_CLK 216
|
||||
#define IMX8QXP_ENET1_REF_25MHZ_125MHZ_CLK 217
|
||||
#define IMX8QXP_ENET0_REF_50MHZ_CLK 218
|
||||
#define IMX8QXP_ENET1_REF_50MHZ_CLK 219
|
||||
#define IMX8QXP_GPMI_BCH_IO_DIV 220
|
||||
#define IMX8QXP_GPMI_BCH_DIV 221
|
||||
#define IMX8QXP_GPMI_APB_CLK 222
|
||||
#define IMX8QXP_GPMI_APB_BCH_CLK 223
|
||||
#define IMX8QXP_GPMI_BCH_IO_CLK 224
|
||||
#define IMX8QXP_GPMI_BCH_CLK 225
|
||||
#define IMX8QXP_APBHDMA_CLK 226
|
||||
#define IMX8QXP_USB3_ACLK_DIV 227
|
||||
#define IMX8QXP_USB3_BUS_DIV 228
|
||||
#define IMX8QXP_USB3_LPM_DIV 229
|
||||
#define IMX8QXP_USB3_IPG_CLK 230
|
||||
#define IMX8QXP_USB3_CORE_PCLK 231
|
||||
#define IMX8QXP_USB3_PHY_CLK 232
|
||||
#define IMX8QXP_USB3_ACLK 233
|
||||
#define IMX8QXP_USB3_BUS_CLK 234
|
||||
#define IMX8QXP_USB3_LPM_CLK 235
|
||||
#define IMX8QXP_USB2_OH_AHB_CLK 236
|
||||
#define IMX8QXP_USB2_OH_IPG_S_CLK 237
|
||||
#define IMX8QXP_USB2_OH_IPG_S_PL301_CLK 238
|
||||
#define IMX8QXP_USB2_PHY_IPG_CLK 239
|
||||
#define IMX8QXP_EDMA_CLK 240
|
||||
#define IMX8QXP_EDMA_IPG_CLK 241
|
||||
#define IMX8QXP_MLB_HCLK 242
|
||||
#define IMX8QXP_MLB_CLK 243
|
||||
#define IMX8QXP_MLB_IPG_CLK 244
|
||||
|
||||
/* Display controller SS */
|
||||
/* DC part1 */
|
||||
#define IMX8QXP_DC_AXI_EXT_CLK 245
|
||||
#define IMX8QXP_DC_AXI_INT_CLK 246
|
||||
#define IMX8QXP_DC_CFG_CLK 247
|
||||
#define IMX8QXP_DC0_DISP0_CLK 248
|
||||
#define IMX8QXP_DC0_DISP1_CLK 249
|
||||
#define IMX8QXP_DC0_PRG0_RTRAM_CLK 250
|
||||
#define IMX8QXP_DC0_PRG0_APB_CLK 251
|
||||
#define IMX8QXP_DC0_PRG1_RTRAM_CLK 252
|
||||
#define IMX8QXP_DC0_PRG1_APB_CLK 253
|
||||
#define IMX8QXP_DC0_PRG2_RTRAM_CLK 254
|
||||
#define IMX8QXP_DC0_PRG2_APB_CLK 255
|
||||
#define IMX8QXP_DC0_PRG3_RTRAM_CLK 256
|
||||
#define IMX8QXP_DC0_PRG3_APB_CLK 257
|
||||
#define IMX8QXP_DC0_PRG4_RTRAM_CLK 258
|
||||
#define IMX8QXP_DC0_PRG4_APB_CLK 259
|
||||
#define IMX8QXP_DC0_PRG5_RTRAM_CLK 260
|
||||
#define IMX8QXP_DC0_PRG5_APB_CLK 261
|
||||
#define IMX8QXP_DC0_PRG6_RTRAM_CLK 262
|
||||
#define IMX8QXP_DC0_PRG6_APB_CLK 263
|
||||
#define IMX8QXP_DC0_PRG7_RTRAM_CLK 264
|
||||
#define IMX8QXP_DC0_PRG7_APB_CLK 265
|
||||
#define IMX8QXP_DC0_PRG8_RTRAM_CLK 266
|
||||
#define IMX8QXP_DC0_PRG8_APB_CLK 267
|
||||
#define IMX8QXP_DC0_DPR0_APB_CLK 268
|
||||
#define IMX8QXP_DC0_DPR0_B_CLK 269
|
||||
#define IMX8QXP_DC0_RTRAM0_CLK 270
|
||||
#define IMX8QXP_DC0_RTRAM1_CLK 271
|
||||
|
||||
/* MIPI-LVDS part1 */
|
||||
#define IMX8QXP_MIPI_IPG_CLK 272
|
||||
#define IMX8QXP_MIPI0_I2C0_DIV 273
|
||||
#define IMX8QXP_MIPI0_I2C1_DIV 274
|
||||
#define IMX8QXP_MIPI0_I2C0_CLK 275
|
||||
#define IMX8QXP_MIPI0_I2C1_CLK 276
|
||||
#define IMX8QXP_MIPI0_I2C0_IPG_S_CLK 277
|
||||
#define IMX8QXP_MIPI0_I2C0_IPG_CLK 278
|
||||
#define IMX8QXP_MIPI0_I2C1_IPG_S_CLK 279
|
||||
#define IMX8QXP_MIPI0_I2C1_IPG_CLK 280
|
||||
#define IMX8QXP_MIPI0_PWM_IPG_S_CLK 281
|
||||
#define IMX8QXP_MIPI0_PWM_IPG_CLK 282
|
||||
#define IMX8QXP_MIPI0_PWM_32K_CLK 283
|
||||
#define IMX8QXP_MIPI0_GPIO_IPG_CLK 284
|
||||
|
||||
#define IMX8QXP_IMG_JPEG_ENC_IPG_CLK 285
|
||||
#define IMX8QXP_IMG_JPEG_ENC_CLK 286
|
||||
#define IMX8QXP_IMG_JPEG_DEC_IPG_CLK 287
|
||||
#define IMX8QXP_IMG_JPEG_DEC_CLK 288
|
||||
#define IMX8QXP_IMG_PXL_LINK_DC0_CLK 289
|
||||
#define IMX8QXP_IMG_PXL_LINK_DC1_CLK 290
|
||||
#define IMX8QXP_IMG_PXL_LINK_CSI0_CLK 291
|
||||
#define IMX8QXP_IMG_PXL_LINK_CSI1_CLK 292
|
||||
#define IMX8QXP_IMG_PXL_LINK_HDMI_IN_CLK 293
|
||||
#define IMX8QXP_IMG_PDMA_0_CLK 294
|
||||
#define IMX8QXP_IMG_PDMA_1_CLK 295
|
||||
#define IMX8QXP_IMG_PDMA_2_CLK 296
|
||||
#define IMX8QXP_IMG_PDMA_3_CLK 297
|
||||
#define IMX8QXP_IMG_PDMA_4_CLK 298
|
||||
#define IMX8QXP_IMG_PDMA_5_CLK 299
|
||||
#define IMX8QXP_IMG_PDMA_6_CLK 300
|
||||
#define IMX8QXP_IMG_PDMA_7_CLK 301
|
||||
#define IMX8QXP_IMG_AXI_CLK 302
|
||||
#define IMX8QXP_IMG_IPG_CLK 303
|
||||
#define IMX8QXP_IMG_PXL_CLK 304
|
||||
|
||||
#define IMX8QXP_CSI0_I2C0_DIV 305
|
||||
#define IMX8QXP_CSI0_PWM0_DIV 306
|
||||
#define IMX8QXP_CSI0_CORE_DIV 307
|
||||
#define IMX8QXP_CSI0_ESC_DIV 308
|
||||
#define IMX8QXP_CSI0_IPG_CLK_S 309
|
||||
#define IMX8QXP_CSI0_IPG_CLK 310
|
||||
#define IMX8QXP_CSI0_APB_CLK 311
|
||||
#define IMX8QXP_CSI0_I2C0_IPG_CLK 312
|
||||
#define IMX8QXP_CSI0_I2C0_CLK 313
|
||||
#define IMX8QXP_CSI0_PWM0_IPG_CLK 314
|
||||
#define IMX8QXP_CSI0_PWM0_CLK 315
|
||||
#define IMX8QXP_CSI0_CORE_CLK 316
|
||||
#define IMX8QXP_CSI0_ESC_CLK 317
|
||||
|
||||
#define IMX8QXP_HSIO_AXI_CLK 318
|
||||
#define IMX8QXP_HSIO_PER_CLK 319
|
||||
#define IMX8QXP_HSIO_PCIE_MSTR_AXI_CLK 320
|
||||
#define IMX8QXP_HSIO_PCIE_SLV_AXI_CLK 321
|
||||
#define IMX8QXP_HSIO_PCIE_DBI_AXI_CLK 322
|
||||
#define IMX8QXP_HSIO_PCIE_X1_PER_CLK 323
|
||||
#define IMX8QXP_HSIO_PHY_X1_PER_CLK 324
|
||||
#define IMX8QXP_HSIO_MISC_PER_CLK 325
|
||||
#define IMX8QXP_HSIO_PHY_X1_APB_CLK 326
|
||||
#define IMX8QXP_HSIO_GPIO_CLK 327
|
||||
#define IMX8QXP_HSIO_PHY_X1_PCLK 328
|
||||
|
||||
#define IMX8QXP_A35_DIV 329
|
||||
|
||||
/* ACM */
|
||||
#define IMX8QXP_EXT_AUD_MCLK0 330
|
||||
#define IMX8QXP_EXT_AUD_MCLK1 331
|
||||
#define IMX8QXP_ESAI0_RX_CLK 332
|
||||
#define IMX8QXP_ESAI0_RX_HF_CLK 333
|
||||
#define IMX8QXP_ESAI0_TX_CLK 334
|
||||
#define IMX8QXP_ESAI0_TX_HF_CLK 335
|
||||
#define IMX8QXP_SPDIF0_RX 336
|
||||
#define IMX8QXP_SAI0_RX_BCLK 337
|
||||
#define IMX8QXP_SAI0_TX_BCLK 338
|
||||
#define IMX8QXP_SAI1_RX_BCLK 339
|
||||
#define IMX8QXP_SAI1_TX_BCLK 340
|
||||
#define IMX8QXP_SAI2_RX_BCLK 341
|
||||
#define IMX8QXP_SAI3_RX_BCLK 342
|
||||
#define IMX8QXP_SAI4_RX_BCLK 343
|
||||
|
||||
#define IMX8QXP_ACM_AUD_CLK0_SEL 344
|
||||
#define IMX8QXP_ACM_AUD_CLK0_CLK 345
|
||||
#define IMX8QXP_ACM_AUD_CLK1_SEL 346
|
||||
#define IMX8QXP_ACM_AUD_CLK1_CLK 347
|
||||
#define IMX8QXP_ACM_MCLKOUT0_SEL 348
|
||||
#define IMX8QXP_ACM_MCLKOUT0_CLK 349
|
||||
#define IMX8QXP_ACM_MCLKOUT1_SEL 350
|
||||
#define IMX8QXP_ACM_MCLKOUT1_CLK 351
|
||||
#define IMX8QXP_ACM_ESAI0_MCLK_SEL 352
|
||||
#define IMX8QXP_ACM_ESAI0_MCLK_CLK 353
|
||||
#define IMX8QXP_ACM_GPT0_MUX_CLK_SEL 354
|
||||
#define IMX8QXP_ACM_GPT0_MUX_CLK_CLK 355
|
||||
#define IMX8QXP_ACM_GPT1_MUX_CLK_SEL 356
|
||||
#define IMX8QXP_ACM_GPT1_MUX_CLK_CLK 357
|
||||
#define IMX8QXP_ACM_GPT2_MUX_CLK_SEL 358
|
||||
#define IMX8QXP_ACM_GPT2_MUX_CLK_CLK 359
|
||||
#define IMX8QXP_ACM_GPT3_MUX_CLK_SEL 360
|
||||
#define IMX8QXP_ACM_GPT3_MUX_CLK_CLK 361
|
||||
#define IMX8QXP_ACM_GPT4_MUX_CLK_SEL 362
|
||||
#define IMX8QXP_ACM_GPT4_MUX_CLK_CLK 363
|
||||
#define IMX8QXP_ACM_GPT5_MUX_CLK_SEL 364
|
||||
#define IMX8QXP_ACM_GPT5_MUX_CLK_CLK 365
|
||||
#define IMX8QXP_ACM_SAI0_MCLK_SEL 366
|
||||
#define IMX8QXP_ACM_SAI0_MCLK_CLK 367
|
||||
#define IMX8QXP_ACM_SAI1_MCLK_SEL 368
|
||||
#define IMX8QXP_ACM_SAI1_MCLK_CLK 369
|
||||
#define IMX8QXP_ACM_SAI2_MCLK_SEL 370
|
||||
#define IMX8QXP_ACM_SAI2_MCLK_CLK 371
|
||||
#define IMX8QXP_ACM_SAI3_MCLK_SEL 372
|
||||
#define IMX8QXP_ACM_SAI3_MCLK_CLK 373
|
||||
#define IMX8QXP_ACM_SAI4_MCLK_SEL 374
|
||||
#define IMX8QXP_ACM_SAI4_MCLK_CLK 375
|
||||
#define IMX8QXP_ACM_SAI5_MCLK_SEL 376
|
||||
#define IMX8QXP_ACM_SAI5_MCLK_CLK 377
|
||||
#define IMX8QXP_ACM_SPDIF0_TX_CLK_SEL 378
|
||||
#define IMX8QXP_ACM_SPDIF0_TX_CLK_CLK 379
|
||||
#define IMX8QXP_ACM_MQS_TX_CLK_SEL 380
|
||||
#define IMX8QXP_ACM_MQS_TX_CLK_CLK 381
|
||||
#define IMX8QXP_ACM_ASRC0_MUX_CLK_SEL 382
|
||||
#define IMX8QXP_ACM_ASRC1_MUX_CLK_SEL 383
|
||||
#define IMX8QXP_ACM_ASRC0_MUX_CLK_CLK 384
|
||||
#define IMX8QXP_ACM_ASRC1_MUX_CLK_CLK 385
|
||||
|
||||
#define IMX8QXP_IPG_AUD_CLK_ROOT 386
|
||||
|
||||
/* Audio */
|
||||
#define IMX8QXP_AUD_PLL0_DIV 387
|
||||
#define IMX8QXP_AUD_PLL0 388
|
||||
#define IMX8QXP_AUD_PLL1_DIV 389
|
||||
#define IMX8QXP_AUD_PLL1 390
|
||||
#define IMX8QXP_AUD_AMIX_IPG 391
|
||||
#define IMX8QXP_AUD_ESAI_0_IPG 392
|
||||
#define IMX8QXP_AUD_ESAI_0_EXTAL_IPG 393
|
||||
#define IMX8QXP_AUD_SAI_0_IPG 394
|
||||
#define IMX8QXP_AUD_SAI_0_MCLK 395
|
||||
#define IMX8QXP_AUD_SAI_1_IPG 396
|
||||
#define IMX8QXP_AUD_SAI_1_MCLK 397
|
||||
#define IMX8QXP_AUD_SAI_2_IPG 398
|
||||
#define IMX8QXP_AUD_SAI_2_MCLK 399
|
||||
#define IMX8QXP_AUD_SAI_3_IPG 400
|
||||
#define IMX8QXP_AUD_SAI_3_MCLK 401
|
||||
#define IMX8QXP_AUD_SAI_4_IPG 402
|
||||
#define IMX8QXP_AUD_SAI_4_MCLK 403
|
||||
#define IMX8QXP_AUD_SAI_5_IPG 404
|
||||
#define IMX8QXP_AUD_SAI_5_MCLK 405
|
||||
#define IMX8QXP_AUD_MQS_IPG 406
|
||||
#define IMX8QXP_AUD_MQS_HMCLK 407
|
||||
#define IMX8QXP_AUD_GPT5_IPG 408
|
||||
#define IMX8QXP_AUD_GPT5_CLKIN 409
|
||||
#define IMX8QXP_AUD_GPT6_IPG 410
|
||||
#define IMX8QXP_AUD_GPT6_CLKIN 411
|
||||
#define IMX8QXP_AUD_GPT7_IPG 412
|
||||
#define IMX8QXP_AUD_GPT7_CLKIN 413
|
||||
#define IMX8QXP_AUD_GPT8_IPG 414
|
||||
#define IMX8QXP_AUD_GPT8_CLKIN 415
|
||||
#define IMX8QXP_AUD_GPT9_IPG 416
|
||||
#define IMX8QXP_AUD_GPT9_CLKIN 417
|
||||
#define IMX8QXP_AUD_GPT10_IPG 418
|
||||
#define IMX8QXP_AUD_GPT10_CLKIN 419
|
||||
#define IMX8QXP_AUD_ACM_AUD_PLL_CLK0_DIV 420
|
||||
#define IMX8QXP_AUD_ACM_AUD_PLL_CLK0_CLK 421
|
||||
#define IMX8QXP_AUD_ACM_AUD_PLL_CLK1_DIV 422
|
||||
#define IMX8QXP_AUD_ACM_AUD_PLL_CLK1_CLK 423
|
||||
#define IMX8QXP_AUD_ACM_AUD_REC_CLK0_DIV 424
|
||||
#define IMX8QXP_AUD_ACM_AUD_REC_CLK0_CLK 425
|
||||
#define IMX8QXP_AUD_ACM_AUD_REC_CLK1_DIV 426
|
||||
#define IMX8QXP_AUD_ACM_AUD_REC_CLK1_CLK 427
|
||||
#define IMX8QXP_AUD_MCLKOUT0 428
|
||||
#define IMX8QXP_AUD_MCLKOUT1 429
|
||||
#define IMX8QXP_AUD_SPDIF_0_TX_CLK 430
|
||||
#define IMX8QXP_AUD_SPDIF_0_GCLKW 431
|
||||
#define IMX8QXP_AUD_SPDIF_0_IPG 432
|
||||
#define IMX8QXP_AUD_ASRC_0_IPG 433
|
||||
#define IMX8QXP_AUD_ASRC_1_IPG 434
|
||||
#define IMX8QXP_AUD_DSP_ADB_ACLK 435
|
||||
#define IMX8QXP_AUD_DSP_IPG 436
|
||||
#define IMX8QXP_AUD_DSP_CORE_CLK 437
|
||||
#define IMX8QXP_AUD_OCRAM_IPG 438
|
||||
|
||||
/* DC part2 */
|
||||
#define IMX8QXP_DC0_DISP0_DIV 439
|
||||
#define IMX8QXP_DC0_DISP1_DIV 440
|
||||
#define IMX8QXP_DC0_BYPASS_0_DIV 441
|
||||
#define IMX8QXP_DC0_BYPASS_1_DIV 442
|
||||
#define IMX8QXP_DC0_PLL0_DIV 443
|
||||
#define IMX8QXP_DC0_PLL1_DIV 444
|
||||
#define IMX8QXP_DC0_PLL0_CLK 445
|
||||
#define IMX8QXP_DC0_PLL1_CLK 446
|
||||
|
||||
/* MIPI-LVDS part2 */
|
||||
#define IMX8QXP_MIPI0_BYPASS_CLK 447
|
||||
#define IMX8QXP_MIPI0_PIXEL_DIV 448
|
||||
#define IMX8QXP_MIPI0_PIXEL_CLK 449
|
||||
#define IMX8QXP_MIPI0_LVDS_PIXEL_DIV 450
|
||||
#define IMX8QXP_MIPI0_LVDS_PIXEL_CLK 451
|
||||
#define IMX8QXP_MIPI0_LVDS_BYPASS_CLK 452
|
||||
#define IMX8QXP_MIPI0_LVDS_PHY_DIV 453
|
||||
#define IMX8QXP_MIPI0_LVDS_PHY_CLK 454
|
||||
#define IMX8QXP_MIPI0_DSI_TX_ESC_DIV 455
|
||||
#define IMX8QXP_MIPI0_DSI_RX_ESC_DIV 456
|
||||
#define IMX8QXP_MIPI0_DSI_TX_ESC_CLK 457
|
||||
#define IMX8QXP_MIPI0_DSI_RX_ESC_CLK 458
|
||||
#define IMX8QXP_MIPI0_LIS_IPG_CLK 459
|
||||
#define IMX8QXP_MIPI1_I2C0_DIV 460
|
||||
#define IMX8QXP_MIPI1_I2C1_DIV 461
|
||||
#define IMX8QXP_MIPI1_I2C0_CLK 462
|
||||
#define IMX8QXP_MIPI1_I2C1_CLK 463
|
||||
#define IMX8QXP_MIPI1_I2C0_IPG_S_CLK 464
|
||||
#define IMX8QXP_MIPI1_I2C0_IPG_CLK 465
|
||||
#define IMX8QXP_MIPI1_I2C1_IPG_S_CLK 466
|
||||
#define IMX8QXP_MIPI1_I2C1_IPG_CLK 467
|
||||
#define IMX8QXP_MIPI1_PWM_IPG_S_CLK 468
|
||||
#define IMX8QXP_MIPI1_PWM_IPG_CLK 469
|
||||
#define IMX8QXP_MIPI1_PWM_32K_CLK 470
|
||||
#define IMX8QXP_MIPI1_GPIO_IPG_CLK 471
|
||||
#define IMX8QXP_MIPI1_BYPASS_CLK 472
|
||||
#define IMX8QXP_MIPI1_PIXEL_DIV 473
|
||||
#define IMX8QXP_MIPI1_PIXEL_CLK 474
|
||||
#define IMX8QXP_MIPI1_LVDS_PIXEL_DIV 475
|
||||
#define IMX8QXP_MIPI1_LVDS_PIXEL_CLK 476
|
||||
#define IMX8QXP_MIPI1_LVDS_BYPASS_CLK 477
|
||||
#define IMX8QXP_MIPI1_LVDS_PHY_DIV 478
|
||||
#define IMX8QXP_MIPI1_LVDS_PHY_CLK 479
|
||||
#define IMX8QXP_MIPI1_DSI_TX_ESC_DIV 480
|
||||
#define IMX8QXP_MIPI1_DSI_RX_ESC_DIV 481
|
||||
#define IMX8QXP_MIPI1_DSI_TX_ESC_CLK 482
|
||||
#define IMX8QXP_MIPI1_DSI_RX_ESC_CLK 483
|
||||
|
||||
#define IMX8QXP_MIPI1_LIS_IPG_CLK 484
|
||||
|
||||
/* CM40 */
|
||||
#define IMX8QXP_CM40_IPG_CLK 485
|
||||
#define IMX8QXP_CM40_I2C_DIV 486
|
||||
#define IMX8QXP_CM40_I2C_CLK 487
|
||||
#define IMX8QXP_CM40_I2C_IPG_CLK 488
|
||||
|
||||
/* VPU clocks. */
|
||||
#define IMX8QXP_VPU_ENC_CLK 489
|
||||
#define IMX8QXP_VPU_DEC_CLK 490
|
||||
|
||||
/* MIPI-LVDS part3 */
|
||||
#define IMX8QXP_MIPI0_DSI_PLL_CLK 491
|
||||
#define IMX8QXP_MIPI0_DSI_PLL_DIV2_CLK 492
|
||||
#define IMX8QXP_MIPI0_LVDS_PIXEL_SEL 493
|
||||
#define IMX8QXP_MIPI0_LVDS_PHY_SEL 494
|
||||
#define IMX8QXP_MIPI0_DSI_TX_ESC_SEL 495
|
||||
#define IMX8QXP_MIPI0_DSI_RX_ESC_SEL 496
|
||||
#define IMX8QXP_MIPI0_DSI_PHY_SEL 498
|
||||
#define IMX8QXP_MIPI0_DSI_PHY_DIV 499
|
||||
#define IMX8QXP_MIPI0_DSI_PHY_CLK 500
|
||||
#define IMX8QXP_MIPI1_DSI_PLL_CLK 501
|
||||
#define IMX8QXP_MIPI1_DSI_PLL_DIV2_CLK 502
|
||||
#define IMX8QXP_MIPI1_LVDS_PIXEL_SEL 503
|
||||
#define IMX8QXP_MIPI1_LVDS_PHY_SEL 504
|
||||
#define IMX8QXP_MIPI1_DSI_TX_ESC_SEL 505
|
||||
#define IMX8QXP_MIPI1_DSI_RX_ESC_SEL 506
|
||||
#define IMX8QXP_MIPI1_DSI_PHY_SEL 507
|
||||
#define IMX8QXP_MIPI1_DSI_PHY_DIV 508
|
||||
#define IMX8QXP_MIPI1_DSI_PHY_CLK 509
|
||||
|
||||
/* DC part3 */
|
||||
#define IMX8QXP_DC0_DPR1_APB_CLK 510
|
||||
#define IMX8QXP_DC0_DPR1_B_CLK 511
|
||||
|
||||
#define IMX8QXP_CONN_PLL0_CLK 512
|
||||
#define IMX8QXP_CONN_PLL1_CLK 513
|
||||
#define IMX8QXP_SDHC0_SEL 514
|
||||
#define IMX8QXP_SDHC1_SEL 515
|
||||
#define IMX8QXP_SDHC2_SEL 516
|
||||
|
||||
/* PARALLER CSI */
|
||||
#define IMX8QXP_PARALLEL_CSI_CLK_DPLL 517
|
||||
#define IMX8QXP_PARALLEL_CSI_CLK_SEL 518
|
||||
#define IMX8QXP_PARALLEL_CSI_PER_CLK_DIV 519
|
||||
#define IMX8QXP_PARALLEL_CSI_PIXEL_CLK 520
|
||||
#define IMX8QXP_PARALLEL_CSI_IPG_CLK 521
|
||||
#define IMX8QXP_PARALLEL_CSI_MCLK_DIV 522
|
||||
#define IMX8QXP_PARALLEL_CSI_MISC0_CLK 523
|
||||
|
||||
#define IMX8QXP_MIPI0_PWM_DIV 524
|
||||
#define IMX8QXP_MIPI1_PWM_DIV 525
|
||||
#define IMX8QXP_MIPI0_PWM_CLK 526
|
||||
#define IMX8QXP_MIPI1_PWM_CLK 527
|
||||
|
||||
#define IMX8QXP_LSIO_MU5A_IPG_S_CLK 528
|
||||
#define IMX8QXP_LSIO_MU5A_IPG_CLK 529
|
||||
|
||||
#define IMX8QXP_CLK_END 530
|
||||
#endif /* __DT_BINDINGS_CLOCK_IMX8QXP_H */
|
||||
757
include/dt-bindings/pinctrl/pads-imx8qxp.h
Normal file
757
include/dt-bindings/pinctrl/pads-imx8qxp.h
Normal file
@@ -0,0 +1,757 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2018 NXP
|
||||
*/
|
||||
|
||||
#ifndef _SC_PADS_H
|
||||
#define _SC_PADS_H
|
||||
|
||||
#define SC_P_PCIE_CTRL0_PERST_B 0 /* HSIO.PCIE0.PERST_B, LSIO.GPIO4.IO00 */
|
||||
#define SC_P_PCIE_CTRL0_CLKREQ_B 1 /* HSIO.PCIE0.CLKREQ_B, LSIO.GPIO4.IO01 */
|
||||
#define SC_P_PCIE_CTRL0_WAKE_B 2 /* HSIO.PCIE0.WAKE_B, LSIO.GPIO4.IO02 */
|
||||
#define SC_P_COMP_CTL_GPIO_1V8_3V3_PCIESEP 3 /* */
|
||||
#define SC_P_USB_SS3_TC0 4 /* ADMA.I2C1.SCL, CONN.USB_OTG1.PWR, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO03 */
|
||||
#define SC_P_USB_SS3_TC1 5 /* ADMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO04 */
|
||||
#define SC_P_USB_SS3_TC2 6 /* ADMA.I2C1.SDA, CONN.USB_OTG1.OC, CONN.USB_OTG2.OC, LSIO.GPIO4.IO05 */
|
||||
#define SC_P_USB_SS3_TC3 7 /* ADMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO06 */
|
||||
#define SC_P_COMP_CTL_GPIO_3V3_USB3IO 8 /* */
|
||||
#define SC_P_EMMC0_CLK 9 /* CONN.EMMC0.CLK, CONN.NAND.READY_B, LSIO.GPIO4.IO07 */
|
||||
#define SC_P_EMMC0_CMD 10 /* CONN.EMMC0.CMD, CONN.NAND.DQS, LSIO.GPIO4.IO08 */
|
||||
#define SC_P_EMMC0_DATA0 11 /* CONN.EMMC0.DATA0, CONN.NAND.DATA00, LSIO.GPIO4.IO09 */
|
||||
#define SC_P_EMMC0_DATA1 12 /* CONN.EMMC0.DATA1, CONN.NAND.DATA01, LSIO.GPIO4.IO10 */
|
||||
#define SC_P_EMMC0_DATA2 13 /* CONN.EMMC0.DATA2, CONN.NAND.DATA02, LSIO.GPIO4.IO11 */
|
||||
#define SC_P_EMMC0_DATA3 14 /* CONN.EMMC0.DATA3, CONN.NAND.DATA03, LSIO.GPIO4.IO12 */
|
||||
#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX0 15 /* */
|
||||
#define SC_P_EMMC0_DATA4 16 /* CONN.EMMC0.DATA4, CONN.NAND.DATA04, CONN.EMMC0.WP, LSIO.GPIO4.IO13 */
|
||||
#define SC_P_EMMC0_DATA5 17 /* CONN.EMMC0.DATA5, CONN.NAND.DATA05, CONN.EMMC0.VSELECT, LSIO.GPIO4.IO14 */
|
||||
#define SC_P_EMMC0_DATA6 18 /* CONN.EMMC0.DATA6, CONN.NAND.DATA06, CONN.MLB.CLK, LSIO.GPIO4.IO15 */
|
||||
#define SC_P_EMMC0_DATA7 19 /* CONN.EMMC0.DATA7, CONN.NAND.DATA07, CONN.MLB.SIG, LSIO.GPIO4.IO16 */
|
||||
#define SC_P_EMMC0_STROBE 20 /* CONN.EMMC0.STROBE, CONN.NAND.CLE, CONN.MLB.DATA, LSIO.GPIO4.IO17 */
|
||||
#define SC_P_EMMC0_RESET_B 21 /* CONN.EMMC0.RESET_B, CONN.NAND.WP_B, LSIO.GPIO4.IO18 */
|
||||
#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX1 22 /* */
|
||||
#define SC_P_USDHC1_RESET_B 23 /* CONN.USDHC1.RESET_B, CONN.NAND.RE_N, ADMA.SPI2.SCK, LSIO.GPIO4.IO19 */
|
||||
#define SC_P_USDHC1_VSELECT 24 /* CONN.USDHC1.VSELECT, CONN.NAND.RE_P, ADMA.SPI2.SDO, CONN.NAND.RE_B, LSIO.GPIO4.IO20 */
|
||||
#define SC_P_CTL_NAND_RE_P_N 25 /* */
|
||||
#define SC_P_USDHC1_WP 26 /* CONN.USDHC1.WP, CONN.NAND.DQS_N, ADMA.SPI2.SDI, LSIO.GPIO4.IO21 */
|
||||
#define SC_P_USDHC1_CD_B 27 /* CONN.USDHC1.CD_B, CONN.NAND.DQS_P, ADMA.SPI2.CS0, CONN.NAND.DQS, LSIO.GPIO4.IO22 */
|
||||
#define SC_P_CTL_NAND_DQS_P_N 28 /* */
|
||||
#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSELSEP 29 /* */
|
||||
#define SC_P_USDHC1_CLK 30 /* CONN.USDHC1.CLK, ADMA.UART3.RX, LSIO.GPIO4.IO23 */
|
||||
#define SC_P_USDHC1_CMD 31 /* CONN.USDHC1.CMD, CONN.NAND.CE0_B, ADMA.MQS.R, LSIO.GPIO4.IO24 */
|
||||
#define SC_P_USDHC1_DATA0 32 /* CONN.USDHC1.DATA0, CONN.NAND.CE1_B, ADMA.MQS.L, LSIO.GPIO4.IO25 */
|
||||
#define SC_P_USDHC1_DATA1 33 /* CONN.USDHC1.DATA1, CONN.NAND.RE_B, ADMA.UART3.TX, LSIO.GPIO4.IO26 */
|
||||
#define SC_P_USDHC1_DATA2 34 /* CONN.USDHC1.DATA2, CONN.NAND.WE_B, ADMA.UART3.CTS_B, LSIO.GPIO4.IO27 */
|
||||
#define SC_P_USDHC1_DATA3 35 /* CONN.USDHC1.DATA3, CONN.NAND.ALE, ADMA.UART3.RTS_B, LSIO.GPIO4.IO28 */
|
||||
#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL3 36 /* */
|
||||
#define SC_P_ENET0_RGMII_TXC 37 /* CONN.ENET0.RGMII_TXC, CONN.ENET0.RCLK50M_OUT, CONN.ENET0.RCLK50M_IN, CONN.NAND.CE1_B, LSIO.GPIO4.IO29 */
|
||||
#define SC_P_ENET0_RGMII_TX_CTL 38 /* CONN.ENET0.RGMII_TX_CTL, CONN.USDHC1.RESET_B, LSIO.GPIO4.IO30 */
|
||||
#define SC_P_ENET0_RGMII_TXD0 39 /* CONN.ENET0.RGMII_TXD0, CONN.USDHC1.VSELECT, LSIO.GPIO4.IO31 */
|
||||
#define SC_P_ENET0_RGMII_TXD1 40 /* CONN.ENET0.RGMII_TXD1, CONN.USDHC1.WP, LSIO.GPIO5.IO00 */
|
||||
#define SC_P_ENET0_RGMII_TXD2 41 /* CONN.ENET0.RGMII_TXD2, CONN.MLB.CLK, CONN.NAND.CE0_B, CONN.USDHC1.CD_B, LSIO.GPIO5.IO01 */
|
||||
#define SC_P_ENET0_RGMII_TXD3 42 /* CONN.ENET0.RGMII_TXD3, CONN.MLB.SIG, CONN.NAND.RE_B, LSIO.GPIO5.IO02 */
|
||||
#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0 43 /* */
|
||||
#define SC_P_ENET0_RGMII_RXC 44 /* CONN.ENET0.RGMII_RXC, CONN.MLB.DATA, CONN.NAND.WE_B, CONN.USDHC1.CLK, LSIO.GPIO5.IO03 */
|
||||
#define SC_P_ENET0_RGMII_RX_CTL 45 /* CONN.ENET0.RGMII_RX_CTL, CONN.USDHC1.CMD, LSIO.GPIO5.IO04 */
|
||||
#define SC_P_ENET0_RGMII_RXD0 46 /* CONN.ENET0.RGMII_RXD0, CONN.USDHC1.DATA0, LSIO.GPIO5.IO05 */
|
||||
#define SC_P_ENET0_RGMII_RXD1 47 /* CONN.ENET0.RGMII_RXD1, CONN.USDHC1.DATA1, LSIO.GPIO5.IO06 */
|
||||
#define SC_P_ENET0_RGMII_RXD2 48 /* CONN.ENET0.RGMII_RXD2, CONN.ENET0.RMII_RX_ER, CONN.USDHC1.DATA2, LSIO.GPIO5.IO07 */
|
||||
#define SC_P_ENET0_RGMII_RXD3 49 /* CONN.ENET0.RGMII_RXD3, CONN.NAND.ALE, CONN.USDHC1.DATA3, LSIO.GPIO5.IO08 */
|
||||
#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1 50 /* */
|
||||
#define SC_P_ENET0_REFCLK_125M_25M 51 /* CONN.ENET0.REFCLK_125M_25M, CONN.ENET0.PPS, CONN.ENET1.PPS, LSIO.GPIO5.IO09 */
|
||||
#define SC_P_ENET0_MDIO 52 /* CONN.ENET0.MDIO, ADMA.I2C3.SDA, CONN.ENET1.MDIO, LSIO.GPIO5.IO10 */
|
||||
#define SC_P_ENET0_MDC 53 /* CONN.ENET0.MDC, ADMA.I2C3.SCL, CONN.ENET1.MDC, LSIO.GPIO5.IO11 */
|
||||
#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOCT 54 /* */
|
||||
#define SC_P_ESAI0_FSR 55 /* ADMA.ESAI0.FSR, CONN.ENET1.RCLK50M_OUT, ADMA.LCDIF.D00, CONN.ENET1.RGMII_TXC, CONN.ENET1.RCLK50M_IN */
|
||||
#define SC_P_ESAI0_FST 56 /* ADMA.ESAI0.FST, CONN.MLB.CLK, ADMA.LCDIF.D01, CONN.ENET1.RGMII_TXD2, LSIO.GPIO0.IO01 */
|
||||
#define SC_P_ESAI0_SCKR 57 /* ADMA.ESAI0.SCKR, ADMA.LCDIF.D02, CONN.ENET1.RGMII_TX_CTL, LSIO.GPIO0.IO02 */
|
||||
#define SC_P_ESAI0_SCKT 58 /* ADMA.ESAI0.SCKT, CONN.MLB.SIG, ADMA.LCDIF.D03, CONN.ENET1.RGMII_TXD3, LSIO.GPIO0.IO03 */
|
||||
#define SC_P_ESAI0_TX0 59 /* ADMA.ESAI0.TX0, CONN.MLB.DATA, ADMA.LCDIF.D04, CONN.ENET1.RGMII_RXC, LSIO.GPIO0.IO04 */
|
||||
#define SC_P_ESAI0_TX1 60 /* ADMA.ESAI0.TX1, ADMA.LCDIF.D05, CONN.ENET1.RGMII_RXD3, LSIO.GPIO0.IO05 */
|
||||
#define SC_P_ESAI0_TX2_RX3 61 /* ADMA.ESAI0.TX2_RX3, CONN.ENET1.RMII_RX_ER, ADMA.LCDIF.D06, CONN.ENET1.RGMII_RXD2, LSIO.GPIO0.IO06 */
|
||||
#define SC_P_ESAI0_TX3_RX2 62 /* ADMA.ESAI0.TX3_RX2, ADMA.LCDIF.D07, CONN.ENET1.RGMII_RXD1, LSIO.GPIO0.IO07 */
|
||||
#define SC_P_ESAI0_TX4_RX1 63 /* ADMA.ESAI0.TX4_RX1, ADMA.LCDIF.D08, CONN.ENET1.RGMII_TXD0, LSIO.GPIO0.IO08 */
|
||||
#define SC_P_ESAI0_TX5_RX0 64 /* ADMA.ESAI0.TX5_RX0, ADMA.LCDIF.D09, CONN.ENET1.RGMII_TXD1, LSIO.GPIO0.IO09 */
|
||||
#define SC_P_SPDIF0_RX 65 /* ADMA.SPDIF0.RX, ADMA.MQS.R, ADMA.LCDIF.D10, CONN.ENET1.RGMII_RXD0, LSIO.GPIO0.IO10 */
|
||||
#define SC_P_SPDIF0_TX 66 /* ADMA.SPDIF0.TX, ADMA.MQS.L, ADMA.LCDIF.D11, CONN.ENET1.RGMII_RX_CTL, LSIO.GPIO0.IO11 */
|
||||
#define SC_P_SPDIF0_EXT_CLK 67 /* ADMA.SPDIF0.EXT_CLK, ADMA.LCDIF.D12, CONN.ENET1.REFCLK_125M_25M, LSIO.GPIO0.IO12 */
|
||||
#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB 68 /* */
|
||||
#define SC_P_SPI3_SCK 69 /* ADMA.SPI3.SCK, ADMA.LCDIF.D13, LSIO.GPIO0.IO13 */
|
||||
#define SC_P_SPI3_SDO 70 /* ADMA.SPI3.SDO, ADMA.LCDIF.D14, LSIO.GPIO0.IO14 */
|
||||
#define SC_P_SPI3_SDI 71 /* ADMA.SPI3.SDI, ADMA.LCDIF.D15, LSIO.GPIO0.IO15 */
|
||||
#define SC_P_SPI3_CS0 72 /* ADMA.SPI3.CS0, ADMA.ACM.MCLK_OUT1, ADMA.LCDIF.HSYNC, LSIO.GPIO0.IO16 */
|
||||
#define SC_P_SPI3_CS1 73 /* ADMA.SPI3.CS1, ADMA.I2C3.SCL, ADMA.LCDIF.RESET, ADMA.SPI2.CS0, ADMA.LCDIF.D16 */
|
||||
#define SC_P_MCLK_IN1 74 /* ADMA.ACM.MCLK_IN1, ADMA.I2C3.SDA, ADMA.LCDIF.EN, ADMA.SPI2.SCK, ADMA.LCDIF.D17 */
|
||||
#define SC_P_MCLK_IN0 75 /* ADMA.ACM.MCLK_IN0, ADMA.ESAI0.RX_HF_CLK, ADMA.LCDIF.VSYNC, ADMA.SPI2.SDI, LSIO.GPIO0.IO19 */
|
||||
#define SC_P_MCLK_OUT0 76 /* ADMA.ACM.MCLK_OUT0, ADMA.ESAI0.TX_HF_CLK, ADMA.LCDIF.CLK, ADMA.SPI2.SDO, LSIO.GPIO0.IO20 */
|
||||
#define SC_P_UART1_TX 77 /* ADMA.UART1.TX, LSIO.PWM0.OUT, LSIO.GPT0.CAPTURE, LSIO.GPIO0.IO21 */
|
||||
#define SC_P_UART1_RX 78 /* ADMA.UART1.RX, LSIO.PWM1.OUT, LSIO.GPT0.COMPARE, LSIO.GPT1.CLK, LSIO.GPIO0.IO22 */
|
||||
#define SC_P_UART1_RTS_B 79 /* ADMA.UART1.RTS_B, LSIO.PWM2.OUT, ADMA.LCDIF.D16, LSIO.GPT1.CAPTURE, LSIO.GPT0.CLK */
|
||||
#define SC_P_UART1_CTS_B 80 /* ADMA.UART1.CTS_B, LSIO.PWM3.OUT, ADMA.LCDIF.D17, LSIO.GPT1.COMPARE, LSIO.GPIO0.IO24 */
|
||||
#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHK 81 /* */
|
||||
#define SC_P_SAI0_TXD 82 /* ADMA.SAI0.TXD, ADMA.SAI1.RXC, ADMA.SPI1.SDO, ADMA.LCDIF.D18, LSIO.GPIO0.IO25 */
|
||||
#define SC_P_SAI0_TXC 83 /* ADMA.SAI0.TXC, ADMA.SAI1.TXD, ADMA.SPI1.SDI, ADMA.LCDIF.D19, LSIO.GPIO0.IO26 */
|
||||
#define SC_P_SAI0_RXD 84 /* ADMA.SAI0.RXD, ADMA.SAI1.RXFS, ADMA.SPI1.CS0, ADMA.LCDIF.D20, LSIO.GPIO0.IO27 */
|
||||
#define SC_P_SAI0_TXFS 85 /* ADMA.SAI0.TXFS, ADMA.SPI2.CS1, ADMA.SPI1.SCK, LSIO.GPIO0.IO28 */
|
||||
#define SC_P_SAI1_RXD 86 /* ADMA.SAI1.RXD, ADMA.SAI0.RXFS, ADMA.SPI1.CS1, ADMA.LCDIF.D21, LSIO.GPIO0.IO29 */
|
||||
#define SC_P_SAI1_RXC 87 /* ADMA.SAI1.RXC, ADMA.SAI1.TXC, ADMA.LCDIF.D22, LSIO.GPIO0.IO30 */
|
||||
#define SC_P_SAI1_RXFS 88 /* ADMA.SAI1.RXFS, ADMA.SAI1.TXFS, ADMA.LCDIF.D23, LSIO.GPIO0.IO31 */
|
||||
#define SC_P_SPI2_CS0 89 /* ADMA.SPI2.CS0, LSIO.GPIO1.IO00 */
|
||||
#define SC_P_SPI2_SDO 90 /* ADMA.SPI2.SDO, LSIO.GPIO1.IO01 */
|
||||
#define SC_P_SPI2_SDI 91 /* ADMA.SPI2.SDI, LSIO.GPIO1.IO02 */
|
||||
#define SC_P_SPI2_SCK 92 /* ADMA.SPI2.SCK, LSIO.GPIO1.IO03 */
|
||||
#define SC_P_SPI0_SCK 93 /* ADMA.SPI0.SCK, ADMA.SAI0.TXC, M40.I2C0.SCL, M40.GPIO0.IO00, LSIO.GPIO1.IO04 */
|
||||
#define SC_P_SPI0_SDI 94 /* ADMA.SPI0.SDI, ADMA.SAI0.TXD, M40.TPM0.CH0, M40.GPIO0.IO02, LSIO.GPIO1.IO05 */
|
||||
#define SC_P_SPI0_SDO 95 /* ADMA.SPI0.SDO, ADMA.SAI0.TXFS, M40.I2C0.SDA, M40.GPIO0.IO01, LSIO.GPIO1.IO06 */
|
||||
#define SC_P_SPI0_CS1 96 /* ADMA.SPI0.CS1, ADMA.SAI0.RXC, ADMA.SAI1.TXD, ADMA.LCD_PWM0.OUT, LSIO.GPIO1.IO07 */
|
||||
#define SC_P_SPI0_CS0 97 /* ADMA.SPI0.CS0, ADMA.SAI0.RXD, M40.TPM0.CH1, M40.GPIO0.IO03, LSIO.GPIO1.IO08 */
|
||||
#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHT 98 /* */
|
||||
#define SC_P_ADC_IN1 99 /* ADMA.ADC.IN1, M40.I2C0.SDA, M40.GPIO0.IO01, LSIO.GPIO1.IO09 */
|
||||
#define SC_P_ADC_IN0 100 /* ADMA.ADC.IN0, M40.I2C0.SCL, M40.GPIO0.IO00, LSIO.GPIO1.IO10 */
|
||||
#define SC_P_ADC_IN3 101 /* ADMA.ADC.IN3, M40.UART0.TX, M40.GPIO0.IO03, ADMA.ACM.MCLK_OUT0, LSIO.GPIO1.IO11 */
|
||||
#define SC_P_ADC_IN2 102 /* ADMA.ADC.IN2, M40.UART0.RX, M40.GPIO0.IO02, ADMA.ACM.MCLK_IN0, LSIO.GPIO1.IO12 */
|
||||
#define SC_P_ADC_IN5 103 /* ADMA.ADC.IN5, M40.TPM0.CH1, M40.GPIO0.IO05, LSIO.GPIO1.IO13 */
|
||||
#define SC_P_ADC_IN4 104 /* ADMA.ADC.IN4, M40.TPM0.CH0, M40.GPIO0.IO04, LSIO.GPIO1.IO14 */
|
||||
#define SC_P_FLEXCAN0_RX 105 /* ADMA.FLEXCAN0.RX, ADMA.SAI2.RXC, ADMA.UART0.RTS_B, ADMA.SAI1.TXC, LSIO.GPIO1.IO15 */
|
||||
#define SC_P_FLEXCAN0_TX 106 /* ADMA.FLEXCAN0.TX, ADMA.SAI2.RXD, ADMA.UART0.CTS_B, ADMA.SAI1.TXFS, LSIO.GPIO1.IO16 */
|
||||
#define SC_P_FLEXCAN1_RX 107 /* ADMA.FLEXCAN1.RX, ADMA.SAI2.RXFS, ADMA.FTM.CH2, ADMA.SAI1.TXD, LSIO.GPIO1.IO17 */
|
||||
#define SC_P_FLEXCAN1_TX 108 /* ADMA.FLEXCAN1.TX, ADMA.SAI3.RXC, ADMA.DMA0.REQ_IN0, ADMA.SAI1.RXD, LSIO.GPIO1.IO18 */
|
||||
#define SC_P_FLEXCAN2_RX 109 /* ADMA.FLEXCAN2.RX, ADMA.SAI3.RXD, ADMA.UART3.RX, ADMA.SAI1.RXFS, LSIO.GPIO1.IO19 */
|
||||
#define SC_P_FLEXCAN2_TX 110 /* ADMA.FLEXCAN2.TX, ADMA.SAI3.RXFS, ADMA.UART3.TX, ADMA.SAI1.RXC, LSIO.GPIO1.IO20 */
|
||||
#define SC_P_UART0_RX 111 /* ADMA.UART0.RX, ADMA.MQS.R, ADMA.FLEXCAN0.RX, SCU.UART0.RX, LSIO.GPIO1.IO21 */
|
||||
#define SC_P_UART0_TX 112 /* ADMA.UART0.TX, ADMA.MQS.L, ADMA.FLEXCAN0.TX, SCU.UART0.TX, LSIO.GPIO1.IO22 */
|
||||
#define SC_P_UART2_TX 113 /* ADMA.UART2.TX, ADMA.FTM.CH1, ADMA.FLEXCAN1.TX, LSIO.GPIO1.IO23 */
|
||||
#define SC_P_UART2_RX 114 /* ADMA.UART2.RX, ADMA.FTM.CH0, ADMA.FLEXCAN1.RX, LSIO.GPIO1.IO24 */
|
||||
#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLH 115 /* */
|
||||
#define SC_P_MIPI_DSI0_I2C0_SCL 116 /* MIPI_DSI0.I2C0.SCL, MIPI_DSI1.GPIO0.IO02, LSIO.GPIO1.IO25 */
|
||||
#define SC_P_MIPI_DSI0_I2C0_SDA 117 /* MIPI_DSI0.I2C0.SDA, MIPI_DSI1.GPIO0.IO03, LSIO.GPIO1.IO26 */
|
||||
#define SC_P_MIPI_DSI0_GPIO0_00 118 /* MIPI_DSI0.GPIO0.IO00, ADMA.I2C1.SCL, MIPI_DSI0.PWM0.OUT, LSIO.GPIO1.IO27 */
|
||||
#define SC_P_MIPI_DSI0_GPIO0_01 119 /* MIPI_DSI0.GPIO0.IO01, ADMA.I2C1.SDA, LSIO.GPIO1.IO28 */
|
||||
#define SC_P_MIPI_DSI1_I2C0_SCL 120 /* MIPI_DSI1.I2C0.SCL, MIPI_DSI0.GPIO0.IO02, LSIO.GPIO1.IO29 */
|
||||
#define SC_P_MIPI_DSI1_I2C0_SDA 121 /* MIPI_DSI1.I2C0.SDA, MIPI_DSI0.GPIO0.IO03, LSIO.GPIO1.IO30 */
|
||||
#define SC_P_MIPI_DSI1_GPIO0_00 122 /* MIPI_DSI1.GPIO0.IO00, ADMA.I2C2.SCL, MIPI_DSI1.PWM0.OUT, LSIO.GPIO1.IO31 */
|
||||
#define SC_P_MIPI_DSI1_GPIO0_01 123 /* MIPI_DSI1.GPIO0.IO01, ADMA.I2C2.SDA, LSIO.GPIO2.IO00 */
|
||||
#define SC_P_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO 124 /* */
|
||||
#define SC_P_JTAG_TRST_B 125 /* SCU.JTAG.TRST_B, SCU.WDOG0.WDOG_OUT */
|
||||
#define SC_P_PMIC_I2C_SCL 126 /* SCU.PMIC_I2C.SCL, SCU.GPIO0.IOXX_PMIC_A35_ON, LSIO.GPIO2.IO01 */
|
||||
#define SC_P_PMIC_I2C_SDA 127 /* SCU.PMIC_I2C.SDA, SCU.GPIO0.IOXX_PMIC_GPU_ON, LSIO.GPIO2.IO02 */
|
||||
#define SC_P_PMIC_INT_B 128 /* SCU.DSC.PMIC_INT_B */
|
||||
#define SC_P_SCU_GPIO0_00 129 /* SCU.GPIO0.IO00, SCU.UART0.RX, M40.UART0.RX, ADMA.UART3.RX, LSIO.GPIO2.IO03 */
|
||||
#define SC_P_SCU_GPIO0_01 130 /* SCU.GPIO0.IO01, SCU.UART0.TX, M40.UART0.TX, ADMA.UART3.TX, SCU.WDOG0.WDOG_OUT */
|
||||
#define SC_P_SCU_PMIC_STANDBY 131 /* SCU.DSC.PMIC_STANDBY */
|
||||
#define SC_P_SCU_BOOT_MODE0 132 /* SCU.DSC.BOOT_MODE0 */
|
||||
#define SC_P_SCU_BOOT_MODE1 133 /* SCU.DSC.BOOT_MODE1 */
|
||||
#define SC_P_SCU_BOOT_MODE2 134 /* SCU.DSC.BOOT_MODE2, SCU.PMIC_I2C.SDA */
|
||||
#define SC_P_SCU_BOOT_MODE3 135 /* SCU.DSC.BOOT_MODE3, SCU.PMIC_I2C.SCL, SCU.DSC.RTC_CLOCK_OUTPUT_32K */
|
||||
#define SC_P_CSI_D00 136 /* CI_PI.D02, ADMA.SAI0.RXC */
|
||||
#define SC_P_CSI_D01 137 /* CI_PI.D03, ADMA.SAI0.RXD */
|
||||
#define SC_P_CSI_D02 138 /* CI_PI.D04, ADMA.SAI0.RXFS */
|
||||
#define SC_P_CSI_D03 139 /* CI_PI.D05, ADMA.SAI2.RXC */
|
||||
#define SC_P_CSI_D04 140 /* CI_PI.D06, ADMA.SAI2.RXD */
|
||||
#define SC_P_CSI_D05 141 /* CI_PI.D07, ADMA.SAI2.RXFS */
|
||||
#define SC_P_CSI_D06 142 /* CI_PI.D08, ADMA.SAI3.RXC */
|
||||
#define SC_P_CSI_D07 143 /* CI_PI.D09, ADMA.SAI3.RXD */
|
||||
#define SC_P_CSI_HSYNC 144 /* CI_PI.HSYNC, CI_PI.D00, ADMA.SAI3.RXFS */
|
||||
#define SC_P_CSI_VSYNC 145 /* CI_PI.VSYNC, CI_PI.D01 */
|
||||
#define SC_P_CSI_PCLK 146 /* CI_PI.PCLK, MIPI_CSI0.I2C0.SCL, ADMA.SPI1.SCK, LSIO.GPIO3.IO00 */
|
||||
#define SC_P_CSI_MCLK 147 /* CI_PI.MCLK, MIPI_CSI0.I2C0.SDA, ADMA.SPI1.SDO, LSIO.GPIO3.IO01 */
|
||||
#define SC_P_CSI_EN 148 /* CI_PI.EN, CI_PI.I2C.SCL, ADMA.I2C3.SCL, ADMA.SPI1.SDI, LSIO.GPIO3.IO02 */
|
||||
#define SC_P_CSI_RESET 149 /* CI_PI.RESET, CI_PI.I2C.SDA, ADMA.I2C3.SDA, ADMA.SPI1.CS0, LSIO.GPIO3.IO03 */
|
||||
#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHD 150 /* */
|
||||
#define SC_P_MIPI_CSI0_MCLK_OUT 151 /* MIPI_CSI0.ACM.MCLK_OUT, LSIO.GPIO3.IO04 */
|
||||
#define SC_P_MIPI_CSI0_I2C0_SCL 152 /* MIPI_CSI0.I2C0.SCL, MIPI_CSI0.GPIO0.IO02, LSIO.GPIO3.IO05 */
|
||||
#define SC_P_MIPI_CSI0_I2C0_SDA 153 /* MIPI_CSI0.I2C0.SDA, MIPI_CSI0.GPIO0.IO03, LSIO.GPIO3.IO06 */
|
||||
#define SC_P_MIPI_CSI0_GPIO0_01 154 /* MIPI_CSI0.GPIO0.IO01, ADMA.I2C0.SDA, LSIO.GPIO3.IO07 */
|
||||
#define SC_P_MIPI_CSI0_GPIO0_00 155 /* MIPI_CSI0.GPIO0.IO00, ADMA.I2C0.SCL, LSIO.GPIO3.IO08 */
|
||||
#define SC_P_QSPI0A_DATA0 156 /* LSIO.QSPI0A.DATA0, LSIO.GPIO3.IO09 */
|
||||
#define SC_P_QSPI0A_DATA1 157 /* LSIO.QSPI0A.DATA1, LSIO.GPIO3.IO10 */
|
||||
#define SC_P_QSPI0A_DATA2 158 /* LSIO.QSPI0A.DATA2, LSIO.GPIO3.IO11 */
|
||||
#define SC_P_QSPI0A_DATA3 159 /* LSIO.QSPI0A.DATA3, LSIO.GPIO3.IO12 */
|
||||
#define SC_P_QSPI0A_DQS 160 /* LSIO.QSPI0A.DQS, LSIO.GPIO3.IO13 */
|
||||
#define SC_P_QSPI0A_SS0_B 161 /* LSIO.QSPI0A.SS0_B, LSIO.GPIO3.IO14 */
|
||||
#define SC_P_QSPI0A_SS1_B 162 /* LSIO.QSPI0A.SS1_B, LSIO.GPIO3.IO15 */
|
||||
#define SC_P_QSPI0A_SCLK 163 /* LSIO.QSPI0A.SCLK, LSIO.GPIO3.IO16 */
|
||||
#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0A 164 /* */
|
||||
#define SC_P_QSPI0B_SCLK 165 /* LSIO.QSPI0B.SCLK, LSIO.QSPI1A.SCLK, LSIO.KPP0.COL0, LSIO.GPIO3.IO17 */
|
||||
#define SC_P_QSPI0B_DATA0 166 /* LSIO.QSPI0B.DATA0, LSIO.QSPI1A.DATA0, LSIO.KPP0.COL1, LSIO.GPIO3.IO18 */
|
||||
#define SC_P_QSPI0B_DATA1 167 /* LSIO.QSPI0B.DATA1, LSIO.QSPI1A.DATA1, LSIO.KPP0.COL2, LSIO.GPIO3.IO19 */
|
||||
#define SC_P_QSPI0B_DATA2 168 /* LSIO.QSPI0B.DATA2, LSIO.QSPI1A.DATA2, LSIO.KPP0.COL3, LSIO.GPIO3.IO20 */
|
||||
#define SC_P_QSPI0B_DATA3 169 /* LSIO.QSPI0B.DATA3, LSIO.QSPI1A.DATA3, LSIO.KPP0.ROW0, LSIO.GPIO3.IO21 */
|
||||
#define SC_P_QSPI0B_DQS 170 /* LSIO.QSPI0B.DQS, LSIO.QSPI1A.DQS, LSIO.KPP0.ROW1, LSIO.GPIO3.IO22 */
|
||||
#define SC_P_QSPI0B_SS0_B 171 /* LSIO.QSPI0B.SS0_B, LSIO.QSPI1A.SS0_B, LSIO.KPP0.ROW2, LSIO.GPIO3.IO23 */
|
||||
#define SC_P_QSPI0B_SS1_B 172 /* LSIO.QSPI0B.SS1_B, LSIO.QSPI1A.SS1_B, LSIO.KPP0.ROW3, LSIO.GPIO3.IO24 */
|
||||
#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0B 173 /* */
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Pad Mux Definitions
|
||||
* format: name padid padmux
|
||||
*/
|
||||
/*@{*/
|
||||
#define SC_P_PCIE_CTRL0_PERST_B_HSIO_PCIE0_PERST_B SC_P_PCIE_CTRL0_PERST_B 0
|
||||
#define SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 SC_P_PCIE_CTRL0_PERST_B 4
|
||||
#define SC_P_PCIE_CTRL0_CLKREQ_B_HSIO_PCIE0_CLKREQ_B SC_P_PCIE_CTRL0_CLKREQ_B 0
|
||||
#define SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 SC_P_PCIE_CTRL0_CLKREQ_B 4
|
||||
#define SC_P_PCIE_CTRL0_WAKE_B_HSIO_PCIE0_WAKE_B SC_P_PCIE_CTRL0_WAKE_B 0
|
||||
#define SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 SC_P_PCIE_CTRL0_WAKE_B 4
|
||||
#define SC_P_USB_SS3_TC0_ADMA_I2C1_SCL SC_P_USB_SS3_TC0 0
|
||||
#define SC_P_USB_SS3_TC0_CONN_USB_OTG1_PWR SC_P_USB_SS3_TC0 1
|
||||
#define SC_P_USB_SS3_TC0_CONN_USB_OTG2_PWR SC_P_USB_SS3_TC0 2
|
||||
#define SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 SC_P_USB_SS3_TC0 4
|
||||
#define SC_P_USB_SS3_TC1_ADMA_I2C1_SCL SC_P_USB_SS3_TC1 0
|
||||
#define SC_P_USB_SS3_TC1_CONN_USB_OTG2_PWR SC_P_USB_SS3_TC1 1
|
||||
#define SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04 SC_P_USB_SS3_TC1 4
|
||||
#define SC_P_USB_SS3_TC2_ADMA_I2C1_SDA SC_P_USB_SS3_TC2 0
|
||||
#define SC_P_USB_SS3_TC2_CONN_USB_OTG1_OC SC_P_USB_SS3_TC2 1
|
||||
#define SC_P_USB_SS3_TC2_CONN_USB_OTG2_OC SC_P_USB_SS3_TC2 2
|
||||
#define SC_P_USB_SS3_TC2_LSIO_GPIO4_IO05 SC_P_USB_SS3_TC2 4
|
||||
#define SC_P_USB_SS3_TC3_ADMA_I2C1_SDA SC_P_USB_SS3_TC3 0
|
||||
#define SC_P_USB_SS3_TC3_CONN_USB_OTG2_OC SC_P_USB_SS3_TC3 1
|
||||
#define SC_P_USB_SS3_TC3_LSIO_GPIO4_IO06 SC_P_USB_SS3_TC3 4
|
||||
#define SC_P_EMMC0_CLK_CONN_EMMC0_CLK SC_P_EMMC0_CLK 0
|
||||
#define SC_P_EMMC0_CLK_CONN_NAND_READY_B SC_P_EMMC0_CLK 1
|
||||
#define SC_P_EMMC0_CLK_LSIO_GPIO4_IO07 SC_P_EMMC0_CLK 4
|
||||
#define SC_P_EMMC0_CMD_CONN_EMMC0_CMD SC_P_EMMC0_CMD 0
|
||||
#define SC_P_EMMC0_CMD_CONN_NAND_DQS SC_P_EMMC0_CMD 1
|
||||
#define SC_P_EMMC0_CMD_LSIO_GPIO4_IO08 SC_P_EMMC0_CMD 4
|
||||
#define SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 SC_P_EMMC0_DATA0 0
|
||||
#define SC_P_EMMC0_DATA0_CONN_NAND_DATA00 SC_P_EMMC0_DATA0 1
|
||||
#define SC_P_EMMC0_DATA0_LSIO_GPIO4_IO09 SC_P_EMMC0_DATA0 4
|
||||
#define SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 SC_P_EMMC0_DATA1 0
|
||||
#define SC_P_EMMC0_DATA1_CONN_NAND_DATA01 SC_P_EMMC0_DATA1 1
|
||||
#define SC_P_EMMC0_DATA1_LSIO_GPIO4_IO10 SC_P_EMMC0_DATA1 4
|
||||
#define SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 SC_P_EMMC0_DATA2 0
|
||||
#define SC_P_EMMC0_DATA2_CONN_NAND_DATA02 SC_P_EMMC0_DATA2 1
|
||||
#define SC_P_EMMC0_DATA2_LSIO_GPIO4_IO11 SC_P_EMMC0_DATA2 4
|
||||
#define SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 SC_P_EMMC0_DATA3 0
|
||||
#define SC_P_EMMC0_DATA3_CONN_NAND_DATA03 SC_P_EMMC0_DATA3 1
|
||||
#define SC_P_EMMC0_DATA3_LSIO_GPIO4_IO12 SC_P_EMMC0_DATA3 4
|
||||
#define SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 SC_P_EMMC0_DATA4 0
|
||||
#define SC_P_EMMC0_DATA4_CONN_NAND_DATA04 SC_P_EMMC0_DATA4 1
|
||||
#define SC_P_EMMC0_DATA4_CONN_EMMC0_WP SC_P_EMMC0_DATA4 3
|
||||
#define SC_P_EMMC0_DATA4_LSIO_GPIO4_IO13 SC_P_EMMC0_DATA4 4
|
||||
#define SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 SC_P_EMMC0_DATA5 0
|
||||
#define SC_P_EMMC0_DATA5_CONN_NAND_DATA05 SC_P_EMMC0_DATA5 1
|
||||
#define SC_P_EMMC0_DATA5_CONN_EMMC0_VSELECT SC_P_EMMC0_DATA5 3
|
||||
#define SC_P_EMMC0_DATA5_LSIO_GPIO4_IO14 SC_P_EMMC0_DATA5 4
|
||||
#define SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 SC_P_EMMC0_DATA6 0
|
||||
#define SC_P_EMMC0_DATA6_CONN_NAND_DATA06 SC_P_EMMC0_DATA6 1
|
||||
#define SC_P_EMMC0_DATA6_CONN_MLB_CLK SC_P_EMMC0_DATA6 3
|
||||
#define SC_P_EMMC0_DATA6_LSIO_GPIO4_IO15 SC_P_EMMC0_DATA6 4
|
||||
#define SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 SC_P_EMMC0_DATA7 0
|
||||
#define SC_P_EMMC0_DATA7_CONN_NAND_DATA07 SC_P_EMMC0_DATA7 1
|
||||
#define SC_P_EMMC0_DATA7_CONN_MLB_SIG SC_P_EMMC0_DATA7 3
|
||||
#define SC_P_EMMC0_DATA7_LSIO_GPIO4_IO16 SC_P_EMMC0_DATA7 4
|
||||
#define SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE SC_P_EMMC0_STROBE 0
|
||||
#define SC_P_EMMC0_STROBE_CONN_NAND_CLE SC_P_EMMC0_STROBE 1
|
||||
#define SC_P_EMMC0_STROBE_CONN_MLB_DATA SC_P_EMMC0_STROBE 3
|
||||
#define SC_P_EMMC0_STROBE_LSIO_GPIO4_IO17 SC_P_EMMC0_STROBE 4
|
||||
#define SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B SC_P_EMMC0_RESET_B 0
|
||||
#define SC_P_EMMC0_RESET_B_CONN_NAND_WP_B SC_P_EMMC0_RESET_B 1
|
||||
#define SC_P_EMMC0_RESET_B_LSIO_GPIO4_IO18 SC_P_EMMC0_RESET_B 4
|
||||
#define SC_P_USDHC1_RESET_B_CONN_USDHC1_RESET_B SC_P_USDHC1_RESET_B 0
|
||||
#define SC_P_USDHC1_RESET_B_CONN_NAND_RE_N SC_P_USDHC1_RESET_B 1
|
||||
#define SC_P_USDHC1_RESET_B_ADMA_SPI2_SCK SC_P_USDHC1_RESET_B 2
|
||||
#define SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO19 SC_P_USDHC1_RESET_B 4
|
||||
#define SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT SC_P_USDHC1_VSELECT 0
|
||||
#define SC_P_USDHC1_VSELECT_CONN_NAND_RE_P SC_P_USDHC1_VSELECT 1
|
||||
#define SC_P_USDHC1_VSELECT_ADMA_SPI2_SDO SC_P_USDHC1_VSELECT 2
|
||||
#define SC_P_USDHC1_VSELECT_CONN_NAND_RE_B SC_P_USDHC1_VSELECT 3
|
||||
#define SC_P_USDHC1_VSELECT_LSIO_GPIO4_IO20 SC_P_USDHC1_VSELECT 4
|
||||
#define SC_P_USDHC1_WP_CONN_USDHC1_WP SC_P_USDHC1_WP 0
|
||||
#define SC_P_USDHC1_WP_CONN_NAND_DQS_N SC_P_USDHC1_WP 1
|
||||
#define SC_P_USDHC1_WP_ADMA_SPI2_SDI SC_P_USDHC1_WP 2
|
||||
#define SC_P_USDHC1_WP_LSIO_GPIO4_IO21 SC_P_USDHC1_WP 4
|
||||
#define SC_P_USDHC1_CD_B_CONN_USDHC1_CD_B SC_P_USDHC1_CD_B 0
|
||||
#define SC_P_USDHC1_CD_B_CONN_NAND_DQS_P SC_P_USDHC1_CD_B 1
|
||||
#define SC_P_USDHC1_CD_B_ADMA_SPI2_CS0 SC_P_USDHC1_CD_B 2
|
||||
#define SC_P_USDHC1_CD_B_CONN_NAND_DQS SC_P_USDHC1_CD_B 3
|
||||
#define SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22 SC_P_USDHC1_CD_B 4
|
||||
#define SC_P_USDHC1_CLK_CONN_USDHC1_CLK SC_P_USDHC1_CLK 0
|
||||
#define SC_P_USDHC1_CLK_ADMA_UART3_RX SC_P_USDHC1_CLK 2
|
||||
#define SC_P_USDHC1_CLK_LSIO_GPIO4_IO23 SC_P_USDHC1_CLK 4
|
||||
#define SC_P_USDHC1_CMD_CONN_USDHC1_CMD SC_P_USDHC1_CMD 0
|
||||
#define SC_P_USDHC1_CMD_CONN_NAND_CE0_B SC_P_USDHC1_CMD 1
|
||||
#define SC_P_USDHC1_CMD_ADMA_MQS_R SC_P_USDHC1_CMD 2
|
||||
#define SC_P_USDHC1_CMD_LSIO_GPIO4_IO24 SC_P_USDHC1_CMD 4
|
||||
#define SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 SC_P_USDHC1_DATA0 0
|
||||
#define SC_P_USDHC1_DATA0_CONN_NAND_CE1_B SC_P_USDHC1_DATA0 1
|
||||
#define SC_P_USDHC1_DATA0_ADMA_MQS_L SC_P_USDHC1_DATA0 2
|
||||
#define SC_P_USDHC1_DATA0_LSIO_GPIO4_IO25 SC_P_USDHC1_DATA0 4
|
||||
#define SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 SC_P_USDHC1_DATA1 0
|
||||
#define SC_P_USDHC1_DATA1_CONN_NAND_RE_B SC_P_USDHC1_DATA1 1
|
||||
#define SC_P_USDHC1_DATA1_ADMA_UART3_TX SC_P_USDHC1_DATA1 2
|
||||
#define SC_P_USDHC1_DATA1_LSIO_GPIO4_IO26 SC_P_USDHC1_DATA1 4
|
||||
#define SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 SC_P_USDHC1_DATA2 0
|
||||
#define SC_P_USDHC1_DATA2_CONN_NAND_WE_B SC_P_USDHC1_DATA2 1
|
||||
#define SC_P_USDHC1_DATA2_ADMA_UART3_CTS_B SC_P_USDHC1_DATA2 2
|
||||
#define SC_P_USDHC1_DATA2_LSIO_GPIO4_IO27 SC_P_USDHC1_DATA2 4
|
||||
#define SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 SC_P_USDHC1_DATA3 0
|
||||
#define SC_P_USDHC1_DATA3_CONN_NAND_ALE SC_P_USDHC1_DATA3 1
|
||||
#define SC_P_USDHC1_DATA3_ADMA_UART3_RTS_B SC_P_USDHC1_DATA3 2
|
||||
#define SC_P_USDHC1_DATA3_LSIO_GPIO4_IO28 SC_P_USDHC1_DATA3 4
|
||||
#define SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC SC_P_ENET0_RGMII_TXC 0
|
||||
#define SC_P_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT SC_P_ENET0_RGMII_TXC 1
|
||||
#define SC_P_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_IN SC_P_ENET0_RGMII_TXC 2
|
||||
#define SC_P_ENET0_RGMII_TXC_CONN_NAND_CE1_B SC_P_ENET0_RGMII_TXC 3
|
||||
#define SC_P_ENET0_RGMII_TXC_LSIO_GPIO4_IO29 SC_P_ENET0_RGMII_TXC 4
|
||||
#define SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL SC_P_ENET0_RGMII_TX_CTL 0
|
||||
#define SC_P_ENET0_RGMII_TX_CTL_CONN_USDHC1_RESET_B SC_P_ENET0_RGMII_TX_CTL 3
|
||||
#define SC_P_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30 SC_P_ENET0_RGMII_TX_CTL 4
|
||||
#define SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 SC_P_ENET0_RGMII_TXD0 0
|
||||
#define SC_P_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT SC_P_ENET0_RGMII_TXD0 3
|
||||
#define SC_P_ENET0_RGMII_TXD0_LSIO_GPIO4_IO31 SC_P_ENET0_RGMII_TXD0 4
|
||||
#define SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 SC_P_ENET0_RGMII_TXD1 0
|
||||
#define SC_P_ENET0_RGMII_TXD1_CONN_USDHC1_WP SC_P_ENET0_RGMII_TXD1 3
|
||||
#define SC_P_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00 SC_P_ENET0_RGMII_TXD1 4
|
||||
#define SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 SC_P_ENET0_RGMII_TXD2 0
|
||||
#define SC_P_ENET0_RGMII_TXD2_CONN_MLB_CLK SC_P_ENET0_RGMII_TXD2 1
|
||||
#define SC_P_ENET0_RGMII_TXD2_CONN_NAND_CE0_B SC_P_ENET0_RGMII_TXD2 2
|
||||
#define SC_P_ENET0_RGMII_TXD2_CONN_USDHC1_CD_B SC_P_ENET0_RGMII_TXD2 3
|
||||
#define SC_P_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 SC_P_ENET0_RGMII_TXD2 4
|
||||
#define SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 SC_P_ENET0_RGMII_TXD3 0
|
||||
#define SC_P_ENET0_RGMII_TXD3_CONN_MLB_SIG SC_P_ENET0_RGMII_TXD3 1
|
||||
#define SC_P_ENET0_RGMII_TXD3_CONN_NAND_RE_B SC_P_ENET0_RGMII_TXD3 2
|
||||
#define SC_P_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02 SC_P_ENET0_RGMII_TXD3 4
|
||||
#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0 0
|
||||
#define SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC SC_P_ENET0_RGMII_RXC 0
|
||||
#define SC_P_ENET0_RGMII_RXC_CONN_MLB_DATA SC_P_ENET0_RGMII_RXC 1
|
||||
#define SC_P_ENET0_RGMII_RXC_CONN_NAND_WE_B SC_P_ENET0_RGMII_RXC 2
|
||||
#define SC_P_ENET0_RGMII_RXC_CONN_USDHC1_CLK SC_P_ENET0_RGMII_RXC 3
|
||||
#define SC_P_ENET0_RGMII_RXC_LSIO_GPIO5_IO03 SC_P_ENET0_RGMII_RXC 4
|
||||
#define SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL SC_P_ENET0_RGMII_RX_CTL 0
|
||||
#define SC_P_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD SC_P_ENET0_RGMII_RX_CTL 3
|
||||
#define SC_P_ENET0_RGMII_RX_CTL_LSIO_GPIO5_IO04 SC_P_ENET0_RGMII_RX_CTL 4
|
||||
#define SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 SC_P_ENET0_RGMII_RXD0 0
|
||||
#define SC_P_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 SC_P_ENET0_RGMII_RXD0 3
|
||||
#define SC_P_ENET0_RGMII_RXD0_LSIO_GPIO5_IO05 SC_P_ENET0_RGMII_RXD0 4
|
||||
#define SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 SC_P_ENET0_RGMII_RXD1 0
|
||||
#define SC_P_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 SC_P_ENET0_RGMII_RXD1 3
|
||||
#define SC_P_ENET0_RGMII_RXD1_LSIO_GPIO5_IO06 SC_P_ENET0_RGMII_RXD1 4
|
||||
#define SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 SC_P_ENET0_RGMII_RXD2 0
|
||||
#define SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER SC_P_ENET0_RGMII_RXD2 1
|
||||
#define SC_P_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 SC_P_ENET0_RGMII_RXD2 3
|
||||
#define SC_P_ENET0_RGMII_RXD2_LSIO_GPIO5_IO07 SC_P_ENET0_RGMII_RXD2 4
|
||||
#define SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 SC_P_ENET0_RGMII_RXD3 0
|
||||
#define SC_P_ENET0_RGMII_RXD3_CONN_NAND_ALE SC_P_ENET0_RGMII_RXD3 2
|
||||
#define SC_P_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 SC_P_ENET0_RGMII_RXD3 3
|
||||
#define SC_P_ENET0_RGMII_RXD3_LSIO_GPIO5_IO08 SC_P_ENET0_RGMII_RXD3 4
|
||||
#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1 0
|
||||
#define SC_P_ENET0_REFCLK_125M_25M_CONN_ENET0_REFCLK_125M_25M SC_P_ENET0_REFCLK_125M_25M 0
|
||||
#define SC_P_ENET0_REFCLK_125M_25M_CONN_ENET0_PPS SC_P_ENET0_REFCLK_125M_25M 1
|
||||
#define SC_P_ENET0_REFCLK_125M_25M_CONN_ENET1_PPS SC_P_ENET0_REFCLK_125M_25M 2
|
||||
#define SC_P_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 SC_P_ENET0_REFCLK_125M_25M 4
|
||||
#define SC_P_ENET0_MDIO_CONN_ENET0_MDIO SC_P_ENET0_MDIO 0
|
||||
#define SC_P_ENET0_MDIO_ADMA_I2C3_SDA SC_P_ENET0_MDIO 1
|
||||
#define SC_P_ENET0_MDIO_CONN_ENET1_MDIO SC_P_ENET0_MDIO 2
|
||||
#define SC_P_ENET0_MDIO_LSIO_GPIO5_IO10 SC_P_ENET0_MDIO 4
|
||||
#define SC_P_ENET0_MDC_CONN_ENET0_MDC SC_P_ENET0_MDC 0
|
||||
#define SC_P_ENET0_MDC_ADMA_I2C3_SCL SC_P_ENET0_MDC 1
|
||||
#define SC_P_ENET0_MDC_CONN_ENET1_MDC SC_P_ENET0_MDC 2
|
||||
#define SC_P_ENET0_MDC_LSIO_GPIO5_IO11 SC_P_ENET0_MDC 4
|
||||
#define SC_P_ESAI0_FSR_ADMA_ESAI0_FSR SC_P_ESAI0_FSR 0
|
||||
#define SC_P_ESAI0_FSR_CONN_ENET1_RCLK50M_OUT SC_P_ESAI0_FSR 1
|
||||
#define SC_P_ESAI0_FSR_ADMA_LCDIF_D00 SC_P_ESAI0_FSR 2
|
||||
#define SC_P_ESAI0_FSR_CONN_ENET1_RGMII_TXC SC_P_ESAI0_FSR 3
|
||||
#define SC_P_ESAI0_FSR_CONN_ENET1_RCLK50M_IN SC_P_ESAI0_FSR 4
|
||||
#define SC_P_ESAI0_FST_ADMA_ESAI0_FST SC_P_ESAI0_FST 0
|
||||
#define SC_P_ESAI0_FST_CONN_MLB_CLK SC_P_ESAI0_FST 1
|
||||
#define SC_P_ESAI0_FST_ADMA_LCDIF_D01 SC_P_ESAI0_FST 2
|
||||
#define SC_P_ESAI0_FST_CONN_ENET1_RGMII_TXD2 SC_P_ESAI0_FST 3
|
||||
#define SC_P_ESAI0_FST_LSIO_GPIO0_IO01 SC_P_ESAI0_FST 4
|
||||
#define SC_P_ESAI0_SCKR_ADMA_ESAI0_SCKR SC_P_ESAI0_SCKR 0
|
||||
#define SC_P_ESAI0_SCKR_ADMA_LCDIF_D02 SC_P_ESAI0_SCKR 2
|
||||
#define SC_P_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL SC_P_ESAI0_SCKR 3
|
||||
#define SC_P_ESAI0_SCKR_LSIO_GPIO0_IO02 SC_P_ESAI0_SCKR 4
|
||||
#define SC_P_ESAI0_SCKT_ADMA_ESAI0_SCKT SC_P_ESAI0_SCKT 0
|
||||
#define SC_P_ESAI0_SCKT_CONN_MLB_SIG SC_P_ESAI0_SCKT 1
|
||||
#define SC_P_ESAI0_SCKT_ADMA_LCDIF_D03 SC_P_ESAI0_SCKT 2
|
||||
#define SC_P_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3 SC_P_ESAI0_SCKT 3
|
||||
#define SC_P_ESAI0_SCKT_LSIO_GPIO0_IO03 SC_P_ESAI0_SCKT 4
|
||||
#define SC_P_ESAI0_TX0_ADMA_ESAI0_TX0 SC_P_ESAI0_TX0 0
|
||||
#define SC_P_ESAI0_TX0_CONN_MLB_DATA SC_P_ESAI0_TX0 1
|
||||
#define SC_P_ESAI0_TX0_ADMA_LCDIF_D04 SC_P_ESAI0_TX0 2
|
||||
#define SC_P_ESAI0_TX0_CONN_ENET1_RGMII_RXC SC_P_ESAI0_TX0 3
|
||||
#define SC_P_ESAI0_TX0_LSIO_GPIO0_IO04 SC_P_ESAI0_TX0 4
|
||||
#define SC_P_ESAI0_TX1_ADMA_ESAI0_TX1 SC_P_ESAI0_TX1 0
|
||||
#define SC_P_ESAI0_TX1_ADMA_LCDIF_D05 SC_P_ESAI0_TX1 2
|
||||
#define SC_P_ESAI0_TX1_CONN_ENET1_RGMII_RXD3 SC_P_ESAI0_TX1 3
|
||||
#define SC_P_ESAI0_TX1_LSIO_GPIO0_IO05 SC_P_ESAI0_TX1 4
|
||||
#define SC_P_ESAI0_TX2_RX3_ADMA_ESAI0_TX2_RX3 SC_P_ESAI0_TX2_RX3 0
|
||||
#define SC_P_ESAI0_TX2_RX3_CONN_ENET1_RMII_RX_ER SC_P_ESAI0_TX2_RX3 1
|
||||
#define SC_P_ESAI0_TX2_RX3_ADMA_LCDIF_D06 SC_P_ESAI0_TX2_RX3 2
|
||||
#define SC_P_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2 SC_P_ESAI0_TX2_RX3 3
|
||||
#define SC_P_ESAI0_TX2_RX3_LSIO_GPIO0_IO06 SC_P_ESAI0_TX2_RX3 4
|
||||
#define SC_P_ESAI0_TX3_RX2_ADMA_ESAI0_TX3_RX2 SC_P_ESAI0_TX3_RX2 0
|
||||
#define SC_P_ESAI0_TX3_RX2_ADMA_LCDIF_D07 SC_P_ESAI0_TX3_RX2 2
|
||||
#define SC_P_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 SC_P_ESAI0_TX3_RX2 3
|
||||
#define SC_P_ESAI0_TX3_RX2_LSIO_GPIO0_IO07 SC_P_ESAI0_TX3_RX2 4
|
||||
#define SC_P_ESAI0_TX4_RX1_ADMA_ESAI0_TX4_RX1 SC_P_ESAI0_TX4_RX1 0
|
||||
#define SC_P_ESAI0_TX4_RX1_ADMA_LCDIF_D08 SC_P_ESAI0_TX4_RX1 2
|
||||
#define SC_P_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 SC_P_ESAI0_TX4_RX1 3
|
||||
#define SC_P_ESAI0_TX4_RX1_LSIO_GPIO0_IO08 SC_P_ESAI0_TX4_RX1 4
|
||||
#define SC_P_ESAI0_TX5_RX0_ADMA_ESAI0_TX5_RX0 SC_P_ESAI0_TX5_RX0 0
|
||||
#define SC_P_ESAI0_TX5_RX0_ADMA_LCDIF_D09 SC_P_ESAI0_TX5_RX0 2
|
||||
#define SC_P_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 SC_P_ESAI0_TX5_RX0 3
|
||||
#define SC_P_ESAI0_TX5_RX0_LSIO_GPIO0_IO09 SC_P_ESAI0_TX5_RX0 4
|
||||
#define SC_P_SPDIF0_RX_ADMA_SPDIF0_RX SC_P_SPDIF0_RX 0
|
||||
#define SC_P_SPDIF0_RX_ADMA_MQS_R SC_P_SPDIF0_RX 1
|
||||
#define SC_P_SPDIF0_RX_ADMA_LCDIF_D10 SC_P_SPDIF0_RX 2
|
||||
#define SC_P_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 SC_P_SPDIF0_RX 3
|
||||
#define SC_P_SPDIF0_RX_LSIO_GPIO0_IO10 SC_P_SPDIF0_RX 4
|
||||
#define SC_P_SPDIF0_TX_ADMA_SPDIF0_TX SC_P_SPDIF0_TX 0
|
||||
#define SC_P_SPDIF0_TX_ADMA_MQS_L SC_P_SPDIF0_TX 1
|
||||
#define SC_P_SPDIF0_TX_ADMA_LCDIF_D11 SC_P_SPDIF0_TX 2
|
||||
#define SC_P_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL SC_P_SPDIF0_TX 3
|
||||
#define SC_P_SPDIF0_TX_LSIO_GPIO0_IO11 SC_P_SPDIF0_TX 4
|
||||
#define SC_P_SPDIF0_EXT_CLK_ADMA_SPDIF0_EXT_CLK SC_P_SPDIF0_EXT_CLK 0
|
||||
#define SC_P_SPDIF0_EXT_CLK_ADMA_LCDIF_D12 SC_P_SPDIF0_EXT_CLK 2
|
||||
#define SC_P_SPDIF0_EXT_CLK_CONN_ENET1_REFCLK_125M_25M SC_P_SPDIF0_EXT_CLK 3
|
||||
#define SC_P_SPDIF0_EXT_CLK_LSIO_GPIO0_IO12 SC_P_SPDIF0_EXT_CLK 4
|
||||
#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB 0
|
||||
#define SC_P_SPI3_SCK_ADMA_SPI3_SCK SC_P_SPI3_SCK 0
|
||||
#define SC_P_SPI3_SCK_ADMA_LCDIF_D13 SC_P_SPI3_SCK 2
|
||||
#define SC_P_SPI3_SCK_LSIO_GPIO0_IO13 SC_P_SPI3_SCK 4
|
||||
#define SC_P_SPI3_SDO_ADMA_SPI3_SDO SC_P_SPI3_SDO 0
|
||||
#define SC_P_SPI3_SDO_ADMA_LCDIF_D14 SC_P_SPI3_SDO 2
|
||||
#define SC_P_SPI3_SDO_LSIO_GPIO0_IO14 SC_P_SPI3_SDO 4
|
||||
#define SC_P_SPI3_SDI_ADMA_SPI3_SDI SC_P_SPI3_SDI 0
|
||||
#define SC_P_SPI3_SDI_ADMA_LCDIF_D15 SC_P_SPI3_SDI 2
|
||||
#define SC_P_SPI3_SDI_LSIO_GPIO0_IO15 SC_P_SPI3_SDI 4
|
||||
#define SC_P_SPI3_CS0_ADMA_SPI3_CS0 SC_P_SPI3_CS0 0
|
||||
#define SC_P_SPI3_CS0_ADMA_ACM_MCLK_OUT1 SC_P_SPI3_CS0 1
|
||||
#define SC_P_SPI3_CS0_ADMA_LCDIF_HSYNC SC_P_SPI3_CS0 2
|
||||
#define SC_P_SPI3_CS0_LSIO_GPIO0_IO16 SC_P_SPI3_CS0 4
|
||||
#define SC_P_SPI3_CS1_ADMA_SPI3_CS1 SC_P_SPI3_CS1 0
|
||||
#define SC_P_SPI3_CS1_ADMA_I2C3_SCL SC_P_SPI3_CS1 1
|
||||
#define SC_P_SPI3_CS1_ADMA_LCDIF_RESET SC_P_SPI3_CS1 2
|
||||
#define SC_P_SPI3_CS1_ADMA_SPI2_CS0 SC_P_SPI3_CS1 3
|
||||
#define SC_P_SPI3_CS1_ADMA_LCDIF_D16 SC_P_SPI3_CS1 4
|
||||
#define SC_P_MCLK_IN1_ADMA_ACM_MCLK_IN1 SC_P_MCLK_IN1 0
|
||||
#define SC_P_MCLK_IN1_ADMA_I2C3_SDA SC_P_MCLK_IN1 1
|
||||
#define SC_P_MCLK_IN1_ADMA_LCDIF_EN SC_P_MCLK_IN1 2
|
||||
#define SC_P_MCLK_IN1_ADMA_SPI2_SCK SC_P_MCLK_IN1 3
|
||||
#define SC_P_MCLK_IN1_ADMA_LCDIF_D17 SC_P_MCLK_IN1 4
|
||||
#define SC_P_MCLK_IN0_ADMA_ACM_MCLK_IN0 SC_P_MCLK_IN0 0
|
||||
#define SC_P_MCLK_IN0_ADMA_ESAI0_RX_HF_CLK SC_P_MCLK_IN0 1
|
||||
#define SC_P_MCLK_IN0_ADMA_LCDIF_VSYNC SC_P_MCLK_IN0 2
|
||||
#define SC_P_MCLK_IN0_ADMA_SPI2_SDI SC_P_MCLK_IN0 3
|
||||
#define SC_P_MCLK_IN0_LSIO_GPIO0_IO19 SC_P_MCLK_IN0 4
|
||||
#define SC_P_MCLK_OUT0_ADMA_ACM_MCLK_OUT0 SC_P_MCLK_OUT0 0
|
||||
#define SC_P_MCLK_OUT0_ADMA_ESAI0_TX_HF_CLK SC_P_MCLK_OUT0 1
|
||||
#define SC_P_MCLK_OUT0_ADMA_LCDIF_CLK SC_P_MCLK_OUT0 2
|
||||
#define SC_P_MCLK_OUT0_ADMA_SPI2_SDO SC_P_MCLK_OUT0 3
|
||||
#define SC_P_MCLK_OUT0_LSIO_GPIO0_IO20 SC_P_MCLK_OUT0 4
|
||||
#define SC_P_UART1_TX_ADMA_UART1_TX SC_P_UART1_TX 0
|
||||
#define SC_P_UART1_TX_LSIO_PWM0_OUT SC_P_UART1_TX 1
|
||||
#define SC_P_UART1_TX_LSIO_GPT0_CAPTURE SC_P_UART1_TX 2
|
||||
#define SC_P_UART1_TX_LSIO_GPIO0_IO21 SC_P_UART1_TX 4
|
||||
#define SC_P_UART1_RX_ADMA_UART1_RX SC_P_UART1_RX 0
|
||||
#define SC_P_UART1_RX_LSIO_PWM1_OUT SC_P_UART1_RX 1
|
||||
#define SC_P_UART1_RX_LSIO_GPT0_COMPARE SC_P_UART1_RX 2
|
||||
#define SC_P_UART1_RX_LSIO_GPT1_CLK SC_P_UART1_RX 3
|
||||
#define SC_P_UART1_RX_LSIO_GPIO0_IO22 SC_P_UART1_RX 4
|
||||
#define SC_P_UART1_RTS_B_ADMA_UART1_RTS_B SC_P_UART1_RTS_B 0
|
||||
#define SC_P_UART1_RTS_B_LSIO_PWM2_OUT SC_P_UART1_RTS_B 1
|
||||
#define SC_P_UART1_RTS_B_ADMA_LCDIF_D16 SC_P_UART1_RTS_B 2
|
||||
#define SC_P_UART1_RTS_B_LSIO_GPT1_CAPTURE SC_P_UART1_RTS_B 3
|
||||
#define SC_P_UART1_RTS_B_LSIO_GPT0_CLK SC_P_UART1_RTS_B 4
|
||||
#define SC_P_UART1_CTS_B_ADMA_UART1_CTS_B SC_P_UART1_CTS_B 0
|
||||
#define SC_P_UART1_CTS_B_LSIO_PWM3_OUT SC_P_UART1_CTS_B 1
|
||||
#define SC_P_UART1_CTS_B_ADMA_LCDIF_D17 SC_P_UART1_CTS_B 2
|
||||
#define SC_P_UART1_CTS_B_LSIO_GPT1_COMPARE SC_P_UART1_CTS_B 3
|
||||
#define SC_P_UART1_CTS_B_LSIO_GPIO0_IO24 SC_P_UART1_CTS_B 4
|
||||
#define SC_P_SAI0_TXD_ADMA_SAI0_TXD SC_P_SAI0_TXD 0
|
||||
#define SC_P_SAI0_TXD_ADMA_SAI1_RXC SC_P_SAI0_TXD 1
|
||||
#define SC_P_SAI0_TXD_ADMA_SPI1_SDO SC_P_SAI0_TXD 2
|
||||
#define SC_P_SAI0_TXD_ADMA_LCDIF_D18 SC_P_SAI0_TXD 3
|
||||
#define SC_P_SAI0_TXD_LSIO_GPIO0_IO25 SC_P_SAI0_TXD 4
|
||||
#define SC_P_SAI0_TXC_ADMA_SAI0_TXC SC_P_SAI0_TXC 0
|
||||
#define SC_P_SAI0_TXC_ADMA_SAI1_TXD SC_P_SAI0_TXC 1
|
||||
#define SC_P_SAI0_TXC_ADMA_SPI1_SDI SC_P_SAI0_TXC 2
|
||||
#define SC_P_SAI0_TXC_ADMA_LCDIF_D19 SC_P_SAI0_TXC 3
|
||||
#define SC_P_SAI0_TXC_LSIO_GPIO0_IO26 SC_P_SAI0_TXC 4
|
||||
#define SC_P_SAI0_RXD_ADMA_SAI0_RXD SC_P_SAI0_RXD 0
|
||||
#define SC_P_SAI0_RXD_ADMA_SAI1_RXFS SC_P_SAI0_RXD 1
|
||||
#define SC_P_SAI0_RXD_ADMA_SPI1_CS0 SC_P_SAI0_RXD 2
|
||||
#define SC_P_SAI0_RXD_ADMA_LCDIF_D20 SC_P_SAI0_RXD 3
|
||||
#define SC_P_SAI0_RXD_LSIO_GPIO0_IO27 SC_P_SAI0_RXD 4
|
||||
#define SC_P_SAI0_TXFS_ADMA_SAI0_TXFS SC_P_SAI0_TXFS 0
|
||||
#define SC_P_SAI0_TXFS_ADMA_SPI2_CS1 SC_P_SAI0_TXFS 1
|
||||
#define SC_P_SAI0_TXFS_ADMA_SPI1_SCK SC_P_SAI0_TXFS 2
|
||||
#define SC_P_SAI0_TXFS_LSIO_GPIO0_IO28 SC_P_SAI0_TXFS 4
|
||||
#define SC_P_SAI1_RXD_ADMA_SAI1_RXD SC_P_SAI1_RXD 0
|
||||
#define SC_P_SAI1_RXD_ADMA_SAI0_RXFS SC_P_SAI1_RXD 1
|
||||
#define SC_P_SAI1_RXD_ADMA_SPI1_CS1 SC_P_SAI1_RXD 2
|
||||
#define SC_P_SAI1_RXD_ADMA_LCDIF_D21 SC_P_SAI1_RXD 3
|
||||
#define SC_P_SAI1_RXD_LSIO_GPIO0_IO29 SC_P_SAI1_RXD 4
|
||||
#define SC_P_SAI1_RXC_ADMA_SAI1_RXC SC_P_SAI1_RXC 0
|
||||
#define SC_P_SAI1_RXC_ADMA_SAI1_TXC SC_P_SAI1_RXC 1
|
||||
#define SC_P_SAI1_RXC_ADMA_LCDIF_D22 SC_P_SAI1_RXC 3
|
||||
#define SC_P_SAI1_RXC_LSIO_GPIO0_IO30 SC_P_SAI1_RXC 4
|
||||
#define SC_P_SAI1_RXFS_ADMA_SAI1_RXFS SC_P_SAI1_RXFS 0
|
||||
#define SC_P_SAI1_RXFS_ADMA_SAI1_TXFS SC_P_SAI1_RXFS 1
|
||||
#define SC_P_SAI1_RXFS_ADMA_LCDIF_D23 SC_P_SAI1_RXFS 3
|
||||
#define SC_P_SAI1_RXFS_LSIO_GPIO0_IO31 SC_P_SAI1_RXFS 4
|
||||
#define SC_P_SPI2_CS0_ADMA_SPI2_CS0 SC_P_SPI2_CS0 0
|
||||
#define SC_P_SPI2_CS0_LSIO_GPIO1_IO00 SC_P_SPI2_CS0 4
|
||||
#define SC_P_SPI2_SDO_ADMA_SPI2_SDO SC_P_SPI2_SDO 0
|
||||
#define SC_P_SPI2_SDO_LSIO_GPIO1_IO01 SC_P_SPI2_SDO 4
|
||||
#define SC_P_SPI2_SDI_ADMA_SPI2_SDI SC_P_SPI2_SDI 0
|
||||
#define SC_P_SPI2_SDI_LSIO_GPIO1_IO02 SC_P_SPI2_SDI 4
|
||||
#define SC_P_SPI2_SCK_ADMA_SPI2_SCK SC_P_SPI2_SCK 0
|
||||
#define SC_P_SPI2_SCK_LSIO_GPIO1_IO03 SC_P_SPI2_SCK 4
|
||||
#define SC_P_SPI0_SCK_ADMA_SPI0_SCK SC_P_SPI0_SCK 0
|
||||
#define SC_P_SPI0_SCK_ADMA_SAI0_TXC SC_P_SPI0_SCK 1
|
||||
#define SC_P_SPI0_SCK_M40_I2C0_SCL SC_P_SPI0_SCK 2
|
||||
#define SC_P_SPI0_SCK_M40_GPIO0_IO00 SC_P_SPI0_SCK 3
|
||||
#define SC_P_SPI0_SCK_LSIO_GPIO1_IO04 SC_P_SPI0_SCK 4
|
||||
#define SC_P_SPI0_SDI_ADMA_SPI0_SDI SC_P_SPI0_SDI 0
|
||||
#define SC_P_SPI0_SDI_ADMA_SAI0_TXD SC_P_SPI0_SDI 1
|
||||
#define SC_P_SPI0_SDI_M40_TPM0_CH0 SC_P_SPI0_SDI 2
|
||||
#define SC_P_SPI0_SDI_M40_GPIO0_IO02 SC_P_SPI0_SDI 3
|
||||
#define SC_P_SPI0_SDI_LSIO_GPIO1_IO05 SC_P_SPI0_SDI 4
|
||||
#define SC_P_SPI0_SDO_ADMA_SPI0_SDO SC_P_SPI0_SDO 0
|
||||
#define SC_P_SPI0_SDO_ADMA_SAI0_TXFS SC_P_SPI0_SDO 1
|
||||
#define SC_P_SPI0_SDO_M40_I2C0_SDA SC_P_SPI0_SDO 2
|
||||
#define SC_P_SPI0_SDO_M40_GPIO0_IO01 SC_P_SPI0_SDO 3
|
||||
#define SC_P_SPI0_SDO_LSIO_GPIO1_IO06 SC_P_SPI0_SDO 4
|
||||
#define SC_P_SPI0_CS1_ADMA_SPI0_CS1 SC_P_SPI0_CS1 0
|
||||
#define SC_P_SPI0_CS1_ADMA_SAI0_RXC SC_P_SPI0_CS1 1
|
||||
#define SC_P_SPI0_CS1_ADMA_SAI1_TXD SC_P_SPI0_CS1 2
|
||||
#define SC_P_SPI0_CS1_ADMA_LCD_PWM0_OUT SC_P_SPI0_CS1 3
|
||||
#define SC_P_SPI0_CS1_LSIO_GPIO1_IO07 SC_P_SPI0_CS1 4
|
||||
#define SC_P_SPI0_CS0_ADMA_SPI0_CS0 SC_P_SPI0_CS0 0
|
||||
#define SC_P_SPI0_CS0_ADMA_SAI0_RXD SC_P_SPI0_CS0 1
|
||||
#define SC_P_SPI0_CS0_M40_TPM0_CH1 SC_P_SPI0_CS0 2
|
||||
#define SC_P_SPI0_CS0_M40_GPIO0_IO03 SC_P_SPI0_CS0 3
|
||||
#define SC_P_SPI0_CS0_LSIO_GPIO1_IO08 SC_P_SPI0_CS0 4
|
||||
#define SC_P_ADC_IN1_ADMA_ADC_IN1 SC_P_ADC_IN1 0
|
||||
#define SC_P_ADC_IN1_M40_I2C0_SDA SC_P_ADC_IN1 1
|
||||
#define SC_P_ADC_IN1_M40_GPIO0_IO01 SC_P_ADC_IN1 2
|
||||
#define SC_P_ADC_IN1_LSIO_GPIO1_IO09 SC_P_ADC_IN1 4
|
||||
#define SC_P_ADC_IN0_ADMA_ADC_IN0 SC_P_ADC_IN0 0
|
||||
#define SC_P_ADC_IN0_M40_I2C0_SCL SC_P_ADC_IN0 1
|
||||
#define SC_P_ADC_IN0_M40_GPIO0_IO00 SC_P_ADC_IN0 2
|
||||
#define SC_P_ADC_IN0_LSIO_GPIO1_IO10 SC_P_ADC_IN0 4
|
||||
#define SC_P_ADC_IN3_ADMA_ADC_IN3 SC_P_ADC_IN3 0
|
||||
#define SC_P_ADC_IN3_M40_UART0_TX SC_P_ADC_IN3 1
|
||||
#define SC_P_ADC_IN3_M40_GPIO0_IO03 SC_P_ADC_IN3 2
|
||||
#define SC_P_ADC_IN3_ADMA_ACM_MCLK_OUT0 SC_P_ADC_IN3 3
|
||||
#define SC_P_ADC_IN3_LSIO_GPIO1_IO11 SC_P_ADC_IN3 4
|
||||
#define SC_P_ADC_IN2_ADMA_ADC_IN2 SC_P_ADC_IN2 0
|
||||
#define SC_P_ADC_IN2_M40_UART0_RX SC_P_ADC_IN2 1
|
||||
#define SC_P_ADC_IN2_M40_GPIO0_IO02 SC_P_ADC_IN2 2
|
||||
#define SC_P_ADC_IN2_ADMA_ACM_MCLK_IN0 SC_P_ADC_IN2 3
|
||||
#define SC_P_ADC_IN2_LSIO_GPIO1_IO12 SC_P_ADC_IN2 4
|
||||
#define SC_P_ADC_IN5_ADMA_ADC_IN5 SC_P_ADC_IN5 0
|
||||
#define SC_P_ADC_IN5_M40_TPM0_CH1 SC_P_ADC_IN5 1
|
||||
#define SC_P_ADC_IN5_M40_GPIO0_IO05 SC_P_ADC_IN5 2
|
||||
#define SC_P_ADC_IN5_LSIO_GPIO1_IO13 SC_P_ADC_IN5 4
|
||||
#define SC_P_ADC_IN4_ADMA_ADC_IN4 SC_P_ADC_IN4 0
|
||||
#define SC_P_ADC_IN4_M40_TPM0_CH0 SC_P_ADC_IN4 1
|
||||
#define SC_P_ADC_IN4_M40_GPIO0_IO04 SC_P_ADC_IN4 2
|
||||
#define SC_P_ADC_IN4_LSIO_GPIO1_IO14 SC_P_ADC_IN4 4
|
||||
#define SC_P_FLEXCAN0_RX_ADMA_FLEXCAN0_RX SC_P_FLEXCAN0_RX 0
|
||||
#define SC_P_FLEXCAN0_RX_ADMA_SAI2_RXC SC_P_FLEXCAN0_RX 1
|
||||
#define SC_P_FLEXCAN0_RX_ADMA_UART0_RTS_B SC_P_FLEXCAN0_RX 2
|
||||
#define SC_P_FLEXCAN0_RX_ADMA_SAI1_TXC SC_P_FLEXCAN0_RX 3
|
||||
#define SC_P_FLEXCAN0_RX_LSIO_GPIO1_IO15 SC_P_FLEXCAN0_RX 4
|
||||
#define SC_P_FLEXCAN0_TX_ADMA_FLEXCAN0_TX SC_P_FLEXCAN0_TX 0
|
||||
#define SC_P_FLEXCAN0_TX_ADMA_SAI2_RXD SC_P_FLEXCAN0_TX 1
|
||||
#define SC_P_FLEXCAN0_TX_ADMA_UART0_CTS_B SC_P_FLEXCAN0_TX 2
|
||||
#define SC_P_FLEXCAN0_TX_ADMA_SAI1_TXFS SC_P_FLEXCAN0_TX 3
|
||||
#define SC_P_FLEXCAN0_TX_LSIO_GPIO1_IO16 SC_P_FLEXCAN0_TX 4
|
||||
#define SC_P_FLEXCAN1_RX_ADMA_FLEXCAN1_RX SC_P_FLEXCAN1_RX 0
|
||||
#define SC_P_FLEXCAN1_RX_ADMA_SAI2_RXFS SC_P_FLEXCAN1_RX 1
|
||||
#define SC_P_FLEXCAN1_RX_ADMA_FTM_CH2 SC_P_FLEXCAN1_RX 2
|
||||
#define SC_P_FLEXCAN1_RX_ADMA_SAI1_TXD SC_P_FLEXCAN1_RX 3
|
||||
#define SC_P_FLEXCAN1_RX_LSIO_GPIO1_IO17 SC_P_FLEXCAN1_RX 4
|
||||
#define SC_P_FLEXCAN1_TX_ADMA_FLEXCAN1_TX SC_P_FLEXCAN1_TX 0
|
||||
#define SC_P_FLEXCAN1_TX_ADMA_SAI3_RXC SC_P_FLEXCAN1_TX 1
|
||||
#define SC_P_FLEXCAN1_TX_ADMA_DMA0_REQ_IN0 SC_P_FLEXCAN1_TX 2
|
||||
#define SC_P_FLEXCAN1_TX_ADMA_SAI1_RXD SC_P_FLEXCAN1_TX 3
|
||||
#define SC_P_FLEXCAN1_TX_LSIO_GPIO1_IO18 SC_P_FLEXCAN1_TX 4
|
||||
#define SC_P_FLEXCAN2_RX_ADMA_FLEXCAN2_RX SC_P_FLEXCAN2_RX 0
|
||||
#define SC_P_FLEXCAN2_RX_ADMA_SAI3_RXD SC_P_FLEXCAN2_RX 1
|
||||
#define SC_P_FLEXCAN2_RX_ADMA_UART3_RX SC_P_FLEXCAN2_RX 2
|
||||
#define SC_P_FLEXCAN2_RX_ADMA_SAI1_RXFS SC_P_FLEXCAN2_RX 3
|
||||
#define SC_P_FLEXCAN2_RX_LSIO_GPIO1_IO19 SC_P_FLEXCAN2_RX 4
|
||||
#define SC_P_FLEXCAN2_TX_ADMA_FLEXCAN2_TX SC_P_FLEXCAN2_TX 0
|
||||
#define SC_P_FLEXCAN2_TX_ADMA_SAI3_RXFS SC_P_FLEXCAN2_TX 1
|
||||
#define SC_P_FLEXCAN2_TX_ADMA_UART3_TX SC_P_FLEXCAN2_TX 2
|
||||
#define SC_P_FLEXCAN2_TX_ADMA_SAI1_RXC SC_P_FLEXCAN2_TX 3
|
||||
#define SC_P_FLEXCAN2_TX_LSIO_GPIO1_IO20 SC_P_FLEXCAN2_TX 4
|
||||
#define SC_P_UART0_RX_ADMA_UART0_RX SC_P_UART0_RX 0
|
||||
#define SC_P_UART0_RX_ADMA_MQS_R SC_P_UART0_RX 1
|
||||
#define SC_P_UART0_RX_ADMA_FLEXCAN0_RX SC_P_UART0_RX 2
|
||||
#define SC_P_UART0_RX_SCU_UART0_RX SC_P_UART0_RX 3
|
||||
#define SC_P_UART0_RX_LSIO_GPIO1_IO21 SC_P_UART0_RX 4
|
||||
#define SC_P_UART0_TX_ADMA_UART0_TX SC_P_UART0_TX 0
|
||||
#define SC_P_UART0_TX_ADMA_MQS_L SC_P_UART0_TX 1
|
||||
#define SC_P_UART0_TX_ADMA_FLEXCAN0_TX SC_P_UART0_TX 2
|
||||
#define SC_P_UART0_TX_SCU_UART0_TX SC_P_UART0_TX 3
|
||||
#define SC_P_UART0_TX_LSIO_GPIO1_IO22 SC_P_UART0_TX 4
|
||||
#define SC_P_UART2_TX_ADMA_UART2_TX SC_P_UART2_TX 0
|
||||
#define SC_P_UART2_TX_ADMA_FTM_CH1 SC_P_UART2_TX 1
|
||||
#define SC_P_UART2_TX_ADMA_FLEXCAN1_TX SC_P_UART2_TX 2
|
||||
#define SC_P_UART2_TX_LSIO_GPIO1_IO23 SC_P_UART2_TX 4
|
||||
#define SC_P_UART2_RX_ADMA_UART2_RX SC_P_UART2_RX 0
|
||||
#define SC_P_UART2_RX_ADMA_FTM_CH0 SC_P_UART2_RX 1
|
||||
#define SC_P_UART2_RX_ADMA_FLEXCAN1_RX SC_P_UART2_RX 2
|
||||
#define SC_P_UART2_RX_LSIO_GPIO1_IO24 SC_P_UART2_RX 4
|
||||
#define SC_P_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL SC_P_MIPI_DSI0_I2C0_SCL 0
|
||||
#define SC_P_MIPI_DSI0_I2C0_SCL_MIPI_DSI1_GPIO0_IO02 SC_P_MIPI_DSI0_I2C0_SCL 1
|
||||
#define SC_P_MIPI_DSI0_I2C0_SCL_LSIO_GPIO1_IO25 SC_P_MIPI_DSI0_I2C0_SCL 4
|
||||
#define SC_P_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA SC_P_MIPI_DSI0_I2C0_SDA 0
|
||||
#define SC_P_MIPI_DSI0_I2C0_SDA_MIPI_DSI1_GPIO0_IO03 SC_P_MIPI_DSI0_I2C0_SDA 1
|
||||
#define SC_P_MIPI_DSI0_I2C0_SDA_LSIO_GPIO1_IO26 SC_P_MIPI_DSI0_I2C0_SDA 4
|
||||
#define SC_P_MIPI_DSI0_GPIO0_00_MIPI_DSI0_GPIO0_IO00 SC_P_MIPI_DSI0_GPIO0_00 0
|
||||
#define SC_P_MIPI_DSI0_GPIO0_00_ADMA_I2C1_SCL SC_P_MIPI_DSI0_GPIO0_00 1
|
||||
#define SC_P_MIPI_DSI0_GPIO0_00_MIPI_DSI0_PWM0_OUT SC_P_MIPI_DSI0_GPIO0_00 2
|
||||
#define SC_P_MIPI_DSI0_GPIO0_00_LSIO_GPIO1_IO27 SC_P_MIPI_DSI0_GPIO0_00 4
|
||||
#define SC_P_MIPI_DSI0_GPIO0_01_MIPI_DSI0_GPIO0_IO01 SC_P_MIPI_DSI0_GPIO0_01 0
|
||||
#define SC_P_MIPI_DSI0_GPIO0_01_ADMA_I2C1_SDA SC_P_MIPI_DSI0_GPIO0_01 1
|
||||
#define SC_P_MIPI_DSI0_GPIO0_01_LSIO_GPIO1_IO28 SC_P_MIPI_DSI0_GPIO0_01 4
|
||||
#define SC_P_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL SC_P_MIPI_DSI1_I2C0_SCL 0
|
||||
#define SC_P_MIPI_DSI1_I2C0_SCL_MIPI_DSI0_GPIO0_IO02 SC_P_MIPI_DSI1_I2C0_SCL 1
|
||||
#define SC_P_MIPI_DSI1_I2C0_SCL_LSIO_GPIO1_IO29 SC_P_MIPI_DSI1_I2C0_SCL 4
|
||||
#define SC_P_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA SC_P_MIPI_DSI1_I2C0_SDA 0
|
||||
#define SC_P_MIPI_DSI1_I2C0_SDA_MIPI_DSI0_GPIO0_IO03 SC_P_MIPI_DSI1_I2C0_SDA 1
|
||||
#define SC_P_MIPI_DSI1_I2C0_SDA_LSIO_GPIO1_IO30 SC_P_MIPI_DSI1_I2C0_SDA 4
|
||||
#define SC_P_MIPI_DSI1_GPIO0_00_MIPI_DSI1_GPIO0_IO00 SC_P_MIPI_DSI1_GPIO0_00 0
|
||||
#define SC_P_MIPI_DSI1_GPIO0_00_ADMA_I2C2_SCL SC_P_MIPI_DSI1_GPIO0_00 1
|
||||
#define SC_P_MIPI_DSI1_GPIO0_00_MIPI_DSI1_PWM0_OUT SC_P_MIPI_DSI1_GPIO0_00 2
|
||||
#define SC_P_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO31 SC_P_MIPI_DSI1_GPIO0_00 4
|
||||
#define SC_P_MIPI_DSI1_GPIO0_01_MIPI_DSI1_GPIO0_IO01 SC_P_MIPI_DSI1_GPIO0_01 0
|
||||
#define SC_P_MIPI_DSI1_GPIO0_01_ADMA_I2C2_SDA SC_P_MIPI_DSI1_GPIO0_01 1
|
||||
#define SC_P_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00 SC_P_MIPI_DSI1_GPIO0_01 4
|
||||
#define SC_P_JTAG_TRST_B_SCU_JTAG_TRST_B SC_P_JTAG_TRST_B 0
|
||||
#define SC_P_JTAG_TRST_B_SCU_WDOG0_WDOG_OUT SC_P_JTAG_TRST_B 1
|
||||
#define SC_P_PMIC_I2C_SCL_SCU_PMIC_I2C_SCL SC_P_PMIC_I2C_SCL 0
|
||||
#define SC_P_PMIC_I2C_SCL_SCU_GPIO0_IOXX_PMIC_A35_ON SC_P_PMIC_I2C_SCL 1
|
||||
#define SC_P_PMIC_I2C_SCL_LSIO_GPIO2_IO01 SC_P_PMIC_I2C_SCL 4
|
||||
#define SC_P_PMIC_I2C_SDA_SCU_PMIC_I2C_SDA SC_P_PMIC_I2C_SDA 0
|
||||
#define SC_P_PMIC_I2C_SDA_SCU_GPIO0_IOXX_PMIC_GPU_ON SC_P_PMIC_I2C_SDA 1
|
||||
#define SC_P_PMIC_I2C_SDA_LSIO_GPIO2_IO02 SC_P_PMIC_I2C_SDA 4
|
||||
#define SC_P_PMIC_INT_B_SCU_DSC_PMIC_INT_B SC_P_PMIC_INT_B 0
|
||||
#define SC_P_SCU_GPIO0_00_SCU_GPIO0_IO00 SC_P_SCU_GPIO0_00 0
|
||||
#define SC_P_SCU_GPIO0_00_SCU_UART0_RX SC_P_SCU_GPIO0_00 1
|
||||
#define SC_P_SCU_GPIO0_00_M40_UART0_RX SC_P_SCU_GPIO0_00 2
|
||||
#define SC_P_SCU_GPIO0_00_ADMA_UART3_RX SC_P_SCU_GPIO0_00 3
|
||||
#define SC_P_SCU_GPIO0_00_LSIO_GPIO2_IO03 SC_P_SCU_GPIO0_00 4
|
||||
#define SC_P_SCU_GPIO0_01_SCU_GPIO0_IO01 SC_P_SCU_GPIO0_01 0
|
||||
#define SC_P_SCU_GPIO0_01_SCU_UART0_TX SC_P_SCU_GPIO0_01 1
|
||||
#define SC_P_SCU_GPIO0_01_M40_UART0_TX SC_P_SCU_GPIO0_01 2
|
||||
#define SC_P_SCU_GPIO0_01_ADMA_UART3_TX SC_P_SCU_GPIO0_01 3
|
||||
#define SC_P_SCU_GPIO0_01_SCU_WDOG0_WDOG_OUT SC_P_SCU_GPIO0_01 4
|
||||
#define SC_P_SCU_PMIC_STANDBY_SCU_DSC_PMIC_STANDBY SC_P_SCU_PMIC_STANDBY 0
|
||||
#define SC_P_SCU_BOOT_MODE0_SCU_DSC_BOOT_MODE0 SC_P_SCU_BOOT_MODE0 0
|
||||
#define SC_P_SCU_BOOT_MODE1_SCU_DSC_BOOT_MODE1 SC_P_SCU_BOOT_MODE1 0
|
||||
#define SC_P_SCU_BOOT_MODE2_SCU_DSC_BOOT_MODE2 SC_P_SCU_BOOT_MODE2 0
|
||||
#define SC_P_SCU_BOOT_MODE2_SCU_PMIC_I2C_SDA SC_P_SCU_BOOT_MODE2 1
|
||||
#define SC_P_SCU_BOOT_MODE3_SCU_DSC_BOOT_MODE3 SC_P_SCU_BOOT_MODE3 0
|
||||
#define SC_P_SCU_BOOT_MODE3_SCU_PMIC_I2C_SCL SC_P_SCU_BOOT_MODE3 1
|
||||
#define SC_P_SCU_BOOT_MODE3_SCU_DSC_RTC_CLOCK_OUTPUT_32K SC_P_SCU_BOOT_MODE3 3
|
||||
#define SC_P_CSI_D00_CI_PI_D02 SC_P_CSI_D00 0
|
||||
#define SC_P_CSI_D00_ADMA_SAI0_RXC SC_P_CSI_D00 2
|
||||
#define SC_P_CSI_D01_CI_PI_D03 SC_P_CSI_D01 0
|
||||
#define SC_P_CSI_D01_ADMA_SAI0_RXD SC_P_CSI_D01 2
|
||||
#define SC_P_CSI_D02_CI_PI_D04 SC_P_CSI_D02 0
|
||||
#define SC_P_CSI_D02_ADMA_SAI0_RXFS SC_P_CSI_D02 2
|
||||
#define SC_P_CSI_D03_CI_PI_D05 SC_P_CSI_D03 0
|
||||
#define SC_P_CSI_D03_ADMA_SAI2_RXC SC_P_CSI_D03 2
|
||||
#define SC_P_CSI_D04_CI_PI_D06 SC_P_CSI_D04 0
|
||||
#define SC_P_CSI_D04_ADMA_SAI2_RXD SC_P_CSI_D04 2
|
||||
#define SC_P_CSI_D05_CI_PI_D07 SC_P_CSI_D05 0
|
||||
#define SC_P_CSI_D05_ADMA_SAI2_RXFS SC_P_CSI_D05 2
|
||||
#define SC_P_CSI_D06_CI_PI_D08 SC_P_CSI_D06 0
|
||||
#define SC_P_CSI_D06_ADMA_SAI3_RXC SC_P_CSI_D06 2
|
||||
#define SC_P_CSI_D07_CI_PI_D09 SC_P_CSI_D07 0
|
||||
#define SC_P_CSI_D07_ADMA_SAI3_RXD SC_P_CSI_D07 2
|
||||
#define SC_P_CSI_HSYNC_CI_PI_HSYNC SC_P_CSI_HSYNC 0
|
||||
#define SC_P_CSI_HSYNC_CI_PI_D00 SC_P_CSI_HSYNC 1
|
||||
#define SC_P_CSI_HSYNC_ADMA_SAI3_RXFS SC_P_CSI_HSYNC 2
|
||||
#define SC_P_CSI_VSYNC_CI_PI_VSYNC SC_P_CSI_VSYNC 0
|
||||
#define SC_P_CSI_VSYNC_CI_PI_D01 SC_P_CSI_VSYNC 1
|
||||
#define SC_P_CSI_PCLK_CI_PI_PCLK SC_P_CSI_PCLK 0
|
||||
#define SC_P_CSI_PCLK_MIPI_CSI0_I2C0_SCL SC_P_CSI_PCLK 1
|
||||
#define SC_P_CSI_PCLK_ADMA_SPI1_SCK SC_P_CSI_PCLK 3
|
||||
#define SC_P_CSI_PCLK_LSIO_GPIO3_IO00 SC_P_CSI_PCLK 4
|
||||
#define SC_P_CSI_MCLK_CI_PI_MCLK SC_P_CSI_MCLK 0
|
||||
#define SC_P_CSI_MCLK_MIPI_CSI0_I2C0_SDA SC_P_CSI_MCLK 1
|
||||
#define SC_P_CSI_MCLK_ADMA_SPI1_SDO SC_P_CSI_MCLK 3
|
||||
#define SC_P_CSI_MCLK_LSIO_GPIO3_IO01 SC_P_CSI_MCLK 4
|
||||
#define SC_P_CSI_EN_CI_PI_EN SC_P_CSI_EN 0
|
||||
#define SC_P_CSI_EN_CI_PI_I2C_SCL SC_P_CSI_EN 1
|
||||
#define SC_P_CSI_EN_ADMA_I2C3_SCL SC_P_CSI_EN 2
|
||||
#define SC_P_CSI_EN_ADMA_SPI1_SDI SC_P_CSI_EN 3
|
||||
#define SC_P_CSI_EN_LSIO_GPIO3_IO02 SC_P_CSI_EN 4
|
||||
#define SC_P_CSI_RESET_CI_PI_RESET SC_P_CSI_RESET 0
|
||||
#define SC_P_CSI_RESET_CI_PI_I2C_SDA SC_P_CSI_RESET 1
|
||||
#define SC_P_CSI_RESET_ADMA_I2C3_SDA SC_P_CSI_RESET 2
|
||||
#define SC_P_CSI_RESET_ADMA_SPI1_CS0 SC_P_CSI_RESET 3
|
||||
#define SC_P_CSI_RESET_LSIO_GPIO3_IO03 SC_P_CSI_RESET 4
|
||||
#define SC_P_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT SC_P_MIPI_CSI0_MCLK_OUT 0
|
||||
#define SC_P_MIPI_CSI0_MCLK_OUT_LSIO_GPIO3_IO04 SC_P_MIPI_CSI0_MCLK_OUT 4
|
||||
#define SC_P_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL SC_P_MIPI_CSI0_I2C0_SCL 0
|
||||
#define SC_P_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_GPIO0_IO02 SC_P_MIPI_CSI0_I2C0_SCL 1
|
||||
#define SC_P_MIPI_CSI0_I2C0_SCL_LSIO_GPIO3_IO05 SC_P_MIPI_CSI0_I2C0_SCL 4
|
||||
#define SC_P_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA SC_P_MIPI_CSI0_I2C0_SDA 0
|
||||
#define SC_P_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_GPIO0_IO03 SC_P_MIPI_CSI0_I2C0_SDA 1
|
||||
#define SC_P_MIPI_CSI0_I2C0_SDA_LSIO_GPIO3_IO06 SC_P_MIPI_CSI0_I2C0_SDA 4
|
||||
#define SC_P_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_IO01 SC_P_MIPI_CSI0_GPIO0_01 0
|
||||
#define SC_P_MIPI_CSI0_GPIO0_01_ADMA_I2C0_SDA SC_P_MIPI_CSI0_GPIO0_01 1
|
||||
#define SC_P_MIPI_CSI0_GPIO0_01_LSIO_GPIO3_IO07 SC_P_MIPI_CSI0_GPIO0_01 4
|
||||
#define SC_P_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_IO00 SC_P_MIPI_CSI0_GPIO0_00 0
|
||||
#define SC_P_MIPI_CSI0_GPIO0_00_ADMA_I2C0_SCL SC_P_MIPI_CSI0_GPIO0_00 1
|
||||
#define SC_P_MIPI_CSI0_GPIO0_00_LSIO_GPIO3_IO08 SC_P_MIPI_CSI0_GPIO0_00 4
|
||||
#define SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 SC_P_QSPI0A_DATA0 0
|
||||
#define SC_P_QSPI0A_DATA0_LSIO_GPIO3_IO09 SC_P_QSPI0A_DATA0 4
|
||||
#define SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 SC_P_QSPI0A_DATA1 0
|
||||
#define SC_P_QSPI0A_DATA1_LSIO_GPIO3_IO10 SC_P_QSPI0A_DATA1 4
|
||||
#define SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 SC_P_QSPI0A_DATA2 0
|
||||
#define SC_P_QSPI0A_DATA2_LSIO_GPIO3_IO11 SC_P_QSPI0A_DATA2 4
|
||||
#define SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 SC_P_QSPI0A_DATA3 0
|
||||
#define SC_P_QSPI0A_DATA3_LSIO_GPIO3_IO12 SC_P_QSPI0A_DATA3 4
|
||||
#define SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS SC_P_QSPI0A_DQS 0
|
||||
#define SC_P_QSPI0A_DQS_LSIO_GPIO3_IO13 SC_P_QSPI0A_DQS 4
|
||||
#define SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B SC_P_QSPI0A_SS0_B 0
|
||||
#define SC_P_QSPI0A_SS0_B_LSIO_GPIO3_IO14 SC_P_QSPI0A_SS0_B 4
|
||||
#define SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B SC_P_QSPI0A_SS1_B 0
|
||||
#define SC_P_QSPI0A_SS1_B_LSIO_GPIO3_IO15 SC_P_QSPI0A_SS1_B 4
|
||||
#define SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK SC_P_QSPI0A_SCLK 0
|
||||
#define SC_P_QSPI0A_SCLK_LSIO_GPIO3_IO16 SC_P_QSPI0A_SCLK 4
|
||||
#define SC_P_QSPI0B_SCLK_LSIO_QSPI0B_SCLK SC_P_QSPI0B_SCLK 0
|
||||
#define SC_P_QSPI0B_SCLK_LSIO_QSPI1A_SCLK SC_P_QSPI0B_SCLK 1
|
||||
#define SC_P_QSPI0B_SCLK_LSIO_KPP0_COL0 SC_P_QSPI0B_SCLK 2
|
||||
#define SC_P_QSPI0B_SCLK_LSIO_GPIO3_IO17 SC_P_QSPI0B_SCLK 4
|
||||
#define SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 SC_P_QSPI0B_DATA0 0
|
||||
#define SC_P_QSPI0B_DATA0_LSIO_QSPI1A_DATA0 SC_P_QSPI0B_DATA0 1
|
||||
#define SC_P_QSPI0B_DATA0_LSIO_KPP0_COL1 SC_P_QSPI0B_DATA0 2
|
||||
#define SC_P_QSPI0B_DATA0_LSIO_GPIO3_IO18 SC_P_QSPI0B_DATA0 4
|
||||
#define SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 SC_P_QSPI0B_DATA1 0
|
||||
#define SC_P_QSPI0B_DATA1_LSIO_QSPI1A_DATA1 SC_P_QSPI0B_DATA1 1
|
||||
#define SC_P_QSPI0B_DATA1_LSIO_KPP0_COL2 SC_P_QSPI0B_DATA1 2
|
||||
#define SC_P_QSPI0B_DATA1_LSIO_GPIO3_IO19 SC_P_QSPI0B_DATA1 4
|
||||
#define SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 SC_P_QSPI0B_DATA2 0
|
||||
#define SC_P_QSPI0B_DATA2_LSIO_QSPI1A_DATA2 SC_P_QSPI0B_DATA2 1
|
||||
#define SC_P_QSPI0B_DATA2_LSIO_KPP0_COL3 SC_P_QSPI0B_DATA2 2
|
||||
#define SC_P_QSPI0B_DATA2_LSIO_GPIO3_IO20 SC_P_QSPI0B_DATA2 4
|
||||
#define SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 SC_P_QSPI0B_DATA3 0
|
||||
#define SC_P_QSPI0B_DATA3_LSIO_QSPI1A_DATA3 SC_P_QSPI0B_DATA3 1
|
||||
#define SC_P_QSPI0B_DATA3_LSIO_KPP0_ROW0 SC_P_QSPI0B_DATA3 2
|
||||
#define SC_P_QSPI0B_DATA3_LSIO_GPIO3_IO21 SC_P_QSPI0B_DATA3 4
|
||||
#define SC_P_QSPI0B_DQS_LSIO_QSPI0B_DQS SC_P_QSPI0B_DQS 0
|
||||
#define SC_P_QSPI0B_DQS_LSIO_QSPI1A_DQS SC_P_QSPI0B_DQS 1
|
||||
#define SC_P_QSPI0B_DQS_LSIO_KPP0_ROW1 SC_P_QSPI0B_DQS 2
|
||||
#define SC_P_QSPI0B_DQS_LSIO_GPIO3_IO22 SC_P_QSPI0B_DQS 4
|
||||
#define SC_P_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B SC_P_QSPI0B_SS0_B 0
|
||||
#define SC_P_QSPI0B_SS0_B_LSIO_QSPI1A_SS0_B SC_P_QSPI0B_SS0_B 1
|
||||
#define SC_P_QSPI0B_SS0_B_LSIO_KPP0_ROW2 SC_P_QSPI0B_SS0_B 2
|
||||
#define SC_P_QSPI0B_SS0_B_LSIO_GPIO3_IO23 SC_P_QSPI0B_SS0_B 4
|
||||
#define SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B SC_P_QSPI0B_SS1_B 0
|
||||
#define SC_P_QSPI0B_SS1_B_LSIO_QSPI1A_SS1_B SC_P_QSPI0B_SS1_B 1
|
||||
#define SC_P_QSPI0B_SS1_B_LSIO_KPP0_ROW3 SC_P_QSPI0B_SS1_B 2
|
||||
#define SC_P_QSPI0B_SS1_B_LSIO_GPIO3_IO24 SC_P_QSPI0B_SS1_B 4
|
||||
|
||||
#endif /* _SC_PADS_H */
|
||||
188
include/dt-bindings/soc/imx8_pd.h
Normal file
188
include/dt-bindings/soc/imx8_pd.h
Normal file
@@ -0,0 +1,188 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2018 NXP
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_IMX8_PD_H
|
||||
#define __DT_BINDINGS_IMX8_PD_H
|
||||
|
||||
/*!
|
||||
* These defines are used to indicate a resource. Resources include peripherals
|
||||
* and bus masters (but not memory regions). Note items from list should
|
||||
* never be changed or removed (only added to at the end of the list).
|
||||
*/
|
||||
#define PD_DC_0 dc0_power_domain
|
||||
#define PD_DC_0_PLL_0 dc0_pll0
|
||||
#define PD_DC_0_PLL_1 dc0_pll1
|
||||
#define PD_LVDS0 lvds0_power_domain
|
||||
#define PD_LVDS0_I2C0 lvds0_i2c0
|
||||
#define PD_LVDS0_I2C1 lvds0_i2c1
|
||||
#define PD_LVDS0_PWM lvds0_pwm
|
||||
#define PD_LVDS0_PWM lvds0_pwm
|
||||
#define PD_LVDS0_GPIO lvds0_gpio
|
||||
#define PD_DC_1 dc1_power_domain
|
||||
#define PD_DC_1_PLL_0 dc1_pll0
|
||||
#define PD_DC_1_PLL_1 dc1_pll1
|
||||
#define PD_LVDS1 lvds1_power_domain
|
||||
#define PD_LVDS1_I2C0 lvds1_i2c0
|
||||
#define PD_LVDS1_I2C1 lvds1_i2c1
|
||||
#define PD_LVDS1_PWM lvds1_pwm
|
||||
#define PD_LVDS1_GPIO lvds1_gpio
|
||||
|
||||
#define PD_DMA dma_power_domain
|
||||
#define PD_DMA_SPI_0 dma_spi0
|
||||
#define PD_DMA_SPI_1 dma_spi1
|
||||
#define PD_DMA_SPI_2 dma_spi2
|
||||
#define PD_DMA_SPI_3 dma_spi3
|
||||
#define PD_DMA_UART0 dma_lpuart0
|
||||
#define PD_DMA_UART1 dma_lpuart1
|
||||
#define PD_DMA_UART2 dma_lpuart2
|
||||
#define PD_DMA_UART3 dma_lpuart3
|
||||
#define PD_DMA_UART4 dma_lpuart4
|
||||
#define PD_DMA_EMVSIM_0 dma_emvsim0
|
||||
#define PD_DMA_EMVSIM_1 dma_emvsim1
|
||||
#define PD_DMA_I2C_0 dma_lpi2c0
|
||||
#define PD_DMA_I2C_1 dma_lpi2c1
|
||||
#define PD_DMA_I2C_2 dma_lpi2c2
|
||||
#define PD_DMA_I2C_3 dma_lpi2c3
|
||||
#define PD_DMA_I2C_4 dma_lpi2c4
|
||||
#define PD_DMA_ADC_0 dma_adc0
|
||||
#define PD_DMA_ADC_1 dma_adc1
|
||||
#define PD_DMA_FTM_0 dma_ftm0
|
||||
#define PD_DMA_FTM_1 dma_ftm1
|
||||
#define PD_DMA_CAN_0 dma_flexcan0
|
||||
#define PD_DMA_CAN_1 dma_flexcan1
|
||||
#define PD_DMA_CAN_2 dma_flexcan2
|
||||
#define PD_DMA_PWM_0 dma_pwm0
|
||||
#define PD_DMA_LCD_0 dma_lcd0
|
||||
|
||||
#define PD_HSIO hsio_power_domain
|
||||
#define PD_HSIO_PCIE_A hsio_pcie0
|
||||
#define PD_HSIO_PCIE_B hsio_pcie1
|
||||
#define PD_HSIO_SATA_0 hsio_sata0
|
||||
#define PD_HSIO_GPIO hsio_gpio
|
||||
|
||||
#define PD_LCD_0 lcd0_power_domain
|
||||
#define PD_LCD_0_I2C_0 lcd0_i2c0
|
||||
#define PD_LCD_0_I2C_1 lcd0_i2c1
|
||||
#define PD_LCD_PWM_0 lcd0_pwm0
|
||||
|
||||
#define PD_LSIO lsio_power_domain
|
||||
#define PD_LSIO_GPIO_0 lsio_gpio0
|
||||
#define PD_LSIO_GPIO_1 lsio_gpio1
|
||||
#define PD_LSIO_GPIO_2 lsio_gpio2
|
||||
#define PD_LSIO_GPIO_3 lsio_gpio3
|
||||
#define PD_LSIO_GPIO_4 lsio_gpio4
|
||||
#define PD_LSIO_GPIO_5 lsio_gpio5
|
||||
#define PD_LSIO_GPIO_6 lsio_gpio6
|
||||
#define PD_LSIO_GPIO_7 lsio_gpio7
|
||||
#define PD_LSIO_GPT_0 lsio_gpt0
|
||||
#define PD_LSIO_GPT_1 lsio_gpt1
|
||||
#define PD_LSIO_GPT_2 lsio_gpt2
|
||||
#define PD_LSIO_GPT_3 lsio_gpt3
|
||||
#define PD_LSIO_GPT_4 lsio_gpt4
|
||||
#define PD_LSIO_KPP lsio_kpp
|
||||
#define PD_LSIO_FSPI_0 lsio_fspi0
|
||||
#define PD_LSIO_FSPI_1 lsio_fspi1
|
||||
#define PD_LSIO_PWM_0 lsio_pwm0
|
||||
#define PD_LSIO_PWM_1 lsio_pwm1
|
||||
#define PD_LSIO_PWM_2 lsio_pwm2
|
||||
#define PD_LSIO_PWM_3 lsio_pwm3
|
||||
#define PD_LSIO_PWM_4 lsio_pwm4
|
||||
#define PD_LSIO_PWM_5 lsio_pwm5
|
||||
#define PD_LSIO_PWM_6 lsio_pwm6
|
||||
#define PD_LSIO_PWM_7 lsio_pwm7
|
||||
|
||||
#define PD_CONN connectivity_power_domain
|
||||
#define PD_CONN_SDHC_0 conn_sdhc0
|
||||
#define PD_CONN_SDHC_1 conn_sdhc1
|
||||
#define PD_CONN_SDHC_2 conn_sdhc2
|
||||
#define PD_CONN_ENET_0 conn_enet0
|
||||
#define PD_CONN_ENET_1 conn_enet1
|
||||
#define PD_CONN_MLB_0 conn_mlb0
|
||||
#define PD_CONN_DMA_4_CH0 conn_dma4_ch0
|
||||
#define PD_CONN_DMA_4_CH1 conn_dma4_ch1
|
||||
#define PD_CONN_DMA_4_CH2 conn_dma4_ch2
|
||||
#define PD_CONN_DMA_4_CH3 conn_dma4_ch3
|
||||
#define PD_CONN_DMA_4_CH4 conn_dma4_ch4
|
||||
#define PD_CONN_USB_0 conn_usb0
|
||||
#define PD_CONN_USB_1 conn_usb1
|
||||
#define PD_CONN_USB_0_PHY conn_usb0_phy
|
||||
#define PD_CONN_USB_2 conn_usb2
|
||||
#define PD_CONN_USB_2_PHY conn_usb2_phy
|
||||
#define PD_CONN_NAND conn_nand
|
||||
|
||||
#define PD_AUDIO audio_power_domain
|
||||
#define PD_AUD_SAI_0 audio_sai0
|
||||
#define PD_AUD_SAI_1 audio_sai1
|
||||
#define PD_AUD_SAI_2 audio_sai2
|
||||
#define PD_AUD_ASRC_0 audio_asrc0
|
||||
#define PD_AUD_ASRC_1 audio_asrc1
|
||||
#define PD_AUD_ESAI_0 audio_esai0
|
||||
#define PD_AUD_ESAI_1 audio_esai1
|
||||
#define PD_AUD_SPDIF_0 audio_spdif0
|
||||
#define PD_AUD_SPDIF_1 audio_spdif1
|
||||
#define PD_AUD_SAI_3 audio_sai3
|
||||
#define PD_AUD_SAI_4 audio_sai4
|
||||
#define PD_AUD_SAI_5 audio_sai5
|
||||
#define PD_AUD_SAI_6 audio_sai6
|
||||
#define PD_AUD_SAI_7 audio_sai7
|
||||
#define PD_AUD_GPT_5 audio_gpt5
|
||||
#define PD_AUD_GPT_6 audio_gpt6
|
||||
#define PD_AUD_GPT_7 audio_gpt7
|
||||
#define PD_AUD_GPT_8 audio_gpt8
|
||||
#define PD_AUD_GPT_9 audio_gpt9
|
||||
#define PD_AUD_GPT_10 audio_gpt10
|
||||
#define PD_AUD_AMIX audio_amix
|
||||
#define PD_AUD_MQS_0 audio_mqs0
|
||||
#define PD_AUD_HIFI audio_hifi
|
||||
#define PD_AUD_OCRAM audio_ocram
|
||||
#define PD_AUD_MCLK_OUT_0 audio_mclkout0
|
||||
#define PD_AUD_MCLK_OUT_1 audio_mclkout1
|
||||
#define PD_AUD_AUDIO_PLL_0 audio_audiopll0
|
||||
#define PD_AUD_AUDIO_PLL_1 audio_audiopll1
|
||||
#define PD_AUD_AUDIO_CLK_0 audio_audioclk0
|
||||
#define PD_AUD_AUDIO_CLK_1 audio_audioclk1
|
||||
|
||||
#define PD_IMAGING imaging_power_domain
|
||||
#define PD_IMAGING_JPEG_DEC imaging_jpeg_dec
|
||||
#define PD_IMAGING_JPEG_ENC imaging_jpeg_enc
|
||||
#define PD_IMAGING_PDMA0 PD_IMAGING
|
||||
#define PD_IMAGING_PDMA1 imaging_pdma1
|
||||
#define PD_IMAGING_PDMA2 imaging_pdma2
|
||||
#define PD_IMAGING_PDMA3 imaging_pdma3
|
||||
#define PD_IMAGING_PDMA4 imaging_pdma4
|
||||
#define PD_IMAGING_PDMA5 imaging_pdma5
|
||||
#define PD_IMAGING_PDMA6 imaging_pdma6
|
||||
#define PD_IMAGING_PDMA7 imaging_pdma7
|
||||
|
||||
#define PD_MIPI_0_DSI mipi0_dsi_power_domain
|
||||
#define PD_MIPI_0_DSI_I2C0 mipi0_dsi_i2c0
|
||||
#define PD_MIPI_0_DSI_I2C1 mipi0_dsi_i2c1
|
||||
#define PD_MIPI_0_DSI_PWM0 mipi0_dsi_pwm0
|
||||
#define PD_MIPI_1_DSI mipi1_dsi_power_domain
|
||||
#define PD_MIPI_1_DSI_I2C0 mipi1_dsi_i2c0
|
||||
#define PD_MIPI_1_DSI_I2C1 mipi1_dsi_i2c1
|
||||
#define PD_MIPI_1_DSI_PWM0 mipi1_dsi_pwm0
|
||||
|
||||
#define PD_MIPI_CSI0 mipi_csi0_power_domain
|
||||
#define PD_MIPI_CSI0_PWM mipi_csi0_pwm
|
||||
#define PD_MIPI_CSI0_I2C mipi_csi0_i2c
|
||||
#define PD_MIPI_CSI1 mipi_csi1_power_domain
|
||||
#define PD_MIPI_CSI1_PWM_0 mipi_csi1_pwm
|
||||
#define PD_MIPI_CSI1_I2C_0 mipi_csi1_i2c
|
||||
|
||||
#define PD_HDMI hdmi_power_domain
|
||||
#define PD_HDMI_I2C_0 hdmi_i2c
|
||||
#define PD_HDMI_PWM_0 hdmi_pwm
|
||||
#define PD_HDMI_GPIO_0 hdmi_gpio
|
||||
|
||||
#define PD_HDMI_RX hdmi_rx_power_domain
|
||||
#define PD_HDMI_RX_I2C hdmi_rx_i2c
|
||||
#define PD_HDMI_RX_PWM hdmi_rx_pwm
|
||||
|
||||
#define PD_CM40 cm40_power_domain
|
||||
#define PD_CM40_I2C cm40_i2c
|
||||
#define PD_CM40_INTMUX cm40_intmux
|
||||
|
||||
#endif /* __DT_BINDINGS_IMX8_PD_H */
|
||||
557
include/dt-bindings/soc/imx_rsrc.h
Normal file
557
include/dt-bindings/soc/imx_rsrc.h
Normal file
@@ -0,0 +1,557 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2018 NXP
|
||||
*/
|
||||
|
||||
#ifndef DT_BINDINGS_RSCRC_IMX_H
|
||||
#define DT_BINDINGS_RSCRC_IMX_H
|
||||
|
||||
/*!
|
||||
* These defines are used to indicate a resource. Resources include peripherals
|
||||
* and bus masters (but not memory regions). Note items from list should
|
||||
* never be changed or removed (only added to at the end of the list).
|
||||
*/
|
||||
#define SC_R_A53 0
|
||||
#define SC_R_A53_0 1
|
||||
#define SC_R_A53_1 2
|
||||
#define SC_R_A53_2 3
|
||||
#define SC_R_A53_3 4
|
||||
#define SC_R_A72 5
|
||||
#define SC_R_A72_0 6
|
||||
#define SC_R_A72_1 7
|
||||
#define SC_R_A72_2 8
|
||||
#define SC_R_A72_3 9
|
||||
#define SC_R_CCI 10
|
||||
#define SC_R_DB 11
|
||||
#define SC_R_DRC_0 12
|
||||
#define SC_R_DRC_1 13
|
||||
#define SC_R_GIC_SMMU 14
|
||||
#define SC_R_IRQSTR_M4_0 15
|
||||
#define SC_R_IRQSTR_M4_1 16
|
||||
#define SC_R_SMMU 17
|
||||
#define SC_R_GIC 18
|
||||
#define SC_R_DC_0_BLIT0 19
|
||||
#define SC_R_DC_0_BLIT1 20
|
||||
#define SC_R_DC_0_BLIT2 21
|
||||
#define SC_R_DC_0_BLIT_OUT 22
|
||||
#define SC_R_DC_0_CAPTURE0 23
|
||||
#define SC_R_DC_0_CAPTURE1 24
|
||||
#define SC_R_DC_0_WARP 25
|
||||
#define SC_R_DC_0_INTEGRAL0 26
|
||||
#define SC_R_DC_0_INTEGRAL1 27
|
||||
#define SC_R_DC_0_VIDEO0 28
|
||||
#define SC_R_DC_0_VIDEO1 29
|
||||
#define SC_R_DC_0_FRAC0 30
|
||||
#define SC_R_DC_0_FRAC1 31
|
||||
#define SC_R_DC_0 32
|
||||
#define SC_R_GPU_2_PID0 33
|
||||
#define SC_R_DC_0_PLL_0 34
|
||||
#define SC_R_DC_0_PLL_1 35
|
||||
#define SC_R_DC_1_BLIT0 36
|
||||
#define SC_R_DC_1_BLIT1 37
|
||||
#define SC_R_DC_1_BLIT2 38
|
||||
#define SC_R_DC_1_BLIT_OUT 39
|
||||
#define SC_R_DC_1_CAPTURE0 40
|
||||
#define SC_R_DC_1_CAPTURE1 41
|
||||
#define SC_R_DC_1_WARP 42
|
||||
#define SC_R_DC_1_INTEGRAL0 43
|
||||
#define SC_R_DC_1_INTEGRAL1 44
|
||||
#define SC_R_DC_1_VIDEO0 45
|
||||
#define SC_R_DC_1_VIDEO1 46
|
||||
#define SC_R_DC_1_FRAC0 47
|
||||
#define SC_R_DC_1_FRAC1 48
|
||||
#define SC_R_DC_1 49
|
||||
#define SC_R_GPU_3_PID0 50
|
||||
#define SC_R_DC_1_PLL_0 51
|
||||
#define SC_R_DC_1_PLL_1 52
|
||||
#define SC_R_SPI_0 53
|
||||
#define SC_R_SPI_1 54
|
||||
#define SC_R_SPI_2 55
|
||||
#define SC_R_SPI_3 56
|
||||
#define SC_R_UART_0 57
|
||||
#define SC_R_UART_1 58
|
||||
#define SC_R_UART_2 59
|
||||
#define SC_R_UART_3 60
|
||||
#define SC_R_UART_4 61
|
||||
#define SC_R_EMVSIM_0 62
|
||||
#define SC_R_EMVSIM_1 63
|
||||
#define SC_R_DMA_0_CH0 64
|
||||
#define SC_R_DMA_0_CH1 65
|
||||
#define SC_R_DMA_0_CH2 66
|
||||
#define SC_R_DMA_0_CH3 67
|
||||
#define SC_R_DMA_0_CH4 68
|
||||
#define SC_R_DMA_0_CH5 69
|
||||
#define SC_R_DMA_0_CH6 70
|
||||
#define SC_R_DMA_0_CH7 71
|
||||
#define SC_R_DMA_0_CH8 72
|
||||
#define SC_R_DMA_0_CH9 73
|
||||
#define SC_R_DMA_0_CH10 74
|
||||
#define SC_R_DMA_0_CH11 75
|
||||
#define SC_R_DMA_0_CH12 76
|
||||
#define SC_R_DMA_0_CH13 77
|
||||
#define SC_R_DMA_0_CH14 78
|
||||
#define SC_R_DMA_0_CH15 79
|
||||
#define SC_R_DMA_0_CH16 80
|
||||
#define SC_R_DMA_0_CH17 81
|
||||
#define SC_R_DMA_0_CH18 82
|
||||
#define SC_R_DMA_0_CH19 83
|
||||
#define SC_R_DMA_0_CH20 84
|
||||
#define SC_R_DMA_0_CH21 85
|
||||
#define SC_R_DMA_0_CH22 86
|
||||
#define SC_R_DMA_0_CH23 87
|
||||
#define SC_R_DMA_0_CH24 88
|
||||
#define SC_R_DMA_0_CH25 89
|
||||
#define SC_R_DMA_0_CH26 90
|
||||
#define SC_R_DMA_0_CH27 91
|
||||
#define SC_R_DMA_0_CH28 92
|
||||
#define SC_R_DMA_0_CH29 93
|
||||
#define SC_R_DMA_0_CH30 94
|
||||
#define SC_R_DMA_0_CH31 95
|
||||
#define SC_R_I2C_0 96
|
||||
#define SC_R_I2C_1 97
|
||||
#define SC_R_I2C_2 98
|
||||
#define SC_R_I2C_3 99
|
||||
#define SC_R_I2C_4 100
|
||||
#define SC_R_ADC_0 101
|
||||
#define SC_R_ADC_1 102
|
||||
#define SC_R_FTM_0 103
|
||||
#define SC_R_FTM_1 104
|
||||
#define SC_R_CAN_0 105
|
||||
#define SC_R_CAN_1 106
|
||||
#define SC_R_CAN_2 107
|
||||
#define SC_R_DMA_1_CH0 108
|
||||
#define SC_R_DMA_1_CH1 109
|
||||
#define SC_R_DMA_1_CH2 110
|
||||
#define SC_R_DMA_1_CH3 111
|
||||
#define SC_R_DMA_1_CH4 112
|
||||
#define SC_R_DMA_1_CH5 113
|
||||
#define SC_R_DMA_1_CH6 114
|
||||
#define SC_R_DMA_1_CH7 115
|
||||
#define SC_R_DMA_1_CH8 116
|
||||
#define SC_R_DMA_1_CH9 117
|
||||
#define SC_R_DMA_1_CH10 118
|
||||
#define SC_R_DMA_1_CH11 119
|
||||
#define SC_R_DMA_1_CH12 120
|
||||
#define SC_R_DMA_1_CH13 121
|
||||
#define SC_R_DMA_1_CH14 122
|
||||
#define SC_R_DMA_1_CH15 123
|
||||
#define SC_R_DMA_1_CH16 124
|
||||
#define SC_R_DMA_1_CH17 125
|
||||
#define SC_R_DMA_1_CH18 126
|
||||
#define SC_R_DMA_1_CH19 127
|
||||
#define SC_R_DMA_1_CH20 128
|
||||
#define SC_R_DMA_1_CH21 129
|
||||
#define SC_R_DMA_1_CH22 130
|
||||
#define SC_R_DMA_1_CH23 131
|
||||
#define SC_R_DMA_1_CH24 132
|
||||
#define SC_R_DMA_1_CH25 133
|
||||
#define SC_R_DMA_1_CH26 134
|
||||
#define SC_R_DMA_1_CH27 135
|
||||
#define SC_R_DMA_1_CH28 136
|
||||
#define SC_R_DMA_1_CH29 137
|
||||
#define SC_R_DMA_1_CH30 138
|
||||
#define SC_R_DMA_1_CH31 139
|
||||
#define SC_R_UNUSED1 140
|
||||
#define SC_R_UNUSED2 141
|
||||
#define SC_R_UNUSED3 142
|
||||
#define SC_R_UNUSED4 143
|
||||
#define SC_R_GPU_0_PID0 144
|
||||
#define SC_R_GPU_0_PID1 145
|
||||
#define SC_R_GPU_0_PID2 146
|
||||
#define SC_R_GPU_0_PID3 147
|
||||
#define SC_R_GPU_1_PID0 148
|
||||
#define SC_R_GPU_1_PID1 149
|
||||
#define SC_R_GPU_1_PID2 150
|
||||
#define SC_R_GPU_1_PID3 151
|
||||
#define SC_R_PCIE_A 152
|
||||
#define SC_R_SERDES_0 153
|
||||
#define SC_R_MATCH_0 154
|
||||
#define SC_R_MATCH_1 155
|
||||
#define SC_R_MATCH_2 156
|
||||
#define SC_R_MATCH_3 157
|
||||
#define SC_R_MATCH_4 158
|
||||
#define SC_R_MATCH_5 159
|
||||
#define SC_R_MATCH_6 160
|
||||
#define SC_R_MATCH_7 161
|
||||
#define SC_R_MATCH_8 162
|
||||
#define SC_R_MATCH_9 163
|
||||
#define SC_R_MATCH_10 164
|
||||
#define SC_R_MATCH_11 165
|
||||
#define SC_R_MATCH_12 166
|
||||
#define SC_R_MATCH_13 167
|
||||
#define SC_R_MATCH_14 168
|
||||
#define SC_R_PCIE_B 169
|
||||
#define SC_R_SATA_0 170
|
||||
#define SC_R_SERDES_1 171
|
||||
#define SC_R_HSIO_GPIO 172
|
||||
#define SC_R_MATCH_15 173
|
||||
#define SC_R_MATCH_16 174
|
||||
#define SC_R_MATCH_17 175
|
||||
#define SC_R_MATCH_18 176
|
||||
#define SC_R_MATCH_19 177
|
||||
#define SC_R_MATCH_20 178
|
||||
#define SC_R_MATCH_21 179
|
||||
#define SC_R_MATCH_22 180
|
||||
#define SC_R_MATCH_23 181
|
||||
#define SC_R_MATCH_24 182
|
||||
#define SC_R_MATCH_25 183
|
||||
#define SC_R_MATCH_26 184
|
||||
#define SC_R_MATCH_27 185
|
||||
#define SC_R_MATCH_28 186
|
||||
#define SC_R_LCD_0 187
|
||||
#define SC_R_LCD_0_PWM_0 188
|
||||
#define SC_R_LCD_0_I2C_0 189
|
||||
#define SC_R_LCD_0_I2C_1 190
|
||||
#define SC_R_PWM_0 191
|
||||
#define SC_R_PWM_1 192
|
||||
#define SC_R_PWM_2 193
|
||||
#define SC_R_PWM_3 194
|
||||
#define SC_R_PWM_4 195
|
||||
#define SC_R_PWM_5 196
|
||||
#define SC_R_PWM_6 197
|
||||
#define SC_R_PWM_7 198
|
||||
#define SC_R_GPIO_0 199
|
||||
#define SC_R_GPIO_1 200
|
||||
#define SC_R_GPIO_2 201
|
||||
#define SC_R_GPIO_3 202
|
||||
#define SC_R_GPIO_4 203
|
||||
#define SC_R_GPIO_5 204
|
||||
#define SC_R_GPIO_6 205
|
||||
#define SC_R_GPIO_7 206
|
||||
#define SC_R_GPT_0 207
|
||||
#define SC_R_GPT_1 208
|
||||
#define SC_R_GPT_2 209
|
||||
#define SC_R_GPT_3 210
|
||||
#define SC_R_GPT_4 211
|
||||
#define SC_R_KPP 212
|
||||
#define SC_R_MU_0A 213
|
||||
#define SC_R_MU_1A 214
|
||||
#define SC_R_MU_2A 215
|
||||
#define SC_R_MU_3A 216
|
||||
#define SC_R_MU_4A 217
|
||||
#define SC_R_MU_5A 218
|
||||
#define SC_R_MU_6A 219
|
||||
#define SC_R_MU_7A 220
|
||||
#define SC_R_MU_8A 221
|
||||
#define SC_R_MU_9A 222
|
||||
#define SC_R_MU_10A 223
|
||||
#define SC_R_MU_11A 224
|
||||
#define SC_R_MU_12A 225
|
||||
#define SC_R_MU_13A 226
|
||||
#define SC_R_MU_5B 227
|
||||
#define SC_R_MU_6B 228
|
||||
#define SC_R_MU_7B 229
|
||||
#define SC_R_MU_8B 230
|
||||
#define SC_R_MU_9B 231
|
||||
#define SC_R_MU_10B 232
|
||||
#define SC_R_MU_11B 233
|
||||
#define SC_R_MU_12B 234
|
||||
#define SC_R_MU_13B 235
|
||||
#define SC_R_ROM_0 236
|
||||
#define SC_R_FSPI_0 237
|
||||
#define SC_R_FSPI_1 238
|
||||
#define SC_R_IEE 239
|
||||
#define SC_R_IEE_R0 240
|
||||
#define SC_R_IEE_R1 241
|
||||
#define SC_R_IEE_R2 242
|
||||
#define SC_R_IEE_R3 243
|
||||
#define SC_R_IEE_R4 244
|
||||
#define SC_R_IEE_R5 245
|
||||
#define SC_R_IEE_R6 246
|
||||
#define SC_R_IEE_R7 247
|
||||
#define SC_R_SDHC_0 248
|
||||
#define SC_R_SDHC_1 249
|
||||
#define SC_R_SDHC_2 250
|
||||
#define SC_R_ENET_0 251
|
||||
#define SC_R_ENET_1 252
|
||||
#define SC_R_MLB_0 253
|
||||
#define SC_R_DMA_2_CH0 254
|
||||
#define SC_R_DMA_2_CH1 255
|
||||
#define SC_R_DMA_2_CH2 256
|
||||
#define SC_R_DMA_2_CH3 257
|
||||
#define SC_R_DMA_2_CH4 258
|
||||
#define SC_R_USB_0 259
|
||||
#define SC_R_USB_1 260
|
||||
#define SC_R_USB_0_PHY 261
|
||||
#define SC_R_USB_2 262
|
||||
#define SC_R_USB_2_PHY 263
|
||||
#define SC_R_DTCP 264
|
||||
#define SC_R_NAND 265
|
||||
#define SC_R_LVDS_0 266
|
||||
#define SC_R_LVDS_0_PWM_0 267
|
||||
#define SC_R_LVDS_0_I2C_0 268
|
||||
#define SC_R_LVDS_0_I2C_1 269
|
||||
#define SC_R_LVDS_1 270
|
||||
#define SC_R_LVDS_1_PWM_0 271
|
||||
#define SC_R_LVDS_1_I2C_0 272
|
||||
#define SC_R_LVDS_1_I2C_1 273
|
||||
#define SC_R_LVDS_2 274
|
||||
#define SC_R_LVDS_2_PWM_0 275
|
||||
#define SC_R_LVDS_2_I2C_0 276
|
||||
#define SC_R_LVDS_2_I2C_1 277
|
||||
#define SC_R_M4_0_PID0 278
|
||||
#define SC_R_M4_0_PID1 279
|
||||
#define SC_R_M4_0_PID2 280
|
||||
#define SC_R_M4_0_PID3 281
|
||||
#define SC_R_M4_0_PID4 282
|
||||
#define SC_R_M4_0_RGPIO 283
|
||||
#define SC_R_M4_0_SEMA42 284
|
||||
#define SC_R_M4_0_TPM 285
|
||||
#define SC_R_M4_0_PIT 286
|
||||
#define SC_R_M4_0_UART 287
|
||||
#define SC_R_M4_0_I2C 288
|
||||
#define SC_R_M4_0_INTMUX 289
|
||||
#define SC_R_M4_0_SIM 290
|
||||
#define SC_R_M4_0_WDOG 291
|
||||
#define SC_R_M4_0_MU_0B 292
|
||||
#define SC_R_M4_0_MU_0A0 293
|
||||
#define SC_R_M4_0_MU_0A1 294
|
||||
#define SC_R_M4_0_MU_0A2 295
|
||||
#define SC_R_M4_0_MU_0A3 296
|
||||
#define SC_R_M4_0_MU_1A 297
|
||||
#define SC_R_M4_1_PID0 298
|
||||
#define SC_R_M4_1_PID1 299
|
||||
#define SC_R_M4_1_PID2 300
|
||||
#define SC_R_M4_1_PID3 301
|
||||
#define SC_R_M4_1_PID4 302
|
||||
#define SC_R_M4_1_RGPIO 303
|
||||
#define SC_R_M4_1_SEMA42 304
|
||||
#define SC_R_M4_1_TPM 305
|
||||
#define SC_R_M4_1_PIT 306
|
||||
#define SC_R_M4_1_UART 307
|
||||
#define SC_R_M4_1_I2C 308
|
||||
#define SC_R_M4_1_INTMUX 309
|
||||
#define SC_R_M4_1_SIM 310
|
||||
#define SC_R_M4_1_WDOG 311
|
||||
#define SC_R_M4_1_MU_0B 312
|
||||
#define SC_R_M4_1_MU_0A0 313
|
||||
#define SC_R_M4_1_MU_0A1 314
|
||||
#define SC_R_M4_1_MU_0A2 315
|
||||
#define SC_R_M4_1_MU_0A3 316
|
||||
#define SC_R_M4_1_MU_1A 317
|
||||
#define SC_R_SAI_0 318
|
||||
#define SC_R_SAI_1 319
|
||||
#define SC_R_SAI_2 320
|
||||
#define SC_R_IRQSTR_SCU2 321
|
||||
#define SC_R_IRQSTR_DSP 322
|
||||
#define SC_R_UNUSED5 323
|
||||
#define SC_R_OCRAM 324
|
||||
#define SC_R_AUDIO_PLL_0 325
|
||||
#define SC_R_PI_0 326
|
||||
#define SC_R_PI_0_PWM_0 327
|
||||
#define SC_R_PI_0_PWM_1 328
|
||||
#define SC_R_PI_0_I2C_0 329
|
||||
#define SC_R_PI_0_PLL 330
|
||||
#define SC_R_PI_1 331
|
||||
#define SC_R_PI_1_PWM_0 332
|
||||
#define SC_R_PI_1_PWM_1 333
|
||||
#define SC_R_PI_1_I2C_0 334
|
||||
#define SC_R_PI_1_PLL 335
|
||||
#define SC_R_SC_PID0 336
|
||||
#define SC_R_SC_PID1 337
|
||||
#define SC_R_SC_PID2 338
|
||||
#define SC_R_SC_PID3 339
|
||||
#define SC_R_SC_PID4 340
|
||||
#define SC_R_SC_SEMA42 341
|
||||
#define SC_R_SC_TPM 342
|
||||
#define SC_R_SC_PIT 343
|
||||
#define SC_R_SC_UART 344
|
||||
#define SC_R_SC_I2C 345
|
||||
#define SC_R_SC_MU_0B 346
|
||||
#define SC_R_SC_MU_0A0 347
|
||||
#define SC_R_SC_MU_0A1 348
|
||||
#define SC_R_SC_MU_0A2 349
|
||||
#define SC_R_SC_MU_0A3 350
|
||||
#define SC_R_SC_MU_1A 351
|
||||
#define SC_R_SYSCNT_RD 352
|
||||
#define SC_R_SYSCNT_CMP 353
|
||||
#define SC_R_DEBUG 354
|
||||
#define SC_R_SYSTEM 355
|
||||
#define SC_R_SNVS 356
|
||||
#define SC_R_OTP 357
|
||||
#define SC_R_VPU_PID0 358
|
||||
#define SC_R_VPU_PID1 359
|
||||
#define SC_R_VPU_PID2 360
|
||||
#define SC_R_VPU_PID3 361
|
||||
#define SC_R_VPU_PID4 362
|
||||
#define SC_R_VPU_PID5 363
|
||||
#define SC_R_VPU_PID6 364
|
||||
#define SC_R_VPU_PID7 365
|
||||
#define SC_R_VPU_UART 366
|
||||
#define SC_R_VPUCORE 367
|
||||
#define SC_R_VPUCORE_0 368
|
||||
#define SC_R_VPUCORE_1 369
|
||||
#define SC_R_VPUCORE_2 370
|
||||
#define SC_R_VPUCORE_3 371
|
||||
#define SC_R_DMA_4_CH0 372
|
||||
#define SC_R_DMA_4_CH1 373
|
||||
#define SC_R_DMA_4_CH2 374
|
||||
#define SC_R_DMA_4_CH3 375
|
||||
#define SC_R_DMA_4_CH4 376
|
||||
#define SC_R_ISI_CH0 377
|
||||
#define SC_R_ISI_CH1 378
|
||||
#define SC_R_ISI_CH2 379
|
||||
#define SC_R_ISI_CH3 380
|
||||
#define SC_R_ISI_CH4 381
|
||||
#define SC_R_ISI_CH5 382
|
||||
#define SC_R_ISI_CH6 383
|
||||
#define SC_R_ISI_CH7 384
|
||||
#define SC_R_MJPEG_DEC_S0 385
|
||||
#define SC_R_MJPEG_DEC_S1 386
|
||||
#define SC_R_MJPEG_DEC_S2 387
|
||||
#define SC_R_MJPEG_DEC_S3 388
|
||||
#define SC_R_MJPEG_ENC_S0 389
|
||||
#define SC_R_MJPEG_ENC_S1 390
|
||||
#define SC_R_MJPEG_ENC_S2 391
|
||||
#define SC_R_MJPEG_ENC_S3 392
|
||||
#define SC_R_MIPI_0 393
|
||||
#define SC_R_MIPI_0_PWM_0 394
|
||||
#define SC_R_MIPI_0_I2C_0 395
|
||||
#define SC_R_MIPI_0_I2C_1 396
|
||||
#define SC_R_MIPI_1 397
|
||||
#define SC_R_MIPI_1_PWM_0 398
|
||||
#define SC_R_MIPI_1_I2C_0 399
|
||||
#define SC_R_MIPI_1_I2C_1 400
|
||||
#define SC_R_CSI_0 401
|
||||
#define SC_R_CSI_0_PWM_0 402
|
||||
#define SC_R_CSI_0_I2C_0 403
|
||||
#define SC_R_CSI_1 404
|
||||
#define SC_R_CSI_1_PWM_0 405
|
||||
#define SC_R_CSI_1_I2C_0 406
|
||||
#define SC_R_HDMI 407
|
||||
#define SC_R_HDMI_I2S 408
|
||||
#define SC_R_HDMI_I2C_0 409
|
||||
#define SC_R_HDMI_PLL_0 410
|
||||
#define SC_R_HDMI_RX 411
|
||||
#define SC_R_HDMI_RX_BYPASS 412
|
||||
#define SC_R_HDMI_RX_I2C_0 413
|
||||
#define SC_R_ASRC_0 414
|
||||
#define SC_R_ESAI_0 415
|
||||
#define SC_R_SPDIF_0 416
|
||||
#define SC_R_SPDIF_1 417
|
||||
#define SC_R_SAI_3 418
|
||||
#define SC_R_SAI_4 419
|
||||
#define SC_R_SAI_5 420
|
||||
#define SC_R_GPT_5 421
|
||||
#define SC_R_GPT_6 422
|
||||
#define SC_R_GPT_7 423
|
||||
#define SC_R_GPT_8 424
|
||||
#define SC_R_GPT_9 425
|
||||
#define SC_R_GPT_10 426
|
||||
#define SC_R_DMA_2_CH5 427
|
||||
#define SC_R_DMA_2_CH6 428
|
||||
#define SC_R_DMA_2_CH7 429
|
||||
#define SC_R_DMA_2_CH8 430
|
||||
#define SC_R_DMA_2_CH9 431
|
||||
#define SC_R_DMA_2_CH10 432
|
||||
#define SC_R_DMA_2_CH11 433
|
||||
#define SC_R_DMA_2_CH12 434
|
||||
#define SC_R_DMA_2_CH13 435
|
||||
#define SC_R_DMA_2_CH14 436
|
||||
#define SC_R_DMA_2_CH15 437
|
||||
#define SC_R_DMA_2_CH16 438
|
||||
#define SC_R_DMA_2_CH17 439
|
||||
#define SC_R_DMA_2_CH18 440
|
||||
#define SC_R_DMA_2_CH19 441
|
||||
#define SC_R_DMA_2_CH20 442
|
||||
#define SC_R_DMA_2_CH21 443
|
||||
#define SC_R_DMA_2_CH22 444
|
||||
#define SC_R_DMA_2_CH23 445
|
||||
#define SC_R_DMA_2_CH24 446
|
||||
#define SC_R_DMA_2_CH25 447
|
||||
#define SC_R_DMA_2_CH26 448
|
||||
#define SC_R_DMA_2_CH27 449
|
||||
#define SC_R_DMA_2_CH28 450
|
||||
#define SC_R_DMA_2_CH29 451
|
||||
#define SC_R_DMA_2_CH30 452
|
||||
#define SC_R_DMA_2_CH31 453
|
||||
#define SC_R_ASRC_1 454
|
||||
#define SC_R_ESAI_1 455
|
||||
#define SC_R_SAI_6 456
|
||||
#define SC_R_SAI_7 457
|
||||
#define SC_R_AMIX 458
|
||||
#define SC_R_MQS_0 459
|
||||
#define SC_R_DMA_3_CH0 460
|
||||
#define SC_R_DMA_3_CH1 461
|
||||
#define SC_R_DMA_3_CH2 462
|
||||
#define SC_R_DMA_3_CH3 463
|
||||
#define SC_R_DMA_3_CH4 464
|
||||
#define SC_R_DMA_3_CH5 465
|
||||
#define SC_R_DMA_3_CH6 466
|
||||
#define SC_R_DMA_3_CH7 467
|
||||
#define SC_R_DMA_3_CH8 468
|
||||
#define SC_R_DMA_3_CH9 469
|
||||
#define SC_R_DMA_3_CH10 470
|
||||
#define SC_R_DMA_3_CH11 471
|
||||
#define SC_R_DMA_3_CH12 472
|
||||
#define SC_R_DMA_3_CH13 473
|
||||
#define SC_R_DMA_3_CH14 474
|
||||
#define SC_R_DMA_3_CH15 475
|
||||
#define SC_R_DMA_3_CH16 476
|
||||
#define SC_R_DMA_3_CH17 477
|
||||
#define SC_R_DMA_3_CH18 478
|
||||
#define SC_R_DMA_3_CH19 479
|
||||
#define SC_R_DMA_3_CH20 480
|
||||
#define SC_R_DMA_3_CH21 481
|
||||
#define SC_R_DMA_3_CH22 482
|
||||
#define SC_R_DMA_3_CH23 483
|
||||
#define SC_R_DMA_3_CH24 484
|
||||
#define SC_R_DMA_3_CH25 485
|
||||
#define SC_R_DMA_3_CH26 486
|
||||
#define SC_R_DMA_3_CH27 487
|
||||
#define SC_R_DMA_3_CH28 488
|
||||
#define SC_R_DMA_3_CH29 489
|
||||
#define SC_R_DMA_3_CH30 490
|
||||
#define SC_R_DMA_3_CH31 491
|
||||
#define SC_R_AUDIO_PLL_1 492
|
||||
#define SC_R_AUDIO_CLK_0 493
|
||||
#define SC_R_AUDIO_CLK_1 494
|
||||
#define SC_R_MCLK_OUT_0 495
|
||||
#define SC_R_MCLK_OUT_1 496
|
||||
#define SC_R_PMIC_0 497
|
||||
#define SC_R_PMIC_1 498
|
||||
#define SC_R_SECO 499
|
||||
#define SC_R_CAAM_JR1 500
|
||||
#define SC_R_CAAM_JR2 501
|
||||
#define SC_R_CAAM_JR3 502
|
||||
#define SC_R_SECO_MU_2 503
|
||||
#define SC_R_SECO_MU_3 504
|
||||
#define SC_R_SECO_MU_4 505
|
||||
#define SC_R_HDMI_RX_PWM_0 506
|
||||
#define SC_R_A35 507
|
||||
#define SC_R_A35_0 508
|
||||
#define SC_R_A35_1 509
|
||||
#define SC_R_A35_2 510
|
||||
#define SC_R_A35_3 511
|
||||
#define SC_R_DSP 512
|
||||
#define SC_R_DSP_RAM 513
|
||||
#define SC_R_CAAM_JR1_OUT 514
|
||||
#define SC_R_CAAM_JR2_OUT 515
|
||||
#define SC_R_CAAM_JR3_OUT 516
|
||||
#define SC_R_VPU_DEC_0 517
|
||||
#define SC_R_VPU_ENC_0 518
|
||||
#define SC_R_CAAM_JR0 519
|
||||
#define SC_R_CAAM_JR0_OUT 520
|
||||
#define SC_R_PMIC_2 521
|
||||
#define SC_R_DBLOGIC 522
|
||||
#define SC_R_HDMI_PLL_1 523
|
||||
#define SC_R_BOARD_R0 524
|
||||
#define SC_R_BOARD_R1 525
|
||||
#define SC_R_BOARD_R2 526
|
||||
#define SC_R_BOARD_R3 527
|
||||
#define SC_R_BOARD_R4 528
|
||||
#define SC_R_BOARD_R5 529
|
||||
#define SC_R_BOARD_R6 530
|
||||
#define SC_R_BOARD_R7 531
|
||||
#define SC_R_MJPEG_DEC_MP 532
|
||||
#define SC_R_MJPEG_ENC_MP 533
|
||||
#define SC_R_VPU_TS_0 534
|
||||
#define SC_R_VPU_MU_0 535
|
||||
#define SC_R_VPU_MU_1 536
|
||||
#define SC_R_VPU_MU_2 537
|
||||
#define SC_R_VPU_MU_3 538
|
||||
#define SC_R_VPU_ENC_1 539
|
||||
#define SC_R_VPU 540
|
||||
#define SC_R_LAST 541
|
||||
|
||||
#endif /* DT_BINDINGS_RSCRC_IMX_H */
|
||||
@@ -4,7 +4,7 @@
|
||||
*
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_ARCH_MX7ULP
|
||||
#if defined(CONFIG_ARCH_MX7ULP) || defined(CONFIG_ARCH_IMX8)
|
||||
struct lpuart_fsl_reg32 {
|
||||
u32 verid;
|
||||
u32 param;
|
||||
|
||||
@@ -251,6 +251,7 @@ enum {
|
||||
IH_TYPE_FLATDT, /* Binary Flat Device Tree Blob */
|
||||
IH_TYPE_KWBIMAGE, /* Kirkwood Boot Image */
|
||||
IH_TYPE_IMXIMAGE, /* Freescale IMXBoot Image */
|
||||
IH_TYPE_IMX8IMAGE, /* Freescale IMX8Boot Image */
|
||||
IH_TYPE_UBLIMAGE, /* Davinci UBL Image */
|
||||
IH_TYPE_OMAPIMAGE, /* TI OMAP Config Header Image */
|
||||
IH_TYPE_AISIMAGE, /* TI Davinci AIS Image */
|
||||
|
||||
273
include/imx8image.h
Normal file
273
include/imx8image.h
Normal file
@@ -0,0 +1,273 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2018 NXP
|
||||
*
|
||||
* Peng Fan <peng.fan@nxp.com>
|
||||
*/
|
||||
|
||||
#ifndef _IMX8IMAGE_H_
|
||||
#define _IMX8IMAGE_H_
|
||||
|
||||
#include <image.h>
|
||||
#include <inttypes.h>
|
||||
#include "imagetool.h"
|
||||
#include "linux/kernel.h"
|
||||
|
||||
#define __packed __attribute__((packed))
|
||||
|
||||
#define IV_MAX_LEN 32
|
||||
#define HASH_MAX_LEN 64
|
||||
#define MAX_NUM_IMGS 6
|
||||
#define MAX_NUM_SRK_RECORDS 4
|
||||
|
||||
#define IVT_HEADER_TAG_B0 0x87
|
||||
#define IVT_VERSION_B0 0x00
|
||||
|
||||
#define IMG_FLAG_HASH_SHA256 0x000
|
||||
#define IMG_FLAG_HASH_SHA384 0x100
|
||||
#define IMG_FLAG_HASH_SHA512 0x200
|
||||
|
||||
#define IMG_FLAG_ENCRYPTED_MASK 0x400
|
||||
#define IMG_FLAG_ENCRYPTED_SHIFT 0x0A
|
||||
|
||||
#define IMG_FLAG_BOOTFLAGS_MASK 0xFFFF0000
|
||||
#define IMG_FLAG_BOOTFLAGS_SHIFT 0x10
|
||||
|
||||
#define IMG_ARRAY_ENTRY_SIZE 128
|
||||
#define HEADER_IMG_ARRAY_OFFSET 0x10
|
||||
|
||||
#define HASH_TYPE_SHA_256 256
|
||||
#define HASH_TYPE_SHA_384 384
|
||||
#define HASH_TYPE_SHA_512 512
|
||||
|
||||
#define IMAGE_HASH_ALGO_DEFAULT 384
|
||||
#define IMAGE_PADDING_DEFAULT 0x1000
|
||||
|
||||
#define DCD_ENTRY_ADDR_IN_SCFW 0x240
|
||||
|
||||
#define CONTAINER_ALIGNMENT 0x400
|
||||
#define CONTAINER_FLAGS_DEFAULT 0x10
|
||||
#define CONTAINER_FUSE_DEFAULT 0x0
|
||||
|
||||
#define SIGNATURE_BLOCK_HEADER_LENGTH 0x10
|
||||
|
||||
#define MAX_NUM_OF_CONTAINER 2
|
||||
|
||||
#define FIRST_CONTAINER_HEADER_LENGTH 0x400
|
||||
|
||||
#define BOOT_IMG_META_MU_RID_SHIFT 10
|
||||
#define BOOT_IMG_META_PART_ID_SHIFT 20
|
||||
|
||||
#define IMAGE_A35_DEFAULT_META(PART) (((PART == 0) ? \
|
||||
PARTITION_ID_AP : PART) << \
|
||||
BOOT_IMG_META_PART_ID_SHIFT | \
|
||||
SC_R_MU_0A << \
|
||||
BOOT_IMG_META_MU_RID_SHIFT | \
|
||||
SC_R_A35_0)
|
||||
|
||||
#define IMAGE_A53_DEFAULT_META(PART) (((PART == 0) ? \
|
||||
PARTITION_ID_AP : PART) << \
|
||||
BOOT_IMG_META_PART_ID_SHIFT | \
|
||||
SC_R_MU_0A << \
|
||||
BOOT_IMG_META_MU_RID_SHIFT | \
|
||||
SC_R_A53_0)
|
||||
|
||||
#define IMAGE_A72_DEFAULT_META(PART) (((PART == 0) ? \
|
||||
PARTITION_ID_AP : PART) << \
|
||||
BOOT_IMG_META_PART_ID_SHIFT | \
|
||||
SC_R_MU_0A << \
|
||||
BOOT_IMG_META_MU_RID_SHIFT | \
|
||||
SC_R_A72_0)
|
||||
|
||||
#define IMAGE_M4_0_DEFAULT_META(PART) (((PART == 0) ? \
|
||||
PARTITION_ID_M4 : PART) << \
|
||||
BOOT_IMG_META_PART_ID_SHIFT | \
|
||||
SC_R_M4_0_MU_1A << \
|
||||
BOOT_IMG_META_MU_RID_SHIFT | \
|
||||
SC_R_M4_0_PID0)
|
||||
|
||||
#define IMAGE_M4_1_DEFAULT_META(PART) (((PART == 0) ? \
|
||||
PARTITION_ID_M4 : PART) << \
|
||||
BOOT_IMG_META_PART_ID_SHIFT | \
|
||||
SC_R_M4_1_MU_1A << \
|
||||
BOOT_IMG_META_MU_RID_SHIFT | \
|
||||
SC_R_M4_1_PID0)
|
||||
|
||||
#define CONTAINER_IMAGE_ARRAY_START_OFFSET 0x2000
|
||||
|
||||
typedef struct {
|
||||
uint8_t version;
|
||||
uint16_t length;
|
||||
uint8_t tag;
|
||||
uint16_t srk_table_offset;
|
||||
uint16_t cert_offset;
|
||||
uint16_t blob_offset;
|
||||
uint16_t signature_offset;
|
||||
uint32_t reserved;
|
||||
} __packed sig_blk_hdr_t;
|
||||
|
||||
typedef struct {
|
||||
uint32_t offset;
|
||||
uint32_t size;
|
||||
uint64_t dst;
|
||||
uint64_t entry;
|
||||
uint32_t hab_flags;
|
||||
uint32_t meta;
|
||||
uint8_t hash[HASH_MAX_LEN];
|
||||
uint8_t iv[IV_MAX_LEN];
|
||||
} __packed boot_img_t;
|
||||
|
||||
typedef struct {
|
||||
uint8_t version;
|
||||
uint16_t length;
|
||||
uint8_t tag;
|
||||
uint32_t flags;
|
||||
uint16_t sw_version;
|
||||
uint8_t fuse_version;
|
||||
uint8_t num_images;
|
||||
uint16_t sig_blk_offset;
|
||||
uint16_t reserved;
|
||||
boot_img_t img[MAX_NUM_IMGS];
|
||||
sig_blk_hdr_t sig_blk_hdr;
|
||||
uint32_t sigblk_size;
|
||||
uint32_t padding;
|
||||
} __packed flash_header_v3_t;
|
||||
|
||||
typedef struct {
|
||||
flash_header_v3_t fhdr[MAX_NUM_OF_CONTAINER];
|
||||
} __packed imx_header_v3_t;
|
||||
|
||||
struct image_array {
|
||||
char *name;
|
||||
unsigned int core_type;
|
||||
unsigned int core_id;
|
||||
unsigned int load_addr;
|
||||
};
|
||||
|
||||
enum imx8image_cmd {
|
||||
CMD_INVALID,
|
||||
CMD_BOOT_FROM,
|
||||
CMD_FUSE_VERSION,
|
||||
CMD_SW_VERSION,
|
||||
CMD_MSG_BLOCK,
|
||||
CMD_FILEOFF,
|
||||
CMD_FLAG,
|
||||
CMD_APPEND,
|
||||
CMD_PARTITION,
|
||||
CMD_SOC_TYPE,
|
||||
CMD_CONTAINER,
|
||||
CMD_IMAGE,
|
||||
CMD_DATA
|
||||
};
|
||||
|
||||
enum imx8image_core_type {
|
||||
CFG_CORE_INVALID,
|
||||
CFG_SCU,
|
||||
CFG_M40,
|
||||
CFG_M41,
|
||||
CFG_A35,
|
||||
CFG_A53,
|
||||
CFG_A72
|
||||
};
|
||||
|
||||
enum imx8image_fld_types {
|
||||
CFG_INVALID = -1,
|
||||
CFG_COMMAND,
|
||||
CFG_CORE_TYPE,
|
||||
CFG_IMAGE_NAME,
|
||||
CFG_LOAD_ADDR
|
||||
};
|
||||
|
||||
typedef enum SOC_TYPE {
|
||||
NONE = 0,
|
||||
QX,
|
||||
QM
|
||||
} soc_type_t;
|
||||
|
||||
typedef enum option_type {
|
||||
NO_IMG = 0,
|
||||
DCD,
|
||||
SCFW,
|
||||
SECO,
|
||||
M40,
|
||||
M41,
|
||||
AP,
|
||||
OUTPUT,
|
||||
SCD,
|
||||
CSF,
|
||||
FLAG,
|
||||
DEVICE,
|
||||
NEW_CONTAINER,
|
||||
APPEND,
|
||||
DATA,
|
||||
PARTITION,
|
||||
FILEOFF,
|
||||
MSG_BLOCK
|
||||
} option_type_t;
|
||||
|
||||
typedef struct {
|
||||
option_type_t option;
|
||||
char *filename;
|
||||
uint64_t src;
|
||||
uint64_t dst;
|
||||
uint64_t entry;
|
||||
uint64_t ext;
|
||||
} image_t;
|
||||
|
||||
#define CORE_SC 1
|
||||
#define CORE_CM4_0 2
|
||||
#define CORE_CM4_1 3
|
||||
#define CORE_CA53 4
|
||||
#define CORE_CA35 4
|
||||
#define CORE_CA72 5
|
||||
#define CORE_SECO 6
|
||||
|
||||
#define SC_R_OTP 357U
|
||||
#define SC_R_DEBUG 354U
|
||||
#define SC_R_ROM_0 236U
|
||||
|
||||
#define MSG_DEBUG_EN SC_R_DEBUG
|
||||
#define MSG_FUSE SC_R_OTP
|
||||
#define MSG_FIELD SC_R_ROM_0
|
||||
|
||||
#define IMG_TYPE_CSF 0x01 /* CSF image type */
|
||||
#define IMG_TYPE_SCD 0x02 /* SCD image type */
|
||||
#define IMG_TYPE_EXEC 0x03 /* Executable image type */
|
||||
#define IMG_TYPE_DATA 0x04 /* Data image type */
|
||||
#define IMG_TYPE_DCD_DDR 0x05 /* DCD/DDR image type */
|
||||
#define IMG_TYPE_SECO 0x06 /* SECO image type */
|
||||
#define IMG_TYPE_PROV 0x07 /* Provisioning image type */
|
||||
#define IMG_TYPE_DEK 0x08 /* DEK validation type */
|
||||
|
||||
#define IMG_TYPE_SHIFT 0
|
||||
#define IMG_TYPE_MASK 0x1f
|
||||
#define IMG_TYPE(x) (((x) & IMG_TYPE_MASK) >> IMG_TYPE_SHIFT)
|
||||
|
||||
#define BOOT_IMG_FLAGS_CORE_MASK 0xF
|
||||
#define BOOT_IMG_FLAGS_CORE_SHIFT 0x04
|
||||
#define BOOT_IMG_FLAGS_CPU_RID_MASK 0x3FF0
|
||||
#define BOOT_IMG_FLAGS_CPU_RID_SHIFT 4
|
||||
#define BOOT_IMG_FLAGS_MU_RID_MASK 0xFFC000
|
||||
#define BOOT_IMG_FLAGS_MU_RID_SHIFT 14
|
||||
#define BOOT_IMG_FLAGS_PARTITION_ID_MASK 0x1F000000
|
||||
#define BOOT_IMG_FLAGS_PARTITION_ID_SHIFT 24
|
||||
|
||||
/* Resource id used in scfw */
|
||||
#define SC_R_A35_0 508
|
||||
#define SC_R_A53_0 1
|
||||
#define SC_R_A72_0 6
|
||||
#define SC_R_MU_0A 213
|
||||
#define SC_R_M4_0_PID0 278
|
||||
#define SC_R_M4_0_MU_1A 297
|
||||
#define SC_R_M4_1_PID0 298
|
||||
#define SC_R_M4_1_MU_1A 317
|
||||
#define PARTITION_ID_M4 0
|
||||
#define PARTITION_ID_AP 1
|
||||
|
||||
#define IMG_STACK_SIZE 32
|
||||
|
||||
#define append(p, s, l) do { \
|
||||
memcpy((p), (uint8_t *)(s), (l)); (p) += (l); \
|
||||
} while (0)
|
||||
|
||||
#endif
|
||||
Reference in New Issue
Block a user