common: Drop linux/bitops.h from common header

Move this uncommon header out of the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>

include/acpi/acpi_table.h

@@ -13,6 +13,8 @@
 #ifndef __ACPI_TABLE_H__
 #define __ACPI_TABLE_H__
 
+#include <linux/bitops.h>
+
 #define RSDP_SIG		"RSD PTR "	/* RSDP pointer signature */
 #define OEM_ID			"U-BOOT"	/* U-Boot */
 #define OEM_TABLE_ID		"U-BOOTBL"	/* U-Boot Table */

include/asm-generic/gpio.h

@@ -8,6 +8,7 @@
 #define _ASM_GENERIC_GPIO_H_
 
 #include <dm/ofnode.h>
+#include <linux/bitops.h>
 
 struct ofnode_phandle_args;
 

include/bitfield.h

@@ -36,6 +36,7 @@
  * tables which describe all bitfields in all registers.
  */
 
+#include <linux/bitops.h>
 #include <linux/types.h>
 
 /* Produces a mask of set bits covering a range of a uint value */

include/common.h

@@ -16,7 +16,6 @@
 #include <config.h>
 #include <errno.h>
 #include <time.h>
-#include <linux/bitops.h>
 #include <linux/types.h>
 #include <linux/printk.h>
 #include <linux/string.h>

include/configs/gardena-smart-gateway-at91sam.h

@@ -9,6 +9,10 @@
 #ifndef __CONFIG_H__
 #define __CONFIG_H__
 
+#ifndef __ASSEMBLY__
+#include <linux/bitops.h>
+#endif
+
 /* ARM asynchronous clock */
 #define CONFIG_SYS_AT91_SLOW_CLOCK	32768
 #define CONFIG_SYS_AT91_MAIN_CLOCK	12000000	/* 12 MHz crystal */

include/dma.h

@@ -9,6 +9,7 @@
 #ifndef _DMA_H_
 #define _DMA_H_
 
+#include <linux/bitops.h>
 #include <linux/errno.h>
 #include <linux/types.h>
 

include/dwc3-sti-glue.h

@@ -8,6 +8,7 @@
 #define __DWC3_STI_UBOOT_H_
 
 /* glue registers */
+#include <linux/bitops.h>
 #define CLKRST_CTRL		0x00
 #define AUX_CLK_EN		BIT(0)
 #define SW_PIPEW_RESET_N	BIT(4)

include/dwmmc.h

@@ -10,6 +10,7 @@
 #include <asm/cache.h>
 #include <asm/io.h>
 #include <mmc.h>
+#include <linux/bitops.h>
 
 #define DWMCI_CTRL		0x000
 #define	DWMCI_PWREN		0x004

include/faraday/ftpci100.h

@@ -11,6 +11,7 @@
 #define __FTPCI100_H
 
 /* AHB Control Registers */
+#include <linux/bitops.h>
 struct ftpci100_ahbc {
 	unsigned int iosize;		/* 0x00 - I/O Space Size Signal */
 	unsigned int prot;		/* 0x04 - AHB Protection */

include/faraday/ftsdc010.h

@@ -12,6 +12,7 @@
 #ifndef __ASSEMBLY__
 
 /* sd controller register */
+#include <linux/bitops.h>
 struct ftsdc010_mmc {
 	unsigned int	cmd;		/* 0x00 - command reg		*/
 	unsigned int	argu;		/* 0x04 - argument reg		*/

include/faraday/ftsdmc021.h

@@ -14,6 +14,7 @@
 #define __FTSDMC021_H
 
 #ifndef __ASSEMBLY__
+#include <linux/bitops.h>
 struct ftsdmc021 {
 	unsigned int	tp1;		/* 0x00 - SDRAM Timing Parameter 1 */
 	unsigned int	tp2;		/* 0x04 - SDRAM Timing Parameter 2 */

include/fsl-mc/fsl_mc.h

@@ -7,6 +7,7 @@
 #define __FSL_MC_H__
 
 #include <common.h>
+#include <linux/bitops.h>
 
 #define MC_CCSR_BASE_ADDR \
 	((struct mc_ccsr_registers __iomem *)0x8340000)

include/linux/bitops.h

@@ -1,6 +1,8 @@
 #ifndef _LINUX_BITOPS_H
 #define _LINUX_BITOPS_H
 
+#ifndef USE_HOSTCC
+
 #include <asm/types.h>
 #include <asm-generic/bitsperlong.h>
 #include <linux/compiler.h>
@@ -216,4 +218,6 @@ static inline void generic_clear_bit(int nr, volatile unsigned long *addr)
 	*p &= ~mask;
 }
 
+#endif /* !USE_HOSTCC */
+
 #endif

include/linux/soc/ti/k3-navss-ringacc.h

@@ -9,6 +9,7 @@
 #define __SOC_TI_K3_NAVSS_RINGACC_API_H_
 
 #include <dm/ofnode.h>
+#include <linux/bitops.h>
 
 /**
  * enum k3_nav_ring_mode - &struct k3_nav_ring_cfg mode

include/linux/soc/ti/ti_sci_protocol.h

@@ -20,6 +20,7 @@
  * @firmware_revision:	Firmware revision (not usually used).
  * @firmware_description: Firmware description (not usually used).
  */
+#include <linux/bitops.h>
 struct ti_sci_version_info {
 	u8 abi_major;
 	u8 abi_minor;

include/mipi_dsi.h

@@ -16,6 +16,7 @@
 #define MIPI_DSI_H
 
 #include <mipi_display.h>
+#include <linux/bitops.h>
 
 struct mipi_dsi_host;
 struct mipi_dsi_device;

include/mmc.h

@@ -9,6 +9,7 @@
 #ifndef _MMC_H_
 #define _MMC_H_
 
+#include <linux/bitops.h>
 #include <linux/list.h>
 #include <linux/sizes.h>
 #include <linux/compiler.h>

include/net/pfe_eth/pfe/cbus/class_csr.h

@@ -12,6 +12,7 @@
  * class_csr - block containing all the classifier control and status register.
  * Mapped on CBUS and accessible from all PE's and ARM.
  */
+#include <linux/bitops.h>
 #define CLASS_VERSION			(CLASS_CSR_BASE_ADDR + 0x000)
 #define CLASS_TX_CTRL			(CLASS_CSR_BASE_ADDR + 0x004)
 #define CLASS_INQ_PKTPTR		(CLASS_CSR_BASE_ADDR + 0x010)

include/net/pfe_eth/pfe/cbus/emac.h

@@ -7,6 +7,7 @@
 #ifndef _EMAC_H_
 #define _EMAC_H_
 
+#include <linux/bitops.h>
 #define EMAC_IEVENT_REG		0x004
 #define EMAC_IMASK_REG		0x008
 #define EMAC_R_DES_ACTIVE_REG	0x010

include/net/pfe_eth/pfe/cbus/hif.h

@@ -12,6 +12,7 @@
  * hif - PFE hif block control and status register.
  * Mapped on CBUS and accessible from all PE's and ARM.
  */
+#include <linux/bitops.h>
 #define HIF_VERSION		(HIF_BASE_ADDR + 0x00)
 #define HIF_TX_CTRL		(HIF_BASE_ADDR + 0x04)
 #define HIF_TX_CURR_BD_ADDR	(HIF_BASE_ADDR + 0x08)

include/net/pfe_eth/pfe/cbus/tmu_csr.h

@@ -7,6 +7,7 @@
 #ifndef _TMU_CSR_H_
 #define _TMU_CSR_H_
 
+#include <linux/bitops.h>
 #define TMU_VERSION			(TMU_CSR_BASE_ADDR + 0x000)
 #define TMU_INQ_WATERMARK		(TMU_CSR_BASE_ADDR + 0x004)
 #define TMU_PHY_INQ_PKTPTR		(TMU_CSR_BASE_ADDR + 0x008)

include/net/pfe_eth/pfe/pfe_hw.h

@@ -8,6 +8,7 @@
 #define _PFE_H_
 
 #include <elf.h>
+#include <linux/bitops.h>
 #include "cbus.h"
 
 #define PFE_RESET_WA

include/net/pfe_eth/pfe_eth.h

@@ -7,6 +7,7 @@
 #ifndef __PFE_ETH_H__
 #define __PFE_ETH_H__
 
+#include <linux/bitops.h>
 #include <linux/sizes.h>
 #include <asm/io.h>
 #include <miiphy.h>

include/pch.h

@@ -7,6 +7,7 @@
 #ifndef __pch_h
 #define __pch_h
 
+#include <linux/bitops.h>
 #define PCH_RCBA		0xf0
 
 #define BIOS_CTRL_BIOSWE	BIT(0)

include/power/stpmic1.h

@@ -6,6 +6,7 @@
 #ifndef __PMIC_STPMIC1_H_
 #define __PMIC_STPMIC1_H_
 
+#include <linux/bitops.h>
 #define STPMIC1_MAIN_CR			0x10
 #define STPMIC1_BUCKS_MRST_CR		0x18
 #define STPMIC1_LDOS_MRST_CR		0x1a

include/sdhci.h

@@ -9,6 +9,7 @@
 #ifndef __SDHCI_HW_H
 #define __SDHCI_HW_H
 
+#include <linux/bitops.h>
 #include <linux/types.h>
 #include <asm/io.h>
 #include <mmc.h>

include/spi.h

@@ -10,6 +10,7 @@
 #define _SPI_H_
 
 #include <common.h>
+#include <linux/bitops.h>
 
 /* SPI mode flags */
 #define SPI_CPHA	BIT(0)			/* clock phase */

include/tee.h

@@ -6,6 +6,7 @@
 #ifndef __TEE_H
 #define __TEE_H
 
+#include <linux/bitops.h>
 #define TEE_UUID_LEN		16
 
 #define TEE_GEN_CAP_GP          BIT(0)	/* GlobalPlatform compliant TEE */

include/tpm-v1.h

@@ -8,6 +8,7 @@
 #define __TPM_V1_H
 
 #include <tpm-common.h>
+#include <linux/bitops.h>
 
 /* Useful constants */
 enum {

include/virtio.h

@@ -20,6 +20,7 @@
 #ifndef __VIRTIO_H__
 #define __VIRTIO_H__
 
+#include <linux/bitops.h>
 #include <linux/bug.h>
 #define VIRTIO_ID_NET		1 /* virtio net */
 #define VIRTIO_ID_BLOCK		2 /* virtio block */

include/vsc9953.h

@@ -11,6 +11,7 @@
 #include <config.h>
 #include <miiphy.h>
 #include <asm/types.h>
+#include <linux/bitops.h>
 
 #define VSC9953_OFFSET			(CONFIG_SYS_CCSRBAR_DEFAULT + 0x800000)
 

include/zynqmppl.h

@@ -8,6 +8,7 @@
 #define _ZYNQMPPL_H_
 
 #include <xilinx.h>
+#include <linux/bitops.h>
 
 #define ZYNQMP_SIP_SVC_CSU_DMA_CHIPID		0xC2000018
 #define ZYNQMP_SIP_SVC_PM_FPGA_LOAD		0xC2000016