* Patch by Laurent Mohin, 10 Feb 2004:
Fix buffer overflow in common/usb.c * Patch by Tolunay Orkun, 10 Feb 2004: Add support for Cogent CSB272 board * Code cleanup
This commit is contained in:
wdenk
@@ -1,5 +1,4 @@
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/*
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* include/asm-armnommu/arch-netarm/netarm_dma_module.h
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/* * include/asm-armnommu/arch-netarm/netarm_dma_module.h
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*
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* Copyright (C) 2000 NETsilicon, Inc.
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* Copyright (C) 2000 WireSpeed Communications Corporation
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@@ -181,4 +180,3 @@ typedef struct __NETARM_DMA_Buff_Desc_M_to_M
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#endif
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#endif
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@@ -34,32 +34,32 @@
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/* GEN unit register offsets */
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#define NETARM_GEN_MODULE_BASE (0xFFB00000)
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#define NETARM_GEN_MODULE_BASE (0xFFB00000)
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#define get_gen_reg_addr(c) ((volatile unsigned int *)(NETARM_GEN_MODULE_BASE + (c)))
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#define NETARM_GEN_SYSTEM_CONTROL (0x00)
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#define NETARM_GEN_STATUS_CONTROL (0x04)
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#define NETARM_GEN_PLL_CONTROL (0x08)
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#define NETARM_GEN_SOFTWARE_SERVICE (0x0c)
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#define NETARM_GEN_SYSTEM_CONTROL (0x00)
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#define NETARM_GEN_STATUS_CONTROL (0x04)
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#define NETARM_GEN_PLL_CONTROL (0x08)
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#define NETARM_GEN_SOFTWARE_SERVICE (0x0c)
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#define NETARM_GEN_TIMER1_CONTROL (0x10)
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#define NETARM_GEN_TIMER1_STATUS (0x14)
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#define NETARM_GEN_TIMER2_CONTROL (0x18)
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#define NETARM_GEN_TIMER2_STATUS (0x1c)
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#define NETARM_GEN_TIMER1_CONTROL (0x10)
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#define NETARM_GEN_TIMER1_STATUS (0x14)
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#define NETARM_GEN_TIMER2_CONTROL (0x18)
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#define NETARM_GEN_TIMER2_STATUS (0x1c)
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#define NETARM_GEN_PORTA (0x20)
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#define NETARM_GEN_PORTB (0x24)
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#define NETARM_GEN_PORTC (0x28)
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#define NETARM_GEN_PORTA (0x20)
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#define NETARM_GEN_PORTB (0x24)
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#define NETARM_GEN_PORTC (0x28)
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#define NETARM_GEN_INTR_ENABLE (0x30)
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#define NETARM_GEN_INTR_ENABLE_SET (0x34)
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#define NETARM_GEN_INTR_ENABLE_CLR (0x38)
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#define NETARM_GEN_INTR_STATUS_EN (0x34)
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#define NETARM_GEN_INTR_STATUS_RAW (0x38)
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#define NETARM_GEN_INTR_ENABLE (0x30)
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#define NETARM_GEN_INTR_ENABLE_SET (0x34)
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#define NETARM_GEN_INTR_ENABLE_CLR (0x38)
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#define NETARM_GEN_INTR_STATUS_EN (0x34)
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#define NETARM_GEN_INTR_STATUS_RAW (0x38)
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#define NETARM_GEN_CACHE_CONTROL1 (0x40)
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#define NETARM_GEN_CACHE_CONTROL2 (0x44)
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#define NETARM_GEN_CACHE_CONTROL1 (0x40)
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#define NETARM_GEN_CACHE_CONTROL2 (0x44)
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/* select bitfield definitions */
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@@ -72,7 +72,7 @@
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#define NETARM_GEN_SYS_CFG_BUSHALF (0x20000000)
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#define NETARM_GEN_SYS_CFG_BUSFULL (0x40000000)
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#define NETARM_GEN_SYS_CFG_BCLK_DISABLE (0x10000000)
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#define NETARM_GEN_SYS_CFG_BCLK_DISABLE (0x10000000)
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#define NETARM_GEN_SYS_CFG_WDOG_EN (0x01000000)
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#define NETARM_GEN_SYS_CFG_WDOG_IRQ (0x00000000)
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@@ -112,57 +112,57 @@
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#define NETARM_GEN_PLL_CTL_PLLCNT_MASK (0x0F000000)
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#define NETARM_GEN_PLL_CTL_PLLCNT(x) (((x)<<24) & \
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NETARM_GEN_PLL_CTL_PLLCNT_MASK)
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NETARM_GEN_PLL_CTL_PLLCNT_MASK)
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/* Defaults for POLTST and ICP Fields in PLL CTL */
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#define NETARM_GEN_PLL_CTL_OUTDIV(x) (x)
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#define NETARM_GEN_PLL_CTL_INDIV(x) ((x)<<6)
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#define NETARM_GEN_PLL_CTL_POLTST_DEF (0x00000E00)
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#define NETARM_GEN_PLL_CTL_ICP_DEF (0x0000003C)
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#define NETARM_GEN_PLL_CTL_OUTDIV(x) (x)
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#define NETARM_GEN_PLL_CTL_INDIV(x) ((x)<<6)
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#define NETARM_GEN_PLL_CTL_POLTST_DEF (0x00000E00)
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#define NETARM_GEN_PLL_CTL_ICP_DEF (0x0000003C)
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/* Software Service Register ( 0xFFB0_000C ) */
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#define NETARM_GEN_SW_SVC_RESETA (0x123)
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#define NETARM_GEN_SW_SVC_RESETB (0x321)
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#define NETARM_GEN_SW_SVC_RESETA (0x123)
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#define NETARM_GEN_SW_SVC_RESETB (0x321)
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/* PORT C Register ( 0xFFB0_0028 ) */
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#define NETARM_GEN_PORT_MODE(x) (((x)<<24) + (0xFF00))
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#define NETARM_GEN_PORT_DIR(x) (((x)<<16) + (0xFF00))
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#define NETARM_GEN_PORT_MODE(x) (((x)<<24) + (0xFF00))
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#define NETARM_GEN_PORT_DIR(x) (((x)<<16) + (0xFF00))
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/* Timer Registers ( 0xFFB0_0010 0xFFB0_0018 ) */
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#define NETARM_GEN_TCTL_ENABLE (0x80000000)
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#define NETARM_GEN_TCTL_INT_ENABLE (0x40000000)
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#define NETARM_GEN_TCTL_ENABLE (0x80000000)
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#define NETARM_GEN_TCTL_INT_ENABLE (0x40000000)
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#define NETARM_GEN_TCTL_USE_IRQ (0x00000000)
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#define NETARM_GEN_TCTL_USE_FIQ (0x20000000)
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#define NETARM_GEN_TCTL_USE_IRQ (0x00000000)
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#define NETARM_GEN_TCTL_USE_FIQ (0x20000000)
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#define NETARM_GEN_TCTL_USE_PRESCALE (0x10000000)
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#define NETARM_GEN_TCTL_INIT_COUNT(x) ((x) & 0x1FF)
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#define NETARM_GEN_TCTL_USE_PRESCALE (0x10000000)
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#define NETARM_GEN_TCTL_INIT_COUNT(x) ((x) & 0x1FF)
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#define NETARM_GEN_TSTAT_INTPEN (0x40000000)
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#define NETARM_GEN_TSTAT_CTC_MASK (0x000001FF)
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#define NETARM_GEN_TSTAT_INTPEN (0x40000000)
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#define NETARM_GEN_TSTAT_CTC_MASK (0x000001FF)
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/* prescale to msecs conversion */
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#define NETARM_GEN_TIMER_MSEC_P(x) ( ( ( 20480 ) * ( 0x1FF - ( (x) & \
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NETARM_GEN_TSTAT_CTC_MASK ) + \
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#define NETARM_GEN_TIMER_MSEC_P(x) ( ( ( 20480 ) * ( 0x1FF - ( (x) & \
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NETARM_GEN_TSTAT_CTC_MASK ) + \
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1 ) ) / (NETARM_XTAL_FREQ/1000) )
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#define NETARM_GEN_TIMER_SET_HZ(x) ( ( ((NETARM_XTAL_FREQ/(20480*(x)))-1) & \
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#define NETARM_GEN_TIMER_SET_HZ(x) ( ( ((NETARM_XTAL_FREQ/(20480*(x)))-1) & \
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NETARM_GEN_TSTAT_CTC_MASK ) | \
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NETARM_GEN_TCTL_USE_PRESCALE )
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#if 0
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/* ifdef CONFIG_NETARM_PLL_BYPASS else */
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#error test
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#define NETARM_GEN_TIMER_MSEC_P(x) ( ( ( 4096 ) * ( 0x1FF - ( (x) & \
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NETARM_GEN_TSTAT_CTC_MASK ) + \
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#define NETARM_GEN_TIMER_MSEC_P(x) ( ( ( 4096 ) * ( 0x1FF - ( (x) & \
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NETARM_GEN_TSTAT_CTC_MASK ) + \
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1 ) ) / (NETARM_XTAL_FREQ/1000) )
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#define NETARM_GEN_TIMER_SET_HZ(x) ( ( ((NETARM_XTAL_FREQ/(4096*(x)))-1) & \
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#define NETARM_GEN_TIMER_SET_HZ(x) ( ( ((NETARM_XTAL_FREQ/(4096*(x)))-1) & \
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NETARM_GEN_TSTAT_CTC_MASK ) | \
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NETARM_GEN_TCTL_USE_PRESCALE )
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#endif
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@@ -155,4 +155,3 @@
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#define NETARM_MEM_OPT_WRITE_SYNC (0x00000001)
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#endif
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@@ -77,4 +77,3 @@
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#include <asm/arch/netarm_eth_module.h>
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#endif
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@@ -18,7 +18,7 @@ unsigned short bmp_logo_palette[] = {
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0x0343, 0x0454, 0x0565, 0x0565, 0x0676, 0x0787, 0x0898, 0x0999,
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0x0AAA, 0x0ABA, 0x0BCB, 0x0CCC, 0x0DDD, 0x0EEE, 0x0FFF, 0x0FB3,
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0x0FB4, 0x0FC4, 0x0FC5, 0x0FC6, 0x0FD7, 0x0FD8, 0x0FD9, 0x0FDA,
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0x0FEA, 0x0FEB, 0x0FEC, 0x0FFD, 0x0FFE, 0x0FFF, 0x0FFF,
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0x0FEA, 0x0FEB, 0x0FEC, 0x0FFD, 0x0FFE, 0x0FFF, 0x0FFF,
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};
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unsigned char bmp_logo_bitmap[] = {
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313
include/configs/csb272.h
Normal file
313
include/configs/csb272.h
Normal file
@@ -0,0 +1,313 @@
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/*
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* (C) Copyright 2004
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* Tolunay Orkun, Nextio Inc., torkun@nextio.com
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* board/config.h - configuration options, board specific
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_405GP 1 /* This is a PPC405GP CPU */
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#define CONFIG_4xx 1 /* ...member of PPC4xx family */
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#define CONFIG_CSB272 1 /* on a Cogent CSB272 board */
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#define CONFIG_BOARD_PRE_INIT 1 /* Call board_pre_init() */
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#define CONFIG_LAST_STAGE_INIT 1 /* Call last_stage_init() */
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#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
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/*
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* OS Bootstrap configuration
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*
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*/
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#if 0
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#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
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#else
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#define CONFIG_BOOTDELAY 3 /* autoboot after X seconds */
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#endif
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#define CONFIG_ZERO_BOOTDELAY_CHECK /* check keypress when bootdelay = 0 */
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#if 1
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#undef CONFIG_BOOTARGS
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#define CONFIG_BOOTCOMMAND \
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"setenv bootargs console=ttyS0,38400 debug " \
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"root=/dev/ram rw ramdisk_size=4096 " \
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"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
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"bootm fe000000 fe100000"
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#endif
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#if 0
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#undef CONFIG_BOOTARGS
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#define CONFIG_BOOTCOMMAND \
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"bootp; " \
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"setenv bootargs console=ttyS0,38400 debug " \
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"root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
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"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
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"bootm"
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#endif
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/*
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* BOOTP/DHCP protocol configuration
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*
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*/
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#define CONFIG_BOOTP_MASK ( CONFIG_BOOTP_DEFAULT | \
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CONFIG_BOOTP_DNS2 | \
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CONFIG_BOOTP_BOOTFILESIZE )
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/*
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* U-Boot Monitor Command Line Functions Configuration
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*
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*/
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#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
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CFG_CMD_ASKENV | \
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CFG_CMD_BEDBUG | \
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CFG_CMD_ELF | \
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CFG_CMD_IRQ | \
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CFG_CMD_I2C | \
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CFG_CMD_PCI | \
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CFG_CMD_DATE | \
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CFG_CMD_MII | \
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CFG_CMD_PING | \
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CFG_CMD_DHCP )
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/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
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#include <cmd_confdefs.h>
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/*
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* Serial download configuration
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*
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*/
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
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/*
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* KGDB Configuration
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*
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*/
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
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#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
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#endif
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/*
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* Miscellaneous configurable options
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*
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*/
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#undef CFG_HUSH_PARSER /* use "hush" command parser */
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#ifdef CFG_HUSH_PARSER
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#define CFG_PROMPT_HUSH_PS2 "> " /* hush shell secondary prompt */
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#endif
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#define CFG_LONGHELP /* undef to save memory */
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#define CFG_PROMPT "=> " /* Monitor Command Prompt */
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
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#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
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#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
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#define CFG_CLKS_IN_HZ 1 /* everything, incl board info, in Hz */
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#define CFG_EXTBDINFO 1 /* To use extended board_info (bd_t) */
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#define CFG_LOAD_ADDR 0x100000 /* default load address */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
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|
||||
/*
|
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* watchdog configuration
|
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*
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*/
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */
|
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|
||||
/*
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||||
* UART configuration
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||||
*
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||||
*/
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#define CFG_EXT_SERIAL_CLOCK 3868400 /* use external serial clock */
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#undef CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */
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#undef CFG_BASE_BAUD
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#define CONFIG_BAUDRATE 38400 /* Default baud rate */
|
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#define CFG_BAUDRATE_TABLE \
|
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{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400 }
|
||||
|
||||
/*
|
||||
* I2C configuration
|
||||
*
|
||||
*/
|
||||
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
|
||||
#define CFG_I2C_SPEED 100000 /* I2C speed */
|
||||
#define CFG_I2C_SLAVE 0x7F /* I2C slave address */
|
||||
|
||||
/*
|
||||
* MII PHY configuration
|
||||
*
|
||||
*/
|
||||
#define CONFIG_MII 1 /* MII PHY management */
|
||||
#define CONFIG_PHY_ADDR 0 /* PHY address */
|
||||
#define CONFIG_PHY_CMD_DELAY 40 /* PHY COMMAND delay */
|
||||
/* 32usec min. for LXT971A */
|
||||
#define CONFIG_PHY_RESET_DELAY 300 /* PHY RESET recovery delay */
|
||||
|
||||
/*
|
||||
* RTC configuration
|
||||
*
|
||||
* Note that DS1307 RTC is limited to 100Khz I2C bus.
|
||||
*
|
||||
*/
|
||||
#define CONFIG_RTC_DS1307 /* Use Dallas 1307 RTC */
|
||||
|
||||
/*
|
||||
* PCI stuff
|
||||
*
|
||||
*/
|
||||
#define CONFIG_PCI /* include pci support */
|
||||
#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
|
||||
#define PCI_HOST_FORCE 1 /* configure as pci host */
|
||||
#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
|
||||
|
||||
#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
|
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */
|
||||
/* resource configuration */
|
||||
#undef CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
|
||||
#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/
|
||||
|
||||
#define CFG_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */
|
||||
#define CFG_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */
|
||||
#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
|
||||
#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
|
||||
#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
|
||||
#define CFG_PCI_PTM2LA 0x00000000 /* disabled */
|
||||
#define CFG_PCI_PTM2MS 0x00000000 /* disabled */
|
||||
#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
|
||||
|
||||
/*
|
||||
* IDE stuff
|
||||
*
|
||||
*/
|
||||
#undef CONFIG_IDE_PCMCIA /* no pcmcia interface required */
|
||||
#undef CONFIG_IDE_LED /* no led for ide supported */
|
||||
#undef CONFIG_IDE_RESET /* no reset for ide supported */
|
||||
|
||||
/*
|
||||
* Environment configuration
|
||||
*
|
||||
*/
|
||||
#define CFG_ENV_IS_IN_FLASH 1 /* environment is in FLASH */
|
||||
#undef CFG_ENV_IS_IN_NVRAM
|
||||
#undef CFG_ENV_IS_IN_EEPROM
|
||||
|
||||
/*
|
||||
* General Memory organization
|
||||
*
|
||||
* Start addresses for the final memory configuration
|
||||
* (Set up by the startup code)
|
||||
* Please note that CFG_SDRAM_BASE _must_ start at 0
|
||||
*/
|
||||
#define CFG_SDRAM_BASE 0x00000000
|
||||
#define CFG_FLASH_BASE 0xFE000000
|
||||
#define CFG_FLASH_SIZE 0x02000000
|
||||
#define CFG_MONITOR_BASE TEXT_BASE
|
||||
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 KB for Monitor */
|
||||
#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 KB for malloc() */
|
||||
|
||||
#if CFG_MONITOR_BASE < CFG_FLASH_BASE
|
||||
#define CFG_RAMSTART
|
||||
#endif
|
||||
|
||||
#if defined(CFG_ENV_IS_IN_FLASH)
|
||||
#define CFG_ENV_IN_OWN_SECTOR 1 /* Give Environment own sector */
|
||||
#define CFG_ENV_ADDR 0xFFF00000 /* Address of Environment Sector */
|
||||
#define CFG_ENV_SIZE 0x00001000 /* Size of Environment */
|
||||
#define CFG_ENV_SECT_SIZE 0x00040000 /* Size of Environment Sector */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* FLASH Device configuration
|
||||
*
|
||||
*/
|
||||
#define CFG_FLASH_CFI 1 /* flash is CFI conformant */
|
||||
#define CFG_FLASH_CFI_DRIVER 1 /* use common cfi driver */
|
||||
#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
|
||||
#define CFG_MAX_FLASH_BANKS 1 /* max # of memory banks */
|
||||
#define CFG_FLASH_INCREMENT 0 /* there is only one bank */
|
||||
#define CFG_MAX_FLASH_SECT 128 /* max # of sectors on one chip */
|
||||
#define CFG_FLASH_PROTECTION 1 /* hardware flash protection */
|
||||
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
|
||||
|
||||
/*
|
||||
* On Chip Memory location/size
|
||||
*
|
||||
*/
|
||||
#define CFG_OCM_DATA_ADDR 0xF8000000
|
||||
#define CFG_OCM_DATA_SIZE 0x1000
|
||||
|
||||
/*
|
||||
* Global info and initial stack
|
||||
*
|
||||
*/
|
||||
#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of on-chip SRAM */
|
||||
#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
|
||||
#define CFG_GBL_DATA_SIZE 128 /* byte size reserved for initial data */
|
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
|
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
|
||||
|
||||
/*
|
||||
* Cache configuration
|
||||
*
|
||||
*/
|
||||
#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */
|
||||
/* have only 8kB, 16kB is save here */
|
||||
#define CFG_CACHELINE_SIZE 32
|
||||
|
||||
/*
|
||||
* Miscellaneous board specific definitions
|
||||
*
|
||||
*/
|
||||
#define CFG_I2C_PLL_ADDR 0x58 /* I2C address of AMIS FS6377-01 PLL */
|
||||
|
||||
/*
|
||||
* Internal Definitions
|
||||
*
|
||||
* Boot Flags
|
||||
*
|
||||
*/
|
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
|
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
Reference in New Issue
Block a user