From 989fd97fe56676dd636803c467834c36a86d06a5 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Sat, 9 Feb 2019 17:45:42 +0530 Subject: [PATCH 01/25] mtd: spi: Kconfig: Update CONFIG_SPI_FLASH 1) CONFIG_SPI_FLASH is not just a legacy code, but it has common core code which handle both dm and non-dm spi flash code. So fix the info text to make it clear globally. 2) Since it's flash core it shouldn't depends on legacy SPI, so remove the 'depends on SPI' Cc: Vignesh R Signed-off-by: Jagan Teki --- drivers/mtd/spi/Kconfig | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig index d3b007a731..a0cfc623c6 100644 --- a/drivers/mtd/spi/Kconfig +++ b/drivers/mtd/spi/Kconfig @@ -26,11 +26,10 @@ config SPI_FLASH_SANDBOX stored in a file on the host filesystem. config SPI_FLASH - bool "Legacy SPI Flash Interface support" - depends on SPI + bool "SPI Flash Core Interface support" select SPI_MEM help - Enable the legacy SPI flash support. This will include basic + Enable the SPI flash Core support. This will include basic standard support for things like probing, read / write, and erasing through cmd_sf interface. From 97009d543dc1870c881b0ce6269fdffddf748085 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Sun, 29 Sep 2019 13:12:37 +0530 Subject: [PATCH 02/25] mtd: spi-nor: ids: Add is25wp256 chip Add is25wp256, chip to spi-nor id table. Tested on SiFive FU540 board. Signed-off-by: Jagan Teki Reviewed-by: Bin Meng Tested-by: Bin Meng --- drivers/mtd/spi/spi-nor-ids.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 6996c0a286..04db986561 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -128,6 +128,8 @@ const struct flash_info spi_nor_ids[] = { SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("is25wp128", 0x9d7018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + { INFO("is25wp256", 0x9d7019, 0, 64 * 1024, 512, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, #endif #ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */ /* Macronix */ From 0c8e605670fac186f225a957eb8e1a774cb17c41 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Wed, 16 Oct 2019 18:04:13 +0530 Subject: [PATCH 03/25] spi: Kconfig: Add help text Add detailed help text for SPI support. Signed-off-by: Jagan Teki --- drivers/spi/Kconfig | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index b8ca2bdedd..0152dff74f 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -1,5 +1,22 @@ menuconfig SPI bool "SPI Support" + help + The "Serial Peripheral Interface" is a low level synchronous + protocol. Chips that support SPI can have data transfer rates + up to several tens of Mbit/sec. Chips are addressed with a + controller and a chipselect. Most SPI slaves don't support + dynamic device discovery; some are even write-only or read-only. + + SPI is widely used by microcontrollers to talk with sensors, + eeprom and flash memory, codecs and various other controller + chips, analog to digital (and d-to-a) converters, and more. + MMC and SD cards can be accessed using SPI protocol; and for + DataFlash cards used in MMC sockets, SPI must always be used. + + SPI is one of a family of similar protocols using a four wire + interface (select, clock, data in, data out) including Microwire + (half duplex), SSP, SSI, and PSP. This driver framework should + work with most such devices and controllers. if SPI From 4dd520b36bce9b35f7a12f3ffd9a95269d425170 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Mon, 9 Sep 2019 06:00:00 -0700 Subject: [PATCH 04/25] dm: spi: Return 0 if driver does not implement ops->cs_info If an SPI controller driver does not implement ops->cs_info, that probably means any chip select number could be valid, hence let's return 0 for spi_cs_info(). Signed-off-by: Bin Meng Tested-by: Jagan Teki # SoPine Reviewed-by: Jagan Teki --- doc/driver-model/spi-howto.rst | 4 ++-- drivers/spi/spi-uclass.c | 7 +++---- 2 files changed, 5 insertions(+), 6 deletions(-) diff --git a/doc/driver-model/spi-howto.rst b/doc/driver-model/spi-howto.rst index 5540eb7d38..44eab3947e 100644 --- a/doc/driver-model/spi-howto.rst +++ b/doc/driver-model/spi-howto.rst @@ -634,8 +634,8 @@ method for cs_info() to deal with this. If you don't provide it, then the device tree will be used to determine what chip selects are valid. Return -ENODEV if the supplied chip select is invalid, or 0 if it is valid. -If you don't provide the cs_info() method, -ENODEV is assumed for all -chip selects that do not appear in the device tree. +If you don't provide the cs_info() method, 0 is assumed for all chip selects +that do not appear in the device tree. Test it diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.c index a4d1b65682..947516073e 100644 --- a/drivers/spi/spi-uclass.c +++ b/drivers/spi/spi-uclass.c @@ -261,11 +261,10 @@ int spi_cs_info(struct udevice *bus, uint cs, struct spi_cs_info *info) return ops->cs_info(bus, cs, info); /* - * We could assume there is at least one valid chip select, but best - * to be sure and return an error in this case. The driver didn't - * care enough to tell us. + * We could assume there is at least one valid chip select. + * The driver didn't care enough to tell us. */ - return -ENODEV; + return 0; } int spi_find_bus_and_cs(int busnum, int cs, struct udevice **busp, From 4b060003957db07fa0e35beafe6559f9cc91954c Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Mon, 9 Sep 2019 06:00:01 -0700 Subject: [PATCH 05/25] dm: spi: Change cs_info op to return -EINVAL for invalid cs num We need distinguish the following two situations in various SPI APIs: - given chip select num is invalid - given chip select num is valid, but no device is attached Currently -ENODEV is returned for both cases. For the first case, it's more reasonable to return -EINVAL instead of -ENODEV for invalid chip select numbers. Signed-off-by: Bin Meng Tested-by: Jagan Teki # SoPine Reviewed-by: Jagan Teki --- doc/driver-model/spi-howto.rst | 4 ++-- drivers/spi/ath79_spi.c | 2 +- drivers/spi/bcm63xx_hsspi.c | 2 +- drivers/spi/bcm63xx_spi.c | 2 +- drivers/spi/sandbox_spi.c | 2 +- drivers/spi/tegra20_sflash.c | 2 +- include/spi.h | 2 +- 7 files changed, 8 insertions(+), 8 deletions(-) diff --git a/doc/driver-model/spi-howto.rst b/doc/driver-model/spi-howto.rst index 44eab3947e..9631a5059d 100644 --- a/doc/driver-model/spi-howto.rst +++ b/doc/driver-model/spi-howto.rst @@ -116,7 +116,7 @@ Put this code at the bottom of your existing driver file: static int exynos_cs_info(struct udevice *bus, uint cs, struct spi_cs_info *info) { - return -ENODEV; + return -EINVAL; } static const struct dm_spi_ops exynos_spi_ops = { @@ -633,7 +633,7 @@ is not obvious from outside the driver. In this case you can provide a method for cs_info() to deal with this. If you don't provide it, then the device tree will be used to determine what chip selects are valid. -Return -ENODEV if the supplied chip select is invalid, or 0 if it is valid. +Return -EINVAL if the supplied chip select is invalid, or 0 if it is valid. If you don't provide the cs_info() method, 0 is assumed for all chip selects that do not appear in the device tree. diff --git a/drivers/spi/ath79_spi.c b/drivers/spi/ath79_spi.c index 4fd3c050e8..207069218f 100644 --- a/drivers/spi/ath79_spi.c +++ b/drivers/spi/ath79_spi.c @@ -198,7 +198,7 @@ static int ath79_cs_info(struct udevice *bus, uint cs, { /* Always allow activity on CS 0/1/2 */ if (cs >= 3) - return -ENODEV; + return -EINVAL; return 0; } diff --git a/drivers/spi/bcm63xx_hsspi.c b/drivers/spi/bcm63xx_hsspi.c index e82b80c107..529adfbc4e 100644 --- a/drivers/spi/bcm63xx_hsspi.c +++ b/drivers/spi/bcm63xx_hsspi.c @@ -108,7 +108,7 @@ static int bcm63xx_hsspi_cs_info(struct udevice *bus, uint cs, if (cs >= priv->num_cs) { printf("no cs %u\n", cs); - return -ENODEV; + return -EINVAL; } return 0; diff --git a/drivers/spi/bcm63xx_spi.c b/drivers/spi/bcm63xx_spi.c index 4d19e03523..69f88c9e08 100644 --- a/drivers/spi/bcm63xx_spi.c +++ b/drivers/spi/bcm63xx_spi.c @@ -130,7 +130,7 @@ static int bcm63xx_spi_cs_info(struct udevice *bus, uint cs, if (cs >= priv->num_cs) { printf("no cs %u\n", cs); - return -ENODEV; + return -EINVAL; } return 0; diff --git a/drivers/spi/sandbox_spi.c b/drivers/spi/sandbox_spi.c index 906401ec8a..16473ec7a0 100644 --- a/drivers/spi/sandbox_spi.c +++ b/drivers/spi/sandbox_spi.c @@ -117,7 +117,7 @@ static int sandbox_cs_info(struct udevice *bus, uint cs, { /* Always allow activity on CS 0 */ if (cs >= 1) - return -ENODEV; + return -EINVAL; return 0; } diff --git a/drivers/spi/tegra20_sflash.c b/drivers/spi/tegra20_sflash.c index a54b10fdeb..567e33f156 100644 --- a/drivers/spi/tegra20_sflash.c +++ b/drivers/spi/tegra20_sflash.c @@ -78,7 +78,7 @@ int tegra20_sflash_cs_info(struct udevice *bus, unsigned int cs, { /* Tegra20 SPI-Flash - only 1 device ('bus/cs') */ if (cs != 0) - return -ENODEV; + return -EINVAL; else return 0; } diff --git a/include/spi.h b/include/spi.h index 5eec0c4775..3f79168df3 100644 --- a/include/spi.h +++ b/include/spi.h @@ -458,7 +458,7 @@ struct dm_spi_ops { * @cs: The chip select (0..n-1) * @info: Returns information about the chip select, if valid. * On entry info->dev is NULL - * @return 0 if OK (and @info is set up), -ENODEV if the chip select + * @return 0 if OK (and @info is set up), -EINVAL if the chip select * is invalid, other -ve value on error */ int (*cs_info)(struct udevice *bus, uint cs, struct spi_cs_info *info); From c2af7fb1ff6f8d6489bdba4216128cbb08ae4243 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Wed, 16 Oct 2019 17:59:42 +0530 Subject: [PATCH 06/25] cmd: sf: Mark it default if DM_SPI_FLASH enabled If DM_SPI_FLASH enabled that means it is using sf command for flash interface to access. SPI_FLASH can be used via sf command and board/driver functions to call spi flash ops, so mark it default only for DM_SPI_FLASH. This would prevent explicit adding of CONFIG_CMD_SF when DM_SPI_FLASH being enabled. Cc: Tom Rini Acked-by: Vignesh Raghavendra Signed-off-by: Jagan Teki --- cmd/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/cmd/Kconfig b/cmd/Kconfig index 82b5d300d2..b08a709857 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -1168,6 +1168,7 @@ config CMD_SDRAM config CMD_SF bool "sf" depends on DM_SPI_FLASH || SPI_FLASH + default y if DM_SPI_FLASH help SPI Flash support From 77df1a9b665461e03e6da94cd9fb0399c85e715a Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Wed, 16 Oct 2019 18:07:24 +0530 Subject: [PATCH 07/25] mtd: spi: Kconfig: Imply SPI_FLASH if DM_SPI_FLASH DM_SPI_FLASH should require spi flash interface code for dm version, so imply SPI_FLASH core by default if any board enabled DM_SPI_FLASH. This overcome the explicit enablement of CONFIG_SPI_FLASH on respective boards when DM_SPI_FLASH being used. Acked-by: Vignesh Raghavendra Signed-off-by: Jagan Teki --- drivers/mtd/spi/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig index a0cfc623c6..681dc9cccc 100644 --- a/drivers/mtd/spi/Kconfig +++ b/drivers/mtd/spi/Kconfig @@ -3,6 +3,7 @@ menu "SPI Flash Support" config DM_SPI_FLASH bool "Enable Driver Model for SPI flash" depends on DM && DM_SPI + imply SPI_FLASH help Enable driver model for SPI flash. This SPI flash interface (spi_flash_probe(), spi_flash_write(), etc.) is then From dc738248db9355c66241979b21d6bf4e2a625bef Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Wed, 16 Oct 2019 18:05:56 +0530 Subject: [PATCH 08/25] spi: Kconfig: Enable SPI_SUNXI for SUNXI SPI_SUNXI driver is fully dm-aware and the Allwinner architecture kconfig would have logic to enable the DM_SPI. So, select default spi sunxi driver for sunxi architecture. Signed-off-by: Jagan Teki --- drivers/spi/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 0152dff74f..7be867d5b6 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -260,6 +260,7 @@ config SPI_SIFIVE config SPI_SUNXI bool "Allwinner SoC SPI controllers" + default ARCH_SUNXI help Enable the Allwinner SoC SPi controller driver. From 7945caf22c44a9e394ef535a27b502ec3f3ba5ed Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Wed, 16 Oct 2019 18:08:26 +0530 Subject: [PATCH 09/25] arm: sunxi: Enable SPI/SPI-FLASH support for A64 SPI is available in Allwinner A64 SoC, so enable it globally in Kconfig. - CONFIG_SPI - CONFIG_DM_SPI - CONFIG_DM_SPI_FLASH Signed-off-by: Jagan Teki --- arch/arm/mach-sunxi/Kconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index ffdf09f29e..16d41b83af 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -275,7 +275,10 @@ config MACH_SUN9I config MACH_SUN50I bool "sun50i (Allwinner A64)" select ARM64 + select SPI select DM_I2C + select DM_SPI if SPI + select DM_SPI_FLASH select PHY_SUN4I_USB select SUN6I_PRCM select SUNXI_DE2 From f8cb77ffbac5ca01b6372bae413f4c205edf089d Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Wed, 16 Oct 2019 19:19:25 +0530 Subject: [PATCH 10/25] configs: sopine-baseboard: Enable SPI-FLASH SoPine has winbond SPI-FLASH, so enable the same in defconfig and add aliases for spi0 in -u-boot.dtsi Signed-off-by: Jagan Teki --- arch/arm/dts/sun50i-a64-sopine-baseboard-u-boot.dtsi | 12 ++++++++++++ configs/sopine_baseboard_defconfig | 1 + 2 files changed, 13 insertions(+) create mode 100644 arch/arm/dts/sun50i-a64-sopine-baseboard-u-boot.dtsi diff --git a/arch/arm/dts/sun50i-a64-sopine-baseboard-u-boot.dtsi b/arch/arm/dts/sun50i-a64-sopine-baseboard-u-boot.dtsi new file mode 100644 index 0000000000..02b1ae046e --- /dev/null +++ b/arch/arm/dts/sun50i-a64-sopine-baseboard-u-boot.dtsi @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Jagan Teki + */ + +#include "sunxi-u-boot.dtsi" + +/ { + aliases { + spi0 = &spi0; + }; +}; diff --git a/configs/sopine_baseboard_defconfig b/configs/sopine_baseboard_defconfig index 5833234b63..c9123fd7ee 100644 --- a/configs/sopine_baseboard_defconfig +++ b/configs/sopine_baseboard_defconfig @@ -10,6 +10,7 @@ CONFIG_DRAM_ZQ=3881949 CONFIG_MMC0_CD_PIN="" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_SPL_SPI_SUNXI=y +CONFIG_SPI_FLASH_WINBOND=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_USE_PREBOOT=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x8000 From 64f736c9013b059696a9c0370e152c1ab6a8f89e Mon Sep 17 00:00:00 2001 From: Frieder Schrempf Date: Fri, 13 Sep 2019 22:43:42 +0000 Subject: [PATCH 11/25] mtd: spi: Add a new option SPL_SPI_FLASH_MTD to Kconfig To allow SPI_FLASH_MTD being enabled separately in SPL we add a new option. The only user currently is the stm32mp15_basic board. Signed-off-by: Frieder Schrempf Acked-by: Lukasz Majewski Reviewed-by: Jagan Teki --- drivers/mtd/spi/Kconfig | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig index 681dc9cccc..d77f818505 100644 --- a/drivers/mtd/spi/Kconfig +++ b/drivers/mtd/spi/Kconfig @@ -196,4 +196,12 @@ config SPI_FLASH_MTD If unsure, say N +config SPL_SPI_FLASH_MTD + bool "SPI flash MTD support for SPL" + depends on SPI_FLASH + help + Enable the MTD support for the SPI flash layer in SPL. + + If unsure, say N + endmenu # menu "SPI Flash Support" From a9ec8423a9c3d2c076ba7706f43859e025e44781 Mon Sep 17 00:00:00 2001 From: Frieder Schrempf Date: Tue, 22 Oct 2019 23:37:43 +0530 Subject: [PATCH 12/25] stm32mp1: configs: Add CONFIG_SPL_SPI_FLASH_MTD As SPI_FLASH_MTD is used in SPL and U-Boot proper, we enable both, now that a separate option for SPL was introduced. Signed-off-by: Frieder Schrempf [jagan: drop unrelated change] Signed-off-by: Jagan Teki Reviewed-by: Lukasz Majewski Reviewed-by: Jagan Teki --- configs/stm32mp15_basic_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/stm32mp15_basic_defconfig b/configs/stm32mp15_basic_defconfig index c54feb03e6..2a54e715cb 100644 --- a/configs/stm32mp15_basic_defconfig +++ b/configs/stm32mp15_basic_defconfig @@ -90,6 +90,7 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_WINBOND=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_SPI_FLASH_MTD=y +CONFIG_SPL_SPI_FLASH_MTD=y CONFIG_DM_ETH=y CONFIG_DWC_ETH_QOS=y CONFIG_PHY=y From cc9118757f6ce57bf1776cca41cb52a3dc24401e Mon Sep 17 00:00:00 2001 From: Vignesh Raghavendra Date: Thu, 26 Sep 2019 19:04:26 +0530 Subject: [PATCH 13/25] mtd: spi-nor-core: Use dev_err for reporting erase/write failures Use dev_err() when reporting reason for erase/write failures so that users can be made aware of the reason for failure. Signed-off-by: Vignesh Raghavendra Reviewed-by: Jagan Teki --- drivers/mtd/spi/spi-nor-core.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index 990e39d7c2..1eebbcb919 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -380,12 +380,12 @@ static int spi_nor_fsr_ready(struct spi_nor *nor) if (fsr & (FSR_E_ERR | FSR_P_ERR)) { if (fsr & FSR_E_ERR) - dev_dbg(nor->dev, "Erase operation failed.\n"); + dev_err(nor->dev, "Erase operation failed.\n"); else - dev_dbg(nor->dev, "Program operation failed.\n"); + dev_err(nor->dev, "Program operation failed.\n"); if (fsr & FSR_PT_ERR) - dev_dbg(nor->dev, + dev_err(nor->dev, "Attempted to modify a protected sector.\n"); nor->write_reg(nor, SPINOR_OP_CLFSR, NULL, 0); From 2a2174d3da33b9e71a26ecc5d40f1369401275fd Mon Sep 17 00:00:00 2001 From: Vignesh Raghavendra Date: Thu, 26 Sep 2019 19:04:27 +0530 Subject: [PATCH 14/25] mtd: spi-nor-core: Replace MTD_SPI_NOR_USE_4K_SECTORS with SPI_FLASH_USE_4K_SECTORS U-Boot uses CONFIG_SPI_FLASH_USE_4K_SECTORS to enable 4K small sector support. Use that instead of MTD_SPI_NOR_USE_4K_SECTORS. Reported-by: Eugeniy Paltsev Signed-off-by: Vignesh Raghavendra Reviewed-by: Jagan Teki --- drivers/mtd/spi/spi-nor-core.c | 2 +- drivers/mtd/spi/spi-nor-ids.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index 1eebbcb919..5a8c084255 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -1916,7 +1916,7 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor, erasesize = 1U << erasesize; opcode = (half >> 8) & 0xff; -#ifdef CONFIG_MTD_SPI_NOR_USE_4K_SECTORS +#ifdef CONFIG_SPI_FLASH_USE_4K_SECTORS if (erasesize == SZ_4K) { nor->erase_opcode = opcode; mtd->erasesize = erasesize; diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 04db986561..164a22d382 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -58,7 +58,7 @@ * All newly added entries should describe *hardware* and should use SECT_4K * (or SECT_4K_PMC) if hardware supports erasing 4 KiB sectors. For usage * scenarios excluding small sectors there is config option that can be - * disabled: CONFIG_MTD_SPI_NOR_USE_4K_SECTORS. + * disabled: CONFIG_SPI_FLASH_USE_4K_SECTORS. * For historical (and compatibility) reasons (before we got above config) some * old entries may be missing 4K flag. */ From e7e05fcb3edb95584e7294099dbf0d28f0f87322 Mon Sep 17 00:00:00 2001 From: Ley Foon Tan Date: Wed, 19 Sep 2018 16:27:19 +0800 Subject: [PATCH 15/25] spi: designware_spi: Disable and free clock when remove driver Disable and free clock when remove driver. Signed-off-by: Ley Foon Tan Acked-by: Marek Vasut Reviewed-by: Jagan Teki --- drivers/spi/designware_spi.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c index 7d58cfae55..91e613e9cd 100644 --- a/drivers/spi/designware_spi.c +++ b/drivers/spi/designware_spi.c @@ -518,8 +518,22 @@ static int dw_spi_set_mode(struct udevice *bus, uint mode) static int dw_spi_remove(struct udevice *bus) { struct dw_spi_priv *priv = dev_get_priv(bus); + int ret; - return reset_release_bulk(&priv->resets); + ret = reset_release_bulk(&priv->resets); + if (ret) + return ret; + +#if CONFIG_IS_ENABLED(CLK) + ret = clk_disable(&priv->clk); + if (ret) + return ret; + + ret = clk_free(&priv->clk); + if (ret) + return ret; +#endif + return 0; } static const struct dm_spi_ops dw_spi_ops = { From d66e07cdf9ab6f84ce121009b08860261bca7df2 Mon Sep 17 00:00:00 2001 From: Vignesh Raghavendra Date: Fri, 11 Oct 2019 13:28:18 +0530 Subject: [PATCH 16/25] spi-nor: spi-nor-ids: Disable SPI_NOR_4B_OPCODES for n25q512* and n25q256* Per datasheets of n25q256* and n25q512* not all variants of n25q256* and n25q512* support 4 Byte stateless addressing opcodes. Therefore drop SPI_NOR_4B_OPCODES flag from these entries Signed-off-by: Vignesh Raghavendra Reviewed-by: Tudor Ambarus Reviewed-by: Simon Goldschmidt Tested-by: Simon Goldschmidt Tested-by: Eugeniy Paltsev Reviewed-by: Jagan Teki --- drivers/mtd/spi/spi-nor-ids.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 164a22d382..17352d17f6 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -163,12 +163,12 @@ const struct flash_info spi_nor_ids[] = { { INFO("n25q064a", 0x20bb17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) }, { INFO("n25q128a11", 0x20bb18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) }, { INFO("n25q128a13", 0x20ba18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) }, - { INFO("n25q256a", 0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, - { INFO("n25q256ax1", 0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, + { INFO("n25q256a", 0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + { INFO("n25q256ax1", 0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) }, { INFO6("mt25qu512a", 0x20bb20, 0x104400, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, - { INFO("n25q512a", 0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, - { INFO("n25q512ax3", 0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, + { INFO("n25q512a", 0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, + { INFO("n25q512ax3", 0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, { INFO("n25q00", 0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, { INFO("n25q00a", 0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, { INFO("mt25qu02g", 0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, From 8651593a8ce0c0599c993d76d2a927b125175cef Mon Sep 17 00:00:00 2001 From: Vignesh Raghavendra Date: Fri, 11 Oct 2019 13:28:19 +0530 Subject: [PATCH 17/25] spi-nor: spi-nor-ids: Add entries for mt25q variants mt25q* flashes support stateless 4 byte addressing opcodes. Add entries for the same. These flashes have bit 6 set in 5th byte of READ ID response when compared to n25q* variants. Signed-off-by: Vignesh Raghavendra Reviewed-by: Tudor Ambarus Tested-by: Simon Goldschmidt Reviewed-by: Jagan Teki --- drivers/mtd/spi/spi-nor-ids.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 17352d17f6..aa64ead7f4 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -163,11 +163,14 @@ const struct flash_info spi_nor_ids[] = { { INFO("n25q064a", 0x20bb17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) }, { INFO("n25q128a11", 0x20bb18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) }, { INFO("n25q128a13", 0x20ba18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) }, + { INFO6("mt25ql256a", 0x20ba19, 0x104400, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, { INFO("n25q256a", 0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + { INFO6("mt25qu256a", 0x20bb19, 0x104400, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, { INFO("n25q256ax1", 0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) }, { INFO6("mt25qu512a", 0x20bb20, 0x104400, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, { INFO("n25q512a", 0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, + { INFO6("mt25ql512a", 0x20ba20, 0x104400, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, { INFO("n25q512ax3", 0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, { INFO("n25q00", 0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, { INFO("n25q00a", 0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, From 73d74b58812373b4973d1fd38fc37f4e6083ab91 Mon Sep 17 00:00:00 2001 From: Vignesh Raghavendra Date: Fri, 11 Oct 2019 13:28:20 +0530 Subject: [PATCH 18/25] spi-nor: spi-nor-ids: Add USE_FSR flag for mt25q* and n25q* entry n25q* and mt25q* (both 256Mb and 512Mb) flashes support Flag status register that indicates various errors that may be encountered during erase/write operations. Therefore add USE_FSR flag wherever missing. Signed-off-by: Vignesh Raghavendra Reviewed-by: Tudor Ambarus Reviewed-by: Simon Goldschmidt Reviewed-by: Jagan Teki --- drivers/mtd/spi/spi-nor-ids.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index aa64ead7f4..0e66ba9890 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -163,12 +163,13 @@ const struct flash_info spi_nor_ids[] = { { INFO("n25q064a", 0x20bb17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) }, { INFO("n25q128a11", 0x20bb18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) }, { INFO("n25q128a13", 0x20ba18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) }, - { INFO6("mt25ql256a", 0x20ba19, 0x104400, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, - { INFO("n25q256a", 0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, - { INFO6("mt25qu256a", 0x20bb19, 0x104400, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, - { INFO("n25q256ax1", 0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) }, + { INFO6("mt25ql256a", 0x20ba19, 0x104400, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | USE_FSR) }, + { INFO("n25q256a", 0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_FSR) }, + { INFO6("mt25qu256a", 0x20bb19, 0x104400, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | USE_FSR) }, + { INFO("n25q256ax1", 0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ | USE_FSR) }, { INFO6("mt25qu512a", 0x20bb20, 0x104400, 64 * 1024, 1024, - SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | + USE_FSR) }, { INFO("n25q512a", 0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, { INFO6("mt25ql512a", 0x20ba20, 0x104400, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, { INFO("n25q512ax3", 0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, From 832ce20278db00aeeed5576f1296a6d905d31563 Mon Sep 17 00:00:00 2001 From: Frieder Schrempf Date: Wed, 23 Oct 2019 07:41:20 +0000 Subject: [PATCH 19/25] mtd: spi: Clean up usage of CONFIG_SPI_FLASH_MTD Most boards currently use SPI_FLASH_MTD only in U-Boot proper, not in SPL. They often rely on hacks in the board header files to include this option conditionally. To be able to fix this, we previously introduced a separate option SPL_SPI_FLASH_MTD. Therefore we can now adjust the Makefile and change the code in sf_probe.c and sf_internal.h to use CONFIG_IS_ENABLED(SPI_FLASH_MTD). We also need to move all occurences of CONFIG_SPI_FLASH_MTD from the header files to the according defconfigs. The affected boards are socfpga, aristainetos, cm_fx6, display5, ventana, rcar-gen2, dh_imx6 and da850evm. We do this all in one patch to guarantee bisectibility. This change was tested with buildman to make sure it does not introduce any regressions by comparing the resulting binary sizes. Signed-off-by: Frieder Schrempf Reviewed-by: Stefan Roese Reviewed-by: Simon Goldschmidt Acked-by: Lukasz Majewski Reviewed-by: Heiko Schocher Reviewed-by: Jagan Teki --- configs/aristainetos2_defconfig | 1 + configs/aristainetos2b_defconfig | 1 + configs/aristainetos_defconfig | 1 + configs/cm_fx6_defconfig | 1 + configs/socfpga_arria5_defconfig | 1 + configs/socfpga_cyclone5_defconfig | 1 + configs/socfpga_dbm_soc1_defconfig | 1 + configs/socfpga_de0_nano_soc_defconfig | 1 + configs/socfpga_de10_nano_defconfig | 1 + configs/socfpga_is1_defconfig | 1 + configs/socfpga_mcvevk_defconfig | 1 + configs/socfpga_sockit_defconfig | 1 + configs/socfpga_socrates_defconfig | 1 + configs/socfpga_sr1500_defconfig | 1 + configs/socfpga_vining_fpga_defconfig | 1 + drivers/mtd/spi/Makefile | 2 +- drivers/mtd/spi/sf_internal.h | 2 +- drivers/mtd/spi/sf_probe.c | 6 +++--- include/configs/aristainetos-common.h | 1 - include/configs/cm_fx6.h | 7 ------- include/configs/da850evm.h | 7 +------ include/configs/dh_imx6.h | 1 - include/configs/display5.h | 1 - include/configs/gw_ventana.h | 10 +--------- include/configs/rcar-gen2-common.h | 4 +--- include/configs/socfpga_common.h | 4 ---- 26 files changed, 23 insertions(+), 37 deletions(-) diff --git a/configs/aristainetos2_defconfig b/configs/aristainetos2_defconfig index 18ef5d2dce..0bfc117762 100644 --- a/configs/aristainetos2_defconfig +++ b/configs/aristainetos2_defconfig @@ -44,6 +44,7 @@ CONFIG_SF_DEFAULT_CS=1 CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_MTD=y CONFIG_MTD_UBI_FASTMAP=y CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1 CONFIG_PHYLIB=y diff --git a/configs/aristainetos2b_defconfig b/configs/aristainetos2b_defconfig index 1054c05d8c..e2da747a8f 100644 --- a/configs/aristainetos2b_defconfig +++ b/configs/aristainetos2b_defconfig @@ -42,6 +42,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_MTD=y CONFIG_MTD_UBI_FASTMAP=y CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1 CONFIG_PHYLIB=y diff --git a/configs/aristainetos_defconfig b/configs/aristainetos_defconfig index 4080a7b310..5caf95c22f 100644 --- a/configs/aristainetos_defconfig +++ b/configs/aristainetos_defconfig @@ -43,6 +43,7 @@ CONFIG_SF_DEFAULT_BUS=3 CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_MTD=y CONFIG_MTD_UBI_FASTMAP=y CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1 CONFIG_PHYLIB=y diff --git a/configs/cm_fx6_defconfig b/configs/cm_fx6_defconfig index eed0558e24..fbaf79d1f0 100644 --- a/configs/cm_fx6_defconfig +++ b/configs/cm_fx6_defconfig @@ -72,6 +72,7 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_SST=y CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_MTD=y CONFIG_PHYLIB=y CONFIG_MII=y CONFIG_DM_PMIC=y diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig index 93254677e7..51f559cda8 100644 --- a/configs/socfpga_arria5_defconfig +++ b/configs/socfpga_arria5_defconfig @@ -47,6 +47,7 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_SPI_FLASH_MTD=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig index 8e5b2e2f66..c648113029 100644 --- a/configs/socfpga_cyclone5_defconfig +++ b/configs/socfpga_cyclone5_defconfig @@ -48,6 +48,7 @@ CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_SPI_FLASH_MTD=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y diff --git a/configs/socfpga_dbm_soc1_defconfig b/configs/socfpga_dbm_soc1_defconfig index c73f3821e7..414f13147e 100644 --- a/configs/socfpga_dbm_soc1_defconfig +++ b/configs/socfpga_dbm_soc1_defconfig @@ -46,6 +46,7 @@ CONFIG_SYS_I2C_DW=y CONFIG_DM_MMC=y CONFIG_MMC_DW=y CONFIG_MTD_DEVICE=y +CONFIG_SPI_FLASH_MTD=y CONFIG_DM_ETH=y CONFIG_PHY_GIGE=y CONFIG_ETH_DESIGNWARE=y diff --git a/configs/socfpga_de0_nano_soc_defconfig b/configs/socfpga_de0_nano_soc_defconfig index 80ccb33fbb..6eb052e9db 100644 --- a/configs/socfpga_de0_nano_soc_defconfig +++ b/configs/socfpga_de0_nano_soc_defconfig @@ -43,6 +43,7 @@ CONFIG_SYS_I2C_DW=y CONFIG_DM_MMC=y CONFIG_MMC_DW=y CONFIG_MTD_DEVICE=y +CONFIG_SPI_FLASH_MTD=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y diff --git a/configs/socfpga_de10_nano_defconfig b/configs/socfpga_de10_nano_defconfig index 98e80b7c86..6b8b5b41a1 100644 --- a/configs/socfpga_de10_nano_defconfig +++ b/configs/socfpga_de10_nano_defconfig @@ -39,6 +39,7 @@ CONFIG_SYS_I2C_DW=y CONFIG_DM_MMC=y CONFIG_MMC_DW=y CONFIG_MTD_DEVICE=y +CONFIG_SPI_FLASH_MTD=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y diff --git a/configs/socfpga_is1_defconfig b/configs/socfpga_is1_defconfig index 99cdb26aae..38b9f6c24b 100644 --- a/configs/socfpga_is1_defconfig +++ b/configs/socfpga_is1_defconfig @@ -43,6 +43,7 @@ CONFIG_SYS_I2C_DW=y CONFIG_MTD_DEVICE=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_MTD=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y diff --git a/configs/socfpga_mcvevk_defconfig b/configs/socfpga_mcvevk_defconfig index e977cd7707..605ffd7c2b 100644 --- a/configs/socfpga_mcvevk_defconfig +++ b/configs/socfpga_mcvevk_defconfig @@ -42,6 +42,7 @@ CONFIG_DM_I2C=y CONFIG_SYS_I2C_DW=y CONFIG_DM_MMC=y CONFIG_MMC_DW=y +CONFIG_SPI_FLASH_MTD=y CONFIG_DM_ETH=y CONFIG_PHY_GIGE=y CONFIG_ETH_DESIGNWARE=y diff --git a/configs/socfpga_sockit_defconfig b/configs/socfpga_sockit_defconfig index b570b9dc94..cae6f7bc9b 100644 --- a/configs/socfpga_sockit_defconfig +++ b/configs/socfpga_sockit_defconfig @@ -48,6 +48,7 @@ CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_SPI_FLASH_MTD=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y diff --git a/configs/socfpga_socrates_defconfig b/configs/socfpga_socrates_defconfig index 9eac00e49d..9cb1daa889 100644 --- a/configs/socfpga_socrates_defconfig +++ b/configs/socfpga_socrates_defconfig @@ -48,6 +48,7 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_MTD=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y diff --git a/configs/socfpga_sr1500_defconfig b/configs/socfpga_sr1500_defconfig index 092347a6df..c48bbb0e9c 100644 --- a/configs/socfpga_sr1500_defconfig +++ b/configs/socfpga_sr1500_defconfig @@ -49,6 +49,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=100000000 CONFIG_SPI_FLASH_STMICRO=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_SPI_FLASH_MTD=y CONFIG_PHY_MARVELL=y CONFIG_DM_ETH=y CONFIG_PHY_GIGE=y diff --git a/configs/socfpga_vining_fpga_defconfig b/configs/socfpga_vining_fpga_defconfig index a9c594e219..80733ba6b1 100644 --- a/configs/socfpga_vining_fpga_defconfig +++ b/configs/socfpga_vining_fpga_defconfig @@ -72,6 +72,7 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_SPI_FLASH_MTD=y CONFIG_MTD_UBI_FASTMAP=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y diff --git a/drivers/mtd/spi/Makefile b/drivers/mtd/spi/Makefile index 20db1015d9..b5dfa300de 100644 --- a/drivers/mtd/spi/Makefile +++ b/drivers/mtd/spi/Makefile @@ -19,5 +19,5 @@ endif obj-$(CONFIG_SPI_FLASH) += spi-nor.o obj-$(CONFIG_SPI_FLASH_DATAFLASH) += sf_dataflash.o -obj-$(CONFIG_SPI_FLASH_MTD) += sf_mtd.o +obj-$(CONFIG_$(SPL_)SPI_FLASH_MTD) += sf_mtd.o obj-$(CONFIG_SPI_FLASH_SANDBOX) += sandbox.o diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h index bb8c19a31c..5c643034c6 100644 --- a/drivers/mtd/spi/sf_internal.h +++ b/drivers/mtd/spi/sf_internal.h @@ -77,7 +77,7 @@ extern const struct flash_info spi_nor_ids[]; int spi_flash_cmd_get_sw_write_prot(struct spi_flash *flash); -#ifdef CONFIG_SPI_FLASH_MTD +#if CONFIG_IS_ENABLED(SPI_FLASH_MTD) int spi_flash_mtd_register(struct spi_flash *flash); void spi_flash_mtd_unregister(void); #endif diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c index 73297e1a0a..f051e473ff 100644 --- a/drivers/mtd/spi/sf_probe.c +++ b/drivers/mtd/spi/sf_probe.c @@ -44,7 +44,7 @@ static int spi_flash_probe_slave(struct spi_flash *flash) if (ret) goto err_read_id; -#ifdef CONFIG_SPI_FLASH_MTD +#if CONFIG_IS_ENABLED(SPI_FLASH_MTD) ret = spi_flash_mtd_register(flash); #endif @@ -83,7 +83,7 @@ struct spi_flash *spi_flash_probe(unsigned int busnum, unsigned int cs, void spi_flash_free(struct spi_flash *flash) { -#ifdef CONFIG_SPI_FLASH_MTD +#if CONFIG_IS_ENABLED(SPI_FLASH_MTD) spi_flash_mtd_unregister(); #endif spi_free_slave(flash->spi); @@ -152,7 +152,7 @@ static int spi_flash_std_probe(struct udevice *dev) static int spi_flash_std_remove(struct udevice *dev) { -#ifdef CONFIG_SPI_FLASH_MTD +#if CONFIG_IS_ENABLED(SPI_FLASH_MTD) spi_flash_mtd_unregister(); #endif return 0; diff --git a/include/configs/aristainetos-common.h b/include/configs/aristainetos-common.h index e998d9b1b2..b451c7e7dc 100644 --- a/include/configs/aristainetos-common.h +++ b/include/configs/aristainetos-common.h @@ -30,7 +30,6 @@ #define CONFIG_ETHPRIME "FEC" #define CONFIG_FEC_MXC_PHYADDR 0 -#define CONFIG_SPI_FLASH_MTD #define CONFIG_SYS_SPI_ST_ENABLE_WP_PIN #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h index b957e9cba4..c1a6625fcb 100644 --- a/include/configs/cm_fx6.h +++ b/include/configs/cm_fx6.h @@ -38,13 +38,6 @@ #define CONFIG_MXC_UART_BASE UART4_BASE #define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} -/* SPI flash */ - -/* MTD support */ -#ifndef CONFIG_SPL_BUILD -#define CONFIG_SPI_FLASH_MTD -#endif - /* Environment */ #define CONFIG_ENV_SECT_SIZE (64 * 1024) #define CONFIG_ENV_SIZE (8 * 1024) diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h index 41f0813a01..6876134a00 100644 --- a/include/configs/da850evm.h +++ b/include/configs/da850evm.h @@ -190,16 +190,11 @@ #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ #endif -#ifdef CONFIG_USE_SPIFLASH -#ifdef CONFIG_ENV_IS_IN_SPI_FLASH +#if defined(CONFIG_USE_SPIFLASH) && defined(CONFIG_ENV_IS_IN_SPI_FLASH) #define CONFIG_ENV_SIZE (64 << 10) #define CONFIG_ENV_OFFSET (512 << 10) #define CONFIG_ENV_SECT_SIZE (64 << 10) #endif -#ifdef CONFIG_SPL_BUILD -#undef CONFIG_SPI_FLASH_MTD -#endif -#endif /* * U-Boot general configuration diff --git a/include/configs/dh_imx6.h b/include/configs/dh_imx6.h index a854d0b531..86c1192035 100644 --- a/include/configs/dh_imx6.h +++ b/include/configs/dh_imx6.h @@ -59,7 +59,6 @@ #if defined(CONFIG_SPL_BUILD) #undef CONFIG_DM_SPI #undef CONFIG_DM_SPI_FLASH -#undef CONFIG_SPI_FLASH_MTD #endif /* UART */ diff --git a/include/configs/display5.h b/include/configs/display5.h index d80641568e..65dae1f62f 100644 --- a/include/configs/display5.h +++ b/include/configs/display5.h @@ -39,7 +39,6 @@ #if defined(CONFIG_SPL_BUILD) #undef CONFIG_DM_SPI #undef CONFIG_DM_SPI_FLASH -#undef CONFIG_SPI_FLASH_MTD #endif /* Below values are "dummy" - only to avoid build break */ diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h index a27627e721..e543061bff 100644 --- a/include/configs/gw_ventana.h +++ b/include/configs/gw_ventana.h @@ -47,15 +47,7 @@ #define CONFIG_MXC_UART #define CONFIG_MXC_UART_BASE UART2_BASE -#ifdef CONFIG_SPI_FLASH - -/* SPI */ -#ifdef CONFIG_CMD_SF - #define CONFIG_SPI_FLASH_MTD - /* GPIO 3-19 (21248) */ -#endif - -#elif defined(CONFIG_SPL_NAND_SUPPORT) +#if !defined(CONFIG_SPI_FLASH) && defined(CONFIG_SPL_NAND_SUPPORT) /* Enable NAND support */ #ifdef CONFIG_CMD_NAND #define CONFIG_SYS_MAX_NAND_DEVICE 1 diff --git a/include/configs/rcar-gen2-common.h b/include/configs/rcar-gen2-common.h index 71a5909045..e940a8b70a 100644 --- a/include/configs/rcar-gen2-common.h +++ b/include/configs/rcar-gen2-common.h @@ -46,11 +46,9 @@ #define CONFIG_ENV_SIZE_REDUND (CONFIG_SYS_MONITOR_LEN) /* SF MTD */ -#if defined(CONFIG_SPI_FLASH_MTD) && !defined(CONFIG_SPL_BUILD) -#else +#ifdef CONFIG_SPL_BUILD #undef CONFIG_DM_SPI #undef CONFIG_DM_SPI_FLASH -#undef CONFIG_SPI_FLASH_MTD #endif /* Timer */ diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 94268ed7a3..baa214399f 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -132,10 +132,6 @@ /* * QSPI support */ -/* Enable multiple SPI NOR flash manufacturers */ -#ifndef CONFIG_SPL_BUILD -#define CONFIG_SPI_FLASH_MTD -#endif /* QSPI reference clock */ #ifndef __ASSEMBLY__ unsigned int cm_get_qspi_controller_clk_hz(void); From 395ec7418695e5ce23f8b48c01a1dbffd2e52d3f Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 21 Oct 2019 10:51:16 -0300 Subject: [PATCH 20/25] spi-nor-ids: Add support for Adesto AT25SL321 Add an entry for the Adesto AT25SL321 SPI NOR chip. This SPI NOR chip is found in the Embedded Artist i.MX7ULP COM board. Signed-off-by: Fabio Estevam Reviewed-by: Jagan Teki --- drivers/mtd/spi/spi-nor-ids.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 0e66ba9890..d3b84574ac 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -75,6 +75,7 @@ const struct flash_info spi_nor_ids[] = { { INFO("at45db161d", 0x1f2600, 0, 64 * 1024, 32, SECT_4K) }, { INFO("at45db321d", 0x1f2700, 0, 64 * 1024, 64, SECT_4K) }, { INFO("at45db641d", 0x1f2800, 0, 64 * 1024, 128, SECT_4K) }, + { INFO("at25sl321", 0x1f4216, 0, 64 * 1024, 64, SECT_4K) }, { INFO("at26df081a", 0x1f4501, 0, 64 * 1024, 16, SECT_4K) }, #endif #ifdef CONFIG_SPI_FLASH_EON /* EON */ From e8c19ffa981bc60bdf651658e083664764df1a95 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Fri, 23 Aug 2019 19:24:04 +0200 Subject: [PATCH 21/25] sunxi: H6: DRAM: Add support for half DQ Half DQ configuration seems to be very rare for H6 based boards/STBs, but exists nevertheless. Currently the only known product which needs this support is Tanix TX6 mini. This commit adds support for half DQ configuration. Code was tested for regressions on other configurations (OrangePi 3 1 GiB/LPDDR3, Tanix TX6 4 GiB/DDR3) and none were found. Thanks to Icenowy Zheng for help with this code. Reviewed-by: Andre Przywara Tested-by: thomas graichen Signed-off-by: Jernej Skrabec Reviewed-by: Maxime Ripard --- .../include/asm/arch-sunxi/dram_sun50i_h6.h | 1 + arch/arm/mach-sunxi/dram_sun50i_h6.c | 78 +++++++++++++------ 2 files changed, 54 insertions(+), 25 deletions(-) diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h index 0a1da02376..49a8a66f7b 100644 --- a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h +++ b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h @@ -315,6 +315,7 @@ struct dram_para { u8 cols; u8 rows; u8 ranks; + u8 bus_full_width; const u8 dx_read_delays[NR_OF_BYTE_LANES][RD_LINES_PER_BYTE_LANE]; const u8 dx_write_delays[NR_OF_BYTE_LANES][WR_LINES_PER_BYTE_LANE]; }; diff --git a/arch/arm/mach-sunxi/dram_sun50i_h6.c b/arch/arm/mach-sunxi/dram_sun50i_h6.c index 2a8275da3a..9375db76a1 100644 --- a/arch/arm/mach-sunxi/dram_sun50i_h6.c +++ b/arch/arm/mach-sunxi/dram_sun50i_h6.c @@ -201,6 +201,9 @@ static void mctl_set_addrmap(struct dram_para *para) u8 rows = para->rows; u8 ranks = para->ranks; + if (!para->bus_full_width) + cols -= 1; + /* Ranks */ if (ranks == 2) mctl_ctl->addrmap[0] = rows + cols - 3; @@ -213,6 +216,10 @@ static void mctl_set_addrmap(struct dram_para *para) /* Columns */ mctl_ctl->addrmap[2] = 0; switch (cols) { + case 7: + mctl_ctl->addrmap[3] = 0x1F1F1F00; + mctl_ctl->addrmap[4] = 0x1F1F; + break; case 8: mctl_ctl->addrmap[3] = 0x1F1F0000; mctl_ctl->addrmap[4] = 0x1F1F; @@ -300,13 +307,16 @@ static void mctl_com_init(struct dram_para *para) reg_val = 0x3f00; clrsetbits_le32(&mctl_com->unk_0x008, 0x3f00, reg_val); - /* TODO: half DQ, DDR4 */ - reg_val = MSTR_BUSWIDTH_FULL | MSTR_BURST_LENGTH(8) | - MSTR_ACTIVE_RANKS(para->ranks); + /* TODO: DDR4 */ + reg_val = MSTR_BURST_LENGTH(8) | MSTR_ACTIVE_RANKS(para->ranks); if (para->type == SUNXI_DRAM_TYPE_LPDDR3) reg_val |= MSTR_DEVICETYPE_LPDDR3; if (para->type == SUNXI_DRAM_TYPE_DDR3) reg_val |= MSTR_DEVICETYPE_DDR3 | MSTR_2TMODE; + if (para->bus_full_width) + reg_val |= MSTR_BUSWIDTH_FULL; + else + reg_val |= MSTR_BUSWIDTH_HALF; writel(reg_val | BIT(31), &mctl_ctl->mstr); if (para->type == SUNXI_DRAM_TYPE_LPDDR3) @@ -333,7 +343,10 @@ static void mctl_com_init(struct dram_para *para) } writel(reg_val, &mctl_ctl->odtcfg); - /* TODO: half DQ */ + if (!para->bus_full_width) { + writel(0x0, &mctl_phy->dx[2].gcr[0]); + writel(0x0, &mctl_phy->dx[3].gcr[0]); + } } static void mctl_bit_delay_set(struct dram_para *para) @@ -514,22 +527,35 @@ static void mctl_channel_init(struct dram_para *para) if (readl(&mctl_phy->pgsr[0]) & 0x400000) { - /* - * Detect single rank. - * TODO: also detect half DQ. - */ + /* Check for single rank and optionally half DQ. */ if ((readl(&mctl_phy->dx[0].rsr[0]) & 0x3) == 2 && - (readl(&mctl_phy->dx[1].rsr[0]) & 0x3) == 2 && - (readl(&mctl_phy->dx[2].rsr[0]) & 0x3) == 2 && - (readl(&mctl_phy->dx[3].rsr[0]) & 0x3) == 2) { + (readl(&mctl_phy->dx[1].rsr[0]) & 0x3) == 2) { para->ranks = 1; + + if ((readl(&mctl_phy->dx[2].rsr[0]) & 0x3) != 2 || + (readl(&mctl_phy->dx[3].rsr[0]) & 0x3) != 2) + para->bus_full_width = 0; + /* Restart DRAM initialization from scratch. */ mctl_core_init(para); return; } - else { - panic("This DRAM setup is currently not supported.\n"); + + /* + * Check for dual rank and half DQ. NOTE: This combination + * is highly unlikely and was not tested. Condition is the + * same as in libdram, though. + */ + if ((readl(&mctl_phy->dx[0].rsr[0]) & 0x3) == 0 && + (readl(&mctl_phy->dx[1].rsr[0]) & 0x3) == 0) { + para->bus_full_width = 0; + + /* Restart DRAM initialization from scratch. */ + mctl_core_init(para); + return; } + + panic("This DRAM setup is currently not supported.\n"); } if (readl(&mctl_phy->pgsr[0]) & 0xff00000) { @@ -557,11 +583,8 @@ static void mctl_channel_init(struct dram_para *para) static void mctl_auto_detect_dram_size(struct dram_para *para) { - /* TODO: non-LPDDR3, half DQ */ - /* - * Detect rank number by the code in mctl_channel_init. Furtherly - * when DQ detection is available it will also be executed there. - */ + /* TODO: non-(LP)DDR3 */ + /* Detect rank number and half DQ by the code in mctl_channel_init. */ mctl_core_init(para); /* detect row address bits */ @@ -570,8 +593,9 @@ static void mctl_auto_detect_dram_size(struct dram_para *para) mctl_core_init(para); for (para->rows = 13; para->rows < 18; para->rows++) { - /* 8 banks, 8 bit per byte and 32 bit width */ - if (mctl_mem_matches((1 << (para->rows + para->cols + 5)))) + /* 8 banks, 8 bit per byte and 16/32 bit width */ + if (mctl_mem_matches((1 << (para->rows + para->cols + + 4 + para->bus_full_width)))) break; } @@ -580,18 +604,21 @@ static void mctl_auto_detect_dram_size(struct dram_para *para) mctl_core_init(para); for (para->cols = 8; para->cols < 11; para->cols++) { - /* 8 bits per byte and 32 bit width */ - if (mctl_mem_matches(1 << (para->cols + 2))) + /* 8 bits per byte and 16/32 bit width */ + if (mctl_mem_matches(1 << (para->cols + 1 + + para->bus_full_width))) break; } } unsigned long mctl_calc_size(struct dram_para *para) { - /* TODO: non-LPDDR3, half DQ */ + u8 width = para->bus_full_width ? 4 : 2; - /* 8 banks, 32-bit (4 byte) data width */ - return (1ULL << (para->cols + para->rows + 3)) * 4 * para->ranks; + /* TODO: non-(LP)DDR3 */ + + /* 8 banks */ + return (1ULL << (para->cols + para->rows + 3)) * width * para->ranks; } #define SUN50I_H6_LPDDR3_DX_WRITE_DELAYS \ @@ -625,6 +652,7 @@ unsigned long sunxi_dram_init(void) .ranks = 2, .cols = 11, .rows = 14, + .bus_full_width = 1, #ifdef CONFIG_SUNXI_DRAM_H6_LPDDR3 .type = SUNXI_DRAM_TYPE_LPDDR3, .dx_read_delays = SUN50I_H6_LPDDR3_DX_READ_DELAYS, From 4ed293ae794b42ca216c53706d9476c3f3126197 Mon Sep 17 00:00:00 2001 From: Sunil Mohan Adapa Date: Tue, 10 Sep 2019 11:43:40 -0700 Subject: [PATCH 22/25] arm64: dts: sun50i: Add support for A64 OLinuXino (with eMMC) A64 OLinuXino board from Olimex has three variants with onboard eMMC: A64-OLinuXino-1Ge16GW, A64-OLinuXino-1Ge4GW and A64-OLinuXino-2Ge8G-IND. In addition, there are two variants without eMMC. One without eMMC and one with SPI flash. This suggests the need for separate device tree for the three eMMC variants. The Linux kernel upstream has chosen to create and use a separate device tree for the eMMC variants instead of adding eMMC support existing device tree. These changes to Linux kernel are queued for Linux 5.4. commit <02bb66b347ff8115f53948f86b884e008ba385b9> ("arm64: dts: allwinner: a64: Add A64 OlinuXino board (with eMMC)") This patch has been tested on A64-OLinuXino-1Ge16GW and is based on Linux device-tree and a64-olinuxino_defconfig. Signed-off-by: Sunil Mohan Adapa [jagan: updated linux-next commit details] Signed-off-by: Jagan Teki Reviewed-by: Jagan Teki --- arch/arm/dts/Makefile | 1 + arch/arm/dts/sun50i-a64-olinuxino-emmc.dts | 23 ++++++++++++++++++++++ board/sunxi/MAINTAINERS | 5 +++++ configs/a64-olinuxino-emmc_defconfig | 17 ++++++++++++++++ 4 files changed, 46 insertions(+) create mode 100644 arch/arm/dts/sun50i-a64-olinuxino-emmc.dts create mode 100644 configs/a64-olinuxino-emmc_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 3b8dc2f56f..24e5526637 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -536,6 +536,7 @@ dtb-$(CONFIG_MACH_SUN50I) += \ sun50i-a64-nanopi-a64.dtb \ sun50i-a64-oceanic-5205-5inmfd.dtb \ sun50i-a64-olinuxino.dtb \ + sun50i-a64-olinuxino-emmc.dtb \ sun50i-a64-orangepi-win.dtb \ sun50i-a64-pine64-lts.dtb \ sun50i-a64-pine64-plus.dtb \ diff --git a/arch/arm/dts/sun50i-a64-olinuxino-emmc.dts b/arch/arm/dts/sun50i-a64-olinuxino-emmc.dts new file mode 100644 index 0000000000..96ab0227e8 --- /dev/null +++ b/arch/arm/dts/sun50i-a64-olinuxino-emmc.dts @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2018 Martin Ayotte + * Copyright (C) 2019 Sunil Mohan Adapa + */ + +#include "sun50i-a64-olinuxino.dts" + +/ { + model = "Olimex A64-Olinuxino-eMMC"; + compatible = "olimex,a64-olinuxino-emmc", "allwinner,sun50i-a64"; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins>; + vmmc-supply = <®_dcdc1>; + vqmmc-supply = <®_dcdc1>; + bus-width = <8>; + non-removable; + cap-mmc-hw-reset; + status = "okay"; +}; diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index 88f13533b8..a2adf89b5d 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -106,6 +106,11 @@ M: Jagan Teki S: Maintained F: configs/a64-olinuxino_defconfig +A64-OLINUXINO-EMMC BOARD +M: Sunil Mohan Adapa +S: Maintained +F: configs/a64-olinuxino-emmc_defconfig + A80 OPTIMUS BOARD M: Chen-Yu Tsai S: Maintained diff --git a/configs/a64-olinuxino-emmc_defconfig b/configs/a64-olinuxino-emmc_defconfig new file mode 100644 index 0000000000..56153e38a7 --- /dev/null +++ b/configs/a64-olinuxino-emmc_defconfig @@ -0,0 +1,17 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SPL=y +CONFIG_MACH_SUN50I=y +CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y +CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y +# CONFIG_CMD_FLASH is not set +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-olinuxino-emmc" +CONFIG_SUN8I_EMAC=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_OHCI_HCD=y +CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y From e6467df1eb3acc238c14a712c46c41bd5c9b1e52 Mon Sep 17 00:00:00 2001 From: Stefan Mavrodiev Date: Wed, 31 Jul 2019 16:15:52 +0300 Subject: [PATCH 23/25] sunxi: Fix pll1 clock calculation clock_sun6i.c is used for sun6i, sun8i and sun50i SoC families. PLL1 clock sets the default system clock, defined as: sun6i: 1008000000 sun8i: 1008000000 sun50i: 816000000 With the current calculation, m = 2 and k = 3. Solving for n, this results 28. Solving back: (24MHz * 28 * 3) / 2 = 1008MHz However if the requested clock is 816, n is 22.66 rounded to 22, which results: (24MHz * 28 * 3) / 2 = 792MHz Changing k to 4 satisfies both system clocks: (24E6 * 21 * 4) / 2 = 1008MHz (24E6 * 17 * 4) / 2 = 816MHz Signed-off-by: Stefan Mavrodiev Acked-by: Jagan Teki --- arch/arm/mach-sunxi/clock_sun6i.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-sunxi/clock_sun6i.c b/arch/arm/mach-sunxi/clock_sun6i.c index 1628f3a7b6..6ca38f73d9 100644 --- a/arch/arm/mach-sunxi/clock_sun6i.c +++ b/arch/arm/mach-sunxi/clock_sun6i.c @@ -118,7 +118,7 @@ void clock_set_pll1(unsigned int clk) if (clk > 1152000000) { k = 2; } else if (clk > 768000000) { - k = 3; + k = 4; m = 2; } From cf05b4b86c60b1083661d8eddb024172923479f1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Cl=C3=A9ment=20P=C3=A9ron?= Date: Sun, 25 Aug 2019 18:04:18 +0200 Subject: [PATCH 24/25] arm: dts: sync dts for Allwinner H6 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sync Kernel DTS for Allwinner H6 boards. Drop /omit-if-no-ref/ keyword as it's not supported by U-boot. commit Linux 5.3-rc4 Signed-off-by: Clément Péron Acked-by: Maxime Ripard Reviewed-by: Jagan Teki --- arch/arm/dts/sun50i-h6-beelink-gs1.dts | 76 ++++++++++++++++++++++++++ arch/arm/dts/sun50i-h6-pine-h64.dts | 12 ++++ arch/arm/dts/sun50i-h6.dtsi | 46 +++++++++++++++- 3 files changed, 131 insertions(+), 3 deletions(-) diff --git a/arch/arm/dts/sun50i-h6-beelink-gs1.dts b/arch/arm/dts/sun50i-h6-beelink-gs1.dts index 54b0882bed..0dc33c90dd 100644 --- a/arch/arm/dts/sun50i-h6-beelink-gs1.dts +++ b/arch/arm/dts/sun50i-h6-beelink-gs1.dts @@ -14,6 +14,7 @@ compatible = "azw,beelink-gs1", "allwinner,sun50i-h6"; aliases { + ethernet0 = &emac; serial0 = &uart0; }; @@ -21,6 +22,17 @@ stdout-path = "serial0:115200n8"; }; + connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + leds { compatible = "gpio-leds"; @@ -41,6 +53,40 @@ }; }; +&de { + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&ext_rgmii_pins>; + phy-mode = "rgmii"; + phy-handle = <&ext_rgmii_phy>; + phy-supply = <®_aldo2>; + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&mdio { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; + &mmc0 { vmmc-supply = <®_cldo1>; cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; @@ -57,6 +103,15 @@ status = "okay"; }; +&ohci0 { + status = "okay"; +}; + +&pio { + vcc-pd-supply = <®_cldo1>; + vcc-pg-supply = <®_aldo1>; +}; + &r_i2c { status = "okay"; @@ -177,8 +232,29 @@ }; }; +&r_pio { + /* + * PL0 and PL1 are used for PMIC I2C + * don't enable the pl-supply else + * it will fail at boot + * + * vcc-pl-supply = <®_aldo1>; + */ + vcc-pm-supply = <®_aldo1>; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_ph_pins>; status = "okay"; }; + +&usb2otg { + dr_mode = "host"; + status = "okay"; +}; + +&usb2phy { + usb0_vbus-supply = <®_vcc5v>; + status = "okay"; +}; diff --git a/arch/arm/dts/sun50i-h6-pine-h64.dts b/arch/arm/dts/sun50i-h6-pine-h64.dts index 4802902e12..1898345183 100644 --- a/arch/arm/dts/sun50i-h6-pine-h64.dts +++ b/arch/arm/dts/sun50i-h6-pine-h64.dts @@ -127,6 +127,12 @@ status = "okay"; }; +&pio { + vcc-pc-supply = <®_bldo2>; + vcc-pd-supply = <®_cldo1>; + vcc-pg-supply = <®_aldo1>; +}; + &r_i2c { status = "okay"; @@ -243,10 +249,16 @@ pcf8563: rtc@51 { compatible = "nxp,pcf8563"; reg = <0x51>; + interrupt-parent = <&r_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; #clock-cells = <0>; }; }; +&r_pio { + vcc-pm-supply = <®_aldo1>; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_ph_pins>; diff --git a/arch/arm/dts/sun50i-h6.dtsi b/arch/arm/dts/sun50i-h6.dtsi index e0dc4a05c1..a117f479ae 100644 --- a/arch/arm/dts/sun50i-h6.dtsi +++ b/arch/arm/dts/sun50i-h6.dtsi @@ -101,7 +101,7 @@ #size-cells = <1>; ranges; - display-engine@1000000 { + bus@1000000 { compatible = "allwinner,sun50i-h6-de3", "allwinner,sun50i-a64-de2"; reg = <0x1000000 0x400000>; @@ -203,11 +203,32 @@ #reset-cells = <1>; }; + dma: dma-controller@3002000 { + compatible = "allwinner,sun50i-h6-dma"; + reg = <0x03002000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>; + clock-names = "bus", "mbus"; + dma-channels = <16>; + dma-requests = <46>; + resets = <&ccu RST_BUS_DMA>; + #dma-cells = <1>; + }; + sid: sid@3006000 { compatible = "allwinner,sun50i-h6-sid"; reg = <0x03006000 0x400>; }; + watchdog: watchdog@30090a0 { + compatible = "allwinner,sun50i-h6-wdt", + "allwinner,sun6i-a31-wdt"; + reg = <0x030090a0 0x20>; + interrupts = ; + /* Broken on some H6 boards */ + status = "disabled"; + }; + pio: pinctrl@300b000 { compatible = "allwinner,sun50i-h6-pinctrl"; reg = <0x0300b000 0x400>; @@ -243,6 +264,18 @@ bias-pull-up; }; + /* + * /omit-if-no-ref/ isn't supported by U-boot + * keep this comment to avoid bad sync with Linux + */ + mmc1_pins: mmc1-pins { + pins = "PG0", "PG1", "PG2", "PG3", + "PG4", "PG5"; + function = "mmc1"; + drive-strength = <30>; + bias-pull-up; + }; + mmc2_pins: mmc2-pins { pins = "PC1", "PC4", "PC5", "PC6", "PC7", "PC8", "PC9", "PC10", @@ -294,6 +327,8 @@ resets = <&ccu RST_BUS_MMC1>; reset-names = "ahb"; interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -445,7 +480,6 @@ resets = <&ccu RST_BUS_OHCI3>, <&ccu RST_BUS_EHCI3>; phys = <&usb2phy 3>; - phy-names = "usb"; status = "disabled"; }; @@ -457,7 +491,6 @@ <&ccu CLK_USB_OHCI3>; resets = <&ccu RST_BUS_OHCI3>; phys = <&usb2phy 3>; - phy-names = "usb"; status = "disabled"; }; @@ -613,6 +646,13 @@ #reset-cells = <1>; }; + r_watchdog: watchdog@7020400 { + compatible = "allwinner,sun50i-h6-wdt", + "allwinner,sun6i-a31-wdt"; + reg = <0x07020400 0x20>; + interrupts = ; + }; + r_intc: interrupt-controller@7021000 { compatible = "allwinner,sun50i-h6-r-intc", "allwinner,sun6i-a31-r-intc"; From 5f19c9302133cda54d5d1a6b1caa400260de9192 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Wed, 24 Apr 2019 13:44:12 +0800 Subject: [PATCH 25/25] sunxi: set PIO voltage to hardware-detected value on startup on H6 The Allwinner H6 SoC has a register to set the PIO banks' voltage. When it mismatches the real voltage supplied to the VCC to the PIO supply, the PIO will work improperly. The PIO controller also has a register that contains the status of each VCC rail of the PIO supplies, and it has the same definition with the configuration register. so we can just copy the content of this register to the configuration register at startup, to ensure the configuration is correct at startup stage. Signed-off-by: Icenowy Zheng [jagan: s/__maybe__unused/__maybe_unused] Signed-off-by: Jagan Teki Acked-by: Jagan Teki --- arch/arm/include/asm/arch-sunxi/gpio.h | 3 +++ arch/arm/mach-sunxi/board.c | 9 +++++++++ 2 files changed, 12 insertions(+) diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h index 40a3f845d0..a646ea6a3c 100644 --- a/arch/arm/include/asm/arch-sunxi/gpio.h +++ b/arch/arm/include/asm/arch-sunxi/gpio.h @@ -73,6 +73,9 @@ struct sunxi_gpio_reg { struct sunxi_gpio_int gpio_int; }; +#define SUN50I_H6_GPIO_POW_MOD_SEL 0x340 +#define SUN50I_H6_GPIO_POW_MOD_VAL 0x348 + #define BANK_TO_GPIO(bank) (((bank) < SUNXI_GPIO_L) ? \ &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank] : \ &((struct sunxi_gpio_reg *)SUNXI_R_PIO_BASE)->gpio_bank[(bank) - SUNXI_GPIO_L]) diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c index 8e9bb63d9d..db506367bf 100644 --- a/arch/arm/mach-sunxi/board.c +++ b/arch/arm/mach-sunxi/board.c @@ -65,6 +65,7 @@ struct mm_region *mem_map = sunxi_mem_map; static int gpio_init(void) { + __maybe_unused uint val; #if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F) #if defined(CONFIG_MACH_SUN4I) || \ defined(CONFIG_MACH_SUN7I) || \ @@ -139,6 +140,14 @@ static int gpio_init(void) #error Unsupported console port number. Please fix pin mux settings in board.c #endif +#ifdef CONFIG_MACH_SUN50I_H6 + /* Update PIO power bias configuration by copy hardware detected value */ + val = readl(SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL); + writel(val, SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL); + val = readl(SUNXI_R_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL); + writel(val, SUNXI_R_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL); +#endif + return 0; }