Merge branch 'master' of git://git.denx.de/u-boot-tegra
This commit is contained in:
Tom Rini
@@ -104,6 +104,8 @@ static inline int bootm_maybe_autostart(cmd_tbl_t *cmdtp, const char *cmd)
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extern int do_bootz(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
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extern int do_booti(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
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extern int common_diskboot(cmd_tbl_t *cmdtp, const char *intf, int argc,
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char *const argv[]);
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75
include/configs/p2571.h
Normal file
75
include/configs/p2571.h
Normal file
@@ -0,0 +1,75 @@
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/*
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* (C) Copyright 2013-2015
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* NVIDIA Corporation <www.nvidia.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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||||
#ifndef _P2571_H
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#define _P2571_H
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#include <linux/sizes.h>
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/* enable PMIC */
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#define CONFIG_MAX77620_POWER
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#include "tegra210-common.h"
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/* High-level configuration options */
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#define V_PROMPT "Tegra210 (P2571) # "
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#define CONFIG_TEGRA_BOARD_STRING "NVIDIA P2571"
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/* Board-specific serial config */
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#define CONFIG_SERIAL_MULTI
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#define CONFIG_TEGRA_ENABLE_UARTA
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#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
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/* I2C */
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#define CONFIG_SYS_I2C_TEGRA
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#define CONFIG_CMD_I2C
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/* SD/MMC */
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#define CONFIG_MMC
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#define CONFIG_GENERIC_MMC
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#define CONFIG_TEGRA_MMC
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#define CONFIG_CMD_MMC
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/* Environment in eMMC, at the end of 2nd "boot sector" */
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#define CONFIG_ENV_IS_IN_MMC
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#define CONFIG_SYS_MMC_ENV_DEV 0
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#define CONFIG_SYS_MMC_ENV_PART 2
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#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
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/* SPI */
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#define CONFIG_TEGRA114_SPI /* Compatible w/ Tegra114 SPI */
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#define CONFIG_TEGRA114_SPI_CTRLS 6
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#define CONFIG_SPI_FLASH_WINBOND
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#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
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#define CONFIG_SF_DEFAULT_SPEED 24000000
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#define CONFIG_CMD_SPI
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#define CONFIG_CMD_SF
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#define CONFIG_SPI_FLASH_SIZE (4 << 20)
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/* USB2.0 Host support */
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#define CONFIG_USB_EHCI
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#define CONFIG_USB_EHCI_TEGRA
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#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
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#define CONFIG_USB_STORAGE
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#define CONFIG_CMD_USB
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/* USB networking support */
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#define CONFIG_USB_HOST_ETHER
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#define CONFIG_USB_ETHER_ASIX
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/* General networking support */
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#define CONFIG_CMD_DHCP
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/*
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* TODO(twarren@nvidia.com) - add tegra-common-usb-gadget.h back
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* breaks 64-bit build in ci_udc.c
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*/
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#include "tegra-common-post.h"
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#define COUNTER_FREQUENCY 38400000
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#endif /* _P2571_H */
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@@ -62,11 +62,19 @@
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#define CONFIG_CHROMEOS_EXTRA_ENV_SETTINGS
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#endif
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#ifdef CONFIG_ARM64
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#define FDT_HIGH "ffffffffffffffff"
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#define INITRD_HIGH "ffffffffffffffff"
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#else
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#define FDT_HIGH "ffffffff"
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#define INITRD_HIGH "ffffffff"
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#endif
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#define CONFIG_EXTRA_ENV_SETTINGS \
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TEGRA_DEVICE_SETTINGS \
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MEM_LAYOUT_ENV_SETTINGS \
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"fdt_high=ffffffff\0" \
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"initrd_high=ffffffff\0" \
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"fdt_high=" FDT_HIGH "\0" \
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"initrd_high=" INITRD_HIGH "\0" \
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BOOTENV \
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BOARD_EXTRA_ENV_SETTINGS \
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CONFIG_CHROMEOS_EXTRA_ENV_SETTINGS
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@@ -18,8 +18,11 @@
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#include <asm/arch/tegra.h> /* get chip and board defs */
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/* Use the Tegra US timer on ARMv7, but the architected timer on ARMv8. */
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#ifndef CONFIG_ARM64
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||||
#define CONFIG_SYS_TIMER_RATE 1000000
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#define CONFIG_SYS_TIMER_COUNTER NV_PA_TMRUS_BASE
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#endif
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||||
/*
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||||
* Display CPU and Board information
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@@ -43,7 +46,9 @@
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#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4MB */
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#endif
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#ifndef CONFIG_ARM64
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#define CONFIG_SYS_NONCACHED_MEMORY (1 << 20) /* 1 MiB */
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||||
#endif
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||||
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||||
/*
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||||
* NS16550 Configuration
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||||
@@ -101,9 +106,11 @@
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#define CONFIG_SYS_MEMTEST_START (NV_PA_SDRC_CS0 + 0x600000)
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#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x100000)
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#ifndef CONFIG_ARM64
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#ifndef CONFIG_SPL_BUILD
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#define CONFIG_USE_ARCH_MEMCPY
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#endif
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#endif
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/*-----------------------------------------------------------------------
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* Physical Memory Map
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@@ -26,7 +26,7 @@
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/*-----------------------------------------------------------------------
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||||
* Physical Memory Map
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||||
*/
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||||
#define CONFIG_SYS_TEXT_BASE 0x8010E000
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#define CONFIG_SYS_TEXT_BASE 0x80110000
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||||
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||||
/*
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* Memory layout for where various images get loaded by boot scripts:
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76
include/configs/tegra210-common.h
Normal file
76
include/configs/tegra210-common.h
Normal file
@@ -0,0 +1,76 @@
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/*
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* (C) Copyright 2013-2015
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* NVIDIA Corporation <www.nvidia.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _TEGRA210_COMMON_H_
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#define _TEGRA210_COMMON_H_
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#include "tegra-common.h"
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/* Cortex-A57 uses a cache line size of 64 bytes */
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#define CONFIG_SYS_CACHELINE_SIZE 64
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||||
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||||
/*
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||||
* NS16550 Configuration
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||||
*/
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||||
#define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */
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||||
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||||
/*
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||||
* Miscellaneous configurable options
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||||
*/
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||||
#define CONFIG_STACKBASE 0x82800000 /* 40MB */
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||||
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||||
/*-----------------------------------------------------------------------
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||||
* Physical Memory Map
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||||
*/
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||||
#define CONFIG_SYS_TEXT_BASE 0x8010E000
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||||
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/* Generic Interrupt Controller */
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#define CONFIG_GICV2
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/*
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||||
* Memory layout for where various images get loaded by boot scripts:
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||||
*
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* scriptaddr can be pretty much anywhere that doesn't conflict with something
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* else. Put it above BOOTMAPSZ to eliminate conflicts.
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*
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* pxefile_addr_r can be pretty much anywhere that doesn't conflict with
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* something else. Put it above BOOTMAPSZ to eliminate conflicts.
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||||
*
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||||
* kernel_addr_r must be within the first 128M of RAM in order for the
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* kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
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* decompress itself to 0x8000 after the start of RAM, kernel_addr_r
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||||
* should not overlap that area, or the kernel will have to copy itself
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||||
* somewhere else before decompression. Similarly, the address of any other
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* data passed to the kernel shouldn't overlap the start of RAM. Pushing
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* this up to 16M allows for a sizable kernel to be decompressed below the
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* compressed load address.
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*
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* fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for
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* the compressed kernel to be up to 16M too.
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*
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* ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
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* for the FDT/DTB to be up to 1M, which is hopefully plenty.
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*/
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#define CONFIG_LOADADDR 0x81000000
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#define MEM_LAYOUT_ENV_SETTINGS \
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"scriptaddr=0x90000000\0" \
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"pxefile_addr_r=0x90100000\0" \
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"kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
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"fdt_addr_r=0x82000000\0" \
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"ramdisk_addr_r=0x82100000\0"
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/* Defines for SPL */
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#define CONFIG_SPL_TEXT_BASE 0x80108000
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#define CONFIG_SYS_SPL_MALLOC_START 0x80090000
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#define CONFIG_SPL_STACK 0x800ffffc
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/* For USB EHCI controller */
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#define CONFIG_EHCI_IS_TDI
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#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10
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#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
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#endif /* _TEGRA210_COMMON_H_ */
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342
include/dt-bindings/clock/tegra210-car.h
Normal file
342
include/dt-bindings/clock/tegra210-car.h
Normal file
@@ -0,0 +1,342 @@
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/*
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* This header provides Tegra210-specific constants for binding
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* nvidia,tegra210-car.
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*/
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#ifndef _DT_BINDINGS_CLOCK_TEGRA210_CAR_H
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#define _DT_BINDINGS_CLOCK_TEGRA210_CAR_H
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/* 0 */
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/* 1 */
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/* 2 */
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#define TEGRA210_CLK_ISPB 3
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#define TEGRA210_CLK_RTC 4
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#define TEGRA210_CLK_TIMER 5
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#define TEGRA210_CLK_UARTA 6
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/* 7 (register bit affects uartb and vfir) */
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/* 8 */
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#define TEGRA210_CLK_SDMMC2 9
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/* 10 (register bit affects spdif_in and spdif_out) */
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#define TEGRA210_CLK_I2S1 11
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#define TEGRA210_CLK_I2C1 12
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/* 13 */
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#define TEGRA210_CLK_SDMMC1 14
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#define TEGRA210_CLK_SDMMC4 15
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/* 16 */
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#define TEGRA210_CLK_PWM 17
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#define TEGRA210_CLK_I2S2 18
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/* 20 (register bit affects vi and vi_sensor) */
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/* 21 */
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#define TEGRA210_CLK_USBD 22
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#define TEGRA210_CLK_ISP 23
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/* 26 */
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/* 25 */
|
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#define TEGRA210_CLK_DISP2 26
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#define TEGRA210_CLK_DISP1 27
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#define TEGRA210_CLK_HOST1X 28
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#define TEGRA210_CLK_VCP 29
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#define TEGRA210_CLK_I2S0 30
|
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/* 31 */
|
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|
||||
#define TEGRA210_CLK_MC 32
|
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/* 33 */
|
||||
#define TEGRA210_CLK_APBDMA 34
|
||||
/* 35 */
|
||||
#define TEGRA210_CLK_KBC 36
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/* 37 */
|
||||
/* 38 */
|
||||
/* 39 (register bit affects fuse and fuse_burn) */
|
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#define TEGRA210_CLK_KFUSE 40
|
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#define TEGRA210_CLK_SBC1 41
|
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#define TEGRA210_CLK_NOR 42
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/* 43 */
|
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#define TEGRA210_CLK_SBC2 44
|
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/* 45 */
|
||||
#define TEGRA210_CLK_SBC3 46
|
||||
#define TEGRA210_CLK_I2C5 47
|
||||
#define TEGRA210_CLK_DSIA 48
|
||||
/* 49 */
|
||||
#define TEGRA210_CLK_MIPI 50
|
||||
#define TEGRA210_CLK_HDMI 51
|
||||
#define TEGRA210_CLK_CSI 52
|
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/* 53 */
|
||||
#define TEGRA210_CLK_I2C2 54
|
||||
#define TEGRA210_CLK_UARTC 55
|
||||
#define TEGRA210_CLK_MIPI_CAL 56
|
||||
#define TEGRA210_CLK_EMC 57
|
||||
#define TEGRA210_CLK_USB2 58
|
||||
#define TEGRA210_CLK_USB3 59
|
||||
/* 60 */
|
||||
#define TEGRA210_CLK_VDE 61
|
||||
#define TEGRA210_CLK_BSEA 62
|
||||
#define TEGRA210_CLK_BSEV 63
|
||||
|
||||
/* 64 */
|
||||
#define TEGRA210_CLK_UARTD 65
|
||||
/* 66 */
|
||||
#define TEGRA210_CLK_I2C3 67
|
||||
#define TEGRA210_CLK_SBC4 68
|
||||
#define TEGRA210_CLK_SDMMC3 69
|
||||
#define TEGRA210_CLK_PCIE 70
|
||||
#define TEGRA210_CLK_OWR 71
|
||||
#define TEGRA210_CLK_AFI 72
|
||||
#define TEGRA210_CLK_CSITE 73
|
||||
/* 74 */
|
||||
/* 75 */
|
||||
#define TEGRA210_CLK_LA 76
|
||||
#define TEGRA210_CLK_TRACE 77
|
||||
#define TEGRA210_CLK_SOC_THERM 78
|
||||
#define TEGRA210_CLK_DTV 79
|
||||
/* 80 */
|
||||
#define TEGRA210_CLK_I2CSLOW 81
|
||||
#define TEGRA210_CLK_DSIB 82
|
||||
#define TEGRA210_CLK_TSEC 83
|
||||
/* 84 */
|
||||
/* 85 */
|
||||
/* 86 */
|
||||
/* 87 */
|
||||
/* 88 */
|
||||
#define TEGRA210_CLK_XUSB_HOST 89
|
||||
/* 90 */
|
||||
#define TEGRA210_CLK_MSENC 91
|
||||
#define TEGRA210_CLK_CSUS 92
|
||||
/* 93 */
|
||||
/* 94 */
|
||||
/* 95 (bit affects xusb_dev and xusb_dev_src) */
|
||||
|
||||
/* 96 */
|
||||
/* 97 */
|
||||
/* 98 */
|
||||
#define TEGRA210_CLK_MSELECT 99
|
||||
#define TEGRA210_CLK_TSENSOR 100
|
||||
#define TEGRA210_CLK_I2S3 101
|
||||
#define TEGRA210_CLK_I2S4 102
|
||||
#define TEGRA210_CLK_I2C4 103
|
||||
#define TEGRA210_CLK_SBC5 104
|
||||
#define TEGRA210_CLK_SBC6 105
|
||||
#define TEGRA210_CLK_D_AUDIO 106
|
||||
#define TEGRA210_CLK_APBIF 107
|
||||
#define TEGRA210_CLK_DAM0 108
|
||||
#define TEGRA210_CLK_DAM1 109
|
||||
#define TEGRA210_CLK_DAM2 110
|
||||
#define TEGRA210_CLK_HDA2CODEC_2X 111
|
||||
/* 112 */
|
||||
#define TEGRA210_CLK_AUDIO0_2X 113
|
||||
#define TEGRA210_CLK_AUDIO1_2X 114
|
||||
#define TEGRA210_CLK_AUDIO2_2X 115
|
||||
#define TEGRA210_CLK_AUDIO3_2X 116
|
||||
#define TEGRA210_CLK_AUDIO4_2X 117
|
||||
#define TEGRA210_CLK_SPDIF_2X 118
|
||||
#define TEGRA210_CLK_ACTMON 119
|
||||
#define TEGRA210_CLK_EXTERN1 120
|
||||
#define TEGRA210_CLK_EXTERN2 121
|
||||
#define TEGRA210_CLK_EXTERN3 122
|
||||
#define TEGRA210_CLK_SATA_OOB 123
|
||||
#define TEGRA210_CLK_SATA 124
|
||||
#define TEGRA210_CLK_HDA 125
|
||||
/* 126 */
|
||||
#define TEGRA210_CLK_SE 127
|
||||
|
||||
#define TEGRA210_CLK_HDA2HDMI 128
|
||||
#define TEGRA210_CLK_SATA_COLD 129
|
||||
/* 130 */
|
||||
/* 131 */
|
||||
/* 132 */
|
||||
/* 133 */
|
||||
/* 134 */
|
||||
/* 135 */
|
||||
/* 136 */
|
||||
/* 137 */
|
||||
/* 138 */
|
||||
/* 139 */
|
||||
/* 140 */
|
||||
/* 141 */
|
||||
/* 142 */
|
||||
/* 143 (bit affects xusb_falcon_src, xusb_fs_src, */
|
||||
/* xusb_host_src and xusb_ss_src) */
|
||||
#define TEGRA210_CLK_CILAB 144
|
||||
#define TEGRA210_CLK_CILCD 145
|
||||
#define TEGRA210_CLK_CILE 146
|
||||
#define TEGRA210_CLK_DSIALP 147
|
||||
#define TEGRA210_CLK_DSIBLP 148
|
||||
#define TEGRA210_CLK_ENTROPY 149
|
||||
#define TEGRA210_CLK_DDS 150
|
||||
/* 151 */
|
||||
#define TEGRA210_CLK_DP2 152
|
||||
#define TEGRA210_CLK_AMX 153
|
||||
#define TEGRA210_CLK_ADX 154
|
||||
/* 155 (bit affects dfll_ref and dfll_soc) */
|
||||
#define TEGRA210_CLK_XUSB_SS 156
|
||||
/* 157 */
|
||||
/* 158 */
|
||||
/* 159 */
|
||||
|
||||
/* 160 */
|
||||
/* 161 */
|
||||
/* 162 */
|
||||
/* 163 */
|
||||
/* 164 */
|
||||
/* 165 */
|
||||
#define TEGRA210_CLK_I2C6 166
|
||||
/* 167 */
|
||||
/* 168 */
|
||||
/* 169 */
|
||||
/* 170 */
|
||||
#define TEGRA210_CLK_VIM2_CLK 171
|
||||
/* 172 */
|
||||
/* 173 */
|
||||
/* 174 */
|
||||
/* 175 */
|
||||
#define TEGRA210_CLK_HDMI_AUDIO 176
|
||||
#define TEGRA210_CLK_CLK72MHZ 177
|
||||
#define TEGRA210_CLK_VIC03 178
|
||||
/* 179 */
|
||||
#define TEGRA210_CLK_ADX1 180
|
||||
#define TEGRA210_CLK_DPAUX 181
|
||||
#define TEGRA210_CLK_SOR0 182
|
||||
/* 183 */
|
||||
#define TEGRA210_CLK_GPU 184
|
||||
#define TEGRA210_CLK_AMX1 185
|
||||
/* 186 */
|
||||
/* 187 */
|
||||
/* 188 */
|
||||
/* 189 */
|
||||
/* 190 */
|
||||
/* 191 */
|
||||
#define TEGRA210_CLK_UARTB 192
|
||||
#define TEGRA210_CLK_VFIR 193
|
||||
#define TEGRA210_CLK_SPDIF_IN 194
|
||||
#define TEGRA210_CLK_SPDIF_OUT 195
|
||||
#define TEGRA210_CLK_VI 196
|
||||
#define TEGRA210_CLK_VI_SENSOR 197
|
||||
#define TEGRA210_CLK_FUSE 198
|
||||
#define TEGRA210_CLK_FUSE_BURN 199
|
||||
#define TEGRA210_CLK_CLK_32K 200
|
||||
#define TEGRA210_CLK_CLK_M 201
|
||||
#define TEGRA210_CLK_CLK_M_DIV2 202
|
||||
#define TEGRA210_CLK_CLK_M_DIV4 203
|
||||
#define TEGRA210_CLK_PLL_REF 204
|
||||
#define TEGRA210_CLK_PLL_C 205
|
||||
#define TEGRA210_CLK_PLL_C_OUT1 206
|
||||
#define TEGRA210_CLK_PLL_C2 207
|
||||
#define TEGRA210_CLK_PLL_C3 208
|
||||
#define TEGRA210_CLK_PLL_M 209
|
||||
#define TEGRA210_CLK_PLL_M_OUT1 210
|
||||
#define TEGRA210_CLK_PLL_P 211
|
||||
#define TEGRA210_CLK_PLL_P_OUT1 212
|
||||
#define TEGRA210_CLK_PLL_P_OUT2 213
|
||||
#define TEGRA210_CLK_PLL_P_OUT3 214
|
||||
#define TEGRA210_CLK_PLL_P_OUT4 215
|
||||
#define TEGRA210_CLK_PLL_A 216
|
||||
#define TEGRA210_CLK_PLL_A_OUT0 217
|
||||
#define TEGRA210_CLK_PLL_D 218
|
||||
#define TEGRA210_CLK_PLL_D_OUT0 219
|
||||
#define TEGRA210_CLK_PLL_D2 220
|
||||
#define TEGRA210_CLK_PLL_D2_OUT0 221
|
||||
#define TEGRA210_CLK_PLL_U 222
|
||||
#define TEGRA210_CLK_PLL_U_480M 223
|
||||
|
||||
#define TEGRA210_CLK_PLL_U_60M 224
|
||||
#define TEGRA210_CLK_PLL_U_48M 225
|
||||
#define TEGRA210_CLK_PLL_U_12M 226
|
||||
/* 227 */
|
||||
/* 228 */
|
||||
#define TEGRA210_CLK_PLL_RE_VCO 229
|
||||
#define TEGRA210_CLK_PLL_RE_OUT 230
|
||||
#define TEGRA210_CLK_PLL_E 231
|
||||
#define TEGRA210_CLK_SPDIF_IN_SYNC 232
|
||||
#define TEGRA210_CLK_I2S0_SYNC 233
|
||||
#define TEGRA210_CLK_I2S1_SYNC 234
|
||||
#define TEGRA210_CLK_I2S2_SYNC 235
|
||||
#define TEGRA210_CLK_I2S3_SYNC 236
|
||||
#define TEGRA210_CLK_I2S4_SYNC 237
|
||||
#define TEGRA210_CLK_VIMCLK_SYNC 238
|
||||
#define TEGRA210_CLK_AUDIO0 239
|
||||
#define TEGRA210_CLK_AUDIO1 240
|
||||
#define TEGRA210_CLK_AUDIO2 241
|
||||
#define TEGRA210_CLK_AUDIO3 242
|
||||
#define TEGRA210_CLK_AUDIO4 243
|
||||
#define TEGRA210_CLK_SPDIF 244
|
||||
#define TEGRA210_CLK_CLK_OUT_1 245
|
||||
#define TEGRA210_CLK_CLK_OUT_2 246
|
||||
#define TEGRA210_CLK_CLK_OUT_3 247
|
||||
#define TEGRA210_CLK_BLINK 248
|
||||
/* 249 */
|
||||
/* 250 */
|
||||
/* 251 */
|
||||
#define TEGRA210_CLK_XUSB_HOST_SRC 252
|
||||
#define TEGRA210_CLK_XUSB_FALCON_SRC 253
|
||||
#define TEGRA210_CLK_XUSB_FS_SRC 254
|
||||
#define TEGRA210_CLK_XUSB_SS_SRC 255
|
||||
|
||||
#define TEGRA210_CLK_XUSB_DEV_SRC 256
|
||||
#define TEGRA210_CLK_XUSB_DEV 257
|
||||
#define TEGRA210_CLK_XUSB_HS_SRC 258
|
||||
#define TEGRA210_CLK_SCLK 259
|
||||
#define TEGRA210_CLK_HCLK 260
|
||||
#define TEGRA210_CLK_PCLK 261
|
||||
/* 262 */
|
||||
/* 263 */
|
||||
#define TEGRA210_CLK_DFLL_REF 264
|
||||
#define TEGRA210_CLK_DFLL_SOC 265
|
||||
#define TEGRA210_CLK_VI_SENSOR2 266
|
||||
#define TEGRA210_CLK_PLL_P_OUT5 267
|
||||
#define TEGRA210_CLK_CML0 268
|
||||
#define TEGRA210_CLK_CML1 269
|
||||
#define TEGRA210_CLK_PLL_C4 270
|
||||
#define TEGRA210_CLK_PLL_DP 271
|
||||
#define TEGRA210_CLK_PLL_E_MUX 272
|
||||
#define TEGRA210_CLK_PLLD_DSI 273
|
||||
/* 274 */
|
||||
/* 275 */
|
||||
/* 276 */
|
||||
/* 277 */
|
||||
/* 278 */
|
||||
/* 279 */
|
||||
/* 280 */
|
||||
/* 281 */
|
||||
/* 282 */
|
||||
/* 283 */
|
||||
/* 284 */
|
||||
/* 285 */
|
||||
/* 286 */
|
||||
/* 287 */
|
||||
|
||||
/* 288 */
|
||||
/* 289 */
|
||||
/* 290 */
|
||||
/* 291 */
|
||||
/* 292 */
|
||||
/* 293 */
|
||||
/* 294 */
|
||||
/* 295 */
|
||||
/* 296 */
|
||||
/* 297 */
|
||||
/* 298 */
|
||||
/* 299 */
|
||||
#define TEGRA210_CLK_AUDIO0_MUX 300
|
||||
#define TEGRA210_CLK_AUDIO1_MUX 301
|
||||
#define TEGRA210_CLK_AUDIO2_MUX 302
|
||||
#define TEGRA210_CLK_AUDIO3_MUX 303
|
||||
#define TEGRA210_CLK_AUDIO4_MUX 304
|
||||
#define TEGRA210_CLK_SPDIF_MUX 305
|
||||
#define TEGRA210_CLK_CLK_OUT_1_MUX 306
|
||||
#define TEGRA210_CLK_CLK_OUT_2_MUX 307
|
||||
#define TEGRA210_CLK_CLK_OUT_3_MUX 308
|
||||
/* 309 */
|
||||
/* 310 */
|
||||
#define TEGRA210_CLK_SOR0_LVDS 311
|
||||
#define TEGRA210_CLK_XUSB_SS_DIV2 312
|
||||
|
||||
#define TEGRA210_CLK_PLL_M_UD 313
|
||||
#define TEGRA210_CLK_PLL_C_UD 314
|
||||
|
||||
#define TEGRA210_CLK_PLL_X 227
|
||||
#define TEGRA210_CLK_PLL_X_OUT0 228
|
||||
|
||||
#define TEGRA210_CLK_CCLK_G 262
|
||||
#define TEGRA210_CLK_CCLK_LP 263
|
||||
|
||||
#define TEGRA210_CLK_CLK_MAX 315
|
||||
|
||||
#endif /* _DT_BINDINGS_CLOCK_TEGRA210_CAR_H */
|
||||
@@ -137,6 +137,7 @@ enum fdt_compat_id {
|
||||
COMPAT_NVIDIA_TEGRA124_SOR, /* Tegra 124 Serial Output Resource */
|
||||
COMPAT_NVIDIA_TEGRA124_PMC, /* Tegra 124 power mgmt controller */
|
||||
COMPAT_NVIDIA_TEGRA20_DC, /* Tegra 2 Display controller */
|
||||
COMPAT_NVIDIA_TEGRA210_SDMMC, /* Tegra210 SDMMC controller */
|
||||
COMPAT_NVIDIA_TEGRA124_SDMMC, /* Tegra124 SDMMC controller */
|
||||
COMPAT_NVIDIA_TEGRA30_SDMMC, /* Tegra30 SDMMC controller */
|
||||
COMPAT_NVIDIA_TEGRA20_SDMMC, /* Tegra20 SDMMC controller */
|
||||
@@ -145,6 +146,8 @@ enum fdt_compat_id {
|
||||
COMPAT_NVIDIA_TEGRA20_PCIE, /* Tegra 20 PCIe controller */
|
||||
COMPAT_NVIDIA_TEGRA124_XUSB_PADCTL,
|
||||
/* Tegra124 XUSB pad controller */
|
||||
COMPAT_NVIDIA_TEGRA210_XUSB_PADCTL,
|
||||
/* Tegra210 XUSB pad controller */
|
||||
COMPAT_SMSC_LAN9215, /* SMSC 10/100 Ethernet LAN9215 */
|
||||
COMPAT_SAMSUNG_EXYNOS5_SROMC, /* Exynos5 SROMC */
|
||||
COMPAT_SAMSUNG_S3C2440_I2C, /* Exynos I2C Controller */
|
||||
|
||||
Reference in New Issue
Block a user