Initial revision
This commit is contained in:
wdenk
57
include/cmd_disk.h
Normal file
57
include/cmd_disk.h
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@@ -0,0 +1,57 @@
|
||||
/*
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||||
* (C) Copyright 2000
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
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||||
*/
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||||
|
||||
/*
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* Harddisk support
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*/
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#ifndef _CMD_DISK_H
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#define _CMD_DISK_H
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#include <common.h>
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#include <command.h>
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/*
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* Type string for PPC bootable partitions
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*/
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#define BOOT_PART_TYPE "U-Boot"
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#if 0
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typedef struct disk_partition {
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ulong start; /* # of first block in partition */
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ulong size; /* number of blocks in partition */
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ulong blksz; /* block size in bytes */
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uchar name[32]; /* partition name */
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uchar type[32]; /* string type description */
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} disk_partition_t;
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int get_partition_info (block_dev_desc_t * dev_desc, int part, disk_partition_t *info);
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#ifdef CONFIG_MAC_PARTITION
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int get_partition_info_mac (block_dev_desc_t * dev_desc, int part, disk_partition_t *info);
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#endif
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#ifdef CONFIG_DOS_PARTITION
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int get_partition_info_dos (block_dev_desc_t * dev_desc, int part, disk_partition_t *info);
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#endif
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#endif /* 0 */
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#endif /* _CMD_DISK_H */
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297
include/configs/AMX860.h
Normal file
297
include/configs/AMX860.h
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@@ -0,0 +1,297 @@
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/*
|
||||
* (C) Copyright 2001
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* board/config.h - configuration options, board specific
|
||||
*/
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||||
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||||
#ifndef __CONFIG_H
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#define __CONFIG_H
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||||
/*
|
||||
* High Level Configuration Options
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||||
* (easy to change)
|
||||
*/
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||||
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#define CONFIG_MPC860 1
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#define CONFIG_AMX860 1
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#undef CONFIG_8xx_CONS_SMC1 /* Console is on SCC2 */
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#undef CONFIG_8xx_CONS_SMC2
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#define CONFIG_8xx_CONS_SCC2 1
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#undef CONFIG_8xx_CONS_NONE
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#define CONFIG_BAUDRATE 9600
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#define MPC8XX_FACT 10 /* Multiply by 10 */
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#define MPC8XX_XIN 5000000 /* 5 MHz in */
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#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT))
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#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
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#if 0
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#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
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#else
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||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
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||||
#endif
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||||
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#define CONFIG_BOOTCOMMAND \
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"bootp;" \
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||||
"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
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"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
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"bootm" /* autoboot command */
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||||
#undef CONFIG_BOOTARGS
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||||
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
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||||
#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
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#undef CONFIG_KGDB_NONE /* define if kgdb on something else */
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#define CONFIG_KGDB_INDEX 1 /* which serial channel for kgdb */
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#define CONFIG_KGDB_BAUDRATE 9600 /* speed to run kgdb serial port at */
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||||
#endif
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||||
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||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */
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||||
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||||
#define CONFIG_SCC1_ENET 1 /* use SCC1 ethernet */
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||||
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||||
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
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#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
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CFG_CMD_DHCP | \
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CFG_CMD_DATE )
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||||
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||||
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
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||||
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||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
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||||
#include <cmd_confdefs.h>
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||||
/*
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||||
* Miscellaneous configurable options
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*/
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#define CFG_LONGHELP /* undef to save memory */
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#define CFG_PROMPT "=> " /* Monitor Command Prompt */
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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||||
#define CFG_MAXARGS 16 /* max number of command args */
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||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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||||
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||||
#define CFG_MEMTEST_START 0x0100000 /* memtest works on */
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||||
#define CFG_MEMTEST_END 0x0200000 /* 1 ... 4 MB in DRAM */
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||||
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||||
#define CFG_LOAD_ADDR 0x00100000
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||||
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||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
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||||
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||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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||||
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||||
/*
|
||||
* Low Level Configuration Settings
|
||||
* (address mappings, register initial values, etc.)
|
||||
* You should know what you are doing if you make changes here.
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||||
*/
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||||
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||||
/*-----------------------------------------------------------------------
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||||
* Internal Memory Mapped Register
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||||
*/
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||||
#define CFG_IMMR 0xFF000000
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||||
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||||
/*-----------------------------------------------------------------------
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||||
* Definitions for initial stack pointer and data area (in DPRAM)
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||||
*/
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||||
#define CFG_INIT_RAM_ADDR CFG_IMMR
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||||
#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
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#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
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||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
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||||
/*-----------------------------------------------------------------------
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||||
* Start addresses for the final memory configuration
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||||
* (Set up by the startup code)
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||||
* Please note that CFG_SDRAM_BASE _must_ start at 0
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||||
*/
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||||
#define CFG_SDRAM_BASE 0x00000000
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#define CFG_FLASH_BASE 0x40000000
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#if defined(DEBUG)
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#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
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||||
#else
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||||
#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
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||||
#endif
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||||
#define CFG_MONITOR_BASE CFG_FLASH_BASE
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||||
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
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||||
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||||
/*
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||||
* U-Boot for AMX board supports two types of memory extension
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* modules: one that provides 4 MB flash memory, and another one with
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* 16 MB EDO DRAM.
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*
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* The flash module swaps the CS0 and CS1 signals: if the module is
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* installed, CS0 is connected to Flash on the module and CS1 is
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* connected to the on-board Flash. This means that you must intall
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||||
* U-Boot when the Flash module is plugged in, if you plan to use
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* it.
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*
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* To enable support for the DRAM extension card, CONFIG_AMX_RAM_EXT
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* must be defined. The DRAM module uses CS1.
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*
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* Only one of these modules may be installed at a time. If U-Boot
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* is compiled with the CONFIG_AMX_RAM_EXT option set, it will not
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||||
* work if the Flash extension module is installed instead of the
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* DRAM module.
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*/
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#define CONFIG_AMX_RAM_EXT /* 16Mb Ext. DRAM module support */
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/*
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||||
* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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||||
*
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||||
* Use 4 MB for without and 8 MB with 16 MB DRAM extension module
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* (CONFIG_AMX_RAM_EXT)
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||||
*/
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||||
#ifdef CONFIG_AMX_RAM_EXT
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# define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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#else
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# define CFG_BOOTMAPSZ (4 << 20) /* Initial Memory map for Linux */
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#endif
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||||
/*-----------------------------------------------------------------------
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||||
* FLASH organization
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||||
*/
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||||
#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
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#define CFG_MAX_FLASH_SECT 35 /* max number of sectors on one chip */
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#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
|
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
|
||||
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#define CFG_ENV_IS_IN_FLASH 1
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||||
#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
|
||||
#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
|
||||
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||||
/*-----------------------------------------------------------------------
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||||
* Cache Configuration
|
||||
*/
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||||
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
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||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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||||
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SYPCR - System Protection Control 11-9
|
||||
* SYPCR can only be written once after reset!
|
||||
*-----------------------------------------------------------------------
|
||||
* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
|
||||
*/
|
||||
#if defined(CONFIG_WATCHDOG)
|
||||
#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
|
||||
SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
|
||||
#else
|
||||
#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SIUMCR - SIU Module Configuration 11-6
|
||||
*-----------------------------------------------------------------------
|
||||
* PCMCIA config., multi-function pin tri-state
|
||||
*/
|
||||
#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* TBSCR - Time Base Status and Control 11-26
|
||||
*-----------------------------------------------------------------------
|
||||
* Clear Reference Interrupt Status, Timebase freezing enabled
|
||||
*/
|
||||
#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PISCR - Periodic Interrupt Status and Control 11-31
|
||||
*-----------------------------------------------------------------------
|
||||
* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
|
||||
*/
|
||||
#define CFG_PISCR (PISCR_PS | PISCR_PITF)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
|
||||
*-----------------------------------------------------------------------
|
||||
* set the PLL, the low-power modes and the reset control (15-29)
|
||||
*/
|
||||
#define CFG_PLPRCR (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \
|
||||
PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SCCR - System Clock and reset Control Register 15-27
|
||||
*-----------------------------------------------------------------------
|
||||
* Set clock output, timebase and RTC source and divider,
|
||||
* power management and some other internal clocks
|
||||
*/
|
||||
#define SCCR_MASK SCCR_EBDF11
|
||||
#define CFG_SCCR (SCCR_TBS|SCCR_COM00|SCCR_DFSYNC00|SCCR_DFBRG00|SCCR_DFNL000|SCCR_DFNH000|SCCR_DFLCD000|SCCR_DFALCD00)
|
||||
|
||||
#define CFG_DER 0
|
||||
|
||||
/*
|
||||
* Init Memory Controller:
|
||||
*
|
||||
* BR0/1 and OR0/1 (FLASH)
|
||||
*/
|
||||
|
||||
#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
|
||||
#ifndef CONFIG_AMX_RAM_EXT
|
||||
#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #1 */
|
||||
#endif
|
||||
|
||||
#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
|
||||
#define CFG_PRELIM_OR_AM 0xFFC00000 /* OR addr mask */
|
||||
|
||||
/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */
|
||||
/* 0x00000800 0x00000400 0x00000100 0x00000030 0x00000004 */
|
||||
#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_5_CLK | OR_TRLX)
|
||||
|
||||
#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
|
||||
|
||||
#define CFG_OR0_PRELIM 0xFFC00954 /* Real values for the board */
|
||||
#define CFG_BR0_PRELIM 0x40000001 /* Real values for the board */
|
||||
|
||||
#ifndef CONFIG_AMX_RAM_EXT
|
||||
#define CFG_OR1_REMAP CFG_OR0_REMAP
|
||||
#define CFG_OR1_PRELIM 0xFFC00954 /* Real values for the board */
|
||||
#define CFG_BR1_PRELIM 0x60000001 /* Real values for the board */
|
||||
#endif
|
||||
|
||||
/* DSP ("Glue") Xilinx */
|
||||
#define CFG_OR6_PRELIM 0xFFFF8000 /* 32kB, 15 waits, cs after addr, no bursts */
|
||||
#define CFG_BR6_PRELIM 0x60000401 /* use GPCM for CS generation, 8 bit port */
|
||||
|
||||
/*
|
||||
* Internal Definitions
|
||||
*
|
||||
* Boot Flags
|
||||
*/
|
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
|
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
357
include/configs/SXNI855T.h
Normal file
357
include/configs/SXNI855T.h
Normal file
@@ -0,0 +1,357 @@
|
||||
/*
|
||||
* U-Boot configuration for SIXNET SXNI855T CPU board.
|
||||
* This board is based (loosely) on the Motorola FADS board, so this
|
||||
* file is based (loosely) on config_FADS860T.h, see it for additional
|
||||
* credits.
|
||||
*
|
||||
* Copyright (c) 2000-2002 Dave Ellis, SIXNET, dge@sixnetio.com
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*
|
||||
*/
|
||||
|
||||
/*
|
||||
* Memory map:
|
||||
*
|
||||
* ff100000 -> ff13ffff : FPGA CS1
|
||||
* ff030000 -> ff03ffff : EXPANSION CS7
|
||||
* ff020000 -> ff02ffff : DATA FLASH CS4
|
||||
* ff018000 -> ff01ffff : UART B CS6/UPMB
|
||||
* ff010000 -> ff017fff : UART A CS5/UPMB
|
||||
* ff000000 -> ff00ffff : IMAP internal to the MPC855T
|
||||
* f8000000 -> fbffffff : FLASH CS0 up to 64MB
|
||||
* f4000000 -> f7ffffff : NVSRAM CS2 up to 64MB
|
||||
* 00000000 -> 0fffffff : SDRAM CS3/UPMA up to 256MB
|
||||
*/
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
/*
|
||||
* board/config.h - configuration options, board specific
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
* (easy to change)
|
||||
*/
|
||||
#include <mpc8xx_irq.h>
|
||||
|
||||
#define CONFIG_SXNI855T 1 /* SIXNET IPm 855T CPU module */
|
||||
|
||||
/* The 855T is just a stripped 860T and needs code for 860, so for now
|
||||
* at least define 860, 860T and 855T
|
||||
*/
|
||||
#define CONFIG_MPC860 1
|
||||
#define CONFIG_MPC860T 1
|
||||
#define CONFIG_MPC855T 1
|
||||
|
||||
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
|
||||
#undef CONFIG_8xx_CONS_SMC2
|
||||
#undef CONFIG_8xx_CONS_SCC1
|
||||
#undef CONFIG_8xx_CONS_NONE
|
||||
#define CONFIG_BAUDRATE 9600
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
|
||||
|
||||
#define MPC8XX_FACT 10 /* 50 MHz is 5 MHz in times 10 */
|
||||
|
||||
#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
|
||||
|
||||
#if 0
|
||||
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
|
||||
#else
|
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
|
||||
#endif
|
||||
|
||||
#define CONFIG_BOOTCOMMAND "bootm f8040000 f8100000" /* autoboot command */
|
||||
#define CONFIG_BOOTARGS "root=/dev/ram ip=off"
|
||||
|
||||
#define CONFIG_MISC_INIT_R /* have misc_init_r() function */
|
||||
#define CONFIG_BOARD_POSTCLK_INIT /* have board_postclk_init() function */
|
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */
|
||||
|
||||
#define CONFIG_RTC_DS1306 /* Dallas 1306 real time clock */
|
||||
|
||||
#define CONFIG_SOFT_I2C /* I2C bit-banged */
|
||||
/*
|
||||
* Software (bit-bang) I2C driver configuration
|
||||
*/
|
||||
#define PB_SCL 0x00000020 /* PB 26 */
|
||||
#define PB_SDA 0x00000010 /* PB 27 */
|
||||
|
||||
#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
|
||||
#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
|
||||
#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
|
||||
#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
|
||||
#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
|
||||
else immr->im_cpm.cp_pbdat &= ~PB_SDA
|
||||
#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
|
||||
else immr->im_cpm.cp_pbdat &= ~PB_SCL
|
||||
#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
|
||||
|
||||
# define CFG_I2C_SPEED 50000
|
||||
# define CFG_I2C_SLAVE 0xFE
|
||||
# define CFG_I2C_EEPROM_ADDR 0x50 /* Atmel 24C64 */
|
||||
# define CFG_I2C_EEPROM_ADDR_LEN 2 /* two byte address */
|
||||
|
||||
#define CONFIG_FEC_ENET 1 /* use FEC ethernet */
|
||||
|
||||
#define CFG_DISCOVER_PHY
|
||||
|
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_EEPROM | CFG_CMD_DATE)
|
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
|
||||
#include <cmd_confdefs.h>
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CFG_LONGHELP /* undef to save a little memory */
|
||||
#define CFG_PROMPT "=>" /* Monitor Command Prompt */
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#else
|
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#endif
|
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CFG_MAXARGS 16 /* max number of command args */
|
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
|
||||
|
||||
#define CFG_MEMTEST_START 0x0100000 /* memtest works on */
|
||||
#define CFG_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */
|
||||
|
||||
#define CFG_LOAD_ADDR 0x00100000
|
||||
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
|
||||
|
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
|
||||
|
||||
/*
|
||||
* Low Level Configuration Settings
|
||||
* (address mappings, register initial values, etc.)
|
||||
* You should know what you are doing if you make changes here.
|
||||
*/
|
||||
/*-----------------------------------------------------------------------
|
||||
* Internal Memory Mapped Register
|
||||
*/
|
||||
#define CFG_IMMR 0xFF000000
|
||||
#define CFG_IMMR_SIZE ((uint)(64 * 1024))
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM)
|
||||
*/
|
||||
#define CFG_INIT_RAM_ADDR CFG_IMMR
|
||||
#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
|
||||
#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
|
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
|
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration
|
||||
* (Set up by the startup code)
|
||||
* Please note that CFG_SDRAM_BASE _must_ start at 0
|
||||
*/
|
||||
#define CFG_SDRAM_BASE 0x00000000
|
||||
#define CFG_SRAM_BASE 0xF4000000
|
||||
#define CFG_SRAM_SIZE 0x04000000 /* autosize up to 64Mbyte */
|
||||
|
||||
#define CFG_FLASH_BASE 0xF8000000
|
||||
#define CFG_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */
|
||||
|
||||
#define CFG_DFLASH_BASE 0xff020000 /* DiskOnChip or NAND FLASH */
|
||||
#define CFG_DFLASH_SIZE 0x00010000
|
||||
|
||||
#define CFG_FPGA_BASE 0xFF100000 /* Xilinx FPGA */
|
||||
#define CFG_FPGA_PROG 0xFF130000 /* Programming address */
|
||||
#define CFG_FPGA_SIZE 0x00040000 /* 256KiB usable */
|
||||
|
||||
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
|
||||
#define CFG_MONITOR_BASE CFG_FLASH_BASE
|
||||
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 8 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization
|
||||
*/
|
||||
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
|
||||
/* Intel 28F640 has 135, 127 64K sectors in 8MB, + 8 more for 8K boot blocks.
|
||||
* AMD 29LV641 has 128 64K sectors in 8MB
|
||||
*/
|
||||
#define CFG_MAX_FLASH_SECT 135 /* max number of sectors on one chip */
|
||||
|
||||
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
|
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration
|
||||
*/
|
||||
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SYPCR - System Protection Control 11-9
|
||||
* SYPCR can only be written once after reset!
|
||||
*-----------------------------------------------------------------------
|
||||
* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
|
||||
*/
|
||||
#if defined(CONFIG_WATCHDOG)
|
||||
#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
|
||||
SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
|
||||
#else
|
||||
#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SIUMCR - SIU Module Configuration 11-6
|
||||
*-----------------------------------------------------------------------
|
||||
* PCMCIA config., multi-function pin tri-state
|
||||
*/
|
||||
#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* TBSCR - Time Base Status and Control 11-26
|
||||
*-----------------------------------------------------------------------
|
||||
* Clear Reference Interrupt Status, Timebase freezing enabled
|
||||
*/
|
||||
#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PISCR - Periodic Interrupt Status and Control 11-31
|
||||
*-----------------------------------------------------------------------
|
||||
* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
|
||||
*/
|
||||
#define CFG_PISCR (PISCR_PS | PISCR_PITF)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
|
||||
*-----------------------------------------------------------------------
|
||||
* set the PLL, the low-power modes and the reset control (15-29)
|
||||
*/
|
||||
#define CFG_PLPRCR (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \
|
||||
PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SCCR - System Clock and reset Control Register 15-27
|
||||
*-----------------------------------------------------------------------
|
||||
* Set clock output, timebase and RTC source and divider,
|
||||
* power management and some other internal clocks
|
||||
*/
|
||||
#define SCCR_MASK SCCR_EBDF11
|
||||
#define CFG_SCCR (SCCR_TBS|SCCR_COM00|SCCR_DFSYNC00|SCCR_DFBRG00|SCCR_DFNL000|SCCR_DFNH000|SCCR_DFLCD000|SCCR_DFALCD00)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*
|
||||
*-----------------------------------------------------------------------
|
||||
*
|
||||
*/
|
||||
#define CFG_DER 0
|
||||
|
||||
/* Because of the way the 860 starts up and assigns CS0 the
|
||||
* entire address space, we have to set the memory controller
|
||||
* differently. Normally, you write the option register
|
||||
* first, and then enable the chip select by writing the
|
||||
* base register. For CS0, you must write the base register
|
||||
* first, followed by the option register.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Init Memory Controller:
|
||||
*
|
||||
**********************************************************
|
||||
* BR0 and OR0 (FLASH)
|
||||
*/
|
||||
|
||||
#define CFG_PRELIM_OR0_AM 0xFC000000 /* OR addr mask */
|
||||
|
||||
/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */
|
||||
#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
|
||||
|
||||
#define CFG_OR0_PRELIM (CFG_PRELIM_OR0_AM | CFG_OR_TIMING_FLASH)
|
||||
|
||||
#define CONFIG_FLASH_16BIT
|
||||
#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_V )
|
||||
#define CFG_FLASH_PROTECTION /* need to lock/unlock sectors in hardware */
|
||||
|
||||
/**********************************************************
|
||||
* BR1 and OR1 (FPGA)
|
||||
* These preliminary values are also the final values.
|
||||
*/
|
||||
#define CFG_OR_TIMING_FPGA \
|
||||
(OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | OR_SCY_5_CLK | OR_EHTR)
|
||||
#define CFG_BR1_PRELIM ((CFG_FPGA_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
|
||||
#define CFG_OR1_PRELIM (((-CFG_FPGA_SIZE) & OR_AM_MSK) | CFG_OR_TIMING_FPGA)
|
||||
|
||||
/**********************************************************
|
||||
* BR4 and OR4 (data flash)
|
||||
* These preliminary values are also the final values.
|
||||
*/
|
||||
#define CFG_OR_TIMING_DFLASH \
|
||||
(OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_5_CLK | OR_EHTR)
|
||||
#define CFG_BR4_PRELIM ((CFG_DFLASH_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
|
||||
#define CFG_OR4_PRELIM (((-CFG_DFLASH_SIZE) & OR_AM_MSK) | CFG_OR_TIMING_DFLASH)
|
||||
|
||||
/**********************************************************
|
||||
* BR5/6 and OR5/6 (Dual UART)
|
||||
*/
|
||||
#define CFG_DUART_SIZE 0x8000 /* 32K window, only uses 8 bytes */
|
||||
#define CFG_DUARTA_BASE 0xff010000
|
||||
#define CFG_DUARTB_BASE 0xff018000
|
||||
|
||||
#define DUART_MBMR 0
|
||||
#define DUART_OR_VALUE (ORMASK(CFG_DUART_SIZE) | OR_G5LS| OR_BI)
|
||||
#define DUART_BR_VALUE (BR_MS_UPMB | BR_PS_8 | BR_V)
|
||||
#define DUART_BR5_VALUE ((CFG_DUARTA_BASE & BR_BA_MSK ) | DUART_BR_VALUE)
|
||||
#define DUART_BR6_VALUE ((CFG_DUARTB_BASE & BR_BA_MSK ) | DUART_BR_VALUE)
|
||||
|
||||
/**********************************************************
|
||||
*
|
||||
* Boot Flags
|
||||
*/
|
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
|
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */
|
||||
|
||||
#define CONFIG_RESET_ON_PANIC /* reset if system panic() */
|
||||
|
||||
/* to put environment in EEROM */
|
||||
#define CFG_ENV_IS_IN_EEPROM 1
|
||||
#define CFG_ENV_OFFSET 0 /* Start right at beginning of NVRAM */
|
||||
#define CFG_ENV_SIZE 1024 /* Use only a part of it*/
|
||||
|
||||
#if 1
|
||||
#define CONFIG_BOOT_RETRY_TIME 60 /* boot if no command in 60 seconds */
|
||||
#endif
|
||||
|
||||
#if 1
|
||||
#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */
|
||||
#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n"
|
||||
#define CONFIG_AUTOBOOT_DELAY_STR "delayabit"
|
||||
#define CONFIG_AUTOBOOT_STOP_STR " " /* easy to stop for now */
|
||||
#endif
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
Reference in New Issue
Block a user