mpc8xx: remove IVMS8, IVML24 board support
This board is still a non-generic board. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Wolfgang Denk <wd@denx.de>
This commit is contained in:
Masahiro Yamada
committed by
Tom Rini
Tom Rini
parent
acc2372db0
commit
ca620cd149
@@ -512,37 +512,6 @@ typedef struct scc_enet {
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#define SICR_ENET_CLKRT ((uint)0x0000002C)
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#endif /* CONFIG_IP860 */
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/*** IVMS8 **********************************************************/
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/* The IVMS8 uses the FEC on a MPC860T for Ethernet */
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#if defined(CONFIG_IVMS8) || defined(CONFIG_IVML24)
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#define FEC_ENET /* use FEC for EThernet */
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#undef SCC_ENET
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#define PB_ENET_POWER ((uint)0x00010000) /* PB 15 */
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#define PC_ENET_RESET ((ushort)0x0010) /* PC 11 */
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#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */
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#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */
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#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */
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#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */
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#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */
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#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */
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#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */
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#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */
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#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */
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#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */
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#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */
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#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */
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#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */
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#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */
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#endif /* CONFIG_IVMS8, CONFIG_IVML24 */
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/*** KM8XX *********************************************************/
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/* The KM8XX Service Module uses SCC3 for Ethernet */
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@@ -1,458 +0,0 @@
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/*
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* (C) Copyright 2001
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/*
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* board/config.h - configuration options, board specific
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_MPC860 1 /* This is a MPC860 CPU */
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#define CONFIG_IVML24 1 /* ...on a IVML24 board */
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#define CONFIG_SYS_TEXT_BASE 0xFF000000
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#if defined (CONFIG_IVML24_16M)
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# define CONFIG_IDENT_STRING " IVML24"
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#elif defined (CONFIG_IVML24_32M)
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# define CONFIG_IDENT_STRING " IVML24_128"
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#elif defined (CONFIG_IVML24_64M)
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# define CONFIG_IDENT_STRING " IVML24_256"
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#endif
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#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
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#undef CONFIG_8xx_CONS_SMC2
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#undef CONFIG_8xx_CONS_NONE
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
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#define CONFIG_8xx_GCLK_FREQ 50331648
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#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
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#define CONFIG_SHOW_BOOT_PROGRESS 1 /* Show boot progress on LEDs */
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#if 0
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#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
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#else
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#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
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#endif
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#define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */
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#define CONFIG_BOOTARGS "root=/dev/nfs rw " \
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"nfsroot=10.0.0.2:/opt/eldk/ppc_8xx " \
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"nfsaddrs=10.0.0.99:10.0.0.2"
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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#define CONFIG_STATUS_LED 1 /* Status LED enabled */
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_IDE
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#define CONFIG_MAC_PARTITION
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#define CONFIG_DOS_PARTITION
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_SUBNETMASK
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#define CONFIG_BOOTP_HOSTNAME
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_BOOTFILESIZE
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */
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#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
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#define CONFIG_SYS_PIO_MODE 0 /* IDE interface in PIO Mode 0 */
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#define CONFIG_SYS_PB_12V_ENABLE 0x00002000 /* PB 18 */
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#define CONFIG_SYS_PB_ILOCK_SWITCH 0x00004000 /* PB 17 */
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#define CONFIG_SYS_PB_SDRAM_CLKE 0x00008000 /* PB 16 */
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#define CONFIG_SYS_PB_ETH_POWERDOWN 0x00010000 /* PB 15 */
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#define CONFIG_SYS_PB_IDE_MOTOR 0x00020000 /* PB 14 */
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#define CONFIG_SYS_PC_ETH_RESET ((ushort)0x0010) /* PC 11 */
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#define CONFIG_SYS_PC_IDE_RESET ((ushort)0x0020) /* PC 10 */
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/*
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* Low Level Configuration Settings
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* (address mappings, register initial values, etc.)
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* You should know what you are doing if you make changes here.
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*/
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/*-----------------------------------------------------------------------
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* Internal Memory Mapped Register
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*/
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#define CONFIG_SYS_IMMR 0xFFF00000 /* was: 0xFF000000 */
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/*-----------------------------------------------------------------------
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* Definitions for initial stack pointer and data area (in DPRAM)
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*/
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#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
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#if defined (CONFIG_IVML24_16M)
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# define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
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#elif defined (CONFIG_IVML24_32M)
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# define CONFIG_SYS_INIT_RAM_SIZE 0x3000 /* Size of used area in DPRAM */
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#elif defined (CONFIG_IVML24_64M)
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# define CONFIG_SYS_INIT_RAM_SIZE 0x3000 /* Size of used area in DPRAM */
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#endif
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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/*-----------------------------------------------------------------------
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
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*/
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#define CONFIG_SYS_SDRAM_BASE 0x00000000
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#define CONFIG_SYS_FLASH_BASE 0xFF000000
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#ifdef DEBUG
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#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
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#else
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#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
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#endif
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*-----------------------------------------------------------------------
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* FLASH organization
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*/
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
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#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
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#define CONFIG_ENV_IS_IN_FLASH 1
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#define CONFIG_ENV_OFFSET 0x7A000 /* Offset of Environment Sector */
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#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
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/*-----------------------------------------------------------------------
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* Cache Configuration
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*/
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#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
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#endif
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/*-----------------------------------------------------------------------
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* SYPCR - System Protection Control 11-9
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* SYPCR can only be written once after reset!
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*-----------------------------------------------------------------------
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* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
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*/
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#if defined(CONFIG_WATCHDOG)
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# if defined (CONFIG_IVML24_16M)
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# define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
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SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
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# elif defined (CONFIG_IVML24_32M)
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# define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
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SYPCR_SWE | SYPCR_SWP)
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# elif defined (CONFIG_IVML24_64M)
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# define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
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SYPCR_SWE | SYPCR_SWP)
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# endif
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#else
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#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
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#endif
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/*-----------------------------------------------------------------------
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* SIUMCR - SIU Module Configuration 11-6
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*-----------------------------------------------------------------------
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* PCMCIA config., multi-function pin tri-state
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*/
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/* EARB, DBGC and DBPC are initialised by the HCW */
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/* => 0x000000C0 */
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#define CONFIG_SYS_SIUMCR (SIUMCR_BSC | SIUMCR_GB5E)
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/*-----------------------------------------------------------------------
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* TBSCR - Time Base Status and Control 11-26
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*-----------------------------------------------------------------------
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* Clear Reference Interrupt Status, Timebase freezing enabled
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*/
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#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
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/*-----------------------------------------------------------------------
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* PISCR - Periodic Interrupt Status and Control 11-31
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*-----------------------------------------------------------------------
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* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
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*/
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#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
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/*-----------------------------------------------------------------------
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* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
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*-----------------------------------------------------------------------
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* Reset PLL lock status sticky bit, timer expired status bit and timer
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* interrupt status bit, set PLL multiplication factor !
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*/
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/* 0x00B0C0C0 */
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#define CONFIG_SYS_PLPRCR \
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( (11 << PLPRCR_MF_SHIFT) | \
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PLPRCR_SPLSS | PLPRCR_TEXPS | /*PLPRCR_TMIST|*/ \
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/*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL | \
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PLPRCR_CSR | PLPRCR_LOLRE /*|PLPRCR_FIOPD*/ \
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)
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/*-----------------------------------------------------------------------
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* SCCR - System Clock and reset Control Register 15-27
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*-----------------------------------------------------------------------
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* Set clock output, timebase and RTC source and divider,
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* power management and some other internal clocks
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*/
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#define SCCR_MASK SCCR_EBDF11
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/* 0x01800014 */
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#define CONFIG_SYS_SCCR (SCCR_COM01 | /*SCCR_TBS|*/ \
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SCCR_RTDIV | SCCR_RTSEL | \
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/*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \
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SCCR_EBDF00 | SCCR_DFSYNC00 | \
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SCCR_DFBRG00 | SCCR_DFNL000 | \
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SCCR_DFNH000 | SCCR_DFLCD101 | \
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SCCR_DFALCD00)
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/*-----------------------------------------------------------------------
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* RTCSC - Real-Time Clock Status and Control Register 11-27
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*-----------------------------------------------------------------------
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*/
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/* 0x00C3 */
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#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
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/*-----------------------------------------------------------------------
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* RCCR - RISC Controller Configuration Register 19-4
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*-----------------------------------------------------------------------
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*/
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/* TIMEP=2 */
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#define CONFIG_SYS_RCCR 0x0200
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/*-----------------------------------------------------------------------
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* RMDS - RISC Microcode Development Support Control Register
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*-----------------------------------------------------------------------
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*/
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#define CONFIG_SYS_RMDS 0
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/*-----------------------------------------------------------------------
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*
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* Interrupt Levels
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*-----------------------------------------------------------------------
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*/
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#define CONFIG_SYS_CPM_INTERRUPT 13 /* SIU_LEVEL6 */
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/*-----------------------------------------------------------------------
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* PCMCIA stuff
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*-----------------------------------------------------------------------
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*
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*/
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#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
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#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
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#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
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#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
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#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
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#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
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#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
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#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
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/*-----------------------------------------------------------------------
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* IDE/ATA stuff
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*-----------------------------------------------------------------------
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*/
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#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
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#define CONFIG_IDE_INIT_POSTRESET 1 /* Use postreset IDE hook */
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#define CONFIG_IDE_8xx_DIRECT 1 /* PCMCIA interface required */
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#define CONFIG_IDE_RESET 1 /* reset for ide supported */
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#define CONFIG_SYS_IDE_MAXBUS 1 /* The IVML24 has only 1 IDE bus*/
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#define CONFIG_SYS_IDE_MAXDEVICE 1 /* ... and only 1 IDE device */
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#define CONFIG_SYS_ATA_BASE_ADDR 0xFE100000
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#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
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#undef CONFIG_SYS_ATA_IDE1_OFFSET /* only one IDE bus available */
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#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
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#define CONFIG_SYS_ATA_REG_OFFSET 0x0080 /* Offset for normal register accesses */
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#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 /* Offset for alternate registers */
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/*-----------------------------------------------------------------------
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*
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*-----------------------------------------------------------------------
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*
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*/
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#define CONFIG_SYS_DER 0
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/*
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* Init Memory Controller:
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*
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* BR0 and OR0 (FLASH)
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*/
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#define FLASH_BASE0_PRELIM 0xFF000000 /* FLASH bank #0 */
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/* used to re-map FLASH both when starting from SRAM or FLASH:
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* restrict access enough to keep SRAM working (if any)
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* but not too much to meddle with FLASH accesses
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*/
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/* EPROMs are 512kb */
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#define CONFIG_SYS_REMAP_OR_AM 0xFFF80000 /* OR addr mask */
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#define CONFIG_SYS_PRELIM_OR_AM 0xFFF80000 /* OR addr mask */
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/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */
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#define CONFIG_SYS_OR_TIMING_FLASH (OR_SCY_5_CLK | OR_EHTR)
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#define CONFIG_SYS_OR0_REMAP ( CONFIG_SYS_REMAP_OR_AM | OR_ACS_DIV4 | OR_BI | \
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CONFIG_SYS_OR_TIMING_FLASH)
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#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | OR_ACS_DIV4 | OR_BI | \
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CONFIG_SYS_OR_TIMING_FLASH)
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/* 16 bit, bank valid */
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#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
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/*
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* BR1/OR1 - ELIC SACCO bank @ 0xFE000000
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*
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* AM=0xFFFF8 ATM=0 CSNT/SAM=1 ACS/G5LA/G5LS=3 BIH=1 SCY=2 SETA=0 TRLX=1 EHTR=1
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*/
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#define ELIC_SACCO_BASE 0xFE000000
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#define ELIC_SACCO_OR_AM 0xFFFF8000
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#define ELIC_SACCO_TIMING (OR_SCY_2_CLK | OR_TRLX | OR_EHTR)
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#define CONFIG_SYS_OR1 (ELIC_SACCO_OR_AM | OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \
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ELIC_SACCO_TIMING)
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#define CONFIG_SYS_BR1 ((ELIC_SACCO_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
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/*
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* BR2/OR2 - ELIC EPIC bank @ 0xFE008000
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*
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* AM=0xFFFF8 ATM=0 CSNT/SAM=1 ACS/G5LA/G5LS=3 BIH=1 SCY=2 SETA=0 TRLX=1 EHTR=1
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*/
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#define ELIC_EPIC_BASE 0xFE008000
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#define ELIC_EPIC_OR_AM 0xFFFF8000
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#define ELIC_EPIC_TIMING (OR_SCY_2_CLK | OR_TRLX | OR_EHTR)
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#define CONFIG_SYS_OR2 (ELIC_EPIC_OR_AM | OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \
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ELIC_EPIC_TIMING)
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#define CONFIG_SYS_BR2 ((ELIC_EPIC_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
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/*
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* BR3/OR3: SDRAM
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*
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* Multiplexed addresses, GPL5 output to GPL5_A (don't care)
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*/
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#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank */
|
||||
#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */
|
||||
#define SDRAM_TIMING OR_SCY_0_CLK /* SDRAM-Timing */
|
||||
|
||||
#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB SDRAM */
|
||||
|
||||
#define CONFIG_SYS_OR3_PRELIM (SDRAM_PRELIM_OR_AM | OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING )
|
||||
#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V )
|
||||
|
||||
/*
|
||||
* BR4/OR4 - HDLC Address
|
||||
*
|
||||
* AM=0xFFFF8 ATM=0 CSNT/SAM=0 ACS/G5LA/G5LS=0 BIH=1 SCY=1 SETA=0 TRLX=0 EHTR=0
|
||||
*/
|
||||
#define HDLC_ADDR_BASE 0xFE108000 /* HDLC Address area */
|
||||
#define HDLC_ADDR_OR_AM 0xFFFF8000
|
||||
#define HDLC_ADDR_TIMING OR_SCY_1_CLK
|
||||
|
||||
#define CONFIG_SYS_OR4 (HDLC_ADDR_OR_AM | OR_BI | HDLC_ADDR_TIMING)
|
||||
#define CONFIG_SYS_BR4 ((HDLC_ADDR_BASE & BR_BA_MSK) | BR_PS_8 | BR_WP | BR_V )
|
||||
|
||||
/*
|
||||
* BR5/OR5: SHARC ADSP-2165L
|
||||
*
|
||||
* AM=0xFFC00 ATM=0 CSNT/SAM=0 ACS/G5LA/G5LS=3 BIH=1 SCY=0 SETA=0 TRLX=0 EHTR=0
|
||||
*/
|
||||
#define SHARC_BASE 0xFE400000
|
||||
#define SHARC_OR_AM 0xFFC00000
|
||||
#define SHARC_TIMING OR_SCY_0_CLK
|
||||
|
||||
#define CONFIG_SYS_OR5 (SHARC_OR_AM | OR_ACS_DIV2 | OR_BI | SHARC_TIMING )
|
||||
#define CONFIG_SYS_BR5 ((SHARC_BASE & BR_BA_MSK) | BR_PS_32 | BR_MS_UPMA | BR_V )
|
||||
|
||||
/*
|
||||
* Memory Periodic Timer Prescaler
|
||||
*/
|
||||
|
||||
/* periodic timer for refresh */
|
||||
#define CONFIG_SYS_MBMR_PTB 204
|
||||
|
||||
/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
|
||||
#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
|
||||
#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
|
||||
|
||||
/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
|
||||
#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
|
||||
|
||||
#if defined (CONFIG_IVML24_16M)
|
||||
# define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
|
||||
#elif defined (CONFIG_IVML24_32M)
|
||||
# define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
|
||||
#elif defined (CONFIG_IVML24_64M)
|
||||
# define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV8 /* setting for 1 bank */
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* MBMR settings for SDRAM
|
||||
*/
|
||||
|
||||
#if defined (CONFIG_IVML24_16M)
|
||||
/* 8 column SDRAM */
|
||||
# define CONFIG_SYS_MBMR_8COL ((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT) | \
|
||||
MBMR_AMB_TYPE_0 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A11 | \
|
||||
MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X)
|
||||
#elif defined (CONFIG_IVML24_32M)
|
||||
/* 128 MBit SDRAM */
|
||||
# define CONFIG_SYS_MBMR_8COL ((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT) | \
|
||||
MBMR_AMB_TYPE_1 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A10 | \
|
||||
MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X)
|
||||
#elif defined (CONFIG_IVML24_64M)
|
||||
/* 128 MBit SDRAM */
|
||||
# define CONFIG_SYS_MBMR_8COL ((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT) | \
|
||||
MBMR_AMB_TYPE_1 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A10 | \
|
||||
MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X)
|
||||
#endif
|
||||
#endif /* __CONFIG_H */
|
||||
@@ -1,441 +0,0 @@
|
||||
/*
|
||||
* (C) Copyright 2000
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
/*
|
||||
* board/config.h - configuration options, board specific
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
* (easy to change)
|
||||
*/
|
||||
|
||||
#define CONFIG_MPC860 1 /* This is a MPC860 CPU */
|
||||
#define CONFIG_IVMS8 1 /* ...on a IVMS8 board */
|
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0xFF000000
|
||||
|
||||
#if defined (CONFIG_IVMS8_16M)
|
||||
# define CONFIG_IDENT_STRING " IVMS8"
|
||||
#elif defined (CONFIG_IVMS8_32M)
|
||||
# define CONFIG_IDENT_STRING " IVMS8_128"
|
||||
#elif defined (CONFIG_IVMS8_64M)
|
||||
# define CONFIG_IDENT_STRING " IVMS8_256"
|
||||
#endif
|
||||
|
||||
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
|
||||
#undef CONFIG_8xx_CONS_SMC2
|
||||
#undef CONFIG_8xx_CONS_NONE
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
|
||||
#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
|
||||
|
||||
#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
|
||||
#define CONFIG_8xx_GCLK_FREQ 50331648
|
||||
|
||||
#define CONFIG_SHOW_BOOT_PROGRESS 1 /* Show boot progress on LEDs */
|
||||
|
||||
#if 0
|
||||
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
|
||||
#else
|
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
|
||||
#endif
|
||||
#define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */
|
||||
|
||||
#define CONFIG_BOOTARGS "root=/dev/nfs rw " \
|
||||
"nfsroot=10.0.0.2:/opt/eldk/ppc_8xx " \
|
||||
"nfsaddrs=10.0.0.99:10.0.0.2"
|
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
|
||||
#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
|
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */
|
||||
|
||||
#define CONFIG_STATUS_LED 1 /* Status LED enabled */
|
||||
|
||||
/*
|
||||
* Command line configuration.
|
||||
*/
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
#define CONFIG_CMD_IDE
|
||||
|
||||
|
||||
#define CONFIG_MAC_PARTITION
|
||||
#define CONFIG_DOS_PARTITION
|
||||
|
||||
/*
|
||||
* BOOTP options
|
||||
*/
|
||||
#define CONFIG_BOOTP_SUBNETMASK
|
||||
#define CONFIG_BOOTP_HOSTNAME
|
||||
#define CONFIG_BOOTP_BOOTPATH
|
||||
#define CONFIG_BOOTP_BOOTFILESIZE
|
||||
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#else
|
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#endif
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
|
||||
#define CONFIG_SYS_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
|
||||
|
||||
#define CONFIG_SYS_PIO_MODE 0 /* IDE interface in PIO Mode 0 */
|
||||
|
||||
#define CONFIG_SYS_PB_SDRAM_CLKE 0x00008000 /* PB 16 */
|
||||
#define CONFIG_SYS_PB_ETH_POWERDOWN 0x00010000 /* PB 15 */
|
||||
#define CONFIG_SYS_PB_IDE_MOTOR 0x00020000 /* PB 14 */
|
||||
|
||||
#define CONFIG_SYS_PC_ETH_RESET ((ushort)0x0010) /* PC 11 */
|
||||
#define CONFIG_SYS_PC_IDE_RESET ((ushort)0x0020) /* PC 10 */
|
||||
|
||||
/*
|
||||
* Low Level Configuration Settings
|
||||
* (address mappings, register initial values, etc.)
|
||||
* You should know what you are doing if you make changes here.
|
||||
*/
|
||||
/*-----------------------------------------------------------------------
|
||||
* Internal Memory Mapped Register
|
||||
*/
|
||||
#define CONFIG_SYS_IMMR 0xFFF00000 /* was: 0xFF000000 */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM)
|
||||
*/
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
|
||||
#if defined (CONFIG_IVMS8_16M)
|
||||
# define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
|
||||
#elif defined (CONFIG_IVMS8_32M)
|
||||
# define CONFIG_SYS_INIT_RAM_SIZE 0x3000 /* Size of used area in DPRAM */
|
||||
#elif defined (CONFIG_IVMS8_64M)
|
||||
# define CONFIG_SYS_INIT_RAM_SIZE 0x3000 /* Size of used area in DPRAM */
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration
|
||||
* (Set up by the startup code)
|
||||
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
|
||||
*/
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000
|
||||
#define CONFIG_SYS_FLASH_BASE 0xFF000000
|
||||
#ifdef DEBUG
|
||||
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
|
||||
#else
|
||||
#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
|
||||
#endif
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
|
||||
#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 8 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization
|
||||
*/
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
|
||||
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
|
||||
|
||||
#define CONFIG_ENV_IS_IN_FLASH 1
|
||||
#define CONFIG_ENV_OFFSET 0x7A000 /* Offset of Environment Sector */
|
||||
#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration
|
||||
*/
|
||||
#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SYPCR - System Protection Control 11-9
|
||||
* SYPCR can only be written once after reset!
|
||||
*-----------------------------------------------------------------------
|
||||
* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
|
||||
*/
|
||||
#if defined(CONFIG_WATCHDOG)
|
||||
# if defined (CONFIG_IVMS8_16M)
|
||||
# define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
|
||||
SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
|
||||
# elif defined (CONFIG_IVMS8_32M)
|
||||
# define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
|
||||
SYPCR_SWE | SYPCR_SWP)
|
||||
# elif defined (CONFIG_IVMS8_64M)
|
||||
# define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
|
||||
SYPCR_SWE | SYPCR_SWP)
|
||||
# endif
|
||||
#else
|
||||
# define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SIUMCR - SIU Module Configuration 11-6
|
||||
*-----------------------------------------------------------------------
|
||||
* PCMCIA config., multi-function pin tri-state
|
||||
*/
|
||||
/* EARB, DBGC and DBPC are initialised by the HCW */
|
||||
/* => 0x000000C0 */
|
||||
#define CONFIG_SYS_SIUMCR (SIUMCR_BSC | SIUMCR_GB5E)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* TBSCR - Time Base Status and Control 11-26
|
||||
*-----------------------------------------------------------------------
|
||||
* Clear Reference Interrupt Status, Timebase freezing enabled
|
||||
*/
|
||||
#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PISCR - Periodic Interrupt Status and Control 11-31
|
||||
*-----------------------------------------------------------------------
|
||||
* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
|
||||
*/
|
||||
#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
|
||||
*-----------------------------------------------------------------------
|
||||
* Reset PLL lock status sticky bit, timer expired status bit and timer
|
||||
* interrupt status bit, set PLL multiplication factor !
|
||||
*/
|
||||
/* 0x00B0C0C0 */
|
||||
#define CONFIG_SYS_PLPRCR \
|
||||
( (11 << PLPRCR_MF_SHIFT) | \
|
||||
PLPRCR_SPLSS | PLPRCR_TEXPS | /*PLPRCR_TMIST|*/ \
|
||||
/*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL | \
|
||||
PLPRCR_CSR | PLPRCR_LOLRE /*|PLPRCR_FIOPD*/ \
|
||||
)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SCCR - System Clock and reset Control Register 15-27
|
||||
*-----------------------------------------------------------------------
|
||||
* Set clock output, timebase and RTC source and divider,
|
||||
* power management and some other internal clocks
|
||||
*/
|
||||
#define SCCR_MASK SCCR_EBDF11
|
||||
/* 0x01800014 */
|
||||
#define CONFIG_SYS_SCCR (SCCR_COM01 | /*SCCR_TBS|*/ \
|
||||
SCCR_RTDIV | SCCR_RTSEL | \
|
||||
/*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \
|
||||
SCCR_EBDF00 | SCCR_DFSYNC00 | \
|
||||
SCCR_DFBRG00 | SCCR_DFNL000 | \
|
||||
SCCR_DFNH000 | SCCR_DFLCD101 | \
|
||||
SCCR_DFALCD00)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RTCSC - Real-Time Clock Status and Control Register 11-27
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
/* 0x00C3 */
|
||||
#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RCCR - RISC Controller Configuration Register 19-4
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
/* TIMEP=2 */
|
||||
#define CONFIG_SYS_RCCR 0x0200
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RMDS - RISC Microcode Development Support Control Register
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
#define CONFIG_SYS_RMDS 0
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*
|
||||
* Interrupt Levels
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
#define CONFIG_SYS_CPM_INTERRUPT 13 /* SIU_LEVEL6 */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCMCIA stuff
|
||||
*-----------------------------------------------------------------------
|
||||
*
|
||||
*/
|
||||
#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
|
||||
#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
|
||||
#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
|
||||
#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
|
||||
#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
|
||||
#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
|
||||
#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
|
||||
#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* IDE/ATA stuff
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
|
||||
#define CONFIG_IDE_INIT_POSTRESET 1 /* Use postreset IDE hook */
|
||||
#define CONFIG_IDE_8xx_DIRECT 1 /* PCMCIA interface required */
|
||||
#define CONFIG_IDE_RESET 1 /* reset for ide supported */
|
||||
|
||||
#define CONFIG_SYS_IDE_MAXBUS 1 /* The IVMS8 has only 1 IDE bus */
|
||||
#define CONFIG_SYS_IDE_MAXDEVICE 1 /* ... and only 1 IDE device */
|
||||
|
||||
#define CONFIG_SYS_ATA_BASE_ADDR 0xFE100000
|
||||
#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
|
||||
#undef CONFIG_SYS_ATA_IDE1_OFFSET /* only one IDE bus available */
|
||||
|
||||
#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
|
||||
#define CONFIG_SYS_ATA_REG_OFFSET 0x0080 /* Offset for normal register accesses */
|
||||
#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 /* Offset for alternate registers */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*
|
||||
*-----------------------------------------------------------------------
|
||||
*
|
||||
*/
|
||||
#define CONFIG_SYS_DER 0
|
||||
|
||||
/*
|
||||
* Init Memory Controller:
|
||||
*
|
||||
* BR0 and OR0 (FLASH)
|
||||
*/
|
||||
|
||||
#define FLASH_BASE0_PRELIM 0xFF000000 /* FLASH bank #0 */
|
||||
|
||||
/* used to re-map FLASH both when starting from SRAM or FLASH:
|
||||
* restrict access enough to keep SRAM working (if any)
|
||||
* but not too much to meddle with FLASH accesses
|
||||
*/
|
||||
/* EPROMs are 512kb */
|
||||
#define CONFIG_SYS_REMAP_OR_AM 0xFFF80000 /* OR addr mask */
|
||||
#define CONFIG_SYS_PRELIM_OR_AM 0xFFF80000 /* OR addr mask */
|
||||
|
||||
/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */
|
||||
#define CONFIG_SYS_OR_TIMING_FLASH (/* OR_CSNT_SAM | */ OR_ACS_DIV4 | OR_BI | \
|
||||
OR_SCY_5_CLK | OR_EHTR)
|
||||
|
||||
#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
|
||||
#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
|
||||
/* 16 bit, bank valid */
|
||||
#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
|
||||
|
||||
/*
|
||||
* BR1/OR1 - ELIC SACCO bank @ 0xFE000000
|
||||
*
|
||||
* AM=0xFFFF8 ATM=0 CSNT/SAM=1 ACS/G5LA/G5LS=3 BIH=1 SCY=2 SETA=0 TRLX=1 EHTR=1
|
||||
*/
|
||||
#define ELIC_SACCO_BASE 0xFE000000
|
||||
#define ELIC_SACCO_OR_AM 0xFFFF8000
|
||||
#define ELIC_SACCO_TIMING 0x00000F26
|
||||
|
||||
#define CONFIG_SYS_OR1 (ELIC_SACCO_OR_AM | ELIC_SACCO_TIMING)
|
||||
#define CONFIG_SYS_BR1 ((ELIC_SACCO_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
|
||||
|
||||
/*
|
||||
* BR2/OR2 - ELIC EPIC bank @ 0xFE008000
|
||||
*
|
||||
* AM=0xFFFF8 ATM=0 CSNT/SAM=1 ACS/G5LA/G5LS=3 BIH=1 SCY=2 SETA=0 TRLX=1 EHTR=1
|
||||
*/
|
||||
#define ELIC_EPIC_BASE 0xFE008000
|
||||
#define ELIC_EPIC_OR_AM 0xFFFF8000
|
||||
#define ELIC_EPIC_TIMING 0x00000F26
|
||||
|
||||
#define CONFIG_SYS_OR2 (ELIC_EPIC_OR_AM | ELIC_EPIC_TIMING)
|
||||
#define CONFIG_SYS_BR2 ((ELIC_EPIC_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
|
||||
|
||||
/*
|
||||
* BR3/OR3: SDRAM
|
||||
*
|
||||
* Multiplexed addresses, GPL5 output to GPL5_A (don't care)
|
||||
*/
|
||||
#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank */
|
||||
#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */
|
||||
#define SDRAM_TIMING 0x00000A00 /* SDRAM-Timing */
|
||||
|
||||
#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB SDRAM */
|
||||
|
||||
#define CONFIG_SYS_OR3_PRELIM (SDRAM_PRELIM_OR_AM | SDRAM_TIMING )
|
||||
#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V )
|
||||
|
||||
/*
|
||||
* BR4/OR4: not used
|
||||
*/
|
||||
|
||||
/*
|
||||
* BR5/OR5: SHARC ADSP-2165L
|
||||
*
|
||||
* AM=0xFFC00 ATM=0 CSNT/SAM=0 ACS/G5LA/G5LS=3 BIH=1 SCY=0 SETA=0 TRLX=0 EHTR=0
|
||||
*/
|
||||
#define SHARC_BASE 0xFE400000
|
||||
#define SHARC_OR_AM 0xFFC00000
|
||||
#define SHARC_TIMING 0x00000700
|
||||
|
||||
#define CONFIG_SYS_OR5 (SHARC_OR_AM | SHARC_TIMING )
|
||||
#define CONFIG_SYS_BR5 ((SHARC_BASE & BR_BA_MSK) | BR_PS_32 | BR_MS_UPMA | BR_V )
|
||||
|
||||
/*
|
||||
* Memory Periodic Timer Prescaler
|
||||
*/
|
||||
|
||||
/* periodic timer for refresh */
|
||||
#define CONFIG_SYS_MBMR_PTB 204
|
||||
|
||||
/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
|
||||
#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
|
||||
#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
|
||||
|
||||
/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
|
||||
#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
|
||||
#if defined (CONFIG_IVMS8_16M)
|
||||
#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
|
||||
#elif defined (CONFIG_IVMS8_32M)
|
||||
#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
|
||||
#elif defined (CONFIG_IVMS8_64M)
|
||||
#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV8 /* setting for 1 bank */
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* MBMR settings for SDRAM
|
||||
*/
|
||||
|
||||
#if defined (CONFIG_IVMS8_16M)
|
||||
/* 8 column SDRAM */
|
||||
# define CONFIG_SYS_MBMR_8COL ((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT) | \
|
||||
MBMR_AMB_TYPE_0 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A11 | \
|
||||
MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X)
|
||||
#elif defined (CONFIG_IVMS8_32M)
|
||||
/* 128 MBit SDRAM */
|
||||
#define CONFIG_SYS_MBMR_8COL ((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT) | \
|
||||
MBMR_AMB_TYPE_1 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A10 | \
|
||||
MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X)
|
||||
#elif defined (CONFIG_IVMS8_64M)
|
||||
/* 128 MBit SDRAM */
|
||||
#define CONFIG_SYS_MBMR_8COL ((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT) | \
|
||||
MBMR_AMB_TYPE_1 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A10 | \
|
||||
MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X)
|
||||
|
||||
#endif
|
||||
#endif /* __CONFIG_H */
|
||||
@@ -23,8 +23,6 @@
|
||||
|
||||
#if defined(CONFIG_TQM8xxL)
|
||||
# define CONFIG_PCMCIA_SLOT_B /* The TQM8xxL use SLOT_B */
|
||||
#elif defined(CONFIG_IVMS8) || defined(CONFIG_IVML24) /* The IVM* use SLOT_A */
|
||||
# define CONFIG_PCMCIA_SLOT_A
|
||||
#elif defined(CONFIG_ATC) /* The ATC use SLOT_A */
|
||||
# define CONFIG_PCMCIA_SLOT_A
|
||||
#else
|
||||
|
||||
@@ -56,64 +56,6 @@ void status_led_set (int led, int state);
|
||||
|
||||
# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
|
||||
|
||||
/***** IVMS8 **********************************************************/
|
||||
#elif defined(CONFIG_IVMS8)
|
||||
|
||||
# define STATUS_LED_PAR im_cpm.cp_pbpar
|
||||
# define STATUS_LED_DIR im_cpm.cp_pbdir
|
||||
# define STATUS_LED_ODR im_cpm.cp_pbodr
|
||||
# define STATUS_LED_DAT im_cpm.cp_pbdat
|
||||
|
||||
# define STATUS_LED_BIT 0x00000010 /* LED 0 is on PB.27 */
|
||||
# define STATUS_LED_PERIOD (1 * CONFIG_SYS_HZ)
|
||||
# define STATUS_LED_STATE STATUS_LED_OFF
|
||||
# define STATUS_LED_BIT1 0x00000020 /* LED 1 is on PB.26 */
|
||||
# define STATUS_LED_PERIOD1 (1 * CONFIG_SYS_HZ)
|
||||
# define STATUS_LED_STATE1 STATUS_LED_OFF
|
||||
/* IDE LED usable for other purposes, too */
|
||||
# define STATUS_LED_BIT2 0x00000008 /* LED 2 is on PB.28 */
|
||||
# define STATUS_LED_PERIOD2 (1 * CONFIG_SYS_HZ)
|
||||
# define STATUS_LED_STATE2 STATUS_LED_OFF
|
||||
|
||||
# define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */
|
||||
|
||||
# define STATUS_ILOCK_SWITCH 0x00800000 /* ILOCK switch in IRQ4 */
|
||||
|
||||
# define STATUS_ILOCK_PERIOD (CONFIG_SYS_HZ / 10) /* about every 100 ms */
|
||||
|
||||
# define STATUS_LED_YELLOW 0
|
||||
# define STATUS_LED_GREEN 1
|
||||
# define STATUS_LED_BOOT 2 /* IDE LED used for boot status */
|
||||
|
||||
/***** IVML24 *********************************************************/
|
||||
#elif defined(CONFIG_IVML24)
|
||||
|
||||
# define STATUS_LED_PAR im_cpm.cp_pbpar
|
||||
# define STATUS_LED_DIR im_cpm.cp_pbdir
|
||||
# define STATUS_LED_ODR im_cpm.cp_pbodr
|
||||
# define STATUS_LED_DAT im_cpm.cp_pbdat
|
||||
|
||||
# define STATUS_LED_BIT 0x00000010 /* LED 0 is on PB.27 */
|
||||
# define STATUS_LED_PERIOD (1 * CONFIG_SYS_HZ)
|
||||
# define STATUS_LED_STATE STATUS_LED_OFF
|
||||
# define STATUS_LED_BIT1 0x00000020 /* LED 1 is on PB.26 */
|
||||
# define STATUS_LED_PERIOD1 (1 * CONFIG_SYS_HZ)
|
||||
# define STATUS_LED_STATE1 STATUS_LED_OFF
|
||||
/* IDE LED usable for other purposes, too */
|
||||
# define STATUS_LED_BIT2 0x00000008 /* LED 2 is on PB.28 */
|
||||
# define STATUS_LED_PERIOD2 (1 * CONFIG_SYS_HZ)
|
||||
# define STATUS_LED_STATE2 STATUS_LED_OFF
|
||||
|
||||
# define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */
|
||||
|
||||
# define STATUS_ILOCK_SWITCH 0x00004000 /* ILOCK is on PB.17 */
|
||||
|
||||
# define STATUS_ILOCK_PERIOD (CONFIG_SYS_HZ / 10) /* about every 100 ms */
|
||||
|
||||
# define STATUS_LED_YELLOW 0
|
||||
# define STATUS_LED_GREEN 1
|
||||
# define STATUS_LED_BOOT 2 /* IDE LED used for boot status */
|
||||
|
||||
/***** Someone else defines these *************************************/
|
||||
#elif defined(STATUS_LED_PAR)
|
||||
|
||||
|
||||
Reference in New Issue
Block a user