From 846d1d9c119b9046fa120a76e6d01192fa74ad52 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 14 Sep 2021 05:22:31 +0200 Subject: [PATCH 1/3] mtd: cqspi: Wait for transfer completion Wait for the read/write transfer finish bit get actually cleared, this does not happen immediately on at least SoCFPGA Gen5. Signed-off-by: Marek Vasut Reviewed-by: Jagan Teki Cc: Vignesh R Cc: Pratyush Yadav --- drivers/spi/cadence_qspi_apb.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index 429ee335db..2cdf4c9c9f 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -858,6 +858,14 @@ cadence_qspi_apb_indirect_read_execute(struct cadence_spi_plat *plat, writel(CQSPI_REG_INDIRECTRD_DONE, plat->regbase + CQSPI_REG_INDIRECTRD); + /* Check indirect done status */ + ret = wait_for_bit_le32(plat->regbase + CQSPI_REG_INDIRECTRD, + CQSPI_REG_INDIRECTRD_DONE, 0, 10, 0); + if (ret) { + printf("Indirect read clear completion error (%i)\n", ret); + goto failrd; + } + return 0; failrd: @@ -1012,6 +1020,15 @@ cadence_qspi_apb_indirect_write_execute(struct cadence_spi_plat *plat, /* Clear indirect completion status */ writel(CQSPI_REG_INDIRECTWR_DONE, plat->regbase + CQSPI_REG_INDIRECTWR); + + /* Check indirect done status */ + ret = wait_for_bit_le32(plat->regbase + CQSPI_REG_INDIRECTWR, + CQSPI_REG_INDIRECTWR_DONE, 0, 10, 0); + if (ret) { + printf("Indirect write clear completion error (%i)\n", ret); + goto failwr; + } + if (bounce_buf) free(bounce_buf); return 0; From b3425a3f4e6f1625e3d06109d2193e70901a1683 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 30 Nov 2021 13:47:10 +0100 Subject: [PATCH 2/3] mtd: spi: Remove SF_DUAL_FLASH symbol from Kconfig This symbol is not used anywhere in the code. Just enable in couple of defconfigs but it does nothing that's why remove it. Signed-off-by: Michal Simek Reviewed-by: Jagan Teki --- drivers/mtd/spi/Kconfig | 6 ------ 1 file changed, 6 deletions(-) diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig index 408a53f861..2f56d46a38 100644 --- a/drivers/mtd/spi/Kconfig +++ b/drivers/mtd/spi/Kconfig @@ -129,12 +129,6 @@ config SPI_FLASH_UNLOCK_ALL For legacy reasons, this option default to y. But if you intend to actually use the software protection bits you should say n here. -config SF_DUAL_FLASH - bool "SPI DUAL flash memory support" - help - Enable this option to support two flash memories connected to a single - controller. Currently Xilinx Zynq qspi supports this. - config SPI_FLASH_ATMEL bool "Atmel SPI flash support" help From d7b1d8259e62c781f2c87acfac08f3c0505030dd Mon Sep 17 00:00:00 2001 From: Ram Narayanan Date: Mon, 29 Nov 2021 21:54:58 -0800 Subject: [PATCH 3/3] mtd: spi-nor-ids: Add support for W25Q01JV Adds support for Winbond's new 128MB spi nor flash. datasheet: https://www.winbond.com/resource-files/W25Q01JV%20SPI%20RevC%2005032021%20Plus%20dummy.pdf Signed-off-by: Ram Narayanan Cc: Jagan Teki Reviewed-by: Jagan Teki --- drivers/mtd/spi/spi-nor-ids.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 3ae7bb1ed7..b551ebd75e 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -355,6 +355,11 @@ const struct flash_info spi_nor_ids[] = { SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, + { + INFO("w25q01jv", 0xef4021, 0, 64 * 1024, 2048, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) + }, { INFO("w25q80", 0xef5014, 0, 64 * 1024, 16, SECT_4K) }, { INFO("w25q80bl", 0xef4014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("w25q16cl", 0xef4015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },