Merge branch 'master' of git://git.denx.de/u-boot-arm

* 'master' of git://git.denx.de/u-boot-arm: davinci: Remove unwanted memsize.c from hawkboard's nand spl build devkit8000: Move CONFIG_SYS_TEXT_BASE out of bss da850evm: pass board revision info to kernel arch/arm/include/asm/arch-omap5/clocks.h: Fix GCC 4.2 warnings arch/arm/cpu/armv7/omap-common/clocks-common.c: Fix GCC 4.6 warnings arch/arm/cpu/armv7/omap-common/spl.c: Fix GCC 4.2 warnings MX35: flea3: changes due to hardware revision B MX: serial_mxc: cleanup removing nasty #ifdef M28: Fix OB1 bug in GPIO driver MXS: Add static annotations to dma driver apbh_dma: return error value on timeout Efika: Configure additional regulators for HDMI output mx5: Correct a warning in clock.c MC13892: Add REGMODE0 bits definitions mx51evk: Configure the pins as GPIOs prior to using gpio_get_value mx53smd: Configure the pins as GPIOs prior to using gpio_get_value mx53evk: Configure the pins as GPIOs prior to using gpio_get_value mx53ard: Configure the pins as GPIOs prior to using gpio_get_value mx53loco: Configure the pins as GPIOs prior to using gpio_get_value OMAP3: Add SPL_BOARD_INIT hook AM3517 CraneBoard: Add SPL support AM3517: Add SPL support OMAP3: Add SPL support to omap3_evm OMAP3: Add SPL support to Beagleboard OMAP3 SPL: Add identify_nand_chip function OMAP3 SPL: Rework memory initalization and devkit8000 support OMAP3: Suffix all Micron memory timing parts with their speed OMAP3: Add optimal SDRC autorefresh control values omap3: mem: Add MCFG helper macro OMAP3: Remove get_mem_type prototype OMAP3: Change mem_ok to clear again after reading back OMAP3: Add a helper function to set timings in SDRC OMAP3: Update SDRC dram_init to always call make_cs1_contiguous() omap3: mem: Comment enable_gpmc_cs_config more ARM: davici_emac: Fix condition for number of phy detects arm: printf() is not available in some SPL configurations arm, davinci: add support for am1808 based enbw_cmc board arm, davinci: move misc function in arch tree arm, board/davinci/common/misc.c: Codingstyle cleanup arm, davinci, da850: add uart1 tx rx pinmux config arm, davinci: move davinci_rtc struct to hardware.h arm, davinci: Remove duplication of pinmux configuration code arm, hawkboard: Use the pinmux configurations defined in the arch tree arm, da850evm: Use the pinmux configurations defined in the arch tree arm, da850: Add pinmux configurations to the arch tree arm, da850evm: Do pinmux configuration for EMAC together with other pinmuxes arm, hawkboard: Remove obsolete struct pinmux_config i2c_pins arm, davinci: Move pinmux functions from board to arch tree arm, arm926ejs: always do cpu critical inits omap_gpmc: use SOFTECC in SPL if it's enabled nand_spl_simple: add support for software ECC AM3517: move AM3517 specific mux defines to generic header AM35xx: add EMAC support davinci_emac: hardcode 100Mbps for AM35xx and RMII davinci_emac: fix for running with dcache enabled arm926ejs: add noop implementation for dcache ops davinci_emac: conditionally compile specific PHY support davinci_emac: use internal addresses in buffer descriptors davinci_emac: move arch-independent defines to separate header BeagleBoard: config: Really switch to ttyO2 ARM: davinci_dm6467Tevm: Fix build breakage ARM: OMAP: Remove STACKSIZE for IRQ and FIQ if unused ARM: OMAP3: Remove unused define SDRC_R_C_B ARM: OMAP3: Remove unused define CONFIG_OMAP3430 omap4: fix IO setting omap4+: streamline CONFIG_SYS_TEXT_BASE and other SDRAM addresses omap4460: add ES1.1 identification omap4: emif: fix error in driver omap: remove I2C from SPL omap4460: fix TPS initialization omap: fix cache line size for omap3/omap4 boards omap4: ttyO2 instead of ttyS2 in default bootargs omap: Improve PLL parameter calculation tool start.S: remove omap3 specific code from start.S armv7: setup vector armv7: include armv7/cpu.c in SPL build armv7: disable L2 cache in cleanup_before_linux() arm, arm926ejs: Fix clear bss loop for zero length bss PXA: Move colibri_pxa270 to board/toradex/ PXA: Flip colibri_pxa27x to pxa-common.h PXA: Introduce common configuration header for PXA PXA: Rename pxa_dram_init to pxa2xx_dram_init PXA: Squash extern pxa_dram_init() PXA: Export cpu_is_ and pxa_dram_init functions PXA: Cleanup Colibri PXA270 PXA: Replace timer driver PXA: Add cpuinfo display for PXA2xx PXA: Separate PXA2xx CPU init PXA: Rename CONFIG_PXA2[57]X to CONFIG_CPU_PXA2[57]X PXA: Unify vpac270 environment size PXA: Enable command line editing for vpac270 PXA: Adapt Voipac PXA270 to OneNAND SPL PXA: Drop Voipac PXA270 OneNAND IPL PXA: Fixup PXA25x boards after start.S update PXA: Re-add the Dcache locking as RAM for pxa250 PXA: Rework start.S to be closer to other ARMs PXA: Drop XM250 board PXA: Drop PLEB2 board PXA: Drop CRADLE board PXA: Drop CERF250 board Fix regression in SMDK6400 nand: Add common functions to linux/mtd/nand.h Ethernut 5 board support net: Armada100: Fix compilation warnings ARM: remove duplicated code for LaCie boards ARM: add support for LaCie 2Big Network v2 mvsata: fix ide_preinit for missing disks netspace_v2: Read Ethernet MAC address from EEPROM omap3evm: Add support for EFI partitions part_efi: Fix compile errors
2011-12-07 09:09:58 +01:00
parent 99dee4b2ef 15422043c4
commit c786f54b9a
219 changed files with 5433 additions and 6288 deletions
--- a/include/configs/am3517_crane.h
+++ b/include/configs/am3517_crane.h
@@ -64,7 +64,6 @@
 /*
 * DDR related
 */
-#define CONFIG_OMAP3_MICRON_DDR		1	/* Micron DDR */
 #define CONFIG_SYS_CS0_SIZE		(256 * 1024 * 1024)

 /*
@@ -264,22 +263,14 @@
 * The stack sizes are set up in start.S using the settings below
 */
 #define CONFIG_STACKSIZE	(128 << 10)	/* regular stack 128 KiB */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ	(4 << 10)	/* IRQ stack 4 KiB */
-#define CONFIG_STACKSIZE_FIQ	(4 << 10)	/* FIQ stack 4 KiB */
-#endif

 /*-----------------------------------------------------------------------
 * Physical Memory Map
 */
 #define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
 #define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
-#define PHYS_SDRAM_1_SIZE	(32 << 20)	/* at least 32 MiB */
 #define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1

-/* SDRAM Bank Allocation method */
-#define SDRC_R_B_C		1
-
 /*-----------------------------------------------------------------------
 * FLASH and environment organization
 */
@@ -330,4 +321,59 @@
 #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
 					 CONFIG_SYS_INIT_RAM_SIZE - \
 					 GENERATED_GBL_DATA_SIZE)
+
+/* Defines for SPL */
+#define CONFIG_SPL
+#define CONFIG_SPL_NAND_SIMPLE
+#define CONFIG_SPL_TEXT_BASE		0x40200800
+#define CONFIG_SPL_MAX_SIZE		(45 * 1024)
+#define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK
+
+#define CONFIG_SPL_BSS_START_ADDR	0x80000000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x80000		/* 512 KB */
+
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /* address 0x60000 */
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x200 /* 256 KB */
+#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION	1
+#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME	"u-boot.img"
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBDISK_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_FAT_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_POWER_SUPPORT
+#define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/omap-common/u-boot-spl.lds"
+
+/* NAND boot config */
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_COUNT	64
+#define CONFIG_SYS_NAND_PAGE_SIZE	2048
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
+#define CONFIG_SYS_NAND_ECCPOS		{2, 3, 4, 5, 6, 7, 8, 9,\
+						10, 11, 12, 13}
+#define CONFIG_SYS_NAND_ECCSIZE		512
+#define CONFIG_SYS_NAND_ECCBYTES	3
+#define CONFIG_SYS_NAND_ECCSTEPS	(CONFIG_SYS_NAND_PAGE_SIZE / \
+						CONFIG_SYS_NAND_ECCSIZE)
+#define CONFIG_SYS_NAND_ECCTOTAL	(CONFIG_SYS_NAND_ECCBYTES * \
+						CONFIG_SYS_NAND_ECCSTEPS)
+#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
+
+/*
+ * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
+ * 64 bytes before this address should be set aside for u-boot.img's
+ * header. That is 0x800FFFC0--0x80100000 should not be used for any
+ * other needs.
+ */
+#define CONFIG_SYS_TEXT_BASE		0x80100000
+#define CONFIG_SYS_SPL_MALLOC_START	0x80208000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
+
 #endif /* __CONFIG_H */
--- a/include/configs/am3517_evm.h
+++ b/include/configs/am3517_evm.h
@@ -63,7 +63,6 @@
 /*
 * DDR related
 */
-#define CONFIG_OMAP3_MICRON_DDR		1	/* Micron DDR */
 #define CONFIG_SYS_CS0_SIZE		(256 * 1024 * 1024)

 /*
@@ -263,22 +262,14 @@
 * The stack sizes are set up in start.S using the settings below
 */
 #define CONFIG_STACKSIZE	(128 << 10)	/* regular stack 128 KiB */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ	(4 << 10)	/* IRQ stack 4 KiB */
-#define CONFIG_STACKSIZE_FIQ	(4 << 10)	/* FIQ stack 4 KiB */
-#endif

 /*-----------------------------------------------------------------------
 * Physical Memory Map
 */
 #define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
 #define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
-#define PHYS_SDRAM_1_SIZE	(32 << 20)	/* at least 32 MiB */
 #define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1

-/* SDRAM Bank Allocation method */
-#define SDRC_R_B_C		1
-
 /*-----------------------------------------------------------------------
 * FLASH and environment organization
 */
@@ -331,4 +322,59 @@
 #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
 					 CONFIG_SYS_INIT_RAM_SIZE - \
 					 GENERATED_GBL_DATA_SIZE)
+
+/* Defines for SPL */
+#define CONFIG_SPL
+#define CONFIG_SPL_NAND_SIMPLE
+#define CONFIG_SPL_TEXT_BASE		0x40200800
+#define CONFIG_SPL_MAX_SIZE		(45 * 1024)
+#define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK
+
+#define CONFIG_SPL_BSS_START_ADDR	0x80000000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x80000		/* 512 KB */
+
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /* address 0x60000 */
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x200 /* 256 KB */
+#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION	1
+#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME	"u-boot.img"
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBDISK_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_FAT_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_POWER_SUPPORT
+#define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/omap-common/u-boot-spl.lds"
+
+/* NAND boot config */
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_COUNT	64
+#define CONFIG_SYS_NAND_PAGE_SIZE	2048
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
+#define CONFIG_SYS_NAND_ECCPOS		{2, 3, 4, 5, 6, 7, 8, 9,\
+						10, 11, 12, 13}
+#define CONFIG_SYS_NAND_ECCSIZE		512
+#define CONFIG_SYS_NAND_ECCBYTES	3
+#define CONFIG_SYS_NAND_ECCSTEPS	(CONFIG_SYS_NAND_PAGE_SIZE / \
+						CONFIG_SYS_NAND_ECCSIZE)
+#define CONFIG_SYS_NAND_ECCTOTAL	(CONFIG_SYS_NAND_ECCBYTES * \
+						CONFIG_SYS_NAND_ECCSTEPS)
+#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
+
+/*
+ * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
+ * 64 bytes before this address should be set aside for u-boot.img's
+ * header. That is 0x800FFFC0--0x80100000 should not be used for any
+ * other needs.
+ */
+#define CONFIG_SYS_TEXT_BASE		0x80100000
+#define CONFIG_SYS_SPL_MALLOC_START	0x80208000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
+
 #endif /* __CONFIG_H */
--- a/include/configs/apollon.h
+++ b/include/configs/apollon.h
@@ -211,10 +211,6 @@
 * The stack sizes are set up in start.S using the settings below
 */
 #define	CONFIG_STACKSIZE SZ_128K	/* regular stack */
-#ifdef	CONFIG_USE_IRQ
-# define	CONFIG_STACKSIZE_IRQ SZ_4K	/* IRQ stack */
-# define	CONFIG_STACKSIZE_FIQ SZ_4K	/* FIQ stack */
-#endif

 /*-----------------------------------------------------------------------
 * Physical Memory Map
--- a/include/configs/balloon3.h
+++ b/include/configs/balloon3.h
@@ -25,7 +25,7 @@
 /*
 * High Level Board Configuration Options
 */
-#define	CONFIG_PXA27X		1	/* Marvell PXA270 CPU */
+#define	CONFIG_CPU_PXA27X		1	/* Marvell PXA270 CPU */
 #define	CONFIG_BALLOON3		1	/* Balloon3 board */

 /*
--- a/include/configs/cerf250.h
+++ b/include/configs/cerf250.h
@@ -1,229 +0,0 @@
-/*
- * (C) Copyright 2002
- * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * Configuation settings for the CERF250 board.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_PXA250		1	/* This is an PXA250 CPU    */
-#define CONFIG_CERF250		1	/* on Cerf PXA Board	    */
-#define CONFIG_BOARD_LATE_INIT
-#define CONFIG_BAUDRATE		38400
-#define	CONFIG_SYS_TEXT_BASE	0x0
-
-#undef	CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff */
-
-/* we will never enable dcache, because we have to setup MMU first */
-#define CONFIG_SYS_DCACHE_OFF
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN	    (CONFIG_ENV_SIZE + 128*1024)
-
-/*
- * Hardware drivers
- */
-#define CONFIG_SMC91111
-#define CONFIG_SMC91111_BASE 0x04000300
-#define CONFIG_SMC_USE_32_BIT
-
-/*
- * select serial console configuration
- */
-#define CONFIG_PXA_SERIAL
-#define CONFIG_FFUART	     1	/* we use FFUART on CERF PXA */
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-
-#define CONFIG_BOOTDELAY	3
-#define CONFIG_ETHADDR		00:D0:CA:F1:3C:D2
-#define CONFIG_NETMASK		255.255.255.0
-#define CONFIG_IPADDR		192.168.0.5
-#define CONFIG_SERVERIP		192.168.0.2
-#define CONFIG_BOOTCOMMAND	"bootm 0xC0000"
-#define CONFIG_BOOTARGS		"root=/dev/mtdblock3 rootfstype=jffs2 console=ttyS0,38400"
-#define CONFIG_CMDLINE_TAG
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2		/* which serial port to use */
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_HUSH_PARSER		1
-#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
-
-#define CONFIG_SYS_LONGHELP					/* undef to save memory		*/
-#ifdef CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT			"uboot$ "	/* Monitor Command Prompt */
-#else
-#define CONFIG_SYS_PROMPT			"=> "		/* Monitor Command Prompt */
-#endif
-#define CONFIG_SYS_CBSIZE			256			/* Console I/O Buffer Size	*/
-#define CONFIG_SYS_PBSIZE			(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-										/* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS			16			/* max number of command args	*/
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
-#define CONFIG_SYS_DEVICE_NULLDEV	1
-
-#define CONFIG_SYS_MEMTEST_START	0xa0400000	/* memtest works on	*/
-#define CONFIG_SYS_MEMTEST_END		0xa0800000	/* 4 ... 8 MB in DRAM	*/
-
-#define CONFIG_SYS_LOAD_ADDR		0xa2000000	/* default load address */
-
-#define CONFIG_SYS_HZ			1000
-#define CONFIG_SYS_CPUSPEED		0x141		/* set core clock to 400/200/100 MHz */
-
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-
-/*
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE		(128*1024)	/* regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
-#endif
-
-/*
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS		1		/* we have 1 bank of DRAM */
-#define PHYS_SDRAM_1			0xa0000000	/* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE		0x04000000	/* 64 MB */
-
-#define PHYS_FLASH_1			0x00000000	/* Flash Bank #1 */
-#define PHYS_FLASH_2			0x04000000	/* Flash Bank #2 */
-#define PHYS_FLASH_SIZE			0x02000000	/* 32 MB */
-#define PHYS_FLASH_BANK_SIZE		0x02000000	/* 32 MB Banks */
-#define PHYS_FLASH_SECT_SIZE		0x00040000	/* 256 KB sectors (x2) */
-
-#define CONFIG_SYS_DRAM_BASE			0xa0000000
-#define CONFIG_SYS_DRAM_SIZE			0x04000000
-
-#define CONFIG_SYS_FLASH_BASE			PHYS_FLASH_1
-
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
-#define	CONFIG_SYS_INIT_SP_ADDR		(GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
-
-/*
- * GPIO settings
- */
-
-
-#define CONFIG_SYS_GPSR0_VAL		0x00408030
-#define CONFIG_SYS_GPSR1_VAL		0x00BFA882
-#define CONFIG_SYS_GPSR2_VAL		0x0001C000
-#define CONFIG_SYS_GPCR0_VAL		0xC0031100
-#define CONFIG_SYS_GPCR1_VAL		0xFC400300
-#define CONFIG_SYS_GPCR2_VAL		0x00003FFF
-#define CONFIG_SYS_GPDR0_VAL		0xC0439330
-#define CONFIG_SYS_GPDR1_VAL		0xFCFFAB82
-#define CONFIG_SYS_GPDR2_VAL		0x0001FFFF
-#define CONFIG_SYS_GAFR0_L_VAL		0x80000000
-#define CONFIG_SYS_GAFR0_U_VAL		0xA5000010
-#define CONFIG_SYS_GAFR1_L_VAL		0x60008018
-#define CONFIG_SYS_GAFR1_U_VAL		0xAAA5AAAA
-#define CONFIG_SYS_GAFR2_L_VAL		0xAAA0000A
-#define CONFIG_SYS_GAFR2_U_VAL		0x00000002
-
-#define CONFIG_SYS_PSSR_VAL		0x20
-
-#define	CONFIG_SYS_CCCR			CCCR_L27|CCCR_M2|CCCR_N10
-#define	CONFIG_SYS_CKEN			0x0
-
-/*
- * Memory settings
- */
-#define CONFIG_SYS_MSC0_VAL		0x12447FF0
-#define CONFIG_SYS_MSC1_VAL		0x12BC5554
-#define CONFIG_SYS_MSC2_VAL		0x7FF97FF1
-#define CONFIG_SYS_MDCNFG_VAL		0x00001AC9
-#define CONFIG_SYS_MDREFR_VAL		0x03CDC017
-#define CONFIG_SYS_MDMRS_VAL		0x00000000
-#define	CONFIG_SYS_FLYCNFG_VAL		0x00000000
-#define	CONFIG_SYS_SXCNFG_VAL		0x00000000
-
-/*
- * PCMCIA and CF Interfaces
- */
-#define CONFIG_SYS_MECR_VAL		0x00000000
-#define CONFIG_SYS_MCMEM0_VAL		0x00010504
-#define CONFIG_SYS_MCMEM1_VAL		0x00010504
-#define CONFIG_SYS_MCATT0_VAL		0x00010504
-#define CONFIG_SYS_MCATT1_VAL		0x00010504
-#define CONFIG_SYS_MCIO0_VAL		0x00004715
-#define CONFIG_SYS_MCIO1_VAL		0x00004715
-
-#define _LED			0x08000010	/*check this */
-#define LED_BLANK		0x08000040
-#define LED_GPIO		0x10
-
-/*
- * FLASH and environment organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max number of sectors on one chip    */
-
-/* timeout values are in ticks */
-#define CONFIG_SYS_FLASH_ERASE_TOUT	(25*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	(25*CONFIG_SYS_HZ) /* Timeout for Flash Write */
-
-#define CONFIG_SYS_MONITOR_LEN		0x40000		/* 256 KiB */
-#define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_ADDR		(PHYS_FLASH_1 + CONFIG_SYS_MONITOR_LEN)
-#define CONFIG_ENV_SIZE		0x40000	/* Total Size of Environment Sector	*/
-
-
-#endif	/* __CONFIG_H */
--- a/include/configs/cm_t35.h
+++ b/include/configs/cm_t35.h
@@ -38,7 +38,6 @@
 */
 #define CONFIG_OMAP		1	/* in a TI OMAP core */
 #define CONFIG_OMAP34XX		1	/* which is a 34XX */
-#define CONFIG_OMAP3430		1	/* which is in a 3430 */
 #define CONFIG_CM_T3X		1	/* working with CM-T35 and CM-T3730 */

 #define CONFIG_SYS_TEXT_BASE	0x80008000
@@ -284,10 +283,6 @@
 * The stack sizes are set up in start.S using the settings below
 */
 #define CONFIG_STACKSIZE	(128 << 10)	/* regular stack 128 KiB */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ	(4 << 10)	/* IRQ stack 4 KiB */
-#define CONFIG_STACKSIZE_FIQ	(4 << 10)	/* FIQ stack 4 KiB */
-#endif

 /*-----------------------------------------------------------------------
 * Physical Memory Map
@@ -296,9 +291,6 @@
 #define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
 #define PHYS_SDRAM_1_SIZE	(32 << 20)	/* at least 32 MiB */

-/* SDRAM Bank Allocation method */
-#define SDRC_R_B_C		1
-
 /*-----------------------------------------------------------------------
 * FLASH and environment organization
 */
--- a/include/configs/colibri_pxa270.h
+++ b/include/configs/colibri_pxa270.h
@@ -25,21 +25,15 @@
 /*
 * High Level Board Configuration Options
 */
-#define	CONFIG_PXA27X		1	/* Marvell PXA270 CPU */
-#define	CONFIG_VPAC270		1	/* Toradex Colibri PXA270 board */
-
-#undef	CONFIG_BOARD_LATE_INIT
-#undef	CONFIG_USE_IRQ
-#undef	CONFIG_SKIP_LOWLEVEL_INIT
+#define	CONFIG_CPU_PXA27X		1	/* Marvell PXA270 CPU */
+#define	CONFIG_SYS_TEXT_BASE		0x0

 /*
 * Environment settings
 */
-#define	CONFIG_ENV_SIZE			0x4000
-#define	CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
-#define	CONFIG_SYS_TEXT_BASE		0x0
-#define	CONFIG_ENV_OVERWRITE		/* override default environment */
-
+#define	CONFIG_ENV_OVERWRITE
+#define	CONFIG_SYS_MALLOC_LEN		(128 * 1024)
+#define	CONFIG_ARCH_CPU_INIT
 #define	CONFIG_BOOTCOMMAND						\
 	"if mmc init && fatload mmc 0 0xa0000000 uImage; then "		\
 		"bootm 0xa0000000; "					\
@@ -53,8 +47,8 @@
 #define	CONFIG_BOOTDELAY		2	/* Autoboot delay */
 #define	CONFIG_CMDLINE_TAG
 #define	CONFIG_SETUP_MEMORY_TAGS
-
 #define	CONFIG_LZMA			/* LZMA compression support */
+#define	CONFIG_OF_LIBFDT

 /*
 * Serial Console Configuration
@@ -96,59 +90,43 @@
 #define	CONFIG_BOOTP_HOSTNAME
 #endif

-/*
- * MMC Card Configuration
- */
-#ifdef	CONFIG_CMD_MMC
-#define	CONFIG_MMC
-#define	CONFIG_PXA_MMC
-#define	CONFIG_SYS_MMC_BASE		0xF0000000
-#define	CONFIG_CMD_FAT
-#define	CONFIG_DOS_PARTITION
-#endif
-
-/*
- * KGDB
- */
-#ifdef	CONFIG_CMD_KGDB
-#define	CONFIG_KGDB_BAUDRATE		230400		/* speed to run kgdb serial port */
-#define	CONFIG_KGDB_SER_INDEX		2		/* which serial port to use */
-#endif
-
 /*
 * HUSH Shell Configuration
 */
 #define	CONFIG_SYS_HUSH_PARSER		1
 #define	CONFIG_SYS_PROMPT_HUSH_PS2	"> "

-#define	CONFIG_SYS_LONGHELP				/* undef to save memory	*/
+#define	CONFIG_SYS_LONGHELP
 #ifdef	CONFIG_SYS_HUSH_PARSER
-#define	CONFIG_SYS_PROMPT		"$ "		/* Monitor Command Prompt */
+#define	CONFIG_SYS_PROMPT		"$ "
 #else
-#define	CONFIG_SYS_PROMPT		"=> "		/* Monitor Command Prompt */
+#define	CONFIG_SYS_PROMPT		"=> "
 #endif
-#define	CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size */
-#define	CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
-#define	CONFIG_SYS_MAXARGS		16		/* max number of command args */
-#define	CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
+#define	CONFIG_SYS_CBSIZE		256
+#define	CONFIG_SYS_PBSIZE		\
+	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define	CONFIG_SYS_MAXARGS		16
+#define	CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
 #define	CONFIG_SYS_DEVICE_NULLDEV	1
+#define	CONFIG_CMDLINE_EDITING		1
+#define	CONFIG_AUTO_COMPLETE		1
+

 /*
 * Clock Configuration
 */
-#undef	CONFIG_SYS_CLKS_IN_HZ
-#define	CONFIG_SYS_HZ			3250000		/* Timer @ 3250000 Hz */
-#define CONFIG_SYS_CPUSPEED		0x290		/* 520 MHz */
+#define	CONFIG_SYS_HZ			1000		/* Timer @ 3250000 Hz */
+#define	CONFIG_SYS_CPUSPEED		0x290		/* 520MHz */

 /*
 * Stack sizes
 *
 * The stack sizes are set up in start.S using the settings below
 */
-#define	CONFIG_STACKSIZE		(128*1024)	/* regular stack */
+#define	CONFIG_STACKSIZE		(128 * 1024)	/* regular stack */
 #ifdef	CONFIG_USE_IRQ
-#define	CONFIG_STACKSIZE_IRQ		(4*1024)	/* IRQ stack */
-#define	CONFIG_STACKSIZE_FIQ		(4*1024)	/* FIQ stack */
+#define	CONFIG_STACKSIZE_IRQ		(4 * 1024)	/* IRQ stack */
+#define	CONFIG_STACKSIZE_FIQ		(4 * 1024)	/* FIQ stack */
 #endif

 /*
@@ -164,10 +142,9 @@
 #define CONFIG_SYS_MEMTEST_START	0xa0400000	/* memtest works on */
 #define CONFIG_SYS_MEMTEST_END		0xa0800000	/* 4 ... 8 MB in DRAM */

-#define	CONFIG_SYS_LOAD_ADDR		(0xa1000000)
-
+#define	CONFIG_SYS_LOAD_ADDR		PHYS_SDRAM_1
 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
-#define	CONFIG_SYS_INIT_SP_ADDR		(GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
+#define	CONFIG_SYS_INIT_SP_ADDR		0x5c010000

 /*
 * NOR FLASH
@@ -182,8 +159,8 @@
 #define	CONFIG_SYS_MAX_FLASH_SECT	(4 + 255)
 #define	CONFIG_SYS_MAX_FLASH_BANKS	1

-#define	CONFIG_SYS_FLASH_ERASE_TOUT	(25*CONFIG_SYS_HZ)
-#define	CONFIG_SYS_FLASH_WRITE_TOUT	(25*CONFIG_SYS_HZ)
+#define	CONFIG_SYS_FLASH_ERASE_TOUT	(25 * CONFIG_SYS_HZ)
+#define	CONFIG_SYS_FLASH_WRITE_TOUT	(25 * CONFIG_SYS_HZ)

 #define	CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
 #define	CONFIG_SYS_FLASH_PROTECTION		1
@@ -195,14 +172,15 @@
 #define	CONFIG_SYS_ENV_IS_NOWHERE
 #endif

-#define	CONFIG_SYS_MONITOR_BASE		0x000000
-#define	CONFIG_SYS_MONITOR_LEN		0x40000
-
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_LEN)
-#define CONFIG_ENV_SECT_SIZE	0x40000
-#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+#define	CONFIG_SYS_MONITOR_BASE		0x0
+#define	CONFIG_SYS_MONITOR_LEN		0x80000

+#define	CONFIG_ENV_ADDR			\
+			(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+#define	CONFIG_ENV_SIZE			0x40000
+#define	CONFIG_ENV_SECT_SIZE		0x40000
+#define CONFIG_ENV_ADDR_REDUND		(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND		(CONFIG_ENV_SIZE)

 /*
 * GPIO settings
@@ -262,17 +240,6 @@
 #define	CONFIG_SYS_MCIO0_VAL	0x0001430f
 #define	CONFIG_SYS_MCIO1_VAL	0x0001430f

-/*
- * USB
- */
-#ifdef CONFIG_CMD_USB
-#define	CONFIG_USB_OHCI_NEW
-#define	CONFIG_SYS_USB_OHCI_CPU_INIT
-#define	CONFIG_SYS_USB_OHCI_BOARD_INIT
-#define	CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
-#define	CONFIG_SYS_USB_OHCI_REGS_BASE	0x4C000000
-#define	CONFIG_SYS_USB_OHCI_SLOT_NAME	"tdex270"
-#define	CONFIG_USB_STORAGE
-#endif
+#include "pxa-common.h"

 #endif	/* __CONFIG_H */
--- a/include/configs/cradle.h
+++ b/include/configs/cradle.h
@@ -1,358 +0,0 @@
-/*
- * (C) Copyright 2002
- * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_PXA250           1       /* This is an PXA250 CPU    */
-#define CONFIG_HHP_CRADLE       1       /* on an Cradle Board       */
-
-#undef CONFIG_USE_IRQ                   /* we don't need IRQ/FIQ stuff */
-
-/* we will never enable dcache, because we have to setup MMU first */
-#define CONFIG_SYS_DCACHE_OFF
-#define	CONFIG_SYS_TEXT_BASE		0x0
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
-
-/*
- * Hardware drivers
- */
-#define CONFIG_SMC91111
-#define CONFIG_SMC91111_BASE 0x10000300
-#define CONFIG_SMC91111_EXT_PHY
-#define CONFIG_SMC_USE_32_BIT
-
-/*
- * select serial console configuration
- */
-#define CONFIG_PXA_SERIAL
-#define CONFIG_FFUART          1       /* we use FFUART on LUBBOCK */
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_BAUDRATE         115200
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-
-#define CONFIG_BOOTDELAY        3
-#define CONFIG_BOOTARGS         "root=/dev/mtdblock2 console=ttyS0,115200"
-#define CONFIG_ETHADDR          08:00:3e:26:0a:5b
-#define CONFIG_NETMASK          255.255.0.0
-#define CONFIG_IPADDR           192.168.0.21
-#define CONFIG_SERVERIP         192.168.0.250
-#define CONFIG_BOOTCOMMAND      "bootm 40000"
-#define CONFIG_CMDLINE_TAG
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP                            /* undef to save memory         */
-#define CONFIG_SYS_PROMPT              "=> "   /* Monitor Command Prompt       */
-#define CONFIG_SYS_CBSIZE              256             /* Console I/O Buffer Size      */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS             16              /* max number of command args   */
-#define CONFIG_SYS_BARGSIZE            CONFIG_SYS_CBSIZE      /* Boot Argument Buffer Size    */
-
-#define CONFIG_SYS_MEMTEST_START       0xa0400000      /* memtest works on     */
-#define CONFIG_SYS_MEMTEST_END         0xa0800000      /* 4 ... 8 MB in DRAM   */
-
-#define CONFIG_SYS_LOAD_ADDR           0xa2000000      /* default load address */
-
-#define CONFIG_SYS_HZ			1000
-#define CONFIG_SYS_CPUSPEED            0x141           /* set core clock to 200/200/100 MHz */
-
-						/* valid baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
-
-/*
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE        (128*1024)      /* regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ    (4*1024)        /* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ    (4*1024)        /* FIQ stack */
-#endif
-
-/*
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS    1          /* we have 1 bank of DRAM */
-#define PHYS_SDRAM_1            0xa0000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE       0x01000000 /* 64 MB */
-
-#define PHYS_FLASH_1            0x00000000 /* Flash Bank #1 */
-#define PHYS_FLASH_2            0x04000000 /* Flash Bank #1 */
-#define PHYS_FLASH_SIZE         0x02000000 /* 32 MB */
-
-#define CONFIG_SYS_DRAM_BASE           0xa0000000
-#define CONFIG_SYS_DRAM_SIZE           0x04000000
-
-#define CONFIG_SYS_FLASH_BASE          PHYS_FLASH_1
-
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
-#define	CONFIG_SYS_INIT_SP_ADDR		(GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
-
-/*
- * FLASH and environment organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS     1     /* max number of memory banks           */
-#define CONFIG_SYS_MAX_FLASH_SECT      32    /* max number of sectors on one chip    */
-
-/* timeout values are in ticks */
-#define CONFIG_SYS_FLASH_ERASE_TOUT    (2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
-#define CONFIG_SYS_FLASH_WRITE_TOUT    (2*CONFIG_SYS_HZ) /* Timeout for Flash Write */
-
-#define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_ADDR				0x00020000	/* absolute address for now   */
-#define CONFIG_ENV_SIZE				0x20000	   /* 8K ouch, this may later be */
-
-/******************************************************************************
- *
- * CPU specific defines
- *
- ******************************************************************************/
-
-/*
- * GPIO settings
- *
- * GPIO pin assignments
- * GPIO     Name        Dir Out AF
- * 0        NC
- * 1        NC
- * 2        SIRQ1       I
- * 3        SIRQ2       I
- * 4        SIRQ3       I
- * 5        DMAACK1     O   0
- * 6        DMAACK2     O   0
- * 7        DMAACK3     O   0
- * 8        TC1         O   0
- * 9        TC2         O   0
- * 10       TC3         O   0
- * 11       nDMAEN      O   1
- * 12       AENCTRL     O   0
- * 13       PLDTC       O   0
- * 14       ETHIRQ      I
- * 15       NC
- * 16       NC
- * 17       NC
- * 18       RDY         I
- * 19       DMASIO      I
- * 20       ETHIRQ      NC
- * 21       NC
- * 22       PGMEN       O   1    FIXME for debug only enable flash
- * 23       NC
- * 24       NC
- * 25       NC
- * 26       NC
- * 27       NC
- * 28       NC
- * 29       NC
- * 30       NC
- * 31       NC
- * 32       NC
- * 33       NC
- * 34       FFRXD       I       01
- * 35       FFCTS       I       01
- * 36       FFDCD       I       01
- * 37       FFDSR       I       01
- * 38       FFRI        I       01
- * 39       FFTXD       O   1   10
- * 40       FFDTR       O   0   10
- * 41       FFRTS       O   0   10
- * 42       RS232FOFF   O   0   00
- * 43       NC
- * 44       NC
- * 45       IRSL0       O   0
- * 46       IRRX0       I       01
- * 47       IRTX0       O   0   10
- * 48       NC
- * 49       nIOWE       O   0
- * 50       NC
- * 51       NC
- * 52       NC
- * 53       NC
- * 54       NC
- * 55       NC
- * 56       NC
- * 57       NC
- * 58       DKDIRQ      I
- * 59       NC
- * 60       NC
- * 61       NC
- * 62       NC
- * 63       NC
- * 64       COMLED      O   0
- * 65       COMLED      O   0
- * 66       COMLED      O   0
- * 67       COMLED      O   0
- * 68       COMLED      O   0
- * 69       COMLED      O   0
- * 70       COMLED      O   0
- * 71       COMLED      O   0
- * 72       NC
- * 73       NC
- * 74       NC
- * 75       NC
- * 76       NC
- * 77       NC
- * 78       CSIO        O   1
- * 79       NC
- * 80       CSETH       O   1
- *
- * NOTE: All NC's are defined to be outputs
- *
- */
-/* Pin direction control */
-/* NOTE GPIO 0, 61, 62 are set for inputs due to CPLD SPAREs */
-#define CONFIG_SYS_GPDR0_VAL       0xfff3bf02
-#define CONFIG_SYS_GPDR1_VAL       0xfbffbf83
-#define CONFIG_SYS_GPDR2_VAL       0x0001ffff
-/* Set and Clear registers */
-#define CONFIG_SYS_GPSR0_VAL       0x00400800
-#define CONFIG_SYS_GPSR1_VAL       0x00000480
-#define CONFIG_SYS_GPSR2_VAL       0x00014000
-#define CONFIG_SYS_GPCR0_VAL       0x00000000
-#define CONFIG_SYS_GPCR1_VAL       0x00000000
-#define CONFIG_SYS_GPCR2_VAL       0x00000000
-/* Edge detect registers (these are set by the kernel) */
-#define CONFIG_SYS_GRER0_VAL       0x00000000
-#define CONFIG_SYS_GRER1_VAL       0x00000000
-#define CONFIG_SYS_GRER2_VAL       0x00000000
-#define CONFIG_SYS_GFER0_VAL       0x00000000
-#define CONFIG_SYS_GFER1_VAL       0x00000000
-#define CONFIG_SYS_GFER2_VAL       0x00000000
-/* Alternate function registers */
-#define CONFIG_SYS_GAFR0_L_VAL     0x00000000
-#define CONFIG_SYS_GAFR0_U_VAL     0x00000010
-#define CONFIG_SYS_GAFR1_L_VAL     0x900a9550
-#define CONFIG_SYS_GAFR1_U_VAL     0x00000008
-#define CONFIG_SYS_GAFR2_L_VAL     0x20000000
-#define CONFIG_SYS_GAFR2_U_VAL     0x00000002
-
-/*
- * Clocks, power control and interrupts
- */
-#define CONFIG_SYS_PSSR_VAL        0x00000020
-#define CONFIG_SYS_CCCR        0x00000141  /* 100 MHz memory, 200 MHz CPU  */
-#define CONFIG_SYS_CKEN        0x00000060  /* FFUART and STUART enabled    */
-#define CONFIG_SYS_ICMR        0x00000000  /* No interrupts enabled        */
-
-/* FIXME
- *
- * RTC settings
- * Watchdog
- *
- */
-
-/*
- * Memory settings
- *
- * FIXME Can ethernet be burst read and/or write?? This is set for lubbock
- *       Verify timings on all
- */
-#define CONFIG_SYS_MSC0_VAL        0x000023FA  /* flash bank    (cs0)   */
-/*#define CONFIG_SYS_MSC1_VAL        0x00003549  / * SuperIO bank  (cs2)   */
-#define CONFIG_SYS_MSC1_VAL        0x0000354c  /* SuperIO bank  (cs2)   */
-#define CONFIG_SYS_MSC2_VAL        0x00001224  /* Ethernet bank (cs4)   */
-#ifdef REDBOOT_WAY
-#define CONFIG_SYS_MDCNFG_VAL      0x00001aa1  /* FIXME can DTC be 01?     */
-#define CONFIG_SYS_MDMRS_VAL       0x00000000
-#define CONFIG_SYS_MDREFR_VAL      0x00018018
-#else
-#define CONFIG_SYS_MDCNFG_VAL      0x00001aa1  /* FIXME can DTC be 01?     */
-#define CONFIG_SYS_MDMRS_VAL       0x00000000
-#define CONFIG_SYS_MDREFR_VAL      0x00403018  /* Initial setting, individual bits set in lowlevel_init.S */
-#endif
-#define	CONFIG_SYS_FLYCNFG_VAL		0x00000000
-#define	CONFIG_SYS_SXCNFG_VAL		0x00000000
-
-/*
- * PCMCIA and CF Interfaces (NOT USED, these values from lubbock init)
- */
-#define CONFIG_SYS_MECR_VAL          0x00000000
-#define CONFIG_SYS_MCMEM0_VAL        0x00010504
-#define CONFIG_SYS_MCMEM1_VAL        0x00010504
-#define CONFIG_SYS_MCATT0_VAL        0x00010504
-#define CONFIG_SYS_MCATT1_VAL        0x00010504
-#define CONFIG_SYS_MCIO0_VAL         0x00004715
-#define CONFIG_SYS_MCIO1_VAL         0x00004715
-
-/* Board specific defines */
-
-/* LED defines */
-#define YELLOW    0x03
-#define RED       0x02
-#define GREEN     0x01
-#define OFF       0x00
-#define LED_IRDA0 0
-#define LED_IRDA1 2
-#define LED_IRDA2 4
-#define LED_IRDA3 6
-
-/* SuperIO defines */
-#define CRADLE_SIO_INDEX      0x2e
-#define CRADLE_SIO_DATA       0x2f
-
-/* IO defines */
-#define CRADLE_CPLD_PHYS      0x08000000
-#define CRADLE_SIO1_PHYS      0x08100000
-#define CRADLE_SIO2_PHYS      0x08200000
-#define CRADLE_SIO3_PHYS      0x08300000
-#define CRADLE_ETH_PHYS       0x10000000
-
-#ifndef __ASSEMBLY__
-
-/* global prototypes */
-void led_code(int code, int color);
-
-#endif
-
-#endif  /* __CONFIG_H */
--- a/include/configs/da850_am18xxevm.h
+++ b/include/configs/da850_am18xxevm.h
@@ -36,6 +36,7 @@
 #define CONFIG_MACH_DAVINCI_DA850_EVM
 #define CONFIG_ARM926EJS		/* arm926ejs CPU core */
 #define CONFIG_SOC_DA8XX		/* TI DA8xx SoC */
+#define CONFIG_SOC_DA850		/* TI DA850 SoC */
 #define CONFIG_SYS_CLK_FREQ		clk_get(DAVINCI_ARM_CLKID)
 #define CONFIG_SYS_OSCIN_FREQ		24000000
 #define CONFIG_SYS_TIMERBASE		DAVINCI_TIMER0_BASE
@@ -43,7 +44,7 @@
 #define CONFIG_SYS_HZ			1000
 #define CONFIG_SKIP_LOWLEVEL_INIT
 #define CONFIG_SYS_TEXT_BASE		0xc1080000
-
+#define CONFIG_DA850_AM18X_EVM
 /*
 * Memory Info
 */
--- a/include/configs/da850evm.h
+++ b/include/configs/da850evm.h
@@ -36,6 +36,7 @@
 #define CONFIG_MACH_DAVINCI_DA850_EVM
 #define CONFIG_ARM926EJS		/* arm926ejs CPU core */
 #define CONFIG_SOC_DA8XX		/* TI DA8xx SoC */
+#define CONFIG_SOC_DA850		/* TI DA850 SoC */
 #define CONFIG_SYS_CLK_FREQ		clk_get(DAVINCI_ARM_CLKID)
 #define CONFIG_SYS_OSCIN_FREQ		24000000
 #define CONFIG_SYS_TIMERBASE		DAVINCI_TIMER0_BASE
--- a/include/configs/davinci_dm6467Tevm.h
+++ b/include/configs/davinci_dm6467Tevm.h
@@ -23,6 +23,7 @@
 /* Spectrum Digital TMS320DM6467T EVM board */
 #define DAVINCI_DM6467EVM
 #define DAVINCI_DM6467TEVM
+#define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_SYS_USE_NAND
 #define CONFIG_SYS_NAND_SMALLPAGE

--- a/include/configs/devkit8000.h
+++ b/include/configs/devkit8000.h
@@ -34,10 +34,15 @@
 /* High Level Configuration Options */
 #define CONFIG_OMAP		1	/* in a TI OMAP core */
 #define CONFIG_OMAP34XX		1	/* which is a 34XX */
-#define CONFIG_OMAP3430		1	/* which is in a 3430 */
 #define CONFIG_OMAP3_DEVKIT8000	1	/* working with DevKit8000 */

-#define	CONFIG_SYS_TEXT_BASE	0x80008000
+/*
+ * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
+ * 64 bytes before this address should be set aside for u-boot.img's
+ * header. That is 0x800FFFC0--0x80100000 should not be used for any
+ * other needs.
+ */
+#define CONFIG_SYS_TEXT_BASE	0x80100000

 #define CONFIG_SDRC	/* The chip has SDRC controller */

@@ -68,10 +73,6 @@
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10))

 /* Hardware drivers */
-
-/* DDR - I use Micron DDR */
-#define CONFIG_OMAP3_MICRON_DDR		1
-
 /* DM9000 */
 #define CONFIG_NET_RETRY_COUNT		20
 #define	CONFIG_DRIVER_DM9000		1
@@ -276,20 +277,12 @@

 /* The stack sizes are set up in start.S using the settings below */
 #define CONFIG_STACKSIZE	(128 << 10)	/* regular stack 128 KiB */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ		(4 << 10)	/* IRQ stack 4 KiB */
-#define CONFIG_STACKSIZE_FIQ		(4 << 10)	/* FIQ stack 4 KiB */
-#endif

 /*  Physical Memory Map  */
 #define CONFIG_NR_DRAM_BANKS		2 /* CS1 may or may not be populated */
 #define PHYS_SDRAM_1			OMAP34XX_SDRC_CS0
-#define PHYS_SDRAM_1_SIZE		(128 << 20)	/* at least 128 MiB */
 #define PHYS_SDRAM_2			OMAP34XX_SDRC_CS1

-/* SDRAM Bank Allocation method */
-#define SDRC_R_B_C			1
-
 /* NAND and environment organization  */
 #define PISMO1_NAND_SIZE		GPMC_SIZE_128M

@@ -317,6 +310,7 @@

 #define CONFIG_SPL_LIBCOMMON_SUPPORT
 #define CONFIG_SPL_LIBDISK_SUPPORT
+#define CONFIG_SPL_BOARD_INIT
 #define CONFIG_SPL_I2C_SUPPORT
 #define CONFIG_SPL_LIBGENERIC_SUPPORT
 #define CONFIG_SPL_SERIAL_SUPPORT
@@ -359,7 +353,7 @@
 #define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
 #define CONFIG_SYS_NAND_U_BOOT_SIZE	0x200000

-#define CONFIG_SYS_SPL_MALLOC_START	0x80108000
+#define CONFIG_SYS_SPL_MALLOC_START	0x80208000
 #define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000	/* 1 MB */

 #endif /* __CONFIG_H */
--- a/include/configs/dig297.h
+++ b/include/configs/dig297.h
@@ -45,7 +45,6 @@
 */
 #define CONFIG_OMAP		/* in a TI OMAP core */
 #define CONFIG_OMAP34XX		/* which is a 34XX */
-#define CONFIG_OMAP3430		/* which is in a 3430 */

 #define CONFIG_SYS_TEXT_BASE	0x80008000

@@ -282,9 +281,6 @@
 #define PHYS_SDRAM_1_SIZE	(32 << 20)	/* at least 32 MiB */
 #define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1

-/* SDRAM Bank Allocation method */
-#define SDRC_R_B_C		1
-
 /*-----------------------------------------------------------------------
 * FLASH and environment organization
 */
--- a/include/configs/efikamx.h
+++ b/include/configs/efikamx.h
@@ -85,7 +85,7 @@
 * Hardware drivers
 */
 #define CONFIG_MXC_UART
-#define CONFIG_SYS_MX51_UART1
+#define CONFIG_MXC_UART_BASE		UART1_BASE
 #define CONFIG_CONS_INDEX		1
 #define CONFIG_BAUDRATE			115200
 #define CONFIG_SYS_BAUDRATE_TABLE	{9600, 19200, 38400, 57600, 115200}
--- a/include/configs/enbw_cmc.h
+++ b/include/configs/enbw_cmc.h
@@ -0,0 +1,451 @@
+/*
+ * (C) Copyright 2011
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Based on davinci_dvevm.h. Original Copyrights follow:
+ *
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * Board
+ */
+#define CONFIG_DRIVER_TI_EMAC
+#define CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT 7
+#define CONFIG_USE_NAND
+
+/*
+ * SoC Configuration
+ */
+#define CONFIG_ARM926EJS		/* arm926ejs CPU core */
+#define CONFIG_SOC_DA8XX		/* TI DA8xx SoC */
+#define CONFIG_SOC_DA850		/* TI DA850 SoC */
+#define CONFIG_SYS_CLK_FREQ		clk_get(DAVINCI_ARM_CLKID)
+#define CONFIG_SYS_OSCIN_FREQ		24000000
+#define CONFIG_SYS_TIMERBASE		DAVINCI_TIMER0_BASE
+#define CONFIG_SYS_HZ_CLOCK		clk_get(DAVINCI_AUXCLK_CLKID)
+#define CONFIG_SYS_HZ			1000
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_DA850_LOWLEVEL
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_DA8XX_GPIO
+#define CONFIG_HOSTNAME		enbw_cmc
+#define CONFIG_DISPLAY_CPUINFO
+
+#define MACH_TYPE_ENBW_CMC	3585
+#define CONFIG_MACH_TYPE	MACH_TYPE_ENBW_CMC
+
+/*
+ * Memory Info
+ */
+#define CONFIG_SYS_MALLOC_LEN	(0x10000 + 1*1024*1024) /* malloc() len */
+#define PHYS_SDRAM_1		DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
+#define PHYS_SDRAM_1_SIZE	(64 << 20) /* SDRAM size 64MB */
+#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
+
+/* memtest start addr */
+#define CONFIG_SYS_MEMTEST_START	(PHYS_SDRAM_1 + 0x2000000)
+
+/* memtest will be run on 16MB */
+#define CONFIG_SYS_MEMTEST_END	(PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)
+
+#define CONFIG_NR_DRAM_BANKS	1 /* we have 1 bank of DRAM */
+#define CONFIG_STACKSIZE	(256*1024) /* regular stack */
+
+/*
+ * Serial Driver info
+ */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	-4	/* NS16550 register size */
+#define CONFIG_SYS_NS16550_COM1	DAVINCI_UART2_BASE /* Base address of UART2 */
+#define CONFIG_SYS_NS16550_CLK	clk_get(DAVINCI_UART2_CLKID)
+#define CONFIG_CONS_INDEX	1		/* use UART0 for console */
+#define CONFIG_BAUDRATE		115200		/* Default baud rate */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_DA850_LPSC_UART	DAVINCI_LPSC_UART2
+/*
+ * I2C Configuration
+ */
+#define CONFIG_HARD_I2C
+#define CONFIG_DRIVER_DAVINCI_I2C
+#define CONFIG_SYS_I2C_SPEED		80000
+#define CONFIG_SYS_I2C_SLAVE		10 /* Bogus, master-only in U-Boot */
+#define CONFIG_SYS_I2C_EXPANDER_ADDR   0x20
+#define CONFIG_CMD_I2C
+
+#define CONFIG_CMD_DTT
+#define CONFIG_DTT_LM75
+#define CONFIG_DTT_SENSORS	{0}	/* Sensor addresses		*/
+#define CONFIG_SYS_DTT_MAX_TEMP	70
+#define CONFIG_SYS_DTT_LOW_TEMP	-30
+#define CONFIG_SYS_DTT_HYSTERESIS	3
+
+/*
+ * Flash & Environment
+ */
+#ifdef CONFIG_USE_NAND
+#define CONFIG_NAND_DAVINCI
+#define CONFIG_SYS_NAND_USE_FLASH_BBT
+#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
+#define CONFIG_SYS_NAND_PAGE_2K
+#define CONFIG_SYS_NAND_CS		3
+#define CONFIG_SYS_NAND_BASE		DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
+#define CONFIG_SYS_CLE_MASK		0x10
+#define CONFIG_SYS_ALE_MASK		0x8
+#undef CONFIG_SYS_NAND_HW_ECC
+#define CONFIG_SYS_MAX_NAND_DEVICE	1 /* Max number of NAND devices */
+#define NAND_MAX_CHIPS			1
+
+#define MTDIDS_DEFAULT		"nor0=physmap-flash.0,nand0=davinci_nand.1"
+#define MTDPARTS_DEFAULT			\
+	"mtdparts="				\
+		"physmap-flash.0:"		\
+			"512k(U-Boot),"		\
+			"64k(env1),"		\
+			"64k(env2),"		\
+			"-(rest);"		\
+		"davinci_nand.1:"		\
+			"128k(dtb),"		\
+			"3m(kernel),"		\
+			"4m(rootfs),"		\
+			"-(userfs)"
+
+
+#define CONFIG_CMD_MTDPARTS
+
+#endif
+
+/*
+ * Network & Ethernet Configuration
+ */
+#ifdef CONFIG_DRIVER_TI_EMAC
+#define CONFIG_MII
+#define CONFIG_BOOTP_DEFAULT
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_NET_RETRY_COUNT	10
+#define CONFIG_NET_MULTI
+#endif
+
+/*
+ * Flash configuration
+ */
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_MTD
+#define CONFIG_SYS_FLASH_BASE           0x60000000
+#define CONFIG_SYS_FLASH_SIZE           0x01000000
+#define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max num of memory banks */
+#define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
+#define CONFIG_SYS_MAX_FLASH_SECT       128
+#define CONFIG_FLASH_16BIT              /* Flash is 16-bit */
+
+#define CONFIG_CMD_FLASH
+
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_SYS_MONITOR_LEN	0x80000
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + \
+					CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_SECT_SIZE	(64 << 10)
+#define CONFIG_ENV_SIZE		(16 << 10)	/* 16 KiB */
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + \
+					CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND		(CONFIG_ENV_SIZE)
+#undef CONFIG_ENV_IS_IN_NAND
+#define CONFIG_DEFAULT_SETTINGS_ADDR	(CONFIG_ENV_ADDR_REDUND + \
+						CONFIG_ENV_SECT_SIZE)
+
+#define xstr(s)	str(s)
+#define str(s)	#s
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"u-boot_addr_r=c0000000\0"					\
+	"u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.bin\0"			\
+	"load=tftp ${u-boot_addr_r} ${u-boot}\0"			\
+	"update=protect off " xstr(CONFIG_SYS_FLASH_BASE) " +${filesize};"\
+		"erase " xstr(CONFIG_SYS_FLASH_BASE) " +${filesize};"	\
+		"cp.b ${u-boot_addr_r} " xstr(CONFIG_SYS_FLASH_BASE)	\
+		" ${filesize};"						\
+		"protect on " xstr(CONFIG_SYS_FLASH_BASE) " +${filesize}\0"\
+	"netdev=eth0\0"							\
+	"rootpath=/opt/eldk-arm/arm\0"					\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"kernel_addr_r=c0700000\0"					\
+	"fdt_addr_r=c0600000\0"						\
+	"ramdisk_addr_r=c0b00000\0"					\
+	"fdt_file=" xstr(CONFIG_HOSTNAME) "/"				\
+		xstr(CONFIG_HOSTNAME) ".dtb\0"				\
+	"kernel_file=" xstr(CONFIG_HOSTNAME) "/uImage \0"		\
+	"nand_ld_ramdsk=nand read ${ramdisk_addr_r} 320000 400000\0"	\
+	"nand_ld_kernel=nand read ${kernel_addr_r} 20000 300000\0"	\
+	"nand_ld_fdt=nand read ${fdt_addr_r} 0 2000\0"			\
+	"load_kernel=tftp ${kernel_addr_r} ${kernel_file}\0"		\
+	"load_fdt=tftp ${fdt_addr_r} ${fdt_file}\0"			\
+	"load_nand=run nand_ld_ramdsk nand_ld_kernel nand_ld_fdt\0"	\
+	"addcon=setenv bootargs ${bootargs} console=ttyS2,"		\
+		"${baudrate}n8\0"					\
+	"net_nfs=run load_fdt load_kernel; "				\
+		"run nfsargs addip addcon addmtd addmisc;"		\
+		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"		\
+	"nand_selfnand=run load_nand ramargs addip addcon addmisc;bootm "\
+		"${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"	\
+	"bootcmd=run net_nfs\0"						\
+	"machid=e01\0"							\
+	"key_cmd_0=echo key:   0\0"					\
+	"key_cmd_1=echo key:   1\0"					\
+	"key_cmd_2=echo key:   2\0"					\
+	"key_cmd_3=echo key:   3\0"					\
+	"key_magic_0=0\0"						\
+	"key_magic_1=1\0"						\
+	"key_magic_2=2\0"						\
+	"key_magic_3=3\0"						\
+	"magic_keys=0123\0"						\
+	"hwconfig=switch:lan=on,pwl=off\0"				\
+	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
+	"addmisc=setenv bootargs ${bootargs} davinci_mmc.use_dma=0\0"	\
+	"mtdids=" MTDIDS_DEFAULT "\0"					\
+	"mtdparts=" MTDPARTS_DEFAULT "\0"				\
+	"logversion=2\0"						\
+	"\0"
+
+/*
+ * U-Boot general configuration
+ */
+#define CONFIG_BOOTFILE		"uImage" /* Boot file name */
+#define CONFIG_SYS_PROMPT	"=> " /* Command Prompt */
+#define CONFIG_SYS_CBSIZE	1024 /* Console I/O Buffer Size	*/
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS	16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
+#define CONFIG_SYS_LOAD_ADDR	(PHYS_SDRAM_1 + 0x700000)
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CRC32_VERIFY
+#define CONFIG_MX_CYCLIC
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_HWCONFIG
+#define CONFIG_SHOW_BOOT_PROGRESS
+#define CONFIG_BOARD_LATE_INIT
+
+/*
+ * U-Boot commands
+ */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_CACHE
+
+#ifndef CONFIG_DRIVER_TI_EMAC
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_DHCP
+#undef CONFIG_CMD_MII
+#undef CONFIG_CMD_PING
+#endif
+
+#ifdef CONFIG_USE_NAND
+#undef CONFIG_CMD_IMLS
+#define CONFIG_CMD_NAND
+
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_LZO
+#define CONFIG_RBTREE
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#endif
+
+#if !defined(CONFIG_USE_NAND) && \
+	!defined(CONFIG_USE_NOR) && \
+	!defined(CONFIG_USE_SPIFLASH)
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_ENV_SIZE		(16 << 10)
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_ENV
+#endif
+
+#define CONFIG_SYS_TEXT_BASE		0x60000000
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_SDRAM_BASE		0xc0000000
+#define CONFIG_SYS_INIT_SP_ADDR		(0x8001ff00)
+
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_PREBOOT	"echo;" \
+	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
+	"echo"
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_CMC_RESET_PIN	0x04000000
+#define CONFIG_CMC_RESET_TIMEOUT	3
+
+#define CONFIG_HW_WATCHDOG
+#define CONFIG_SYS_WDTTIMERBASE		DAVINCI_TIMER1_BASE
+#define CONFIG_SYS_WDT_PERIOD_LOW	0x0c000000
+#define CONFIG_SYS_WDT_PERIOD_HIGH	0x0
+
+#define CONFIG_CMD_DATE
+#define CONFIG_RTC_DAVINCI
+
+/* SD/MMC */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_DAVINCI_MMC
+#define CONFIG_MMC_MBLOCK
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_MMC
+
+
+/* FDT support */
+#define CONFIG_OF_LIBFDT
+
+/* LowLevel Init */
+/* PLL */
+#define CONFIG_SYS_DV_CLKMODE		0
+#define CONFIG_SYS_DA850_PLL0_POSTDIV	0
+#define CONFIG_SYS_DA850_PLL0_PLLDIV1	0x8000
+#define CONFIG_SYS_DA850_PLL0_PLLDIV2	0x8001
+#define CONFIG_SYS_DA850_PLL0_PLLDIV3	0x8002 /* 150MHz */
+#define CONFIG_SYS_DA850_PLL0_PLLDIV4	0x8003
+#define CONFIG_SYS_DA850_PLL0_PLLDIV5	0x8002
+#define CONFIG_SYS_DA850_PLL0_PLLDIV6	CONFIG_SYS_DA850_PLL0_PLLDIV1
+#define CONFIG_SYS_DA850_PLL0_PLLDIV7	0x8005
+
+#define CONFIG_SYS_DA850_PLL1_POSTDIV	1
+#define CONFIG_SYS_DA850_PLL1_PLLDIV1	0x8000
+#define CONFIG_SYS_DA850_PLL1_PLLDIV2	0x8001
+#define CONFIG_SYS_DA850_PLL1_PLLDIV3	0x8002
+
+#define CONFIG_SYS_DA850_PLL0_PLLM	18	/* PLL0 -> 456 MHz */
+#define CONFIG_SYS_DA850_PLL1_PLLM	24	/* PLL1 -> 300 MHz */
+
+/* DDR RAM */
+#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
+			DV_DDR_PHY_EXT_STRBEN   | \
+			(0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT))
+
+#define CONFIG_SYS_DA850_DDR2_SDBCR (0 | \
+		  (0 << DV_DDR_SDCR_DDR2TERM1_SHIFT) | \
+		  (0 << DV_DDR_SDCR_MSDRAMEN_SHIFT) | \
+		  (1 << DV_DDR_SDCR_DDR2EN_SHIFT) | \
+		  (0x1 << DV_DDR_SDCR_DDREN_SHIFT)	| \
+		  (0x1 << DV_DDR_SDCR_SDRAMEN_SHIFT)	| \
+		  (0x1 << DV_DDR_SDCR_TIMUNLOCK_SHIFT)	| \
+		  (0x1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT)	| \
+		  (0x3 << DV_DDR_SDCR_CL_SHIFT)		| \
+		  (0x2 << DV_DDR_SDCR_IBANK_SHIFT)		| \
+		  (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
+
+#define CONFIG_SYS_DA850_DDR2_SDBCR2 4 /* 13 row address bits */
+
+/*
+ * freq = 150MHz -> t = 7ns
+ */
+#define CONFIG_SYS_DA850_DDR2_SDTIMR (0 | \
+		(0x0d << DV_DDR_SDTMR1_RFC_SHIFT)	| \
+		(1 << DV_DDR_SDTMR1_RP_SHIFT)		| \
+		(1 << DV_DDR_SDTMR1_RCD_SHIFT)		| \
+		(1 << DV_DDR_SDTMR1_WR_SHIFT)		| \
+		(5 << DV_DDR_SDTMR1_RAS_SHIFT)		| \
+		(7 << DV_DDR_SDTMR1_RC_SHIFT)		| \
+		(1 << DV_DDR_SDTMR1_RRD_SHIFT)		| \
+		(readl(&dv_ddr2_regs_ctrl->sdtimr) & 0x4) |  /* Reserved */ \
+		((2 - 1) << DV_DDR_SDTMR1_WTR_SHIFT))
+
+/*
+ * freq = 150MHz -> t=7ns
+ */
+#define CONFIG_SYS_DA850_DDR2_SDTIMR2 (0 | \
+	(readl(&dv_ddr2_regs_ctrl->sdtimr2) & 0x80000000) | /* Reserved */ \
+	(8 << DV_DDR_SDTMR2_RASMAX_SHIFT)		| \
+	(2 << DV_DDR_SDTMR2_XP_SHIFT)			| \
+	(0 << DV_DDR_SDTMR2_ODT_SHIFT)			| \
+	(15 << DV_DDR_SDTMR2_XSNR_SHIFT)		| \
+	(27 << DV_DDR_SDTMR2_XSRD_SHIFT)		| \
+	(0 << DV_DDR_SDTMR2_RTP_SHIFT)			| \
+	(2 << DV_DDR_SDTMR2_CKE_SHIFT))
+
+#define CONFIG_SYS_DA850_DDR2_SDRCR	0x00000407
+#define CONFIG_SYS_DA850_DDR2_PBBPR	0x30
+#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC (DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \
+					DAVINCI_SYSCFG_SUSPSRC_SPI1 | \
+					DAVINCI_SYSCFG_SUSPSRC_UART2 | \
+					DAVINCI_SYSCFG_SUSPSRC_EMAC |\
+					DAVINCI_SYSCFG_SUSPSRC_I2C)
+
+#define CONFIG_SYS_DA850_CS2CFG	(DAVINCI_ABCR_WSETUP(2)	| \
+				DAVINCI_ABCR_WSTROBE(6)	| \
+				DAVINCI_ABCR_WHOLD(1)	| \
+				DAVINCI_ABCR_RSETUP(2)	| \
+				DAVINCI_ABCR_RSTROBE(6)	| \
+				DAVINCI_ABCR_RHOLD(1)	| \
+				DAVINCI_ABCR_ASIZE_16BIT)
+
+#define CONFIG_SYS_DA850_CS3CFG	(DAVINCI_ABCR_WSETUP(1)	| \
+				DAVINCI_ABCR_WSTROBE(2)	| \
+				DAVINCI_ABCR_WHOLD(1)	| \
+				DAVINCI_ABCR_RSETUP(1)	| \
+				DAVINCI_ABCR_RSTROBE(6)	| \
+				DAVINCI_ABCR_RHOLD(1)	| \
+				DAVINCI_ABCR_ASIZE_8BIT)
+
+/*
+ * NOR Bootconfiguration word:
+ * Method: Direc boot
+ * EMIFA access mode: 16 Bit
+ */
+#define CONFIG_SYS_DV_NOR_BOOT_CFG	(0x11)
+
+#define CONFIG_POST	(CONFIG_SYS_POST_MEMORY)
+#define CONFIG_SYS_POST_WORD_ADDR 0x8001FFF0
+#define CONFIG_LOGBUFFER
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+
+#define CONFIG_BOOTCOUNT_LIMIT
+#define CONFIG_SYS_BOOTCOUNT_ADDR	DAVINCI_RTC_BASE
+
+#define CONFIG_SYS_NAND_U_BOOT_DST	0xc0080000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x60004000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	0x70000
+#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_NAND_U_BOOT_DST
+#endif /* __CONFIG_H */
--- a/include/configs/ethernut5.h
+++ b/include/configs/ethernut5.h
@@ -0,0 +1,287 @@
+/*
+ * (C) Copyright 2011
+ * egnite GmbH <info@egnite.de>
+ *
+ * Configuation settings for Ethernut 5 with AT91SAM9XE.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/hardware.h>
+
+/* The first stage boot loader expects u-boot running at this address. */
+#define CONFIG_SYS_TEXT_BASE	0x27000000	/* 16MB available */
+
+/* The first stage boot loader takes care of low level initialization. */
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/* Set our official architecture number. */
+#define MACH_TYPE_ETHERNUT5 1971
+#define CONFIG_MACH_TYPE MACH_TYPE_ETHERNUT5
+
+/* CPU information */
+#define CONFIG_ARM926EJS
+#define CONFIG_AT91FAMILY
+#define CONFIG_DISPLAY_CPUINFO		/* Display at console. */
+#define CONFIG_ARCH_CPU_INIT
+
+/* ARM asynchronous clock */
+#define CONFIG_SYS_AT91_SLOW_CLOCK	32768	/* slow clock xtal */
+#define CONFIG_SYS_AT91_MAIN_CLOCK	18432000 /* 18.432 MHz crystal */
+#define CONFIG_SYS_HZ			1000
+#undef CONFIG_USE_IRQ			/* Running w/o interrupts */
+
+/* 32kB internal SRAM */
+#define CONFIG_SRAM_BASE	0x00300000 /*AT91SAM9XE_SRAM_BASE */
+#define CONFIG_SRAM_SIZE	(32 << 10)
+#define CONFIG_STACKSIZE	(CONFIG_SRAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SRAM_BASE + CONFIG_STACKSIZE)
+
+/* 128MB SDRAM in 1 bank */
+#define CONFIG_NR_DRAM_BANKS		1
+#define CONFIG_SYS_SDRAM_BASE		0x20000000
+#define CONFIG_SYS_SDRAM_SIZE		(128 << 20)
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SDRAM_BASE
+#define CONFIG_LOADADDR			CONFIG_SYS_LOAD_ADDR
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (1 << 20))
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_TEXT_BASE \
+					- CONFIG_SYS_MALLOC_LEN)
+
+/* 512kB on-chip NOR flash */
+# define CONFIG_SYS_MAX_FLASH_BANKS	1
+# define CONFIG_SYS_FLASH_BASE		0x00200000 /* AT91SAM9XE_FLASH_BASE */
+# define CONFIG_AT91_EFLASH
+# define CONFIG_SYS_MAX_FLASH_SECT	32
+# define CONFIG_SYS_FLASH_PROTECTION	/* First stage loader in sector 0 */
+# define CONFIG_EFLASH_PROTSECTORS	1
+
+/* 512kB DataFlash at NPCS0 */
+#define CONFIG_SYS_MAX_DATAFLASH_BANKS	1
+#define CONFIG_HAS_DATAFLASH
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_ATMEL
+#define CONFIG_ATMEL_DATAFLASH_SPI
+#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0	0xC0000000
+#define DATAFLASH_TCSS			(0x1a << 16)
+#define DATAFLASH_TCHS			(0x1 << 24)
+
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_OFFSET		0x3DE000
+#define CONFIG_ENV_SECT_SIZE		(132 << 10)
+#define CONFIG_ENV_SIZE			CONFIG_ENV_SECT_SIZE
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 \
+					+ CONFIG_ENV_OFFSET)
+#define CONFIG_SYS_MONITOR_BASE		(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 \
+					+ 0x042000)
+
+/* SPI */
+#define CONFIG_ATMEL_SPI
+#define CONFIG_SYS_SPI_WRITE_TOUT	(5 * CONFIG_SYS_HZ)
+#define AT91_SPI_CLK			15000000
+
+/* Serial port */
+#define CONFIG_ATMEL_USART
+#define CONFIG_USART3			/* USART 3 is DBGU */
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{115200 , 19200, 38400, 57600, 9600 }
+#define CONFIG_USART_BASE		ATMEL_BASE_DBGU
+#define	CONFIG_USART_ID			ATMEL_ID_SYS
+
+/* Misc. hardware drivers */
+#define CONFIG_AT91_GPIO
+
+/* Command line configuration */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_LOADS
+
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_SPI
+
+#ifdef MINIMAL_LOADER
+#undef CONFIG_CMD_CONSOLE
+#undef CONFIG_CMD_EDITENV
+#undef CONFIG_CMD_IMI
+#undef CONFIG_CMD_ITEST
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_LOADB
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_NFS
+#undef CONFIG_CMD_SETGETDCR
+#undef CONFIG_CMD_XIMG
+#else
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_CDP
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DNS
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_RARP
+#define CONFIG_CMD_REISER
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SNTP
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_CMD_UNZIP
+#define CONFIG_CMD_USB
+#endif
+
+/* NAND flash */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		0x40000000
+#define CONFIG_SYS_NAND_DBW_8
+#define CONFIG_NAND_ATMEL
+/* our ALE is AD21 */
+#define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
+/* our CLE is AD22 */
+#define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
+#define CONFIG_SYS_NAND_ENABLE_PIN	AT91_PIO_PORTC, 14
+#endif
+
+/* JFFS2 */
+#ifdef CONFIG_CMD_JFFS2
+#define CONFIG_MTD_NAND_ECC_JFFS2
+#define CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_NAND
+#endif
+
+/* Ethernet */
+#define CONFIG_NET_MULTI
+#define CONFIG_NET_RETRY_COUNT		20
+#define CONFIG_MACB
+#define CONFIG_RMII
+#define CONFIG_PHY_ID			0
+#define CONFIG_MACB_SEARCH_PHY
+
+/* MMC */
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_GENERIC_ATMEL_MCI
+#define CONFIG_SYS_MMC_CD_PIN		AT91_PIO_PORTC, 8
+#endif
+
+/* USB */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_ATMEL
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_SYS_USB_OHCI_CPU_INIT
+#define CONFIG_SYS_USB_OHCI_REGS_BASE	0x00500000
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME	"host"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
+#define CONFIG_USB_STORAGE
+#endif
+
+/* RTC */
+#if defined(CONFIG_CMD_DATE) || defined(CONFIG_CMD_SNTP)
+#define CONFIG_RTC_PCF8563
+#define CONFIG_SYS_I2C_RTC_ADDR		0x51
+#endif
+
+/* I2C */
+#define CONFIG_SYS_MAX_I2C_BUS	1
+#define CONFIG_SYS_I2C_SLAVE	0
+#define CONFIG_SYS_I2C_SPEED	100000
+
+#define CONFIG_SOFT_I2C
+#define I2C_SOFT_DECLARATIONS
+
+#define GPIO_I2C_SCL		AT91_PIO_PORTA, 24
+#define GPIO_I2C_SDA		AT91_PIO_PORTA, 23
+
+#define I2C_INIT { \
+	at91_set_pio_periph(AT91_PIO_PORTA, 23, 0); \
+	at91_set_pio_multi_drive(AT91_PIO_PORTA, 23, 1); \
+	at91_set_pio_periph(AT91_PIO_PORTA, 24, 0); \
+	at91_set_pio_output(AT91_PIO_PORTA, 24, 0); \
+	at91_set_pio_multi_drive(AT91_PIO_PORTA, 24, 1); \
+}
+
+#define I2C_ACTIVE	at91_set_pio_output(AT91_PIO_PORTA, 23, 0)
+#define I2C_TRISTATE	at91_set_pio_input(AT91_PIO_PORTA, 23, 0)
+#define I2C_SCL(bit)	at91_set_pio_value(AT91_PIO_PORTA, 24, bit)
+#define I2C_SDA(bit)	at91_set_pio_value(AT91_PIO_PORTA, 23, bit)
+#define I2C_DELAY	udelay(100)
+#define I2C_READ	at91_get_pio_value(AT91_PIO_PORTA, 23)
+
+/* DHCP/BOOTP options */
+#ifdef CONFIG_CMD_DHCP
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_SYS_AUTOLOAD	"n"
+#endif
+
+/* File systems */
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#if defined(CONFIG_CMD_MTDPARTS) || defined(CONFIG_CMD_NAND)
+#define MTDIDS_DEFAULT		"nand0=atmel_nand"
+#define MTDPARTS_DEFAULT	"mtdparts=atmel_nand:-(root)"
+#endif
+#if defined(CONFIG_CMD_REISER) || defined(CONFIG_CMD_EXT2) || \
+	defined(CONFIG_CMD_USB) || defined(CONFIG_MMC)
+#define CONFIG_DOS_PARTITION
+#endif
+#define CONFIG_LZO
+#define CONFIG_RBTREE
+
+/* Boot command */
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_BOOTCOMMAND	"cp.b 0xC00C6000 ${loadaddr} 0x294000; bootm"
+#if defined(CONFIG_CMD_NAND)
+#define CONFIG_BOOTARGS		"console=ttyS0,115200 " \
+				"root=/dev/mtdblock0 " \
+				MTDPARTS_DEFAULT \
+				" rw rootfstype=jffs2"
+#endif
+
+/* Misc. u-boot settings */
+#define CONFIG_SYS_PROMPT		"U-Boot> "
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + 16 \
+					+ sizeof(CONFIG_SYS_PROMPT))
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING
+
+#endif
--- a/include/configs/flea3.h
+++ b/include/configs/flea3.h
@@ -77,7 +77,7 @@
 * UART (console)
 */
 #define CONFIG_MXC_UART
-#define CONFIG_SYS_MX35_UART3
+#define CONFIG_MXC_UART_BASE	UART3_BASE

 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
@@ -107,7 +107,7 @@

 #define CONFIG_BOOTDELAY	3

-#define CONFIG_LOADADDR		0x90800000	/* loadaddr env var */
+#define CONFIG_LOADADDR		0x80800000	/* loadaddr env var */


 /*
@@ -162,10 +162,10 @@
 * Physical Memory Map
 */
 #define CONFIG_NR_DRAM_BANKS	1
-#define PHYS_SDRAM_1		CSD1_BASE_ADDR
+#define PHYS_SDRAM_1		CSD0_BASE_ADDR
 #define PHYS_SDRAM_1_SIZE	(128 * 1024 * 1024)

-#define CONFIG_SYS_SDRAM_BASE		CSD1_BASE_ADDR
+#define CONFIG_SYS_SDRAM_BASE		CSD0_BASE_ADDR
 #define CONFIG_SYS_INIT_RAM_ADDR	(IRAM_BASE_ADDR + 0x10000)
 #define CONFIG_SYS_INIT_RAM_SIZE		(IRAM_SIZE / 2)
 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
@@ -181,10 +181,14 @@
 #define CONFIG_FLASH_CFI_MTD
 #define CONFIG_MTD_PARTITIONS
 #define MTDIDS_DEFAULT		"nand0=mxc_nand,nor0=physmap-flash.0"
-#define MTDPARTS_DEFAULT	"mtdparts=mxc_nand:196m(root1)," \
-				"196m(root2),-(user);"	\
+#define MTDPARTS_DEFAULT	"mtdparts=mxc_nand:50m(root1)," \
+				"32m(rootfb)," \
+				"64m(pcache)," \
+				"64m(app1)," \
+				"10m(app2),-(spool);" \
 				"physmap-flash.0:512k(u-boot),64k(env1)," \
 				"64k(env2),3776k(kernel1),3776k(kernel2)"
+
 /*
 * FLASH and environment organization
 */
@@ -249,10 +253,10 @@
 		"else run addip_sta;fi\0"	\
 	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
 	"addtty=setenv bootargs ${bootargs}"				\
-		" console=ttymxc0,${baudrate}\0"			\
+		" console=ttymxc2,${baudrate}\0"			\
 	"addmisc=setenv bootargs ${bootargs} ${misc}\0"			\
-	"loadaddr=90800000\0"						\
-	"kernel_addr_r=90800000\0"					\
+	"loadaddr=80800000\0"						\
+	"kernel_addr_r=80800000\0"					\
 	"hostname=" xstr(CONFIG_HOSTNAME) "\0"				\
 	"bootfile=" xstr(CONFIG_HOSTNAME) "/uImage\0"			\
 	"ramdisk_file=" xstr(CONFIG_HOSTNAME) "/uRamdisk\0"		\
--- a/include/configs/hawkboard.h
+++ b/include/configs/hawkboard.h
@@ -34,6 +34,7 @@
 #define CONFIG_MACH_DAVINCI_HAWK
 #define CONFIG_ARM926EJS		/* arm926ejs CPU core */
 #define CONFIG_SOC_DA8XX		/* TI DA8xx SoC */
+#define CONFIG_SOC_DA850		/* TI DA850 SoC */
 #define CONFIG_SYS_CLK_FREQ		clk_get(DAVINCI_ARM_CLKID)
 #define CONFIG_SYS_OSCIN_FREQ		24000000
 #define CONFIG_SYS_TIMERBASE		DAVINCI_TIMER0_BASE
--- a/include/configs/igep0020.h
+++ b/include/configs/igep0020.h
@@ -27,7 +27,6 @@
 */
 #define CONFIG_OMAP		1	/* in a TI OMAP core */
 #define CONFIG_OMAP34XX		1	/* which is a 34XX */
-#define CONFIG_OMAP3430		1	/* which is in a 3430 */
 #define CONFIG_OMAP3_IGEP0020	1	/* working with IGEP0020 */

 #define CONFIG_SDRC	/* The chip has SDRC controller */
@@ -238,9 +237,6 @@
 #define PHYS_SDRAM_1_SIZE	(32 << 20)	/* at least 32 meg */
 #define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1

-/* SDRAM Bank Allocation method */
-#define SDRC_R_B_C		1
-
 /*
 * FLASH and environment organization
 */
--- a/include/configs/igep0030.h
+++ b/include/configs/igep0030.h
@@ -27,7 +27,6 @@
 */
 #define CONFIG_OMAP		1	/* in a TI OMAP core */
 #define CONFIG_OMAP34XX		1	/* which is a 34XX */
-#define CONFIG_OMAP3430		1	/* which is in a 3430 */
 #define CONFIG_OMAP3_IGEP0030	1	/* working with IGEP0030 */

 #define CONFIG_SDRC	/* The chip has SDRC controller */
@@ -236,9 +235,6 @@
 #define PHYS_SDRAM_1_SIZE	(32 << 20)	/* at least 32 meg */
 #define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1

-/* SDRAM Bank Allocation method */
-#define SDRC_R_B_C		1
-
 /*
 * FLASH and environment organization
 */
--- a/include/configs/imx27lite-common.h
+++ b/include/configs/imx27lite-common.h
@@ -102,7 +102,7 @@
 * Serial Driver info
 */
 #define CONFIG_MXC_UART
-#define CONFIG_SYS_MX27_UART1
+#define CONFIG_MXC_UART_BASE	UART1_BASE
 #define CONFIG_CONS_INDEX	1		/* use UART0 for console */
 #define CONFIG_BAUDRATE		115200		/* Default baud rate */
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
--- a/include/configs/imx31_litekit.h
+++ b/include/configs/imx31_litekit.h
@@ -63,8 +63,8 @@
 * Hardware drivers
 */

-#define CONFIG_MXC_UART	1
-#define CONFIG_SYS_MX31_UART1		1
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE	UART1_BASE
 #define CONFIG_MXC_GPIO

 #define CONFIG_HARD_SPI		1
--- a/include/configs/imx31_phycore.h
+++ b/include/configs/imx31_phycore.h
@@ -59,7 +59,7 @@
 #define CONFIG_SYS_I2C_SLAVE		0xfe

 #define CONFIG_MXC_UART
-#define CONFIG_SYS_MX31_UART1
+#define CONFIG_MXC_UART_BASE		UART1_BASE

 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
--- a/include/configs/netspace_v2.h
+++ b/include/configs/netspace_v2.h
@@ -15,8 +15,8 @@
 * GNU General Public License for more details.
 */

-#ifndef _CONFIG_NETSPACE_V2_H
-#define _CONFIG_NETSPACE_V2_H
+#ifndef _CONFIG_LACIE_KW_H
+#define _CONFIG_LACIE_KW_H

 /*
 * Machine number definition
@@ -30,6 +30,9 @@
 #elif defined(CONFIG_NETSPACE_MAX_V2)
 #define CONFIG_MACH_TYPE		MACH_TYPE_NETSPACE_MAX_V2
 #define CONFIG_IDENT_STRING		" NS Max v2"
+#elif defined(CONFIG_NET2BIG_V2)
+#define CONFIG_MACH_TYPE		MACH_TYPE_NET2BIG_V2
+#define CONFIG_IDENT_STRING		" 2Big v2"
 #else
 #error "Unknown board"
 #endif
@@ -56,11 +59,19 @@
 #define CONFIG_CMD_USB

 /*
- * Core clock definition.
+ * Core clock definition
 */
 #define CONFIG_SYS_TCLK			166000000 /* 166MHz */

+/*
+ * SDRAM configuration
+ */
+#if defined(CONFIG_NET2BIG_V2)
+#define CONFIG_NR_DRAM_BANKS		2
+#else
 #define CONFIG_NR_DRAM_BANKS		1
+#endif
+
 #ifdef CONFIG_INETSPACE_V2
 /* Different SDRAM configuration and size for Internet Space v2 */
 #define CONFIG_SYS_KWD_CONFIG ($(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-is2.cfg)
@@ -81,12 +92,17 @@
 #define CONFIG_ENV_SPI_MAX_HZ           20000000 /* 20Mhz */
 #define CONFIG_SYS_IDE_MAXBUS           1
 #define CONFIG_SYS_IDE_MAXDEVICE        1
+#if defined(CONFIG_NET2BIG_V2)
+#define CONFIG_SYS_PROMPT		"2big2> "
+#else
 #define CONFIG_SYS_PROMPT		"ns2> "
+#endif

 /*
 * Ethernet Driver configuration
 */
 #ifdef CONFIG_CMD_NET
+#define CONFIG_MISC_INIT_R /* Call misc_init_r() to initialize MAC address */
 #define CONFIG_MVGBE_PORTS		{1, 0} /* enable port 0 only */
 #define CONFIG_NETCONSOLE
 #endif
@@ -96,11 +112,10 @@
 */
 #ifdef CONFIG_MVSATA_IDE
 #define CONFIG_SYS_ATA_IDE0_OFFSET      MV_SATA_PORT0_OFFSET
-/* Network Space Max v2 use 2 SATA ports */
-#ifdef CONFIG_NETSPACE_MAX_V2
+#if defined(CONFIG_NETSPACE_MAX_V2) || defined(CONFIG_NET2BIG_V2)
 #define CONFIG_SYS_ATA_IDE1_OFFSET      MV_SATA_PORT1_OFFSET
 #endif
-#endif
+#endif /* CONFIG_MVSATA_IDE */

 /*
 * Enable GPI0 support
@@ -175,4 +190,4 @@
 	"usbload=usb start && "					\
 		"fatload usb 0:1 $loadaddr /boot/$bootfile\0"

-#endif /* _CONFIG_NETSPACE_V2_H */
+#endif /* _CONFIG_LACIE_KW_H */
--- a/include/configs/lubbock.h
+++ b/include/configs/lubbock.h
@@ -34,7 +34,7 @@
 * High Level Configuration Options
 * (easy to change)
 */
-#define CONFIG_PXA250		1	/* This is an PXA250 CPU    */
+#define CONFIG_CPU_PXA25X		1	/* This is an PXA250 CPU    */
 #define CONFIG_LUBBOCK		1	/* on an LUBBOCK Board	    */
 #define CONFIG_LCD		1
 #ifdef CONFIG_LCD
@@ -175,7 +175,7 @@
 #define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1

 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
-#define	CONFIG_SYS_INIT_SP_ADDR		(GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
+#define	CONFIG_SYS_INIT_SP_ADDR		0xfffff800

 #define FPGA_REGS_BASE_PHYSICAL 0x08000000

--- a/include/configs/mx25pdk.h
+++ b/include/configs/mx25pdk.h
@@ -54,7 +54,7 @@

 /* Serial Info */
 #define CONFIG_MXC_UART
-#define CONFIG_SYS_MX25_UART1
+#define CONFIG_MXC_UART_BASE	UART1_BASE
 #define CONFIG_CONS_INDEX	1	/* use UART0 for console */
 #define CONFIG_BAUDRATE		115200	/* Default baud rate */
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
--- a/include/configs/mx31ads.h
+++ b/include/configs/mx31ads.h
@@ -60,8 +60,8 @@
 * Hardware drivers
 */

-#define CONFIG_MXC_UART	1
-#define CONFIG_SYS_MX31_UART1		1
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE	UART1_BASE

 #define CONFIG_HARD_SPI		1
 #define CONFIG_MXC_SPI		1
--- a/include/configs/mx31pdk.h
+++ b/include/configs/mx31pdk.h
@@ -61,7 +61,7 @@
 */

 #define CONFIG_MXC_UART
-#define CONFIG_SYS_MX31_UART1
+#define CONFIG_MXC_UART_BASE	UART1_BASE
 #define CONFIG_HW_WATCHDOG
 #define CONFIG_MXC_GPIO

--- a/include/configs/mx35pdk.h
+++ b/include/configs/mx35pdk.h
@@ -85,7 +85,7 @@
 * UART (console)
 */
 #define CONFIG_MXC_UART
-#define CONFIG_SYS_MX35_UART1
+#define CONFIG_MXC_UART_BASE	UART1_BASE

 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
--- a/include/configs/mx51evk.h
+++ b/include/configs/mx51evk.h
@@ -59,7 +59,7 @@
 * Hardware drivers
 */
 #define CONFIG_MXC_UART
-#define CONFIG_SYS_MX51_UART1
+#define CONFIG_MXC_UART_BASE	UART1_BASE
 #define CONFIG_MXC_GPIO

 /*
--- a/include/configs/mx53ard.h
+++ b/include/configs/mx53ard.h
@@ -44,7 +44,7 @@
 #define CONFIG_MXC_GPIO

 #define CONFIG_MXC_UART
-#define CONFIG_SYS_MX53_UART1
+#define CONFIG_MXC_UART_BASE	UART1_BASE

 /* I2C Configs */
 #define CONFIG_CMD_I2C
--- a/include/configs/mx53evk.h
+++ b/include/configs/mx53evk.h
@@ -47,7 +47,7 @@
 #define CONFIG_MXC_GPIO

 #define CONFIG_MXC_UART
-#define CONFIG_SYS_MX53_UART1
+#define CONFIG_MXC_UART_BASE	UART1_BASE

 /* I2C Configs */
 #define CONFIG_CMD_I2C
--- a/include/configs/mx53loco.h
+++ b/include/configs/mx53loco.h
@@ -45,7 +45,7 @@
 #define CONFIG_MXC_GPIO

 #define CONFIG_MXC_UART
-#define CONFIG_SYS_MX53_UART1
+#define CONFIG_MXC_UART_BASE	UART1_BASE

 /* MMC Configs */
 #define CONFIG_FSL_ESDHC
--- a/include/configs/mx53smd.h
+++ b/include/configs/mx53smd.h
@@ -44,7 +44,7 @@
 #define CONFIG_MXC_GPIO

 #define CONFIG_MXC_UART
-#define CONFIG_SYS_MX53_UART1
+#define CONFIG_MXC_UART_BASE	UART1_BASE

 /* I2C Configs */
 #define CONFIG_CMD_I2C
--- a/include/configs/omap3_beagle.h
+++ b/include/configs/omap3_beagle.h
@@ -33,7 +33,6 @@
 */
 #define CONFIG_OMAP		1	/* in a TI OMAP core */
 #define CONFIG_OMAP34XX		1	/* which is a 34XX */
-#define CONFIG_OMAP3430		1	/* which is in a 3430 */
 #define CONFIG_OMAP3_BEAGLE	1	/* working with BEAGLE */

 #define CONFIG_SDRC	/* The chip has SDRC controller */
@@ -111,9 +110,6 @@
 #define STATUS_LED_BOOT			STATUS_LED_BIT
 #define STATUS_LED_GREEN		STATUS_LED_BIT1

-/* DDR - I use Micron DDR */
-#define CONFIG_OMAP3_MICRON_DDR		1
-
 /* Enable Multi Bus support for I2C */
 #define CONFIG_I2C_MULTI_BUS		1

@@ -215,7 +211,7 @@
 	"rdaddr=0x81000000\0" \
 	"usbtty=cdc_acm\0" \
 	"bootfile=uImage.beagle\0" \
-	"console=tty02,115200n8\0" \
+	"console=ttyO2,115200n8\0" \
 	"mpurate=auto\0" \
 	"buddy=none "\
 	"optargs=\0" \
@@ -337,22 +333,14 @@
 * The stack sizes are set up in start.S using the settings below
 */
 #define CONFIG_STACKSIZE	(128 << 10)	/* regular stack 128 KiB */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ	(4 << 10)	/* IRQ stack 4 KiB */
-#define CONFIG_STACKSIZE_FIQ	(4 << 10)	/* FIQ stack 4 KiB */
-#endif

 /*-----------------------------------------------------------------------
 * Physical Memory Map
 */
 #define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
 #define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
-#define PHYS_SDRAM_1_SIZE	(32 << 20)	/* at least 32 MiB */
 #define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1

-/* SDRAM Bank Allocation method */
-#define SDRC_R_B_C		1
-
 /*-----------------------------------------------------------------------
 * FLASH and environment organization
 */
@@ -390,4 +378,61 @@

 #define CONFIG_OMAP3_SPI

+#define CONFIG_SYS_CACHELINE_SIZE	64
+
+/* Defines for SPL */
+#define CONFIG_SPL
+#define CONFIG_SPL_NAND_SIMPLE
+#define CONFIG_SPL_TEXT_BASE		0x40200800
+#define CONFIG_SPL_MAX_SIZE		(45 * 1024)
+#define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK
+
+#define CONFIG_SPL_BSS_START_ADDR	0x80000000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x80000		/* 512 KB */
+
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /* address 0x60000 */
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x200 /* 256 KB */
+#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION	1
+#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME	"u-boot.img"
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBDISK_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_FAT_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_POWER_SUPPORT
+#define CONFIG_SPL_OMAP3_ID_NAND
+#define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/omap-common/u-boot-spl.lds"
+
+/* NAND boot config */
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_COUNT	64
+#define CONFIG_SYS_NAND_PAGE_SIZE	2048
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
+#define CONFIG_SYS_NAND_ECCPOS		{2, 3, 4, 5, 6, 7, 8, 9,\
+						10, 11, 12, 13}
+#define CONFIG_SYS_NAND_ECCSIZE		512
+#define CONFIG_SYS_NAND_ECCBYTES	3
+#define CONFIG_SYS_NAND_ECCSTEPS	(CONFIG_SYS_NAND_PAGE_SIZE / \
+						CONFIG_SYS_NAND_ECCSIZE)
+#define CONFIG_SYS_NAND_ECCTOTAL	(CONFIG_SYS_NAND_ECCBYTES * \
+						CONFIG_SYS_NAND_ECCSTEPS)
+#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
+
+/*
+ * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
+ * 64 bytes before this address should be set aside for u-boot.img's
+ * header. That is 0x800FFFC0--0x80100000 should not be used for any
+ * other needs.
+ */
+#define CONFIG_SYS_TEXT_BASE		0x80100000
+#define CONFIG_SYS_SPL_MALLOC_START	0x80208000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
+
 #endif /* __CONFIG_H */
--- a/include/configs/omap3_evm.h
+++ b/include/configs/omap3_evm.h
@@ -83,6 +83,20 @@
 #define CONFIG_MMC
 #define CONFIG_GENERIC_MMC
 #define CONFIG_OMAP_HSMMC
+
+/* SPL */
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_FAT_SUPPORT
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /* address 0x60000 */
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x200 /* 256 KB */
+#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION	1
+#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME	"u-boot.img"
+
+/* Partition tables */
+/* Only need DOS partition support for SPL, currently */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_EFI_PARTITION
+#endif
 #define CONFIG_DOS_PARTITION

 /* USB
@@ -94,6 +108,26 @@
 #define CONFIG_MUSB_HCD
 /* #define CONFIG_MUSB_UDC */

+/* NAND SPL */
+#define CONFIG_SPL_NAND_SIMPLE
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_COUNT	64
+#define CONFIG_SYS_NAND_PAGE_SIZE	2048
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
+#define CONFIG_SYS_NAND_ECCPOS		{2, 3, 4, 5, 6, 7, 8, 9,\
+						10, 11, 12, 13}
+#define CONFIG_SYS_NAND_ECCSIZE		512
+#define CONFIG_SYS_NAND_ECCBYTES	3
+#define CONFIG_SYS_NAND_ECCSTEPS	(CONFIG_SYS_NAND_PAGE_SIZE / \
+						CONFIG_SYS_NAND_ECCSIZE)
+#define CONFIG_SYS_NAND_ECCTOTAL       (CONFIG_SYS_NAND_ECCBYTES * \
+						CONFIG_SYS_NAND_ECCSTEPS)
+#define CONFIG_SYS_NAND_U_BOOT_START   CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
+
 /* -----------------------------------------------------------------------------
 * Include common board configuration
 * -----------------------------------------------------------------------------
--- a/include/configs/omap3_evm_common.h
+++ b/include/configs/omap3_evm_common.h
@@ -22,12 +22,10 @@
 */
 #define CONFIG_OMAP			/* This is TI OMAP core */
 #define CONFIG_OMAP34XX			/* belonging to 34XX family */
-#define CONFIG_OMAP3430			/* which is in a 3430 */

 #define CONFIG_SDRC			/* The chip has SDRC controller */

 #define CONFIG_OMAP3_EVM		/* This is a OMAP3 EVM */
-#define CONFIG_OMAP3_MICRON_DDR		/* with MICRON DDR part */
 #define CONFIG_TWL4030_POWER		/* with TWL4030 PMIC */

 #undef CONFIG_USE_IRQ			/* no support for IRQs */
@@ -59,11 +57,6 @@
 */
 #define CONFIG_STACKSIZE	(128 << 10)	/* regular stack 128 KiB */

-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ	(4 << 10)	/* IRQ stack 4 KiB */
-#define CONFIG_STACKSIZE_FIQ	(4 << 10)	/* FIQ stack 4 KiB */
-#endif
-
 /*
 * Physical Memory Map
 * Note 1: CS1 may or may not be populated
@@ -71,12 +64,8 @@
 */
 #define CONFIG_NR_DRAM_BANKS		2
 #define PHYS_SDRAM_1			OMAP34XX_SDRC_CS0
-#define PHYS_SDRAM_1_SIZE		(32 << 20)
 #define PHYS_SDRAM_2			OMAP34XX_SDRC_CS1

-/* SDRAM Bank Allocation method */
-#define SDRC_R_B_C
-
 /* Limits for memtest */
 #define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)
 #define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
@@ -289,4 +278,34 @@
 /* Uncomment to define the board revision statically */
 /* #define CONFIG_STATIC_BOARD_REV	OMAP3EVM_BOARD_GEN_2 */

+#define CONFIG_SYS_CACHELINE_SIZE	64
+
+/* Defines for SPL */
+#define CONFIG_SPL
+#define CONFIG_SPL_TEXT_BASE		0x40200800
+#define CONFIG_SPL_MAX_SIZE		(45 * 1024)	/* 45 KB */
+#define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK
+
+#define CONFIG_SPL_BSS_START_ADDR	0x80000000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x80000		/* 512 KB */
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBDISK_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_POWER_SUPPORT
+#define CONFIG_SPL_OMAP3_ID_NAND
+#define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/omap-common/u-boot-spl.lds"
+
+/*
+ * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
+ * 64 bytes before this address should be set aside for u-boot.img's
+ * header. That is 0x800FFFC0--0x80100000 should not be used for any
+ * other needs.
+ */
+#define CONFIG_SYS_TEXT_BASE		0x80100000
+#define CONFIG_SYS_SPL_MALLOC_START	0x80208000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
+
 #endif /* __OMAP3_EVM_COMMON_H */
--- a/include/configs/omap3_evm_quick_mmc.h
+++ b/include/configs/omap3_evm_quick_mmc.h
@@ -88,4 +88,14 @@
 	"root=/dev/mmcblk0p2 rw "	\
 	"rootfstype=ext3 rootwait"

+/*
+ * SPL
+ */
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_FAT_SUPPORT
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /* address 0x60000 */
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x200 /* 256 KB */
+#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION	1
+#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME	"u-boot.img"
+
 #endif /* __OMAP3_EVM_QUICK_MMC_H */
--- a/include/configs/omap3_evm_quick_nand.h
+++ b/include/configs/omap3_evm_quick_nand.h
@@ -76,4 +76,26 @@
 	"root=/dev/mtdblock4 rw "	\
 	"rootfstype=jffs2 "

+/*
+ * SPL
+ */
+#define CONFIG_SPL_NAND_SIMPLE
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_COUNT	64
+#define CONFIG_SYS_NAND_PAGE_SIZE	2048
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
+#define CONFIG_SYS_NAND_ECCPOS		{2, 3, 4, 5, 6, 7, 8, 9,\
+						10, 11, 12, 13}
+#define CONFIG_SYS_NAND_ECCSIZE		512
+#define CONFIG_SYS_NAND_ECCBYTES	3
+#define CONFIG_SYS_NAND_ECCSTEPS	(CONFIG_SYS_NAND_PAGE_SIZE / \
+						CONFIG_SYS_NAND_ECCSIZE)
+#define CONFIG_SYS_NAND_ECCTOTAL       (CONFIG_SYS_NAND_ECCBYTES * \
+						CONFIG_SYS_NAND_ECCSTEPS)
+#define CONFIG_SYS_NAND_U_BOOT_START   CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
+
 #endif /* __OMAP3_EVM_QUICK_NAND_H */
--- a/include/configs/omap3_mvblx.h
+++ b/include/configs/omap3_mvblx.h
@@ -37,7 +37,6 @@
 #define CONFIG_ARMV7		1	/* This is an ARM V7 CPU core */
 #define CONFIG_OMAP		1	/* in a TI OMAP core */
 #define CONFIG_OMAP34XX		1	/* which is a 34XX */
-#define CONFIG_OMAP3430		1	/* which is in a 3430 */
 #define CONFIG_MVBLX		1	/* working with mvBlueLYNX-X */
 #define CONFIG_MACH_TYPE	MACH_TYPE_MVBLX

@@ -257,10 +256,6 @@
 * The stack sizes are set up in start.S using the settings below
 */
 #define CONFIG_STACKSIZE	(128 << 10)	/* regular stack 128 KiB */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ	(4 << 10)	/* IRQ stack 4 KiB */
-#define CONFIG_STACKSIZE_FIQ	(4 << 10)	/* FIQ stack 4 KiB */
-#endif

 /*-----------------------------------------------------------------------
 * Physical Memory Map
@@ -270,9 +265,6 @@
 #define PHYS_SDRAM_1_SIZE	(32 << 20)	/* at least 32 MiB */
 #define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1

-/* SDRAM Bank Allocation method */
-#define SDRC_R_B_C		1
-
 #define CONFIG_ENV_IS_NOWHERE	1

 /*----------------------------------------------------------------------------
@@ -310,4 +302,6 @@

 #define CONFIG_OMAP3_SPI

+#define CONFIG_SYS_CACHELINE_SIZE	64
+
 #endif /* __CONFIG_H */
--- a/include/configs/omap3_overo.h
+++ b/include/configs/omap3_overo.h
@@ -25,7 +25,6 @@
 */
 #define CONFIG_OMAP		1	/* in a TI OMAP core */
 #define CONFIG_OMAP34XX		1	/* which is a 34XX */
-#define CONFIG_OMAP3430		1	/* which is in a 3430 */
 #define CONFIG_OMAP3_OVERO	1	/* working with overo */

 #define CONFIG_SDRC	/* The chip has SDRC controller */
@@ -244,10 +243,6 @@
 * The stack sizes are set up in start.S using the settings below
 */
 #define CONFIG_STACKSIZE	(128 << 10)	/* regular stack 128 KiB */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ	(4 << 10)	/* IRQ stack 4 KiB */
-#define CONFIG_STACKSIZE_FIQ	(4 << 10)	/* FIQ stack 4 KiB */
-#endif

 /*-----------------------------------------------------------------------
 * Physical Memory Map
@@ -257,9 +252,6 @@
 #define PHYS_SDRAM_1_SIZE	(32 << 20)	/* at least 32 MiB */
 #define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1

-/* SDRAM Bank Allocation method */
-#define SDRC_R_B_C		1
-
 /*-----------------------------------------------------------------------
 * FLASH and environment organization
 */
@@ -307,4 +299,6 @@
 					 CONFIG_SYS_INIT_RAM_SIZE - \
 					 GENERATED_GBL_DATA_SIZE)

+#define CONFIG_SYS_CACHELINE_SIZE	64
+
 #endif				/* __CONFIG_H */
--- a/include/configs/omap3_pandora.h
+++ b/include/configs/omap3_pandora.h
@@ -28,7 +28,6 @@
 */
 #define CONFIG_OMAP		1	/* in a TI OMAP core */
 #define CONFIG_OMAP34XX		1	/* which is a 34XX */
-#define CONFIG_OMAP3430		1	/* which is in a 3430 */
 #define CONFIG_OMAP3_PANDORA	1	/* working with pandora */

 #define CONFIG_SDRC	/* The chip has SDRC controller */
@@ -228,10 +227,6 @@
 * The stack sizes are set up in start.S using the settings below
 */
 #define CONFIG_STACKSIZE	(128 << 10)	/* regular stack 128 KiB */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ	(4 << 10)	/* IRQ stack 4 KiB */
-#define CONFIG_STACKSIZE_FIQ	(4 << 10)	/* FIQ stack 4 KiB */
-#endif

 /*-----------------------------------------------------------------------
 * Physical Memory Map
@@ -241,9 +236,6 @@
 #define PHYS_SDRAM_1_SIZE	(32 << 20)	/* at least 32 MiB */
 #define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1

-/* SDRAM Bank Allocation method */
-#define SDRC_R_B_C		1
-
 #define CONFIG_SYS_TEXT_BASE		0x80008000
 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
 #define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
@@ -278,4 +270,6 @@
 #define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET
 #define CONFIG_ENV_ADDR			SMNAND_ENV_OFFSET

+#define CONFIG_SYS_CACHELINE_SIZE	64
+
 #endif				/* __CONFIG_H */
--- a/include/configs/omap3_sdp3430.h
+++ b/include/configs/omap3_sdp3430.h
@@ -38,7 +38,6 @@
 */
 #define CONFIG_OMAP		1	/* in a TI OMAP core */
 #define CONFIG_OMAP34XX		1	/* which is a 34XX */
-#define CONFIG_OMAP3430		1	/* which is in a 3430 */
 #define CONFIG_OMAP3_3430SDP	1	/* working with SDP Rev2 */

 #define CONFIG_SDRC	/* The chip has SDRC controller */
@@ -304,10 +303,6 @@
 * The stack sizes are set up in start.S using the settings below
 */
 #define CONFIG_STACKSIZE	(128 << 10) /* Regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ	(4 << 10) /* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ	(4 << 10) /* FIQ stack */
-#endif

 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
 #define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
@@ -323,9 +318,6 @@
 #define PHYS_SDRAM_1_SIZE	(32 << 20) /* at least 32 meg */
 #define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1

-/* SDRAM Bank Allocation method */
-#define SDRC_R_B_C		1
-
 /*--------------------------------------------------------------------------*/

 /*
@@ -358,4 +350,6 @@
 *  - rest for filesystem
 */

+#define CONFIG_SYS_CACHELINE_SIZE	64
+
 #endif				/* __CONFIG_H */
--- a/include/configs/omap3_zoom1.h
+++ b/include/configs/omap3_zoom1.h
@@ -34,7 +34,6 @@
 */
 #define CONFIG_OMAP		1	/* in a TI OMAP core */
 #define CONFIG_OMAP34XX		1	/* which is a 34XX */
-#define CONFIG_OMAP3430		1	/* which is in a 3430 */
 #define CONFIG_OMAP3_ZOOM1	1	/* working with Zoom MDK Rev1 */

 #define CONFIG_SDRC	/* The chip has SDRC controller */
@@ -259,10 +258,6 @@
 * The stack sizes are set up in start.S using the settings below
 */
 #define CONFIG_STACKSIZE	(128 << 10)	/* regular stack 128 KiB */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ	(4 << 10)	/* IRQ stack 4 KiB */
-#define CONFIG_STACKSIZE_FIQ	(4 << 10)	/* FIQ stack 4 KiB */
-#endif

 /*-----------------------------------------------------------------------
 * Physical Memory Map
@@ -272,9 +267,6 @@
 #define PHYS_SDRAM_1_SIZE	(32 << 20)	/* at least 32 MiB */
 #define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1

-/* SDRAM Bank Allocation method */
-#define SDRC_R_B_C		1
-
 /*-----------------------------------------------------------------------
 * FLASH and environment organization
 */
@@ -303,4 +295,6 @@
 #define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET
 #define CONFIG_ENV_ADDR			SMNAND_ENV_OFFSET

+#define CONFIG_SYS_CACHELINE_SIZE	64
+
 #endif				/* __CONFIG_H */
--- a/include/configs/omap3_zoom2.h
+++ b/include/configs/omap3_zoom2.h
@@ -35,7 +35,6 @@
 */
 #define CONFIG_OMAP		1	/* in a TI OMAP core */
 #define CONFIG_OMAP34XX		1	/* which is a 34XX */
-#define CONFIG_OMAP3430		1	/* which is in a 3430 */
 #define CONFIG_OMAP3_ZOOM2	1	/* working with Zoom II */

 #define CONFIG_SDRC	/* The chip has SDRC controller */
@@ -227,10 +226,6 @@
 * The stack sizes are set up in start.S using these settings
 */
 #define CONFIG_STACKSIZE	(128 << 10)	/* regular stack 128 KiB */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ	(4 << 10)	/* IRQ stack 4 KiB */
-#define CONFIG_STACKSIZE_FIQ	(4 << 10)	/* FIQ stack 4 KiB */
-#endif

 /*-----------------------------------------------------------------------
 * Physical Memory Map
@@ -240,9 +235,6 @@
 #define PHYS_SDRAM_1_SIZE	(32 << 20)	/* at least 32 MiB */
 #define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1

-/* SDRAM Bank Allocation method */
-#define SDRC_R_B_C		1
-
 /*-----------------------------------------------------------------------
 * FLASH and environment organization
 */
@@ -269,4 +261,6 @@
 #define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET
 #define CONFIG_ENV_ADDR			SMNAND_ENV_OFFSET

+#define CONFIG_SYS_CACHELINE_SIZE	64
+
 #endif /* __CONFIG_H */
--- a/include/configs/omap4_common.h
+++ b/include/configs/omap4_common.h
@@ -150,7 +150,7 @@

 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"loadaddr=0x82000000\0" \
-	"console=ttyS2,115200n8\0" \
+	"console=ttyO2,115200n8\0" \
 	"usbtty=cdc_acm\0" \
 	"vram=16M\0" \
 	"mmcdev=0\0" \
@@ -239,6 +239,7 @@
 #define CONFIG_SYS_L2_PL310		1
 #define CONFIG_SYS_PL310_BASE	0x48242000
 #endif
+#define CONFIG_SYS_CACHELINE_SIZE	32

 /* Defines for SDRAM init */
 #define CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
@@ -254,18 +255,21 @@
 #define CONFIG_SPL_MAX_SIZE		(38 * 1024)
 #define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK

-#define CONFIG_SPL_BSS_START_ADDR	0x80000000
-#define CONFIG_SPL_BSS_MAX_SIZE		0x80000		/* 512 KB */
 /*
- * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
 * 64 bytes before this address should be set aside for u-boot.img's
- * header. That is 0x800FFFC0--0x80100000 should not be used for any
+ * header. That is 80E7FFC0--0x80E80000 should not be used for any
 * other needs.
 */
-#define CONFIG_SYS_TEXT_BASE		0x80100000
-#define CONFIG_SYS_SPL_MALLOC_START	0x80200000
-#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000	/* 1 MB */
+#define CONFIG_SYS_TEXT_BASE		0x80E80000

+/*
+ * BSS and malloc area 64MB into memory to allow enough
+ * space for the kernel at the beginning of memory
+ */
+#define CONFIG_SPL_BSS_START_ADDR	0x84000000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x100000	/* 1 MB */
+#define CONFIG_SYS_SPL_MALLOC_START	0x84100000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000	/* 1 MB */

 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /* address 0x60000 */
 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x200 /* 256 KB */
--- a/include/configs/omap5_evm.h
+++ b/include/configs/omap5_evm.h
@@ -254,9 +254,6 @@
 #define CONFIG_SPL_MAX_SIZE		0x1E000	/* 120K */
 #define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK

-#define CONFIG_SPL_BSS_START_ADDR	0x80000000
-#define CONFIG_SPL_BSS_MAX_SIZE		0x80000		/* 512 KB */
-
 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /* address 0x60000 */
 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x200 /* 256 KB */
 #define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION	1
@@ -272,13 +269,19 @@
 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/omap-common/u-boot-spl.lds"

 /*
- * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
 * 64 bytes before this address should be set aside for u-boot.img's
- * header. That is 0x800FFFC0--0x80100000 should not be used for any
+ * header. That is 80E7FFC0--0x80E80000 should not be used for any
 * other needs.
 */
-#define CONFIG_SYS_TEXT_BASE		0x80100000
-#define CONFIG_SYS_SPL_MALLOC_START     0x80200000
-#define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000        /* 1 MB */
+#define CONFIG_SYS_TEXT_BASE		0x80E80000
+
+/*
+ * BSS and malloc area 64MB into memory to allow enough
+ * space for the kernel at the beginning of memory
+ */
+#define CONFIG_SPL_BSS_START_ADDR	0x84000000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x100000	/* 1 MB */
+#define CONFIG_SYS_SPL_MALLOC_START	0x84100000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000	/* 1 MB */

 #endif /* __CONFIG_H */
--- a/include/configs/palmld.h
+++ b/include/configs/palmld.h
@@ -25,7 +25,7 @@
 /*
 * High Level Board Configuration Options
 */
-#define	CONFIG_PXA27X		1	/* Marvell PXA270 CPU */
+#define	CONFIG_CPU_PXA27X		1	/* Marvell PXA270 CPU */
 #define	CONFIG_PALMLD		1	/* Palm LifeDrive board */

 /*
--- a/include/configs/palmtc.h
+++ b/include/configs/palmtc.h
@@ -27,7 +27,7 @@
 /*
 * High Level Board Configuration Options
 */
-#define	CONFIG_PXA250			1	/* Intel PXA255 CPU */
+#define	CONFIG_CPU_PXA25X			1	/* Intel PXA255 CPU */
 #define	CONFIG_PALMTC			1	/* Palm Tungsten|C board */

 /*
@@ -157,7 +157,7 @@
 #define	CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_DRAM_BASE

 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
-#define	CONFIG_SYS_INIT_SP_ADDR		(GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
+#define	CONFIG_SYS_INIT_SP_ADDR		0xfffff800

 /*
 * NOR FLASH
--- a/include/configs/pleb2.h
+++ b/include/configs/pleb2.h
@@ -1,266 +0,0 @@
-/*
- * (C) Copyright 2002
- * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * Configuration settings for the PLEB 2 board.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_PXA250		1	/* This is an PXA255 CPU    */
-#define CONFIG_PLEB2		1	/* on an PLEB2 Board	    */
-#undef CONFIG_LCD
-#undef CONFIG_MMC
-#define CONFIG_BOARD_LATE_INIT
-#define	CONFIG_SYS_TEXT_BASE	0x0
-
-#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff */
-
-/* we will never enable dcache, because we have to setup MMU first */
-#define CONFIG_SYS_DCACHE_OFF
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN	    (CONFIG_ENV_SIZE + 128*1024)
-
-/*
- * Hardware drivers
- */
-
-/* None - PLEB 2 doesn't have any of this.
-	#define CONFIG_LAN91C96
-	#define CONFIG_LAN91C96_BASE 0x0C000000
- */
-
-/*
- * select serial console configuration
- */
-#define CONFIG_PXA_SERIAL
-#define CONFIG_FFUART	       1       /* we use FFUART on PLEB 2 */
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_BAUDRATE		115200
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#undef CONFIG_CMD_NET
-#undef CONFIG_CMD_NFS
-
-
-#define CONFIG_BOOTDELAY	3
-#define CONFIG_ETHADDR		08:00:3e:26:0a:5b
-#define CONFIG_NETMASK		255.255.0.0
-#define CONFIG_IPADDR		192.168.0.21
-#define CONFIG_SERVERIP		192.168.0.250
-#define CONFIG_BOOTCOMMAND	"bootm 40000"
-#define CONFIG_BOOTARGS		"root=/dev/mtdblock2 prompt_ramdisk=0 load_ramdisk=1 console=ttyS0,115200"
-
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_INITRD_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	230400		/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2		/* which serial port to use */
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_HUSH_PARSER		1
-#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
-
-#define CONFIG_SYS_LONGHELP				/* undef to save memory		*/
-#ifdef CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT		"$ "		/* Monitor Command Prompt */
-#else
-#define CONFIG_SYS_PROMPT		"=> "		/* Monitor Command Prompt */
-#endif
-#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
-#define CONFIG_SYS_DEVICE_NULLDEV	1
-
-#define CONFIG_SYS_MEMTEST_START	0xa0400000	/* memtest works on	*/
-#define CONFIG_SYS_MEMTEST_END		0xa0800000	/* 4 ... 8 MB in DRAM	*/
-
-#define CONFIG_SYS_LOAD_ADDR		0xa2000000	/* default load address */
-
-#define CONFIG_SYS_HZ			1000
-#define CONFIG_SYS_CPUSPEED		0x141		/* set core clock to 200/200/100 MHz */
-
-						/* valid baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-#ifdef CONFIG_MMC
-#define CONFIG_PXA_MMC
-#define CONFIG_CMD_MMC
-#endif
-
-/*
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
-#endif
-
-/*
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS	1	   /* we have 1 bank of DRAM */
-#define PHYS_SDRAM_1		0xa0000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE	0x02000000 /* 32 MB */
-
-#define PHYS_FLASH_1		0x00000000 /* Flash Bank #1 */
-#define PHYS_FLASH_2		0x04000000 /* Flash Bank #2 */
-#define PHYS_FLASH_SIZE		0x00800000 /* 4 MB */
-
-/* Not entirely sure about this - DS/CHC */
-#define PHYS_FLASH_BANK_SIZE	0x02000000 /* 32 MB Banks */
-#define PHYS_FLASH_SECT_SIZE	0x00010000 /* 64 KB sectors (x2) */
-
-#define CONFIG_SYS_DRAM_BASE		PHYS_SDRAM_1
-#define CONFIG_SYS_DRAM_SIZE		PHYS_SDRAM_1_SIZE
-
-#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
-
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
-#define	CONFIG_SYS_INIT_SP_ADDR		(GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
-
-/*
- * GPIO settings
- */
-#define CONFIG_SYS_GPSR0_VAL		0x00000000  /* Don't set anything */
-#define CONFIG_SYS_GPSR1_VAL		0x00000080
-#define CONFIG_SYS_GPSR2_VAL		0x00000000
-
-#define CONFIG_SYS_GPCR0_VAL		0x00000000  /* Don't clear anything */
-#define CONFIG_SYS_GPCR1_VAL		0x00000000
-#define CONFIG_SYS_GPCR2_VAL		0x00000000
-
-#define CONFIG_SYS_GPDR0_VAL		0x00000000
-#define CONFIG_SYS_GPDR1_VAL		0x000007C3
-#define CONFIG_SYS_GPDR2_VAL		0x00000000
-
-/* Edge detect registers (these are set by the kernel) */
-#define CONFIG_SYS_GRER0_VAL	    0x00000000
-#define CONFIG_SYS_GRER1_VAL	    0x00000000
-#define CONFIG_SYS_GRER2_VAL	    0x00000000
-#define CONFIG_SYS_GFER0_VAL	    0x00000000
-#define CONFIG_SYS_GFER1_VAL	    0x00000000
-#define CONFIG_SYS_GFER2_VAL	    0x00000000
-
-#define CONFIG_SYS_GAFR0_L_VAL		0x00000000
-#define CONFIG_SYS_GAFR0_U_VAL		0x00000000
-#define CONFIG_SYS_GAFR1_L_VAL		0x00008010  /* Use FF UART Send and Receive */
-#define CONFIG_SYS_GAFR1_U_VAL		0x00000000
-#define CONFIG_SYS_GAFR2_L_VAL		0x00000000
-#define CONFIG_SYS_GAFR2_U_VAL		0x00000000
-
-#define CONFIG_SYS_PSSR_VAL		0x20
-#define CONFIG_SYS_CCCR		    0x00000141	/* 100 MHz memory, 200 MHz CPU	*/
-#define CONFIG_SYS_CKEN		    0x00000060	/* FFUART and STUART enabled	*/
-#define CONFIG_SYS_ICMR		    0x00000000	/* No interrupts enabled	*/
-
-/*
- * Memory settings
- */
-#define CONFIG_SYS_MSC0_VAL		0x00007FF0 /* Not properly calculated - FIXME (DS) */
-#define CONFIG_SYS_MSC1_VAL		0x00000000
-#define CONFIG_SYS_MSC2_VAL		0x00000000
-
-#define CONFIG_SYS_MDCNFG_VAL		0x00000aC9 /* Memory timings for the SDRAM.
-					      tRP=2, CL=2, tRCD=2, tRAS=5, tRC=8 */
-
-#define CONFIG_SYS_MDREFR_VAL		0x00403018 /* Initial setting, individual	*/
-					   /* bits set in lowlevel_init.S	*/
-#define CONFIG_SYS_MDMRS_VAL		0x00000000
-
-#define	CONFIG_SYS_FLYCNFG_VAL		0x00000000
-#define	CONFIG_SYS_SXCNFG_VAL		0x00000000
-
-/*
- * PCMCIA and CF Interfaces
- */
-#define CONFIG_SYS_MECR_VAL		0x00000000  /* Hangover from Lubbock.
-					       Needs calculating. (DS/CHC) */
-#define CONFIG_SYS_MCMEM0_VAL		0x00010504
-#define CONFIG_SYS_MCMEM1_VAL		0x00010504
-#define CONFIG_SYS_MCATT0_VAL		0x00010504
-#define CONFIG_SYS_MCATT1_VAL		0x00010504
-#define CONFIG_SYS_MCIO0_VAL		0x00004715
-#define CONFIG_SYS_MCIO1_VAL		0x00004715
-
-/*
- * FLASH and environment organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CONFIG_SYS_MAX_FLASH_SECT	64	/* max number of sectors on one chip	*/
-
-/* timeout values are in ticks */
-/* FIXME */
-#define CONFIG_SYS_FLASH_ERASE_TOUT	(25*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	(25*CONFIG_SYS_HZ) /* Timeout for Flash Write */
-
-/* Flash protection */
-#define CONFIG_SYS_FLASH_PROTECTION	1
-
-/* FIXME */
-#define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_ADDR		(PHYS_FLASH_1 + 0x3C000)	/* Addr of Environment Sector	*/
-#define CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment */
-#define CONFIG_ENV_SECT_SIZE	0x20000
-
-/* Option added to get around byte ordering issues in the flash driver */
-#define CONFIG_SYS_LITTLE_ENDIAN	1
-
-#endif	/* __CONFIG_H */
--- a/include/configs/pxa-common.h
+++ b/include/configs/pxa-common.h
@@ -0,0 +1,60 @@
+/*
+ * Toradex Colibri PXA270 configuration file
+ *
+ * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef	__CONFIG_PXA_COMMON_H__
+#define	__CONFIG_PXA_COMMON_H__
+
+#define	CONFIG_DISPLAY_CPUINFO
+
+/*
+ * KGDB
+ */
+#ifdef	CONFIG_CMD_KGDB
+#define	CONFIG_KGDB_BAUDRATE		230400
+#define	CONFIG_KGDB_SER_INDEX		2
+#endif
+
+/*
+ * MMC Card Configuration
+ */
+#ifdef	CONFIG_CMD_MMC
+#define	CONFIG_MMC
+#define	CONFIG_GENERIC_MMC
+#define	CONFIG_PXA_MMC_GENERIC
+#define	CONFIG_CMD_FAT
+#define	CONFIG_CMD_EXT2
+#define	CONFIG_DOS_PARTITION
+#endif
+
+/*
+ * OHCI USB
+ */
+#ifdef	CONFIG_CMD_USB
+#define	CONFIG_USB_OHCI_NEW
+#define	CONFIG_SYS_USB_OHCI_CPU_INIT
+#define	CONFIG_SYS_USB_OHCI_BOARD_INIT
+#define	CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
+#define	CONFIG_SYS_USB_OHCI_REGS_BASE		0x4c000000
+#define	CONFIG_SYS_USB_OHCI_SLOT_NAME		"pxa-ohci"
+#define	CONFIG_USB_STORAGE
+#endif
+
+#endif	/* __CONFIG_PXA_COMMON_H__ */
--- a/include/configs/pxa255_idp.h
+++ b/include/configs/pxa255_idp.h
@@ -55,7 +55,7 @@
 * High Level Configuration Options
 * (easy to change)
 */
-#define CONFIG_PXA250		1	/* This is an PXA250 CPU    */
+#define CONFIG_CPU_PXA25X		1	/* This is an PXA250 CPU    */

 #undef CONFIG_LCD
 #ifdef CONFIG_LCD
@@ -291,7 +291,7 @@
 #define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1

 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
-#define	CONFIG_SYS_INIT_SP_ADDR		(GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
+#define	CONFIG_SYS_INIT_SP_ADDR		0xfffff800

 /*
 * GPIO settings
--- a/include/configs/qong.h
+++ b/include/configs/qong.h
@@ -49,8 +49,8 @@
 * Hardware drivers
 */

-#define CONFIG_MXC_UART	1
-#define CONFIG_SYS_MX31_UART1	1
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE	UART1_BASE

 #define CONFIG_MXC_GPIO
 #define CONFIG_HW_WATCHDOG
--- a/include/configs/trizepsiv.h
+++ b/include/configs/trizepsiv.h
@@ -40,7 +40,7 @@
 * High Level Configuration Options
 * (easy to change)
 */
-#define CONFIG_PXA27X		1	/* This is an PXA27x CPU    */
+#define CONFIG_CPU_PXA27X		1	/* This is an PXA27x CPU    */

 #define CONFIG_MMC		1
 #define CONFIG_BOARD_LATE_INIT
--- a/include/configs/tt01.h
+++ b/include/configs/tt01.h
@@ -148,7 +148,7 @@
 * make sure that the transceiver is enabled during PL=1 for testing!
 */
 #define CONFIG_MXC_UART
-#define CONFIG_SYS_MX31_UART2
+#define CONFIG_MXC_UART_BASE	UART2_BASE

 #define CONFIG_MXC_SPI
 #define CONFIG_MXC_GPIO
--- a/include/configs/tx25.h
+++ b/include/configs/tx25.h
@@ -90,7 +90,7 @@
 * Serial Info
 */
 #define CONFIG_MXC_UART
-#define CONFIG_SYS_MX25_UART1
+#define CONFIG_MXC_UART_BASE	UART1_BASE
 #define CONFIG_CONS_INDEX	1	/* use UART0 for console */
 #define CONFIG_BAUDRATE		115200	/* Default baud rate */
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
--- a/include/configs/vision2.h
+++ b/include/configs/vision2.h
@@ -54,7 +54,7 @@
 * Hardware drivers
 */
 #define CONFIG_MXC_UART
-#define CONFIG_SYS_MX51_UART3
+#define CONFIG_MXC_UART_BASE	UART3_BASE
 #define CONFIG_MXC_GPIO
 #define CONFIG_MXC_SPI
 #define CONFIG_HW_WATCHDOG
--- a/include/configs/vpac270.h
+++ b/include/configs/vpac270.h
@@ -25,9 +25,19 @@
 /*
 * High Level Board Configuration Options
 */
-#define	CONFIG_PXA27X		1	/* Marvell PXA270 CPU */
+#define	CONFIG_CPU_PXA27X		1	/* Marvell PXA270 CPU */
 #define	CONFIG_VPAC270		1	/* Voipac PXA270 board */
-#define	CONFIG_SYS_TEXT_BASE	0x0
+#define	CONFIG_SYS_TEXT_BASE	0xa0000000
+
+#ifdef	CONFIG_ONENAND
+#define	CONFIG_SPL
+#define	CONFIG_SPL_ONENAND_SUPPORT
+#define	CONFIG_SPL_ONENAND_LOAD_ADDR	0x2000
+#define	CONFIG_SPL_ONENAND_LOAD_SIZE	\
+	(512 * 1024 - CONFIG_SPL_ONENAND_LOAD_ADDR)
+#define	CONFIG_SPL_TEXT_BASE	0x5c000000
+#define	CONFIG_SPL_LDSCRIPT	"board/vpac270/u-boot-spl.lds"
+#endif

 /*
 * Environment settings
@@ -46,12 +56,19 @@
 		"bootm 0xa4000000; "					\
 	"fi; "								\
 	"bootm 0x60000;"
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"update_onenand="						\
+		"onenand erase 0x0 0x80000 ; "				\
+		"onenand write 0xa0000000 0x0 0x80000"
+
 #define	CONFIG_BOOTARGS			"console=tty0 console=ttyS0,115200"
 #define	CONFIG_TIMESTAMP
 #define	CONFIG_BOOTDELAY		2	/* Autoboot delay */
 #define	CONFIG_CMDLINE_TAG
 #define	CONFIG_SETUP_MEMORY_TAGS
 #define	CONFIG_LZMA			/* LZMA compression support */
+#define	CONFIG_OF_LIBFDT

 /*
 * Serial Console Configuration
@@ -141,6 +158,8 @@
 #define	CONFIG_SYS_MAXARGS		16
 #define	CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
 #define	CONFIG_SYS_DEVICE_NULLDEV	1
+#define	CONFIG_CMDLINE_EDITING		1
+#define	CONFIG_AUTO_COMPLETE		1

 /*
 * Clock Configuration
@@ -180,19 +199,18 @@
 #define	CONFIG_SYS_MEMTEST_END		0xa0800000	/* 4 ... 8 MB in DRAM */

 #define	CONFIG_SYS_LOAD_ADDR		PHYS_SDRAM_1
-#define	CONFIG_SYS_IPL_LOAD_ADDR	(0x5c000000)
 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
-#define	CONFIG_SYS_INIT_SP_ADDR		\
-	(PHYS_SDRAM_1 + GENERATED_GBL_DATA_SIZE + 2048)
+#define	CONFIG_SYS_INIT_SP_ADDR		0x5c010000

 /*
 * NOR FLASH
 */
 #define	CONFIG_SYS_MONITOR_BASE		0x0
-#define	CONFIG_SYS_MONITOR_LEN		0x40000
+#define	CONFIG_SYS_MONITOR_LEN		0x80000
 #define	CONFIG_ENV_ADDR			\
 			(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
-#define	CONFIG_ENV_SIZE			0x4000
+#define	CONFIG_ENV_SIZE			0x20000
+#define	CONFIG_ENV_SECT_SIZE		0x20000

 #if	defined(CONFIG_CMD_FLASH)	/* NOR */
 #define	PHYS_FLASH_1			0x00000000	/* Flash Bank #1 */
@@ -221,22 +239,11 @@

 #define	CONFIG_ENV_IS_IN_FLASH		1

-/*
- * The first four sectors of the NOR flash are 0x8000 bytes big, the rest of the
- * flash consists of 0x20000 bytes big sectors.
- */
-#if	(CONFIG_ENV_ADDR <= 0x18000)
-#define	CONFIG_ENV_SECT_SIZE		0x8000
-#else
-#define	CONFIG_ENV_SECT_SIZE		0x20000
-#endif
-
 #elif	defined(CONFIG_CMD_ONENAND)	/* OneNAND */
 #define	CONFIG_SYS_NO_FLASH
 #define	CONFIG_SYS_ONENAND_BASE		0x00000000

 #define	CONFIG_ENV_IS_IN_ONENAND	1
-#define	CONFIG_ENV_SECT_SIZE		0x20000

 #else	/* No flash */
 #define	CONFIG_SYS_NO_FLASH
--- a/include/configs/xaeniax.h
+++ b/include/configs/xaeniax.h
@@ -40,7 +40,7 @@
 * High Level Configuration Options
 * (easy to change)
 */
-#define CONFIG_PXA250		1	/* This is an PXA255 CPU    */
+#define CONFIG_CPU_PXA25X		1	/* This is an PXA255 CPU    */
 #define CONFIG_XAENIAX		1	/* on a xaeniax board	    */
 #define	CONFIG_SYS_TEXT_BASE	0x0

@@ -168,7 +168,7 @@
 #define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1

 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
-#define	CONFIG_SYS_INIT_SP_ADDR		(GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
+#define	CONFIG_SYS_INIT_SP_ADDR		0xfffff800

 /*
 * FLASH and environment organization
--- a/include/configs/xm250.h
+++ b/include/configs/xm250.h
@@ -1,369 +0,0 @@
-/*
- * (C) Copyright 2002
- * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_PXA250	       1	/* This is an PXA250 CPU	*/
-#define CONFIG_XM250	       1	/* on a MicroSys XM250 Board	*/
-#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff	*/
-#define	CONFIG_SYS_TEXT_BASE	0x0
-
-/* we will never enable dcache, because we have to setup MMU first */
-#define CONFIG_SYS_DCACHE_OFF
-
-/*
- * Size of malloc() pool; this lives below the uppermost 128 KiB which are
- * used for the RAM copy of the uboot code
- *
- */
-#define CONFIG_SYS_MALLOC_LEN		(256*1024)
-
-/*
- * Hardware drivers
- */
-#define CONFIG_SMC91111
-#define CONFIG_SMC91111_BASE		0x04000300
-#undef	CONFIG_SMC91111_EXT_PHY
-#define CONFIG_SMC_USE_32_BIT
-#undef	CONFIG_SHOW_ACTIVITY
-#define CONFIG_NET_RETRY_COUNT		10	   /* # of retries		*/
-
-/*
- * I2C bus
- */
-#define CONFIG_I2C_MV			1
-#define CONFIG_MV_I2C_REG		0x40301680
-#define CONFIG_HARD_I2C			1
-#define CONFIG_SYS_I2C_SPEED			50000
-#define CONFIG_SYS_I2C_SLAVE			0xfe
-
-#define CONFIG_RTC_PCF8563		1
-#define CONFIG_SYS_I2C_RTC_ADDR		0x51
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR		0x58	/* A0 = 0 (hardwired)		*/
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4	/* 4 bits = 16 octets		*/
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* between stop and start	*/
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1	/* length of address		*/
-#define CONFIG_SYS_EEPROM_SIZE			2048	/* size in bytes		*/
-#undef	CONFIG_SYS_I2C_INIT_BOARD			/* board has no own init	*/
-
-/*
- * select serial console configuration
- */
-#define CONFIG_PXA_SERIAL
-#define CONFIG_FFUART	       1       /* we use FFUART */
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_BAUDRATE		115200
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_I2C
-
-
-#define CONFIG_BOOTDELAY	3
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP				/* undef to save memory		*/
-#define CONFIG_SYS_PROMPT		"=> "		/* Monitor Command Prompt	*/
-#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CONFIG_SYS_MEMTEST_START	0xa0400000	/* memtest works on		*/
-#define CONFIG_SYS_MEMTEST_END		0xa0800000	/* 4 ... 8 MB in DRAM		*/
-
-#define CONFIG_SYS_LOAD_ADDR		0xa3000000	/* default load address */
-
-#define CONFIG_SYS_HZ			1000
-#define CONFIG_SYS_CPUSPEED		0x161		/* set core clock to 400/400/100 MHz */
-
-						/* valid baudrates */
-
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-/*
- * Definitions related to passing arguments to kernel.
- */
-#define CONFIG_CMDLINE_TAG	 1	 /* send commandline to Kernel		*/
-#define CONFIG_SETUP_MEMORY_TAGS 1	 /* send memory definition to kernel	*/
-#define	CONFIG_INITRD_TAG	 1	 /* do not send initrd params		*/
-
-/*
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
-#endif
-
-/*
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS	4
-#define PHYS_SDRAM_1		0xa0000000 /* SDRAM Bank #1	*/
-#define PHYS_SDRAM_1_SIZE	0x04000000 /* 64 MB		*/
-#define PHYS_SDRAM_2		0xa4000000 /* SDRAM Bank #2	*/
-#define PHYS_SDRAM_2_SIZE	0x00000000 /* 0 MB		*/
-#define PHYS_SDRAM_3		0xa8000000 /* SDRAM Bank #3	*/
-#define PHYS_SDRAM_3_SIZE	0x00000000 /* 0 MB		*/
-#define PHYS_SDRAM_4		0xac000000 /* SDRAM Bank #4	*/
-#define PHYS_SDRAM_4_SIZE	0x00000000 /* 0 MB		*/
-
-#define PHYS_FLASH_1		0x00000000 /* Flash Bank #1	*/
-#define PHYS_FLASH_2		0x04000000 /* Flash Bank #1	*/
-#define PHYS_FLASH_SIZE		0x01000000 /* 16 MB		*/
-#define PHYS_FLASH_BANK_SIZE	0x01000000 /* 16 MB Banks	*/
-#define PHYS_FLASH_SECT_SIZE	0x00040000 /* 256 KB sectors (x2) */
-
-#define CONFIG_SYS_DRAM_BASE		0xa0000000
-#define CONFIG_SYS_DRAM_SIZE		0x04000000
-
-#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
-
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
-#define	CONFIG_SYS_INIT_SP_ADDR		(GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
-
-/*
- * FLASH and environment organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS	1     /* max number of memory banks		*/
-#define CONFIG_SYS_MAX_FLASH_SECT	128   /* max number of sectors on one chip	*/
-
-/* timeout values are in ticks */
-#define CONFIG_SYS_FLASH_ERASE_TOUT	(2*CONFIG_SYS_HZ)	/* Timeout for Flash Erase	*/
-#define CONFIG_SYS_FLASH_WRITE_TOUT	(2*CONFIG_SYS_HZ)	/* Timeout for Flash Write	*/
-#define CONFIG_SYS_FLASH_LOCK_TOUT	(2*CONFIG_SYS_HZ)	/* Timeout for Flash Set Lock Bit */
-#define CONFIG_SYS_FLASH_UNLOCK_TOUT	(2*CONFIG_SYS_HZ)	/* Timeout for Flash Clear Lock Bits */
-#define CONFIG_SYS_FLASH_PROTECTION			/* "Real" (hardware) sectors protection */
-
-#define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_ADDR		(PHYS_FLASH_1 + 0x40000)	/* Addr of Environment Sector	*/
-#define CONFIG_ENV_SIZE		0x4000
-#define CONFIG_ENV_SECT_SIZE	0x40000				/* Size of the Environment Sector	*/
-#define CONFIG_SYS_MONITOR_LEN		0x20000				/* 128 KiB */
-
-/******************************************************************************
- *
- * CPU specific defines
- *
- ******************************************************************************/
-
-/*
- * GPIO settings
- *
- * GPIO pin assignments
- * GPIO	    Name	Dir Out AF
- * 0	    NC
- * 1	    NC
- * 2	    SIRQ1	I
- * 3	    SIRQ2	I
- * 4	    SIRQ3	I
- * 5	    DMAACK1	O   0
- * 6	    DMAACK2	O   0
- * 7	    DMAACK3	O   0
- * 8	    TC1		O   0
- * 9	    TC2		O   0
- * 10	    TC3		O   0
- * 11	    nDMAEN	O   1
- * 12	    AENCTRL	O   0
- * 13	    PLDTC	O   0
- * 14	    ETHIRQ	I
- * 15	    NC
- * 16	    NC
- * 17	    NC
- * 18	    RDY		I
- * 19	    DMASIO	I
- * 20	    ETHIRQ	NC
- * 21	    NC
- * 22	    PGMEN	O   1	 FIXME for debug only enable flash
- * 23	    NC
- * 24	    NC
- * 25	    NC
- * 26	    NC
- * 27	    NC
- * 28	    NC
- * 29	    NC
- * 30	    NC
- * 31	    NC
- * 32	    NC
- * 33	    NC
- * 34	    FFRXD	I	01
- * 35	    FFCTS	I	01
- * 36	    FFDCD	I	01
- * 37	    FFDSR	I	01
- * 38	    FFRI	I	01
- * 39	    FFTXD	O   1	10
- * 40	    FFDTR	O   0	10
- * 41	    FFRTS	O   0	10
- * 42	    RS232FOFF	O   0	00
- * 43	    NC
- * 44	    NC
- * 45	    IRSL0	O   0
- * 46	    IRRX0	I	01
- * 47	    IRTX0	O   0	10
- * 48	    NC
- * 49	    nIOWE	O   0
- * 50	    NC
- * 51	    NC
- * 52	    NC
- * 53	    NC
- * 54	    NC
- * 55	    NC
- * 56	    NC
- * 57	    NC
- * 58	    DKDIRQ	I
- * 59	    NC
- * 60	    NC
- * 61	    NC
- * 62	    NC
- * 63	    NC
- * 64	    COMLED	O   0
- * 65	    COMLED	O   0
- * 66	    COMLED	O   0
- * 67	    COMLED	O   0
- * 68	    COMLED	O   0
- * 69	    COMLED	O   0
- * 70	    COMLED	O   0
- * 71	    COMLED	O   0
- * 72	    NC
- * 73	    NC
- * 74	    NC
- * 75	    NC
- * 76	    NC
- * 77	    NC
- * 78	    CSIO	O   1
- * 79	    NC
- * 80	    CSETH	O   1
- *
- * NOTE: All NC's are defined to be outputs
- *
- */
-/* Pin direction control */
-#define CONFIG_SYS_GPDR0_VAL	    0xd3808000
-#define CONFIG_SYS_GPDR1_VAL	    0xfcffab83
-#define CONFIG_SYS_GPDR2_VAL	    0x0001ffff
-/* Set and Clear registers */
-#define CONFIG_SYS_GPSR0_VAL	    0x00008000
-#define CONFIG_SYS_GPSR1_VAL	    0x00ff0002
-#define CONFIG_SYS_GPSR2_VAL	    0x0001c000
-#define CONFIG_SYS_GPCR0_VAL	    0x00000000
-#define CONFIG_SYS_GPCR1_VAL	    0x00000000
-#define CONFIG_SYS_GPCR2_VAL	    0x00000000
-/* Edge detect registers (these are set by the kernel) */
-#define CONFIG_SYS_GRER0_VAL	    0x00002180
-#define CONFIG_SYS_GRER1_VAL	    0x00000000
-#define CONFIG_SYS_GRER2_VAL	    0x00000000
-#define CONFIG_SYS_GFER0_VAL	    0x000043e0
-#define CONFIG_SYS_GFER1_VAL	    0x00000000
-#define CONFIG_SYS_GFER2_VAL	    0x00000000
-/* Alternate function registers */
-#define CONFIG_SYS_GAFR0_L_VAL	    0x80000004
-#define CONFIG_SYS_GAFR0_U_VAL	    0x595a8010
-#define CONFIG_SYS_GAFR1_L_VAL	    0x699a9559
-#define CONFIG_SYS_GAFR1_U_VAL	    0xaaa5aaaa
-#define CONFIG_SYS_GAFR2_L_VAL	    0xaaaaaaaa
-#define CONFIG_SYS_GAFR2_U_VAL	    0x00000002
-
-/*
- * Clocks, power control and interrupts
- */
-#define CONFIG_SYS_PSSR_VAL	    0x00000030
-#define CONFIG_SYS_CCCR		    0x00000161	/* 100 MHz memory, 400 MHz CPU, 400 Turbo  */
-#define CONFIG_SYS_CKEN		    0x000141ec	/* FFUART and STUART enabled	*/
-#define CONFIG_SYS_ICMR		    0x00000000	/* No interrupts enabled	*/
-
-/* FIXME
- *
- * RTC settings
- * Watchdog
- *
- */
-
-/*
- * Memory settings
- *
- */
-#define CONFIG_SYS_MSC0_VAL	    0x122423f0	/* FLASH   / LAN	    (cs0)/(cS1)	  */
-#define CONFIG_SYS_MSC1_VAL	    0x35f4aa4c	/* USB	   / ST3+ST5	    (cs2)/(cS3)	  */
-#define CONFIG_SYS_MSC2_VAL	    0x35f435fc	/* IDE	   / BCR + WatchDog (cs4)/(cS5)	  */
-#define CONFIG_SYS_MDCNFG_VAL	    0x000009c9
-#define CONFIG_SYS_MDMRS_VAL	    0x00220022
-#define CONFIG_SYS_MDREFR_VAL	    0x000da018	/* Initial setting, individual bits set in lowlevel_init.S */
-#define	CONFIG_SYS_FLYCNFG_VAL		0x00000000
-#define	CONFIG_SYS_SXCNFG_VAL		0x00000000
-
-/*
- * PCMCIA and CF Interfaces (NOT USED, these values from lubbock init)
- */
-#define CONFIG_SYS_MECR_VAL	      0x00000000
-#define CONFIG_SYS_MCMEM0_VAL	      0x00010504
-#define CONFIG_SYS_MCMEM1_VAL	      0x00010504
-#define CONFIG_SYS_MCATT0_VAL	      0x00010504
-#define CONFIG_SYS_MCATT1_VAL	      0x00010504
-#define CONFIG_SYS_MCIO0_VAL	      0x00004715
-#define CONFIG_SYS_MCIO1_VAL	      0x00004715
-
-/* Board specific defines */
-
-#ifndef __ASSEMBLY__
-
-/* global prototypes */
-void led_code(int code, int color);
-
-#endif
-
-#endif	/* __CONFIG_H */
--- a/include/configs/zipitz2.h
+++ b/include/configs/zipitz2.h
@@ -25,7 +25,7 @@
 /*
 * High Level Board Configuration Options
 */
-#define	CONFIG_PXA27X		1	/* Marvell PXA270 CPU */
+#define	CONFIG_CPU_PXA27X		1	/* Marvell PXA270 CPU */
 #define	CONFIG_ZIPITZ2		1	/* Zipit Z2 board */
 #define	CONFIG_SYS_TEXT_BASE	0x0

--- a/include/configs/zmx25.h
+++ b/include/configs/zmx25.h
@@ -66,7 +66,7 @@
 * Serial
 */
 #define CONFIG_MXC_UART
-#define CONFIG_SYS_MX25_UART2
+#define CONFIG_MXC_UART_BASE	UART2_BASE
 #define CONFIG_CONS_INDEX	1	/* use UART2 for console */
 #define CONFIG_BAUDRATE		115200	/* Default baud rate */
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
--- a/include/lcd.h
+++ b/include/lcd.h
@@ -87,7 +87,8 @@ typedef struct vidinfo {
 	u_char	vl_wbf;		/* Wait between frames */
 } vidinfo_t;

-#elif defined CONFIG_PXA250 || defined CONFIG_PXA27X || defined CONFIG_CPU_MONAHANS
+#elif defined(CONFIG_CPU_PXA25X) || defined(CONFIG_CPU_PXA27X) || \
+	defined CONFIG_CPU_MONAHANS
 /*
 * PXA LCD DMA descriptor
 */
@@ -195,7 +196,7 @@ typedef struct vidinfo {
 	void	*priv;		/* Pointer to driver-specific data */
 } vidinfo_t;

-#endif /* CONFIG_MPC823, CONFIG_PXA250 or CONFIG_MCC200 or CONFIG_ATMEL_LCD */
+#endif /* CONFIG_MPC823, CONFIG_CPU_PXA25X, CONFIG_MCC200, CONFIG_ATMEL_LCD */

 extern vidinfo_t panel_info;

--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -623,4 +623,11 @@ struct platform_nand_chip *get_platform_nandchip(struct mtd_info *mtd)
 	return chip->priv;
 }

+/* Standard NAND functions from nand_base.c */
+void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len);
+void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len);
+void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len);
+void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len);
+uint8_t nand_read_byte(struct mtd_info *mtd);
+
 #endif /* __LINUX_MTD_NAND_H */
--- a/include/mc13892.h
+++ b/include/mc13892.h
@@ -139,6 +139,22 @@
 #define VCAM_3_0	(3 << 16)
 #define VCAM_MASK	(3 << 16)

+/* Reg Mode 0 */
+#define VGEN1EN		(1 << 0)
+#define VGEN1STBY	(1 << 1)
+#define VGEN1MODE	(1 << 2)
+#define VIOHIEN		(1 << 3)
+#define VIOHISTBY	(1 << 4)
+#define VDIGEN		(1 << 9)
+#define VDIGSTBY	(1 << 10)
+#define VGEN2EN		(1 << 12)
+#define VGEN2STBY	(1 << 13)
+#define VGEN2MODE	(1 << 14)
+#define VPLLEN		(1 << 15)
+#define VPLLSTBY	(1 << 16)
+#define VUSBEN		(1 << 18)
+#define VUSBSTBY	(1 << 19)
+
 /* Reg Mode 1 */
 #define VGEN3EN		(1 << 0)
 #define VGEN3STBY	(1 << 1)
--- a/include/nand.h
+++ b/include/nand.h
@@ -135,9 +135,6 @@ int nand_get_lock_status(nand_info_t *meminfo, loff_t offset);
 int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst);
 void nand_deselect(void);

-void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len);
-void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len);
-
 #ifdef CONFIG_SYS_NAND_SELECT_DEVICE
 void board_nand_select_device(struct nand_chip *nand, int chip);
 #endif