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Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq

Browse Source
This commit is contained in:
Tom Rini
2016-06-04 08:49:08 -04:00
parent f15715afea ff78aa2ba1
commit c41c649c2f
77 changed files with 2616 additions and 370 deletions
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7
board/freescale/common/ls102xa_stream_id.c
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@@ -12,9 +12,12 @@ void ls102xa_config_smmu_stream_id(struct smmu_stream_id *id, uint32_t num)
{
void *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
int i;
u32 icid;
for (i = 0; i < num; i++)
out_be32((u32 *)(scfg + id[i].offset), id[i].stream_id);
for (i = 0; i < num; i++) {
icid = (id[i].stream_id & 0xff) << 24;
out_be32((u32 *)(scfg + id[i].offset), icid);
}
}
void ls1021x_config_caam_stream_id(struct liodn_id_table *tbl, int size)

13
board/freescale/common/qixis.c
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@@ -14,6 +14,13 @@
#include <i2c.h>
#include "qixis.h"
#ifndef QIXIS_LBMAP_BRDCFG_REG
/*
* For consistency with existing platforms
*/
#define QIXIS_LBMAP_BRDCFG_REG 0x00
#endif
#ifdef CONFIG_SYS_I2C_FPGA_ADDR
u8 qixis_read_i2c(unsigned int reg)
{
@@ -27,6 +34,7 @@ void qixis_write_i2c(unsigned int reg, u8 value)
}
#endif
#ifdef QIXIS_BASE
u8 qixis_read(unsigned int reg)
{
void *p = (void *)QIXIS_BASE;
@@ -40,6 +48,7 @@ void qixis_write(unsigned int reg, u8 value)
out_8(p + reg, value);
}
#endif
u16 qixis_read_minor(void)
{
@@ -142,9 +151,9 @@ static void __maybe_unused set_lbmap(int lbmap)
{
u8 reg;
reg = QIXIS_READ(brdcfg[0]);
reg = QIXIS_READ(brdcfg[QIXIS_LBMAP_BRDCFG_REG]);
reg = (reg & ~QIXIS_LBMAP_MASK) | lbmap;
QIXIS_WRITE(brdcfg[0], reg);
QIXIS_WRITE(brdcfg[QIXIS_LBMAP_BRDCFG_REG], reg);
}
static void __maybe_unused set_rcw_src(int rcw_src)

15
board/freescale/ls1012afrdm/Kconfig Normal file
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@@ -0,0 +1,15 @@
if TARGET_LS1012AFRDM
config SYS_BOARD
default "ls1012afrdm"
config SYS_VENDOR
default "freescale"
config SYS_SOC
default "fsl-layerscape"
config SYS_CONFIG_NAME
default "ls1012afrdm"
endif

6
board/freescale/ls1012afrdm/MAINTAINERS Normal file
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@@ -0,0 +1,6 @@
LS1012AFRDM BOARD
M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
S: Maintained
F: board/freescale/ls1012afrdm/
F: include/configs/ls1012afrdm.h
F: configs/ls1012afrdm_qspi_defconfig

7
board/freescale/ls1012afrdm/Makefile Normal file
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@@ -0,0 +1,7 @@
#
# Copyright 2016 Freescale Semiconductor, Inc.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += ls1012afrdm.o

58
board/freescale/ls1012afrdm/README Normal file
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@@ -0,0 +1,58 @@
Overview
--------
QorIQ LS1012A FREEDOM (LS1012AFRDM) is a high-performance development
platform, with a complete debugging environment. The LS1012AFRDM board
supports the QorIQ LS1012A processor and is optimized to support the
high-bandwidth DDR3L memory and a full complement of high-speed SerDes ports.
LS1012A SoC Overview
--------------------
Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A
SoC overview.
LS1012AFRDM board Overview
-----------------------
- SERDES Connections, 2 lanes supportingspeeds upto 1 Gbit/s
- 2 SGMII 1G PHYs
- DDR Controller
- 4 Gb DDR3L SDRAM memory, running at data rates up to 1 GT/s
operating at 1.35 V
- QSPI
- Onboard 512 Mbit QSPI flash memory running at speed up
to 108/54 MHz
- One high-speed USB 2.0/3.0 port, one USB 2.0 port
- USB 2.0/3.0 port is configured as On-The-Go (OTG) with a
Micro-AB connector.
- USB 2.0 port is a debug port (CMSIS DAP) and is configured
as a Micro-AB device.
- I2C controller
- One I2C bus with connectivity to Arduino headers
- UART
- UART (Console): UART1 (Without flow control) for console
- ARM JTAG support
- ARM Cortex® 10-pin JTAG connector for LS1012A
- CMSIS DAP through K20 microcontroller
- SAI Audio interface
- One SAI port, SAI 2 with full duplex support
- Clocks
- 25 MHz crystal for LS1012A
- 8 MHz Crystal for K20
- 24 MHz for SC16IS740IPW SPI to Dual UART bridge
- Power Supplies
- 5 V input supply from USB
- 0.9 V, 1.35 V, and 1.8 V for VDD/Core, DDR, I/O, and
other board interfaces
Booting Options
---------------
QSPI Flash 1
QSPI flash map
--------------
Images | Size |QSPI Flash Address
------------------------------------------
RCW + PBI | 1MB | 0x4000_0000
U-boot | 1MB | 0x4010_0000
U-boot Env | 1MB | 0x4020_0000
PPA FIT image | 2MB | 0x4050_0000
Linux ITB | ~53MB | 0x40A0_0000

192
board/freescale/ls1012afrdm/ls1012afrdm.c Normal file
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@@ -0,0 +1,192 @@
/*
* Copyright 2016 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <i2c.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/fsl_serdes.h>
#include <asm/arch/soc.h>
#include <hwconfig.h>
#include <fsl_csu.h>
#include <environment.h>
#include <fsl_mmdc.h>
#include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;
static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
{
int timeout = 1000;
out_be32(ptr, value);
while (in_be32(ptr) & bits) {
udelay(100);
timeout--;
}
if (timeout <= 0)
puts("Error: wait for clear timeout.\n");
}
int checkboard(void)
{
puts("Board: LS1012AFRDM ");
return 0;
}
void mmdc_init(void)
{
struct mmdc_p_regs *mmdc =
(struct mmdc_p_regs *)CONFIG_SYS_FSL_DDR_ADDR;
out_be32(&mmdc->mdscr, CONFIGURATION_REQ);
/* configure timing parms */
out_be32(&mmdc->mdotc, CONFIG_SYS_MMDC_CORE_ODT_TIMING);
out_be32(&mmdc->mdcfg0, CONFIG_SYS_MMDC_CORE_TIMING_CFG_0);
out_be32(&mmdc->mdcfg1, CONFIG_SYS_MMDC_CORE_TIMING_CFG_1);
out_be32(&mmdc->mdcfg2, CONFIG_SYS_MMDC_CORE_TIMING_CFG_2);
/* other parms */
out_be32(&mmdc->mdmisc, CONFIG_SYS_MMDC_CORE_MISC);
out_be32(&mmdc->mpmur0, CONFIG_SYS_MMDC_PHY_MEASURE_UNIT);
out_be32(&mmdc->mdrwd, CONFIG_SYS_MMDC_CORE_RDWR_CMD_DELAY);
out_be32(&mmdc->mpodtctrl, CONFIG_SYS_MMDC_PHY_ODT_CTRL);
/* out of reset delays */
out_be32(&mmdc->mdor, CONFIG_SYS_MMDC_CORE_OUT_OF_RESET_DELAY);
/* physical parms */
out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_1);
out_be32(&mmdc->mdasp, CONFIG_SYS_MMDC_CORE_ADDR_PARTITION);
/* Enable MMDC */
out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_2);
/* dram init sequence: update MRs */
out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x8) | CONFIGURATION_REQ |
CMD_LOAD_MODE_REG | CMD_BANK_ADDR_2));
out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
CMD_BANK_ADDR_3));
out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1));
out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x19) |
CMD_ADDR_LSB_MR_ADDR(0x30) | CONFIGURATION_REQ |
CMD_LOAD_MODE_REG | CMD_BANK_ADDR_0));
/* dram init sequence: ZQCL */
out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
CMD_ZQ_CALIBRATION | CMD_BANK_ADDR_0));
set_wait_for_bits_clear(&mmdc->mpzqhwctrl,
CONFIG_SYS_MMDC_PHY_ZQ_HW_CTRL,
FORCE_ZQ_AUTO_CALIBRATION);
/* Calibrations now: wr lvl */
out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x84) |
CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
CMD_BANK_ADDR_1));
out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | WL_EN | CMD_NORMAL));
set_wait_for_bits_clear(&mmdc->mpwlgcr, WR_LVL_HW_EN, WR_LVL_HW_EN);
mdelay(1);
out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1));
out_be32(&mmdc->mdscr, CONFIGURATION_REQ);
mdelay(1);
/* Calibrations now: Read DQS gating calibration */
out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0));
out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3));
out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN);
out_be32(&mmdc->mprddlctl, CONFIG_SYS_MMDC_PHY_RD_DLY_LINES_CFG);
set_wait_for_bits_clear(&mmdc->mpdgctrl0,
AUTO_RD_DQS_GATING_CALIBRATION_EN,
AUTO_RD_DQS_GATING_CALIBRATION_EN);
out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
CMD_BANK_ADDR_3));
/* Calibrations now: Read calibration */
out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0));
out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3));
out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN);
set_wait_for_bits_clear(&mmdc->mprddlhwctl,
AUTO_RD_CALIBRATION_EN,
AUTO_RD_CALIBRATION_EN);
out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
CMD_BANK_ADDR_3));
/* PD, SR */
out_be32(&mmdc->mdpdc, CONFIG_SYS_MMDC_CORE_PWR_DOWN_CTRL);
out_be32(&mmdc->mapsr, CONFIG_SYS_MMDC_CORE_PWR_SAV_CTRL_STAT);
/* refresh scheme */
set_wait_for_bits_clear(&mmdc->mdref,
CONFIG_SYS_MMDC_CORE_REFRESH_CTL,
START_REFRESH);
/* disable CON_REQ */
out_be32(&mmdc->mdscr, DISABLE_CFG_REQ);
}
int dram_init(void)
{
mmdc_init();
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
return 0;
}
int board_eth_init(bd_t *bis)
{
return pci_eth_init(bis);
}
int board_early_init_f(void)
{
fsl_lsch2_early_init_f();
return 0;
}
int board_init(void)
{
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
/*
* Set CCI-400 control override register to enable barrier
* transaction
*/
out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
#ifdef CONFIG_ENV_IS_NOWHERE
gd->env_addr = (ulong)&default_environment[0];
#endif
#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
enable_layerscape_ns_access();
#endif
return 0;
}
int ft_board_setup(void *blob, bd_t *bd)
{
arch_fixup_fdt(blob);
ft_cpu_setup(blob, bd);
return 0;
}

15
board/freescale/ls1012aqds/Kconfig Normal file
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@@ -0,0 +1,15 @@
if TARGET_LS1012AQDS
config SYS_BOARD
default "ls1012aqds"
config SYS_VENDOR
default "freescale"
config SYS_SOC
default "fsl-layerscape"
config SYS_CONFIG_NAME
default "ls1012aqds"
endif

6
board/freescale/ls1012aqds/MAINTAINERS Normal file
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@@ -0,0 +1,6 @@
LS1012AQDS BOARD
M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
S: Maintained
F: board/freescale/ls1012aqds/
F: include/configs/ls1012aqds.h
F: configs/ls1012aqds_qspi_defconfig

7
board/freescale/ls1012aqds/Makefile Normal file
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@@ -0,0 +1,7 @@
#
# Copyright 2016 Freescale Semiconductor, Inc.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += ls1012aqds.o

59
board/freescale/ls1012aqds/README Normal file
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@@ -0,0 +1,59 @@
Overview
--------
QorIQ LS1012A Development System (LS1012AQDS) is a high-performance
development platform, with a complete debugging environment.
The LS1012AQDS board supports the QorIQ LS1012A processor and is
optimized to support the high-bandwidth DDR3L memory and
a full complement of high-speed SerDes ports.
LS1012A SoC Overview
--------------------
Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1012A
SoC overview.
LS1012AQDS board Overview
-----------------------
- SERDES Connections, 4 lanes supporting:
- PCI Express - 3.0
- SGMII, SGMII 2.5
- SATA 3.0
- DDR Controller
- 16-bit, 1 GB DDR3L SDRAM memory, running at data rates up to 1 GT/s
- QSPI Controller
- A dual 1:3 switch, NX3L4357GM,115 (U35) drives the QSPI chip-select
signals to QSPI NOR flash memory (2 virtual banks) and the QSPI
emulator
- USB 3.0
- One USB 3.0 controller with integrated PHY
- One high-speed USB 3.0 port
- USB 2.0
- One USB 2.0 controller with ULPI interface
- Two enhanced secure digital host controllers:
- SDHC1 controller can be connected to onboard SDHC connector
- SDHC2 controller: 1-/4-bit SD/MMC card supporting 1.8 V devices
- 2 I2C controllers
- One SATA onboard connectors
- UART
- 5 SAI
- One SAI port with audio codec SGTL5000:
• Provides MIC bias
• Provides headphone and line output
- One SAI port terminated at 2x6 header
- Three SAI Tx/Rx ports terminated at 2x3 headers
- ARM JTAG support
Booting Options
---------------
a) QSPI Flash Emu Boot
b) QSPI Flash 1
c) QSPI Flash 2
QSPI flash map
--------------
Images | Size |QSPI Flash Address
------------------------------------------
RCW + PBI | 1MB | 0x4000_0000
U-boot | 1MB | 0x4010_0000
U-boot Env | 1MB | 0x4020_0000
PPA FIT image | 2MB | 0x4050_0000
Linux ITB | ~53MB | 0x40A0_0000

234
board/freescale/ls1012aqds/ls1012aqds.c Normal file
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@@ -0,0 +1,234 @@
/*
* Copyright 2016 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <i2c.h>
#include <fdt_support.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/fsl_serdes.h>
#include <asm/arch/fdt.h>
#include <asm/arch/soc.h>
#include <ahci.h>
#include <hwconfig.h>
#include <mmc.h>
#include <scsi.h>
#include <fm_eth.h>
#include <fsl_csu.h>
#include <fsl_esdhc.h>
#include <fsl_mmdc.h>
#include <spl.h>
#include <netdev.h>
#include "../common/qixis.h"
#include "ls1012aqds_qixis.h"
DECLARE_GLOBAL_DATA_PTR;
static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
{
int timeout = 1000;
out_be32(ptr, value);
while (in_be32(ptr) & bits) {
udelay(100);
timeout--;
}
if (timeout <= 0)
puts("Error: wait for clear timeout.\n");
}
int checkboard(void)
{
char buf[64];
u8 sw;
sw = QIXIS_READ(arch);
printf("Board Arch: V%d, ", sw >> 4);
printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
sw = QIXIS_READ(brdcfg[QIXIS_LBMAP_BRDCFG_REG]);
if (sw & QIXIS_LBMAP_ALTBANK)
printf("flash: 2\n");
else
printf("flash: 1\n");
printf("FPGA: v%d (%s), build %d",
(int)QIXIS_READ(scver), qixis_read_tag(buf),
(int)qixis_read_minor());
/* the timestamp string contains "\n" at the end */
printf(" on %s", qixis_read_time(buf));
return 0;
}
void mmdc_init(void)
{
struct mmdc_p_regs *mmdc =
(struct mmdc_p_regs *)CONFIG_SYS_FSL_DDR_ADDR;
out_be32(&mmdc->mdscr, CONFIGURATION_REQ);
/* configure timing parms */
out_be32(&mmdc->mdotc, CONFIG_SYS_MMDC_CORE_ODT_TIMING);
out_be32(&mmdc->mdcfg0, CONFIG_SYS_MMDC_CORE_TIMING_CFG_0);
out_be32(&mmdc->mdcfg1, CONFIG_SYS_MMDC_CORE_TIMING_CFG_1);
out_be32(&mmdc->mdcfg2, CONFIG_SYS_MMDC_CORE_TIMING_CFG_2);
/* other parms */
out_be32(&mmdc->mdmisc, CONFIG_SYS_MMDC_CORE_MISC);
out_be32(&mmdc->mpmur0, CONFIG_SYS_MMDC_PHY_MEASURE_UNIT);
out_be32(&mmdc->mdrwd, CONFIG_SYS_MMDC_CORE_RDWR_CMD_DELAY);
out_be32(&mmdc->mpodtctrl, CONFIG_SYS_MMDC_PHY_ODT_CTRL);
/* out of reset delays */
out_be32(&mmdc->mdor, CONFIG_SYS_MMDC_CORE_OUT_OF_RESET_DELAY);
/* physical parms */
out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_1);
out_be32(&mmdc->mdasp, CONFIG_SYS_MMDC_CORE_ADDR_PARTITION);
/* Enable MMDC */
out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_2);
/* dram init sequence: update MRs */
out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x8) | CONFIGURATION_REQ |
CMD_LOAD_MODE_REG | CMD_BANK_ADDR_2));
out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
CMD_BANK_ADDR_3));
out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1));
out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x19) |
CMD_ADDR_LSB_MR_ADDR(0x30) | CONFIGURATION_REQ |
CMD_LOAD_MODE_REG | CMD_BANK_ADDR_0));
/* dram init sequence: ZQCL */
out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
CMD_ZQ_CALIBRATION | CMD_BANK_ADDR_0));
set_wait_for_bits_clear(&mmdc->mpzqhwctrl,
CONFIG_SYS_MMDC_PHY_ZQ_HW_CTRL,
FORCE_ZQ_AUTO_CALIBRATION);
/* Calibrations now: wr lvl */
out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x84) |
CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
CMD_BANK_ADDR_1));
out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | WL_EN | CMD_NORMAL));
set_wait_for_bits_clear(&mmdc->mpwlgcr, WR_LVL_HW_EN, WR_LVL_HW_EN);
mdelay(1);
out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1));
out_be32(&mmdc->mdscr, CONFIGURATION_REQ);
mdelay(1);
/* Calibrations now: Read DQS gating calibration */
out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0));
out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3));
out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN);
out_be32(&mmdc->mprddlctl, CONFIG_SYS_MMDC_PHY_RD_DLY_LINES_CFG);
set_wait_for_bits_clear(&mmdc->mpdgctrl0,
AUTO_RD_DQS_GATING_CALIBRATION_EN,
AUTO_RD_DQS_GATING_CALIBRATION_EN);
out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
CMD_BANK_ADDR_3));
/* Calibrations now: Read calibration */
out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0));
out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3));
out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN);
set_wait_for_bits_clear(&mmdc->mprddlhwctl,
AUTO_RD_CALIBRATION_EN,
AUTO_RD_CALIBRATION_EN);
out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
CMD_BANK_ADDR_3));
/* PD, SR */
out_be32(&mmdc->mdpdc, CONFIG_SYS_MMDC_CORE_PWR_DOWN_CTRL);
out_be32(&mmdc->mapsr, CONFIG_SYS_MMDC_CORE_PWR_SAV_CTRL_STAT);
/* refresh scheme */
set_wait_for_bits_clear(&mmdc->mdref,
CONFIG_SYS_MMDC_CORE_REFRESH_CTL,
START_REFRESH);
/* disable CON_REQ */
out_be32(&mmdc->mdscr, DISABLE_CFG_REQ);
}
int dram_init(void)
{
mmdc_init();
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
return 0;
}
int board_early_init_f(void)
{
fsl_lsch2_early_init_f();
return 0;
}
#ifdef CONFIG_MISC_INIT_R
int misc_init_r(void)
{
u8 mux_sdhc_cd = 0x80;
i2c_set_bus_num(0);
i2c_write(CONFIG_SYS_I2C_FPGA_ADDR, 0x5a, 1, &mux_sdhc_cd, 1);
return 0;
}
#endif
int board_init(void)
{
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)
CONFIG_SYS_CCI400_ADDR;
/* Set CCI-400 control override register to enable barrier
* transaction */
out_le32(&cci->ctrl_ord,
CCI400_CTRLORD_EN_BARRIER);
#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
enable_layerscape_ns_access();
#endif
#ifdef CONFIG_ENV_IS_NOWHERE
gd->env_addr = (ulong)&default_environment[0];
#endif
return 0;
}
int board_eth_init(bd_t *bis)
{
return pci_eth_init(bis);
}
#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, bd_t *bd)
{
arch_fixup_fdt(blob);
ft_cpu_setup(blob, bd);
return 0;
}
#endif

35
board/freescale/ls1012aqds/ls1012aqds_qixis.h Normal file
View File

@@ -0,0 +1,35 @@
/*
* Copyright 2016 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __LS1043AQDS_QIXIS_H__
#define __LS1043AQDS_QIXIS_H__
/* Definitions of QIXIS Registers for LS1043AQDS */
/* BRDCFG4[4:7] select EC1 and EC2 as a pair */
#define BRDCFG4_EMISEL_MASK 0xe0
#define BRDCFG4_EMISEL_SHIFT 5
/* SYSCLK */
#define QIXIS_SYSCLK_66 0x0
#define QIXIS_SYSCLK_83 0x1
#define QIXIS_SYSCLK_100 0x2
#define QIXIS_SYSCLK_125 0x3
#define QIXIS_SYSCLK_133 0x4
/* DDRCLK */
#define QIXIS_DDRCLK_66 0x0
#define QIXIS_DDRCLK_100 0x1
#define QIXIS_DDRCLK_125 0x2
#define QIXIS_DDRCLK_133 0x3
/* BRDCFG2 - SD clock*/
#define QIXIS_SDCLK1_100 0x0
#define QIXIS_SDCLK1_125 0x1
#define QIXIS_SDCLK1_165 0x2
#define QIXIS_SDCLK1_100_SP 0x3
#endif

15
board/freescale/ls1012ardb/Kconfig Normal file
View File

@@ -0,0 +1,15 @@
if TARGET_LS1012ARDB
config SYS_BOARD
default "ls1012ardb"
config SYS_VENDOR
default "freescale"
config SYS_SOC
default "fsl-layerscape"
config SYS_CONFIG_NAME
default "ls1012ardb"
endif

6
board/freescale/ls1012ardb/MAINTAINERS Normal file
View File

@@ -0,0 +1,6 @@
LS1012ARDB BOARD
M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
S: Maintained
F: board/freescale/ls1012ardb/
F: include/configs/ls1012ardb.h
F: configs/ls1012ardb_qspi_defconfig

7
board/freescale/ls1012ardb/Makefile Normal file
View File

@@ -0,0 +1,7 @@
#
# Copyright 2016 Freescale Semiconductor, Inc.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += ls1012ardb.o

54
board/freescale/ls1012ardb/README Normal file
View File

@@ -0,0 +1,54 @@
Overview
--------
QorIQ LS1012A Reference Design System (LS1012ARDB) is a high-performance
development platform, with a complete debugging environment.
The LS1012ARDB board supports the QorIQ LS1012A processor and is
optimized to support the high-bandwidth DDR3L memory and
a full complement of high-speed SerDes ports.
LS1012A SoC Overview
--------------------
Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A
SoC overview.
LS1012ARDB board Overview
-----------------------
- SERDES Connections, 4 lanes supporting:
- PCI Express - 3.0
- SGMII, SGMII 2.5
- SATA 3.0
- DDR Controller
- 16-bit, 1 GB DDR3L SDRAM memory, running at data rates up to 1 GT/s
-QSPI: A dual 1:3 switch, NX3L4357GM,115 (U35) drives the QSPI chip-select
signals to
- QSPI NOR flash memory (2 virtual banks)
- the QSPI emulator.s
- USB 3.0
- one high-speed USB 2.0/3.0 port.
- Two enhanced secure digital host controllers:
- SDHC1 controller can be connected to onboard SDHC connector
- SDHC2 controller: Three dual 1:4 mux/demux devices,
74CBTLV3253DS (U30, U31, U33) drive the SDHC2 signals to eMMC,
SDIO WiFi, SPI, and Ardiuno shield
- 2 I2C controllers
- One SATA onboard connectors
- UART
- The LS1012A processor consists of two UART controllers,
out of which only UART1 is used on RDB.
- ARM JTAG support
Booting Options
---------------
a) QSPI Flash Emu Boot
b) QSPI Flash 1
c) QSPI Flash 2
QSPI flash map
--------------
Images | Size |QSPI Flash Address
------------------------------------------
RCW + PBI | 1MB | 0x4000_0000
U-boot | 1MB | 0x4010_0000
U-boot Env | 1MB | 0x4020_0000
PPA FIT image | 2MB | 0x4050_0000
Linux ITB | ~53MB | 0x40A0_0000

224
board/freescale/ls1012ardb/ls1012ardb.c Normal file
View File

@@ -0,0 +1,224 @@
/*
* Copyright 2016 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <i2c.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/fsl_serdes.h>
#include <asm/arch/soc.h>
#include <hwconfig.h>
#include <ahci.h>
#include <mmc.h>
#include <scsi.h>
#include <fsl_csu.h>
#include <fsl_esdhc.h>
#include <environment.h>
#include <fsl_mmdc.h>
#include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;
static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
{
int timeout = 1000;
out_be32(ptr, value);
while (in_be32(ptr) & bits) {
udelay(100);
timeout--;
}
if (timeout <= 0)
puts("Error: wait for clear timeout.\n");
}
int checkboard(void)
{
u8 in1;
puts("Board: LS1012ARDB ");
/* Initialize i2c early for Serial flash bank information */
i2c_set_bus_num(0);
if (i2c_read(I2C_MUX_IO1_ADDR, 1, 1, &in1, 1) < 0) {
printf("Error reading i2c boot information!\n");
return 0; /* Don't want to hang() on this error */
}
puts("Version");
if ((in1 & (~__SW_REV_MASK)) == __SW_REV_A)
puts(": RevA");
else if ((in1 & (~__SW_REV_MASK)) == __SW_REV_B)
puts(": RevB");
else
puts(": unknown");
printf(", boot from QSPI");
if ((in1 & (~__SW_BOOT_MASK)) == __SW_BOOT_EMU)
puts(": emu\n");
else if ((in1 & (~__SW_BOOT_MASK)) == __SW_BOOT_BANK1)
puts(": bank1\n");
else if ((in1 & (~__SW_BOOT_MASK)) == __SW_BOOT_BANK2)
puts(": bank2\n");
else
puts("unknown\n");
return 0;
}
void mmdc_init(void)
{
struct mmdc_p_regs *mmdc =
(struct mmdc_p_regs *)CONFIG_SYS_FSL_DDR_ADDR;
out_be32(&mmdc->mdscr, CONFIGURATION_REQ);
/* configure timing parms */
out_be32(&mmdc->mdotc, CONFIG_SYS_MMDC_CORE_ODT_TIMING);
out_be32(&mmdc->mdcfg0, CONFIG_SYS_MMDC_CORE_TIMING_CFG_0);
out_be32(&mmdc->mdcfg1, CONFIG_SYS_MMDC_CORE_TIMING_CFG_1);
out_be32(&mmdc->mdcfg2, CONFIG_SYS_MMDC_CORE_TIMING_CFG_2);
/* other parms */
out_be32(&mmdc->mdmisc, CONFIG_SYS_MMDC_CORE_MISC);
out_be32(&mmdc->mpmur0, CONFIG_SYS_MMDC_PHY_MEASURE_UNIT);
out_be32(&mmdc->mdrwd, CONFIG_SYS_MMDC_CORE_RDWR_CMD_DELAY);
out_be32(&mmdc->mpodtctrl, CONFIG_SYS_MMDC_PHY_ODT_CTRL);
/* out of reset delays */
out_be32(&mmdc->mdor, CONFIG_SYS_MMDC_CORE_OUT_OF_RESET_DELAY);
/* physical parms */
out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_1);
out_be32(&mmdc->mdasp, CONFIG_SYS_MMDC_CORE_ADDR_PARTITION);
/* Enable MMDC */
out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_2);
/* dram init sequence: update MRs */
out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x8) | CONFIGURATION_REQ |
CMD_LOAD_MODE_REG | CMD_BANK_ADDR_2));
out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
CMD_BANK_ADDR_3));
out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1));
out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x19) |
CMD_ADDR_LSB_MR_ADDR(0x30) | CONFIGURATION_REQ |
CMD_LOAD_MODE_REG | CMD_BANK_ADDR_0));
/* dram init sequence: ZQCL */
out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
CMD_ZQ_CALIBRATION | CMD_BANK_ADDR_0));
set_wait_for_bits_clear(&mmdc->mpzqhwctrl,
CONFIG_SYS_MMDC_PHY_ZQ_HW_CTRL,
FORCE_ZQ_AUTO_CALIBRATION);
/* Calibrations now: wr lvl */
out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x84) |
CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
CMD_BANK_ADDR_1));
out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | WL_EN | CMD_NORMAL));
set_wait_for_bits_clear(&mmdc->mpwlgcr, WR_LVL_HW_EN, WR_LVL_HW_EN);
mdelay(1);
out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1));
out_be32(&mmdc->mdscr, CONFIGURATION_REQ);
mdelay(1);
/* Calibrations now: Read DQS gating calibration */
out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0));
out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3));
out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN);
out_be32(&mmdc->mprddlctl, CONFIG_SYS_MMDC_PHY_RD_DLY_LINES_CFG);
set_wait_for_bits_clear(&mmdc->mpdgctrl0,
AUTO_RD_DQS_GATING_CALIBRATION_EN,
AUTO_RD_DQS_GATING_CALIBRATION_EN);
out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
CMD_BANK_ADDR_3));
/* Calibrations now: Read calibration */
out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0));
out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3));
out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN);
set_wait_for_bits_clear(&mmdc->mprddlhwctl,
AUTO_RD_CALIBRATION_EN,
AUTO_RD_CALIBRATION_EN);
out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
CMD_BANK_ADDR_3));
/* PD, SR */
out_be32(&mmdc->mdpdc, CONFIG_SYS_MMDC_CORE_PWR_DOWN_CTRL);
out_be32(&mmdc->mapsr, CONFIG_SYS_MMDC_CORE_PWR_SAV_CTRL_STAT);
/* refresh scheme */
set_wait_for_bits_clear(&mmdc->mdref,
CONFIG_SYS_MMDC_CORE_REFRESH_CTL,
START_REFRESH);
/* disable CON_REQ */
out_be32(&mmdc->mdscr, DISABLE_CFG_REQ);
}
int dram_init(void)
{
mmdc_init();
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
return 0;
}
int board_eth_init(bd_t *bis)
{
return pci_eth_init(bis);
}
int board_early_init_f(void)
{
fsl_lsch2_early_init_f();
return 0;
}
int board_init(void)
{
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
/*
* Set CCI-400 control override register to enable barrier
* transaction
*/
out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
#ifdef CONFIG_ENV_IS_NOWHERE
gd->env_addr = (ulong)&default_environment[0];
#endif
#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
enable_layerscape_ns_access();
#endif
return 0;
}
int ft_board_setup(void *blob, bd_t *bd)
{
arch_fixup_fdt(blob);
ft_cpu_setup(blob, bd);
return 0;
}

28
board/freescale/ls1021aqds/ddr.h
View File

@@ -31,21 +31,21 @@ static const struct board_specific_parameters udimm0[] = {
* ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay |
*/
#ifdef CONFIG_SYS_FSL_DDR4
{2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,},
{2, 1900, 0, 4, 6, 0x08080A0C, 0x0D0E0F0A,},
{1, 1666, 0, 4, 8, 0x090A0B0B, 0x0C0D0E0C,},
{1, 1900, 0, 4, 9, 0x0A0B0C0B, 0x0D0E0F0D,},
{1, 2200, 0, 4, 10, 0x0B0C0D0C, 0x0E0F110E,},
{2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,},
{2, 1900, 0, 8, 6, 0x08080A0C, 0x0D0E0F0A,},
{1, 1666, 0, 8, 8, 0x090A0B0B, 0x0C0D0E0C,},
{1, 1900, 0, 8, 9, 0x0A0B0C0B, 0x0D0E0F0D,},
{1, 2200, 0, 8, 10, 0x0B0C0D0C, 0x0E0F110E,},
#elif defined(CONFIG_SYS_FSL_DDR3)
{1, 833, 1, 6, 8, 0x06060607, 0x08080807, 0x1f, 2, 0},
{1, 1350, 1, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},
{1, 833, 2, 6, 8, 0x06060607, 0x08080807, 0x1f, 2, 0},
{1, 1350, 2, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},
{2, 833, 4, 6, 8, 0x06060607, 0x08080807, 0x1f, 2, 0},
{2, 1350, 4, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},
{2, 1350, 0, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},
{2, 1666, 4, 4, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0},
{2, 1666, 0, 4, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0},
{1, 833, 1, 12, 8, 0x06060607, 0x08080807, 0x1f, 2, 0},
{1, 1350, 1, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},
{1, 833, 2, 12, 8, 0x06060607, 0x08080807, 0x1f, 2, 0},
{1, 1350, 2, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},
{2, 833, 4, 12, 8, 0x06060607, 0x08080807, 0x1f, 2, 0},
{2, 1350, 4, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},
{2, 1350, 0, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},
{2, 1666, 4, 8, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0},
{2, 1666, 0, 8, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0},
#else
#error DDR type not defined
#endif

37
board/freescale/ls1043aqds/README
View File

@@ -8,41 +8,8 @@ debugging environment.
LS1043A SoC Overview
--------------------
The LS1043A integrated multicore processor combines four ARM Cortex-A53
processor cores with datapath acceleration optimized for L2/3 packet
processing, single pass security offload and robust traffic management
and quality of service.
The LS1043A SoC includes the following function and features:
- Four 64-bit ARM Cortex-A53 CPUs
- 1 MB unified L2 Cache
- One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving
support
- Data Path Acceleration Architecture (DPAA) incorporating acceleration the
the following functions:
- Packet parsing, classification, and distribution (FMan)
- Queue management for scheduling, packet sequencing, and congestion
management (QMan)
- Hardware buffer management for buffer allocation and de-allocation (BMan)
- Cryptography acceleration (SEC)
- Ethernet interfaces by FMan
- Up to 1 x XFI supporting 10G interface
- Up to 1 x QSGMII
- Up to 4 x SGMII supporting 1000Mbps
- Up to 2 x SGMII supporting 2500Mbps
- Up to 2 x RGMII supporting 1000Mbps
- High-speed peripheral interfaces
- Three PCIe 2.0 controllers, one supporting x4 operation
- One serial ATA (SATA 3.0) controllers
- Additional peripheral interfaces
- Three high-speed USB 3.0 controllers with integrated PHY
- Enhanced secure digital host controller (eSDXC/eMMC)
- Quad Serial Peripheral Interface (QSPI) Controller
- Serial peripheral interface (SPI) controller
- Four I2C controllers
- Two DUARTs
- Integrated flash controller supporting NAND and NOR flash
- QorIQ platform's trust architecture 2.1
Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1043A
SoC overview.
LS1043AQDS board Overview
-----------------------

28
board/freescale/ls1043aqds/ddr.h
View File

@@ -34,21 +34,21 @@ static const struct board_specific_parameters udimm0[] = {
* ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay |
*/
#ifdef CONFIG_SYS_FSL_DDR4
{2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,},
{2, 1900, 0, 4, 6, 0x08080A0C, 0x0D0E0F0A,},
{1, 1666, 0, 4, 6, 0x0708090B, 0x0C0D0E0A,},
{1, 1900, 0, 4, 9, 0x0A0B0C0B, 0x0D0E0F0D,},
{1, 2200, 0, 4, 10, 0x0B0C0D0C, 0x0E0F110E,},
{2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,},
{2, 1900, 0, 8, 6, 0x08080A0C, 0x0D0E0F0A,},
{1, 1666, 0, 8, 6, 0x0708090B, 0x0C0D0E0A,},
{1, 1900, 0, 8, 9, 0x0A0B0C0B, 0x0D0E0F0D,},
{1, 2200, 0, 8, 10, 0x0B0C0D0C, 0x0E0F110E,},
#elif defined(CONFIG_SYS_FSL_DDR3)
{1, 833, 1, 6, 8, 0x06060607, 0x08080807, 0x1f, 2, 0},
{1, 1350, 1, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},
{1, 833, 2, 6, 8, 0x06060607, 0x08080807, 0x1f, 2, 0},
{1, 1350, 2, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},
{2, 833, 4, 6, 8, 0x06060607, 0x08080807, 0x1f, 2, 0},
{2, 1350, 4, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},
{2, 1350, 0, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},
{2, 1666, 4, 4, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0},
{2, 1666, 0, 4, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0},
{1, 833, 1, 12, 8, 0x06060607, 0x08080807, 0x1f, 2, 0},
{1, 1350, 1, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},
{1, 833, 2, 12, 8, 0x06060607, 0x08080807, 0x1f, 2, 0},
{1, 1350, 2, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},
{2, 833, 4, 12, 8, 0x06060607, 0x08080807, 0x1f, 2, 0},
{2, 1350, 4, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},
{2, 1350, 0, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},
{2, 1666, 4, 8, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0},
{2, 1666, 0, 8, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0},
#else
#error DDR type not defined
#endif

4
board/freescale/ls1043aqds/ls1043aqds.c
View File

@@ -238,8 +238,8 @@ int board_early_init_f(void)
out_be32(&scfg->rcwpmuxcr0, 0x3333);
out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
usb_pwrfault =
(SCFG_USBPWRFAULT_SHARED << SCFG_USBPWRFAULT_USB3_SHIFT) |
(SCFG_USBPWRFAULT_SHARED << SCFG_USBPWRFAULT_USB2_SHIFT) |
(SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB3_SHIFT) |
(SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB2_SHIFT) |
(SCFG_USBPWRFAULT_SHARED << SCFG_USBPWRFAULT_USB1_SHIFT);
out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
#endif

37
board/freescale/ls1043ardb/README
View File

@@ -8,41 +8,8 @@ debugging environment. The LS1043A RDB is lead-free and RoHS-compliant.
LS1043A SoC Overview
--------------------
The LS1043A integrated multicore processor combines four ARM Cortex-A53
processor cores with datapath acceleration optimized for L2/3 packet
processing, single pass security offload and robust traffic management
and quality of service.
The LS1043A SoC includes the following function and features:
- Four 64-bit ARM Cortex-A53 CPUs
- 1 MB unified L2 Cache
- One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving
support
- Data Path Acceleration Architecture (DPAA) incorporating acceleration the
the following functions:
- Packet parsing, classification, and distribution (FMan)
- Queue management for scheduling, packet sequencing, and congestion
management (QMan)
- Hardware buffer management for buffer allocation and de-allocation (BMan)
- Cryptography acceleration (SEC)
- Ethernet interfaces by FMan
- Up to 1 x XFI supporting 10G interface
- Up to 1 x QSGMII
- Up to 4 x SGMII supporting 1000Mbps
- Up to 2 x SGMII supporting 2500Mbps
- Up to 2 x RGMII supporting 1000Mbps
- High-speed peripheral interfaces
- Three PCIe 2.0 controllers, one supporting x4 operation
- One serial ATA (SATA 3.0) controllers
- Additional peripheral interfaces
- Three high-speed USB 3.0 controllers with integrated PHY
- Enhanced secure digital host controller (eSDXC/eMMC)
- Quad Serial Peripheral Interface (QSPI) Controller
- Serial peripheral interface (SPI) controller
- Four I2C controllers
- Two DUARTs
- Integrated flash controller supporting NAND and NOR flash
- QorIQ platform's trust architecture 2.1
Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1043A
SoC overview.
LS1043ARDB board Overview
-----------------------

6
board/freescale/ls1043ardb/ddr.h
View File

@@ -34,9 +34,9 @@ static const struct board_specific_parameters udimm0[] = {
* ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay |
*/
#ifdef CONFIG_SYS_FSL_DDR4
{1, 1666, 0, 6, 7, 0x07090800, 0x00000000,},
{1, 1900, 0, 6, 7, 0x07090800, 0x00000000,},
{1, 2200, 0, 6, 7, 0x07090800, 0x00000000,},
{1, 1666, 0, 12, 7, 0x07090800, 0x00000000,},
{1, 1900, 0, 12, 7, 0x07090800, 0x00000000,},
{1, 2200, 0, 12, 7, 0x07090800, 0x00000000,},
#endif
{}
};

45
board/freescale/ls2080aqds/README
View File

@@ -7,48 +7,9 @@ SW development platform for the Freescale LS2080A processor series, with
a complete debugging environment.
LS2080A SoC Overview
------------------
The LS2080A integrated multicore processor combines eight ARM Cortex-A57
processor cores with high-performance data path acceleration logic and network
and peripheral bus interfaces required for networking, telecom/datacom,
wireless infrastructure, and mil/aerospace applications.
The LS2080A SoC includes the following function and features:
- Eight 64-bit ARM Cortex-A57 CPUs
- 1 MB platform cache with ECC
- Two 64-bit DDR4 SDRAM memory controllers with ECC and interleaving support
- One secondary 32-bit DDR4 SDRAM memory controller, intended for use by
the AIOP
- Data path acceleration architecture (DPAA2) incorporating acceleration for
the following functions:
- Packet parsing, classification, and distribution (WRIOP)
- Queue and Hardware buffer management for scheduling, packet sequencing, and
congestion management, buffer allocation and de-allocation (QBMan)
- Cryptography acceleration (SEC) at up to 10 Gbps
- RegEx pattern matching acceleration (PME) at up to 10 Gbps
- Decompression/compression acceleration (DCE) at up to 20 Gbps
- Accelerated I/O processing (AIOP) at up to 20 Gbps
- QDMA engine
- 16 SerDes lanes at up to 10.3125 GHz
- Ethernet interfaces
- Up to eight 10 Gbps Ethernet MACs
- Up to eight 1 / 2.5 Gbps Ethernet MACs
- High-speed peripheral interfaces
- Four PCIe 3.0 controllers, one supporting SR-IOV
- Additional peripheral interfaces
- Two serial ATA (SATA 3.0) controllers
- Two high-speed USB 3.0 controllers with integrated PHY
- Enhanced secure digital host controller (eSDXC/eMMC)
- Serial peripheral interface (SPI) controller
- Quad Serial Peripheral Interface (QSPI) Controller
- Four I2C controllers
- Two DUARTs
- Integrated flash controller (IFC 2.0) supporting NAND and NOR flash
- Support for hardware virtualization and partitioning enforcement
- QorIQ platform's trust architecture 3.0
- Service processor (SP) provides pre-boot initialization and secure-boot
capabilities
--------------------
Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A
SoC overview.
LS2080AQDS board Overview
-----------------------

32
board/freescale/ls2080aqds/ddr.h
View File

@@ -28,10 +28,10 @@ static const struct board_specific_parameters udimm0[] = {
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl
* ranks| mhz| GB |adjst| start | ctl2 | ctl3
*/
{2, 1350, 0, 4, 6, 0x0708090B, 0x0C0D0E09,},
{2, 1666, 0, 4, 7, 0x08090A0C, 0x0D0F100B,},
{2, 1900, 0, 4, 7, 0x09090B0D, 0x0E10120B,},
{2, 2300, 0, 4, 8, 0x090A0C0F, 0x1012130C,},
{2, 1350, 0, 8, 6, 0x0708090B, 0x0C0D0E09,},
{2, 1666, 0, 8, 7, 0x08090A0C, 0x0D0F100B,},
{2, 1900, 0, 8, 7, 0x09090B0D, 0x0E10120B,},
{2, 2300, 0, 8, 8, 0x090A0C0F, 0x1012130C,},
{}
};
@@ -42,10 +42,10 @@ static const struct board_specific_parameters udimm2[] = {
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl
* ranks| mhz| GB |adjst| start | ctl2 | ctl3
*/
{2, 1350, 0, 4, 0xd, 0x0C0A0A00, 0x00000009,},
{2, 1666, 0, 4, 0xd, 0x0C0A0A00, 0x00000009,},
{2, 1900, 0, 4, 0xe, 0x0D0C0B00, 0x0000000A,},
{2, 2200, 0, 4, 0xe, 0x0D0C0B00, 0x0000000A,},
{2, 1350, 0, 8, 0xd, 0x0C0A0A00, 0x00000009,},
{2, 1666, 0, 8, 0xd, 0x0C0A0A00, 0x00000009,},
{2, 1900, 0, 8, 0xe, 0x0D0C0B00, 0x0000000A,},
{2, 2200, 0, 8, 0xe, 0x0D0C0B00, 0x0000000A,},
{}
};
@@ -55,10 +55,10 @@ static const struct board_specific_parameters rdimm0[] = {
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl
* ranks| mhz| GB |adjst| start | ctl2 | ctl3
*/
{2, 1350, 0, 4, 6, 0x0708090B, 0x0C0D0E09,},
{2, 1666, 0, 4, 7, 0x08090A0C, 0x0D0F100B,},
{2, 1900, 0, 4, 7, 0x09090B0D, 0x0E10120B,},
{2, 2200, 0, 4, 8, 0x090A0C0F, 0x1012130C,},
{2, 1350, 0, 8, 6, 0x0708090B, 0x0C0D0E09,},
{2, 1666, 0, 8, 7, 0x08090A0C, 0x0D0F100B,},
{2, 1900, 0, 8, 7, 0x09090B0D, 0x0E10120B,},
{2, 2200, 0, 8, 8, 0x090A0C0F, 0x1012130C,},
{}
};
@@ -69,10 +69,10 @@ static const struct board_specific_parameters rdimm2[] = {
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl
* ranks| mhz| GB |adjst| start | ctl2 | ctl3
*/
{2, 1350, 0, 4, 6, 0x0708090B, 0x0C0D0E09,},
{2, 1666, 0, 4, 7, 0x0B0A090C, 0x0D0F100B,},
{2, 1900, 0, 4, 7, 0x09090B0D, 0x0E10120B,},
{2, 2200, 0, 4, 8, 0x090A0C0F, 0x1012130C,},
{2, 1350, 0, 8, 6, 0x0708090B, 0x0C0D0E09,},
{2, 1666, 0, 8, 7, 0x0B0A090C, 0x0D0F100B,},
{2, 1900, 0, 8, 7, 0x09090B0D, 0x0E10120B,},
{2, 2200, 0, 8, 8, 0x090A0C0F, 0x1012130C,},
{}
};

2
board/freescale/ls2080aqds/ls2080aqds.c
View File

@@ -282,7 +282,9 @@ void fdt_fixup_board_enet(void *fdt)
#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, bd_t *bd)
{
#ifdef CONFIG_FSL_MC_ENET
int err;
#endif
u64 base[CONFIG_NR_DRAM_BANKS];
u64 size[CONFIG_NR_DRAM_BANKS];

45
board/freescale/ls2080ardb/README
View File

@@ -5,48 +5,9 @@ evaluation, and development platform that supports the QorIQ LS2080A
Layerscape Architecture processor.
LS2080A SoC Overview
------------------
The LS2080A integrated multicore processor combines eight ARM Cortex-A57
processor cores with high-performance data path acceleration logic and network
and peripheral bus interfaces required for networking, telecom/datacom,
wireless infrastructure, and mil/aerospace applications.
The LS2080A SoC includes the following function and features:
- Eight 64-bit ARM Cortex-A57 CPUs
- 1 MB platform cache with ECC
- Two 64-bit DDR4 SDRAM memory controllers with ECC and interleaving support
- One secondary 32-bit DDR4 SDRAM memory controller, intended for use by
the AIOP
- Data path acceleration architecture (DPAA2) incorporating acceleration for
the following functions:
- Packet parsing, classification, and distribution (WRIOP)
- Queue and Hardware buffer management for scheduling, packet sequencing, and
congestion management, buffer allocation and de-allocation (QBMan)
- Cryptography acceleration (SEC) at up to 10 Gbps
- RegEx pattern matching acceleration (PME) at up to 10 Gbps
- Decompression/compression acceleration (DCE) at up to 20 Gbps
- Accelerated I/O processing (AIOP) at up to 20 Gbps
- QDMA engine
- 16 SerDes lanes at up to 10.3125 GHz
- Ethernet interfaces
- Up to eight 10 Gbps Ethernet MACs
- Up to eight 1 / 2.5 Gbps Ethernet MACs
- High-speed peripheral interfaces
- Four PCIe 3.0 controllers, one supporting SR-IOV
- Additional peripheral interfaces
- Two serial ATA (SATA 3.0) controllers
- Two high-speed USB 3.0 controllers with integrated PHY
- Enhanced secure digital host controller (eSDXC/eMMC)
- Serial peripheral interface (SPI) controller
- Quad Serial Peripheral Interface (QSPI) Controller
- Four I2C controllers
- Two DUARTs
- Integrated flash controller (IFC 2.0) supporting NAND and NOR flash
- Support for hardware virtualization and partitioning enforcement
- QorIQ platform's trust architecture 3.0
- Service processor (SP) provides pre-boot initialization and secure-boot
capabilities
--------------------
Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A
SoC overview.
LS2080ARDB board Overview
-----------------------

32
board/freescale/ls2080ardb/ddr.h
View File

@@ -28,10 +28,10 @@ static const struct board_specific_parameters udimm0[] = {
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl
* ranks| mhz| GB |adjst| start | ctl2 | ctl3
*/
{2, 1350, 0, 4, 6, 0x0708090B, 0x0C0D0E09,},
{2, 1666, 0, 5, 9, 0x090A0B0E, 0x0F11110C,},
{2, 1900, 0, 6, 0xA, 0x0B0C0E11, 0x1214140F,},
{2, 2300, 0, 6, 0xB, 0x0C0D0F12, 0x14161610,},
{2, 1350, 0, 8, 6, 0x0708090B, 0x0C0D0E09,},
{2, 1666, 0, 10, 9, 0x090A0B0E, 0x0F11110C,},
{2, 1900, 0, 12, 0xA, 0x0B0C0E11, 0x1214140F,},
{2, 2300, 0, 12, 0xB, 0x0C0D0F12, 0x14161610,},
{}
};
@@ -42,10 +42,10 @@ static const struct board_specific_parameters udimm2[] = {
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl
* ranks| mhz| GB |adjst| start | ctl2 | ctl3
*/
{2, 1350, 0, 4, 0xd, 0x0C0A0A00, 0x00000009,},
{2, 1666, 0, 4, 0xd, 0x0C0A0A00, 0x00000009,},
{2, 1900, 0, 4, 0xe, 0x0D0C0B00, 0x0000000A,},
{2, 2200, 0, 4, 0xe, 0x0D0C0B00, 0x0000000A,},
{2, 1350, 0, 8, 0xd, 0x0C0A0A00, 0x00000009,},
{2, 1666, 0, 8, 0xd, 0x0C0A0A00, 0x00000009,},
{2, 1900, 0, 8, 0xe, 0x0D0C0B00, 0x0000000A,},
{2, 2200, 0, 8, 0xe, 0x0D0C0B00, 0x0000000A,},
{}
};
@@ -55,10 +55,10 @@ static const struct board_specific_parameters rdimm0[] = {
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl
* ranks| mhz| GB |adjst| start | ctl2 | ctl3
*/
{2, 1350, 0, 4, 6, 0x0708090B, 0x0C0D0E09,},
{2, 1666, 0, 4, 7, 0x08090A0C, 0x0D0F100B,},
{2, 1900, 0, 4, 7, 0x09090B0D, 0x0E10120B,},
{2, 2200, 0, 4, 8, 0x090A0C0F, 0x1012130C,},
{2, 1350, 0, 8, 6, 0x0708090B, 0x0C0D0E09,},
{2, 1666, 0, 8, 7, 0x08090A0C, 0x0D0F100B,},
{2, 1900, 0, 8, 7, 0x09090B0D, 0x0E10120B,},
{2, 2200, 0, 8, 8, 0x090A0C0F, 0x1012130C,},
{}
};
@@ -69,10 +69,10 @@ static const struct board_specific_parameters rdimm2[] = {
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl
* ranks| mhz| GB |adjst| start | ctl2 | ctl3
*/
{2, 1350, 0, 4, 6, 0x0708090B, 0x0C0D0E09,},
{2, 1666, 0, 4, 7, 0x0B0A090C, 0x0D0F100B,},
{2, 1900, 0, 4, 7, 0x09090B0D, 0x0E10120B,},
{2, 2200, 0, 4, 8, 0x090A0C0F, 0x1012130C,},
{2, 1350, 0, 8, 6, 0x0708090B, 0x0C0D0E09,},
{2, 1666, 0, 8, 7, 0x0B0A090C, 0x0D0F100B,},
{2, 1900, 0, 8, 7, 0x09090B0D, 0x0E10120B,},
{2, 2200, 0, 8, 8, 0x090A0C0F, 0x1012130C,},
{}
};

6
board/freescale/ls2080ardb/ls2080ardb.c
View File

@@ -156,7 +156,9 @@ int board_init(void)
{
char *env_hwconfig;
u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
#ifdef CONFIG_FSL_MC_ENET
u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
#endif
u32 val;
init_final_memctl_regs();
@@ -178,8 +180,10 @@ int board_init(void)
QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN);
#ifdef CONFIG_FSL_MC_ENET
/* invert AQR405 IRQ pins polarity */
out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK);
#endif
return 0;
}
@@ -261,7 +265,9 @@ void fdt_fixup_board_enet(void *fdt)
#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, bd_t *bd)
{
#ifdef CONFIG_FSL_MC_ENET
int err;
#endif
u64 base[CONFIG_NR_DRAM_BANKS];
u64 size[CONFIG_NR_DRAM_BANKS];

22
board/freescale/t102xqds/ddr.c
View File

@@ -35,18 +35,18 @@ static const struct board_specific_parameters udimm0[] = {
* ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
*/
#if defined(CONFIG_SYS_FSL_DDR4)
{2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,},
{2, 1900, 0, 4, 6, 0x08080A0C, 0x0D0E0F0A,},
{1, 1666, 0, 4, 6, 0x0708090B, 0x0C0D0E09,},
{1, 1900, 0, 4, 6, 0x08080A0C, 0x0D0E0F0A,},
{1, 2200, 0, 4, 7, 0x08090A0D, 0x0F0F100C,},
{2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,},
{2, 1900, 0, 8, 6, 0x08080A0C, 0x0D0E0F0A,},
{1, 1666, 0, 8, 6, 0x0708090B, 0x0C0D0E09,},
{1, 1900, 0, 8, 6, 0x08080A0C, 0x0D0E0F0A,},
{1, 2200, 0, 8, 7, 0x08090A0D, 0x0F0F100C,},
#elif defined(CONFIG_SYS_FSL_DDR3)
{2, 833, 0, 4, 6, 0x06060607, 0x08080807,},
{2, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09,},
{2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,},
{1, 833, 0, 4, 6, 0x06060607, 0x08080807,},
{1, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09,},
{1, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,},
{2, 833, 0, 8, 6, 0x06060607, 0x08080807,},
{2, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09,},
{2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,},
{1, 833, 0, 8, 6, 0x06060607, 0x08080807,},
{1, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09,},
{1, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,},
#else
#error DDR type not defined
#endif

12
board/freescale/t102xrdb/ddr.c
View File

@@ -34,12 +34,12 @@ static const struct board_specific_parameters udimm0[] = {
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl |
* ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
*/
{2, 833, 0, 4, 6, 0x06060607, 0x08080807,},
{2, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09,},
{2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,},
{1, 833, 0, 4, 6, 0x06060607, 0x08080807,},
{1, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09,},
{1, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,},
{2, 833, 0, 8, 6, 0x06060607, 0x08080807,},
{2, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09,},
{2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,},
{1, 833, 0, 8, 6, 0x06060607, 0x08080807,},
{1, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09,},
{1, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,},
{}
};

22
board/freescale/t1040qds/ddr.h
View File

@@ -29,18 +29,18 @@ static const struct board_specific_parameters udimm0[] = {
* ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
*/
#ifdef CONFIG_SYS_FSL_DDR4
{2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,},
{2, 1900, 0, 4, 6, 0x08080A0C, 0x0D0E0F0A,},
{1, 1666, 0, 4, 6, 0x0708090B, 0x0C0D0E09,},
{1, 1900, 0, 4, 6, 0x08080A0C, 0x0D0E0F0A,},
{1, 2200, 0, 4, 7, 0x08090A0D, 0x0F0F100C,},
{2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,},
{2, 1900, 0, 8, 6, 0x08080A0C, 0x0D0E0F0A,},
{1, 1666, 0, 8, 6, 0x0708090B, 0x0C0D0E09,},
{1, 1900, 0, 8, 6, 0x08080A0C, 0x0D0E0F0A,},
{1, 2200, 0, 8, 7, 0x08090A0D, 0x0F0F100C,},
#elif defined(CONFIG_SYS_FSL_DDR3)
{2, 833, 0, 4, 6, 0x06060607, 0x08080807,},
{2, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09,},
{2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,},
{1, 833, 0, 4, 6, 0x06060607, 0x08080807,},
{1, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09,},
{1, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,},
{2, 833, 0, 8, 6, 0x06060607, 0x08080807,},
{2, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09,},
{2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,},
{1, 833, 0, 8, 6, 0x06060607, 0x08080807,},
{1, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09,},
{1, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,},
#else
#error DDR type not defined
#endif

26
board/freescale/t104xrdb/ddr.h
View File

@@ -29,20 +29,20 @@ static const struct board_specific_parameters udimm0[] = {
* ranks| mhz| GB |adjst| start | ctl2
*/
#ifdef CONFIG_SYS_FSL_DDR4
{2, 1600, 4, 4, 6, 0x07090A0c, 0x0e0f100a},
{2, 1600, 4, 8, 6, 0x07090A0c, 0x0e0f100a},
#elif defined(CONFIG_SYS_FSL_DDR3)
{2, 833, 4, 4, 6, 0x06060607, 0x08080807},
{2, 833, 0, 4, 6, 0x06060607, 0x08080807},
{2, 1350, 4, 4, 7, 0x0708080A, 0x0A0B0C09},
{2, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09},
{2, 1666, 4, 4, 7, 0x0808090B, 0x0C0D0E0A},
{2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A},
{1, 833, 4, 4, 6, 0x06060607, 0x08080807},
{1, 833, 0, 4, 6, 0x06060607, 0x08080807},
{1, 1350, 4, 4, 7, 0x0708080A, 0x0A0B0C09},
{1, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09},
{1, 1666, 4, 4, 7, 0x0808090B, 0x0C0D0E0A},
{1, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A},
{2, 833, 4, 8, 6, 0x06060607, 0x08080807},
{2, 833, 0, 8, 6, 0x06060607, 0x08080807},
{2, 1350, 4, 8, 7, 0x0708080A, 0x0A0B0C09},
{2, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09},
{2, 1666, 4, 8, 7, 0x0808090B, 0x0C0D0E0A},
{2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A},
{1, 833, 4, 8, 6, 0x06060607, 0x08080807},
{1, 833, 0, 8, 6, 0x06060607, 0x08080807},
{1, 1350, 4, 8, 7, 0x0708080A, 0x0A0B0C09},
{1, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09},
{1, 1666, 4, 8, 7, 0x0808090B, 0x0C0D0E0A},
{1, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A},
#else
#error DDR type not defined
#endif

40
board/freescale/t208xqds/ddr.h
View File

@@ -28,17 +28,17 @@ static const struct board_specific_parameters udimm0[] = {
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl |
* ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
*/
{2, 1200, 0, 5, 7, 0x0708090a, 0x0b0c0d09},
{2, 1400, 0, 5, 7, 0x08090a0c, 0x0d0e0f0a},
{2, 1700, 0, 5, 8, 0x090a0b0c, 0x0e10110c},
{2, 1900, 0, 5, 8, 0x090b0c0f, 0x1012130d},
{2, 2140, 0, 5, 8, 0x090b0c0f, 0x1012130d},
{1, 1200, 0, 5, 7, 0x0808090a, 0x0b0c0c0a},
{1, 1500, 0, 5, 6, 0x07070809, 0x0a0b0b09},
{1, 1600, 0, 5, 8, 0x090b0b0d, 0x0d0e0f0b},
{1, 1700, 0, 4, 8, 0x080a0a0c, 0x0c0d0e0a},
{1, 1900, 0, 5, 8, 0x090a0c0d, 0x0e0f110c},
{1, 2140, 0, 4, 8, 0x090a0b0d, 0x0e0f110b},
{2, 1200, 0, 10, 7, 0x0708090a, 0x0b0c0d09},
{2, 1400, 0, 10, 7, 0x08090a0c, 0x0d0e0f0a},
{2, 1700, 0, 10, 8, 0x090a0b0c, 0x0e10110c},
{2, 1900, 0, 10, 8, 0x090b0c0f, 0x1012130d},
{2, 2140, 0, 10, 8, 0x090b0c0f, 0x1012130d},
{1, 1200, 0, 10, 7, 0x0808090a, 0x0b0c0c0a},
{1, 1500, 0, 10, 6, 0x07070809, 0x0a0b0b09},
{1, 1600, 0, 10, 8, 0x090b0b0d, 0x0d0e0f0b},
{1, 1700, 0, 8, 8, 0x080a0a0c, 0x0c0d0e0a},
{1, 1900, 0, 10, 8, 0x090a0c0d, 0x0e0f110c},
{1, 2140, 0, 8, 8, 0x090a0b0d, 0x0e0f110b},
{}
};
@@ -49,15 +49,15 @@ static const struct board_specific_parameters rdimm0[] = {
* ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
*/
/* TODO: need tuning these parameters if RDIMM is used */
{4, 1350, 0, 5, 9, 0x08070605, 0x06070806},
{4, 1666, 0, 5, 11, 0x0a080706, 0x07090906},
{4, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07},
{2, 1350, 0, 5, 9, 0x08070605, 0x06070806},
{2, 1666, 0, 5, 11, 0x0a090806, 0x08090a06},
{2, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07},
{1, 1350, 0, 5, 9, 0x08070605, 0x06070806},
{1, 1666, 0, 5, 11, 0x0a090806, 0x08090a06},
{1, 2140, 0, 4, 12, 0x0b090807, 0x080a0b07},
{4, 1350, 0, 10, 9, 0x08070605, 0x06070806},
{4, 1666, 0, 10, 11, 0x0a080706, 0x07090906},
{4, 2140, 0, 10, 12, 0x0b090807, 0x080a0b07},
{2, 1350, 0, 10, 9, 0x08070605, 0x06070806},
{2, 1666, 0, 10, 11, 0x0a090806, 0x08090a06},
{2, 2140, 0, 10, 12, 0x0b090807, 0x080a0b07},
{1, 1350, 0, 10, 9, 0x08070605, 0x06070806},
{1, 1666, 0, 10, 11, 0x0a090806, 0x08090a06},
{1, 2140, 0, 8, 12, 0x0b090807, 0x080a0b07},
{}
};

20
board/freescale/t208xrdb/ddr.h
View File

@@ -28,16 +28,16 @@ static const struct board_specific_parameters udimm0[] = {
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl |
* ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
*/
{2, 1200, 2, 5, 7, 0x0808090a, 0x0b0c0c0a},
{2, 1500, 2, 5, 6, 0x07070809, 0x0a0b0b09},
{2, 1600, 2, 5, 8, 0x0808070b, 0x0c0d0e0a},
{2, 1700, 2, 4, 7, 0x080a0a0c, 0x0c0d0e0a},
{2, 1900, 0, 5, 7, 0x0808080c, 0x0b0c0c09},
{1, 1200, 2, 5, 7, 0x0808090a, 0x0b0c0c0a},
{1, 1500, 2, 5, 6, 0x07070809, 0x0a0b0b09},
{1, 1600, 2, 5, 8, 0x0808070b, 0x0c0d0e0a},
{1, 1700, 2, 4, 7, 0x080a0a0c, 0x0c0d0e0a},
{1, 1900, 0, 5, 7, 0x0808080c, 0x0b0c0c09},
{2, 1200, 2, 10, 7, 0x0808090a, 0x0b0c0c0a},
{2, 1500, 2, 10, 6, 0x07070809, 0x0a0b0b09},
{2, 1600, 2, 10, 8, 0x0808070b, 0x0c0d0e0a},
{2, 1700, 2, 8, 7, 0x080a0a0c, 0x0c0d0e0a},
{2, 1900, 0, 10, 7, 0x0808080c, 0x0b0c0c09},
{1, 1200, 2, 10, 7, 0x0808090a, 0x0b0c0c0a},
{1, 1500, 2, 10, 6, 0x07070809, 0x0a0b0b09},
{1, 1600, 2, 10, 8, 0x0808070b, 0x0c0d0e0a},
{1, 1700, 2, 8, 7, 0x080a0a0c, 0x0c0d0e0a},
{1, 1900, 0, 10, 7, 0x0808080c, 0x0b0c0c09},
{}
};

38
board/freescale/t4qds/ddr.h
View File

@@ -31,16 +31,16 @@ static const struct board_specific_parameters udimm0[] = {
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
* ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay |
*/
{2, 1350, 4, 4, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0},
{2, 1350, 0, 5, 7, 0x0709090b, 0x0c0c0d09, 0xff, 2, 0},
{2, 1666, 4, 4, 8, 0x080a0a0d, 0x0d10100b, 0xff, 2, 0},
{2, 1666, 0, 5, 7, 0x080a0a0c, 0x0d0d0e0a, 0xff, 2, 0},
{2, 1900, 0, 4, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0},
{2, 2140, 0, 4, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0},
{1, 1350, 0, 5, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0},
{1, 1700, 0, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0},
{1, 1900, 0, 4, 8, 0x080a0a0c, 0x0e0e0f0a, 0xff, 2, 0},
{1, 2140, 0, 4, 8, 0x090a0b0c, 0x0e0f100b, 0xff, 2, 0},
{2, 1350, 4, 8, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0},
{2, 1350, 0, 10, 7, 0x0709090b, 0x0c0c0d09, 0xff, 2, 0},
{2, 1666, 4, 8, 8, 0x080a0a0d, 0x0d10100b, 0xff, 2, 0},
{2, 1666, 0, 10, 7, 0x080a0a0c, 0x0d0d0e0a, 0xff, 2, 0},
{2, 1900, 0, 8, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0},
{2, 2140, 0, 8, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0},
{1, 1350, 0, 10, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0},
{1, 1700, 0, 10, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0},
{1, 1900, 0, 8, 8, 0x080a0a0c, 0x0e0e0f0a, 0xff, 2, 0},
{1, 2140, 0, 8, 8, 0x090a0b0c, 0x0e0f100b, 0xff, 2, 0},
{}
};
@@ -50,15 +50,15 @@ static const struct board_specific_parameters rdimm0[] = {
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
* ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay |
*/
{4, 1350, 0, 5, 9, 0x08070605, 0x06070806, 0xff, 2, 0},
{4, 1666, 0, 5, 11, 0x0a080706, 0x07090906, 0xff, 2, 0},
{4, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0},
{2, 1350, 0, 5, 9, 0x08070605, 0x06070806, 0xff, 2, 0},
{2, 1666, 0, 5, 11, 0x0a090806, 0x08090a06, 0xff, 2, 0},
{2, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0},
{1, 1350, 0, 5, 9, 0x08070605, 0x06070806, 0xff, 2, 0},
{1, 1666, 0, 5, 11, 0x0a090806, 0x08090a06, 0xff, 2, 0},
{1, 2140, 0, 4, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0},
{4, 1350, 0, 10, 9, 0x08070605, 0x06070806, 0xff, 2, 0},
{4, 1666, 0, 10, 11, 0x0a080706, 0x07090906, 0xff, 2, 0},
{4, 2140, 0, 10, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0},
{2, 1350, 0, 10, 9, 0x08070605, 0x06070806, 0xff, 2, 0},
{2, 1666, 0, 10, 11, 0x0a090806, 0x08090a06, 0xff, 2, 0},
{2, 2140, 0, 10, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0},
{1, 1350, 0, 10, 9, 0x08070605, 0x06070806, 0xff, 2, 0},
{1, 1666, 0, 10, 11, 0x0a090806, 0x08090a06, 0xff, 2, 0},
{1, 2140, 0, 8, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0},
{}
};

38
board/freescale/t4rdb/ddr.h
View File

@@ -27,16 +27,16 @@ static const struct board_specific_parameters udimm0[] = {
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl
* ranks| mhz| GB |adjst| start | ctl2 | ctl3
*/
{2, 1350, 4, 4, 8, 0x0809090b, 0x0c0c0d0a},
{2, 1350, 0, 5, 7, 0x0709090b, 0x0c0c0d09},
{2, 1666, 4, 4, 8, 0x080a0a0d, 0x0d10100b},
{2, 1666, 0, 5, 7, 0x080a0a0c, 0x0d0d0e0a},
{2, 1900, 0, 4, 8, 0x090a0b0e, 0x0f11120c},
{2, 2140, 0, 4, 8, 0x090a0b0e, 0x0f11120c},
{1, 1350, 0, 5, 8, 0x0809090b, 0x0c0c0d0a},
{1, 1700, 0, 5, 8, 0x080a0a0c, 0x0c0d0e0a},
{1, 1900, 0, 4, 8, 0x080a0a0c, 0x0e0e0f0a},
{1, 2140, 0, 4, 8, 0x090a0b0c, 0x0e0f100b},
{2, 1350, 4, 8, 8, 0x0809090b, 0x0c0c0d0a},
{2, 1350, 0, 10, 7, 0x0709090b, 0x0c0c0d09},
{2, 1666, 4, 8, 8, 0x080a0a0d, 0x0d10100b},
{2, 1666, 0, 10, 7, 0x080a0a0c, 0x0d0d0e0a},
{2, 1900, 0, 8, 8, 0x090a0b0e, 0x0f11120c},
{2, 2140, 0, 8, 8, 0x090a0b0e, 0x0f11120c},
{1, 1350, 0, 10, 8, 0x0809090b, 0x0c0c0d0a},
{1, 1700, 0, 10, 8, 0x080a0a0c, 0x0c0d0e0a},
{1, 1900, 0, 8, 8, 0x080a0a0c, 0x0e0e0f0a},
{1, 2140, 0, 8, 8, 0x090a0b0c, 0x0e0f100b},
{}
};
@@ -46,15 +46,15 @@ static const struct board_specific_parameters rdimm0[] = {
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl
* ranks| mhz| GB |adjst| start | ctl2 | ctl3
*/
{4, 1350, 0, 5, 9, 0x08070605, 0x06070806},
{4, 1666, 0, 5, 11, 0x0a080706, 0x07090906},
{4, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07},
{2, 1350, 0, 5, 9, 0x08070605, 0x06070806},
{2, 1666, 0, 5, 11, 0x0a090806, 0x08090a06},
{2, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07},
{1, 1350, 0, 5, 9, 0x08070605, 0x06070806},
{1, 1666, 0, 5, 11, 0x0a090806, 0x08090a06},
{1, 2140, 0, 4, 12, 0x0b090807, 0x080a0b07},
{4, 1350, 0, 10, 9, 0x08070605, 0x06070806},
{4, 1666, 0, 10, 11, 0x0a080706, 0x07090906},
{4, 2140, 0, 10, 12, 0x0b090807, 0x080a0b07},
{2, 1350, 0, 10, 9, 0x08070605, 0x06070806},
{2, 1666, 0, 10, 11, 0x0a090806, 0x08090a06},
{2, 2140, 0, 10, 12, 0x0b090807, 0x080a0b07},
{1, 1350, 0, 10, 9, 0x08070605, 0x06070806},
{1, 1666, 0, 10, 11, 0x0a090806, 0x08090a06},
{1, 2140, 0, 8, 12, 0x0b090807, 0x080a0b07},
{}
};