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powerpc/8xxx: Refactor fsl_ddr_get_spd into common code from board

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Move fsl_ddr_get_spd into common mpc8xxx/ddr/main.c as most boards
pretty much do the same thing.  The only variations are in how many
controllers or DIMMs per controller exist.  To make this work we
standardize on the names of the SPD_EEPROM_ADDRESS defines based on the
use case of the board.

We allow boards to override get_spd to either do board specific fixups
to the SPD data or deal with any unique behavior of how the SPD eeproms
are wired up.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Kumar Gala
2011-01-31 22:18:47 -06:00
parent 5df4b0ad0d
commit c39f44dc6f
31 changed files with 69 additions and 551 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
include/configs/MPC8569MDS.h
View File

@@ -139,8 +139,7 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
/* I2C addresses of SPD EEPROMs */
#define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */
#define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 1 DIMM 0 */
#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
/* These are used when DDR doesn't use SPD. */
#define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR is 1024MB */

2
include/configs/MPC8610HPCD.h
View File

@@ -108,7 +108,7 @@
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
#define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */
#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
/* These are used when DDR doesn't use SPD. */
#define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */

2
include/configs/P1022DS.h
View File

@@ -87,7 +87,7 @@
/* I2C addresses of SPD EEPROMs */
#define CONFIG_SYS_SPD_BUS_NUM 1
#define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */
#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
/*
* Memory map

2
include/configs/P2020DS.h
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@@ -130,7 +130,7 @@
/* I2C addresses of SPD EEPROMs */
#define CONFIG_DDR_SPD
#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD EEPROM located on I2C bus 0 */
#define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */
#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
/* These are used when DDR doesn't use SPD. */
#define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR is 1GB */

2
include/configs/xpedite550x.h
View File

@@ -67,7 +67,7 @@
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
#define CONFIG_DDR_SPD
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#define SPD_EEPROM_ADDRESS1 0x54
#define SPD_EEPROM_ADDRESS 0x54
#define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */
#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_DIMM_SLOTS_PER_CTLR 1