Merge branch 'master' of git://www.denx.de/git/u-boot-ppc4xx

include/configs/PMC440.h

@@ -41,7 +41,9 @@
 
 #define CONFIG_SYS_CLK_FREQ	33333400
 
+#if 0 /* temporary disabled because OS/9 does not like dcache on startup */
 #define CONFIG_4xx_DCACHE		/* enable dcache        */
+#endif
 
 #define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f */
 #define CONFIG_MISC_INIT_R	1	/* Call misc_init_r     */
@@ -272,6 +274,7 @@
 	CFG_BOOTFILE							\
 	CFG_ROOTPATH							\
 	"netdev=eth0\0"							\
+	"ethrotate=no\0"						\
 	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
 	"nfsroot=${serverip}:${rootpath}\0"				\
 	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
@@ -354,10 +357,6 @@
 #define CONFIG_CMD_SDRAM
 
 /* POST support */
-/* ethernet POST sometimes freezes the CPU.
- * So disable it for now until issue is solved
- */
-#if 0
 #define CONFIG_POST		(CFG_POST_MEMORY |	\
 				 CFG_POST_CPU    |	\
 				 CFG_POST_UART   |	\
@@ -366,15 +365,6 @@
 				 CFG_POST_FPU    |	\
 				 CFG_POST_ETHER  |	\
 				 CFG_POST_SPR)
-#else
-#define CONFIG_POST		(CFG_POST_MEMORY |	\
-				 CFG_POST_CPU    |	\
-				 CFG_POST_UART   |	\
-				 CFG_POST_I2C    |	\
-				 CFG_POST_CACHE  |	\
-				 CFG_POST_FPU    |	\
-				 CFG_POST_SPR)
-#endif
 
 #define CFG_POST_WORD_ADDR	(CFG_GBL_DATA_OFFSET - 0x4)
 

include/configs/lwmon5.h

@@ -248,6 +248,18 @@
 #define CONFIG_HAS_ETH1		1	/* add support for "eth1addr"	*/
 #define CONFIG_PHY1_ADDR	1
 
+/* Video console */
+#define CONFIG_VIDEO
+#define CONFIG_VIDEO_MB862xx
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_CONSOLE_EXTRA_INFO
+#define VIDEO_FB_16BPP_PIXEL_SWAP
+
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_VIDEO_SW_CURSOR
+#define CONFIG_SPLASH_SCREEN
+
 /* USB */
 #ifdef CONFIG_440EPX
 #define CONFIG_USB_OHCI
@@ -294,6 +306,10 @@
 #define CONFIG_CMD_REGINFO
 #define CONFIG_CMD_SDRAM
 
+#ifdef CONFIG_VIDEO
+#define CONFIG_CMD_BMP
+#endif
+
 #ifdef CONFIG_440EPX
 #define CONFIG_CMD_USB
 #endif

include/configs/sequoia.h

@@ -61,6 +61,7 @@
 #define CFG_MONITOR_LEN		(384 * 1024)	/* Reserve 384 kB for Monitor	*/
 #define CFG_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/
 
+#define CFG_TLB_FOR_BOOT_FLASH	0x0003
 #define CFG_BOOT_BASE_ADDR	0xf0000000
 #define CFG_SDRAM_BASE		0x00000000	/* _must_ be 0		*/
 #define CFG_FLASH_BASE		0xfc000000	/* start of FLASH	*/