Merge branch 'rmobile' of git://git.denx.de/u-boot-sh
This commit is contained in:
Tom Rini
@@ -2,7 +2,7 @@
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* include/configs/rcar-gen3-common.h
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* This file is R-Car Gen3 common configuration file.
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*
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* Copyright (C) 2015 Renesas Electronics Corporation
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* Copyright (C) 2015-2017 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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@@ -17,7 +17,6 @@
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#define CONFIG_CMD_EXT2
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#define CONFIG_CMD_EXT4
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#define CONFIG_CMD_EXT4_WRITE
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#define CONFIG_CMD_FDT
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#define CONFIG_REMAKE_ELF
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@@ -34,7 +33,6 @@
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_INITRD_TAG
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#define CONFIG_CMDLINE_EDITING
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#define CONFIG_OF_LIBFDT
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#undef CONFIG_SHOW_BOOT_PROGRESS
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@@ -52,13 +50,34 @@
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#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400 }
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/* MEMORY */
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#define CONFIG_SYS_TEXT_BASE 0x49000000
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#define CONFIG_SYS_TEXT_BASE 0x50000000
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0x7fff0)
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#define CONFIG_SYS_SDRAM_BASE (0x48000000)
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#define CONFIG_SYS_SDRAM_SIZE (1024u * 1024 * 1024 - 0x08000000)
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#define CONFIG_SYS_LOAD_ADDR (0x48080000)
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#define CONFIG_NR_DRAM_BANKS 1
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#define DRAM_RSV_SIZE 0x08000000
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#if defined(CONFIG_R8A7795)
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#define CONFIG_NR_DRAM_BANKS 4
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#define PHYS_SDRAM_1 (0x40000000 + DRAM_RSV_SIZE)
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#define PHYS_SDRAM_1_SIZE (0x40000000u - DRAM_RSV_SIZE)
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#define PHYS_SDRAM_2 0x500000000
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#define PHYS_SDRAM_2_SIZE 0x40000000u
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#define PHYS_SDRAM_3 0x600000000
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#define PHYS_SDRAM_3_SIZE 0x40000000u
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#define PHYS_SDRAM_4 0x700000000
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#define PHYS_SDRAM_4_SIZE 0x40000000u
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#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
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#define CONFIG_SYS_SDRAM_SIZE PHYS_SDRAM_1_SIZE
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#elif defined(CONFIG_R8A7796)
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#define CONFIG_NR_DRAM_BANKS 2
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#define PHYS_SDRAM_1 (0x40000000 + DRAM_RSV_SIZE)
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#define PHYS_SDRAM_1_SIZE (0x80000000u - DRAM_RSV_SIZE)
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#define PHYS_SDRAM_2 0x0600000000
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#define PHYS_SDRAM_2_SIZE 0x80000000u
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#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
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#define CONFIG_SYS_SDRAM_SIZE PHYS_SDRAM_1_SIZE
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#endif
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#define CONFIG_SYS_LOAD_ADDR 0x48080000
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#define CONFIG_VERY_BIG_RAM
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#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_SDRAM_SIZE
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#define CONFIG_SYS_MONITOR_BASE 0x00000000
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#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
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@@ -81,7 +100,7 @@
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#define CONFIG_BOOTCOMMAND \
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"tftp 0x48080000 Image; " \
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"tftp 0x48000000 Image-r8a7795-salvator-x.dtb; " \
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"tftp 0x48000000 Image-"CONFIG_DEFAULT_FDT_FILE"; " \
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"booti 0x48080000 - 0x48000000"
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#endif /* __RCAR_GEN3_COMMON_H */
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@@ -20,21 +20,27 @@
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#define CONFIG_SCIF_CONSOLE
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#define CONFIG_CONS_SCIF2
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#define CONFIG_CONS_INDEX 2
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#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
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#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_S3D4_CLK_FREQ
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/* [A] Hyper Flash */
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/* use to RPC(SPI Multi I/O Bus Controller) */
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#define CONFIG_ENV_IS_NOWHERE
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/* Ethernet RAVB */
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#define CONFIG_NET_MULTI
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#define CONFIG_PHY_MICREL
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#define CONFIG_BITBANGMII
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#define CONFIG_BITBANGMII_MULTI
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/* Board Clock */
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/* XTAL_CLK : 33.33MHz */
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#define RCAR_XTAL_CLK 33333333u
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#define CONFIG_SYS_CLK_FREQ RCAR_XTAL_CLK
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/* ch0to2 CPclk, ch3to11 S3D2_PEREclk, ch12to14 S3D2_RTclk */
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/* CPclk 16.66MHz, S3D2 133.33MHz */
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/* CPclk 16.66MHz, S3D2 133.33MHz , S3D4 66.66MHz */
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#define CONFIG_CP_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2)
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#define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 192 / 2)
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#define CONFIG_S3D2_CLK_FREQ (266666666u/2)
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#define CONFIG_S3D4_CLK_FREQ (266666666u/4)
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/* Generic Timer Definitions (use in assembler source) */
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#define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */
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@@ -44,9 +50,39 @@
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#define GICD_BASE 0xF1010000
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#define GICC_BASE 0xF1020000
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/* i2c */
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_SH
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#define CONFIG_SYS_I2C_SLAVE 0x60
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#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 1
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#define CONFIG_SYS_I2C_SH_SPEED0 400000
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#define CONFIG_SH_I2C_DATA_HIGH 4
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#define CONFIG_SH_I2C_DATA_LOW 5
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#define CONFIG_SH_I2C_CLOCK 10000000
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#define CONFIG_SYS_I2C_POWERIC_ADDR 0x30
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/* USB */
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#ifdef CONFIG_R8A7795
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#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
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#else
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#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
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#endif
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/* SDHI */
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#define CONFIG_SH_SDHI_FREQ 200000000
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/* Environment in eMMC, at the end of 2nd "boot sector" */
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#define CONFIG_ENV_IS_IN_MMC
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#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
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#define CONFIG_SYS_MMC_ENV_DEV 1
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#define CONFIG_SYS_MMC_ENV_PART 2
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/* Module stop status bits */
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/* MFIS, SCIF1 */
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#define CONFIG_SMSTP2_ENA 0x00002040
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/* SCIF2 */
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#define CONFIG_SMSTP3_ENA 0x00000400
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/* INTC-AP, IRQC */
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#define CONFIG_SMSTP4_ENA 0x00000180
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