Xilinx fixes for v2020.04-rc4

- Fix link good bit handling in dp83867
- Rename generic Zynq defconfig
- Fix zybo z7 low leve setup
- Fix error path in zynq_gem driver and fix 64bit usage
- Fix invalid clock name quieries for Versal
- Fix zynq/zynqmp SPL low level configuration via DT selection
This commit is contained in:
Tom Rini
2020-03-02 09:20:12 -05:00
11 changed files with 50 additions and 14 deletions

View File

@@ -41,8 +41,6 @@
# define CONFIG_BOOTP_MAY_FAIL
#endif
/* QSPI */
/* NOR */
#ifdef CONFIG_MTD_NOR_FLASH
# define CONFIG_SYS_FLASH_BASE 0xE2000000