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riscv: timer: Add support for an early timer

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Added support for timer_early_get_count() and timer_early_get_rate()
This is mostly useful in tracing.

Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Rick Chen <rick@andestech.com>
This commit is contained in:
Pragnesh Patel
2021-01-17 18:11:25 +05:30
committed by Andes
parent a80f85138c
commit bc8d12bfd8
6 changed files with 75 additions and 3 deletions
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5
include/configs/ax25-ae350.h
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@@ -17,6 +17,11 @@
#endif
#endif
#define RISCV_MMODE_TIMERBASE 0xe6000000
#define RISCV_MMODE_TIMER_FREQ 60000000
#define RISCV_SMODE_TIMER_FREQ 60000000
/*
* CPU and Board Configuration Options
*/

5
include/configs/qemu-riscv.h
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@@ -29,6 +29,11 @@
#define CONFIG_STANDALONE_LOAD_ADDR 0x80200000
#define RISCV_MMODE_TIMERBASE 0x2000000
#define RISCV_MMODE_TIMER_FREQ 1000000
#define RISCV_SMODE_TIMER_FREQ 1000000
/* Environment options */
#ifndef CONFIG_SPL_BUILD

5
include/configs/sifive-fu540.h
View File

@@ -36,6 +36,11 @@
#define CONFIG_STANDALONE_LOAD_ADDR 0x80200000
#define RISCV_MMODE_TIMERBASE 0x2000000
#define RISCV_MMODE_TIMER_FREQ 1000000
#define RISCV_SMODE_TIMER_FREQ 1000000
/* Environment options */
#ifndef CONFIG_SPL_BUILD