Merge tag 'xilinx-for-v2021.04' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze into next
Xilinx changes for v2021.04 arm64: - DT updates microblaze: - Add support for NOR device support spi: - Fix unaligned data write issue nand: - Minor code change xilinx: - Fru fix in limit calculation - Fill git repo link for all Xilinx boards video: - Add support for seps525 spi display tools: - Minor Vitis file support cmd/common - Minor code indentation fixes serial: - Uartlite debug uart initialization fix
This commit is contained in:
Tom Rini
@@ -23,6 +23,7 @@
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serial1 = &dcc;
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spi0 = &qspi;
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mmc0 = &sdhci1;
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ethernet0 = &gem1;
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};
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chosen {
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@@ -40,6 +41,29 @@
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status = "okay";
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};
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&gem1 {
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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phy1: ethernet-phy@1 {
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reg = <1>; /* KSZ9031RNXIC on AES-FMC-NETW1-G */
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rxc-skew-ps = <1800>; /* Skew control of RX_CLK pad output */
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txc-skew-ps = <1800>; /* Skew control of GTX_CLK pad input */
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txen-skew-ps = <900>; /* Skew control of TX_CTL pad input */
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rxdv-skew-ps = <0>; /* Skew control of RX_CTL pad output */
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rxd0-skew-ps = <0>; /* Skew control of RXD0 pad output */
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rxd1-skew-ps = <0>; /* Skew control of RXD1 pad output */
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rxd2-skew-ps = <0>; /* Skew control of RXD2 pad output */
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rxd3-skew-ps = <0>; /* Skew control of RXD3 pad output */
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txd0-skew-ps = <900>; /* Skew control of TXD0 pad input */
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txd1-skew-ps = <900>; /* Skew control of TXD1 pad input */
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txd2-skew-ps = <900>; /* Skew control of TXD2 pad input */
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txd3-skew-ps = <900>; /* Skew control of TXD3 pad input */
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};
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};
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};
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&qspi {
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status = "okay";
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flash@0 {
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@@ -23,6 +23,7 @@
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serial1 = &dcc;
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spi0 = &qspi;
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mmc0 = &sdhci1;
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ethernet0 = &gem1; /* EMIO */
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i2c = &i2c0; /* EMIO */
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};
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@@ -222,6 +223,28 @@
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};
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};
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&gem1 {
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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phy1: ethernet-phy@1 {
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reg = <1>; /* KSZ9031RNXIC on AES-FMC-NETW1-G */
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rxc-skew-ps = <1800>; /* Skew control of RX_CLK pad output */
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txc-skew-ps = <1800>; /* Skew control of GTX_CLK pad input */
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txen-skew-ps = <900>; /* Skew control of TX_CTL pad input */
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rxdv-skew-ps = <0>; /* Skew control of RX_CTL pad output */
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rxd0-skew-ps = <0>; /* Skew control of RXD0 pad output */
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rxd1-skew-ps = <0>; /* Skew control of RXD1 pad output */
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rxd2-skew-ps = <0>; /* Skew control of RXD2 pad output */
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rxd3-skew-ps = <0>; /* Skew control of RXD3 pad output */
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txd0-skew-ps = <900>; /* Skew control of TXD0 pad input */
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txd1-skew-ps = <900>; /* Skew control of TXD1 pad input */
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txd2-skew-ps = <900>; /* Skew control of TXD2 pad input */
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txd3-skew-ps = <900>; /* Skew control of TXD3 pad input */
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};
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};
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};
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&qspi {
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status = "okay";
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flash@0 {
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@@ -115,8 +115,10 @@
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<0x0 0xff9905e0 0x0 0x20>,
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<0x0 0xff990e80 0x0 0x20>,
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<0x0 0xff990ea0 0x0 0x20>;
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reg-names = "local_request_region", "local_response_region",
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"remote_request_region", "remote_response_region";
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reg-names = "local_request_region",
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"local_response_region",
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"remote_request_region",
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"remote_response_region";
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#mbox-cells = <1>;
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xlnx,ipi-id = <4>;
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};
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@@ -145,15 +147,10 @@
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firmware {
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zynqmp_firmware: zynqmp-firmware {
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compatible = "xlnx,zynqmp-firmware";
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#power-domain-cells = <1>;
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method = "smc";
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#power-domain-cells = <0x1>;
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u-boot,dm-pre-reloc;
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zynqmp_pcap: pcap {
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compatible = "xlnx,zynqmp-pcap-fpga";
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clock-names = "ref_clk";
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};
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zynqmp_power: zynqmp-power {
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u-boot,dm-pre-reloc;
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compatible = "xlnx,zynqmp-power";
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@@ -163,6 +160,11 @@
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mbox-names = "tx", "rx";
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};
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zynqmp_pcap: pcap {
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compatible = "xlnx,zynqmp-pcap-fpga";
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clock-names = "ref_clk";
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};
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zynqmp_reset: reset-controller {
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compatible = "xlnx,zynqmp-reset";
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#reset-cells = <1>;
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@@ -206,26 +208,7 @@
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};
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};
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amba_apu: amba-apu@0 {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <1>;
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ranges = <0 0 0 0 0xffffffff>;
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gic: interrupt-controller@f9010000 {
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compatible = "arm,gic-400";
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#interrupt-cells = <3>;
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reg = <0x0 0xf9010000 0x10000>,
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<0x0 0xf9020000 0x20000>,
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<0x0 0xf9040000 0x20000>,
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<0x0 0xf9060000 0x20000>;
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interrupt-controller;
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interrupt-parent = <&gic>;
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interrupts = <1 9 0xf04>;
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};
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};
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amba: amba {
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amba: axi {
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compatible = "simple-bus";
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u-boot,dm-pre-reloc;
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#address-cells = <2>;
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@@ -380,6 +363,18 @@
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power-domains = <&zynqmp_firmware PD_GDMA>;
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};
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gic: interrupt-controller@f9010000 {
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compatible = "arm,gic-400";
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#interrupt-cells = <3>;
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reg = <0x0 0xf9010000 0x0 0x10000>,
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<0x0 0xf9020000 0x0 0x20000>,
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<0x0 0xf9040000 0x0 0x20000>,
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<0x0 0xf9060000 0x0 0x20000>;
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interrupt-controller;
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interrupt-parent = <&gic>;
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interrupts = <1 9 0xf04>;
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};
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gpu: gpu@fd4b0000 {
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status = "disabled";
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compatible = "arm,mali-400", "arm,mali-utgard";
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@@ -590,7 +585,7 @@
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};
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i2c0: i2c@ff020000 {
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compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10";
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compatible = "cdns,i2c-r1p14";
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status = "disabled";
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interrupt-parent = <&gic>;
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interrupts = <0 17 4>;
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@@ -601,7 +596,7 @@
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};
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i2c1: i2c@ff030000 {
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compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10";
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compatible = "cdns,i2c-r1p14";
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status = "disabled";
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interrupt-parent = <&gic>;
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interrupts = <0 18 4>;
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@@ -639,8 +634,8 @@
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<0x0 0xfd480000 0x0 0x1000>,
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<0x80 0x00000000 0x0 0x1000000>;
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reg-names = "breg", "pcireg", "cfg";
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ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000 /* non-prefetchable memory */
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0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */
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ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000>,/* non-prefetchable memory */
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<0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */
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bus-range = <0x00 0xff>;
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interrupt-map-mask = <0x0 0x0 0x0 0x7>;
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interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
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@@ -770,7 +765,7 @@
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clock-output-names = "clk_out_sd1", "clk_in_sd1";
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};
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smmu: smmu@fd800000 {
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smmu: iommu@fd800000 {
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compatible = "arm,mmu-500";
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reg = <0x0 0xfd800000 0x0 0x20000>;
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#iommu-cells = <1>;
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