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Merge commit 'origin/master'

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This commit is contained in:
Haavard Skinnemoen
2007-10-02 19:05:53 +02:00
parent e80e585b00 527c80f012
commit b90296fc39
549 changed files with 52188 additions and 17469 deletions
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139
include/asm-arm/arch-at91rm9200/AT91RM9200.h
View File

@@ -27,9 +27,9 @@
typedef volatile unsigned int AT91_REG; /* Hardware register definition */
/******************************************************************************/
/* SOFTWARE API DEFINITION FOR Timer Counter Channel Interface */
/******************************************************************************/
/*****************************************************************************/
/* SOFTWARE API DEFINITION FOR Timer Counter Channel Interface */
/*****************************************************************************/
typedef struct _AT91S_TC
{
AT91_REG TC_CCR; /* Channel Control Register */
@@ -45,24 +45,24 @@ typedef struct _AT91S_TC
AT91_REG TC_IMR; /* Interrupt Mask Register */
} AT91S_TC, *AT91PS_TC;
#define AT91C_TC_TIMER_DIV1_CLOCK ((unsigned int) 0x0 << 0) /* (TC) MCK/2 */
#define AT91C_TC_TIMER_DIV2_CLOCK ((unsigned int) 0x1 << 0) /* (TC) MCK/8 */
#define AT91C_TC_TIMER_DIV3_CLOCK ((unsigned int) 0x2 << 0) /* (TC) MCK/32 */
#define AT91C_TC_TIMER_DIV4_CLOCK ((unsigned int) 0x3 << 0) /* (TC) MCK/128 */
#define AT91C_TC_SLOW_CLOCK ((unsigned int) 0x4 << 0) /* (TC) SLOW CLK */
#define AT91C_TC_XC0_CLOCK ((unsigned int) 0x5 << 0) /* (TC) XC0 */
#define AT91C_TC_XC1_CLOCK ((unsigned int) 0x6 << 0) /* (TC) XC1 */
#define AT91C_TC_XC2_CLOCK ((unsigned int) 0x7 << 0) /* (TC) XC2 */
#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) /* (TCB) None signal connected to XC0 */
#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) /* (TCB) None signal connected to XC1 */
#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) /* (TCB) None signal connected to XC2 */
#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) /* (TC) Counter Clock Disable Command */
#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) /* (TC) Software Trigger Command */
#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) /* (TC) Counter Clock Enable Command */
#define AT91C_TC_TIMER_DIV1_CLOCK ((unsigned int) 0x0 << 0) /* (TC) MCK/2 */
#define AT91C_TC_TIMER_DIV2_CLOCK ((unsigned int) 0x1 << 0) /* (TC) MCK/8 */
#define AT91C_TC_TIMER_DIV3_CLOCK ((unsigned int) 0x2 << 0) /* (TC) MCK/32 */
#define AT91C_TC_TIMER_DIV4_CLOCK ((unsigned int) 0x3 << 0) /* (TC) MCK/128 */
#define AT91C_TC_SLOW_CLOCK ((unsigned int) 0x4 << 0) /* (TC) SLOW CLK*/
#define AT91C_TC_XC0_CLOCK ((unsigned int) 0x5 << 0) /* (TC) XC0 */
#define AT91C_TC_XC1_CLOCK ((unsigned int) 0x6 << 0) /* (TC) XC1 */
#define AT91C_TC_XC2_CLOCK ((unsigned int) 0x7 << 0) /* (TC) XC2 */
#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) /* (TCB) None signal connected to XC0 */
#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) /* (TCB) None signal connected to XC1 */
#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) /* (TCB) None signal connected to XC2 */
#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) /* (TC) Counter Clock Disable Command */
#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) /* (TC) Software Trigger Command */
#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) /* (TC) Counter Clock Enable Command */
/******************************************************************************/
/* SOFTWARE API DEFINITION FOR Usart */
/******************************************************************************/
/*****************************************************************************/
/* SOFTWARE API DEFINITION FOR Usart */
/*****************************************************************************/
typedef struct _AT91S_USART
{
AT91_REG US_CR; /* Control Register */
@@ -94,9 +94,9 @@ typedef struct _AT91S_USART
AT91_REG US_PTSR; /* PDC Transfer Status Register */
} AT91S_USART, *AT91PS_USART;
/******************************************************************************/
/* SOFTWARE API DEFINITION FOR Clock Generator Controler */
/******************************************************************************/
/*****************************************************************************/
/* SOFTWARE API DEFINITION FOR Clock Generator Controler */
/*****************************************************************************/
typedef struct _AT91S_CKGR
{
AT91_REG CKGR_MOR; /* Main Oscillator Register */
@@ -141,9 +141,9 @@ typedef struct _AT91S_CKGR
#define AT91C_CKGR_USB_96M ((unsigned int) 0x1 << 28) /* (CKGR) Divider for USB Ports */
#define AT91C_CKGR_USB_PLL ((unsigned int) 0x1 << 29) /* (CKGR) PLL Use */
/******************************************************************************/
/* SOFTWARE API DEFINITION FOR Parallel Input Output Controler */
/******************************************************************************/
/*****************************************************************************/
/* SOFTWARE API DEFINITION FOR Parallel Input Output Controler */
/*****************************************************************************/
typedef struct _AT91S_PIO
{
AT91_REG PIO_PER; /* PIO Enable Register */
@@ -184,9 +184,9 @@ typedef struct _AT91S_PIO
} AT91S_PIO, *AT91PS_PIO;
/******************************************************************************/
/* SOFTWARE API DEFINITION FOR Debug Unit */
/******************************************************************************/
/*****************************************************************************/
/* SOFTWARE API DEFINITION FOR Debug Unit */
/*****************************************************************************/
typedef struct _AT91S_DBGU
{
AT91_REG DBGU_CR; /* Control Register */
@@ -242,9 +242,9 @@ typedef struct _AT91S_DBGU
#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) /* (DBGU) No Parity */
#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) /* (USART) 1 stop bit */
/******************************************************************************/
/* SOFTWARE API DEFINITION FOR Static Memory Controller 2 Interface */
/******************************************************************************/
/*****************************************************************************/
/* SOFTWARE API DEFINITION FOR Static Memory Controller 2 Interface */
/*****************************************************************************/
typedef struct _AT91S_SMC2
{
AT91_REG SMC2_CSR[8]; /* SMC2 Chip Select Register */
@@ -267,9 +267,9 @@ typedef struct _AT91S_SMC2
#define AT91C_SMC2_RWSETUP ((unsigned int) 0x7 << 24) /* (SMC2) Read and Write Signal Setup Time */
#define AT91C_SMC2_RWHOLD ((unsigned int) 0x7 << 29) /* (SMC2) Read and Write Signal Hold Time */
/******************************************************************************/
/* SOFTWARE API DEFINITION FOR Power Management Controler */
/******************************************************************************/
/*****************************************************************************/
/* SOFTWARE API DEFINITION FOR Power Management Controler */
/*****************************************************************************/
typedef struct _AT91S_PMC
{
AT91_REG PMC_SCER; /* System Clock Enable Register */
@@ -341,9 +341,9 @@ typedef struct _AT91S_PMC
/*-------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------*/
/*-------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------*/
/******************************************************************************/
/* SOFTWARE API DEFINITION FOR Ethernet MAC */
/******************************************************************************/
/*****************************************************************************/
/* SOFTWARE API DEFINITION FOR Ethernet MAC */
/*****************************************************************************/
typedef struct _AT91S_EMAC
{
AT91_REG EMAC_CTL; /* Network Control Register */
@@ -424,11 +424,11 @@ typedef struct _AT91S_EMAC
#define AT91C_EMAC_MDIO ((unsigned int) 0x1 << 1) /* (EMAC) */
#define AT91C_EMAC_IDLE ((unsigned int) 0x1 << 2) /* (EMAC) */
/* -------- EMAC_TCR : (EMAC Offset: 0x10) Transmit Control Register -------- */
/* -------- EMAC_TCR : (EMAC Offset: 0x10) Transmit Control Register ------- */
#define AT91C_EMAC_LEN ((unsigned int) 0x7FF << 0) /* (EMAC) */
#define AT91C_EMAC_NCRC ((unsigned int) 0x1 << 15) /* (EMAC) */
/* -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Control Register -------- */
/* -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Control Register ------- */
#define AT91C_EMAC_OVR ((unsigned int) 0x1 << 0) /* (EMAC) */
#define AT91C_EMAC_COL ((unsigned int) 0x1 << 1) /* (EMAC) */
#define AT91C_EMAC_RLE ((unsigned int) 0x1 << 2) /* (EMAC) */
@@ -442,7 +442,7 @@ typedef struct _AT91S_EMAC
#define AT91C_EMAC_REC ((unsigned int) 0x1 << 1) /* (EMAC) */
#define AT91C_EMAC_RSR_OVR ((unsigned int) 0x1 << 2) /* (EMAC) */
/* -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- */
/* -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register ------- */
#define AT91C_EMAC_DONE ((unsigned int) 0x1 << 0) /* (EMAC) */
#define AT91C_EMAC_RCOM ((unsigned int) 0x1 << 1) /* (EMAC) */
#define AT91C_EMAC_RBNA ((unsigned int) 0x1 << 2) /* (EMAC) */
@@ -456,8 +456,8 @@ typedef struct _AT91S_EMAC
#define AT91C_EMAC_ROVR ((unsigned int) 0x1 << 10) /* (EMAC) */
#define AT91C_EMAC_HRESP ((unsigned int) 0x1 << 11) /* (EMAC) */
/* -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- */
/* -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- */
/* -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register ------- */
/* -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register ------ */
/* -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- */
/* -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- */
#define AT91C_EMAC_DATA ((unsigned int) 0xFFFF << 0) /* (EMAC) */
@@ -471,9 +471,9 @@ typedef struct _AT91S_EMAC
#define AT91C_EMAC_HIGH ((unsigned int) 0x1 << 30) /* (EMAC) */
#define AT91C_EMAC_LOW ((unsigned int) 0x1 << 31) /* (EMAC) */
/******************************************************************************/
/* SOFTWARE API DEFINITION FOR Serial Parallel Interface */
/******************************************************************************/
/*****************************************************************************/
/* SOFTWARE API DEFINITION FOR Serial Parallel Interface */
/*****************************************************************************/
typedef struct _AT91S_SPI
{
AT91_REG SPI_CR; /* Control Register */
@@ -536,7 +536,7 @@ typedef struct _AT91S_SPI
#define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) /* (SPI) Enable Status */
/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */
/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */
/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register ------- */
/* -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- */
/* -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- */
#define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) /* (SPI) Clock Polarity */
@@ -555,9 +555,9 @@ typedef struct _AT91S_SPI
#define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) /* (SPI) Serial Clock Baud Rate */
#define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) /* (SPI) Delay Between Consecutive Transfers */
/******************************************************************************/
/* SOFTWARE API DEFINITION FOR Peripheral Data Controller */
/******************************************************************************/
/*****************************************************************************/
/* SOFTWARE API DEFINITION FOR Peripheral Data Controller */
/*****************************************************************************/
typedef struct _AT91S_PDC
{
AT91_REG PDC_RPR; /* Receive Pointer Register */
@@ -692,11 +692,15 @@ typedef struct _AT91S_PDC
#define AT91C_PIO_PA7 ((unsigned int) 1 << 7) /* Pin Controlled by PA7 */
#define AT91C_PA7_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PA7) /* Ethernet MAC Transmit Clock/Reference Clock */
#define AT91C_PIO_PB0 ((unsigned int) 1 << 0) /* Pin Controlled by PB3 */
#define AT91C_PIO_PB1 ((unsigned int) 1 << 1) /* Pin Controlled by PB3 */
#define AT91C_PIO_PB2 ((unsigned int) 1 << 2) /* Pin Controlled by PB3 */
#define AT91C_PIO_PB3 ((unsigned int) 1 << 3) /* Pin Controlled by PB3 */
#define AT91C_PIO_PB4 ((unsigned int) 1 << 4) /* Pin Controlled by PB4 */
#define AT91C_PIO_PB5 ((unsigned int) 1 << 5) /* Pin Controlled by PB5 */
#define AT91C_PIO_PB6 ((unsigned int) 1 << 6) /* Pin Controlled by PB6 */
#define AT91C_PIO_PB7 ((unsigned int) 1 << 7) /* Pin Controlled by PB7 */
#define AT91C_PIO_PB22 ((unsigned int) 1 << 22) /* Pin Controlled by PB22 */
#define AT91C_PIO_PB25 ((unsigned int) 1 << 25) /* Pin Controlled by PB25 */
#define AT91C_PB25_DSR1 ((unsigned int) AT91C_PIO_PB25) /* USART 1 Data Set ready */
#define AT91C_PB25_EF100 ((unsigned int) AT91C_PIO_PB25) /* Ethernet MAC Force 100 Mbits */
@@ -737,19 +741,36 @@ typedef struct _AT91S_PDC
#define AT91C_PIOC_CODR ((AT91_REG *) 0xFFFFF834) /* (PIOC) Clear Output Data Register */
#define AT91C_PIOC_PDSR ((AT91_REG *) 0xFFFFF83C) /* (PIOC) Pin Data Status Register */
#define AT91C_BASE_SPI ((AT91PS_SPI) 0xFFFE0000) /* (SPI) Base Address */
#define AT91C_BASE_EMAC ((AT91PS_EMAC) 0xFFFBC000) /* (EMAC) Base Address */
#define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) /* (PMC) Base Address */
#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) /* (TC0) Base Address */
#define AT91C_BASE_AIC ((AT91PS_AIC) 0xFFFFF000) /* (AIC) Base Address */
#define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) /* (DBGU) Base Address */
#define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) /* (CKGR) Base Address */
#define AT91C_BASE_PIOC ((AT91PS_PIO) 0xFFFFF800) /* (PIOC) Base Address */
#define AT91C_BASE_PIOB ((AT91PS_PIO) 0xFFFFF600) /* (PIOB) Base Address */
#define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) /* (PIOA) Base Address */
#define AT91C_EBI_CSA ((AT91_REG *) 0xFFFFFF60) /* (EBI) Chip Select Assignment Register */
#define AT91C_BASE_SMC2 ((AT91PS_SMC2) 0xFFFFFF70) /* (SMC2) Base Address */
#define AT91C_BASE_PIOB ((AT91PS_PIO) 0xFFFFF600) /* (PIOB) Base Address */
#define AT91C_BASE_PIOC ((AT91PS_PIO) 0xFFFFF800) /* (PIOC) Base Address */
#define AT91C_BASE_PIOD ((AT91PS_PIO) 0xFFFFFA00) /* (PIOC) Base Address */
#define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) /* (PMC) Base Address */
#if 0
#define AT91C_BASE_ST ((AT91PS_ST) 0xFFFFFD00) /* (PMC) Base Address */
#define AT91C_BASE_RTC ((AT91PS_RTC) 0xFFFFFE00) /* (PMC) Base Address */
#define AT91C_BASE_MC ((AT91PS_MC) 0xFFFFFF00) /* (PMC) Base Address */
#endif
#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) /* (TC0) Base Address */
#define AT91C_BASE_TC1 ((AT91PS_TC) 0xFFFA4000) /* (TC0) Base Address */
#if 0
#define AT91C_BASE_UDP ((AT91PS_UDP) 0xFFFB0000) /* (TC0) Base Address */
#define AT91C_BASE_MCI ((AT91PS_MCI) 0xFFFB4000) /* (TC0) Base Address */
#define AT91C_BASE_TWI ((AT91PS_TWI) 0xFFFB8000) /* (TC0) Base Address */
#endif
#define AT91C_BASE_EMAC ((AT91PS_EMAC) 0xFFFBC000) /* (EMAC) Base Address */
#define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) /* (US0) Base Address */
#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) /* (US1) Base Address */
#define AT91C_BASE_US2 ((AT91PS_USART) 0xFFFC8000) /* (US1) Base Address */
#define AT91C_BASE_US3 ((AT91PS_USART) 0xFFFCC000) /* (US1) Base Address */
#define AT91C_BASE_SPI ((AT91PS_SPI) 0xFFFE0000) /* (SPI) Base Address */
#define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) /* (CKGR) Base Address */
#define AT91C_EBI_CSA ((AT91_REG *) 0xFFFFFF60) /* (EBI) Chip Select Assignment Register */
#define AT91C_BASE_SMC2 ((AT91PS_SMC2) 0xFFFFFF70) /* (SMC2) Base Address */
#define AT91C_TCB0_BMR ((AT91_REG *) 0xFFFA00C4) /* (TCB0) TC Block Mode Register */
#define AT91C_TCB0_BCR ((AT91_REG *) 0xFFFA00C0) /* (TCB0) TC Block Control Register */
#define AT91C_PIOC_PDR ((AT91_REG *) 0xFFFFF804) /* (PIOC) PIO Disable Register */

18
include/asm-arm/arch-pxa/pxa-regs.h
View File

@@ -1288,15 +1288,15 @@ typedef void (*ExcpHndlr) (void) ;
#define _GEDR(x) __REG2(0x40E00048, ((x) & 0x60) >> 3)
#define _GAFR(x) __REG2(0x40E00054, ((x) & 0x70) >> 2)
#define GPLR(x) ((((x) & 0x7f) < 96) ? _GPLR(x) : GPLR3)
#define GPDR(x) ((((x) & 0x7f) < 96) ? _GPDR(x) : GPDR3)
#define GPSR(x) ((((x) & 0x7f) < 96) ? _GPSR(x) : GPSR3)
#define GPCR(x) ((((x) & 0x7f) < 96) ? _GPCR(x) : GPCR3)
#define GRER(x) ((((x) & 0x7f) < 96) ? _GRER(x) : GRER3)
#define GFER(x) ((((x) & 0x7f) < 96) ? _GFER(x) : GFER3)
#define GEDR(x) ((((x) & 0x7f) < 96) ? _GEDR(x) : GEDR3)
#define GAFR(x) ((((x) & 0x7f) < 96) ? _GAFR(x) : \
((((x) & 0x7f) < 112) ? GAFR3_L : GAFR3_U))
#define GPLR(x) __REG2(0x40E00000 + (((x) & 0x7f) < 96) ? 0:0x100, ((x) & 0x60) >> 3)
#define GPDR(x) __REG2(0x40E0000C + (((x) & 0x7f) < 96) ? 0:0x100, ((x) & 0x60) >> 3)
#define GPSR(x) __REG2(0x40E00018 + (((x) & 0x7f) < 96) ? 0:0x100, ((x) & 0x60) >> 3)
#define GPCR(x) __REG2(0x40E00024 + (((x) & 0x7f) < 96) ? 0:0x100, ((x) & 0x60) >> 3)
#define GRER(x) __REG2(0x40E00030 + (((x) & 0x7f) < 96) ? 0:0x100, ((x) & 0x60) >> 3)
#define GFER(x) __REG2(0x40E0003C + (((x) & 0x7f) < 96) ? 0:0x100, ((x) & 0x60) >> 3)
#define GEDR(x) __REG2(0x40E00048 + (((x) & 0x7f) < 96) ? 0:0x100, ((x) & 0x60) >> 3)
#define GAFR(x) __REG2((((x) & 0x7f) < 96) ? 0x40E00054 : \
((((x) & 0x7f) < 112) ? 0x40E0006C : 0x40E00070),((x) & 0x60) >> 3)
#else
#define GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3)

69
include/asm-arm/mach-types.h
View File

@@ -736,7 +736,11 @@ extern unsigned int __machine_arch_type;
#define MACH_TYPE_LN2410SBC 725
#define MACH_TYPE_CB3RUFC 726
#define MACH_TYPE_MP2USB 727
#define MACH_TYPE_AT91SAM9261EK 848
#define MACH_TYPE_PDNB3 1002
#define MACH_TYPE_AT91SAM9260EK 1099
#define MACH_TYPE_AT91RM9200DF 1119
#define MACH_TYPE_AT91SAM9263EK 1202
#ifdef CONFIG_ARCH_EBSA110
# ifdef machine_arch_type
@@ -9402,6 +9406,71 @@ extern unsigned int __machine_arch_type;
# define machine_is_mp2usb() (0)
#endif
#ifdef CONFIG_MACH_AT91SAM9261EK
# ifdef machine_arch_type
# undef machine_arch_type
# define machine_arch_type __machine_arch_type
# else
# define machine_arch_type MACH_TYPE_AT91SAM9261EK
# endif
# define machine_is_at91sam9261ek() \
(machine_arch_type == MACH_TYPE_AT91SAM9261EK)
#else
# define machine_is_at91sam9261ek() (0)
#endif
#ifdef CONFIG_MACH_AT91SAM9260EK
# ifdef machine_arch_type
# undef machine_arch_type
# define machine_arch_type __machine_arch_type
# else
# define machine_arch_type MACH_TYPE_AT91SAM9260EK
# endif
# define machine_is_at91sam9260ek() \
(machine_arch_type == MACH_TYPE_AT91SAM9260EK)
#else
# define machine_is_at91sam9260ek() (0)
#endif
#ifdef CONFIG_MACH_AT91SAM9263EK
# ifdef machine_arch_type
# undef machine_arch_type
# define machine_arch_type __machine_arch_type
# else
# define machine_arch_type MACH_TYPE_AT91SAM9263EK
# endif
# define machine_is_at91sam9263ek() \
(machine_arch_type == MACH_TYPE_AT91SAM9263EK)
#else
# define machine_is_at91sam9263ek() (0)
#endif
#ifdef CONFIG_MACH_AT91RM9200DF
# ifdef machine_arch_type
# undef machine_arch_type
# define machine_arch_type __machine_arch_type
# else
# define machine_arch_type MACH_TYPE_AT91RM9200DF
# endif
# define machine_is_at91rm9200df() \
(machine_arch_type == MACH_TYPE_AT91RM9200DF)
#else
# define machine_is_at91rm9200df() (0)
#endif
#ifdef CONFIG_MACH_AT91SAM9263EK
# ifdef machine_arch_type
# undef machine_arch_type
# define machine_arch_type __machine_arch_type
# else
# define machine_arch_type MACH_TYPE_AT91SAM9263EK
# endif
# define machine_is_at91sam9263ek() \
(machine_arch_type == MACH_TYPE_AT91SAM9263EK)
#else
# define machine_is_at91sam9263ek() (0)
#endif
/*
* These have not yet been registered
*/

39
include/asm-m68k/bitops.h
View File

@@ -15,4 +15,43 @@ extern int test_and_set_bit(int nr, volatile void *addr);
extern int test_and_clear_bit(int nr, volatile void *addr);
extern int test_and_change_bit(int nr, volatile void *addr);
#ifdef __KERNEL__
/*
* ffs: find first bit set. This is defined the same way as
* the libc and compiler builtin ffs routines, therefore
* differs in spirit from the above ffz (man ffs).
*/
extern __inline__ int ffs(int x)
{
int r = 1;
if (!x)
return 0;
if (!(x & 0xffff)) {
x >>= 16;
r += 16;
}
if (!(x & 0xff)) {
x >>= 8;
r += 8;
}
if (!(x & 0xf)) {
x >>= 4;
r += 4;
}
if (!(x & 3)) {
x >>= 2;
r += 2;
}
if (!(x & 1)) {
x >>= 1;
r += 1;
}
return r;
}
#define __ffs(x) (ffs(x) - 1)
#endif /* __KERNEL__ */
#endif /* _M68K_BITOPS_H */

102
include/asm-m68k/byteorder.h
View File

@@ -1,7 +1,107 @@
/*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _M68K_BYTEORDER_H
#define _M68K_BYTEORDER_H
#include <asm/types.h>
#ifdef __GNUC__
#define __sw16(x) \
((__u16)( \
(((__u16)(x) & (__u16)0x00ffU) << 8) | \
(((__u16)(x) & (__u16)0xff00U) >> 8) ))
#define __sw32(x) \
((__u32)( \
(((__u32)(x)) << 24) | \
(((__u32)(x) & (__u32)0x0000ff00UL) << 8) | \
(((__u32)(x) & (__u32)0x00ff0000UL) >> 8) | \
(((__u32)(x)) >> 24) ))
extern __inline__ unsigned ld_le16(const volatile unsigned short *addr)
{
unsigned result = *addr;
return __sw16(result);
}
extern __inline__ void st_le16(volatile unsigned short *addr,
const unsigned val)
{
*addr = __sw16(val);
}
extern __inline__ unsigned ld_le32(const volatile unsigned *addr)
{
unsigned result = *addr;
return __sw32(result);
}
extern __inline__ void st_le32(volatile unsigned *addr, const unsigned val)
{
*addr = __sw32(val);
}
#if 0
/* alas, egcs sounds like it has a bug in this code that doesn't use the
inline asm correctly, and can cause file corruption. Until I hear that
it's fixed, I can live without the extra speed. I hope. */
#if !(__GNUC__ >= 2 && __GNUC_MINOR__ >= 90)
#if 0
# define __arch_swab16(x) ld_le16(&x)
# define __arch_swab32(x) ld_le32(&x)
#else
static __inline__ __attribute__ ((const))
__u16 ___arch__swab16(__u16 value)
{
return __sw16(value);
}
static __inline__ __attribute__ ((const))
__u32 ___arch__swab32(__u32 value)
{
return __sw32(value);
}
#define __arch__swab32(x) ___arch__swab32(x)
#define __arch__swab16(x) ___arch__swab16(x)
#endif /* 0 */
#endif
/* The same, but returns converted value from the location pointer by addr. */
#define __arch__swab16p(addr) ld_le16(addr)
#define __arch__swab32p(addr) ld_le32(addr)
/* The same, but do the conversion in situ, ie. put the value back to addr. */
#define __arch__swab16s(addr) st_le16(addr,*addr)
#define __arch__swab32s(addr) st_le32(addr,*addr)
#endif
#endif /* __GNUC__ */
#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
#define __BYTEORDER_HAS_U64__
#endif
#include <linux/byteorder/big_endian.h>
#endif /* _M68K_BYTEORDER_H */
#endif /* _M68K_BYTEORDER_H */

138
include/asm-m68k/errno.h Normal file
View File

@@ -0,0 +1,138 @@
#ifndef _PPC_ERRNO_H
#define _PPC_ERRNO_H
#define EPERM 1 /* Operation not permitted */
#define ENOENT 2 /* No such file or directory */
#define ESRCH 3 /* No such process */
#define EINTR 4 /* Interrupted system call */
#define EIO 5 /* I/O error */
#define ENXIO 6 /* No such device or address */
#define E2BIG 7 /* Arg list too long */
#define ENOEXEC 8 /* Exec format error */
#define EBADF 9 /* Bad file number */
#define ECHILD 10 /* No child processes */
#define EAGAIN 11 /* Try again */
#define ENOMEM 12 /* Out of memory */
#define EACCES 13 /* Permission denied */
#define EFAULT 14 /* Bad address */
#define ENOTBLK 15 /* Block device required */
#define EBUSY 16 /* Device or resource busy */
#define EEXIST 17 /* File exists */
#define EXDEV 18 /* Cross-device link */
#define ENODEV 19 /* No such device */
#define ENOTDIR 20 /* Not a directory */
#define EISDIR 21 /* Is a directory */
#define EINVAL 22 /* Invalid argument */
#define ENFILE 23 /* File table overflow */
#define EMFILE 24 /* Too many open files */
#define ENOTTY 25 /* Not a typewriter */
#define ETXTBSY 26 /* Text file busy */
#define EFBIG 27 /* File too large */
#define ENOSPC 28 /* No space left on device */
#define ESPIPE 29 /* Illegal seek */
#define EROFS 30 /* Read-only file system */
#define EMLINK 31 /* Too many links */
#define EPIPE 32 /* Broken pipe */
#define EDOM 33 /* Math argument out of domain of func */
#define ERANGE 34 /* Math result not representable */
#define EDEADLK 35 /* Resource deadlock would occur */
#define ENAMETOOLONG 36 /* File name too long */
#define ENOLCK 37 /* No record locks available */
#define ENOSYS 38 /* Function not implemented */
#define ENOTEMPTY 39 /* Directory not empty */
#define ELOOP 40 /* Too many symbolic links encountered */
#define EWOULDBLOCK EAGAIN /* Operation would block */
#define ENOMSG 42 /* No message of desired type */
#define EIDRM 43 /* Identifier removed */
#define ECHRNG 44 /* Channel number out of range */
#define EL2NSYNC 45 /* Level 2 not synchronized */
#define EL3HLT 46 /* Level 3 halted */
#define EL3RST 47 /* Level 3 reset */
#define ELNRNG 48 /* Link number out of range */
#define EUNATCH 49 /* Protocol driver not attached */
#define ENOCSI 50 /* No CSI structure available */
#define EL2HLT 51 /* Level 2 halted */
#define EBADE 52 /* Invalid exchange */
#define EBADR 53 /* Invalid request descriptor */
#define EXFULL 54 /* Exchange full */
#define ENOANO 55 /* No anode */
#define EBADRQC 56 /* Invalid request code */
#define EBADSLT 57 /* Invalid slot */
#define EDEADLOCK 58 /* File locking deadlock error */
#define EBFONT 59 /* Bad font file format */
#define ENOSTR 60 /* Device not a stream */
#define ENODATA 61 /* No data available */
#define ETIME 62 /* Timer expired */
#define ENOSR 63 /* Out of streams resources */
#define ENONET 64 /* Machine is not on the network */
#define ENOPKG 65 /* Package not installed */
#define EREMOTE 66 /* Object is remote */
#define ENOLINK 67 /* Link has been severed */
#define EADV 68 /* Advertise error */
#define ESRMNT 69 /* Srmount error */
#define ECOMM 70 /* Communication error on send */
#define EPROTO 71 /* Protocol error */
#define EMULTIHOP 72 /* Multihop attempted */
#define EDOTDOT 73 /* RFS specific error */
#define EBADMSG 74 /* Not a data message */
#define EOVERFLOW 75 /* Value too large for defined data type */
#define ENOTUNIQ 76 /* Name not unique on network */
#define EBADFD 77 /* File descriptor in bad state */
#define EREMCHG 78 /* Remote address changed */
#define ELIBACC 79 /* Can not access a needed shared library */
#define ELIBBAD 80 /* Accessing a corrupted shared library */
#define ELIBSCN 81 /* .lib section in a.out corrupted */
#define ELIBMAX 82 /* Attempting to link in too many shared libraries */
#define ELIBEXEC 83 /* Cannot exec a shared library directly */
#define EILSEQ 84 /* Illegal byte sequence */
#define ERESTART 85 /* Interrupted system call should be restarted */
#define ESTRPIPE 86 /* Streams pipe error */
#define EUSERS 87 /* Too many users */
#define ENOTSOCK 88 /* Socket operation on non-socket */
#define EDESTADDRREQ 89 /* Destination address required */
#define EMSGSIZE 90 /* Message too long */
#define EPROTOTYPE 91 /* Protocol wrong type for socket */
#define ENOPROTOOPT 92 /* Protocol not available */
#define EPROTONOSUPPORT 93 /* Protocol not supported */
#define ESOCKTNOSUPPORT 94 /* Socket type not supported */
#define EOPNOTSUPP 95 /* Operation not supported on transport endpoint */
#define EPFNOSUPPORT 96 /* Protocol family not supported */
#define EAFNOSUPPORT 97 /* Address family not supported by protocol */
#define EADDRINUSE 98 /* Address already in use */
#define EADDRNOTAVAIL 99 /* Cannot assign requested address */
#define ENETDOWN 100 /* Network is down */
#define ENETUNREACH 101 /* Network is unreachable */
#define ENETRESET 102 /* Network dropped connection because of reset */
#define ECONNABORTED 103 /* Software caused connection abort */
#define ECONNRESET 104 /* Connection reset by peer */
#define ENOBUFS 105 /* No buffer space available */
#define EISCONN 106 /* Transport endpoint is already connected */
#define ENOTCONN 107 /* Transport endpoint is not connected */
#define ESHUTDOWN 108 /* Cannot send after transport endpoint shutdown */
#define ETOOMANYREFS 109 /* Too many references: cannot splice */
#define ETIMEDOUT 110 /* Connection timed out */
#define ECONNREFUSED 111 /* Connection refused */
#define EHOSTDOWN 112 /* Host is down */
#define EHOSTUNREACH 113 /* No route to host */
#define EALREADY 114 /* Operation already in progress */
#define EINPROGRESS 115 /* Operation now in progress */
#define ESTALE 116 /* Stale NFS file handle */
#define EUCLEAN 117 /* Structure needs cleaning */
#define ENOTNAM 118 /* Not a XENIX named type file */
#define ENAVAIL 119 /* No XENIX semaphores available */
#define EISNAM 120 /* Is a named type file */
#define EREMOTEIO 121 /* Remote I/O error */
#define EDQUOT 122 /* Quota exceeded */
#define ENOMEDIUM 123 /* No medium found */
#define EMEDIUMTYPE 124 /* Wrong medium type */
/* Should never be seen by user programs */
#define ERESTARTSYS 512
#define ERESTARTNOINTR 513
#define ERESTARTNOHAND 514 /* restart if no handler.. */
#define ENOIOCTLCMD 515 /* No ioctl command */
#define _LAST_ERRNO 515
#endif

277
include/asm-m68k/fec.h
View File

@@ -5,6 +5,10 @@
* MPC8xx Communication Processor Module.
* Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
*
* Add FEC Structure and definitions
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
@@ -30,9 +34,9 @@
/* Buffer descriptors used FEC.
*/
typedef struct cpm_buf_desc {
ushort cbd_sc; /* Status and Control */
ushort cbd_datlen; /* Data length in buffer */
uint cbd_bufaddr; /* Buffer address in host memory */
ushort cbd_sc; /* Status and Control */
ushort cbd_datlen; /* Data length in buffer */
uint cbd_bufaddr; /* Buffer address in host memory */
} cbd_t;
#define BD_SC_EMPTY ((ushort)0x8000) /* Recieve is empty */
@@ -53,28 +57,36 @@ typedef struct cpm_buf_desc {
/* Buffer descriptor control/status used by Ethernet receive.
*/
#define BD_ENET_RX_EMPTY ((ushort)0x8000)
#define BD_ENET_RX_RO1 ((ushort)0x4000)
#define BD_ENET_RX_WRAP ((ushort)0x2000)
#define BD_ENET_RX_INTR ((ushort)0x1000)
#define BD_ENET_RX_RO2 BD_ENET_RX_INTR
#define BD_ENET_RX_LAST ((ushort)0x0800)
#define BD_ENET_RX_FIRST ((ushort)0x0400)
#define BD_ENET_RX_MISS ((ushort)0x0100)
#define BD_ENET_RX_BC ((ushort)0x0080)
#define BD_ENET_RX_MC ((ushort)0x0040)
#define BD_ENET_RX_LG ((ushort)0x0020)
#define BD_ENET_RX_NO ((ushort)0x0010)
#define BD_ENET_RX_SH ((ushort)0x0008)
#define BD_ENET_RX_CR ((ushort)0x0004)
#define BD_ENET_RX_OV ((ushort)0x0002)
#define BD_ENET_RX_CL ((ushort)0x0001)
#define BD_ENET_RX_TR BD_ENET_RX_CL
#define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */
/* Buffer descriptor control/status used by Ethernet transmit.
*/
#define BD_ENET_TX_READY ((ushort)0x8000)
#define BD_ENET_TX_PAD ((ushort)0x4000)
#define BD_ENET_TX_TO1 BD_ENET_TX_PAD
#define BD_ENET_TX_WRAP ((ushort)0x2000)
#define BD_ENET_TX_INTR ((ushort)0x1000)
#define BD_ENET_TX_TO2 BD_ENET_TX_INTR_
#define BD_ENET_TX_LAST ((ushort)0x0800)
#define BD_ENET_TX_TC ((ushort)0x0400)
#define BD_ENET_TX_DEF ((ushort)0x0200)
#define BD_ENET_TX_ABC BD_ENET_TX_DEF
#define BD_ENET_TX_HB ((ushort)0x0100)
#define BD_ENET_TX_LC ((ushort)0x0080)
#define BD_ENET_TX_RL ((ushort)0x0040)
@@ -83,4 +95,261 @@ typedef struct cpm_buf_desc {
#define BD_ENET_TX_CSL ((ushort)0x0001)
#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */
#endif /* fec_h */
#ifdef CONFIG_MCFFEC
/*********************************************************************
*
* Fast Ethernet Controller (FEC)
*
*********************************************************************/
/* FEC private information */
struct fec_info_s {
int index;
u32 iobase;
u32 pinmux;
u32 miibase;
int phy_addr;
int dup_spd;
char *phy_name;
int phyname_init;
cbd_t *rxbd; /* Rx BD */
cbd_t *txbd; /* Tx BD */
uint rxIdx;
uint txIdx;
char *txbuf;
int initialized;
};
/* Register read/write struct */
typedef struct fec {
#ifdef CONFIG_M5272
u32 ecr; /* 0x00 */
u32 eir; /* 0x04 */
u32 eimr; /* 0x08 */
u32 ivsr; /* 0x0C */
u32 rdar; /* 0x10 */
u32 tdar; /* 0x14 */
u8 resv1[0x28]; /* 0x18 */
u32 mmfr; /* 0x40 */
u32 mscr; /* 0x44 */
u8 resv2[0x44]; /* 0x48 */
u32 frbr; /* 0x8C */
u32 frsr; /* 0x90 */
u8 resv3[0x10]; /* 0x94 */
u32 tfwr; /* 0xA4 */
u32 res4; /* 0xA8 */
u32 tfsr; /* 0xAC */
u8 resv4[0x50]; /* 0xB0 */
u32 opd; /* 0x100 - dummy */
u32 rcr; /* 0x104 */
u32 mibc; /* 0x108 */
u8 resv5[0x38]; /* 0x10C */
u32 tcr; /* 0x144 */
u8 resv6[0x270]; /* 0x148 */
u32 iaur; /* 0x3B8 - dummy */
u32 ialr; /* 0x3BC - dummy */
u32 palr; /* 0x3C0 */
u32 paur; /* 0x3C4 */
u32 gaur; /* 0x3C8 */
u32 galr; /* 0x3CC */
u32 erdsr; /* 0x3D0 */
u32 etdsr; /* 0x3D4 */
u32 emrbr; /* 0x3D8 */
u8 resv12[0x74]; /* 0x18C */
#else
u8 resv0[0x4];
u32 eir;
u32 eimr;
u8 resv1[0x4];
u32 rdar;
u32 tdar;
u8 resv2[0xC];
u32 ecr;
u8 resv3[0x18];
u32 mmfr;
u32 mscr;
u8 resv4[0x1C];
u32 mibc;
u8 resv5[0x1C];
u32 rcr;
u8 resv6[0x3C];
u32 tcr;
u8 resv7[0x1C];
u32 palr;
u32 paur;
u32 opd;
u8 resv8[0x28];
u32 iaur;
u32 ialr;
u32 gaur;
u32 galr;
u8 resv9[0x1C];
u32 tfwr;
u8 resv10[0x4];
u32 frbr;
u32 frsr;
u8 resv11[0x2C];
u32 erdsr;
u32 etdsr;
u32 emrbr;
u8 resv12[0x74];
#endif
u32 rmon_t_drop;
u32 rmon_t_packets;
u32 rmon_t_bc_pkt;
u32 rmon_t_mc_pkt;
u32 rmon_t_crc_align;
u32 rmon_t_undersize;
u32 rmon_t_oversize;
u32 rmon_t_frag;
u32 rmon_t_jab;
u32 rmon_t_col;
u32 rmon_t_p64;
u32 rmon_t_p65to127;
u32 rmon_t_p128to255;
u32 rmon_t_p256to511;
u32 rmon_t_p512to1023;
u32 rmon_t_p1024to2047;
u32 rmon_t_p_gte2048;
u32 rmon_t_octets;
u32 ieee_t_drop;
u32 ieee_t_frame_ok;
u32 ieee_t_1col;
u32 ieee_t_mcol;
u32 ieee_t_def;
u32 ieee_t_lcol;
u32 ieee_t_excol;
u32 ieee_t_macerr;
u32 ieee_t_cserr;
u32 ieee_t_sqe;
u32 ieee_t_fdxfc;
u32 ieee_t_octets_ok;
u8 resv13[0x8];
u32 rmon_r_drop;
u32 rmon_r_packets;
u32 rmon_r_bc_pkt;
u32 rmon_r_mc_pkt;
u32 rmon_r_crc_align;
u32 rmon_r_undersize;
u32 rmon_r_oversize;
u32 rmon_r_frag;
u32 rmon_r_jab;
u32 rmon_r_resvd_0;
u32 rmon_r_p64;
u32 rmon_r_p65to127;
u32 rmon_r_p128to255;
u32 rmon_r_p256to511;
u32 rmon_r_p512to1023;
u32 rmon_r_p1024to2047;
u32 rmon_r_p_gte2048;
u32 rmon_r_octets;
u32 ieee_r_drop;
u32 ieee_r_frame_ok;
u32 ieee_r_crc;
u32 ieee_r_align;
u32 ieee_r_macerr;
u32 ieee_r_fdxfc;
u32 ieee_r_octets_ok;
} fec_t;
/*********************************************************************
* Fast Ethernet Controller (FEC)
*********************************************************************/
/* Bit definitions and macros for FEC_EIR */
#define FEC_EIR_CLEAR_ALL (0xFFF80000)
#define FEC_EIR_HBERR (0x80000000)
#define FEC_EIR_BABR (0x40000000)
#define FEC_EIR_BABT (0x20000000)
#define FEC_EIR_GRA (0x10000000)
#define FEC_EIR_TXF (0x08000000)
#define FEC_EIR_TXB (0x04000000)
#define FEC_EIR_RXF (0x02000000)
#define FEC_EIR_RXB (0x01000000)
#define FEC_EIR_MII (0x00800000)
#define FEC_EIR_EBERR (0x00400000)
#define FEC_EIR_LC (0x00200000)
#define FEC_EIR_RL (0x00100000)
#define FEC_EIR_UN (0x00080000)
/* Bit definitions and macros for FEC_RDAR */
#define FEC_RDAR_R_DES_ACTIVE (0x01000000)
/* Bit definitions and macros for FEC_TDAR */
#define FEC_TDAR_X_DES_ACTIVE (0x01000000)
/* Bit definitions and macros for FEC_ECR */
#define FEC_ECR_ETHER_EN (0x00000002)
#define FEC_ECR_RESET (0x00000001)
/* Bit definitions and macros for FEC_MMFR */
#define FEC_MMFR_DATA(x) (((x)&0xFFFF))
#define FEC_MMFR_ST(x) (((x)&0x03)<<30)
#define FEC_MMFR_ST_01 (0x40000000)
#define FEC_MMFR_OP_RD (0x20000000)
#define FEC_MMFR_OP_WR (0x10000000)
#define FEC_MMFR_PA(x) (((x)&0x1F)<<23)
#define FEC_MMFR_RA(x) (((x)&0x1F)<<18)
#define FEC_MMFR_TA(x) (((x)&0x03)<<16)
#define FEC_MMFR_TA_10 (0x00020000)
/* Bit definitions and macros for FEC_MSCR */
#define FEC_MSCR_DIS_PREAMBLE (0x00000080)
#define FEC_MSCR_MII_SPEED(x) (((x)&0x3F)<<1)
/* Bit definitions and macros for FEC_MIBC */
#define FEC_MIBC_MIB_DISABLE (0x80000000)
#define FEC_MIBC_MIB_IDLE (0x40000000)
/* Bit definitions and macros for FEC_RCR */
#define FEC_RCR_MAX_FL(x) (((x)&0x7FF)<<16)
#define FEC_RCR_FCE (0x00000020)
#define FEC_RCR_BC_REJ (0x00000010)
#define FEC_RCR_PROM (0x00000008)
#define FEC_RCR_MII_MODE (0x00000004)
#define FEC_RCR_DRT (0x00000002)
#define FEC_RCR_LOOP (0x00000001)
/* Bit definitions and macros for FEC_TCR */
#define FEC_TCR_RFC_PAUSE (0x00000010)
#define FEC_TCR_TFC_PAUSE (0x00000008)
#define FEC_TCR_FDEN (0x00000004)
#define FEC_TCR_HBC (0x00000002)
#define FEC_TCR_GTS (0x00000001)
/* Bit definitions and macros for FEC_PAUR */
#define FEC_PAUR_PADDR2(x) (((x)&0xFFFF)<<16)
#define FEC_PAUR_TYPE(x) ((x)&0xFFFF)
/* Bit definitions and macros for FEC_OPD */
#define FEC_OPD_PAUSE_DUR(x) (((x)&0x0000FFFF)<<0)
#define FEC_OPD_OPCODE(x) (((x)&0x0000FFFF)<<16)
/* Bit definitions and macros for FEC_TFWR */
#define FEC_TFWR_X_WMRK(x) ((x)&0x03)
#define FEC_TFWR_X_WMRK_64 (0x01)
#define FEC_TFWR_X_WMRK_128 (0x02)
#define FEC_TFWR_X_WMRK_192 (0x03)
/* Bit definitions and macros for FEC_FRBR */
#define FEC_FRBR_R_BOUND(x) (((x)&0xFF)<<2)
/* Bit definitions and macros for FEC_FRSR */
#define FEC_FRSR_R_FSTART(x) (((x)&0xFF)<<2)
/* Bit definitions and macros for FEC_ERDSR */
#define FEC_ERDSR_R_DES_START(x) (((x)&0x3FFFFFFF)<<2)
/* Bit definitions and macros for FEC_ETDSR */
#define FEC_ETDSR_X_DES_START(x) (((x)&0x3FFFFFFF)<<2)
/* Bit definitions and macros for FEC_EMRBR */
#define FEC_EMRBR_R_BUF_SIZE(x) (((x)&0x7F)<<4)
#define FEC_RESET_DELAY 100
#define FEC_RX_TOUT 100
#endif /* CONFIG_MCFFEC */
#endif /* fec_h */

86
include/asm-m68k/fsl_i2c.h Normal file
View File

@@ -0,0 +1,86 @@
/*
* Freescale I2C Controller
*
* Copyright 2006 Freescale Semiconductor, Inc.
*
* Based on earlier versions by Gleb Natapov <gnatapov@mrv.com>,
* Xianghua Xiao <x.xiao@motorola.com>, Eran Liberty (liberty@freescale.com),
* and Jeff Brown.
* Some bits are taken from linux driver writen by adrian@humboldt.co.uk.
*
* This software may be used and distributed according to the
* terms of the GNU Public License, Version 2, incorporated
* herein by reference.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* Version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _ASM_FSL_I2C_H_
#define _ASM_FSL_I2C_H_
#include <asm/types.h>
typedef struct fsl_i2c {
u8 adr; /* I2C slave address */
u8 res0[3];
#define I2C_ADR 0xFE
#define I2C_ADR_SHIFT 1
#define I2C_ADR_RES ~(I2C_ADR)
u8 fdr; /* I2C frequency divider register */
u8 res1[3];
#define IC2_FDR 0x3F
#define IC2_FDR_SHIFT 0
#define IC2_FDR_RES ~(IC2_FDR)
u8 cr; /* I2C control redister */
u8 res2[3];
#define I2C_CR_MEN 0x80
#define I2C_CR_MIEN 0x40
#define I2C_CR_MSTA 0x20
#define I2C_CR_MTX 0x10
#define I2C_CR_TXAK 0x08
#define I2C_CR_RSTA 0x04
#define I2C_CR_BCST 0x01
u8 sr; /* I2C status register */
u8 res3[3];
#define I2C_SR_MCF 0x80
#define I2C_SR_MAAS 0x40
#define I2C_SR_MBB 0x20
#define I2C_SR_MAL 0x10
#define I2C_SR_BCSTM 0x08
#define I2C_SR_SRW 0x04
#define I2C_SR_MIF 0x02
#define I2C_SR_RXAK 0x01
u8 dr; /* I2C data register */
u8 res4[3];
#define I2C_DR 0xFF
#define I2C_DR_SHIFT 0
#define I2C_DR_RES ~(I2C_DR)
u8 dfsrr; /* I2C digital filter sampling rate register */
u8 res5[3];
#define I2C_DFSRR 0x3F
#define I2C_DFSRR_SHIFT 0
#define I2C_DFSRR_RES ~(I2C_DR)
/* Fill out the reserved block */
u8 res6[0xE8];
} fsl_i2c_t;
#endif /* _ASM_I2C_H_ */

8
include/asm-m68k/global_data.h
View File

@@ -39,6 +39,14 @@ typedef struct global_data {
unsigned long baudrate;
unsigned long cpu_clk; /* CPU clock in Hz! */
unsigned long bus_clk;
#ifdef CONFIG_PCI
unsigned long pci_clk;
#endif
#ifdef CONFIG_EXTRA_CLOCK
unsigned long inp_clk;
unsigned long vco_clk;
unsigned long flb_clk;
#endif
unsigned long ram_size; /* RAM size */
unsigned long reloc_off; /* Relocation Offset */
unsigned long reset_status; /* reset status register at boot */

242
include/asm-m68k/immap.h Normal file
View File

@@ -0,0 +1,242 @@
/*
* ColdFire Internal Memory Map and Defines
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __IMMAP_H
#define __IMMAP_H
#ifdef CONFIG_M5235
#include <asm/immap_5235.h>
#include <asm/m5235.h>
#define CFG_FEC0_IOBASE (MMAP_FEC)
#define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x40))
/* Timer */
#ifdef CONFIG_MCFTMR
#define CFG_UDELAY_BASE (MMAP_DTMR0)
#define CFG_TMR_BASE (MMAP_DTMR3)
#define CFG_TMRPND_REG (((volatile int0_t *)(CFG_INTR_BASE))->iprl0)
#define CFG_TMRINTR_NO (INT0_LO_DTMR3)
#define CFG_TMRINTR_MASK (INTC_IPRL_INT22)
#define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK)
#define CFG_TMRINTR_PRI (0x1E) /* Level must include inorder to work */
#define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
#endif
#ifdef CONFIG_MCFPIT
#define CFG_UDELAY_BASE (MMAP_PIT0)
#define CFG_PIT_BASE (MMAP_PIT1)
#define CFG_PIT_PRESCALE (6)
#endif
#define CFG_INTR_BASE (MMAP_INTC0)
#define CFG_NUM_IRQS (128)
#endif /* CONFIG_M5235 */
#ifdef CONFIG_M5249
#include <asm/immap_5249.h>
#include <asm/m5249.h>
#define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x40))
#define CFG_INTR_BASE (MMAP_INTC)
#define CFG_NUM_IRQS (64)
/* Timer */
#ifdef CONFIG_MCFTMR
#define CFG_UDELAY_BASE (MMAP_DTMR0)
#define CFG_TMR_BASE (MMAP_DTMR1)
#define CFG_TMRPND_REG (mbar_readLong(MCFSIM_IPR))
#define CFG_TMRINTR_NO (31)
#define CFG_TMRINTR_MASK (0x00000400)
#define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK)
#define CFG_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3)
#define CFG_TIMER_PRESCALER (((gd->bus_clk / 2000000) - 1) << 8)
#endif
#endif /* CONFIG_M5249 */
#ifdef CONFIG_M5253
#include <asm/immap_5253.h>
#include <asm/m5249.h>
#include <asm/m5253.h>
#define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x40))
#define CFG_INTR_BASE (MMAP_INTC)
#define CFG_NUM_IRQS (64)
/* Timer */
#ifdef CONFIG_MCFTMR
#define CFG_UDELAY_BASE (MMAP_DTMR0)
#define CFG_TMR_BASE (MMAP_DTMR1)
#define CFG_TMRPND_REG (mbar_readLong(MCFSIM_IPR))
#define CFG_TMRINTR_NO (27)
#define CFG_TMRINTR_MASK (0x00000400)
#define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK)
#define CFG_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL3 | MCFSIM_ICR_PRI3)
#define CFG_TIMER_PRESCALER (((gd->bus_clk / 2000000) - 1) << 8)
#endif
#endif /* CONFIG_M5253 */
#ifdef CONFIG_M5271
#include <asm/immap_5271.h>
#include <asm/m5271.h>
#define CFG_FEC0_IOBASE (MMAP_FEC)
#define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x40))
/* Timer */
#ifdef CONFIG_MCFTMR
#define CFG_UDELAY_BASE (MMAP_DTMR0)
#define CFG_TMR_BASE (MMAP_DTMR3)
#define CFG_TMRPND_REG (((volatile int0_t *)(CFG_INTR_BASE))->iprl0)
#define CFG_TMRINTR_NO (INT0_LO_DTMR3)
#define CFG_TMRINTR_MASK (INTC_IPRL_INT22)
#define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK)
#define CFG_TMRINTR_PRI (0) /* Level must include inorder to work */
#define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
#endif
#define CFG_INTR_BASE (MMAP_INTC0)
#define CFG_NUM_IRQS (128)
#endif /* CONFIG_M5271 */
#ifdef CONFIG_M5272
#include <asm/immap_5272.h>
#include <asm/m5272.h>
#define CFG_FEC0_IOBASE (MMAP_FEC)
#define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x40))
#define CFG_INTR_BASE (MMAP_INTC)
#define CFG_NUM_IRQS (64)
/* Timer */
#ifdef CONFIG_MCFTMR
#define CFG_UDELAY_BASE (MMAP_TMR0)
#define CFG_TMR_BASE (MMAP_TMR3)
#define CFG_TMRPND_REG (((volatile intctrl_t *)(CFG_INTR_BASE))->int_isr)
#define CFG_TMRINTR_NO (INT_TMR3)
#define CFG_TMRINTR_MASK (INT_ISR_INT24)
#define CFG_TMRINTR_PEND (0)
#define CFG_TMRINTR_PRI (INT_ICR1_TMR3PI | INT_ICR1_TMR3IPL(5))
#define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
#endif
#endif /* CONFIG_M5272 */
#ifdef CONFIG_M5282
#include <asm/immap_5282.h>
#include <asm/m5282.h>
#define CFG_FEC0_IOBASE (MMAP_FEC)
#define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x40))
#define CFG_INTR_BASE (MMAP_INTC0)
#define CFG_NUM_IRQS (128)
/* Timer */
#ifdef CONFIG_MCFTMR
#define CFG_UDELAY_BASE (MMAP_DTMR0)
#define CFG_TMR_BASE (MMAP_DTMR3)
#define CFG_TMRPND_REG (((volatile int0_t *)(CFG_INTR_BASE))->iprl0)
#define CFG_TMRINTR_NO (INT0_LO_DTMR3)
#define CFG_TMRINTR_MASK (1 << INT0_LO_DTMR3)
#define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK)
#define CFG_TMRINTR_PRI (0x1E) /* Level must include inorder to work */
#define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
#endif
#endif /* CONFIG_M5282 */
#ifdef CONFIG_M5329
#include <asm/immap_5329.h>
#include <asm/m5329.h>
#define CFG_FEC0_IOBASE (MMAP_FEC)
#define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x4000))
#define CFG_MCFRTC_BASE (MMAP_RTC)
/* Timer */
#ifdef CONFIG_MCFTMR
#define CFG_UDELAY_BASE (MMAP_DTMR0)
#define CFG_TMR_BASE (MMAP_DTMR1)
#define CFG_TMRPND_REG (((volatile int0_t *)(CFG_INTR_BASE))->iprh0)
#define CFG_TMRINTR_NO (INT0_HI_DTMR1)
#define CFG_TMRINTR_MASK (INTC_IPRH_INT33)
#define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK)
#define CFG_TMRINTR_PRI (6)
#define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
#endif
#ifdef CONFIG_MCFPIT
#define CFG_UDELAY_BASE (MMAP_PIT0)
#define CFG_PIT_BASE (MMAP_PIT1)
#define CFG_PIT_PRESCALE (6)
#endif
#define CFG_INTR_BASE (MMAP_INTC0)
#define CFG_NUM_IRQS (128)
#endif /* CONFIG_M5329 */
#ifdef CONFIG_M54455
#include <asm/immap_5445x.h>
#include <asm/m5445x.h>
#define CFG_FEC0_IOBASE (MMAP_FEC0)
#define CFG_FEC1_IOBASE (MMAP_FEC1)
#define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x4000))
#define CFG_MCFRTC_BASE (MMAP_RTC)
/* Timer */
#ifdef CONFIG_MCFTMR
#define CFG_UDELAY_BASE (MMAP_DTMR0)
#define CFG_TMR_BASE (MMAP_DTMR1)
#define CFG_TMRPND_REG (((volatile int0_t *)(CFG_INTR_BASE))->iprh0)
#define CFG_TMRINTR_NO (INT0_HI_DTMR1)
#define CFG_TMRINTR_MASK (INTC_IPRH_INT33)
#define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK)
#define CFG_TMRINTR_PRI (6)
#define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
#endif
#ifdef CONFIG_MCFPIT
#define CFG_UDELAY_BASE (MMAP_PIT0)
#define CFG_PIT_BASE (MMAP_PIT1)
#define CFG_PIT_PRESCALE (6)
#endif
#define CFG_INTR_BASE (MMAP_INTC0)
#define CFG_NUM_IRQS (128)
#ifdef CONFIG_PCI
#define CFG_PCI_BAR0 CFG_SDRAM_BASE
#define CFG_PCI_BAR4 CFG_SDRAM_BASE
#define CFG_PCI_TBATR0 (CFG_SDRAM_BASE)
#define CFG_PCI_TBATR4 (CFG_SDRAM_BASE)
#endif
#endif /* CONFIG_M54455 */
#endif /* __IMMAP_H */

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/*
* MCF5329 Internal Memory Map
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __IMMAP_5235__
#define __IMMAP_5235__
#define MMAP_SCM (CFG_MBAR + 0x00000000)
#define MMAP_SDRAM (CFG_MBAR + 0x00000040)
#define MMAP_FBCS (CFG_MBAR + 0x00000080)
#define MMAP_DMA0 (CFG_MBAR + 0x00000100)
#define MMAP_DMA1 (CFG_MBAR + 0x00000110)
#define MMAP_DMA2 (CFG_MBAR + 0x00000120)
#define MMAP_DMA3 (CFG_MBAR + 0x00000130)
#define MMAP_UART0 (CFG_MBAR + 0x00000200)
#define MMAP_UART1 (CFG_MBAR + 0x00000240)
#define MMAP_UART2 (CFG_MBAR + 0x00000280)
#define MMAP_I2C (CFG_MBAR + 0x00000300)
#define MMAP_QSPI (CFG_MBAR + 0x00000340)
#define MMAP_DTMR0 (CFG_MBAR + 0x00000400)
#define MMAP_DTMR1 (CFG_MBAR + 0x00000440)
#define MMAP_DTMR2 (CFG_MBAR + 0x00000480)
#define MMAP_DTMR3 (CFG_MBAR + 0x000004C0)
#define MMAP_INTC0 (CFG_MBAR + 0x00000C00)
#define MMAP_INTC1 (CFG_MBAR + 0x00000D00)
#define MMAP_INTCACK (CFG_MBAR + 0x00000F00)
#define MMAP_FEC (CFG_MBAR + 0x00001000)
#define MMAP_FECFIFO (CFG_MBAR + 0x00001400)
#define MMAP_GPIO (CFG_MBAR + 0x00100000)
#define MMAP_CCM (CFG_MBAR + 0x00110000)
#define MMAP_PLL (CFG_MBAR + 0x00120000)
#define MMAP_EPORT (CFG_MBAR + 0x00130000)
#define MMAP_WDOG (CFG_MBAR + 0x00140000)
#define MMAP_PIT0 (CFG_MBAR + 0x00150000)
#define MMAP_PIT1 (CFG_MBAR + 0x00160000)
#define MMAP_PIT2 (CFG_MBAR + 0x00170000)
#define MMAP_PIT3 (CFG_MBAR + 0x00180000)
#define MMAP_MDHA (CFG_MBAR + 0x00190000)
#define MMAP_RNG (CFG_MBAR + 0x001A0000)
#define MMAP_SKHA (CFG_MBAR + 0x001B0000)
#define MMAP_CAN1 (CFG_MBAR + 0x001C0000)
#define MMAP_ETPU (CFG_MBAR + 0x001D0000)
#define MMAP_CAN2 (CFG_MBAR + 0x001F0000)
/* System Control Module register */
typedef struct scm_ctrl {
u32 ipsbar; /* 0x00 - MBAR */
u32 res1; /* 0x04 */
u32 rambar; /* 0x08 - RAMBAR */
u32 res2; /* 0x0C */
u8 crsr; /* 0x10 Core Reset Status Register */
u8 cwcr; /* 0x11 Core Watchdog Control Register */
u8 lpicr; /* 0x12 Low-Power Interrupt Control Register */
u8 cwsr; /* 0x13 Core Watchdog Service Register */
u32 dmareqc; /* 0x14 */
u32 res3; /* 0x18 */
u32 mpark; /* 0x1C */
u8 mpr; /* 0x20 */
u8 res4[3]; /* 0x21 - 0x23 */
u8 pacr0; /* 0x24 */
u8 pacr1; /* 0x25 */
u8 pacr2; /* 0x26 */
u8 pacr3; /* 0x27 */
u8 pacr4; /* 0x28 */
u32 res5; /* 0x29 */
u8 pacr5; /* 0x2a */
u8 pacr6; /* 0x2b */
u8 pacr7; /* 0x2c */
u32 res6; /* 0x2d */
u8 pacr8; /* 0x2e */
u32 res7; /* 0x2f */
u8 gpacr; /* 0x30 */
u8 res8[3]; /* 0x31 - 0x33 */
} scm_t;
/* SDRAM controller registers */
typedef struct sdram_ctrl {
u16 dcr; /* 0x00 Control register */
u16 res1[3]; /* 0x02 - 0x07 */
u32 dacr0; /* 0x08 address and control register 0 */
u32 dmr0; /* 0x0C mask register block 0 */
u32 dacr1; /* 0x10 address and control register 1 */
u32 dmr1; /* 0x14 mask register block 1 */
} sdram_t;
/* Flexbus module Chip select registers */
typedef struct fbcs_ctrl {
u16 csar0; /* 0x00 Chip-Select Address Register 0 */
u16 res0;
u32 csmr0; /* 0x04 Chip-Select Mask Register 0 */
u16 res1; /* 0x08 */
u16 cscr0; /* 0x0A Chip-Select Control Register 0 */
u16 csar1; /* 0x0C Chip-Select Address Register 1 */
u16 res2;
u32 csmr1; /* 0x10 Chip-Select Mask Register 1 */
u16 res3; /* 0x14 */
u16 cscr1; /* 0x16 Chip-Select Control Register 1 */
u16 csar2; /* 0x18 Chip-Select Address Register 2 */
u16 res4;
u32 csmr2; /* 0x1C Chip-Select Mask Register 2 */
u16 res5; /* 0x20 */
u16 cscr2; /* 0x22 Chip-Select Control Register 2 */
u16 csar3; /* 0x24 Chip-Select Address Register 3 */
u16 res6;
u32 csmr3; /* 0x28 Chip-Select Mask Register 3 */
u16 res7; /* 0x2C */
u16 cscr3; /* 0x2E Chip-Select Control Register 3 */
u16 csar4; /* 0x30 Chip-Select Address Register 4 */
u16 res8;
u32 csmr4; /* 0x34 Chip-Select Mask Register 4 */
u16 res9; /* 0x38 */
u16 cscr4; /* 0x3A Chip-Select Control Register 4 */
u16 csar5; /* 0x3C Chip-Select Address Register 5 */
u16 res10;
u32 csmr5; /* 0x40 Chip-Select Mask Register 5 */
u16 res11; /* 0x44 */
u16 cscr5; /* 0x46 Chip-Select Control Register 5 */
u16 csar6; /* 0x48 Chip-Select Address Register 5 */
u16 res12;
u32 csmr6; /* 0x4C Chip-Select Mask Register 5 */
u16 res13; /* 0x50 */
u16 cscr6; /* 0x52 Chip-Select Control Register 5 */
u16 csar7; /* 0x54 Chip-Select Address Register 5 */
u16 res14;
u32 csmr7; /* 0x58 Chip-Select Mask Register 5 */
u16 res15; /* 0x5C */
u16 cscr7; /* 0x5E Chip-Select Control Register 5 */
} fbcs_t;
/* QSPI module registers */
typedef struct qspi_ctrl {
u16 qmr; /* Mode register */
u16 res1;
u16 qdlyr; /* Delay register */
u16 res2;
u16 qwr; /* Wrap register */
u16 res3;
u16 qir; /* Interrupt register */
u16 res4;
u16 qar; /* Address register */
u16 res5;
u16 qdr; /* Data register */
u16 res6;
} qspi_t;
/* Interrupt module registers */
typedef struct int0_ctrl {
/* Interrupt Controller 0 */
u32 iprh0; /* 0x00 Pending Register High */
u32 iprl0; /* 0x04 Pending Register Low */
u32 imrh0; /* 0x08 Mask Register High */
u32 imrl0; /* 0x0C Mask Register Low */
u32 frch0; /* 0x10 Force Register High */
u32 frcl0; /* 0x14 Force Register Low */
u8 irlr; /* 0x18 */
u8 iacklpr; /* 0x19 */
u16 res1[19]; /* 0x1a - 0x3c */
u8 icr0[64]; /* 0x40 - 0x7F Control registers */
u32 res3[24]; /* 0x80 - 0xDF */
u8 swiack0; /* 0xE0 Software Interrupt Acknowledge */
u8 res4[3]; /* 0xE1 - 0xE3 */
u8 Lniack0_1; /* 0xE4 Level n interrupt acknowledge resister */
u8 res5[3]; /* 0xE5 - 0xE7 */
u8 Lniack0_2; /* 0xE8 Level n interrupt acknowledge resister */
u8 res6[3]; /* 0xE9 - 0xEB */
u8 Lniack0_3; /* 0xEC Level n interrupt acknowledge resister */
u8 res7[3]; /* 0xED - 0xEF */
u8 Lniack0_4; /* 0xF0 Level n interrupt acknowledge resister */
u8 res8[3]; /* 0xF1 - 0xF3 */
u8 Lniack0_5; /* 0xF4 Level n interrupt acknowledge resister */
u8 res9[3]; /* 0xF5 - 0xF7 */
u8 Lniack0_6; /* 0xF8 Level n interrupt acknowledge resister */
u8 resa[3]; /* 0xF9 - 0xFB */
u8 Lniack0_7; /* 0xFC Level n interrupt acknowledge resister */
u8 resb[3]; /* 0xFD - 0xFF */
} int0_t;
typedef struct int1_ctrl {
/* Interrupt Controller 1 */
u32 iprh1; /* 0x00 Pending Register High */
u32 iprl1; /* 0x04 Pending Register Low */
u32 imrh1; /* 0x08 Mask Register High */
u32 imrl1; /* 0x0C Mask Register Low */
u32 frch1; /* 0x10 Force Register High */
u32 frcl1; /* 0x14 Force Register Low */
u8 irlr; /* 0x18 */
u8 iacklpr; /* 0x19 */
u16 res1[19]; /* 0x1a - 0x3c */
u8 icr1[64]; /* 0x40 - 0x7F */
u32 res4[24]; /* 0x80 - 0xDF */
u8 swiack1; /* 0xE0 Software Interrupt Acknowledge */
u8 res5[3]; /* 0xE1 - 0xE3 */
u8 Lniack1_1; /* 0xE4 Level n interrupt acknowledge resister */
u8 res6[3]; /* 0xE5 - 0xE7 */
u8 Lniack1_2; /* 0xE8 Level n interrupt acknowledge resister */
u8 res7[3]; /* 0xE9 - 0xEB */
u8 Lniack1_3; /* 0xEC Level n interrupt acknowledge resister */
u8 res8[3]; /* 0xED - 0xEF */
u8 Lniack1_4; /* 0xF0 Level n interrupt acknowledge resister */
u8 res9[3]; /* 0xF1 - 0xF3 */
u8 Lniack1_5; /* 0xF4 Level n interrupt acknowledge resister */
u8 resa[3]; /* 0xF5 - 0xF7 */
u8 Lniack1_6; /* 0xF8 Level n interrupt acknowledge resister */
u8 resb[3]; /* 0xF9 - 0xFB */
u8 Lniack1_7; /* 0xFC Level n interrupt acknowledge resister */
u8 resc[3]; /* 0xFD - 0xFF */
} int1_t;
typedef struct intgack_ctrl1 {
/* Global IACK Registers */
u8 swiack; /* 0xE0 Global Software Interrupt Acknowledge */
u8 Lniack[7]; /* 0xE1 - 0xE7 Global Level 0 Interrupt Acknowledge */
} intgack_t;
/* GPIO port registers */
typedef struct gpio_ctrl {
/* Port Output Data Registers */
u8 podr_addr; /* 0x00 */
u8 podr_datah; /* 0x01 */
u8 podr_datal; /* 0x02 */
u8 podr_busctl; /* 0x03 */
u8 podr_bs; /* 0x04 */
u8 podr_cs; /* 0x05 */
u8 podr_sdram; /* 0x06 */
u8 podr_feci2c; /* 0x07 */
u8 podr_uarth; /* 0x08 */
u8 podr_uartl; /* 0x09 */
u8 podr_qspi; /* 0x0A */
u8 podr_timer; /* 0x0B */
u8 podr_etpu; /* 0x0C */
u8 res1[3]; /* 0x0D - 0x0F */
/* Port Data Direction Registers */
u8 pddr_addr; /* 0x10 */
u8 pddr_datah; /* 0x11 */
u8 pddr_datal; /* 0x12 */
u8 pddr_busctl; /* 0x13 */
u8 pddr_bs; /* 0x14 */
u8 pddr_cs; /* 0x15 */
u8 pddr_sdram; /* 0x16 */
u8 pddr_feci2c; /* 0x17 */
u8 pddr_uarth; /* 0x18 */
u8 pddr_uartl; /* 0x19 */
u8 pddr_qspi; /* 0x1A */
u8 pddr_timer; /* 0x1B */
u8 pddr_etpu; /* 0x1C */
u8 res2[3]; /* 0x1D - 0x1F */
/* Port Data Direction Registers */
u8 ppdsdr_addr; /* 0x20 */
u8 ppdsdr_datah; /* 0x21 */
u8 ppdsdr_datal; /* 0x22 */
u8 ppdsdr_busctl; /* 0x23 */
u8 ppdsdr_bs; /* 0x24 */
u8 ppdsdr_cs; /* 0x25 */
u8 ppdsdr_sdram; /* 0x26 */
u8 ppdsdr_feci2c; /* 0x27 */
u8 ppdsdr_uarth; /* 0x28 */
u8 ppdsdr_uartl; /* 0x29 */
u8 ppdsdr_qspi; /* 0x2A */
u8 ppdsdr_timer; /* 0x2B */
u8 ppdsdr_etpu; /* 0x2C */
u8 res3[3]; /* 0x2D - 0x2F */
/* Port Clear Output Data Registers */
u8 pclrr_addr; /* 0x30 */
u8 pclrr_datah; /* 0x31 */
u8 pclrr_datal; /* 0x32 */
u8 pclrr_busctl; /* 0x33 */
u8 pclrr_bs; /* 0x34 */
u8 pclrr_cs; /* 0x35 */
u8 pclrr_sdram; /* 0x36 */
u8 pclrr_feci2c; /* 0x37 */
u8 pclrr_uarth; /* 0x38 */
u8 pclrr_uartl; /* 0x39 */
u8 pclrr_qspi; /* 0x3A */
u8 pclrr_timer; /* 0x3B */
u8 pclrr_etpu; /* 0x3C */
u8 res4[3]; /* 0x3D - 0x3F */
/* Pin Assignment Registers */
u8 par_ad; /* 0x40 */
u8 res5; /* 0x41 */
u16 par_busctl; /* 0x42 */
u8 par_bs; /* 0x44 */
u8 par_cs; /* 0x45 */
u8 par_sdram; /* 0x46 */
u8 par_feci2c; /* 0x47 */
u16 par_uart; /* 0x48 */
u8 par_qspi; /* 0x4A */
u8 res6; /* 0x4B */
u16 par_timer; /* 0x4C */
u8 par_etpu; /* 0x4E */
u8 res7; /* 0x4F */
/* Drive Strength Control Registers */
u8 dscr_eim; /* 0x50 */
u8 dscr_etpu; /* 0x51 */
u8 dscr_feci2c; /* 0x52 */
u8 dscr_uart; /* 0x53 */
u8 dscr_qspi; /* 0x54 */
u8 dscr_timer; /* 0x55 */
u16 res8; /* 0x56 */
} gpio_t;
/*Chip configuration module registers */
typedef struct ccm_ctrl {
u8 rcr; /* 0x01 */
u8 rsr; /* 0x02 */
u16 res1; /* 0x03 */
u16 ccr; /* 0x04 Chip configuration register */
u16 lpcr; /* 0x06 Low-power Control register */
u16 rcon; /* 0x08 Rreset configuration register */
u16 cir; /* 0x0a Chip identification register */
} ccm_t;
/* Clock Module registers */
typedef struct pll_ctrl {
u32 syncr; /* 0x00 synthesizer control register */
u32 synsr; /* 0x04 synthesizer status register */
} pll_t;
/* Watchdog registers */
typedef struct wdog_ctrl {
u16 cr; /* 0x00 Control register */
u16 mr; /* 0x02 Modulus register */
u16 cntr; /* 0x04 Count register */
u16 sr; /* 0x06 Service register */
} wdog_t;
/* FlexCan module registers */
typedef struct can_ctrl {
u32 mcr; /* 0x00 Module Configuration register */
u32 ctrl; /* 0x04 Control register */
u32 timer; /* 0x08 Free Running Timer */
u32 res1; /* 0x0C */
u32 rxgmask; /* 0x10 Rx Global Mask */
u32 rx14mask; /* 0x14 RxBuffer 14 Mask */
u32 rx15mask; /* 0x18 RxBuffer 15 Mask */
u32 errcnt; /* 0x1C Error Counter Register */
u32 errstat; /* 0x20 Error and status Register */
u32 res2; /* 0x24 */
u32 imask; /* 0x28 Interrupt Mask Register */
u32 res3; /* 0x2C */
u32 iflag; /* 0x30 Interrupt Flag Register */
u32 res4[19]; /* 0x34 - 0x7F */
u32 MB0_15[2048]; /* 0x80 Message Buffer 0-15 */
} can_t;
#endif /* __IMMAP_5235__ */

22
include/asm-m68k/immap_5249.h
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@@ -25,19 +25,11 @@
#ifndef __IMMAP_5249__
#define __IMMAP_5249__
/* Timer module registers
*/
typedef struct timer_ctrl {
ushort timer_tmr;
ushort res1;
ushort timer_trr;
ushort res2;
ushort timer_tcap;
ushort res3;
ushort timer_tcn;
ushort res4;
ushort timer_ter;
uchar res5[14];
} timer_t;
#define MMAP_INTC (CFG_MBAR + 0x00000040)
#define MMAP_DTMR0 (CFG_MBAR + 0x00000140)
#define MMAP_DTMR1 (CFG_MBAR + 0x00000180)
#define MMAP_UART0 (CFG_MBAR + 0x000001C0)
#define MMAP_UART1 (CFG_MBAR + 0x00000200)
#define MMAP_QSPI (CFG_MBAR + 0x00000400)
#endif /* __IMMAP_5249__ */
#endif /* __IMMAP_5249__ */

95
include/asm-m68k/immap_5253.h Normal file
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@@ -0,0 +1,95 @@
/*
* MCF5253 Internal Memory Map
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __IMMAP_5249__
#define __IMMAP_5249__
#define MMAP_INTC (CFG_MBAR + 0x00000040)
#define MMAP_DTMR0 (CFG_MBAR + 0x00000140)
#define MMAP_DTMR1 (CFG_MBAR + 0x00000180)
#define MMAP_UART0 (CFG_MBAR + 0x000001C0)
#define MMAP_UART1 (CFG_MBAR + 0x00000200)
#define MMAP_I2C0 (CFG_MBAR + 0x00000280)
#define MMAP_QSPI (CFG_MBAR + 0x00000400)
#define MMAP_CAN0 (CFG_MBAR + 0x00010000)
#define MMAP_CAN1 (CFG_MBAR + 0x00011000)
#define MMAP_I2C1 (CFG_MBAR2 + 0x00000440)
#define MMAP_UART2 (CFG_MBAR2 + 0x00000C00)
/*********************************************************************
* ATA Module (ATAC)
*********************************************************************/
/* Register read/write struct */
typedef struct atac {
/* PIO */
u8 toff; /* 0x00 */
u8 ton; /* 0x01 */
u8 t1; /* 0x02 */
u8 t2w; /* 0x03 */
u8 t2r; /* 0x04 */
u8 ta; /* 0x05 */
u8 trd; /* 0x06 */
u8 t4; /* 0x07 */
u8 t9; /* 0x08 */
/* DMA */
u8 tm; /* 0x09 */
u8 tn; /* 0x0A */
u8 td; /* 0x0B */
u8 tk; /* 0x0C */
u8 tack; /* 0x0D */
u8 tenv; /* 0x0E */
u8 trp; /* 0x0F */
u8 tzah; /* 0x10 */
u8 tmli; /* 0x11 */
u8 tdvh; /* 0x12 */
u8 tdzfs; /* 0x13 */
u8 tdvs; /* 0x14 */
u8 tcvh; /* 0x15 */
u8 tss; /* 0x16 */
u8 tcyc; /* 0x17 */
/* FIFO */
u32 fifo32; /* 0x18 */
u16 fifo16; /* 0x1C */
u8 rsvd0[2];
u8 ffill; /* 0x20 */
u8 rsvd1[3];
/* ATA */
u8 cr; /* 0x24 */
u8 rsvd2[3];
u8 isr; /* 0x28 */
u8 rsvd3[3];
u8 ier; /* 0x2C */
u8 rsvd4[3];
u8 icr; /* 0x30 */
u8 rsvd5[3];
u8 falarm; /* 0x34 */
} atac_t;
#endif /* __IMMAP_5249__ */

136
include/asm-m68k/immap_5271.h
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@@ -26,73 +26,73 @@
#ifndef __IMMAP_5271__
#define __IMMAP_5271__
/* Interrupt module registers
*/
typedef struct int_ctrl {
uint int_icr1;
uint int_icr2;
uint int_icr3;
uint int_icr4;
uint int_isr;
uint int_pitr;
uint int_piwr;
uchar res1[3];
uchar int_pivr;
} intctrl_t;
#define MMAP_SCM (CFG_MBAR + 0x00000000)
#define MMAP_SDRAM (CFG_MBAR + 0x00000040)
#define MMAP_FBCS (CFG_MBAR + 0x00000080)
#define MMAP_DMA0 (CFG_MBAR + 0x00000100)
#define MMAP_DMA1 (CFG_MBAR + 0x00000110)
#define MMAP_DMA2 (CFG_MBAR + 0x00000120)
#define MMAP_DMA3 (CFG_MBAR + 0x00000130)
#define MMAP_UART0 (CFG_MBAR + 0x00000200)
#define MMAP_UART1 (CFG_MBAR + 0x00000240)
#define MMAP_UART2 (CFG_MBAR + 0x00000280)
#define MMAP_I2C (CFG_MBAR + 0x00000300)
#define MMAP_QSPI (CFG_MBAR + 0x00000340)
#define MMAP_DTMR0 (CFG_MBAR + 0x00000400)
#define MMAP_DTMR1 (CFG_MBAR + 0x00000440)
#define MMAP_DTMR2 (CFG_MBAR + 0x00000480)
#define MMAP_DTMR3 (CFG_MBAR + 0x000004C0)
#define MMAP_INTC0 (CFG_MBAR + 0x00000C00)
#define MMAP_INTC1 (CFG_MBAR + 0x00000D00)
#define MMAP_INTCACK (CFG_MBAR + 0x00000F00)
#define MMAP_FEC (CFG_MBAR + 0x00001000)
#define MMAP_FECFIFO (CFG_MBAR + 0x00001400)
#define MMAP_GPIO (CFG_MBAR + 0x00100000)
#define MMAP_CCM (CFG_MBAR + 0x00110000)
#define MMAP_PLL (CFG_MBAR + 0x00120000)
#define MMAP_EPORT (CFG_MBAR + 0x00130000)
#define MMAP_WDOG (CFG_MBAR + 0x00140000)
#define MMAP_PIT0 (CFG_MBAR + 0x00150000)
#define MMAP_PIT1 (CFG_MBAR + 0x00160000)
#define MMAP_PIT2 (CFG_MBAR + 0x00170000)
#define MMAP_PIT3 (CFG_MBAR + 0x00180000)
#define MMAP_MDHA (CFG_MBAR + 0x00190000)
#define MMAP_RNG (CFG_MBAR + 0x001A0000)
#define MMAP_SKHA (CFG_MBAR + 0x001B0000)
#define MMAP_CAN1 (CFG_MBAR + 0x001C0000)
#define MMAP_ETPU (CFG_MBAR + 0x001D0000)
#define MMAP_CAN2 (CFG_MBAR + 0x001F0000)
/* Timer module registers
*/
typedef struct timer_ctrl {
ushort timer_tmr;
ushort res1;
ushort timer_trr;
ushort res2;
ushort timer_tcap;
ushort res3;
ushort timer_tcn;
ushort res4;
ushort timer_ter;
uchar res5[14];
} timer_t;
/* Interrupt module registers */
typedef struct int0_ctrl {
/* Interrupt Controller 0 */
u32 iprh0; /* 0x00 Pending Register High */
u32 iprl0; /* 0x04 Pending Register Low */
u32 imrh0; /* 0x08 Mask Register High */
u32 imrl0; /* 0x0C Mask Register Low */
u32 frch0; /* 0x10 Force Register High */
u32 frcl0; /* 0x14 Force Register Low */
u8 irlr; /* 0x18 */
u8 iacklpr; /* 0x19 */
u16 res1[19]; /* 0x1a - 0x3c */
u8 icr0[64]; /* 0x40 - 0x7F Control registers */
u32 res3[24]; /* 0x80 - 0xDF */
u8 swiack0; /* 0xE0 Software Interrupt Acknowledge */
u8 res4[3]; /* 0xE1 - 0xE3 */
u8 Lniack0_1; /* 0xE4 Level n interrupt acknowledge resister */
u8 res5[3]; /* 0xE5 - 0xE7 */
u8 Lniack0_2; /* 0xE8 Level n interrupt acknowledge resister */
u8 res6[3]; /* 0xE9 - 0xEB */
u8 Lniack0_3; /* 0xEC Level n interrupt acknowledge resister */
u8 res7[3]; /* 0xED - 0xEF */
u8 Lniack0_4; /* 0xF0 Level n interrupt acknowledge resister */
u8 res8[3]; /* 0xF1 - 0xF3 */
u8 Lniack0_5; /* 0xF4 Level n interrupt acknowledge resister */
u8 res9[3]; /* 0xF5 - 0xF7 */
u8 Lniack0_6; /* 0xF8 Level n interrupt acknowledge resister */
u8 resa[3]; /* 0xF9 - 0xFB */
u8 Lniack0_7; /* 0xFC Level n interrupt acknowledge resister */
u8 resb[3]; /* 0xFD - 0xFF */
} int0_t;
/* Fast ethernet controller registers
*/
typedef struct fec {
uint res1;
uint fec_ievent;
uint fec_imask;
uint res2;
uint fec_r_des_active;
uint fec_x_des_active;
uint res3[3];
uint fec_ecntrl;
uint res4[6];
uint fec_mii_data;
uint fec_mii_speed;
uint res5[7];
uint fec_mibc;
uint res6[7];
uint fec_r_cntrl;
uint res7[15];
uint fec_x_cntrl;
uint res8[7];
uint fec_addr_low;
uint fec_addr_high;
uint fec_opd;
uint res9[10];
uint fec_ihash_table_high;
uint fec_ihash_table_low;
uint fec_ghash_table_high;
uint fec_ghash_table_low;
uint res10[7];
uint fec_tfwr;
uint res11;
uint fec_r_bound;
uint fec_r_fstart;
uint res12[11];
uint fec_r_des_start;
uint fec_x_des_start;
uint fec_r_buff_size;
} fec_t;
#endif /* __IMMAP_5271__ */
#endif /* __IMMAP_5271__ */

689
include/asm-m68k/immap_5272.h
View File

@@ -25,423 +25,326 @@
#ifndef __IMMAP_5272__
#define __IMMAP_5272__
/* System configuration registers
*/
typedef struct sys_ctrl {
uint sc_mbar;
ushort sc_scr;
ushort sc_spr;
uint sc_pmr;
char res1[2];
ushort sc_alpr;
uint sc_dir;
char res2[12];
#define MMAP_CFG (CFG_MBAR + 0x00000000)
#define MMAP_INTC (CFG_MBAR + 0x00000020)
#define MMAP_FBCS (CFG_MBAR + 0x00000040)
#define MMAP_GPIO (CFG_MBAR + 0x00000080)
#define MMAP_QSPI (CFG_MBAR + 0x000000A0)
#define MMAP_PWM (CFG_MBAR + 0x000000C0)
#define MMAP_DMA0 (CFG_MBAR + 0x000000E0)
#define MMAP_UART0 (CFG_MBAR + 0x00000100)
#define MMAP_UART1 (CFG_MBAR + 0x00000140)
#define MMAP_SDRAM (CFG_MBAR + 0x00000180)
#define MMAP_TMR0 (CFG_MBAR + 0x00000200)
#define MMAP_TMR1 (CFG_MBAR + 0x00000220)
#define MMAP_TMR2 (CFG_MBAR + 0x00000240)
#define MMAP_TMR3 (CFG_MBAR + 0x00000260)
#define MMAP_WDOG (CFG_MBAR + 0x00000280)
#define MMAP_PLIC (CFG_MBAR + 0x00000300)
#define MMAP_FEC (CFG_MBAR + 0x00000840)
#define MMAP_USB (CFG_MBAR + 0x00001000)
/* System configuration registers */
typedef struct sys_ctrl {
uint sc_mbar;
ushort sc_scr;
ushort sc_spr;
uint sc_pmr;
char res1[2];
ushort sc_alpr;
uint sc_dir;
char res2[12];
} sysctrl_t;
/* Interrupt module registers
*/
/* Interrupt module registers */
typedef struct int_ctrl {
uint int_icr1;
uint int_icr2;
uint int_icr3;
uint int_icr4;
uint int_isr;
uint int_pitr;
uint int_piwr;
uchar res1[3];
uchar int_pivr;
uint int_icr1;
uint int_icr2;
uint int_icr3;
uint int_icr4;
uint int_isr;
uint int_pitr;
uint int_piwr;
uchar res1[3];
uchar int_pivr;
} intctrl_t;
/* Chip select module registers.
*/
typedef struct cs_ctlr {
uint cs_br0;
uint cs_or0;
uint cs_br1;
uint cs_or1;
uint cs_br2;
uint cs_or2;
uint cs_br3;
uint cs_or3;
uint cs_br4;
uint cs_or4;
uint cs_br5;
uint cs_or5;
uint cs_br6;
uint cs_or6;
uint cs_br7;
uint cs_or7;
/* Chip select module registers */
typedef struct cs_ctlr {
uint cs_br0;
uint cs_or0;
uint cs_br1;
uint cs_or1;
uint cs_br2;
uint cs_or2;
uint cs_br3;
uint cs_or3;
uint cs_br4;
uint cs_or4;
uint cs_br5;
uint cs_or5;
uint cs_br6;
uint cs_or6;
uint cs_br7;
uint cs_or7;
} csctrl_t;
/* GPIO port registers
*/
typedef struct gpio_ctrl {
uint gpio_pacnt;
ushort gpio_paddr;
ushort gpio_padat;
uint gpio_pbcnt;
ushort gpio_pbddr;
ushort gpio_pbdat;
uchar res1[4];
ushort gpio_pcddr;
ushort gpio_pcdat;
uint gpio_pdcnt;
uchar res2[4];
/* GPIO port registers */
typedef struct gpio_ctrl {
uint gpio_pacnt;
ushort gpio_paddr;
ushort gpio_padat;
uint gpio_pbcnt;
ushort gpio_pbddr;
ushort gpio_pbdat;
uchar res1[4];
ushort gpio_pcddr;
ushort gpio_pcdat;
uint gpio_pdcnt;
uchar res2[4];
} gpio_t;
/* QSPI module registers
*/
typedef struct qspi_ctrl {
ushort qspi_qmr;
uchar res1[2];
ushort qspi_qdlyr;
uchar res2[2];
ushort qspi_qwr;
uchar res3[2];
ushort qspi_qir;
uchar res4[2];
ushort qspi_qar;
uchar res5[2];
ushort qspi_qdr;
uchar res6[10];
/* QSPI module registers */
typedef struct qspi_ctrl {
ushort qspi_qmr;
uchar res1[2];
ushort qspi_qdlyr;
uchar res2[2];
ushort qspi_qwr;
uchar res3[2];
ushort qspi_qir;
uchar res4[2];
ushort qspi_qar;
uchar res5[2];
ushort qspi_qdr;
uchar res6[10];
} qspi_t;
/* PWM module registers
*/
typedef struct pwm_ctrl {
uchar pwm_pwcr0;
uchar res1[3];
uchar pwm_pwcr1;
uchar res2[3];
uchar pwm_pwcr2;
uchar res3[7];
uchar pwm_pwwd0;
uchar res4[3];
uchar pwm_pwwd1;
uchar res5[3];
uchar pwm_pwwd2;
uchar res6[7];
/* PWM module registers */
typedef struct pwm_ctrl {
uchar pwm_pwcr0;
uchar res1[3];
uchar pwm_pwcr1;
uchar res2[3];
uchar pwm_pwcr2;
uchar res3[7];
uchar pwm_pwwd0;
uchar res4[3];
uchar pwm_pwwd1;
uchar res5[3];
uchar pwm_pwwd2;
uchar res6[7];
} pwm_t;
/* DMA module registers
*/
typedef struct dma_ctrl {
ulong dma_dmr;
uchar res1[2];
ushort dma_dir;
ulong dma_dbcr;
ulong dma_dsar;
ulong dma_ddar;
uchar res2[12];
/* DMA module registers */
typedef struct dma_ctrl {
ulong dma_dmr;
uchar res1[2];
ushort dma_dir;
ulong dma_dbcr;
ulong dma_dsar;
ulong dma_ddar;
uchar res2[12];
} dma_t;
/* UART module registers
*/
typedef struct uart_ctrl {
uchar uart_umr;
uchar res1[3];
uchar uart_usr_ucsr;
uchar res2[3];
uchar uart_ucr;
uchar res3[3];
uchar uart_urb_utb;
uchar res4[3];
uchar uart_uipcr_uacr;
uchar res5[3];
uchar uart_uisr_uimr;
uchar res6[3];
uchar uart_udu;
uchar res7[3];
uchar uart_udl;
uchar res8[3];
uchar uart_uabu;
uchar res9[3];
uchar uart_uabl;
uchar res10[3];
uchar uart_utf;
uchar res11[3];
uchar uart_urf;
uchar res12[3];
uchar uart_ufpd;
uchar res13[3];
uchar uart_uip;
uchar res14[3];
uchar uart_uop1;
uchar res15[3];
uchar uart_uop0;
uchar res16[3];
} uart_t;
/* SDRAM controller registers, offset: 0x180
*/
/* SDRAM controller registers, offset: 0x180 */
typedef struct sdram_ctrl {
uchar res1[2];
ushort sdram_sdcr;
uchar res2[2];
ushort sdram_sdtr;
uchar res3[120];
uchar res1[2];
ushort sdram_sdcr;
uchar res2[2];
ushort sdram_sdtr;
uchar res3[120];
} sdramctrl_t;
/* Timer module registers
*/
typedef struct timer_ctrl {
ushort timer_tmr;
ushort res1;
ushort timer_trr;
ushort res2;
ushort timer_tcap;
ushort res3;
ushort timer_tcn;
ushort res4;
ushort timer_ter;
uchar res5[14];
} timer_t;
/* Watchdog registers
*/
/* Watchdog registers */
typedef struct wdog_ctrl {
ushort wdog_wrrr;
ushort res1;
ushort wdog_wirr;
ushort res2;
ushort wdog_wcr;
ushort res3;
ushort wdog_wer;
uchar res4[114];
ushort wdog_wrrr;
ushort res1;
ushort wdog_wirr;
ushort res2;
ushort wdog_wcr;
ushort res3;
ushort wdog_wer;
uchar res4[114];
} wdog_t;
/* PLIC module registers
*/
/* PLIC module registers */
typedef struct plic_ctrl {
ulong plic_p0b1rr;
ulong plic_p1b1rr;
ulong plic_p2b1rr;
ulong plic_p3b1rr;
ulong plic_p0b2rr;
ulong plic_p1b2rr;
ulong plic_p2b2rr;
ulong plic_p3b2rr;
uchar plic_p0drr;
uchar plic_p1drr;
uchar plic_p2drr;
uchar plic_p3drr;
uchar res1[4];
ulong plic_p0b1tr;
ulong plic_p1b1tr;
ulong plic_p2b1tr;
ulong plic_p3b1tr;
ulong plic_p0b2tr;
ulong plic_p1b2tr;
ulong plic_p2b2tr;
ulong plic_p3b2tr;
uchar plic_p0dtr;
uchar plic_p1dtr;
uchar plic_p2dtr;
uchar plic_p3dtr;
uchar res2[4];
ushort plic_p0cr;
ushort plic_p1cr;
ushort plic_p2cr;
ushort plic_p3cr;
ushort plic_p0icr;
ushort plic_p1icr;
ushort plic_p2icr;
ushort plic_p3icr;
ushort plic_p0gmr;
ushort plic_p1gmr;
ushort plic_p2gmr;
ushort plic_p3gmr;
ushort plic_p0gmt;
ushort plic_p1gmt;
ushort plic_p2gmt;
ushort plic_p3gmt;
uchar res3;
uchar plic_pgmts;
uchar plic_pgmta;
uchar res4;
uchar plic_p0gcir;
uchar plic_p1gcir;
uchar plic_p2gcir;
uchar plic_p3gcir;
uchar plic_p0gcit;
uchar plic_p1gcit;
uchar plic_p2gcit;
uchar plic_p3gcit;
uchar res5[3];
uchar plic_pgcitsr;
uchar res6[3];
uchar plic_pdcsr;
ushort plic_p0psr;
ushort plic_p1psr;
ushort plic_p2psr;
ushort plic_p3psr;
ushort plic_pasr;
uchar res7;
uchar plic_plcr;
ushort res8;
ushort plic_pdrqr;
ushort plic_p0sdr;
ushort plic_p1sdr;
ushort plic_p2sdr;
ushort plic_p3sdr;
ushort res9;
ushort plic_pcsr;
uchar res10[1184];
ulong plic_p0b1rr;
ulong plic_p1b1rr;
ulong plic_p2b1rr;
ulong plic_p3b1rr;
ulong plic_p0b2rr;
ulong plic_p1b2rr;
ulong plic_p2b2rr;
ulong plic_p3b2rr;
uchar plic_p0drr;
uchar plic_p1drr;
uchar plic_p2drr;
uchar plic_p3drr;
uchar res1[4];
ulong plic_p0b1tr;
ulong plic_p1b1tr;
ulong plic_p2b1tr;
ulong plic_p3b1tr;
ulong plic_p0b2tr;
ulong plic_p1b2tr;
ulong plic_p2b2tr;
ulong plic_p3b2tr;
uchar plic_p0dtr;
uchar plic_p1dtr;
uchar plic_p2dtr;
uchar plic_p3dtr;
uchar res2[4];
ushort plic_p0cr;
ushort plic_p1cr;
ushort plic_p2cr;
ushort plic_p3cr;
ushort plic_p0icr;
ushort plic_p1icr;
ushort plic_p2icr;
ushort plic_p3icr;
ushort plic_p0gmr;
ushort plic_p1gmr;
ushort plic_p2gmr;
ushort plic_p3gmr;
ushort plic_p0gmt;
ushort plic_p1gmt;
ushort plic_p2gmt;
ushort plic_p3gmt;
uchar res3;
uchar plic_pgmts;
uchar plic_pgmta;
uchar res4;
uchar plic_p0gcir;
uchar plic_p1gcir;
uchar plic_p2gcir;
uchar plic_p3gcir;
uchar plic_p0gcit;
uchar plic_p1gcit;
uchar plic_p2gcit;
uchar plic_p3gcit;
uchar res5[3];
uchar plic_pgcitsr;
uchar res6[3];
uchar plic_pdcsr;
ushort plic_p0psr;
ushort plic_p1psr;
ushort plic_p2psr;
ushort plic_p3psr;
ushort plic_pasr;
uchar res7;
uchar plic_plcr;
ushort res8;
ushort plic_pdrqr;
ushort plic_p0sdr;
ushort plic_p1sdr;
ushort plic_p2sdr;
ushort plic_p3sdr;
ushort res9;
ushort plic_pcsr;
uchar res10[1184];
} plic_t;
/* Fast ethernet controller registers
*/
typedef struct fec {
uint fec_ecntrl; /* ethernet control register */
uint fec_ievent; /* interrupt event register */
uint fec_imask; /* interrupt mask register */
uint fec_ivec; /* interrupt level and vector status */
uint fec_r_des_active; /* Rx ring updated flag */
uint fec_x_des_active; /* Tx ring updated flag */
uint res3[10]; /* reserved */
uint fec_mii_data; /* MII data register */
uint fec_mii_speed; /* MII speed control register */
uint res4[17]; /* reserved */
uint fec_r_bound; /* end of RAM (read-only) */
uint fec_r_fstart; /* Rx FIFO start address */
uint res5[6]; /* reserved */
uint fec_x_fstart; /* Tx FIFO start address */
uint res7[21]; /* reserved */
uint fec_r_cntrl; /* Rx control register */
uint fec_r_hash; /* Rx hash register */
uint res8[14]; /* reserved */
uint fec_x_cntrl; /* Tx control register */
uint res9[0x9e]; /* reserved */
uint fec_addr_low; /* lower 32 bits of station address */
uint fec_addr_high; /* upper 16 bits of station address */
uint fec_hash_table_high; /* upper 32-bits of hash table */
uint fec_hash_table_low; /* lower 32-bits of hash table */
uint fec_r_des_start; /* beginning of Rx descriptor ring */
uint fec_x_des_start; /* beginning of Tx descriptor ring */
uint fec_r_buff_size; /* Rx buffer size */
uint res2[9]; /* reserved */
uchar fec_fifo[960]; /* fifo RAM */
} fec_t;
/* USB module registers
*/
/* USB module registers */
typedef struct usb {
ushort res1;
ushort usb_fnr;
ushort res2;
ushort usb_fnmr;
ushort res3;
ushort usb_rfmr;
ushort res4;
ushort usb_rfmmr;
uchar res5[3];
uchar usb_far;
ulong usb_asr;
ulong usb_drr1;
ulong usb_drr2;
ushort res6;
ushort usb_specr;
ushort res7;
ushort usb_ep0sr;
ulong usb_iep0cfg;
ulong usb_oep0cfg;
ulong usb_ep1cfg;
ulong usb_ep2cfg;
ulong usb_ep3cfg;
ulong usb_ep4cfg;
ulong usb_ep5cfg;
ulong usb_ep6cfg;
ulong usb_ep7cfg;
ulong usb_ep0ctl;
ushort res8;
ushort usb_ep1ctl;
ushort res9;
ushort usb_ep2ctl;
ushort res10;
ushort usb_ep3ctl;
ushort res11;
ushort usb_ep4ctl;
ushort res12;
ushort usb_ep5ctl;
ushort res13;
ushort usb_ep6ctl;
ushort res14;
ushort usb_ep7ctl;
ulong usb_ep0isr;
ushort res15;
ushort usb_ep1isr;
ushort res16;
ushort usb_ep2isr;
ushort res17;
ushort usb_ep3isr;
ushort res18;
ushort usb_ep4isr;
ushort res19;
ushort usb_ep5isr;
ushort res20;
ushort usb_ep6isr;
ushort res21;
ushort usb_ep7isr;
ulong usb_ep0imr;
ushort res22;
ushort usb_ep1imr;
ushort res23;
ushort usb_ep2imr;
ushort res24;
ushort usb_ep3imr;
ushort res25;
ushort usb_ep4imr;
ushort res26;
ushort usb_ep5imr;
ushort res27;
ushort usb_ep6imr;
ushort res28;
ushort usb_ep7imr;
ulong usb_ep0dr;
ulong usb_ep1dr;
ulong usb_ep2dr;
ulong usb_ep3dr;
ulong usb_ep4dr;
ulong usb_ep5dr;
ulong usb_ep6dr;
ulong usb_ep7dr;
ushort res29;
ushort usb_ep0dpr;
ushort res30;
ushort usb_ep1dpr;
ushort res31;
ushort usb_ep2dpr;
ushort res32;
ushort usb_ep3dpr;
ushort res33;
ushort usb_ep4dpr;
ushort res34;
ushort usb_ep5dpr;
ushort res35;
ushort usb_ep6dpr;
ushort res36;
ushort usb_ep7dpr;
uchar res37[788];
uchar usb_cfgram[1024];
ushort res1;
ushort usb_fnr;
ushort res2;
ushort usb_fnmr;
ushort res3;
ushort usb_rfmr;
ushort res4;
ushort usb_rfmmr;
uchar res5[3];
uchar usb_far;
ulong usb_asr;
ulong usb_drr1;
ulong usb_drr2;
ushort res6;
ushort usb_specr;
ushort res7;
ushort usb_ep0sr;
ulong usb_iep0cfg;
ulong usb_oep0cfg;
ulong usb_ep1cfg;
ulong usb_ep2cfg;
ulong usb_ep3cfg;
ulong usb_ep4cfg;
ulong usb_ep5cfg;
ulong usb_ep6cfg;
ulong usb_ep7cfg;
ulong usb_ep0ctl;
ushort res8;
ushort usb_ep1ctl;
ushort res9;
ushort usb_ep2ctl;
ushort res10;
ushort usb_ep3ctl;
ushort res11;
ushort usb_ep4ctl;
ushort res12;
ushort usb_ep5ctl;
ushort res13;
ushort usb_ep6ctl;
ushort res14;
ushort usb_ep7ctl;
ulong usb_ep0isr;
ushort res15;
ushort usb_ep1isr;
ushort res16;
ushort usb_ep2isr;
ushort res17;
ushort usb_ep3isr;
ushort res18;
ushort usb_ep4isr;
ushort res19;
ushort usb_ep5isr;
ushort res20;
ushort usb_ep6isr;
ushort res21;
ushort usb_ep7isr;
ulong usb_ep0imr;
ushort res22;
ushort usb_ep1imr;
ushort res23;
ushort usb_ep2imr;
ushort res24;
ushort usb_ep3imr;
ushort res25;
ushort usb_ep4imr;
ushort res26;
ushort usb_ep5imr;
ushort res27;
ushort usb_ep6imr;
ushort res28;
ushort usb_ep7imr;
ulong usb_ep0dr;
ulong usb_ep1dr;
ulong usb_ep2dr;
ulong usb_ep3dr;
ulong usb_ep4dr;
ulong usb_ep5dr;
ulong usb_ep6dr;
ulong usb_ep7dr;
ushort res29;
ushort usb_ep0dpr;
ushort res30;
ushort usb_ep1dpr;
ushort res31;
ushort usb_ep2dpr;
ushort res32;
ushort usb_ep3dpr;
ushort res33;
ushort usb_ep4dpr;
ushort res34;
ushort usb_ep5dpr;
ushort res35;
ushort usb_ep6dpr;
ushort res36;
ushort usb_ep7dpr;
uchar res37[788];
uchar usb_cfgram[1024];
} usb_t;
/* Internal memory map.
*/
typedef struct immap {
sysctrl_t sysctrl_reg; /* System configuration registers */
intctrl_t intctrl_reg; /* Interrupt controller registers */
csctrl_t csctrl_reg; /* Chip select controller registers */
gpio_t gpio_reg; /* GPIO controller registers */
qspi_t qspi_reg; /* QSPI controller registers */
pwm_t pwm_reg; /* Pulse width modulation registers */
dma_t dma_reg; /* DMA registers */
uart_t uart_reg[2]; /* UART registers */
sdramctrl_t sdram_reg; /* SDRAM controller registers */
timer_t timer_reg[4]; /* Timer registers */
wdog_t wdog_reg; /* Watchdog registers */
plic_t plic_reg; /* Physical layer interface registers */
fec_t fec_reg; /* Fast ethernet controller registers */
usb_t usb_reg; /* USB controller registers */
} immap_t;
#endif /* __IMMAP_5272__ */
#endif /* __IMMAP_5272__ */

217
include/asm-m68k/immap_5282.h
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@@ -25,61 +25,168 @@
#ifndef __IMMAP_5282__
#define __IMMAP_5282__
struct sys_ctrl {
uint ipsbar;
char res1[4];
uint rambar;
char res2[4];
uchar crsr;
uchar cwcr;
uchar lpicr;
uchar cwsr;
uint dmareqc;
char res3[4];
uint mpark;
#define MMAP_SCM (CFG_MBAR + 0x00000000)
#define MMAP_SDRAMC (CFG_MBAR + 0x00000040)
#define MMAP_FBCS (CFG_MBAR + 0x00000080)
#define MMAP_DMA0 (CFG_MBAR + 0x00000100)
#define MMAP_DMA1 (CFG_MBAR + 0x00000140)
#define MMAP_DMA2 (CFG_MBAR + 0x00000180)
#define MMAP_DMA3 (CFG_MBAR + 0x000001C0)
#define MMAP_UART0 (CFG_MBAR + 0x00000200)
#define MMAP_UART1 (CFG_MBAR + 0x00000240)
#define MMAP_UART2 (CFG_MBAR + 0x00000280)
#define MMAP_I2C (CFG_MBAR + 0x00000300)
#define MMAP_QSPI (CFG_MBAR + 0x00000340)
#define MMAP_DTMR0 (CFG_MBAR + 0x00000400)
#define MMAP_DTMR1 (CFG_MBAR + 0x00000440)
#define MMAP_DTMR2 (CFG_MBAR + 0x00000480)
#define MMAP_DTMR3 (CFG_MBAR + 0x000004C0)
#define MMAP_INTC0 (CFG_MBAR + 0x00000C00)
#define MMAP_INTC1 (CFG_MBAR + 0x00000D00)
#define MMAP_INTCACK (CFG_MBAR + 0x00000F00)
#define MMAP_FEC (CFG_MBAR + 0x00001000)
#define MMAP_FECFIFO (CFG_MBAR + 0x00001400)
#define MMAP_GPIO (CFG_MBAR + 0x00100000)
#define MMAP_CCM (CFG_MBAR + 0x00110000)
#define MMAP_PLL (CFG_MBAR + 0x00120000)
#define MMAP_EPORT (CFG_MBAR + 0x00130000)
#define MMAP_WDOG (CFG_MBAR + 0x00140000)
#define MMAP_PIT0 (CFG_MBAR + 0x00150000)
#define MMAP_PIT1 (CFG_MBAR + 0x00160000)
#define MMAP_PIT2 (CFG_MBAR + 0x00170000)
#define MMAP_PIT3 (CFG_MBAR + 0x00180000)
#define MMAP_QADC (CFG_MBAR + 0x00190000)
#define MMAP_GPTMRA (CFG_MBAR + 0x001A0000)
#define MMAP_GPTMRB (CFG_MBAR + 0x001B0000)
#define MMAP_CAN (CFG_MBAR + 0x001C0000)
#define MMAP_CFMC (CFG_MBAR + 0x001D0000)
#define MMAP_CFMMEM (CFG_MBAR + 0x04000000)
/* TODO: finish these */
};
/* System Control Module */
typedef struct scm_ctrl {
u32 ipsbar;
u32 res1;
u32 rambar;
u32 res2;
u8 crsr;
u8 cwcr;
u8 lpicr;
u8 cwsr;
u32 res3;
u8 mpark;
u8 res4[3];
u8 pacr0;
u8 pacr1;
u8 pacr2;
u8 pacr3;
u8 pacr4;
u8 res5;
u8 pacr5;
u8 pacr6;
u8 pacr7;
u8 res6;
u8 pacr8;
u8 res7;
u8 gpacr0;
u8 gpacr1;
u16 res8;
} scm_t;
/* Fast ethernet controller registers
*/
typedef struct fec {
uint res1; /* reserved 1000*/
uint fec_ievent; /* interrupt event register 1004*/ /* EIR */
uint fec_imask; /* interrupt mask register 1008*/ /* EIMR */
uint res2; /* reserved 100c*/
uint fec_r_des_active; /* Rx ring updated flag 1010*/ /* RDAR */
uint fec_x_des_active; /* Tx ring updated flag 1014*/ /* XDAR */
uint res3[3]; /* reserved 1018*/
uint fec_ecntrl; /* ethernet control register 1024*/ /* ECR */
uint res4[6]; /* reserved 1028*/
uint fec_mii_data; /* MII data register 1040*/ /* MDATA */
uint fec_mii_speed; /* MII speed control register 1044*/ /* MSCR */
/*1044*/
uint res5[7]; /* reserved 1048*/
uint fec_mibc; /* MIB Control/Status register 1064*/ /* MIBC */
uint res6[7]; /* reserved 1068*/
uint fec_r_cntrl; /* Rx control register 1084*/ /* RCR */
uint res7[15]; /* reserved 1088*/
uint fec_x_cntrl; /* Tx control register 10C4*/ /* TCR */
uint res8[7]; /* reserved 10C8*/
uint fec_addr_low; /* lower 32 bits of station address */ /* PALR */
uint fec_addr_high; /* upper 16 bits of station address */ /* PAUR */
uint fec_opd; /* opcode + pause duration 10EC*/ /* OPD */
uint res9[10]; /* reserved 10F0*/
uint fec_ihash_table_high; /* upper 32-bits of individual hash */ /* IAUR */
uint fec_ihash_table_low; /* lower 32-bits of individual hash */ /* IALR */
uint fec_ghash_table_high; /* upper 32-bits of group hash */ /* GAUR */
uint fec_ghash_table_low; /* lower 32-bits of group hash */ /* GALR */
uint res10[7]; /* reserved 1128*/
uint fec_tfwr; /* Transmit FIFO watermark 1144*/ /* TFWR */
uint res11; /* reserved 1148*/
uint fec_r_bound; /* FIFO Receive Bound Register = end of */ /* FRBR */
uint fec_r_fstart; /* FIFO Receive FIfo Start Registers = */ /* FRSR */
uint res12[11]; /* reserved 1154*/
uint fec_r_des_start;/* beginning of Rx descriptor ring 1180*/ /* ERDSR */
uint fec_x_des_start;/* beginning of Tx descriptor ring 1184*/ /* ETDSR */
uint fec_r_buff_size;/* Rx buffer size 1188*/ /* EMRBR */
} fec_t;
/* Flexbus module Chip select registers */
typedef struct fbcs_ctrl {
u16 csar0; /* 0x00 Chip-Select Address Register 0 */
u16 res0;
u32 csmr0; /* 0x04 Chip-Select Mask Register 0 */
u16 res1; /* 0x08 */
u16 cscr0; /* 0x0A Chip-Select Control Register 0 */
#endif /* __IMMAP_5282__ */
u16 csar1; /* 0x0C Chip-Select Address Register 1 */
u16 res2;
u32 csmr1; /* 0x10 Chip-Select Mask Register 1 */
u16 res3; /* 0x14 */
u16 cscr1; /* 0x16 Chip-Select Control Register 1 */
u16 csar2; /* 0x18 Chip-Select Address Register 2 */
u16 res4;
u32 csmr2; /* 0x1C Chip-Select Mask Register 2 */
u16 res5; /* 0x20 */
u16 cscr2; /* 0x22 Chip-Select Control Register 2 */
u16 csar3; /* 0x24 Chip-Select Address Register 3 */
u16 res6;
u32 csmr3; /* 0x28 Chip-Select Mask Register 3 */
u16 res7; /* 0x2C */
u16 cscr3; /* 0x2E Chip-Select Control Register 3 */
u16 csar4; /* 0x30 Chip-Select Address Register 4 */
u16 res8;
u32 csmr4; /* 0x34 Chip-Select Mask Register 4 */
u16 res9; /* 0x38 */
u16 cscr4; /* 0x3A Chip-Select Control Register 4 */
u16 csar5; /* 0x3C Chip-Select Address Register 5 */
u16 res10;
u32 csmr5; /* 0x40 Chip-Select Mask Register 5 */
u16 res11; /* 0x44 */
u16 cscr5; /* 0x46 Chip-Select Control Register 5 */
u16 csar6; /* 0x48 Chip-Select Address Register 5 */
u16 res12;
u32 csmr6; /* 0x4C Chip-Select Mask Register 5 */
u16 res13; /* 0x50 */
u16 cscr6; /* 0x52 Chip-Select Control Register 5 */
u16 csar7; /* 0x54 Chip-Select Address Register 5 */
u16 res14;
u32 csmr7; /* 0x58 Chip-Select Mask Register 5 */
u16 res15; /* 0x5C */
u16 cscr7; /* 0x5E Chip-Select Control Register 5 */
} fbcs_t;
/* Interrupt module registers */
typedef struct int0_ctrl {
/* Interrupt Controller 0 */
u32 iprh0; /* 0x00 Pending Register High */
u32 iprl0; /* 0x04 Pending Register Low */
u32 imrh0; /* 0x08 Mask Register High */
u32 imrl0; /* 0x0C Mask Register Low */
u32 frch0; /* 0x10 Force Register High */
u32 frcl0; /* 0x14 Force Register Low */
u8 irlr; /* 0x18 */
u8 iacklpr; /* 0x19 */
u16 res1[19]; /* 0x1a - 0x3c */
u8 icr0[64]; /* 0x40 - 0x7F Control registers */
u32 res3[24]; /* 0x80 - 0xDF */
u8 swiack0; /* 0xE0 Software Interrupt Acknowledge */
u8 res4[3]; /* 0xE1 - 0xE3 */
u8 Lniack0_1; /* 0xE4 Level n interrupt acknowledge resister */
u8 res5[3]; /* 0xE5 - 0xE7 */
u8 Lniack0_2; /* 0xE8 Level n interrupt acknowledge resister */
u8 res6[3]; /* 0xE9 - 0xEB */
u8 Lniack0_3; /* 0xEC Level n interrupt acknowledge resister */
u8 res7[3]; /* 0xED - 0xEF */
u8 Lniack0_4; /* 0xF0 Level n interrupt acknowledge resister */
u8 res8[3]; /* 0xF1 - 0xF3 */
u8 Lniack0_5; /* 0xF4 Level n interrupt acknowledge resister */
u8 res9[3]; /* 0xF5 - 0xF7 */
u8 Lniack0_6; /* 0xF8 Level n interrupt acknowledge resister */
u8 resa[3]; /* 0xF9 - 0xFB */
u8 Lniack0_7; /* 0xFC Level n interrupt acknowledge resister */
u8 resb[3]; /* 0xFD - 0xFF */
} int0_t;
/* Clock Module registers */
typedef struct pll_ctrl {
u16 syncr; /* 0x00 synthesizer control register */
u16 synsr; /* 0x02 synthesizer status register */
} pll_t;
/* Watchdog registers */
typedef struct wdog_ctrl {
ushort wcr;
ushort wmr;
ushort wcntr;
ushort wsr;
} wdog_t;
#endif /* __IMMAP_5282__ */

793
include/asm-m68k/immap_5329.h Normal file
View File

@@ -0,0 +1,793 @@
/*
* MCF5329 Internal Memory Map
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __IMMAP_5329__
#define __IMMAP_5329__
#define MMAP_SCM1 0xEC000000
#define MMAP_MDHA 0xEC080000
#define MMAP_SKHA 0xEC084000
#define MMAP_RNG 0xEC088000
#define MMAP_SCM2 0xFC000000
#define MMAP_XBS 0xFC004000
#define MMAP_FBCS 0xFC008000
#define MMAP_CAN 0xFC020000
#define MMAP_FEC 0xFC030000
#define MMAP_SCM3 0xFC040000
#define MMAP_EDMA 0xFC044000
#define MMAP_TCD 0xFC045000
#define MMAP_INTC0 0xFC048000
#define MMAP_INTC1 0xFC04C000
#define MMAP_INTCACK 0xFC054000
#define MMAP_I2C 0xFC058000
#define MMAP_QSPI 0xFC05C000
#define MMAP_UART0 0xFC060000
#define MMAP_UART1 0xFC064000
#define MMAP_UART2 0xFC068000
#define MMAP_DTMR0 0xFC070000
#define MMAP_DTMR1 0xFC074000
#define MMAP_DTMR2 0xFC078000
#define MMAP_DTMR3 0xFC07C000
#define MMAP_PIT0 0xFC080000
#define MMAP_PIT1 0xFC084000
#define MMAP_PIT2 0xFC088000
#define MMAP_PIT3 0xFC08C000
#define MMAP_PWM 0xFC090000
#define MMAP_EPORT 0xFC094000
#define MMAP_WDOG 0xFC098000
#define MMAP_CCM 0xFC0A0000
#define MMAP_GPIO 0xFC0A4000
#define MMAP_RTC 0xFC0A8000
#define MMAP_LCDC 0xFC0AC000
#define MMAP_USBOTG 0xFC0B0000
#define MMAP_USBH 0xFC0B4000
#define MMAP_SDRAM 0xFC0B8000
#define MMAP_SSI 0xFC0BC000
#define MMAP_PLL 0xFC0C0000
/* System control module registers */
typedef struct scm1_ctrl {
u32 mpr0; /* 0x00 Master Privilege Register 0 */
u32 res1[15]; /* 0x04 - 0x3F */
u32 pacrh; /* 0x40 Peripheral Access Control Register H */
u32 res2[3]; /* 0x44 - 0x53 */
u32 bmt0; /*0x54 Bus Monitor Timeout 0 */
} scm1_t;
/* Message Digest Hardware Accelerator */
typedef struct mdha_ctrl {
u32 mdmr; /* 0x00 MDHA Mode Register */
u32 mdcr; /* 0x04 Control register */
u32 mdcmr; /* 0x08 Command Register */
u32 mdsr; /* 0x0C Status Register */
u32 mdisr; /* 0x10 Interrupt Status Register */
u32 mdimr; /* 0x14 Interrupt Mask Register */
u32 mddsr; /* 0x1C Data Size Register */
u32 mdin; /* 0x20 Input FIFO */
u32 res1[3]; /* 0x24 - 0x2F */
u32 mdao; /* 0x30 Message Digest AO Register */
u32 mdbo; /* 0x34 Message Digest BO Register */
u32 mdco; /* 0x38 Message Digest CO Register */
u32 mddo; /* 0x3C Message Digest DO Register */
u32 mdeo; /* 0x40 Message Digest EO Register */
u32 mdmds; /* 0x44 Message Data Size Register */
u32 res[10]; /* 0x48 - 0x6F */
u32 mda1; /* 0x70 Message Digest A1 Register */
u32 mdb1; /* 0x74 Message Digest B1 Register */
u32 mdc1; /* 0x78 Message Digest C1 Register */
u32 mdd1; /* 0x7C Message Digest D1 Register */
u32 mde1; /* 0x80 Message Digest E1 Register */
} mdha_t;
/* Symmetric Key Hardware Accelerator */
typedef struct skha_ctrl {
u32 mr; /* 0x00 Mode Register */
u32 cr; /* 0x04 Control Register */
u32 cmr; /* 0x08 Command Register */
u32 sr; /* 0x0C Status Register */
u32 esr; /* 0x10 Error Status Register */
u32 emr; /* 0x14 Error Status Mask Register) */
u32 ksr; /* 0x18 Key Size Register */
u32 dsr; /* 0x1C Data Size Register */
u32 in; /* 0x20 Input FIFO */
u32 out; /* 0x24 Output FIFO */
u32 res1[2]; /* 0x28 - 0x2F */
u32 kdr1; /* 0x30 Key Data Register 1 */
u32 kdr2; /* 0x34 Key Data Register 2 */
u32 kdr3; /* 0x38 Key Data Register 3 */
u32 kdr4; /* 0x3C Key Data Register 4 */
u32 kdr5; /* 0x40 Key Data Register 5 */
u32 kdr6; /* 0x44 Key Data Register 6 */
u32 res2[10]; /* 0x48 - 0x6F */
u32 c1; /* 0x70 Context 1 */
u32 c2; /* 0x74 Context 2 */
u32 c3; /* 0x78 Context 3 */
u32 c4; /* 0x7C Context 4 */
u32 c5; /* 0x80 Context 5 */
u32 c6; /* 0x84 Context 6 */
u32 c7; /* 0x88 Context 7 */
u32 c8; /* 0x8C Context 8 */
u32 c9; /* 0x90 Context 9 */
u32 c10; /* 0x94 Context 10 */
u32 c11; /* 0x98 Context 11 */
} skha_t;
/* Random Number Generator */
typedef struct rng_ctrl {
u32 rngcr; /* 0x00 RNG Control Register */
u32 rngsr; /* 0x04 RNG Status Register */
u32 rnger; /* 0x08 RNG Entropy Register */
u32 rngout; /* 0x0C RNG Output FIFO */
} rng_t;
/* System control module registers 2 */
typedef struct scm2_ctrl {
u32 mpr1; /* 0x00 Master Privilege Register */
u32 res1[7]; /* 0x04 - 0x1F */
u32 pacra; /* 0x20 Peripheral Access Control Register A */
u32 pacrb; /* 0x24 Peripheral Access Control Register B */
u32 pacrc; /* 0x28 Peripheral Access Control Register C */
u32 pacrd; /* 0x2C Peripheral Access Control Register D */
u32 res2[4]; /* 0x30 - 0x3F */
u32 pacre; /* 0x40 Peripheral Access Control Register E */
u32 pacrf; /* 0x44 Peripheral Access Control Register F */
u32 pacrg; /* 0x48 Peripheral Access Control Register G */
u32 res3[2]; /* 0x4C - 0x53 */
u32 bmt1; /* 0x54 Bus Monitor Timeout 1 */
} scm2_t;
/* Cross-Bar Switch Module */
typedef struct xbs_ctrl {
u32 prs1; /* 0x100 Priority Register Slave 1 */
u32 res1[3]; /* 0x104 - 0F */
u32 crs1; /* 0x110 Control Register Slave 1 */
u32 res2[187]; /* 0x114 - 0x3FF */
u32 prs4; /* 0x400 Priority Register Slave 4 */
u32 res3[3]; /* 0x404 - 0F */
u32 crs4; /* 0x410 Control Register Slave 4 */
u32 res4[123]; /* 0x414 - 0x5FF */
u32 prs6; /* 0x600 Priority Register Slave 6 */
u32 res5[3]; /* 0x604 - 0F */
u32 crs6; /* 0x610 Control Register Slave 6 */
u32 res6[59]; /* 0x614 - 0x6FF */
u32 prs7; /* 0x700 Priority Register Slave 7 */
u32 res7[3]; /* 0x704 - 0F */
u32 crs7; /* 0x710 Control Register Slave 7 */
} xbs_t;
/* Flexbus module Chip select registers */
typedef struct fbcs_ctrl {
u16 csar0; /* 0x00 Chip-Select Address Register 0 */
u16 res0;
u32 csmr0; /* 0x04 Chip-Select Mask Register 0 */
u32 cscr0; /* 0x08 Chip-Select Control Register 0 */
u16 csar1; /* 0x0C Chip-Select Address Register 1 */
u16 res1;
u32 csmr1; /* 0x10 Chip-Select Mask Register 1 */
u32 cscr1; /* 0x14 Chip-Select Control Register 1 */
u16 csar2; /* 0x18 Chip-Select Address Register 2 */
u16 res2;
u32 csmr2; /* 0x1C Chip-Select Mask Register 2 */
u32 cscr2; /* 0x20 Chip-Select Control Register 2 */
u16 csar3; /* 0x24 Chip-Select Address Register 3 */
u16 res3;
u32 csmr3; /* 0x28 Chip-Select Mask Register 3 */
u32 cscr3; /* 0x2C Chip-Select Control Register 3 */
u16 csar4; /* 0x30 Chip-Select Address Register 4 */
u16 res4;
u32 csmr4; /* 0x34 Chip-Select Mask Register 4 */
u32 cscr4; /* 0x38 Chip-Select Control Register 4 */
u16 csar5; /* 0x3C Chip-Select Address Register 5 */
u16 res5;
u32 csmr5; /* 0x40 Chip-Select Mask Register 5 */
u32 cscr5; /* 0x44 Chip-Select Control Register 5 */
} fbcs_t;
/* FlexCan module registers */
typedef struct can_ctrl {
u32 mcr; /* 0x00 Module Configuration register */
u32 ctrl; /* 0x04 Control register */
u32 timer; /* 0x08 Free Running Timer */
u32 res1; /* 0x0C */
u32 rxgmask; /* 0x10 Rx Global Mask */
u32 rx14mask; /* 0x14 RxBuffer 14 Mask */
u32 rx15mask; /* 0x18 RxBuffer 15 Mask */
u32 errcnt; /* 0x1C Error Counter Register */
u32 errstat; /* 0x20 Error and status Register */
u32 res2; /* 0x24 */
u32 imask; /* 0x28 Interrupt Mask Register */
u32 res3; /* 0x2C */
u32 iflag; /* 0x30 Interrupt Flag Register */
u32 res4[19]; /* 0x34 - 0x7F */
u32 MB0_15[2048]; /* 0x80 Message Buffer 0-15 */
} can_t;
/* System Control Module register 3 */
typedef struct scm3_ctrl {
u8 res1[19]; /* 0x00 - 0x12 */
u8 wcr; /* 0x13 wakeup control register */
u16 res2; /* 0x14 - 0x15 */
u16 cwcr; /* 0x16 Core Watchdog Control Register */
u8 res3[3]; /* 0x18 - 0x1A */
u8 cwsr; /* 0x1B Core Watchdog Service Register */
u8 res4[2]; /* 0x1C - 0x1D */
u8 scmisr; /* 0x1F Interrupt Status Register */
u32 res5; /* 0x20 */
u32 bcr; /* 0x24 Burst Configuration Register */
u32 res6[18]; /* 0x28 - 0x6F */
u32 cfadr; /* 0x70 Core Fault Address Register */
u8 res7[4]; /* 0x71 - 0x74 */
u8 cfier; /* 0x75 Core Fault Interrupt Enable Register */
u8 cfloc; /* 0x76 Core Fault Location Register */
u8 cfatr; /* 0x77 Core Fault Attributes Register */
u32 res8; /* 0x78 */
u32 cfdtr; /* 0x7C Core Fault Data Register */
} scm3_t;
/* eDMA module registers */
typedef struct edma_ctrl {
u32 cr; /* 0x00 Control Register */
u32 es; /* 0x04 Error Status Register */
u16 res1[3]; /* 0x08 - 0x0D */
u16 erq; /* 0x0E Enable Request Register */
u16 res2[3]; /* 0x10 - 0x15 */
u16 eei; /* 0x16 Enable Error Interrupt Request */
u8 serq; /* 0x18 Set Enable Request */
u8 cerq; /* 0x19 Clear Enable Request */
u8 seei; /* 0x1A Set Enable Error Interrupt Request */
u8 ceei; /* 0x1B Clear Enable Error Interrupt Request */
u8 cint; /* 0x1C Clear Interrupt Enable Register */
u8 cerr; /* 0x1D Clear Error Register */
u8 ssrt; /* 0x1E Set START Bit Register */
u8 cdne; /* 0x1F Clear DONE Status Bit Register */
u16 res3[3]; /* 0x20 - 0x25 */
u16 intr; /* 0x26 Interrupt Request Register */
u16 res4[3]; /* 0x28 - 0x2D */
u16 err; /* 0x2E Error Register */
u32 res5[52]; /* 0x30 - 0xFF */
u8 dchpri0; /* 0x100 Channel 0 Priority Register */
u8 dchpri1; /* 0x101 Channel 1 Priority Register */
u8 dchpri2; /* 0x102 Channel 2 Priority Register */
u8 dchpri3; /* 0x103 Channel 3 Priority Register */
u8 dchpri4; /* 0x104 Channel 4 Priority Register */
u8 dchpri5; /* 0x105 Channel 5 Priority Register */
u8 dchpri6; /* 0x106 Channel 6 Priority Register */
u8 dchpri7; /* 0x107 Channel 7 Priority Register */
u8 dchpri8; /* 0x108 Channel 8 Priority Register */
u8 dchpri9; /* 0x109 Channel 9 Priority Register */
u8 dchpri10; /* 0x110 Channel 10 Priority Register */
u8 dchpri11; /* 0x111 Channel 11 Priority Register */
u8 dchpri12; /* 0x112 Channel 12 Priority Register */
u8 dchpri13; /* 0x113 Channel 13 Priority Register */
u8 dchpri14; /* 0x114 Channel 14 Priority Register */
u8 dchpri15; /* 0x115 Channel 15 Priority Register */
} edma_t;
/* TCD - eDMA*/
typedef struct tcd_ctrl {
u32 saddr; /* 0x00 Source Address */
u16 attr; /* 0x04 Transfer Attributes */
u16 soff; /* 0x06 Signed Source Address Offset */
u32 nbytes; /* 0x08 Minor Byte Count */
u32 slast; /* 0x0C Last Source Address Adjustment */
u32 daddr; /* 0x10 Destination address */
u16 citer; /* 0x14 Current Minor Loop Link, Major Loop Count */
u16 doff; /* 0x16 Signed Destination Address Offset */
u32 dlast_sga; /* 0x18 Last Destination Address Adjustment/Scatter Gather Address */
u16 biter; /* 0x1C Beginning Minor Loop Link, Major Loop Count */
u16 csr; /* 0x1E Control and Status */
} tcd_st;
typedef struct tcd_multiple {
tcd_st tcd[16];
} tcd_t;
/* Interrupt module registers */
typedef struct int0_ctrl {
/* Interrupt Controller 0 */
u32 iprh0; /* 0x00 Pending Register High */
u32 iprl0; /* 0x04 Pending Register Low */
u32 imrh0; /* 0x08 Mask Register High */
u32 imrl0; /* 0x0C Mask Register Low */
u32 frch0; /* 0x10 Force Register High */
u32 frcl0; /* 0x14 Force Register Low */
u16 res1; /* 0x18 - 0x19 */
u16 icfg0; /* 0x1A Configuration Register */
u8 simr0; /* 0x1C Set Interrupt Mask */
u8 cimr0; /* 0x1D Clear Interrupt Mask */
u8 clmask0; /* 0x1E Current Level Mask */
u8 slmask; /* 0x1F Saved Level Mask */
u32 res2[8]; /* 0x20 - 0x3F */
u8 icr0[64]; /* 0x40 - 0x7F Control registers */
u32 res3[24]; /* 0x80 - 0xDF */
u8 swiack0; /* 0xE0 Software Interrupt Acknowledge */
u8 res4[3]; /* 0xE1 - 0xE3 */
u8 Lniack0_1; /* 0xE4 Level n interrupt acknowledge resister */
u8 res5[3]; /* 0xE5 - 0xE7 */
u8 Lniack0_2; /* 0xE8 Level n interrupt acknowledge resister */
u8 res6[3]; /* 0xE9 - 0xEB */
u8 Lniack0_3; /* 0xEC Level n interrupt acknowledge resister */
u8 res7[3]; /* 0xED - 0xEF */
u8 Lniack0_4; /* 0xF0 Level n interrupt acknowledge resister */
u8 res8[3]; /* 0xF1 - 0xF3 */
u8 Lniack0_5; /* 0xF4 Level n interrupt acknowledge resister */
u8 res9[3]; /* 0xF5 - 0xF7 */
u8 Lniack0_6; /* 0xF8 Level n interrupt acknowledge resister */
u8 resa[3]; /* 0xF9 - 0xFB */
u8 Lniack0_7; /* 0xFC Level n interrupt acknowledge resister */
u8 resb[3]; /* 0xFD - 0xFF */
} int0_t;
typedef struct int1_ctrl {
/* Interrupt Controller 1 */
u32 iprh1; /* 0x00 Pending Register High */
u32 iprl1; /* 0x04 Pending Register Low */
u32 imrh1; /* 0x08 Mask Register High */
u32 imrl1; /* 0x0C Mask Register Low */
u32 frch1; /* 0x10 Force Register High */
u32 frcl1; /* 0x14 Force Register Low */
u16 res1; /* 0x18 */
u16 icfg1; /* 0x1A Configuration Register */
u8 simr1; /* 0x1C Set Interrupt Mask */
u8 cimr1; /* 0x1D Clear Interrupt Mask */
u16 res2; /* 0x1E - 0x1F */
u32 res3[8]; /* 0x20 - 0x3F */
u8 icr1[64]; /* 0x40 - 0x7F */
u32 res4[24]; /* 0x80 - 0xDF */
u8 swiack1; /* 0xE0 Software Interrupt Acknowledge */
u8 res5[3]; /* 0xE1 - 0xE3 */
u8 Lniack1_1; /* 0xE4 Level n interrupt acknowledge resister */
u8 res6[3]; /* 0xE5 - 0xE7 */
u8 Lniack1_2; /* 0xE8 Level n interrupt acknowledge resister */
u8 res7[3]; /* 0xE9 - 0xEB */
u8 Lniack1_3; /* 0xEC Level n interrupt acknowledge resister */
u8 res8[3]; /* 0xED - 0xEF */
u8 Lniack1_4; /* 0xF0 Level n interrupt acknowledge resister */
u8 res9[3]; /* 0xF1 - 0xF3 */
u8 Lniack1_5; /* 0xF4 Level n interrupt acknowledge resister */
u8 resa[3]; /* 0xF5 - 0xF7 */
u8 Lniack1_6; /* 0xF8 Level n interrupt acknowledge resister */
u8 resb[3]; /* 0xF9 - 0xFB */
u8 Lniack1_7; /* 0xFC Level n interrupt acknowledge resister */
u8 resc[3]; /* 0xFD - 0xFF */
} int1_t;
typedef struct intgack_ctrl1 {
/* Global IACK Registers */
u8 swiack; /* 0xE0 Global Software Interrupt Acknowledge */
u8 Lniack[7]; /* 0xE1 - 0xE7 Global Level 0 Interrupt Acknowledge */
} intgack_t;
/*I2C module registers */
typedef struct i2c_ctrl {
u8 adr; /* 0x00 address register */
u8 res1[3]; /* 0x01 - 0x03 */
u8 fdr; /* 0x04 frequency divider register */
u8 res2[3]; /* 0x05 - 0x07 */
u8 cr; /* 0x08 control register */
u8 res3[3]; /* 0x09 - 0x0B */
u8 sr; /* 0x0C status register */
u8 res4[3]; /* 0x0D - 0x0F */
u8 dr; /* 0x10 data register */
u8 res5[3]; /* 0x11 - 0x13 */
} i2c_t;
/* QSPI module registers */
typedef struct qspi_ctrl {
u16 qmr; /* Mode register */
u16 res1;
u16 qdlyr; /* Delay register */
u16 res2;
u16 qwr; /* Wrap register */
u16 res3;
u16 qir; /* Interrupt register */
u16 res4;
u16 qar; /* Address register */
u16 res5;
u16 qdr; /* Data register */
u16 res6;
} qspi_t;
/* PWM module registers */
typedef struct pwm_ctrl {
u8 en; /* 0x00 PWM Enable Register */
u8 pol; /* 0x01 Polarity Register */
u8 clk; /* 0x02 Clock Select Register */
u8 prclk; /* 0x03 Prescale Clock Select Register */
u8 cae; /* 0x04 Center Align Enable Register */
u8 ctl; /* 0x05 Control Register */
u8 res1[2]; /* 0x06 - 0x07 */
u8 scla; /* 0x08 Scale A register */
u8 sclb; /* 0x09 Scale B register */
u8 res2[2]; /* 0x0A - 0x0B */
u8 cnt0; /* 0x0C Channel 0 Counter register */
u8 cnt1; /* 0x0D Channel 1 Counter register */
u8 cnt2; /* 0x0E Channel 2 Counter register */
u8 cnt3; /* 0x0F Channel 3 Counter register */
u8 cnt4; /* 0x10 Channel 4 Counter register */
u8 cnt5; /* 0x11 Channel 5 Counter register */
u8 cnt6; /* 0x12 Channel 6 Counter register */
u8 cnt7; /* 0x13 Channel 7 Counter register */
u8 per0; /* 0x14 Channel 0 Period register */
u8 per1; /* 0x15 Channel 1 Period register */
u8 per2; /* 0x16 Channel 2 Period register */
u8 per3; /* 0x17 Channel 3 Period register */
u8 per4; /* 0x18 Channel 4 Period register */
u8 per5; /* 0x19 Channel 5 Period register */
u8 per6; /* 0x1A Channel 6 Period register */
u8 per7; /* 0x1B Channel 7 Period register */
u8 dty0; /* 0x1C Channel 0 Duty register */
u8 dty1; /* 0x1D Channel 1 Duty register */
u8 dty2; /* 0x1E Channel 2 Duty register */
u8 dty3; /* 0x1F Channel 3 Duty register */
u8 dty4; /* 0x20 Channel 4 Duty register */
u8 dty5; /* 0x21 Channel 5 Duty register */
u8 dty6; /* 0x22 Channel 6 Duty register */
u8 dty7; /* 0x23 Channel 7 Duty register */
u8 sdn; /* 0x24 Shutdown register */
u8 res3[3]; /* 0x25 - 0x27 */
} pwm_t;
/* Edge Port module registers */
typedef struct eport_ctrl {
u16 par; /* 0x00 Pin Assignment Register */
u8 ddar; /* 0x02 Data Direction Register */
u8 ier; /* 0x03 Interrupt Enable Register */
u8 dr; /* 0x04 Data Register */
u8 pdr; /* 0x05 Pin Data Register */
u8 fr; /* 0x06 Flag_Register */
u8 res1;
} eport_t;
/* Watchdog registers */
typedef struct wdog_ctrl {
u16 cr; /* 0x00 Control register */
u16 mr; /* 0x02 Modulus register */
u16 cntr; /* 0x04 Count register */
u16 sr; /* 0x06 Service register */
} wdog_t;
/*Chip configuration module registers */
typedef struct ccm_ctrl {
u8 rstctrl; /* 0x00 Reset Controller register */
u8 rststat; /* 0x01 Reset Status register */
u16 res1; /* 0x02 - 0x03 */
u16 ccr; /* 0x04 Chip configuration register */
u16 res2; /* 0x06 */
u16 rcon; /* 0x08 Rreset configuration register */
u16 cir; /* 0x0A Chip identification register */
u32 res3; /* 0x0C */
u16 misccr; /* 0x10 Miscellaneous control register */
u16 cdr; /* 0x12 Clock divider register */
u16 uhcsr; /* 0x14 USB Host controller status register */
u16 uocsr; /* 0x16 USB On-the-Go Controller Status Register */
} ccm_t;
/* GPIO port registers */
typedef struct gpio_ctrl {
/* Port Output Data Registers */
u8 podr_fech; /* 0x00 */
u8 podr_fecl; /* 0x01 */
u8 podr_ssi; /* 0x02 */
u8 podr_busctl; /* 0x03 */
u8 podr_be; /* 0x04 */
u8 podr_cs; /* 0x05 */
u8 podr_pwm; /* 0x06 */
u8 podr_feci2c; /* 0x07 */
u8 res1; /* 0x08 */
u8 podr_uart; /* 0x09 */
u8 podr_qspi; /* 0x0A */
u8 podr_timer; /* 0x0B */
u8 res2; /* 0x0C */
u8 podr_lcddatah; /* 0x0D */
u8 podr_lcddatam; /* 0x0E */
u8 podr_lcddatal; /* 0x0F */
u8 podr_lcdctlh; /* 0x10 */
u8 podr_lcdctll; /* 0x11 */
/* Port Data Direction Registers */
u16 res3; /* 0x12 - 0x13 */
u8 pddr_fech; /* 0x14 */
u8 pddr_fecl; /* 0x15 */
u8 pddr_ssi; /* 0x16 */
u8 pddr_busctl; /* 0x17 */
u8 pddr_be; /* 0x18 */
u8 pddr_cs; /* 0x19 */
u8 pddr_pwm; /* 0x1A */
u8 pddr_feci2c; /* 0x1B */
u8 res4; /* 0x1C */
u8 pddr_uart; /* 0x1D */
u8 pddr_qspi; /* 0x1E */
u8 pddr_timer; /* 0x1F */
u8 res5; /* 0x20 */
u8 pddr_lcddatah; /* 0x21 */
u8 pddr_lcddatam; /* 0x22 */
u8 pddr_lcddatal; /* 0x23 */
u8 pddr_lcdctlh; /* 0x24 */
u8 pddr_lcdctll; /* 0x25 */
u16 res6; /* 0x26 - 0x27 */
/* Port Data Direction Registers */
u8 ppd_fech; /* 0x28 */
u8 ppd_fecl; /* 0x29 */
u8 ppd_ssi; /* 0x2A */
u8 ppd_busctl; /* 0x2B */
u8 ppd_be; /* 0x2C */
u8 ppd_cs; /* 0x2D */
u8 ppd_pwm; /* 0x2E */
u8 ppd_feci2c; /* 0x2F */
u8 res7; /* 0x30 */
u8 ppd_uart; /* 0x31 */
u8 ppd_qspi; /* 0x32 */
u8 ppd_timer; /* 0x33 */
u8 res8; /* 0x34 */
u8 ppd_lcddatah; /* 0x35 */
u8 ppd_lcddatam; /* 0x36 */
u8 ppd_lcddatal; /* 0x37 */
u8 ppd_lcdctlh; /* 0x38 */
u8 ppd_lcdctll; /* 0x39 */
u16 res9; /* 0x3A - 0x3B */
/* Port Clear Output Data Registers */
u8 pclrr_fech; /* 0x3C */
u8 pclrr_fecl; /* 0x3D */
u8 pclrr_ssi; /* 0x3E */
u8 pclrr_busctl; /* 0x3F */
u8 pclrr_be; /* 0x40 */
u8 pclrr_cs; /* 0x41 */
u8 pclrr_pwm; /* 0x42 */
u8 pclrr_feci2c; /* 0x43 */
u8 res10; /* 0x44 */
u8 pclrr_uart; /* 0x45 */
u8 pclrr_qspi; /* 0x46 */
u8 pclrr_timer; /* 0x47 */
u8 res11; /* 0x48 */
u8 pclrr_lcddatah; /* 0x49 */
u8 pclrr_lcddatam; /* 0x4A */
u8 pclrr_lcddatal; /* 0x4B */
u8 pclrr_lcdctlh; /* 0x4C */
u8 pclrr_lcdctll; /* 0x4D */
u16 res12; /* 0x4E - 0x4F */
/* Pin Assignment Registers */
u8 par_fec; /* 0x50 */
u8 par_pwm; /* 0x51 */
u8 par_busctl; /* 0x52 */
u8 par_feci2c; /* 0x53 */
u8 par_be; /* 0x54 */
u8 par_cs; /* 0x55 */
u16 par_ssi; /* 0x56 */
u16 par_uart; /* 0x58 */
u16 par_qspi; /* 0x5A */
u8 par_timer; /* 0x5C */
u8 par_lcddata; /* 0x5D */
u16 par_lcdctl; /* 0x5E */
u16 par_irq; /* 0x60 */
u16 res16; /* 0x62 - 0x63 */
/* Mode Select Control Registers */
u8 mscr_flexbus; /* 0x64 */
u8 mscr_sdram; /* 0x65 */
u16 res17; /* 0x66 - 0x67 */
/* Drive Strength Control Registers */
u8 dscr_i2c; /* 0x68 */
u8 dscr_pwm; /* 0x69 */
u8 dscr_fec; /* 0x6A */
u8 dscr_uart; /* 0x6B */
u8 dscr_qspi; /* 0x6C */
u8 dscr_timer; /* 0x6D */
u8 dscr_ssi; /* 0x6E */
u8 dscr_lcd; /* 0x6F */
u8 dscr_debug; /* 0x70 */
u8 dscr_clkrst; /* 0x71 */
u8 dscr_irq; /* 0x72 */
} gpio_t;
/* LCD module registers */
typedef struct lcd_ctrl {
u32 ssar; /* 0x00 Screen Start Address Register */
u32 sr; /* 0x04 LCD Size Register */
u32 vpw; /* 0x08 Virtual Page Width Register */
u32 cpr; /* 0x0C Cursor Position Register */
u32 cwhb; /* 0x10 Cursor Width Height and Blink Register */
u32 ccmr; /* 0x14 Color Cursor Mapping Register */
u32 pcr; /* 0x18 Panel Configuration Register */
u32 hcr; /* 0x1C Horizontal Configuration Register */
u32 vcr; /* 0x20 Vertical Configuration Register */
u32 por; /* 0x24 Panning Offset Register */
u32 scr; /* 0x28 Sharp Configuration Register */
u32 pccr; /* 0x2C PWM Contrast Control Register */
u32 dcr; /* 0x30 DMA Control Register */
u32 rmcr; /* 0x34 Refresh Mode Control Register */
u32 icr; /* 0x38 Refresh Mode Control Register */
u32 ier; /* 0x3C Interrupt Enable Register */
u32 isr; /* 0x40 Interrupt Status Register */
u32 res[4];
u32 gwsar; /* 0x50 Graphic Window Start Address Register */
u32 gwsr; /* 0x54 Graphic Window Size Register */
u32 gwvpw; /* 0x58 Graphic Window Virtual Page Width Register */
u32 gwpor; /* 0x5C Graphic Window Panning Offset Register */
u32 gwpr; /* 0x60 Graphic Window Position Register */
u32 gwcr; /* 0x64 Graphic Window Control Register */
u32 gwdcr; /* 0x68 Graphic Window DMA Control Register */
} lcd_t;
typedef struct lcdbg_ctrl {
u32 bglut[255];
} lcdbg_t;
typedef struct lcdgw_ctrl {
u32 gwlut[255];
} lcdgw_t;
/* USB OTG module registers */
typedef struct usb_otg {
u32 id; /* 0x000 Identification Register */
u32 hwgeneral; /* 0x004 General HW Parameters */
u32 hwhost; /* 0x008 Host HW Parameters */
u32 hwdev; /* 0x00C Device HW parameters */
u32 hwtxbuf; /* 0x010 TX Buffer HW Parameters */
u32 hwrxbuf; /* 0x014 RX Buffer HW Parameters */
u32 res1[58]; /* 0x18 - 0xFF */
u8 caplength; /* 0x100 Capability Register Length */
u8 res2; /* 0x101 */
u16 hciver; /* 0x102 Host Interface Version Number */
u32 hcsparams; /* 0x104 Host Structural Parameters */
u32 hccparams; /* 0x108 Host Capability Parameters */
u32 res3[5]; /* 0x10C - 0x11F */
u16 dciver; /* 0x120 Device Interface Version Number */
u16 res4; /* 0x122 */
u32 dccparams; /* 0x124 Device Capability Parameters */
u32 res5[6]; /* 0x128 - 0x13F */
u32 cmd; /* 0x140 USB Command */
u32 sts; /* 0x144 USB Status */
u32 intr; /* 0x148 USB Interrupt Enable */
u32 frindex; /* 0x14C USB Frame Index */
u32 res6; /* 0x150 */
u32 prd_dev; /* 0x154 Periodic Frame List Base or Device Address */
u32 aync_ep; /* 0x158 Current Asynchronous List or Address at Endpoint List Address */
u32 ttctrl; /* 0x15C Host TT Asynchronous Buffer Control */
u32 burstsize; /* 0x160 Master Interface Data Burst Size */
u32 txfill; /* 0x164 Host Transmit FIFO Tuning Control */
u32 res7[6]; /* 0x168 - 0x17F */
u32 cfgflag; /* 0x180 Configure Flag Register */
u32 portsc1; /* 0x184 Port Status/Control */
u32 res8[7]; /* 0x188 - 0x1A3 */
u32 otgsc; /* 0x1A4 On The Go Status and Control */
u32 mode; /* 0x1A8 USB mode register */
u32 eptsetstat; /* 0x1AC Endpoint Setup status */
u32 eptprime; /* 0x1B0 Endpoint initialization */
u32 eptflush; /* 0x1B4 Endpoint de-initialize */
u32 eptstat; /* 0x1B8 Endpoint status */
u32 eptcomplete; /* 0x1BC Endpoint Complete */
u32 eptctrl0; /* 0x1C0 Endpoint control 0 */
u32 eptctrl1; /* 0x1C4 Endpoint control 1 */
u32 eptctrl2; /* 0x1C8 Endpoint control 2 */
u32 eptctrl3; /* 0x1CC Endpoint control 3 */
} usbotg_t;
/* USB Host module registers */
typedef struct usb_host {
u32 id; /* 0x000 Identification Register */
u32 hwgeneral; /* 0x004 General HW Parameters */
u32 hwhost; /* 0x008 Host HW Parameters */
u32 res1; /* 0x0C */
u32 hwtxbuf; /* 0x010 TX Buffer HW Parameters */
u32 hwrxbuf; /* 0x014 RX Buffer HW Parameters */
u32 res2[58]; /* 0x18 - 0xFF */
/* Host Controller Capability Register */
u8 caplength; /* 0x100 Capability Register Length */
u8 res3; /* 0x101 */
u16 hciver; /* 0x102 Host Interface Version Number */
u32 hcsparams; /* 0x104 Host Structural Parameters */
u32 hccparams; /* 0x108 Host Capability Parameters */
u32 res4[13]; /* 0x10C - 0x13F */
/* Host Controller Operational Register */
u32 cmd; /* 0x140 USB Command */
u32 sts; /* 0x144 USB Status */
u32 intr; /* 0x148 USB Interrupt Enable */
u32 frindex; /* 0x14C USB Frame Index */
u32 res5; /* 0x150 (ctrl segment register in EHCI spec) */
u32 prdlst; /* 0x154 Periodic Frame List Base Address */
u32 aynclst; /* 0x158 Current Asynchronous List Address */
u32 ttctrl; /* 0x15C Host TT Asynchronous Buffer Control (non-ehci) */
u32 burstsize; /* 0x160 Master Interface Data Burst Size (non-ehci) */
u32 txfill; /* 0x164 Host Transmit FIFO Tuning Control (non-ehci) */
u32 res6[6]; /* 0x168 - 0x17F */
u32 cfgflag; /* 0x180 Configure Flag Register */
u32 portsc1; /* 0x184 Port Status/Control */
u32 res7[8]; /* 0x188 - 0x1A7 */
/* non-ehci registers */
u32 mode; /* 0x1A8 USB mode register */
u32 eptsetstat; /* 0x1AC Endpoint Setup status */
u32 eptprime; /* 0x1B0 Endpoint initialization */
u32 eptflush; /* 0x1B4 Endpoint de-initialize */
u32 eptstat; /* 0x1B8 Endpoint status */
u32 eptcomplete; /* 0x1BC Endpoint Complete */
u32 eptctrl0; /* 0x1C0 Endpoint control 0 */
u32 eptctrl1; /* 0x1C4 Endpoint control 1 */
u32 eptctrl2; /* 0x1C8 Endpoint control 2 */
u32 eptctrl3; /* 0x1CC Endpoint control 3 */
} usbhost_t;
/* SDRAM controller registers */
typedef struct sdram_ctrl {
u32 mode; /* 0x00 Mode/Extended Mode register */
u32 ctrl; /* 0x04 Control register */
u32 cfg1; /* 0x08 Configuration register 1 */
u32 cfg2; /* 0x0C Configuration register 2 */
u32 res1[64]; /* 0x10 - 0x10F */
u32 cs0; /* 0x110 Chip Select 0 Configuration */
u32 cs1; /* 0x114 Chip Select 1 Configuration */
} sdram_t;
/* Synchronous serial interface */
typedef struct ssi_ctrl {
u32 tx0; /* 0x00 Transmit Data Register 0 */
u32 tx1; /* 0x04 Transmit Data Register 1 */
u32 rx0; /* 0x08 Receive Data Register 0 */
u32 rx1; /* 0x0C Receive Data Register 1 */
u32 cr; /* 0x10 Control Register */
u32 isr; /* 0x14 Interrupt Status Register */
u32 ier; /* 0x18 Interrupt Enable Register */
u32 tcr; /* 0x1C Transmit Configuration Register */
u32 rcr; /* 0x20 Receive Configuration Register */
u32 ccr; /* 0x24 Clock Control Register */
u32 res1; /* 0x28 */
u32 fcsr; /* 0x2C FIFO Control/Status Register */
u32 res2[2]; /* 0x30 - 0x37 */
u32 acr; /* 0x38 AC97 Control Register */
u32 acadd; /* 0x3C AC97 Command Address Register */
u32 acdat; /* 0x40 AC97 Command Data Register */
u32 atag; /* 0x44 AC97 Tag Register */
u32 tmask; /* 0x48 Transmit Time Slot Mask Register */
u32 rmask; /* 0x4C Receive Time Slot Mask Register */
} ssi_t;
/* Clock Module registers */
typedef struct pll_ctrl {
u8 podr; /* 0x00 Output Divider Register */
u8 res1[3];
u8 pcr; /* 0x04 Control Register */
u8 res2[3];
u8 pmdr; /* 0x08 Modulation Divider Register */
u8 res3[3];
u8 pfdr; /* 0x0C Feedback Divider Register */
u8 res4[3];
} pll_t;
#endif /* __IMMAP_5329__ */

937
include/asm-m68k/immap_5445x.h Normal file
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/*
* MCF5445x Internal Memory Map
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __IMMAP_5445X__
#define __IMMAP_5445X__
/* Module Base Addresses */
#define MMAP_SCM1 0xFC000000
#define MMAP_XBS 0xFC004000
#define MMAP_FBCS 0xFC008000
#define MMAP_FEC0 0xFC030000
#define MMAP_FEC1 0xFC034000
#define MMAP_RTC 0xFC03C000
#define MMAP_EDMA 0xFC044000
#define MMAP_INTC0 0xFC048000
#define MMAP_INTC1 0xFC04C000
#define MMAP_IACK 0xFC054000
#define MMAP_I2C 0xFC058000
#define MMAP_DSPI 0xFC05C000
#define MMAP_UART0 0xFC060000
#define MMAP_UART1 0xFC064000
#define MMAP_UART2 0xFC068000
#define MMAP_DTMR0 0xFC070000
#define MMAP_DTMR1 0xFC074000
#define MMAP_DTMR2 0xFC078000
#define MMAP_DTMR3 0xFC07C000
#define MMAP_PIT0 0xFC080000
#define MMAP_PIT1 0xFC084000
#define MMAP_PIT2 0xFC088000
#define MMAP_PIT3 0xFC08C000
#define MMAP_EPORT 0xFC094000
#define MMAP_WTM 0xFC098000
#define MMAP_SBF 0xFC0A0000
#define MMAP_RCM 0xFC0A0000
#define MMAP_CCM 0xFC0A0000
#define MMAP_GPIO 0xFC0A4000
#define MMAP_PCI 0xFC0A8000
#define MMAP_PCIARB 0xFC0AC000
#define MMAP_RNG 0xFC0B4000
#define MMAP_SDRAM 0xFC0B8000
#define MMAP_SSI 0xFC0BC000
#define MMAP_PLL 0xFC0C4000
#define MMAP_ATA 0x90000000
/*********************************************************************
* ATA
*********************************************************************/
typedef struct atac {
/* PIO */
u8 toff; /* 0x00 */
u8 ton; /* 0x01 */
u8 t1; /* 0x02 */
u8 t2w; /* 0x03 */
u8 t2r; /* 0x04 */
u8 ta; /* 0x05 */
u8 trd; /* 0x06 */
u8 t4; /* 0x07 */
u8 t9; /* 0x08 */
/* DMA */
u8 tm; /* 0x09 */
u8 tn; /* 0x0A */
u8 td; /* 0x0B */
u8 tk; /* 0x0C */
u8 tack; /* 0x0D */
u8 tenv; /* 0x0E */
u8 trp; /* 0x0F */
u8 tzah; /* 0x10 */
u8 tmli; /* 0x11 */
u8 tdvh; /* 0x12 */
u8 tdzfs; /* 0x13 */
u8 tdvs; /* 0x14 */
u8 tcvh; /* 0x15 */
u8 tss; /* 0x16 */
u8 tcyc; /* 0x17 */
/* FIFO */
u32 fifo32; /* 0x18 */
u16 fifo16; /* 0x1C */
u8 rsvd0[2];
u8 ffill; /* 0x20 */
u8 rsvd1[3];
/* ATA */
u8 cr; /* 0x24 */
u8 rsvd2[3];
u8 isr; /* 0x28 */
u8 rsvd3[3];
u8 ier; /* 0x2C */
u8 rsvd4[3];
u8 icr; /* 0x30 */
u8 rsvd5[3];
u8 falarm; /* 0x34 */
u8 rsvd6[106];
} atac_t;
/*********************************************************************
* Cross-bar switch (XBS)
*********************************************************************/
typedef struct xbs {
u8 resv0[0x100];
u32 prs1; /* XBS Priority Register */
u8 resv1[0xC];
u32 crs1; /* XBS Control Register */
u8 resv2[0xEC];
u32 prs2; /* XBS Priority Register */
u8 resv3[0xC];
u32 crs2; /* XBS Control Register */
u8 resv4[0xEC];
u32 prs3; /* XBS Priority Register */
u8 resv5[0xC];
u32 crs3; /* XBS Control Register */
u8 resv6[0xEC];
u32 prs4; /* XBS Priority Register */
u8 resv7[0xC];
u32 crs4; /* XBS Control Register */
u8 resv8[0xEC];
u32 prs5; /* XBS Priority Register */
u8 resv9[0xC];
u32 crs5; /* XBS Control Register */
u8 resv10[0xEC];
u32 prs6; /* XBS Priority Register */
u8 resv11[0xC];
u32 crs6; /* XBS Control Register */
u8 resv12[0xEC];
u32 prs7; /* XBS Priority Register */
u8 resv13[0xC];
u32 crs7; /* XBS Control Register */
} xbs_t;
/*********************************************************************
* FlexBus Chip Selects (FBCS)
*********************************************************************/
typedef struct fbcs {
u32 csar0; /* Chip-select Address Register */
u32 csmr0; /* Chip-select Mask Register */
u32 cscr0; /* Chip-select Control Register */
u32 csar1; /* Chip-select Address Register */
u32 csmr1; /* Chip-select Mask Register */
u32 cscr1; /* Chip-select Control Register */
u32 csar2; /* Chip-select Address Register */
u32 csmr2; /* Chip-select Mask Register */
u32 cscr2; /* Chip-select Control Register */
u32 csar3; /* Chip-select Address Register */
u32 csmr3; /* Chip-select Mask Register */
u32 cscr3; /* Chip-select Control Register */
} fbcs_t;
/*********************************************************************
* Enhanced DMA (EDMA)
*********************************************************************/
typedef struct edma {
u32 cr;
u32 es;
u8 resv0[0x6];
u16 erq;
u8 resv1[0x6];
u16 eei;
u8 serq;
u8 cerq;
u8 seei;
u8 ceei;
u8 cint;
u8 cerr;
u8 ssrt;
u8 cdne;
u8 resv2[0x6];
u16 intr;
u8 resv3[0x6];
u16 err;
u8 resv4[0xD0];
u8 dchpri0;
u8 dchpri1;
u8 dchpri2;
u8 dchpri3;
u8 dchpri4;
u8 dchpri5;
u8 dchpri6;
u8 dchpri7;
u8 dchpri8;
u8 dchpri9;
u8 dchpri10;
u8 dchpri11;
u8 dchpri12;
u8 dchpri13;
u8 dchpri14;
u8 dchpri15;
u8 resv5[0xEF0];
u32 tcd0_saddr;
u16 tcd0_attr;
u16 tcd0_soff;
u32 tcd0_nbytes;
u32 tcd0_slast;
u32 tcd0_daddr;
union {
u16 tcd0_citer_elink;
u16 tcd0_citer;
};
u16 tcd0_doff;
u32 tcd0_dlast_sga;
union {
u16 tcd0_biter_elink;
u16 tcd0_biter;
};
u16 tcd0_csr;
u32 tcd1_saddr;
u16 tcd1_attr;
u16 tcd1_soff;
u32 tcd1_nbytes;
u32 tcd1_slast;
u32 tcd1_daddr;
union {
u16 tcd1_citer_elink;
u16 tcd1_citer;
};
u16 tcd1_doff;
u32 tcd1_dlast_sga;
union {
u16 tcd1_biter;
u16 tcd1_biter_elink;
};
u16 tcd1_csr;
u32 tcd2_saddr;
u16 tcd2_attr;
u16 tcd2_soff;
u32 tcd2_nbytes;
u32 tcd2_slast;
u32 tcd2_daddr;
union {
u16 tcd2_citer;
u16 tcd2_citer_elink;
};
u16 tcd2_doff;
u32 tcd2_dlast_sga;
union {
u16 tcd2_biter_elink;
u16 tcd2_biter;
};
u16 tcd2_csr;
u32 tcd3_saddr;
u16 tcd3_attr;
u16 tcd3_soff;
u32 tcd3_nbytes;
u32 tcd3_slast;
u32 tcd3_daddr;
union {
u16 tcd3_citer;
u16 tcd3_citer_elink;
};
u16 tcd3_doff;
u32 tcd3_dlast_sga;
union {
u16 tcd3_biter_elink;
u16 tcd3_biter;
};
u16 tcd3_csr;
u32 tcd4_saddr;
u16 tcd4_attr;
u16 tcd4_soff;
u32 tcd4_nbytes;
u32 tcd4_slast;
u32 tcd4_daddr;
union {
u16 tcd4_citer;
u16 tcd4_citer_elink;
};
u16 tcd4_doff;
u32 tcd4_dlast_sga;
union {
u16 tcd4_biter;
u16 tcd4_biter_elink;
};
u16 tcd4_csr;
u32 tcd5_saddr;
u16 tcd5_attr;
u16 tcd5_soff;
u32 tcd5_nbytes;
u32 tcd5_slast;
u32 tcd5_daddr;
union {
u16 tcd5_citer;
u16 tcd5_citer_elink;
};
u16 tcd5_doff;
u32 tcd5_dlast_sga;
union {
u16 tcd5_biter_elink;
u16 tcd5_biter;
};
u16 tcd5_csr;
u32 tcd6_saddr;
u16 tcd6_attr;
u16 tcd6_soff;
u32 tcd6_nbytes;
u32 tcd6_slast;
u32 tcd6_daddr;
union {
u16 tcd6_citer;
u16 tcd6_citer_elink;
};
u16 tcd6_doff;
u32 tcd6_dlast_sga;
union {
u16 tcd6_biter_elink;
u16 tcd6_biter;
};
u16 tcd6_csr;
u32 tcd7_saddr;
u16 tcd7_attr;
u16 tcd7_soff;
u32 tcd7_nbytes;
u32 tcd7_slast;
u32 tcd7_daddr;
union {
u16 tcd7_citer;
u16 tcd7_citer_elink;
};
u16 tcd7_doff;
u32 tcd7_dlast_sga;
union {
u16 tcd7_biter_elink;
u16 tcd7_biter;
};
u16 tcd7_csr;
u32 tcd8_saddr;
u16 tcd8_attr;
u16 tcd8_soff;
u32 tcd8_nbytes;
u32 tcd8_slast;
u32 tcd8_daddr;
union {
u16 tcd8_citer;
u16 tcd8_citer_elink;
};
u16 tcd8_doff;
u32 tcd8_dlast_sga;
union {
u16 tcd8_biter_elink;
u16 tcd8_biter;
};
u16 tcd8_csr;
u32 tcd9_saddr;
u16 tcd9_attr;
u16 tcd9_soff;
u32 tcd9_nbytes;
u32 tcd9_slast;
u32 tcd9_daddr;
union {
u16 tcd9_citer_elink;
u16 tcd9_citer;
};
u16 tcd9_doff;
u32 tcd9_dlast_sga;
union {
u16 tcd9_biter_elink;
u16 tcd9_biter;
};
u16 tcd9_csr;
u32 tcd10_saddr;
u16 tcd10_attr;
u16 tcd10_soff;
u32 tcd10_nbytes;
u32 tcd10_slast;
u32 tcd10_daddr;
union {
u16 tcd10_citer_elink;
u16 tcd10_citer;
};
u16 tcd10_doff;
u32 tcd10_dlast_sga;
union {
u16 tcd10_biter;
u16 tcd10_biter_elink;
};
u16 tcd10_csr;
u32 tcd11_saddr;
u16 tcd11_attr;
u16 tcd11_soff;
u32 tcd11_nbytes;
u32 tcd11_slast;
u32 tcd11_daddr;
union {
u16 tcd11_citer;
u16 tcd11_citer_elink;
};
u16 tcd11_doff;
u32 tcd11_dlast_sga;
union {
u16 tcd11_biter;
u16 tcd11_biter_elink;
};
u16 tcd11_csr;
u32 tcd12_saddr;
u16 tcd12_attr;
u16 tcd12_soff;
u32 tcd12_nbytes;
u32 tcd12_slast;
u32 tcd12_daddr;
union {
u16 tcd12_citer;
u16 tcd12_citer_elink;
};
u16 tcd12_doff;
u32 tcd12_dlast_sga;
union {
u16 tcd12_biter;
u16 tcd12_biter_elink;
};
u16 tcd12_csr;
u32 tcd13_saddr;
u16 tcd13_attr;
u16 tcd13_soff;
u32 tcd13_nbytes;
u32 tcd13_slast;
u32 tcd13_daddr;
union {
u16 tcd13_citer_elink;
u16 tcd13_citer;
};
u16 tcd13_doff;
u32 tcd13_dlast_sga;
union {
u16 tcd13_biter_elink;
u16 tcd13_biter;
};
u16 tcd13_csr;
u32 tcd14_saddr;
u16 tcd14_attr;
u16 tcd14_soff;
u32 tcd14_nbytes;
u32 tcd14_slast;
u32 tcd14_daddr;
union {
u16 tcd14_citer;
u16 tcd14_citer_elink;
};
u16 tcd14_doff;
u32 tcd14_dlast_sga;
union {
u16 tcd14_biter_elink;
u16 tcd14_biter;
};
u16 tcd14_csr;
u32 tcd15_saddr;
u16 tcd15_attr;
u16 tcd15_soff;
u32 tcd15_nbytes;
u32 tcd15_slast;
u32 tcd15_daddr;
union {
u16 tcd15_citer_elink;
u16 tcd15_citer;
};
u16 tcd15_doff;
u32 tcd15_dlast_sga;
union {
u16 tcd15_biter;
u16 tcd15_biter_elink;
};
u16 tcd15_csr;
} edma_t;
/*********************************************************************
* Interrupt Controller (INTC)
*********************************************************************/
typedef struct int0_ctrl {
u32 iprh0; /* 0x00 Pending Register High */
u32 iprl0; /* 0x04 Pending Register Low */
u32 imrh0; /* 0x08 Mask Register High */
u32 imrl0; /* 0x0C Mask Register Low */
u32 frch0; /* 0x10 Force Register High */
u32 frcl0; /* 0x14 Force Register Low */
u16 res1; /* 0x18 - 0x19 */
u16 icfg0; /* 0x1A Configuration Register */
u8 simr0; /* 0x1C Set Interrupt Mask */
u8 cimr0; /* 0x1D Clear Interrupt Mask */
u8 clmask0; /* 0x1E Current Level Mask */
u8 slmask; /* 0x1F Saved Level Mask */
u32 res2[8]; /* 0x20 - 0x3F */
u8 icr0[64]; /* 0x40 - 0x7F Control registers */
u32 res3[24]; /* 0x80 - 0xDF */
u8 swiack0; /* 0xE0 Software Interrupt Acknowledge */
u8 res4[3]; /* 0xE1 - 0xE3 */
u8 Lniack0_1; /* 0xE4 Level n interrupt acknowledge resister */
u8 res5[3]; /* 0xE5 - 0xE7 */
u8 Lniack0_2; /* 0xE8 Level n interrupt acknowledge resister */
u8 res6[3]; /* 0xE9 - 0xEB */
u8 Lniack0_3; /* 0xEC Level n interrupt acknowledge resister */
u8 res7[3]; /* 0xED - 0xEF */
u8 Lniack0_4; /* 0xF0 Level n interrupt acknowledge resister */
u8 res8[3]; /* 0xF1 - 0xF3 */
u8 Lniack0_5; /* 0xF4 Level n interrupt acknowledge resister */
u8 res9[3]; /* 0xF5 - 0xF7 */
u8 Lniack0_6; /* 0xF8 Level n interrupt acknowledge resister */
u8 resa[3]; /* 0xF9 - 0xFB */
u8 Lniack0_7; /* 0xFC Level n interrupt acknowledge resister */
u8 resb[3]; /* 0xFD - 0xFF */
} int0_t;
typedef struct int1_ctrl {
/* Interrupt Controller 1 */
u32 iprh1; /* 0x00 Pending Register High */
u32 iprl1; /* 0x04 Pending Register Low */
u32 imrh1; /* 0x08 Mask Register High */
u32 imrl1; /* 0x0C Mask Register Low */
u32 frch1; /* 0x10 Force Register High */
u32 frcl1; /* 0x14 Force Register Low */
u16 res1; /* 0x18 */
u16 icfg1; /* 0x1A Configuration Register */
u8 simr1; /* 0x1C Set Interrupt Mask */
u8 cimr1; /* 0x1D Clear Interrupt Mask */
u16 res2; /* 0x1E - 0x1F */
u32 res3[8]; /* 0x20 - 0x3F */
u8 icr1[64]; /* 0x40 - 0x7F */
u32 res4[24]; /* 0x80 - 0xDF */
u8 swiack1; /* 0xE0 Software Interrupt Acknowledge */
u8 res5[3]; /* 0xE1 - 0xE3 */
u8 Lniack1_1; /* 0xE4 Level n interrupt acknowledge resister */
u8 res6[3]; /* 0xE5 - 0xE7 */
u8 Lniack1_2; /* 0xE8 Level n interrupt acknowledge resister */
u8 res7[3]; /* 0xE9 - 0xEB */
u8 Lniack1_3; /* 0xEC Level n interrupt acknowledge resister */
u8 res8[3]; /* 0xED - 0xEF */
u8 Lniack1_4; /* 0xF0 Level n interrupt acknowledge resister */
u8 res9[3]; /* 0xF1 - 0xF3 */
u8 Lniack1_5; /* 0xF4 Level n interrupt acknowledge resister */
u8 resa[3]; /* 0xF5 - 0xF7 */
u8 Lniack1_6; /* 0xF8 Level n interrupt acknowledge resister */
u8 resb[3]; /* 0xF9 - 0xFB */
u8 Lniack1_7; /* 0xFC Level n interrupt acknowledge resister */
u8 resc[3]; /* 0xFD - 0xFF */
} int1_t;
/*********************************************************************
* Global Interrupt Acknowledge (IACK)
*********************************************************************/
typedef struct iack {
u8 resv0[0xE0];
u8 gswiack;
u8 resv1[0x3];
u8 gl1iack;
u8 resv2[0x3];
u8 gl2iack;
u8 resv3[0x3];
u8 gl3iack;
u8 resv4[0x3];
u8 gl4iack;
u8 resv5[0x3];
u8 gl5iack;
u8 resv6[0x3];
u8 gl6iack;
u8 resv7[0x3];
u8 gl7iack;
} iack_t;
/*********************************************************************
* DMA Serial Peripheral Interface (DSPI)
*********************************************************************/
typedef struct dspi {
u32 dmcr;
u8 resv0[0x4];
u32 dtcr;
u32 dctar0;
u32 dctar1;
u32 dctar2;
u32 dctar3;
u32 dctar4;
u32 dctar5;
u32 dctar6;
u32 dctar7;
u32 dsr;
u32 dirsr;
u32 dtfr;
u32 drfr;
u32 dtfdr0;
u32 dtfdr1;
u32 dtfdr2;
u32 dtfdr3;
u8 resv1[0x30];
u32 drfdr0;
u32 drfdr1;
u32 drfdr2;
u32 drfdr3;
} dspi_t;
/*********************************************************************
* Edge Port Module (EPORT)
*********************************************************************/
typedef struct eport {
u16 eppar;
u8 epddr;
u8 epier;
u8 epdr;
u8 eppdr;
u8 epfr;
} eport_t;
/*********************************************************************
* Watchdog Timer Modules (WTM)
*********************************************************************/
typedef struct wtm {
u16 wcr;
u16 wmr;
u16 wcntr;
u16 wsr;
} wtm_t;
/*********************************************************************
* Serial Boot Facility (SBF)
*********************************************************************/
typedef struct sbf {
u8 resv0[0x18];
u16 sbfsr; /* Serial Boot Facility Status Register */
u8 resv1[0x6];
u16 sbfcr; /* Serial Boot Facility Control Register */
} sbf_t;
/*********************************************************************
* Reset Controller Module (RCM)
*********************************************************************/
typedef struct rcm {
u8 rcr;
u8 rsr;
} rcm_t;
/*********************************************************************
* Chip Configuration Module (CCM)
*********************************************************************/
typedef struct ccm {
u8 ccm_resv0[0x4];
u16 ccr; /* Chip Configuration Register (256 TEPBGA, Read-only) */
u8 resv1[0x2];
u16 rcon; /* Reset Configuration (256 TEPBGA, Read-only) */
u16 cir; /* Chip Identification Register (Read-only) */
u8 resv2[0x4];
u16 misccr; /* Miscellaneous Control Register */
u16 cdr; /* Clock Divider Register */
u16 uocsr; /* USB On-the-Go Controller Status Register */
} ccm_t;
/*********************************************************************
* General Purpose I/O Module (GPIO)
*********************************************************************/
typedef struct gpio {
u8 podr_fec0h; /* FEC0 High Port Output Data Register */
u8 podr_fec0l; /* FEC0 Low Port Output Data Register */
u8 podr_ssi; /* SSI Port Output Data Register */
u8 podr_fbctl; /* Flexbus Control Port Output Data Register */
u8 podr_be; /* Flexbus Byte Enable Port Output Data Register */
u8 podr_cs; /* Flexbus Chip-Select Port Output Data Register */
u8 podr_dma; /* DMA Port Output Data Register */
u8 podr_feci2c; /* FEC1 / I2C Port Output Data Register */
u8 resv0[0x1];
u8 podr_uart; /* UART Port Output Data Register */
u8 podr_dspi; /* DSPI Port Output Data Register */
u8 podr_timer; /* Timer Port Output Data Register */
u8 podr_pci; /* PCI Port Output Data Register */
u8 podr_usb; /* USB Port Output Data Register */
u8 podr_atah; /* ATA High Port Output Data Register */
u8 podr_atal; /* ATA Low Port Output Data Register */
u8 podr_fec1h; /* FEC1 High Port Output Data Register */
u8 podr_fec1l; /* FEC1 Low Port Output Data Register */
u8 resv1[0x2];
u8 podr_fbadh; /* Flexbus AD High Port Output Data Register */
u8 podr_fbadmh; /* Flexbus AD Med-High Port Output Data Register */
u8 podr_fbadml; /* Flexbus AD Med-Low Port Output Data Register */
u8 podr_fbadl; /* Flexbus AD Low Port Output Data Register */
u8 pddr_fec0h; /* FEC0 High Port Data Direction Register */
u8 pddr_fec0l; /* FEC0 Low Port Data Direction Register */
u8 pddr_ssi; /* SSI Port Data Direction Register */
u8 pddr_fbctl; /* Flexbus Control Port Data Direction Register */
u8 pddr_be; /* Flexbus Byte Enable Port Data Direction Register */
u8 pddr_cs; /* Flexbus Chip-Select Port Data Direction Register */
u8 pddr_dma; /* DMA Port Data Direction Register */
u8 pddr_feci2c; /* FEC1 / I2C Port Data Direction Register */
u8 resv2[0x1];
u8 pddr_uart; /* UART Port Data Direction Register */
u8 pddr_dspi; /* DSPI Port Data Direction Register */
u8 pddr_timer; /* Timer Port Data Direction Register */
u8 pddr_pci; /* PCI Port Data Direction Register */
u8 pddr_usb; /* USB Port Data Direction Register */
u8 pddr_atah; /* ATA High Port Data Direction Register */
u8 pddr_atal; /* ATA Low Port Data Direction Register */
u8 pddr_fec1h; /* FEC1 High Port Data Direction Register */
u8 pddr_fec1l; /* FEC1 Low Port Data Direction Register */
u8 resv3[0x2];
u8 pddr_fbadh; /* Flexbus AD High Port Data Direction Register */
u8 pddr_fbadmh; /* Flexbus AD Med-High Port Data Direction Register */
u8 pddr_fbadml; /* Flexbus AD Med-Low Port Data Direction Register */
u8 pddr_fbadl; /* Flexbus AD Low Port Data Direction Register */
u8 ppdsdr_fec0h; /* FEC0 High Port Pin Data/Set Data Register */
u8 ppdsdr_fec0l; /* FEC0 Low Port Clear Output Data Register */
u8 ppdsdr_ssi; /* SSI Port Pin Data/Set Data Register */
u8 ppdsdr_fbctl; /* Flexbus Control Port Pin Data/Set Data Register */
u8 ppdsdr_be; /* Flexbus Byte Enable Port Pin Data/Set Data Register */
u8 ppdsdr_cs; /* Flexbus Chip-Select Port Pin Data/Set Data Register */
u8 ppdsdr_dma; /* DMA Port Pin Data/Set Data Register */
u8 ppdsdr_feci2c; /* FEC1 / I2C Port Pin Data/Set Data Register */
u8 resv4[0x1];
u8 ppdsdr_uart; /* UART Port Pin Data/Set Data Register */
u8 ppdsdr_dspi; /* DSPI Port Pin Data/Set Data Register */
u8 ppdsdr_timer; /* FTimer Port Pin Data/Set Data Register */
u8 ppdsdr_pci; /* PCI Port Pin Data/Set Data Register */
u8 ppdsdr_usb; /* USB Port Pin Data/Set Data Register */
u8 ppdsdr_atah; /* ATA High Port Pin Data/Set Data Register */
u8 ppdsdr_atal; /* ATA Low Port Pin Data/Set Data Register */
u8 ppdsdr_fec1h; /* FEC1 High Port Pin Data/Set Data Register */
u8 ppdsdr_fec1l; /* FEC1 Low Port Pin Data/Set Data Register */
u8 resv5[0x2];
u8 ppdsdr_fbadh; /* Flexbus AD High Port Pin Data/Set Data Register */
u8 ppdsdr_fbadmh; /* Flexbus AD Med-High Port Pin Data/Set Data Register */
u8 ppdsdr_fbadml; /* Flexbus AD Med-Low Port Pin Data/Set Data Register */
u8 ppdsdr_fbadl; /* Flexbus AD Low Port Pin Data/Set Data Register */
u8 pclrr_fec0h; /* FEC0 High Port Clear Output Data Register */
u8 pclrr_fec0l; /* FEC0 Low Port Pin Data/Set Data Register */
u8 pclrr_ssi; /* SSI Port Clear Output Data Register */
u8 pclrr_fbctl; /* Flexbus Control Port Clear Output Data Register */
u8 pclrr_be; /* Flexbus Byte Enable Port Clear Output Data Register */
u8 pclrr_cs; /* Flexbus Chip-Select Port Clear Output Data Register */
u8 pclrr_dma; /* DMA Port Clear Output Data Register */
u8 pclrr_feci2c; /* FEC1 / I2C Port Clear Output Data Register */
u8 resv6[0x1];
u8 pclrr_uart; /* UART Port Clear Output Data Register */
u8 pclrr_dspi; /* DSPI Port Clear Output Data Register */
u8 pclrr_timer; /* Timer Port Clear Output Data Register */
u8 pclrr_pci; /* PCI Port Clear Output Data Register */
u8 pclrr_usb; /* USB Port Clear Output Data Register */
u8 pclrr_atah; /* ATA High Port Clear Output Data Register */
u8 pclrr_atal; /* ATA Low Port Clear Output Data Register */
u8 pclrr_fec1h; /* FEC1 High Port Clear Output Data Register */
u8 pclrr_fec1l; /* FEC1 Low Port Clear Output Data Register */
u8 resv7[0x2];
u8 pclrr_fbadh; /* Flexbus AD High Port Clear Output Data Register */
u8 pclrr_fbadmh; /* Flexbus AD Med-High Port Clear Output Data Register */
u8 pclrr_fbadml; /* Flexbus AD Med-Low Port Clear Output Data Register */
u8 pclrr_fbadl; /* Flexbus AD Low Port Clear Output Data Register */
u8 par_fec; /* FEC Pin Assignment Register */
u8 par_dma; /* DMA Pin Assignment Register */
u8 par_fbctl; /* Flexbus Control Pin Assignment Register */
u8 par_dspi; /* DSPI Pin Assignment Register */
u8 par_be; /* Flexbus Byte-Enable Pin Assignment Register */
u8 par_cs; /* Flexbus Chip-Select Pin Assignment Register */
u8 par_timer; /* Time Pin Assignment Register */
u8 par_usb; /* USB Pin Assignment Register */
u8 resv8[0x1];
u8 par_uart; /* UART Pin Assignment Register */
u16 par_feci2c; /* FEC / I2C Pin Assignment Register */
u16 par_ssi; /* SSI Pin Assignment Register */
u16 par_ata; /* ATA Pin Assignment Register */
u8 par_irq; /* IRQ Pin Assignment Register */
u8 resv9[0x1];
u16 par_pci; /* PCI Pin Assignment Register */
u8 mscr_sdram; /* SDRAM Mode Select Control Register */
u8 mscr_pci; /* PCI Mode Select Control Register */
u8 resv10[0x2];
u8 dscr_i2c; /* I2C Drive Strength Control Register */
u8 dscr_flexbus; /* FLEXBUS Drive Strength Control Register */
u8 dscr_fec; /* FEC Drive Strength Control Register */
u8 dscr_uart; /* UART Drive Strength Control Register */
u8 dscr_dspi; /* DSPI Drive Strength Control Register */
u8 dscr_timer; /* TIMER Drive Strength Control Register */
u8 dscr_ssi; /* SSI Drive Strength Control Register */
u8 dscr_dma; /* DMA Drive Strength Control Register */
u8 dscr_debug; /* DEBUG Drive Strength Control Register */
u8 dscr_reset; /* RESET Drive Strength Control Register */
u8 dscr_irq; /* IRQ Drive Strength Control Register */
u8 dscr_usb; /* USB Drive Strength Control Register */
u8 dscr_ata; /* ATA Drive Strength Control Register */
} gpio_t;
/*********************************************************************
* Random Number Generator (RNG)
*********************************************************************/
typedef struct rng {
u32 rngcr;
u32 rngsr;
u32 rnger;
u32 rngout;
} rng_t;
/*********************************************************************
* SDRAM Controller (SDRAMC)
*********************************************************************/
typedef struct sdramc {
u32 sdmr; /* SDRAM Mode/Extended Mode Register */
u32 sdcr; /* SDRAM Control Register */
u32 sdcfg1; /* SDRAM Configuration Register 1 */
u32 sdcfg2; /* SDRAM Chip Select Register */
u8 resv0[0x100];
u32 sdcs0; /* SDRAM Mode/Extended Mode Register */
u32 sdcs1; /* SDRAM Mode/Extended Mode Register */
} sdramc_t;
/*********************************************************************
* Synchronous Serial Interface (SSI)
*********************************************************************/
typedef struct ssi {
u32 tx0;
u32 tx1;
u32 rx0;
u32 rx1;
u32 cr;
u32 isr;
u32 ier;
u32 tcr;
u32 rcr;
u32 ccr;
u8 resv0[0x4];
u32 fcsr;
u8 resv1[0x8];
u32 acr;
u32 acadd;
u32 acdat;
u32 atag;
u32 tmask;
u32 rmask;
} ssi_t;
/*********************************************************************
* Phase Locked Loop (PLL)
*********************************************************************/
typedef struct pll {
u32 pcr; /* PLL Control Register */
u32 psr; /* PLL Status Register */
} pll_t;
typedef struct pci {
u32 idr; /* 0x00 Device Id / Vendor Id Register */
u32 scr; /* 0x04 Status / command Register */
u32 ccrir; /* 0x08 Class Code / Revision Id Register */
u32 cr1; /* 0x0c Configuration 1 Register */
u32 bar0; /* 0x10 Base address register 0 Register */
u32 bar1; /* 0x14 Base address register 1 Register */
u32 bar2; /* 0x18 Base address register 2 Register */
u32 bar3; /* 0x1c Base address register 3 Register */
u32 bar4; /* 0x20 Base address register 4 Register */
u32 bar5; /* 0x24 Base address register 5 Register */
u32 ccpr; /* 0x28 Cardbus CIS Pointer Register */
u32 sid; /* 0x2c Subsystem ID / Subsystem Vendor ID Register */
u32 erbar; /* 0x30 Expansion ROM Base Address Register */
u32 cpr; /* 0x34 Capabilities Pointer Register */
u32 rsvd1; /* 0x38 */
u32 cr2; /* 0x3c Configuration Register 2 */
u32 rsvd2[8]; /* 0x40 - 0x5f */
/* General control / status registers */
u32 gscr; /* 0x60 Global Status / Control Register */
u32 tbatr0a; /* 0x64 Target Base Address Translation Register 0 */
u32 tbatr1a; /* 0x68 Target Base Address Translation Register 1 */
u32 tcr1; /* 0x6c Target Control 1 Register */
u32 iw0btar; /* 0x70 Initiator Window 0 Base/Translation addr */
u32 iw1btar; /* 0x74 Initiator Window 1 Base/Translation addr */
u32 iw2btar; /* 0x78 Initiator Window 2 Base/Translation addr */
u32 rsvd3; /* 0x7c */
u32 iwcr; /* 0x80 Initiator Window Configuration Register */
u32 icr; /* 0x84 Initiator Control Register */
u32 isr; /* 0x88 Initiator Status Register */
u32 tcr2; /* 0x8c Target Control 2 Register */
u32 tbatr0; /* 0x90 Target Base Address Translation Register 0 */
u32 tbatr1; /* 0x94 Target Base Address Translation Register 1 */
u32 tbatr2; /* 0x98 Target Base Address Translation Register 2 */
u32 tbatr3; /* 0x9c Target Base Address Translation Register 3 */
u32 tbatr4; /* 0xa0 Target Base Address Translation Register 4 */
u32 tbatr5; /* 0xa4 Target Base Address Translation Register 5 */
u32 intr; /* 0xa8 Interrupt Register */
u32 rsvd4[19]; /* 0xac - 0xf7 */
u32 car; /* 0xf8 Configuration Address Register */
} pci_t;
typedef struct pci_arbiter {
/* Pci Arbiter Registers */
union {
u32 acr; /* Arbiter Control Register */
u32 asr; /* Arbiter Status Register */
};
} pciarb_t;
/* Register read/write struct */
typedef struct scm1 {
u32 mpr; /* 0x00 Master Privilege Register */
u32 rsvd1[7];
u32 pacra; /* 0x20 Peripheral Access Control Register A */
u32 pacrb; /* 0x24 Peripheral Access Control Register B */
u32 pacrc; /* 0x28 Peripheral Access Control Register C */
u32 pacrd; /* 0x2C Peripheral Access Control Register D */
u32 rsvd2[4];
u32 pacre; /* 0x40 Peripheral Access Control Register E */
u32 pacrf; /* 0x44 Peripheral Access Control Register F */
u32 pacrg; /* 0x48 Peripheral Access Control Register G */
} scm1_t;
/********************************************************************/
typedef struct rtcex {
u32 rsvd1[3];
u32 gocu;
u32 gocl;
} rtcex_t;
#endif /* __IMMAP_5445X__ */

221
include/asm-m68k/io.h
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@@ -1,8 +1,221 @@
#ifndef __ASM_M68K_IO_H_
#define __ASM_M68K_IO_H_
/*
* IO header file
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __ASM_M68K_IO_H__
#define __ASM_M68K_IO_H__
#include <asm/byteorder.h>
#define readb(addr) in_8((volatile u8 *)(addr))
#define writeb(b,addr) out_8((volatile u8 *)(addr), (b))
#if !defined(__BIG_ENDIAN)
#define readw(addr) (*(volatile u16 *) (addr))
#define readl(addr) (*(volatile u32 *) (addr))
#define writew(b,addr) ((*(volatile u16 *) (addr)) = (b))
#define writel(b,addr) ((*(volatile u32 *) (addr)) = (b))
#else
#define readw(addr) in_le16((volatile u16 *)(addr))
#define readl(addr) in_le32((volatile u32 *)(addr))
#define writew(b,addr) out_le16((volatile u16 *)(addr),(b))
#define writel(b,addr) out_le32((volatile u32 *)(addr),(b))
#endif
/*
* The insw/outsw/insl/outsl macros don't do byte-swapping.
* They are only used in practice for transferring buffers which
* are arrays of bytes, and byte-swapping is not appropriate in
* that case. - paulus
*/
#define insb(port, buf, ns) _insb((u8 *)((port)+_IO_BASE), (buf), (ns))
#define outsb(port, buf, ns) _outsb((u8 *)((port)+_IO_BASE), (buf), (ns))
#define insw(port, buf, ns) _insw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
#define outsw(port, buf, ns) _outsw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
#define insl(port, buf, nl) _insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
#define outsl(port, buf, nl) _outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
#define inb(port) in_8((u8 *)((port)+_IO_BASE))
#define outb(val, port) out_8((u8 *)((port)+_IO_BASE), (val))
#if !defined(__BIG_ENDIAN)
#define inw(port) in_be16((u16 *)((port)+_IO_BASE))
#define outw(val, port) out_be16((u16 *)((port)+_IO_BASE), (val))
#define inl(port) in_be32((u32 *)((port)+_IO_BASE))
#define outl(val, port) out_be32((u32 *)((port)+_IO_BASE), (val))
#else
#define inw(port) in_le16((u16 *)((port)+_IO_BASE))
#define outw(val, port) out_le16((u16 *)((port)+_IO_BASE), (val))
#define inl(port) in_le32((u32 *)((port)+_IO_BASE))
#define outl(val, port) out_le32((u32 *)((port)+_IO_BASE), (val))
#endif
extern inline void _insb(volatile u8 * port, void *buf, int ns)
{
u8 *data = (u8 *) buf;
while (ns--)
*data++ = *port;
}
extern inline void _outsb(volatile u8 * port, const void *buf, int ns)
{
u8 *data = (u8 *) buf;
while (ns--)
*port = *data++;
}
extern inline void _insw(volatile u16 * port, void *buf, int ns)
{
u16 *data = (u16 *) buf;
while (ns--)
*data++ = __sw16(*port);
}
extern inline void _outsw(volatile u16 * port, const void *buf, int ns)
{
u16 *data = (u16 *) buf;
while (ns--) {
*port = __sw16(*data);
data++;
}
}
extern inline void _insl(volatile u32 * port, void *buf, int nl)
{
u32 *data = (u32 *) buf;
while (nl--)
*data++ = __sw32(*port);
}
extern inline void _outsl(volatile u32 * port, const void *buf, int nl)
{
u32 *data = (u32 *) buf;
while (nl--) {
*port = __sw32(*data);
data++;
}
}
extern inline void _insw_ns(volatile u16 * port, void *buf, int ns)
{
u16 *data = (u16 *) buf;
while (ns--)
*data++ = *port;
}
extern inline void _outsw_ns(volatile u16 * port, const void *buf, int ns)
{
u16 *data = (u16 *) buf;
while (ns--) {
*port = *data++;
}
}
extern inline void _insl_ns(volatile u32 * port, void *buf, int nl)
{
u32 *data = (u32 *) buf;
while (nl--)
*data++ = *port;
}
extern inline void _outsl_ns(volatile u32 * port, const void *buf, int nl)
{
u32 *data = (u32 *) buf;
while (nl--) {
*port = *data;
data++;
}
}
/*
* The *_ns versions below don't do byte-swapping.
* Neither do the standard versions now, these are just here
* for older code.
*/
#define insw_ns(port, buf, ns) _insw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
#define outsw_ns(port, buf, ns) _outsw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
#define insl_ns(port, buf, nl) _insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
#define outsl_ns(port, buf, nl) _outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
#define IO_SPACE_LIMIT ~0
/*
* 8, 16 and 32 bit, big and little endian I/O operations, with barrier.
*/
extern inline int in_8(volatile u8 * addr)
{
return (int)*addr;
}
extern inline void out_8(volatile u8 * addr, int val)
{
*addr = (u8) val;
}
extern inline int in_le16(volatile u16 * addr)
{
return __sw16(*addr);
}
extern inline int in_be16(volatile u16 * addr)
{
return (*addr & 0xFFFF);
}
extern inline void out_le16(volatile u16 * addr, int val)
{
*addr = __sw16(val);
}
extern inline void out_be16(volatile u16 * addr, int val)
{
*addr = (u16) val;
}
extern inline unsigned in_le32(volatile u32 * addr)
{
return __sw32(*addr);
}
extern inline unsigned in_be32(volatile u32 * addr)
{
return (*addr);
}
extern inline void out_le32(volatile unsigned *addr, int val)
{
*addr = __sw32(val);
}
extern inline void out_be32(volatile unsigned *addr, int val)
{
*addr = val;
}
static inline void sync(void)
{
/* This sync function is for PowerPC or other architecture instruction
* ColdFire does not have this instruction. Dummy function, added for
* compatibility (CFI driver)
*/
}
#endif /* __ASM_M68K_IO_H_ */
#endif /* __ASM_M68K_IO_H__ */

905
include/asm-m68k/m5235.h Normal file
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@@ -0,0 +1,905 @@
/*
* mcf5329.h -- Definitions for Freescale Coldfire 5329
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef mcf5235_h
#define mcf5235_h
/****************************************************************************/
/*********************************************************************
* System Control Module (SCM)
*********************************************************************/
/* Bit definition and macros for SCM_IPSBAR */
#define SCM_IPSBAR_BA(x) (((x)&0x03)<<30)
#define SCM_IPSBAR_V (0x00000001)
/* Bit definition and macros for SCM_RAMBAR */
#define SCM_RAMBAR_BA(x) (((x)&0xFFFF)<<16)
#define SCM_RAMBAR_BDE (0x00000200)
/* Bit definition and macros for SCM_CRSR */
#define SCM_CRSR_EXT (0x80)
/* Bit definitions and macros for SCM_CWCR */
#define SCM_CWCR_CWE (0x80)
#define SCM_CWCR_CWRI (0x40)
#define SCM_CWCR_CWT(x) (((x)&0x07)<<3)
#define SCM_CWCR_CWTA (0x04)
#define SCM_CWCR_CWTAVAL (0x02)
#define SCM_CWCR_CWTIC (0x01)
/* Bit definitions and macros for SCM_LPICR */
#define SCM_LPICR_ENBSTOP (0x80)
#define SCM_LPICR_XLPM_IPL(x) (((x)&0x07)<<4)
#define SCM_LPICR_XLPM_IPL_ANY (0x00)
#define SCM_LPICR_XLPM_IPL_L2_7 (0x10)
#define SCM_LPICR_XLPM_IPL_L3_7 (0x20)
#define SCM_LPICR_XLPM_IPL_L4_7 (0x30)
#define SCM_LPICR_XLPM_IPL_L5_7 (0x40)
#define SCM_LPICR_XLPM_IPL_L6_7 (0x50)
#define SCM_LPICR_XLPM_IPL_L7 (0x70)
/* Bit definitions and macros for SCM_DMAREQC */
#define SCM_DMAREQC_EXT(x) (((x)&0x0F)<<16)
#define SCM_DMAREQC_EXT_ETPU (0x00080000)
#define SCM_DMAREQC_EXT_EXTDREQ2 (0x00040000)
#define SCM_DMAREQC_EXT_EXTDREQ1 (0x00020000)
#define SCM_DMAREQC_EXT_EXTDREQ0 (0x00010000)
#define SCM_DMAREQC_DMAC3(x) (((x)&0x0F)<<12)
#define SCM_DMAREQC_DMAC2(x) (((x)&0x0F)<<8)
#define SCM_DMAREQC_DMAC1(x) (((x)&0x0F)<<4)
#define SCM_DMAREQC_DMAC0(x) (((x)&0x0F))
#define SCM_DMAREQC_DMACn_DTMR0 (0x04)
#define SCM_DMAREQC_DMACn_DTMR1 (0x05)
#define SCM_DMAREQC_DMACn_DTMR2 (0x06)
#define SCM_DMAREQC_DMACn_DTMR3 (0x07)
#define SCM_DMAREQC_DMACn_UART0RX (0x08)
#define SCM_DMAREQC_DMACn_UART1RX (0x09)
#define SCM_DMAREQC_DMACn_UART2RX (0x0A)
#define SCM_DMAREQC_DMACn_UART0TX (0x0C)
#define SCM_DMAREQC_DMACn_UART1TX (0x0D)
#define SCM_DMAREQC_DMACn_UART3TX (0x0E)
/* Bit definitions and macros for SCM_MPARK */
#define SCM_MPARK_M2_P_EN (0x02000000)
#define SCM_MPARK_M3_PRTY_MSK (0x00C00000)
#define SCM_MPARK_M3_PRTY_4TH (0x00000000)
#define SCM_MPARK_M3_PRTY_3RD (0x00400000)
#define SCM_MPARK_M3_PRTY_2ND (0x00800000)
#define SCM_MPARK_M3_PRTY_1ST (0x00C00000)
#define SCM_MPARK_M2_PRTY_MSK (0x00300000)
#define SCM_MPARK_M2_PRTY_4TH (0x00000000)
#define SCM_MPARK_M2_PRTY_3RD (0x00100000)
#define SCM_MPARK_M2_PRTY_2ND (0x00200000)
#define SCM_MPARK_M2_PRTY_1ST (0x00300000)
#define SCM_MPARK_M0_PRTY_MSK (0x000C0000)
#define SCM_MPARK_M0_PRTY_4TH (0x00000000)
#define SCM_MPARK_M0_PRTY_3RD (0x00040000)
#define SCM_MPARK_M0_PRTY_2ND (0x00080000)
#define SCM_MPARK_M0_PRTY_1ST (0x000C0000)
#define SCM_MPARK_FIXED (0x00004000)
#define SCM_MPARK_TIMEOUT (0x00002000)
#define SCM_MPARK_PRKLAST (0x00001000)
#define SCM_MPARK_LCKOUT_TIME(x) (((x)&0x0F)<<8)
/* Bit definitions and macros for SCM_MPR */
#define SCM_MPR_MPR3 (0x08)
#define SCM_MPR_MPR2 (0x04)
#define SCM_MPR_MPR1 (0x02)
#define SCM_MPR_MPR0 (0x01)
/* Bit definitions and macros for SCM_PACRn */
#define SCM_PACRn_LOCK1 (0x80)
#define SCM_PACRn_ACCESSCTRL1(x) (((x)&0x07)<<4)
#define SCM_PACRn_LOCK0 (0x08)
#define SCM_PACRn_ACCESSCTRL0(x) (((x)&0x07))
/* Bit definitions and macros for SCM_GPACR */
#define SCM_PACRn_LOCK (0x80)
#define SCM_PACRn_ACCESSCTRL0(x) (((x)&0x07))
/*********************************************************************
* SDRAM Controller (SDRAMC)
*********************************************************************/
/* Bit definitions and macros for SDRAMC_DCR */
#define SDRAMC_DCR_NAM (0x2000)
#define SDRAMC_DCR_COC (0x1000)
#define SDRAMC_DCR_IS (0x0800)
#define SDRAMC_DCR_RTIM_MASK (0x0C00)
#define SDRAMC_DCR_RTIM_3CLKS (0x0000)
#define SDRAMC_DCR_RTIM_6CLKS (0x0200)
#define SDRAMC_DCR_RTIM_9CLKS (0x0400)
#define SDRAMC_DCR_RC(x) (((x)&0xFF)<<8)
/* Bit definitions and macros for SDRAMC_DARCn */
#define SDRAMC_DARCn_BA(x) (((x)&0xFFFC)<<18)
#define SDRAMC_DARCn_RE (0x00008000)
#define SDRAMC_DARCn_CASL_MASK (0x00003000)
#define SDRAMC_DARCn_CASL_C0 (0x00000000)
#define SDRAMC_DARCn_CASL_C1 (0x00001000)
#define SDRAMC_DARCn_CASL_C2 (0x00002000)
#define SDRAMC_DARCn_CASL_C3 (0x00003000)
#define SDRAMC_DARCn_CBM_MASK (0x00000700)
#define SDRAMC_DARCn_CBM_CMD17 (0x00000000)
#define SDRAMC_DARCn_CBM_CMD18 (0x00000100)
#define SDRAMC_DARCn_CBM_CMD19 (0x00000200)
#define SDRAMC_DARCn_CBM_CMD20 (0x00000300)
#define SDRAMC_DARCn_CBM_CMD21 (0x00000400)
#define SDRAMC_DARCn_CBM_CMD22 (0x00000500)
#define SDRAMC_DARCn_CBM_CMD23 (0x00000600)
#define SDRAMC_DARCn_CBM_CMD24 (0x00000700)
#define SDRAMC_DARCn_IMRS (0x00000040)
#define SDRAMC_DARCn_PS_MASK (0x00000030)
#define SDRAMC_DARCn_PS_32 (0x00000000)
#define SDRAMC_DARCn_PS_16 (0x00000010)
#define SDRAMC_DARCn_PS_8 (0x00000020)
#define SDRAMC_DARCn_IP (0x00000008)
/* Bit definitions and macros for SDRAMC_DMRn */
#define SDRAMC_DMRn_BAM(x) (((x)&0x3FFF)<<18)
#define SDRAMC_DMRn_WP (0x00000100)
#define SDRAMC_DMRn_V (0x00000001)
/*********************************************************************
* FlexBus Chip Selects (FBCS)
*********************************************************************/
/* Bit definitions and macros for FBCS_CSMR */
#define FBCS_CSMR_BAM(x) (((x)&0xFFFF)<<16)
#define FBCS_CSMR_BAM_4G (0xFFFF0000)
#define FBCS_CSMR_BAM_2G (0x7FFF0000)
#define FBCS_CSMR_BAM_1G (0x3FFF0000)
#define FBCS_CSMR_BAM_1024M (0x3FFF0000)
#define FBCS_CSMR_BAM_512M (0x1FFF0000)
#define FBCS_CSMR_BAM_256M (0x0FFF0000)
#define FBCS_CSMR_BAM_128M (0x07FF0000)
#define FBCS_CSMR_BAM_64M (0x03FF0000)
#define FBCS_CSMR_BAM_32M (0x01FF0000)
#define FBCS_CSMR_BAM_16M (0x00FF0000)
#define FBCS_CSMR_BAM_8M (0x007F0000)
#define FBCS_CSMR_BAM_4M (0x003F0000)
#define FBCS_CSMR_BAM_2M (0x001F0000)
#define FBCS_CSMR_BAM_1M (0x000F0000)
#define FBCS_CSMR_BAM_1024K (0x000F0000)
#define FBCS_CSMR_BAM_512K (0x00070000)
#define FBCS_CSMR_BAM_256K (0x00030000)
#define FBCS_CSMR_BAM_128K (0x00010000)
#define FBCS_CSMR_BAM_64K (0x00000000)
#define FBCS_CSMR_WP (0x00000100)
#define FBCS_CSMR_V (0x00000001)
/* Bit definitions and macros for FBCS_CSCR */
#define FBCS_CSCR_SRWS(x) (((x)&0x03)<<14)
#define FBCS_CSCR_IWS(x) (((x)&0x0F)<<10)
#define FBCS_CSCR_AA (0x0100)
#define FBCS_CSCR_PS_MASK (0x00C0)
#define FBCS_CSCR_PS_32 (0x0000)
#define FBCS_CSCR_PS_16 (0x0080)
#define FBCS_CSCR_PS_8 (0x0040)
#define FBCS_CSCR_BEM (0x0020)
#define FBCS_CSCR_BSTR (0x0010)
#define FBCS_CSCR_BSTW (0x0008)
#define FBCS_CSCR_SWWS(x) ((x)&0x07)
/*********************************************************************
* Queued Serial Peripheral Interface (QSPI)
*********************************************************************/
/* Bit definitions and macros for QSPI_QMR */
#define QSPI_QMR_MSTR (0x8000)
#define QSPI_QMR_DOHIE (0x4000)
#define QSPI_QMR_BITS(x) (((x)&0x000F)<<10)
#define QSPI_QMR_CPOL (0x0200)
#define QSPI_QMR_CPHA (0x0100)
#define QSPI_QMR_BAUD(x) ((x)&0x00FF)
/* Bit definitions and macros for QSPI_QDLYR */
#define QSPI_QDLYR_SPE (0x8000)
#define QSPI_QDLYR_QCD(x) (((x)&0x007F)<<8)
#define QSPI_QDLYR_DTL(x) ((x)&0x00FF)
/* Bit definitions and macros for QSPI_QWR */
#define QSPI_QWR_HALT (0x8000)
#define QSPI_QWR_WREN (0x4000)
#define QSPI_QWR_WRTO (0x2000)
#define QSPI_QWR_CSIV (0x1000)
#define QSPI_QWR_ENDQP(x) (((x)&0x000F)<<8)
#define QSPI_QWR_NEWQP(x) ((x)&0x000F)
/* Bit definitions and macros for QSPI_QIR */
#define QSPI_QIR_WCEFB (0x8000)
#define QSPI_QIR_ABRTB (0x4000)
#define QSPI_QIR_ABRTL (0x1000)
#define QSPI_QIR_WCEFE (0x0800)
#define QSPI_QIR_ABRTE (0x0400)
#define QSPI_QIR_SPIFE (0x0100)
#define QSPI_QIR_WCEF (0x0008)
#define QSPI_QIR_ABRT (0x0004)
#define QSPI_QIR_SPIF (0x0001)
/* Bit definitions and macros for QSPI_QAR */
#define QSPI_QAR_ADDR(x) ((x)&0x003F)
/* Bit definitions and macros for QSPI_QDR */
#define QSPI_QDR_CONT (0x8000)
#define QSPI_QDR_BITSE (0x4000)
#define QSPI_QDR_DT (0x2000)
#define QSPI_QDR_DSCK (0x1000)
#define QSPI_QDR_QSPI_CS3 (0x0800)
#define QSPI_QDR_QSPI_CS2 (0x0400)
#define QSPI_QDR_QSPI_CS1 (0x0200)
#define QSPI_QDR_QSPI_CS0 (0x0100)
/*********************************************************************
* Interrupt Controller (INTC)
*********************************************************************/
#define INT0_LO_RSVD0 (0)
#define INT0_LO_EPORT1 (1)
#define INT0_LO_EPORT2 (2)
#define INT0_LO_EPORT3 (3)
#define INT0_LO_EPORT4 (4)
#define INT0_LO_EPORT5 (5)
#define INT0_LO_EPORT6 (6)
#define INT0_LO_EPORT7 (7)
#define INT0_LO_SCM (8)
#define INT0_LO_DMA0 (9)
#define INT0_LO_DMA1 (10)
#define INT0_LO_DMA2 (11)
#define INT0_LO_DMA3 (12)
#define INT0_LO_UART0 (13)
#define INT0_LO_UART1 (14)
#define INT0_LO_UART2 (15)
#define INT0_LO_RSVD1 (16)
#define INT0_LO_I2C (17)
#define INT0_LO_QSPI (18)
#define INT0_LO_DTMR0 (19)
#define INT0_LO_DTMR1 (20)
#define INT0_LO_DTMR2 (21)
#define INT0_LO_DTMR3 (22)
#define INT0_LO_FEC_TXF (23)
#define INT0_LO_FEC_TXB (24)
#define INT0_LO_FEC_UN (25)
#define INT0_LO_FEC_RL (26)
#define INT0_LO_FEC_RXF (27)
#define INT0_LO_FEC_RXB (28)
#define INT0_LO_FEC_MII (29)
#define INT0_LO_FEC_LC (30)
#define INT0_LO_FEC_HBERR (31)
#define INT0_HI_FEC_GRA (32)
#define INT0_HI_FEC_EBERR (33)
#define INT0_HI_FEC_BABT (34)
#define INT0_HI_FEC_BABR (35)
#define INT0_HI_PIT0 (36)
#define INT0_HI_PIT1 (37)
#define INT0_HI_PIT2 (38)
#define INT0_HI_PIT3 (39)
#define INT0_HI_RNG (40)
#define INT0_HI_SKHA (41)
#define INT0_HI_MDHA (42)
#define INT0_HI_CAN1_BUF0I (43)
#define INT0_HI_CAN1_BUF1I (44)
#define INT0_HI_CAN1_BUF2I (45)
#define INT0_HI_CAN1_BUF3I (46)
#define INT0_HI_CAN1_BUF4I (47)
#define INT0_HI_CAN1_BUF5I (48)
#define INT0_HI_CAN1_BUF6I (49)
#define INT0_HI_CAN1_BUF7I (50)
#define INT0_HI_CAN1_BUF8I (51)
#define INT0_HI_CAN1_BUF9I (52)
#define INT0_HI_CAN1_BUF10I (53)
#define INT0_HI_CAN1_BUF11I (54)
#define INT0_HI_CAN1_BUF12I (55)
#define INT0_HI_CAN1_BUF13I (56)
#define INT0_HI_CAN1_BUF14I (57)
#define INT0_HI_CAN1_BUF15I (58)
#define INT0_HI_CAN1_ERRINT (59)
#define INT0_HI_CAN1_BOFFINT (60)
/* 60-63 Reserved */
/* 0 - 7 Reserved */
#define INT1_LO_CAN1_BUF0I (8)
#define INT1_LO_CAN1_BUF1I (9)
#define INT1_LO_CAN1_BUF2I (10)
#define INT1_LO_CAN1_BUF3I (11)
#define INT1_LO_CAN1_BUF4I (12)
#define INT1_LO_CAN1_BUF5I (13)
#define INT1_LO_CAN1_BUF6I (14)
#define INT1_LO_CAN1_BUF7I (15)
#define INT1_LO_CAN1_BUF8I (16)
#define INT1_LO_CAN1_BUF9I (17)
#define INT1_LO_CAN1_BUF10I (18)
#define INT1_LO_CAN1_BUF11I (19)
#define INT1_LO_CAN1_BUF12I (20)
#define INT1_LO_CAN1_BUF13I (21)
#define INT1_LO_CAN1_BUF14I (22)
#define INT1_LO_CAN1_BUF15I (23)
#define INT1_LO_CAN1_ERRINT (24)
#define INT1_LO_CAN1_BOFFINT (25)
/* 26 Reserved */
#define INT1_LO_ETPU_TC0F (27)
#define INT1_LO_ETPU_TC1F (28)
#define INT1_LO_ETPU_TC2F (29)
#define INT1_LO_ETPU_TC3F (30)
#define INT1_LO_ETPU_TC4F (31)
#define INT1_HI_ETPU_TC5F (32)
#define INT1_HI_ETPU_TC6F (33)
#define INT1_HI_ETPU_TC7F (34)
#define INT1_HI_ETPU_TC8F (35)
#define INT1_HI_ETPU_TC9F (36)
#define INT1_HI_ETPU_TC10F (37)
#define INT1_HI_ETPU_TC11F (38)
#define INT1_HI_ETPU_TC12F (39)
#define INT1_HI_ETPU_TC13F (40)
#define INT1_HI_ETPU_TC14F (41)
#define INT1_HI_ETPU_TC15F (42)
#define INT1_HI_ETPU_TC16F (43)
#define INT1_HI_ETPU_TC17F (44)
#define INT1_HI_ETPU_TC18F (45)
#define INT1_HI_ETPU_TC19F (46)
#define INT1_HI_ETPU_TC20F (47)
#define INT1_HI_ETPU_TC21F (48)
#define INT1_HI_ETPU_TC22F (49)
#define INT1_HI_ETPU_TC23F (50)
#define INT1_HI_ETPU_TC24F (51)
#define INT1_HI_ETPU_TC25F (52)
#define INT1_HI_ETPU_TC26F (53)
#define INT1_HI_ETPU_TC27F (54)
#define INT1_HI_ETPU_TC28F (55)
#define INT1_HI_ETPU_TC29F (56)
#define INT1_HI_ETPU_TC30F (57)
#define INT1_HI_ETPU_TC31F (58)
#define INT1_HI_ETPU_TGIF (59)
/* Bit definitions and macros for INTC_IPRH */
#define INTC_IPRH_INT63 (0x80000000)
#define INTC_IPRH_INT62 (0x40000000)
#define INTC_IPRH_INT61 (0x20000000)
#define INTC_IPRH_INT60 (0x10000000)
#define INTC_IPRH_INT59 (0x08000000)
#define INTC_IPRH_INT58 (0x04000000)
#define INTC_IPRH_INT57 (0x02000000)
#define INTC_IPRH_INT56 (0x01000000)
#define INTC_IPRH_INT55 (0x00800000)
#define INTC_IPRH_INT54 (0x00400000)
#define INTC_IPRH_INT53 (0x00200000)
#define INTC_IPRH_INT52 (0x00100000)
#define INTC_IPRH_INT51 (0x00080000)
#define INTC_IPRH_INT50 (0x00040000)
#define INTC_IPRH_INT49 (0x00020000)
#define INTC_IPRH_INT48 (0x00010000)
#define INTC_IPRH_INT47 (0x00008000)
#define INTC_IPRH_INT46 (0x00004000)
#define INTC_IPRH_INT45 (0x00002000)
#define INTC_IPRH_INT44 (0x00001000)
#define INTC_IPRH_INT43 (0x00000800)
#define INTC_IPRH_INT42 (0x00000400)
#define INTC_IPRH_INT41 (0x00000200)
#define INTC_IPRH_INT40 (0x00000100)
#define INTC_IPRH_INT39 (0x00000080)
#define INTC_IPRH_INT38 (0x00000040)
#define INTC_IPRH_INT37 (0x00000020)
#define INTC_IPRH_INT36 (0x00000010)
#define INTC_IPRH_INT35 (0x00000008)
#define INTC_IPRH_INT34 (0x00000004)
#define INTC_IPRH_INT33 (0x00000002)
#define INTC_IPRH_INT32 (0x00000001)
/* Bit definitions and macros for INTC_IPRL */
#define INTC_IPRL_INT31 (0x80000000)
#define INTC_IPRL_INT30 (0x40000000)
#define INTC_IPRL_INT29 (0x20000000)
#define INTC_IPRL_INT28 (0x10000000)
#define INTC_IPRL_INT27 (0x08000000)
#define INTC_IPRL_INT26 (0x04000000)
#define INTC_IPRL_INT25 (0x02000000)
#define INTC_IPRL_INT24 (0x01000000)
#define INTC_IPRL_INT23 (0x00800000)
#define INTC_IPRL_INT22 (0x00400000)
#define INTC_IPRL_INT21 (0x00200000)
#define INTC_IPRL_INT20 (0x00100000)
#define INTC_IPRL_INT19 (0x00080000)
#define INTC_IPRL_INT18 (0x00040000)
#define INTC_IPRL_INT17 (0x00020000)
#define INTC_IPRL_INT16 (0x00010000)
#define INTC_IPRL_INT15 (0x00008000)
#define INTC_IPRL_INT14 (0x00004000)
#define INTC_IPRL_INT13 (0x00002000)
#define INTC_IPRL_INT12 (0x00001000)
#define INTC_IPRL_INT11 (0x00000800)
#define INTC_IPRL_INT10 (0x00000400)
#define INTC_IPRL_INT9 (0x00000200)
#define INTC_IPRL_INT8 (0x00000100)
#define INTC_IPRL_INT7 (0x00000080)
#define INTC_IPRL_INT6 (0x00000040)
#define INTC_IPRL_INT5 (0x00000020)
#define INTC_IPRL_INT4 (0x00000010)
#define INTC_IPRL_INT3 (0x00000008)
#define INTC_IPRL_INT2 (0x00000004)
#define INTC_IPRL_INT1 (0x00000002)
#define INTC_IPRL_INT0 (0x00000001)
/* Bit definitions and macros for INTC_IRLR */
#define INTC_IRLRn(x) (((x)&0x7F)<<1)
/* Bit definitions and macros for INTC_IACKLPRn */
#define INTC_IACKLPRn_LEVEL(x) (((x)&0x07)<<4)
#define INTC_IACKLPRn_PRI(x) ((x)&0x0F)
/* Bit definitions and macros for INTC_ICRnx */
#define INTC_ICRnx_IL(x) (((x)&0x07)<<3)
#define INTC_ICRnx_IP(x) ((x)&0x07)
/*********************************************************************
* General Purpose I/O (GPIO)
*********************************************************************/
/* Bit definitions and macros for GPIO_PODR */
#define GPIO_PODR_ADDR(x) (((x)&0x07)<<5)
#define GPIO_PODR_ADDR_MASK (0xE0)
#define GPIO_PODR_BS(x) ((x)&0x0F)
#define GPIO_PODR_BS_MASK (0x0F)
#define GPIO_PODR_CS(x) (((x)&0x7F)<<1)
#define GPIO_PODR_CS_MASK (0xFE)
#define GPIO_PODR_SDRAM(X) ((x)&0x3F)
#define GPIO_PODR_SDRAM_MASK (0x3F)
#define GPIO_PODR_FECI2C(x) GPIO_PODR_BS(x)
#define GPIO_PODR_FECI2C_MASK GPIO_PODR_BS_MASK
#define GPIO_PODR_UARTH(x) ((x)&0x03)
#define GPIO_PODR_UARTH_MASK (0x03)
#define GPIO_PODR_QSPI(x) ((x)&0x1F)
#define GPIO_PODR_QSPI_MASK (0x1F)
#define GPIO_PODR_ETPU(x) ((x)&0x07)
#define GPIO_PODR_ETPU_MASK (0x07)
/* Bit definitions and macros for GPIO_PDDR */
#define GPIO_PDDR_ADDR(x) GPIO_PODR_ADDR(x)
#define GPIO_PDDR_ADDR_MASK GPIO_PODR_ADDR_MASK
#define GPIO_PDDR_BS(x) GPIO_PODR_BS(x)
#define GPIO_PDDR_BS_MASK GPIO_PODR_BS_MASK
#define GPIO_PDDR_CS(x) GPIO_PODR_CS(x)
#define GPIO_PDDR_CS_MASK GPIO_PODR_CS_MASK
#define GPIO_PDDR_SDRAM(X) GPIO_PODR_SDRAM(X)
#define GPIO_PDDR_SDRAM_MASK GPIO_PODR_SDRAM_MASK
#define GPIO_PDDR_FECI2C(x) GPIO_PDDR_BS(x)
#define GPIO_PDDR_FECI2C_MASK GPIO_PDDR_BS_MASK
#define GPIO_PDDR_UARTH(x) GPIO_PODR_UARTH(x)
#define GPIO_PDDR_UARTH_MASK GPIO_PODR_UARTH_MASK
#define GPIO_PDDR_QSPI(x) GPIO_PODR_QSPI(x)
#define GPIO_PDDR_QSPI_MASK GPIO_PODR_QSPI_MASK
#define GPIO_PDDR_ETPU(x) GPIO_PODR_ETPU(x)
#define GPIO_PDDR_ETPU_MASK GPIO_PODR_ETPU_MASK
/* Bit definitions and macros for GPIO_PPDSDR */
#define GPIO_PPDSDR_ADDR(x) GPIO_PODR_ADDR(x)
#define GPIO_PPDSDR_ADDR_MASK GPIO_PODR_ADDR_MASK
#define GPIO_PPDSDR_BS(x) GPIO_PODR_BS(x)
#define GPIO_PPDSDR_BS_MASK GPIO_PODR_BS_MASK
#define GPIO_PPDSDR_CS(x) GPIO_PODR_CS(x)
#define GPIO_PPDSDR_CS_MASK GPIO_PODR_CS_MASK
#define GPIO_PPDSDR_SDRAM(X) GPIO_PODR_SDRAM(X)
#define GPIO_PPDSDR_SDRAM_MASK GPIO_PODR_SDRAM_MASK
#define GPIO_PPDSDR_FECI2C(x) GPIO_PPDSDR_BS(x)
#define GPIO_PPDSDR_FECI2C_MASK GPIO_PPDSDR_BS_MASK
#define GPIO_PPDSDR_UARTH(x) GPIO_PODR_UARTH(x)
#define GPIO_PPDSDR_UARTH_MASK GPIO_PODR_UARTH_MASK
#define GPIO_PPDSDR_QSPI(x) GPIO_PODR_QSPI(x)
#define GPIO_PPDSDR_QSPI_MASK GPIO_PODR_QSPI_MASK
#define GPIO_PPDSDR_ETPU(x) GPIO_PODR_ETPU(x)
#define GPIO_PPDSDR_ETPU_MASK GPIO_PODR_ETPU_MASK
/* Bit definitions and macros for GPIO_PCLRR */
#define GPIO_PCLRR_ADDR(x) GPIO_PODR_ADDR(x)
#define GPIO_PCLRR_ADDR_MASK GPIO_PODR_ADDR_MASK
#define GPIO_PCLRR_BS(x) GPIO_PODR_BS(x)
#define GPIO_PCLRR_BS_MASK GPIO_PODR_BS_MASK
#define GPIO_PCLRR_CS(x) GPIO_PODR_CS(x)
#define GPIO_PCLRR_CS_MASK GPIO_PODR_CS_MASK
#define GPIO_PCLRR_SDRAM(X) GPIO_PODR_SDRAM(X)
#define GPIO_PCLRR_SDRAM_MASK GPIO_PODR_SDRAM_MASK
#define GPIO_PCLRR_FECI2C(x) GPIO_PCLRR_BS(x)
#define GPIO_PCLRR_FECI2C_MASK GPIO_PCLRR_BS_MASK
#define GPIO_PCLRR_UARTH(x) GPIO_PODR_UARTH(x)
#define GPIO_PCLRR_UARTH_MASK GPIO_PODR_UARTH_MASK
#define GPIO_PCLRR_QSPI(x) GPIO_PODR_QSPI(x)
#define GPIO_PCLRR_QSPI_MASK GPIO_PODR_QSPI_MASK
#define GPIO_PCLRR_ETPU(x) GPIO_PODR_ETPU(x)
#define GPIO_PCLRR_ETPU_MASK GPIO_PODR_ETPU_MASK
/* Bit definitions and macros for GPIO_PAR */
#define GPIO_PAR_AD_ADDR23 (0x80)
#define GPIO_PAR_AD_ADDR22 (0x40)
#define GPIO_PAR_AD_ADDR21 (0x20)
#define GPIO_PAR_AD_DATAL (0x01)
#define GPIO_PAR_BUSCTL_OE (0x4000)
#define GPIO_PAR_BUSCTL_TA (0x1000)
#define GPIO_PAR_BUSCTL_TEA(x) (((x)&0x03)<<10)
#define GPIO_PAR_BUSCTL_TEA_MASK (0x0C00)
#define GPIO_PAR_BUSCTL_TEA_GPIO (0x0400)
#define GPIO_PAR_BUSCTL_TEA_DREQ1 (0x0800)
#define GPIO_PAR_BUSCTL_TEA_EXTBUS (0x0C00)
#define GPIO_PAR_BUSCTL_RWB (0x0100)
#define GPIO_PAR_BUSCTL_TSIZ1 (0x0040)
#define GPIO_PAR_BUSCTL_TSIZ0 (0x0010)
#define GPIO_PAR_BUSCTL_TS(x) (((x)&0x03)<<2)
#define GPIO_PAR_BUSCTL_TS_MASK (0x0C)
#define GPIO_PAR_BUSCTL_TS_GPIO (0x04)
#define GPIO_PAR_BUSCTL_TS_DACK2 (0x08)
#define GPIO_PAR_BUSCTL_TS_EXTBUS (0x0C)
#define GPIO_PAR_BUSCTL_TIP(x) ((x)&0x03)
#define GPIO_PAR_BUSCTL_TIP_MASK (0x03)
#define GPIO_PAR_BUSCTL_TIP_GPIO (0x01)
#define GPIO_PAR_BUSCTL_TIP_DREQ0 (0x02)
#define GPIO_PAR_BUSCTL_TIP_EXTBUS (0x03)
#define GPIO_PAR_BS(x) ((x)&0x0F)
#define GPIO_PAR_BS_MASK (0x0F)
#define GPIO_PAR_CS(x) (((x)&0x7F)<<1)
#define GPIO_PAR_CS_MASK (0xFE)
#define GPIO_PAR_CS_CS7 (0x80)
#define GPIO_PAR_CS_CS6 (0x40)
#define GPIO_PAR_CS_CS5 (0x20)
#define GPIO_PAR_CS_CS4 (0x10)
#define GPIO_PAR_CS_CS3 (0x08)
#define GPIO_PAR_CS_CS2 (0x04)
#define GPIO_PAR_CS_CS1 (0x02)
#define GPIO_PAR_CS_SD3 GPIO_PAR_CS_CS3
#define GPIO_PAR_CS_SD2 GPIO_PAR_CS_CS2
#define GPIO_PAR_SDRAM_CSSDCS(x) (((x)&0x03)<<6)
#define GPIO_PAR_SDRAM_CSSDCS_MASK (0xC0)
#define GPIO_PAR_SDRAM_SDWE (0x20)
#define GPIO_PAR_SDRAM_SCAS (0x10)
#define GPIO_PAR_SDRAM_SRAS (0x08)
#define GPIO_PAR_SDRAM_SCKE (0x04)
#define GPIO_PAR_SDRAM_SDCS(x) ((x)&0x03)
#define GPIO_PAR_SDRAM_SDCS_MASK (0x03)
#define GPIO_PAR_FECI2C_EMDC(x) (((x)&0x03)<<6)
#define GPIO_PAR_FECI2C_EMDC_MASK (0xC0)
#define GPIO_PAR_FECI2C_EMDC_U2TXD (0x40)
#define GPIO_PAR_FECI2C_EMDC_I2CSCL (0x80)
#define GPIO_PAR_FECI2C_EMDC_FECEMDC (0xC0)
#define GPIO_PAR_FECI2C_EMDIO(x) (((x)&0x03)<<4)
#define GPIO_PAR_FECI2C_EMDIO_MASK (0x30)
#define GPIO_PAR_FECI2C_EMDIO_U2RXD (0x10)
#define GPIO_PAR_FECI2C_EMDIO_I2CSDA (0x20)
#define GPIO_PAR_FECI2C_EMDIO_FECEMDIO (0x30)
#define GPIO_PAR_FECI2C_SCL(x) (((x)&0x03)<<2)
#define GPIO_PAR_FECI2C_SCL_MASK (0x0C)
#define GPIO_PAR_FECI2C_SCL_CAN0RX (0x08)
#define GPIO_PAR_FECI2C_SCL_I2CSCL (0x0C)
#define GPIO_PAR_FECI2C_SDA(x) ((x)&0x03)
#define GPIO_PAR_FECI2C_SDA_MASK (0x03)
#define GPIO_PAR_FECI2C_SDA_CAN0TX (0x02)
#define GPIO_PAR_FECI2C_SDA_I2CSDA (0x03)
#define GPIO_PAR_UART_DREQ2 (0x8000)
#define GPIO_PAR_UART_CAN1EN (0x4000)
#define GPIO_PAR_UART_U2RXD (0x2000)
#define GPIO_PAR_UART_U2TXD (0x1000)
#define GPIO_PAR_UART_U1RXD(x) (((x)&0x03)<<10)
#define GPIO_PAR_UART_U1RXD_MASK (0x0C00)
#define GPIO_PAR_UART_U1RXD_CAN0RX (0x0800)
#define GPIO_PAR_UART_U1RXD_U1RXD (0x0C00)
#define GPIO_PAR_UART_U1TXD(x) (((x)&0x03)<<8)
#define GPIO_PAR_UART_U1TXD_MASK (0x0300)
#define GPIO_PAR_UART_U1TXD_CAN0TX (0x0200)
#define GPIO_PAR_UART_U1TXD_U1TXD (0x0300)
#define GPIO_PAR_UART_U1CTS(x) (((x)&0x03)<<6)
#define GPIO_PAR_UART_U1CTS_MASK (0x00C0)
#define GPIO_PAR_UART_U1CTS_U2CTS (0x0080)
#define GPIO_PAR_UART_U1CTS_U1CTS (0x00C0)
#define GPIO_PAR_UART_U1RTS(x) (((x)&0x03)<<4)
#define GPIO_PAR_UART_U1RTS_MASK (0x0030)
#define GPIO_PAR_UART_U1RTS_U2RTS (0x0020)
#define GPIO_PAR_UART_U1RTS_U1RTS (0x0030)
#define GPIO_PAR_UART_U0RXD (0x0008)
#define GPIO_PAR_UART_U0TXD (0x0004)
#define GPIO_PAR_UART_U0CTS (0x0002)
#define GPIO_PAR_UART_U0RTS (0x0001)
#define GPIO_PAR_QSPI_CS1(x) (((x)&0x03)<<6)
#define GPIO_PAR_QSPI_CS1_MASK (0xC0)
#define GPIO_PAR_QSPI_CS1_SDRAMSCKE (0x80)
#define GPIO_PAR_QSPI_CS1_QSPICS1 (0xC0)
#define GPIO_PAR_QSPI_CS0 (0x20)
#define GPIO_PAR_QSPI_DIN(x) (((x)&0x03)<<3)
#define GPIO_PAR_QSPI_DIN_MASK (0x18)
#define GPIO_PAR_QSPI_DIN_I2CSDA (0x10)
#define GPIO_PAR_QSPI_DIN_QSPIDIN (0x18)
#define GPIO_PAR_QSPI_DOUT (0x04)
#define GPIO_PAR_QSPI_SCK(x) ((x)&0x03)
#define GPIO_PAR_QSPI_SCK_MASK (0x03)
#define GPIO_PAR_QSPI_SCK_I2CSCL (0x02)
#define GPIO_PAR_QSPI_SCK_QSPISCK (0x03)
#define GPIO_PAR_DT3IN(x) (((x)&0x03)<<14)
#define GPIO_PAR_DT3IN_MASK (0xC000)
#define GPIO_PAR_DT3IN_QSPICS2 (0x4000)
#define GPIO_PAR_DT3IN_U2CTS (0x8000)
#define GPIO_PAR_DT3IN_DT3IN (0xC000)
#define GPIO_PAR_DT2IN(x) (((x)&0x03)<<12)
#define GPIO_PAR_DT2IN_MASK (0x3000)
#define GPIO_PAR_DT2IN_DT2OUT (0x1000)
#define GPIO_PAR_DT2IN_DREQ2 (0x2000)
#define GPIO_PAR_DT2IN_DT2IN (0x3000)
#define GPIO_PAR_DT1IN(x) (((x)&0x03)<<10)
#define GPIO_PAR_DT1IN_MASK (0x0C00)
#define GPIO_PAR_DT1IN_DT1OUT (0x0400)
#define GPIO_PAR_DT1IN_DREQ1 (0x0800)
#define GPIO_PAR_DT1IN_DT1IN (0x0C00)
#define GPIO_PAR_DT0IN(x) (((x)&0x03)<<8)
#define GPIO_PAR_DT0IN_MASK (0x0300)
#define GPIO_PAR_DT0IN_DREQ0 (0x0200)
#define GPIO_PAR_DT0IN_DT0IN (0x0300)
#define GPIO_PAR_DT3OUT(x) (((x)&0x03)<<6)
#define GPIO_PAR_DT3OUT_MASK (0x00C0)
#define GPIO_PAR_DT3OUT_QSPICS3 (0x0040)
#define GPIO_PAR_DT3OUT_U2RTS (0x0080)
#define GPIO_PAR_DT3OUT_DT3OUT (0x00C0)
#define GPIO_PAR_DT2OUT(x) (((x)&0x03)<<4)
#define GPIO_PAR_DT2OUT_MASK (0x0030)
#define GPIO_PAR_DT2OUT_DACK2 (0x0020)
#define GPIO_PAR_DT2OUT_DT2OUT (0x0030)
#define GPIO_PAR_DT1OUT(x) (((x)&0x03)<<2)
#define GPIO_PAR_DT1OUT_MASK (0x000C)
#define GPIO_PAR_DT1OUT_DACK1 (0x0008)
#define GPIO_PAR_DT1OUT_DT1OUT (0x000C)
#define GPIO_PAR_DT0OUT(x) ((x)&0x03)
#define GPIO_PAR_DT0OUT_MASK (0x0003)
#define GPIO_PAR_DT0OUT_DACK0 (0x0002)
#define GPIO_PAR_DT0OUT_DT0OUT (0x0003)
#define GPIO_PAR_ETPU_TCRCLK (0x04)
#define GPIO_PAR_ETPU_UTPU_ODIS (0x02)
#define GPIO_PAR_ETPU_LTPU_ODIS (0x01)
/* Bit definitions and macros for GPIO_DSCR */
#define GPIO_DSCR_EIM_EIM1 (0x10)
#define GPIO_DSCR_EIM_EIM0 (0x01)
#define GPIO_DSCR_ETPU_ETPU31_24 (0x40)
#define GPIO_DSCR_ETPU_ETPU23_16 (0x10)
#define GPIO_DSCR_ETPU_ETPU15_8 (0x04)
#define GPIO_DSCR_ETPU_ETPU7_0 (0x01)
#define GPIO_DSCR_FECI2C_FEC (0x10)
#define GPIO_DSCR_FECI2C_I2C (0x01)
#define GPIO_DSCR_UART_IRQ (0x40)
#define GPIO_DSCR_UART_UART2 (0x10)
#define GPIO_DSCR_UART_UART1 (0x04)
#define GPIO_DSCR_UART_UART0 (0x01)
#define GPIO_DSCR_QSPI_QSPI (0x01)
#define GPIO_DSCR_TIMER (0x01)
/*********************************************************************
* Chip Configuration Module (CCM)
*********************************************************************/
/* Bit definitions and macros for CCM_RCR */
#define CCM_RCR_SOFTRST (0x80)
#define CCM_RCR_FRCRSTOUT (0x40)
/* Bit definitions and macros for CCM_RSR */
#define CCM_RSR_SOFT (0x20)
#define CCM_RSR_WDR (0x10)
#define CCM_RSR_POR (0x08)
#define CCM_RSR_EXT (0x04)
#define CCM_RSR_LOC (0x02)
#define CCM_RSR_LOL (0x01)
/* Bit definitions and macros for CCM_CCR */
#define CCM_CCR_LOAD (0x8000)
#define CCM_CCR_SZEN (0x0040)
#define CCM_CCR_PSTEN (0x0020)
#define CCM_CCR_BME (0x0008)
#define CCM_CCR_BMT(x) ((x)&0x07)
#define CCM_CCR_BMT_MASK (0x0007)
#define CCM_CCR_BMT_64K (0x0000)
#define CCM_CCR_BMT_32K (0x0001)
#define CCM_CCR_BMT_16K (0x0002)
#define CCM_CCR_BMT_8K (0x0003)
#define CCM_CCR_BMT_4K (0x0004)
#define CCM_CCR_BMT_2K (0x0005)
#define CCM_CCR_BMT_1K (0x0006)
#define CCM_CCR_BMT_512 (0x0007)
/* Bit definitions and macros for CCM_RCON */
#define CCM_RCON_RCSC(x) (((x)&0x0003)<<8)
#define CCM_RCON_RLOAD (0x0020)
#define CCM_RCON_BOOTPS(x) (((x)&0x0003)<<3)
#define CCM_RCON_BOOTPS_MASK (0x0018)
#define CCM_RCON_BOOTPS_32 (0x0018)
#define CCM_RCON_BOOTPS_16 (0x0008)
#define CCM_RCON_BOOTPS_8 (0x0010)
#define CCM_RCON_MODE (0x0001)
/* Bit definitions and macros for CCM_CIR */
#define CCM_CIR_PIN(x) (((x)&0x03FF)<<6)
#define CCM_CIR_PRN(x) ((x)&0x003F)
/*********************************************************************
* PLL Clock Module
*********************************************************************/
/* Bit definitions and macros for PLL_SYNCR */
#define PLL_SYNCR_MFD(x) (((x)&0x07)<<24)
#define PLL_SYNCR_MFD_MASK (0x07000000)
#define PLL_SYNCR_RFC(x) (((x)&0x07)<<19)
#define PLL_SYNCR_RFC_MASK (0x00380000)
#define PLL_SYNCR_LOCEN (0x00040000)
#define PLL_SYNCR_LOLRE (0x00020000)
#define PLL_SYNCR_LOCRE (0x00010000)
#define PLL_SYNCR_DISCLK (0x00008000)
#define PLL_SYNCR_LOLIRQ (0x00004000)
#define PLL_SYNCR_LOCIRQ (0x00002000)
#define PLL_SYNCR_RATE (0x00001000)
#define PLL_SYNCR_DEPTH(x) (((x)&0x03)<<10)
#define PLL_SYNCR_EXP(x) ((x)&0x03FF)
/* Bit definitions and macros for PLL_SYNSR */
#define PLL_SYNSR_LOLF (0x00000200)
#define PLL_SYNSR_LOC (0x00000100)
#define PLL_SYNSR_MODE (0x00000080)
#define PLL_SYNSR_PLLSEL (0x00000040)
#define PLL_SYNSR_PLLREF (0x00000020)
#define PLL_SYNSR_LOCKS (0x00000010)
#define PLL_SYNSR_LOCK (0x00000008)
#define PLL_SYNSR_LOCF (0x00000004)
#define PLL_SYNSR_CALDONE (0x00000002)
#define PLL_SYNSR_CALPASS (0x00000001)
/*********************************************************************
* Edge Port
*********************************************************************/
#define EPORT_EPPAR_EPPA7(x) (((x)&0x03)<<14)
#define EPORT_EPPAR_EPPA6(x) (((x)&0x03)<<12)
#define EPORT_EPPAR_EPPA5(x) (((x)&0x03)<<10)
#define EPORT_EPPAR_EPPA4(x) (((x)&0x03)<<8)
#define EPORT_EPPAR_EPPA3(x) (((x)&0x03)<<6)
#define EPORT_EPPAR_EPPA2(x) (((x)&0x03)<<4)
#define EPORT_EPPAR_EPPA1(x) (((x)&0x03)<<2)
#define EPORT_EPDDR_EPDD7(x) EPORT_EPPAR_EPPA7(x)
#define EPORT_EPDDR_EPDD6(x) EPORT_EPPAR_EPPA6(x)
#define EPORT_EPDDR_EPDD5(x) EPORT_EPPAR_EPPA5(x)
#define EPORT_EPDDR_EPDD4(x) EPORT_EPPAR_EPPA4(x)
#define EPORT_EPDDR_EPDD3(x) EPORT_EPPAR_EPPA3(x)
#define EPORT_EPDDR_EPDD2(x) EPORT_EPPAR_EPPA2(x)
#define EPORT_EPDDR_EPDD1(x) EPORT_EPPAR_EPPA1(x)
#define EPORT_EPIER_EPIE7 (0x80)
#define EPORT_EPIER_EPIE6 (0x40)
#define EPORT_EPIER_EPIE5 (0x20)
#define EPORT_EPIER_EPIE4 (0x10)
#define EPORT_EPIER_EPIE3 (0x08)
#define EPORT_EPIER_EPIE2 (0x04)
#define EPORT_EPIER_EPIE1 (0x02)
#define EPORT_EPDR_EPDR7 EPORT_EPIER_EPIE7
#define EPORT_EPDR_EPDR6 EPORT_EPIER_EPIE6
#define EPORT_EPDR_EPDR5 EPORT_EPIER_EPIE5
#define EPORT_EPDR_EPDR4 EPORT_EPIER_EPIE4
#define EPORT_EPDR_EPDR3 EPORT_EPIER_EPIE3
#define EPORT_EPDR_EPDR2 EPORT_EPIER_EPIE2
#define EPORT_EPDR_EPDR1 EPORT_EPIER_EPIE1
#define EPORT_EPPDR_EPPDR7 EPORT_EPIER_EPIE7
#define EPORT_EPPDR_EPPDR6 EPORT_EPIER_EPIE6
#define EPORT_EPPDR_EPPDR5 EPORT_EPIER_EPIE5
#define EPORT_EPPDR_EPPDR4 EPORT_EPIER_EPIE4
#define EPORT_EPPDR_EPPDR3 EPORT_EPIER_EPIE3
#define EPORT_EPPDR_EPPDR2 EPORT_EPIER_EPIE2
#define EPORT_EPPDR_EPPDR1 EPORT_EPIER_EPIE1
/*********************************************************************
* Watchdog Timer Modules (WTM)
*********************************************************************/
/* Bit definitions and macros for WTM_WCR */
#define WTM_WCR_WAIT (0x0008)
#define WTM_WCR_DOZE (0x0004)
#define WTM_WCR_HALTED (0x0002)
#define WTM_WCR_EN (0x0001)
/*********************************************************************
* FlexCAN Module (CAN)
*********************************************************************/
/* Bit definitions and macros for CAN_CANMCR */
#define CANMCR_MDIS (0x80000000)
#define CANMCR_FRZ (0x40000000)
#define CANMCR_HALT (0x10000000)
#define CANMCR_NORDY (0x08000000)
#define CANMCR_SOFTRST (0x02000000)
#define CANMCR_FRZACK (0x01000000)
#define CANMCR_SUPV (0x00800000)
#define CANMCR_LPMACK (0x00100000)
#define CANMCR_MAXMB(x) (((x)&0x0F))
/* Bit definitions and macros for CAN_CANCTRL */
#define CANCTRL_PRESDIV(x) (((x)&0xFF)<<24)
#define CANCTRL_RJW(x) (((x)&0x03)<<22)
#define CANCTRL_PSEG1(x) (((x)&0x07)<<19)
#define CANCTRL_PSEG2(x) (((x)&0x07)<<16)
#define CANCTRL_BOFFMSK (0x00008000)
#define CANCTRL_ERRMSK (0x00004000)
#define CANCTRL_CLKSRC (0x00002000)
#define CANCTRL_LPB (0x00001000)
#define CANCTRL_SMP (0x00000080)
#define CANCTRL_BOFFREC (0x00000040)
#define CANCTRL_TSYNC (0x00000020)
#define CANCTRL_LBUF (0x00000010)
#define CANCTRL_LOM (0x00000008)
#define CANCTRL_PROPSEG(x) (((x)&0x07))
/* Bit definitions and macros for CAN_TIMER */
#define TIMER_TIMER(x) ((x)&0xFFFF)
/* Bit definitions and macros for CAN_RXGMASK */
#define RXGMASK_MI(x) ((x)&0x1FFFFFFF)
/* Bit definitions and macros for CAN_ERRCNT */
#define ERRCNT_TXECTR(x) (((x)&0xFF))
#define ERRCNT_RXECTR(x) (((x)&0xFF)<<8)
/* Bit definitions and macros for CAN_ERRSTAT */
#define ERRSTAT_BITERR1 (0x00008000)
#define ERRSTAT_BITERR0 (0x00004000)
#define ERRSTAT_ACKERR (0x00002000)
#define ERRSTAT_CRCERR (0x00001000)
#define ERRSTAT_FRMERR (0x00000800)
#define ERRSTAT_STFERR (0x00000400)
#define ERRSTAT_TXWRN (0x00000200)
#define ERRSTAT_RXWRN (0x00000100)
#define ERRSTAT_IDLE (0x00000080)
#define ERRSTAT_TXRX (0x00000040)
#define ERRSTAT_FLT_BUSOFF (0x00000020)
#define ERRSTAT_FLT_PASSIVE (0x00000010)
#define ERRSTAT_FLT_ACTIVE (0x00000000)
#define ERRSTAT_BOFFINT (0x00000004)
#define ERRSTAT_ERRINT (0x00000002)
/* Bit definitions and macros for CAN_IMASK */
#define IMASK_BUF15M (0x00008000)
#define IMASK_BUF14M (0x00004000)
#define IMASK_BUF13M (0x00002000)
#define IMASK_BUF12M (0x00001000)
#define IMASK_BUF11M (0x00000800)
#define IMASK_BUF10M (0x00000400)
#define IMASK_BUF9M (0x00000200)
#define IMASK_BUF8M (0x00000100)
#define IMASK_BUF7M (0x00000080)
#define IMASK_BUF6M (0x00000040)
#define IMASK_BUF5M (0x00000020)
#define IMASK_BUF4M (0x00000010)
#define IMASK_BUF3M (0x00000008)
#define IMASK_BUF2M (0x00000004)
#define IMASK_BUF1M (0x00000002)
#define IMASK_BUF0M (0x00000001)
/* Bit definitions and macros for CAN_IFLAG */
#define IFLAG_BUF15I (0x00008000)
#define IFLAG_BUF14I (0x00004000)
#define IFLAG_BUF13I (0x00002000)
#define IFLAG_BUF12I (0x00001000)
#define IFLAG_BUF11I (0x00000800)
#define IFLAG_BUF10I (0x00000400)
#define IFLAG_BUF9I (0x00000200)
#define IFLAG_BUF8I (0x00000100)
#define IFLAG_BUF7I (0x00000080)
#define IFLAG_BUF6I (0x00000040)
#define IFLAG_BUF5I (0x00000020)
#define IFLAG_BUF4I (0x00000010)
#define IFLAG_BUF3I (0x00000008)
#define IFLAG_BUF2I (0x00000004)
#define IFLAG_BUF1I (0x00000002)
#define IFLAG_BUF0I (0x00000001)
#endif /* mcf5235_h */

183
include/asm-m68k/m5249.h
View File

@@ -24,7 +24,6 @@
* MA 02111-1307 USA
*/
#ifndef mcf5249_h
#define mcf5249_h
/****************************************************************************/
@@ -32,22 +31,21 @@
/*
* useful definitions for reading/writing MBAR offset memory
*/
#define mbar_readLong(x) *((volatile unsigned long *) (CFG_MBAR + x))
#define mbar_writeLong(x,y) *((volatile unsigned long *) (CFG_MBAR + x)) = y
#define mbar_writeShort(x,y) *((volatile unsigned short *) (CFG_MBAR + x)) = y
#define mbar_writeByte(x,y) *((volatile unsigned char *) (CFG_MBAR + x)) = y
#define mbar2_readLong(x) *((volatile unsigned long *) (CFG_MBAR2 + x))
#define mbar2_writeLong(x,y) *((volatile unsigned long *) (CFG_MBAR2 + x)) = y
#define mbar2_writeShort(x,y) *((volatile unsigned short *) (CFG_MBAR2 + x)) = y
#define mbar2_writeByte(x,y) *((volatile unsigned char *) (CFG_MBAR2 + x)) = y
#define mbar_readLong(x) *((volatile unsigned long *) (CFG_MBAR + x))
#define mbar_writeLong(x,y) *((volatile unsigned long *) (CFG_MBAR + x)) = y
#define mbar_writeShort(x,y) *((volatile unsigned short *) (CFG_MBAR + x)) = y
#define mbar_writeByte(x,y) *((volatile unsigned char *) (CFG_MBAR + x)) = y
#define mbar2_readLong(x) *((volatile unsigned long *) (CFG_MBAR2 + x))
#define mbar2_writeLong(x,y) *((volatile unsigned long *) (CFG_MBAR2 + x)) = y
#define mbar2_writeShort(x,y) *((volatile unsigned short *) (CFG_MBAR2 + x)) = y
#define mbar2_writeByte(x,y) *((volatile unsigned char *) (CFG_MBAR2 + x)) = y
/*
* Size of internal RAM
*/
#define INT_RAM_SIZE 32768 /* RAMBAR0 - 32k */
#define INT_RAM_SIZE2 65536 /* RAMBAR1 - 64k */
#define INT_RAM_SIZE 32768 /* RAMBAR0 - 32k */
#define INT_RAM_SIZE2 65536 /* RAMBAR1 - 64k */
/*
* Define the 5249 SIM register set addresses.
@@ -56,51 +54,47 @@
/*****************
***** MBAR1 *****
*****************/
#define MCFSIM_RSR 0x00 /* Reset Status reg (r/w) */
#define MCFSIM_SYPCR 0x01 /* System Protection reg (r/w)*/
#define MCFSIM_SWIVR 0x02 /* SW Watchdog intr reg (r/w) */
#define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */
#define MCFSIM_MPARK 0x0c /* Bus master park register (r/w) */
#define MCFSIM_RSR 0x00 /* Reset Status reg (r/w) */
#define MCFSIM_SYPCR 0x01 /* System Protection reg (r/w) */
#define MCFSIM_SWIVR 0x02 /* SW Watchdog intr reg (r/w) */
#define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */
#define MCFSIM_MPARK 0x0c /* Bus master park register (r/w) */
#define MCFSIM_SIMR 0x00 /* SIM Config reg (r/w) */
#define MCFSIM_ICR0 0x4c /* Intr Ctrl reg 0 (r/w) */
#define MCFSIM_ICR1 0x4d /* Intr Ctrl reg 1 (r/w) */
#define MCFSIM_ICR2 0x4e /* Intr Ctrl reg 2 (r/w) */
#define MCFSIM_ICR3 0x4f /* Intr Ctrl reg 3 (r/w) */
#define MCFSIM_ICR4 0x50 /* Intr Ctrl reg 4 (r/w) */
#define MCFSIM_ICR5 0x51 /* Intr Ctrl reg 5 (r/w) */
#define MCFSIM_ICR6 0x52 /* Intr Ctrl reg 6 (r/w) */
#define MCFSIM_ICR7 0x53 /* Intr Ctrl reg 7 (r/w) */
#define MCFSIM_ICR8 0x54 /* Intr Ctrl reg 8 (r/w) */
#define MCFSIM_ICR9 0x55 /* Intr Ctrl reg 9 (r/w) */
#define MCFSIM_ICR10 0x56 /* Intr Ctrl reg 10 (r/w) */
#define MCFSIM_ICR11 0x57 /* Intr Ctrl reg 11 (r/w) */
#define MCFSIM_SIMR 0x00 /* SIM Config reg (r/w) */
#define MCFSIM_ICR0 0x4c /* Intr Ctrl reg 0 (r/w) */
#define MCFSIM_ICR1 0x4d /* Intr Ctrl reg 1 (r/w) */
#define MCFSIM_ICR2 0x4e /* Intr Ctrl reg 2 (r/w) */
#define MCFSIM_ICR3 0x4f /* Intr Ctrl reg 3 (r/w) */
#define MCFSIM_ICR4 0x50 /* Intr Ctrl reg 4 (r/w) */
#define MCFSIM_ICR5 0x51 /* Intr Ctrl reg 5 (r/w) */
#define MCFSIM_ICR6 0x52 /* Intr Ctrl reg 6 (r/w) */
#define MCFSIM_ICR7 0x53 /* Intr Ctrl reg 7 (r/w) */
#define MCFSIM_ICR8 0x54 /* Intr Ctrl reg 8 (r/w) */
#define MCFSIM_ICR9 0x55 /* Intr Ctrl reg 9 (r/w) */
#define MCFSIM_ICR10 0x56 /* Intr Ctrl reg 10 (r/w) */
#define MCFSIM_ICR11 0x57 /* Intr Ctrl reg 11 (r/w) */
#define MCFSIM_IPR 0x40 /* Interrupt Pend reg (r/w) */
#define MCFSIM_IMR 0x44 /* Interrupt Mask reg (r/w) */
#define MCFSIM_IPR 0x40 /* Interrupt Pend reg (r/w) */
#define MCFSIM_IMR 0x44 /* Interrupt Mask reg (r/w) */
#define MCFSIM_CSAR0 0x80 /* CS 0 Address 0 reg (r/w) */
#define MCFSIM_CSMR0 0x84 /* CS 0 Mask 0 reg (r/w) */
#define MCFSIM_CSCR0 0x8a /* CS 0 Control reg (r/w) */
#define MCFSIM_CSAR1 0x8c /* CS 1 Address reg (r/w) */
#define MCFSIM_CSMR1 0x90 /* CS 1 Mask reg (r/w) */
#define MCFSIM_CSCR1 0x96 /* CS 1 Control reg (r/w) */
#define MCFSIM_CSAR2 0x98 /* CS 2 Address reg (r/w) */
#define MCFSIM_CSMR2 0x9c /* CS 2 Mask reg (r/w) */
#define MCFSIM_CSCR2 0xa2 /* CS 2 Control reg (r/w) */
#define MCFSIM_CSAR3 0xa4 /* CS 3 Address reg (r/w) */
#define MCFSIM_CSMR3 0xa8 /* CS 3 Mask reg (r/w) */
#define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */
#define MCFSIM_CSAR0 0x80 /* CS 0 Address 0 reg (r/w) */
#define MCFSIM_CSMR0 0x84 /* CS 0 Mask 0 reg (r/w) */
#define MCFSIM_CSCR0 0x8a /* CS 0 Control reg (r/w) */
#define MCFSIM_CSAR1 0x8c /* CS 1 Address reg (r/w) */
#define MCFSIM_CSMR1 0x90 /* CS 1 Mask reg (r/w) */
#define MCFSIM_CSCR1 0x96 /* CS 1 Control reg (r/w) */
#define MCFSIM_CSAR2 0x98 /* CS 2 Address reg (r/w) */
#define MCFSIM_CSMR2 0x9c /* CS 2 Mask reg (r/w) */
#define MCFSIM_CSCR2 0xa2 /* CS 2 Control reg (r/w) */
#define MCFSIM_CSAR3 0xa4 /* CS 3 Address reg (r/w) */
#define MCFSIM_CSMR3 0xa8 /* CS 3 Mask reg (r/w) */
#define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */
#define MCFSIM_DCR 0x100 /* DRAM Control reg (r/w) */
#define MCFSIM_DACR0 0x108 /* DRAM 0 Addr and Ctrl (r/w) */
#define MCFSIM_DMR0 0x10c /* DRAM 0 Mask reg (r/w) */
#define MCFSIM_DACR1 0x110 /* DRAM 1 Addr and Ctrl (r/w) */
#define MCFSIM_DMR1 0x114 /* DRAM 1 Mask reg (r/w) */
/** UART Bases **/
#define MCFUART_BASE1 0x1c0 /* Base address of UART1 */
#define MCFUART_BASE2 0x200 /* Base address of UART2 */
#define MCFSIM_DCR 0x100 /* DRAM Control reg (r/w) */
#define MCFSIM_DACR0 0x108 /* DRAM 0 Addr and Ctrl (r/w) */
#define MCFSIM_DMR0 0x10c /* DRAM 0 Mask reg (r/w) */
#define MCFSIM_DACR1 0x110 /* DRAM 1 Addr and Ctrl (r/w) */
#define MCFSIM_DMR1 0x114 /* DRAM 1 Mask reg (r/w) */
/*****************
***** MBAR2 *****
@@ -109,39 +103,39 @@
/* GPIO Addresses
* Note: These are offset from MBAR2!
*/
#define MCFSIM_GPIO_READ 0x00 /* Read-Only access to gpio 0-31 (MBAR2) (r) */
#define MCFSIM_GPIO_OUT 0x04 /* Output register for gpio 0-31 (MBAR2) (r/w)*/
#define MCFSIM_GPIO_EN 0x08 /* gpio 0-31 enable (r/w)*/
#define MCFSIM_GPIO_FUNC 0x0c /* gpio 0-31 function select (r/w) */
#define MCFSIM_GPIO1_READ 0xb0 /* Read-Only access to gpio 32-63 (MBAR2) (r) */
#define MCFSIM_GPIO1_OUT 0xb4 /* Output register for gpio 32-63 (MBAR2) (r/w) */
#define MCFSIM_GPIO1_EN 0xb8 /* gpio 32-63 enable (r/w) */
#define MCFSIM_GPIO1_FUNC 0xbc /* gpio 32-63 function select (r/w) */
#define MCFSIM_GPIO_READ 0x00 /* Read-Only access to gpio 0-31 (MBAR2) (r) */
#define MCFSIM_GPIO_OUT 0x04 /* Output register for gpio 0-31 (MBAR2) (r/w) */
#define MCFSIM_GPIO_EN 0x08 /* gpio 0-31 enable (r/w) */
#define MCFSIM_GPIO_FUNC 0x0c /* gpio 0-31 function select (r/w) */
#define MCFSIM_GPIO1_READ 0xb0 /* Read-Only access to gpio 32-63 (MBAR2) (r) */
#define MCFSIM_GPIO1_OUT 0xb4 /* Output register for gpio 32-63 (MBAR2) (r/w) */
#define MCFSIM_GPIO1_EN 0xb8 /* gpio 32-63 enable (r/w) */
#define MCFSIM_GPIO1_FUNC 0xbc /* gpio 32-63 function select (r/w) */
#define MCFSIM_GPIO_INT_STAT 0xc0 /* Secondary Interrupt status (r) */
#define MCFSIM_GPIO_INT_CLEAR 0xc0 /* Secondary Interrupt status (w) */
#define MCFSIM_GPIO_INT_EN 0xc4 /* Secondary Interrupt status (r/w) */
#define MCFSIM_GPIO_INT_STAT 0xc0 /* Secondary Interrupt status (r) */
#define MCFSIM_GPIO_INT_CLEAR 0xc0 /* Secondary Interrupt status (w) */
#define MCFSIM_GPIO_INT_EN 0xc4 /* Secondary Interrupt status (r/w) */
#define MCFSIM_INT_STAT3 0xe0 /* 3rd Interrupt ctrl status (r) */
#define MCFSIM_INT_CLEAR3 0xe0 /* 3rd Interrupt ctrl clear (w) */
#define MCFSIM_INT_EN3 0xe4 /* 3rd Interrupt ctrl enable (r/w) */
#define MCFSIM_INT_STAT3 0xe0 /* 3rd Interrupt ctrl status (r) */
#define MCFSIM_INT_CLEAR3 0xe0 /* 3rd Interrupt ctrl clear (w) */
#define MCFSIM_INT_EN3 0xe4 /* 3rd Interrupt ctrl enable (r/w) */
#define MCFSIM_INTLEV1 0x140 /* Interrupts 0 - 7 (r/w) */
#define MCFSIM_INTLEV2 0x144 /* Interrupts 8 -15 (r/w) */
#define MCFSIM_INTLEV3 0x148 /* Interrupts 16-23 (r/w) */
#define MCFSIM_INTLEV4 0x14c /* Interrupts 24-31 (r/w) */
#define MCFSIM_INTLEV5 0x150 /* Interrupts 32-39 (r/w) */
#define MCFSIM_INTLEV6 0x154 /* Interrupts 40-47 (r/w) */
#define MCFSIM_INTLEV7 0x158 /* Interrupts 48-55 (r/w) */
#define MCFSIM_INTLEV8 0x15c /* Interrupts 56-63 (r/w) */
#define MCFSIM_INTLEV1 0x140 /* Interrupts 0 - 7 (r/w) */
#define MCFSIM_INTLEV2 0x144 /* Interrupts 8 -15 (r/w) */
#define MCFSIM_INTLEV3 0x148 /* Interrupts 16-23 (r/w) */
#define MCFSIM_INTLEV4 0x14c /* Interrupts 24-31 (r/w) */
#define MCFSIM_INTLEV5 0x150 /* Interrupts 32-39 (r/w) */
#define MCFSIM_INTLEV6 0x154 /* Interrupts 40-47 (r/w) */
#define MCFSIM_INTLEV7 0x158 /* Interrupts 48-55 (r/w) */
#define MCFSIM_INTLEV8 0x15c /* Interrupts 56-63 (r/w) */
#define MCFSIM_SPURVEC 0x167 /* Spurious Vector Register (r/w) */
#define MCFSIM_INTBASE 0x16b /* Software interrupt base address (r/w) */
#define MCFSIM_SPURVEC 0x167 /* Spurious Vector Register (r/w) */
#define MCFSIM_INTBASE 0x16b /* Software interrupt base address (r/w) */
#define MCFSIM_IDECONFIG1 0x18c /* IDE config register 1 (r/w) */
#define MCFSIM_IDECONFIG2 0x190 /* IDE config register 1 (r/w) */
#define MCFSIM_IDECONFIG1 0x18c /* IDE config register 1 (r/w) */
#define MCFSIM_IDECONFIG2 0x190 /* IDE config register 1 (r/w) */
#define MCFSIM_PLLCR 0x180 /* PLL Control register */
#define MCFSIM_PLLCR 0x180 /* PLL Control register */
/*
* Some symbol defines for the above...
@@ -158,21 +152,20 @@
/*
* Bit definitions for the ICR family of registers.
*/
#define MCFSIM_ICR_AUTOVEC 0x80 /* Auto-vectored intr */
#define MCFSIM_ICR_LEVEL0 0x00 /* Level 0 intr */
#define MCFSIM_ICR_LEVEL1 0x04 /* Level 1 intr */
#define MCFSIM_ICR_LEVEL2 0x08 /* Level 2 intr */
#define MCFSIM_ICR_LEVEL3 0x0c /* Level 3 intr */
#define MCFSIM_ICR_LEVEL4 0x10 /* Level 4 intr */
#define MCFSIM_ICR_LEVEL5 0x14 /* Level 5 intr */
#define MCFSIM_ICR_LEVEL6 0x18 /* Level 6 intr */
#define MCFSIM_ICR_LEVEL7 0x1c /* Level 7 intr */
#define MCFSIM_ICR_PRI0 0x00 /* Priority 0 intr */
#define MCFSIM_ICR_PRI1 0x01 /* Priority 1 intr */
#define MCFSIM_ICR_PRI2 0x02 /* Priority 2 intr */
#define MCFSIM_ICR_PRI3 0x03 /* Priority 3 intr */
#define MCFSIM_ICR_AUTOVEC 0x80 /* Auto-vectored intr */
#define MCFSIM_ICR_LEVEL0 0x00 /* Level 0 intr */
#define MCFSIM_ICR_LEVEL1 0x04 /* Level 1 intr */
#define MCFSIM_ICR_LEVEL2 0x08 /* Level 2 intr */
#define MCFSIM_ICR_LEVEL3 0x0c /* Level 3 intr */
#define MCFSIM_ICR_LEVEL4 0x10 /* Level 4 intr */
#define MCFSIM_ICR_LEVEL5 0x14 /* Level 5 intr */
#define MCFSIM_ICR_LEVEL6 0x18 /* Level 6 intr */
#define MCFSIM_ICR_LEVEL7 0x1c /* Level 7 intr */
#define MCFSIM_ICR_PRI0 0x00 /* Priority 0 intr */
#define MCFSIM_ICR_PRI1 0x01 /* Priority 1 intr */
#define MCFSIM_ICR_PRI2 0x02 /* Priority 2 intr */
#define MCFSIM_ICR_PRI3 0x03 /* Priority 3 intr */
/*
* Macros to read/set IMR register. It is 32 bits on the 5249.
@@ -184,4 +177,4 @@
#define mcf_setimr(imr) \
*((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR)) = (imr);
#endif /* mcf5249_h */
#endif /* mcf5249_h */

73
include/asm-m68k/m5253.h Normal file
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@@ -0,0 +1,73 @@
/*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef m5253_h
#define m5253_h
/****************************************************************************/
/*
* PLL Module (PLL)
*/
/* Register read/write macros */
#define PLL_PLLCR (0x000180)
#define SIM_RSR (0x000000)
#define SIM_SYPCR (0x000001)
#define SIM_SWIVR (0x000002)
#define SIM_SWSR (0x000003)
#define SIM_MPARK (0x00000C)
/* Bit definitions and macros for RSR */
#define SIM_RSR_SWTR (0x20)
#define SIM_RSR_HRST (0x80)
/* Register read/write macros */
#define CIM_MISCCR (0x000500)
#define CIM_ATA_DADDR (0x000504)
#define CIM_ATA_DCOUNT (0x000508)
#define CIM_RTC_TIME (0x00050C)
#define CIM_USB_CANCLK (0x000510)
/* Bit definitions and macros for MISCCR */
#define CIM_MISCCR_ADTA (0x00000001)
#define CIM_MISCCR_ADTD (0x00000002)
#define CIM_MISCCR_ADIE (0x00000004)
#define CIM_MISCCR_ADIC (0x00000008)
#define CIM_MISCCR_ADIP (0x00000010)
#define CIM_MISCCR_CPUEND (0x00000020)
#define CIM_MISCCR_DMAEND (0x00000040)
#define CIM_MISCCR_RTCCLR (0x00000080)
#define CIM_MISCCR_RTCPL (0x00000100)
#define CIM_MISCCR_URIE (0x00000800)
#define CIM_MISCCR_URIC (0x00001000)
#define CIM_MISCCR_URIP (0x00002000)
/* Bit definitions and macros for ATA_DADDR */
#define CIM_ATA_DADDR_ATAADDR(x) (((x)&0x00003FFF)<<2)
#define CIM_ATA_DADDR_RAMADDR(x) (((x)&0x00003FFF)<<18)
/* Bit definitions and macros for ATA_DCOUNT */
#define CIM_ATA_DCOUNT_COUNT(x) (((x)&0x0000FFFF))
#endif /* m5253_h */

105
include/asm-m68k/m5271.h
View File

@@ -25,7 +25,6 @@
* MA 02111-1307 USA
*/
#ifndef _MCF5271_H_
#define _MCF5271_H_
@@ -91,7 +90,7 @@
#define MCF_GPIO_PAR_UART_U1RXD_UART1 0x0C00
#define MCF_GPIO_PAR_UART_U1TXD_UART1 0x0300
#define MCF_GPIO_PAR_SDRAM_PAR_CSSDCS(x) (((x)&0x03)<<6)
#define MCF_GPIO_PAR_SDRAM_PAR_CSSDCS(x) (((x)&0x03)<<6)
#define MCF_SDRAMC_DCR 0x000040
#define MCF_SDRAMC_DACR0 0x000048
@@ -117,4 +116,104 @@
#define MCFSIM_ICR1 0x000C41
#endif /* _MCF5271_H_ */
/*********************************************************************
* Interrupt Controller (INTC)
*********************************************************************/
#define INT0_LO_RSVD0 (0)
#define INT0_LO_EPORT1 (1)
#define INT0_LO_EPORT2 (2)
#define INT0_LO_EPORT3 (3)
#define INT0_LO_EPORT4 (4)
#define INT0_LO_EPORT5 (5)
#define INT0_LO_EPORT6 (6)
#define INT0_LO_EPORT7 (7)
#define INT0_LO_SCM (8)
#define INT0_LO_DMA0 (9)
#define INT0_LO_DMA1 (10)
#define INT0_LO_DMA2 (11)
#define INT0_LO_DMA3 (12)
#define INT0_LO_UART0 (13)
#define INT0_LO_UART1 (14)
#define INT0_LO_UART2 (15)
#define INT0_LO_RSVD1 (16)
#define INT0_LO_I2C (17)
#define INT0_LO_QSPI (18)
#define INT0_LO_DTMR0 (19)
#define INT0_LO_DTMR1 (20)
#define INT0_LO_DTMR2 (21)
#define INT0_LO_DTMR3 (22)
#define INT0_LO_FEC_TXF (23)
#define INT0_LO_FEC_TXB (24)
#define INT0_LO_FEC_UN (25)
#define INT0_LO_FEC_RL (26)
#define INT0_LO_FEC_RXF (27)
#define INT0_LO_FEC_RXB (28)
#define INT0_LO_FEC_MII (29)
#define INT0_LO_FEC_LC (30)
#define INT0_LO_FEC_HBERR (31)
#define INT0_HI_FEC_GRA (32)
#define INT0_HI_FEC_EBERR (33)
#define INT0_HI_FEC_BABT (34)
#define INT0_HI_FEC_BABR (35)
#define INT0_HI_PIT0 (36)
#define INT0_HI_PIT1 (37)
#define INT0_HI_PIT2 (38)
#define INT0_HI_PIT3 (39)
#define INT0_HI_RNG (40)
#define INT0_HI_SKHA (41)
#define INT0_HI_MDHA (42)
#define INT0_HI_CAN1_BUF0I (43)
#define INT0_HI_CAN1_BUF1I (44)
#define INT0_HI_CAN1_BUF2I (45)
#define INT0_HI_CAN1_BUF3I (46)
#define INT0_HI_CAN1_BUF4I (47)
#define INT0_HI_CAN1_BUF5I (48)
#define INT0_HI_CAN1_BUF6I (49)
#define INT0_HI_CAN1_BUF7I (50)
#define INT0_HI_CAN1_BUF8I (51)
#define INT0_HI_CAN1_BUF9I (52)
#define INT0_HI_CAN1_BUF10I (53)
#define INT0_HI_CAN1_BUF11I (54)
#define INT0_HI_CAN1_BUF12I (55)
#define INT0_HI_CAN1_BUF13I (56)
#define INT0_HI_CAN1_BUF14I (57)
#define INT0_HI_CAN1_BUF15I (58)
#define INT0_HI_CAN1_ERRINT (59)
#define INT0_HI_CAN1_BOFFINT (60)
/* 60-63 Reserved */
/* Bit definitions and macros for INTC_IPRL */
#define INTC_IPRL_INT31 (0x80000000)
#define INTC_IPRL_INT30 (0x40000000)
#define INTC_IPRL_INT29 (0x20000000)
#define INTC_IPRL_INT28 (0x10000000)
#define INTC_IPRL_INT27 (0x08000000)
#define INTC_IPRL_INT26 (0x04000000)
#define INTC_IPRL_INT25 (0x02000000)
#define INTC_IPRL_INT24 (0x01000000)
#define INTC_IPRL_INT23 (0x00800000)
#define INTC_IPRL_INT22 (0x00400000)
#define INTC_IPRL_INT21 (0x00200000)
#define INTC_IPRL_INT20 (0x00100000)
#define INTC_IPRL_INT19 (0x00080000)
#define INTC_IPRL_INT18 (0x00040000)
#define INTC_IPRL_INT17 (0x00020000)
#define INTC_IPRL_INT16 (0x00010000)
#define INTC_IPRL_INT15 (0x00008000)
#define INTC_IPRL_INT14 (0x00004000)
#define INTC_IPRL_INT13 (0x00002000)
#define INTC_IPRL_INT12 (0x00001000)
#define INTC_IPRL_INT11 (0x00000800)
#define INTC_IPRL_INT10 (0x00000400)
#define INTC_IPRL_INT9 (0x00000200)
#define INTC_IPRL_INT8 (0x00000100)
#define INTC_IPRL_INT7 (0x00000080)
#define INTC_IPRL_INT6 (0x00000040)
#define INTC_IPRL_INT5 (0x00000020)
#define INTC_IPRL_INT4 (0x00000010)
#define INTC_IPRL_INT3 (0x00000008)
#define INTC_IPRL_INT2 (0x00000004)
#define INTC_IPRL_INT1 (0x00000002)
#define INTC_IPRL_INT0 (0x00000001)
#endif /* _MCF5271_H_ */

221
include/asm-m68k/m5272.h
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@@ -24,7 +24,6 @@
* MA 02111-1307 USA
*/
#ifndef mcf5272_h
#define mcf5272_h
/****************************************************************************/
@@ -35,65 +34,173 @@
#define INT_RAM_SIZE 4096
#define GPIO_PACNT_PA15MSK (0xC0000000)
#define GPIO_PACNT_DGNT1 (0x40000000)
#define GPIO_PACNT_PA14MSK (0x30000000)
#define GPIO_PACNT_DREQ1 (0x10000000)
#define GPIO_PACNT_PA13MSK (0x0C000000)
#define GPIO_PACNT_DFSC3 (0x04000000)
#define GPIO_PACNT_PA12MSK (0x03000000)
#define GPIO_PACNT_DFSC2 (0x01000000)
#define GPIO_PACNT_PA11MSK (0x00C00000)
#define GPIO_PACNT_QSPI_CS1 (0x00800000)
#define GPIO_PACNT_PA10MSK (0x00300000)
#define GPIO_PACNT_DREQ0 (0x00100000)
#define GPIO_PACNT_PA9MSK (0x000C0000)
#define GPIO_PACNT_DGNT0 (0x00040000)
#define GPIO_PACNT_PA8MSK (0x00030000)
#define GPIO_PACNT_FSC0 (0x00010000)
#define GPIO_PACNT_FSR0 (0x00010000)
#define GPIO_PACNT_PA7MSK (0x0000C000)
#define GPIO_PACNT_DOUT3 (0x00008000)
#define GPIO_PACNT_QSPI_CS3 (0x00004000)
#define GPIO_PACNT_PA6MSK (0x00003000)
#define GPIO_PACNT_USB_RXD (0x00001000)
#define GPIO_PACNT_PA5MSK (0x00000C00)
#define GPIO_PACNT_USB_TXEN (0x00000400)
#define GPIO_PACNT_PA4MSK (0x00000300)
#define GPIO_PACNT_USB_SUSP (0x00000100)
#define GPIO_PACNT_PA3MSK (0x000000C0)
#define GPIO_PACNT_USB_TN (0x00000040)
#define GPIO_PACNT_PA2MSK (0x00000030)
#define GPIO_PACNT_USB_RN (0x00000010)
#define GPIO_PACNT_PA1MSK (0x0000000C)
#define GPIO_PACNT_USB_RP (0x00000004)
#define GPIO_PACNT_PA0MSK (0x00000003)
#define GPIO_PACNT_USB_TP (0x00000001)
/*
* Define the 5272 SIM register set addresses.
*/
#define MCFSIM_SCR 0x04 /* SIM Config reg (r/w) */
#define MCFSIM_SPR 0x06 /* System Protection reg (r/w)*/
#define MCFSIM_PMR 0x08 /* Power Management reg (r/w) */
#define MCFSIM_APMR 0x0e /* Active Low Power reg (r/w) */
#define MCFSIM_DIR 0x10 /* Device Identity reg (r/w) */
#define GPIO_PBCNT_PB15MSK (0xC0000000)
#define GPIO_PBCNT_E_MDC (0x40000000)
#define GPIO_PBCNT_PB14MSK (0x30000000)
#define GPIO_PBCNT_E_RXER (0x10000000)
#define GPIO_PBCNT_PB13MSK (0x0C000000)
#define GPIO_PBCNT_E_RXD1 (0x04000000)
#define GPIO_PBCNT_PB12MSK (0x03000000)
#define GPIO_PBCNT_E_RXD2 (0x01000000)
#define GPIO_PBCNT_PB11MSK (0x00C00000)
#define GPIO_PBCNT_E_RXD3 (0x00400000)
#define GPIO_PBCNT_PB10MSK (0x00300000)
#define GPIO_PBCNT_E_TXD1 (0x00100000)
#define GPIO_PBCNT_PB9MSK (0x000C0000)
#define GPIO_PBCNT_E_TXD2 (0x00040000)
#define GPIO_PBCNT_PB8MSK (0x00030000)
#define GPIO_PBCNT_E_TXD3 (0x00010000)
#define GPIO_PBCNT_PB7MSK (0x0000C000)
#define GPIO_PBCNT_TOUT0 (0x00004000)
#define GPIO_PBCNT_PB6MSK (0x00003000)
#define GPIO_PBCNT_TA (0x00001000)
#define GPIO_PBCNT_PB4MSK (0x00000300)
#define GPIO_PBCNT_URT0_CLK (0x00000100)
#define GPIO_PBCNT_PB3MSK (0x000000C0)
#define GPIO_PBCNT_URT0_RTS (0x00000040)
#define GPIO_PBCNT_PB2MSK (0x00000030)
#define GPIO_PBCNT_URT0_CTS (0x00000010)
#define GPIO_PBCNT_PB1MSK (0x0000000C)
#define GPIO_PBCNT_URT0_RXD (0x00000004)
#define GPIO_PBCNT_URT0_TIN2 (0x00000004)
#define GPIO_PBCNT_PB0MSK (0x00000003)
#define GPIO_PBCNT_URT0_TXD (0x00000001)
#define MCFSIM_ICR1 0x20 /* Intr Ctrl reg 1 (r/w) */
#define MCFSIM_ICR2 0x24 /* Intr Ctrl reg 2 (r/w) */
#define MCFSIM_ICR3 0x28 /* Intr Ctrl reg 3 (r/w) */
#define MCFSIM_ICR4 0x2c /* Intr Ctrl reg 4 (r/w) */
#define GPIO_PDCNT_PD7MSK (0x0000C000)
#define GPIO_PDCNT_TIN1 (0x00008000)
#define GPIO_PDCNT_PWM_OUT2 (0x00004000)
#define GPIO_PDCNT_PD6MSK (0x00003000)
#define GPIO_PDCNT_TOUT1 (0x00002000)
#define GPIO_PDCNT_PWM_OUT1 (0x00001000)
#define GPIO_PDCNT_PD5MSK (0x00000C00)
#define GPIO_PDCNT_INT4 (0x00000C00)
#define GPIO_PDCNT_DIN3 (0x00000800)
#define GPIO_PDCNT_PD4MSK (0x00000300)
#define GPIO_PDCNT_URT1_TXD (0x00000200)
#define GPIO_PDCNT_DOUT0 (0x00000100)
#define GPIO_PDCNT_PD3MSK (0x000000C0)
#define GPIO_PDCNT_INT5 (0x000000C0)
#define GPIO_PDCNT_URT1_RTS (0x00000080)
#define GPIO_PDCNT_PD2MSK (0x00000030)
#define GPIO_PDCNT_QSPI_CS2 (0x00000030)
#define GPIO_PDCNT_URT1_CTS (0x00000020)
#define GPIO_PDCNT_PD1MSK (0x0000000C)
#define GPIO_PDCNT_URT1_RXD (0x00000008)
#define GPIO_PDCNT_URT1_TIN3 (0x00000008)
#define GPIO_PDCNT_DIN0 (0x00000004)
#define GPIO_PDCNT_PD0MSK (0x00000003)
#define GPIO_PDCNT_URT1_CLK (0x00000002)
#define GPIO_PDCNT_DCL0 (0x00000001)
#define MCFSIM_ISR 0x30 /* Interrupt Source reg (r/w) */
#define MCFSIM_PITR 0x34 /* Interrupt Transition (r/w) */
#define MCFSIM_PIWR 0x38 /* Interrupt Wakeup reg (r/w) */
#define MCFSIM_PIVR 0x3f /* Interrupt Vector reg (r/w( */
#define INT_RSVD0 (0)
#define INT_INT1 (1)
#define INT_INT2 (2)
#define INT_INT3 (3)
#define INT_INT4 (4)
#define INT_TMR0 (5)
#define INT_TMR1 (6)
#define INT_TMR2 (7)
#define INT_TMR3 (8)
#define INT_UART1 (9)
#define INT_UART2 (10)
#define INT_PLIP (11)
#define INT_PLIA (12)
#define INT_USB0 (13)
#define INT_USB1 (14)
#define INT_USB2 (15)
#define INT_USB3 (16)
#define INT_USB4 (17)
#define INT_USB5 (18)
#define INT_USB6 (19)
#define INT_USB7 (20)
#define INT_DMA (21)
#define INT_ERX (22)
#define INT_ETX (23)
#define INT_ENTC (24)
#define INT_QSPI (25)
#define INT_INT5 (26)
#define INT_INT6 (27)
#define INT_SWTO (28)
#define MCFSIM_WRRR 0x280 /* Watchdog reference (r/w) */
#define MCFSIM_WIRR 0x284 /* Watchdog interrupt (r/w) */
#define MCFSIM_WCR 0x288 /* Watchdog counter (r/w) */
#define MCFSIM_WER 0x28c /* Watchdog event (r/w) */
#define INT_ICR1_TMR0MASK (0x000F000)
#define INT_ICR1_TMR0PI (0x0008000)
#define INT_ICR1_TMR0IPL(x) (((x)&0x7)<<12)
#define INT_ICR1_TMR1MASK (0x0000F00)
#define INT_ICR1_TMR1PI (0x0000800)
#define INT_ICR1_TMR1IPL(x) (((x)&0x7)<<8)
#define INT_ICR1_TMR2MASK (0x00000F0)
#define INT_ICR1_TMR2PI (0x0000080)
#define INT_ICR1_TMR2IPL(x) (((x)&0x7)<<4)
#define INT_ICR1_TMR3MASK (0x000000F)
#define INT_ICR1_TMR3PI (0x0000008)
#define INT_ICR1_TMR3IPL(x) (((x)&0x7))
#define MCFSIM_CSBR0 0x40 /* CS0 Base Address (r/w) */
#define MCFSIM_CSOR0 0x44 /* CS0 Option (r/w) */
#define MCFSIM_CSBR1 0x48 /* CS1 Base Address (r/w) */
#define MCFSIM_CSOR1 0x4c /* CS1 Option (r/w) */
#define MCFSIM_CSBR2 0x50 /* CS2 Base Address (r/w) */
#define MCFSIM_CSOR2 0x54 /* CS2 Option (r/w) */
#define MCFSIM_CSBR3 0x58 /* CS3 Base Address (r/w) */
#define MCFSIM_CSOR3 0x5c /* CS3 Option (r/w) */
#define MCFSIM_CSBR4 0x60 /* CS4 Base Address (r/w) */
#define MCFSIM_CSOR4 0x64 /* CS4 Option (r/w) */
#define MCFSIM_CSBR5 0x68 /* CS5 Base Address (r/w) */
#define MCFSIM_CSOR5 0x6c /* CS5 Option (r/w) */
#define MCFSIM_CSBR6 0x70 /* CS6 Base Address (r/w) */
#define MCFSIM_CSOR6 0x74 /* CS6 Option (r/w) */
#define MCFSIM_CSBR7 0x78 /* CS7 Base Address (r/w) */
#define MCFSIM_CSOR7 0x7c /* CS7 Option (r/w) */
#define INT_ISR_INT31 (0x80000000)
#define INT_ISR_INT30 (0x40000000)
#define INT_ISR_INT29 (0x20000000)
#define INT_ISR_INT28 (0x10000000)
#define INT_ISR_INT27 (0x08000000)
#define INT_ISR_INT26 (0x04000000)
#define INT_ISR_INT25 (0x02000000)
#define INT_ISR_INT24 (0x01000000)
#define INT_ISR_INT23 (0x00800000)
#define INT_ISR_INT22 (0x00400000)
#define INT_ISR_INT21 (0x00200000)
#define INT_ISR_INT20 (0x00100000)
#define INT_ISR_INT19 (0x00080000)
#define INT_ISR_INT18 (0x00040000)
#define INT_ISR_INT17 (0x00020000)
#define INT_ISR_INT16 (0x00010000)
#define INT_ISR_INT15 (0x00008000)
#define INT_ISR_INT14 (0x00004000)
#define INT_ISR_INT13 (0x00002000)
#define INT_ISR_INT12 (0x00001000)
#define INT_ISR_INT11 (0x00000800)
#define INT_ISR_INT10 (0x00000400)
#define INT_ISR_INT9 (0x00000200)
#define INT_ISR_INT8 (0x00000100)
#define INT_ISR_INT7 (0x00000080)
#define INT_ISR_INT6 (0x00000040)
#define INT_ISR_INT5 (0x00000020)
#define INT_ISR_INT4 (0x00000010)
#define INT_ISR_INT3 (0x00000008)
#define INT_ISR_INT2 (0x00000004)
#define INT_ISR_INT1 (0x00000002)
#define INT_ISR_INT0 (0x00000001)
#define MCFSIM_SDCR 0x180 /* SDRAM Configuration (r/w) */
#define MCFSIM_SDTR 0x184 /* SDRAM Timing (r/w) */
#define MCFSIM_DCAR0 0x4c /* DRAM 0 Address reg(r/w) */
#define MCFSIM_DCMR0 0x50 /* DRAM 0 Mask reg (r/w) */
#define MCFSIM_DCCR0 0x57 /* DRAM 0 Control reg (r/w) */
#define MCFSIM_DCAR1 0x58 /* DRAM 1 Address reg (r/w) */
#define MCFSIM_DCMR1 0x5c /* DRAM 1 Mask reg (r/w) */
#define MCFSIM_DCCR1 0x63 /* DRAM 1 Control reg (r/w) */
#define MCFSIM_PACNT 0x80 /* Port A Control (r/w) */
#define MCFSIM_PADDR 0x84 /* Port A Direction (r/w) */
#define MCFSIM_PADAT 0x86 /* Port A Data (r/w) */
#define MCFSIM_PBCNT 0x88 /* Port B Control (r/w) */
#define MCFSIM_PBDDR 0x8c /* Port B Direction (r/w) */
#define MCFSIM_PBDAT 0x8e /* Port B Data (r/w) */
#define MCFSIM_PCDDR 0x94 /* Port C Direction (r/w) */
#define MCFSIM_PCDAT 0x96 /* Port C Data (r/w) */
#define MCFSIM_PDCNT 0x98 /* Port D Control (r/w) */
#endif /* mcf5272_h */
#endif /* mcf5272_h */

262
include/asm-m68k/m5282.h
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@@ -23,7 +23,99 @@
/****************************************************************************/
#ifndef m5282_h
#define m5282_h
/****************************************************************************/
/*********************************************************************
* PLL Clock Module
*********************************************************************/
/* Bit definitions and macros for PLL_SYNCR */
#define PLL_SYNCR_LOLRE (0x8000)
#define PLL_SYNCR_MFD2 (0x4000)
#define PLL_SYNCR_MFD1 (0x2000)
#define PLL_SYNCR_MFD0 (0x1000)
#define PLL_SYNCR_LOCRE (0x0800)
#define PLL_SYNCR_RFC2 (0x0400)
#define PLL_SYNCR_RFC1 (0x0200)
#define PLL_SYNCR_RFC0 (0x0100)
#define PLL_SYNCR_LOCEN (0x0080)
#define PLL_SYNCR_DISCLK (0x0040)
#define PLL_SYNCR_FWKUP (0x0020)
#define PLL_SYNCR_STPMD1 (0x0008)
#define PLL_SYNCR_STPMD0 (0x0004)
/* Bit definitions and macros for PLL_SYNSR */
#define PLL_SYNSR_MODE (0x0080)
#define PLL_SYNSR_PLLSEL (0x0040)
#define PLL_SYNSR_PLLREF (0x0020)
#define PLL_SYNSR_LOCKS (0x0010)
#define PLL_SYNSR_LOCK (0x0008)
#define PLL_SYNSR_LOCS (0x0004)
/*********************************************************************
* Interrupt Controller (INTC)
*********************************************************************/
#define INT0_LO_RSVD0 (0)
#define INT0_LO_EPORT1 (1)
#define INT0_LO_EPORT2 (2)
#define INT0_LO_EPORT3 (3)
#define INT0_LO_EPORT4 (4)
#define INT0_LO_EPORT5 (5)
#define INT0_LO_EPORT6 (6)
#define INT0_LO_EPORT7 (7)
#define INT0_LO_SCM_SWT1 (8)
#define INT0_LO_DMA_00 (9)
#define INT0_LO_DMA_01 (10)
#define INT0_LO_DMA_02 (11)
#define INT0_LO_DMA_03 (12)
#define INT0_LO_UART0 (13)
#define INT0_LO_UART1 (14)
#define INT0_LO_UART2 (15)
#define INT0_LO_RSVD1 (16)
#define INT0_LO_I2C (17)
#define INT0_LO_QSPI (18)
#define INT0_LO_DTMR0 (19)
#define INT0_LO_DTMR1 (20)
#define INT0_LO_DTMR2 (21)
#define INT0_LO_DTMR3 (22)
#define INT0_LO_FEC_TXF (23)
#define INT0_LO_FEC_TXB (24)
#define INT0_LO_FEC_UN (25)
#define INT0_LO_FEC_RL (26)
#define INT0_LO_FEC_RXF (27)
#define INT0_LO_FEC_RXB (28)
#define INT0_LO_FEC_MII (29)
#define INT0_LO_FEC_LC (30)
#define INT0_LO_FEC_HBERR (31)
#define INT0_HI_FEC_GRA (32)
#define INT0_HI_FEC_EBERR (33)
#define INT0_HI_FEC_BABT (34)
#define INT0_HI_FEC_BABR (35)
#define INT0_HI_PMM_LVDF (36)
#define INT0_HI_QADC_CF1 (37)
#define INT0_HI_QADC_CF2 (38)
#define INT0_HI_QADC_PF1 (39)
#define INT0_HI_QADC_PF2 (40)
#define INT0_HI_GPTA_TOF (41)
#define INT0_HI_GPTA_PAIF (42)
#define INT0_HI_GPTA_PAOVF (43)
#define INT0_HI_GPTA_C0F (44)
#define INT0_HI_GPTA_C1F (45)
#define INT0_HI_GPTA_C2F (46)
#define INT0_HI_GPTA_C3F (47)
#define INT0_HI_GPTB_TOF (48)
#define INT0_HI_GPTB_PAIF (49)
#define INT0_HI_GPTB_PAOVF (50)
#define INT0_HI_GPTB_C0F (51)
#define INT0_HI_GPTB_C1F (52)
#define INT0_HI_GPTB_C2F (53)
#define INT0_HI_GPTB_C3F (54)
#define INT0_HI_PIT0 (55)
#define INT0_HI_PIT1 (56)
#define INT0_HI_PIT2 (57)
#define INT0_HI_PIT3 (58)
#define INT0_HI_CFM_CBEIF (59)
#define INT0_HI_CFM_CCIF (60)
#define INT0_HI_CFM_PVIF (61)
#define INT0_HI_CFM_AEIF (62)
/*
* Size of internal RAM
@@ -96,49 +188,49 @@
#define MCFGPIO_SETD (*(vu_char *) (CFG_MBAR+0x10002B))
#define MCFGPIO_SETE (*(vu_char *) (CFG_MBAR+0x10002C))
#define MCFGPIO_SETF (*(vu_char *) (CFG_MBAR+0x10002D))
#define MCFGPIO_SETG (*(vu_char *) (CFG_MBAR+0x10002E))
#define MCFGPIO_SETH (*(vu_char *) (CFG_MBAR+0x10002F))
#define MCFGPIO_SETJ (*(vu_char *) (CFG_MBAR+0x100030))
#define MCFGPIO_SETDD (*(vu_char *) (CFG_MBAR+0x100031))
#define MCFGPIO_SETEH (*(vu_char *) (CFG_MBAR+0x100032))
#define MCFGPIO_SETEL (*(vu_char *) (CFG_MBAR+0x100033))
#define MCFGPIO_SETAS (*(vu_char *) (CFG_MBAR+0x100034))
#define MCFGPIO_SETQS (*(vu_char *) (CFG_MBAR+0x100035))
#define MCFGPIO_SETSD (*(vu_char *) (CFG_MBAR+0x100036))
#define MCFGPIO_SETTC (*(vu_char *) (CFG_MBAR+0x100037))
#define MCFGPIO_SETTD (*(vu_char *) (CFG_MBAR+0x100038))
#define MCFGPIO_SETUA (*(vu_char *) (CFG_MBAR+0x100039))
#define MCFGPIO_SETG (*(vu_char *) (CFG_MBAR+0x10002E))
#define MCFGPIO_SETH (*(vu_char *) (CFG_MBAR+0x10002F))
#define MCFGPIO_SETJ (*(vu_char *) (CFG_MBAR+0x100030))
#define MCFGPIO_SETDD (*(vu_char *) (CFG_MBAR+0x100031))
#define MCFGPIO_SETEH (*(vu_char *) (CFG_MBAR+0x100032))
#define MCFGPIO_SETEL (*(vu_char *) (CFG_MBAR+0x100033))
#define MCFGPIO_SETAS (*(vu_char *) (CFG_MBAR+0x100034))
#define MCFGPIO_SETQS (*(vu_char *) (CFG_MBAR+0x100035))
#define MCFGPIO_SETSD (*(vu_char *) (CFG_MBAR+0x100036))
#define MCFGPIO_SETTC (*(vu_char *) (CFG_MBAR+0x100037))
#define MCFGPIO_SETTD (*(vu_char *) (CFG_MBAR+0x100038))
#define MCFGPIO_SETUA (*(vu_char *) (CFG_MBAR+0x100039))
#define MCFGPIO_CLRA (*(vu_char *) (CFG_MBAR+0x10003C))
#define MCFGPIO_CLRB (*(vu_char *) (CFG_MBAR+0x10003D))
#define MCFGPIO_CLRC (*(vu_char *) (CFG_MBAR+0x10003E))
#define MCFGPIO_CLRD (*(vu_char *) (CFG_MBAR+0x10003F))
#define MCFGPIO_CLRE (*(vu_char *) (CFG_MBAR+0x100040))
#define MCFGPIO_CLRF (*(vu_char *) (CFG_MBAR+0x100041))
#define MCFGPIO_CLRG (*(vu_char *) (CFG_MBAR+0x100042))
#define MCFGPIO_CLRH (*(vu_char *) (CFG_MBAR+0x100043))
#define MCFGPIO_CLRJ (*(vu_char *) (CFG_MBAR+0x100044))
#define MCFGPIO_CLRDD (*(vu_char *) (CFG_MBAR+0x100045))
#define MCFGPIO_CLREH (*(vu_char *) (CFG_MBAR+0x100046))
#define MCFGPIO_CLREL (*(vu_char *) (CFG_MBAR+0x100047))
#define MCFGPIO_CLRAS (*(vu_char *) (CFG_MBAR+0x100048))
#define MCFGPIO_CLRQS (*(vu_char *) (CFG_MBAR+0x100049))
#define MCFGPIO_CLRSD (*(vu_char *) (CFG_MBAR+0x10004A))
#define MCFGPIO_CLRTC (*(vu_char *) (CFG_MBAR+0x10004B))
#define MCFGPIO_CLRTD (*(vu_char *) (CFG_MBAR+0x10004C))
#define MCFGPIO_CLRUA (*(vu_char *) (CFG_MBAR+0x10004D))
#define MCFGPIO_CLRA (*(vu_char *) (CFG_MBAR+0x10003C))
#define MCFGPIO_CLRB (*(vu_char *) (CFG_MBAR+0x10003D))
#define MCFGPIO_CLRC (*(vu_char *) (CFG_MBAR+0x10003E))
#define MCFGPIO_CLRD (*(vu_char *) (CFG_MBAR+0x10003F))
#define MCFGPIO_CLRE (*(vu_char *) (CFG_MBAR+0x100040))
#define MCFGPIO_CLRF (*(vu_char *) (CFG_MBAR+0x100041))
#define MCFGPIO_CLRG (*(vu_char *) (CFG_MBAR+0x100042))
#define MCFGPIO_CLRH (*(vu_char *) (CFG_MBAR+0x100043))
#define MCFGPIO_CLRJ (*(vu_char *) (CFG_MBAR+0x100044))
#define MCFGPIO_CLRDD (*(vu_char *) (CFG_MBAR+0x100045))
#define MCFGPIO_CLREH (*(vu_char *) (CFG_MBAR+0x100046))
#define MCFGPIO_CLREL (*(vu_char *) (CFG_MBAR+0x100047))
#define MCFGPIO_CLRAS (*(vu_char *) (CFG_MBAR+0x100048))
#define MCFGPIO_CLRQS (*(vu_char *) (CFG_MBAR+0x100049))
#define MCFGPIO_CLRSD (*(vu_char *) (CFG_MBAR+0x10004A))
#define MCFGPIO_CLRTC (*(vu_char *) (CFG_MBAR+0x10004B))
#define MCFGPIO_CLRTD (*(vu_char *) (CFG_MBAR+0x10004C))
#define MCFGPIO_CLRUA (*(vu_char *) (CFG_MBAR+0x10004D))
#define MCFGPIO_PBCDPAR (*(vu_char *) (CFG_MBAR+0x100050))
#define MCFGPIO_PFPAR (*(vu_char *) (CFG_MBAR+0x100051))
#define MCFGPIO_PEPAR (*(vu_short *)(CFG_MBAR+0x100052))
#define MCFGPIO_PJPAR (*(vu_char *) (CFG_MBAR+0x100054))
#define MCFGPIO_PSDPAR (*(vu_char *) (CFG_MBAR+0x100055))
#define MCFGPIO_PASPAR (*(vu_short *)(CFG_MBAR+0x100056))
#define MCFGPIO_PEHLPAR (*(vu_char *) (CFG_MBAR+0x100058))
#define MCFGPIO_PQSPAR (*(vu_char *) (CFG_MBAR+0x100059))
#define MCFGPIO_PTCPAR (*(vu_char *) (CFG_MBAR+0x10005A))
#define MCFGPIO_PTDPAR (*(vu_char *) (CFG_MBAR+0x10005B))
#define MCFGPIO_PUAPAR (*(vu_char *) (CFG_MBAR+0x10005C))
#define MCFGPIO_PBCDPAR (*(vu_char *) (CFG_MBAR+0x100050))
#define MCFGPIO_PFPAR (*(vu_char *) (CFG_MBAR+0x100051))
#define MCFGPIO_PEPAR (*(vu_short *)(CFG_MBAR+0x100052))
#define MCFGPIO_PJPAR (*(vu_char *) (CFG_MBAR+0x100054))
#define MCFGPIO_PSDPAR (*(vu_char *) (CFG_MBAR+0x100055))
#define MCFGPIO_PASPAR (*(vu_short *)(CFG_MBAR+0x100056))
#define MCFGPIO_PEHLPAR (*(vu_char *) (CFG_MBAR+0x100058))
#define MCFGPIO_PQSPAR (*(vu_char *) (CFG_MBAR+0x100059))
#define MCFGPIO_PTCPAR (*(vu_char *) (CFG_MBAR+0x10005A))
#define MCFGPIO_PTDPAR (*(vu_char *) (CFG_MBAR+0x10005B))
#define MCFGPIO_PUAPAR (*(vu_char *) (CFG_MBAR+0x10005C))
/* Bit level definitions and macros */
#define MCFGPIO_PORT7 (0x80)
@@ -171,7 +263,6 @@
#define MCFGPIO_Px0 (0x01)
#define MCFGPIO_Px(x) (0x01<<x)
#define MCFGPIO_PBCDPAR_PBPA (0x80)
#define MCFGPIO_PBCDPAR_PCDPA (0x40)
@@ -236,7 +327,7 @@
/* System Conrol Module SCM */
#define MCFSCM_RAMBAR (*(vu_long *) (CFG_MBAR+0x00000008))
#define MCFSCM_RAMBAR (*(vu_long *) (CFG_MBAR+0x00000008))
#define MCFSCM_CRSR (*(vu_char *) (CFG_MBAR+0x00000010))
#define MCFSCM_CWCR (*(vu_char *) (CFG_MBAR+0x00000011))
#define MCFSCM_LPICR (*(vu_char *) (CFG_MBAR+0x00000012))
@@ -256,34 +347,33 @@
#define MCFSCM_GPACR0 (*(vu_char *) (CFG_MBAR+0x00000030))
#define MCFSCM_GPACR1 (*(vu_char *) (CFG_MBAR+0x00000031))
#define MCFSCM_CRSR_EXT (0x80)
#define MCFSCM_CRSR_CWDR (0x20)
#define MCFSCM_RAMBAR_BA(x) ((x)&0xFFFF0000)
#define MCFSCM_RAMBAR_BDE (0x00000200)
#define MCFSCM_RAMBAR_BA(x) ((x)&0xFFFF0000)
#define MCFSCM_RAMBAR_BDE (0x00000200)
/* Reset Controller Module RCM */
#define MCFRESET_RCR (*(vu_char *) (CFG_MBAR+0x00110000))
#define MCFRESET_RSR (*(vu_char *) (CFG_MBAR+0x00110001))
#define MCFRESET_RCR_SOFTRST (0x80)
#define MCFRESET_RCR_FRCRSTOUT (0x40)
#define MCFRESET_RCR_LVDF (0x10)
#define MCFRESET_RCR_LVDIE (0x08)
#define MCFRESET_RCR_LVDRE (0x04)
#define MCFRESET_RCR_LVDE (0x01)
#define MCFRESET_RCR_SOFTRST (0x80)
#define MCFRESET_RCR_FRCRSTOUT (0x40)
#define MCFRESET_RCR_LVDF (0x10)
#define MCFRESET_RCR_LVDIE (0x08)
#define MCFRESET_RCR_LVDRE (0x04)
#define MCFRESET_RCR_LVDE (0x01)
#define MCFRESET_RSR_LVD (0x40)
#define MCFRESET_RSR_SOFT (0x20)
#define MCFRESET_RSR_WDR (0x10)
#define MCFRESET_RSR_POR (0x08)
#define MCFRESET_RSR_EXT (0x04)
#define MCFRESET_RSR_LOC (0x02)
#define MCFRESET_RSR_LOL (0x01)
#define MCFRESET_RSR_ALL (0x7F)
#define MCFRESET_RCR_SOFTRST (0x80)
#define MCFRESET_RCR_FRCRSTOUT (0x40)
#define MCFRESET_RSR_LVD (0x40)
#define MCFRESET_RSR_SOFT (0x20)
#define MCFRESET_RSR_WDR (0x10)
#define MCFRESET_RSR_POR (0x08)
#define MCFRESET_RSR_EXT (0x04)
#define MCFRESET_RSR_LOC (0x02)
#define MCFRESET_RSR_LOL (0x01)
#define MCFRESET_RSR_ALL (0x7F)
#define MCFRESET_RCR_SOFTRST (0x80)
#define MCFRESET_RCR_FRCRSTOUT (0x40)
/* Chip Configuration Module CCM */
@@ -291,26 +381,25 @@
#define MCFCCM_RCON (*(vu_short *)(CFG_MBAR+0x00110008))
#define MCFCCM_CIR (*(vu_short *)(CFG_MBAR+0x0011000A))
/* Bit level definitions and macros */
#define MCFCCM_CCR_LOAD (0x8000)
#define MCFCCM_CCR_MODE(x) (((x)&0x0007)<<8)
#define MCFCCM_CCR_SZEN (0x0040)
#define MCFCCM_CCR_PSTEN (0x0020)
#define MCFCCM_CCR_SZEN (0x0040)
#define MCFCCM_CCR_PSTEN (0x0020)
#define MCFCCM_CCR_BME (0x0008)
#define MCFCCM_CCR_BMT(x) (((x)&0x0007))
#define MCFCCM_CCR_BMT(x) (((x)&0x0007))
#define MCFCCM_CIR_PIN_MASK (0xFF00)
#define MCFCCM_CIR_PRN_MASK (0x00FF)
/* Clock Module */
#define MCFCLOCK_SYNCR (*(vu_short *)(CFG_MBAR+0x120000))
#define MCFCLOCK_SYNSR (*(vu_char *) (CFG_MBAR+0x120002))
#define MCFCLOCK_SYNCR (*(vu_short *)(CFG_MBAR+0x120000))
#define MCFCLOCK_SYNSR (*(vu_char *) (CFG_MBAR+0x120002))
#define MCFCLOCK_SYNCR_MFD(x) (((x)&0x0007)<<12)
#define MCFCLOCK_SYNCR_RFD(x) (((x)&0x0007)<<8)
#define MCFCLOCK_SYNSR_LOCK 0x08
#define MCFCLOCK_SYNCR_MFD(x) (((x)&0x0007)<<12)
#define MCFCLOCK_SYNCR_RFD(x) (((x)&0x0007)<<8)
#define MCFCLOCK_SYNSR_LOCK 0x08
#define MCFSDRAMC_DCR (*(vu_short *)(CFG_MBAR+0x00000040))
#define MCFSDRAMC_DACR0 (*(vu_long *) (CFG_MBAR+0x00000048))
@@ -337,19 +426,19 @@
#define MCFSDRAMC_DACR_IMRS (0x00000040)
#define MCFSDRAMC_DMR_BAM_16M (0x00FC0000)
#define MCFSDRAMC_DMR_WP (0x00000100)
#define MCFSDRAMC_DMR_CI (0x00000040)
#define MCFSDRAMC_DMR_AM (0x00000020)
#define MCFSDRAMC_DMR_SC (0x00000010)
#define MCFSDRAMC_DMR_SD (0x00000008)
#define MCFSDRAMC_DMR_UC (0x00000004)
#define MCFSDRAMC_DMR_UD (0x00000002)
#define MCFSDRAMC_DMR_V (0x00000001)
#define MCFSDRAMC_DMR_WP (0x00000100)
#define MCFSDRAMC_DMR_CI (0x00000040)
#define MCFSDRAMC_DMR_AM (0x00000020)
#define MCFSDRAMC_DMR_SC (0x00000010)
#define MCFSDRAMC_DMR_SD (0x00000008)
#define MCFSDRAMC_DMR_UC (0x00000004)
#define MCFSDRAMC_DMR_UD (0x00000002)
#define MCFSDRAMC_DMR_V (0x00000001)
#define MCFWTM_WCR (*(vu_short *)(CFG_MBAR+0x00140000))
#define MCFWTM_WMR (*(vu_short *)(CFG_MBAR+0x00140002))
#define MCFWTM_WCNTR (*(vu_short *)(CFG_MBAR+0x00140004))
#define MCFWTM_WSR (*(vu_short *)(CFG_MBAR+0x00140006))
#define MCFWTM_WCR (*(vu_short *)(CFG_MBAR+0x00140000))
#define MCFWTM_WMR (*(vu_short *)(CFG_MBAR+0x00140002))
#define MCFWTM_WCNTR (*(vu_short *)(CFG_MBAR+0x00140004))
#define MCFWTM_WSR (*(vu_short *)(CFG_MBAR+0x00140006))
/* Chip SELECT Module CSM */
#define MCFCSM_CSAR0 (*(vu_short *)(CFG_MBAR+0x00000080))
@@ -375,9 +464,7 @@
#define MCFCSM_CSCR_PS_16 (0x0080)
/*********************************************************************
*
* General Purpose Timer (GPT) Module
*
*********************************************************************/
#define MCFGPTA_GPTIOS (*(vu_char *)(CFG_MBAR+0x1A0000))
@@ -403,7 +490,6 @@
#define MCFGPTA_GPTPORT (*(vu_char *)(CFG_MBAR+0x1A001D))
#define MCFGPTA_GPTDDR (*(vu_char *)(CFG_MBAR+0x1A001E))
#define MCFGPTB_GPTIOS (*(vu_char *)(CFG_MBAR+0x1B0000))
#define MCFGPTB_GPTCFORC (*(vu_char *)(CFG_MBAR+0x1B0001))
#define MCFGPTB_GPTOC3M (*(vu_char *)(CFG_MBAR+0x1B0002))
@@ -542,4 +628,4 @@
#define MCFCFM_CMD_MASERS 0x41
/****************************************************************************/
#endif /* m5282_h */
#endif /* m5282_h */

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include/asm-m68k/m5329.h Normal file
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1541
include/asm-m68k/m5445x.h Normal file
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113
include/asm-m68k/mcftimer.h
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/*
* mcftimer.h -- ColdFire internal TIMER support defines.
*
* Based on mcftimer.h of uCLinux distribution:
* (C) Copyright 1999-2002, Greg Ungerer (gerg@snapgear.com)
* (C) Copyright 2000, Lineo Inc. (www.lineo.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/****************************************************************************/
#ifndef mcftimer_h
#define mcftimer_h
/****************************************************************************/
#include <linux/config.h>
/*
* Get address specific defines for this ColdFire member.
*/
#if defined(CONFIG_M5204) || defined(CONFIG_M5206) || defined(CONFIG_M5206e)
#define MCFTIMER_BASE1 0x100 /* Base address of TIMER1 */
#define MCFTIMER_BASE2 0x120 /* Base address of TIMER2 */
#elif defined(CONFIG_M5272)
#define MCFTIMER_BASE1 0x200 /* Base address of TIMER1 */
#define MCFTIMER_BASE2 0x220 /* Base address of TIMER2 */
#define MCFTIMER_BASE3 0x240 /* Base address of TIMER4 */
#define MCFTIMER_BASE4 0x260 /* Base address of TIMER3 */
#elif defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407)
#define MCFTIMER_BASE1 0x140 /* Base address of TIMER1 */
#define MCFTIMER_BASE2 0x180 /* Base address of TIMER2 */
#elif defined(CONFIG_M5282) | defined(CONFIG_M5271)
#define MCFTIMER_BASE1 0x150000 /* Base address of TIMER1 */
#define MCFTIMER_BASE2 0x160000 /* Base address of TIMER2 */
#define MCFTIMER_BASE3 0x170000 /* Base address of TIMER4 */
#define MCFTIMER_BASE4 0x180000 /* Base address of TIMER3 */
#endif
/*
* Define the TIMER register set addresses.
*/
#define MCFTIMER_TMR 0x00 /* Timer Mode reg (r/w) */
#define MCFTIMER_TRR 0x02 /* Timer Reference (r/w) */
#define MCFTIMER_TCR 0x04 /* Timer Capture reg (r/w) */
#define MCFTIMER_TCN 0x06 /* Timer Counter reg (r/w) */
#define MCFTIMER_TER 0x11 /* Timer Event reg (r/w) */
/*
* Define the TIMER register set addresses for 5282.
*/
#define MCFTIMER_PCSR 0
#define MCFTIMER_PMR 1
#define MCFTIMER_PCNTR 2
/*
* Bit definitions for the Timer Mode Register (TMR).
* Register bit flags are common accross ColdFires.
*/
#define MCFTIMER_TMR_PREMASK 0xff00 /* Prescalar mask */
#define MCFTIMER_TMR_DISCE 0x0000 /* Disable capture */
#define MCFTIMER_TMR_ANYCE 0x00c0 /* Capture any edge */
#define MCFTIMER_TMR_FALLCE 0x0080 /* Capture fallingedge */
#define MCFTIMER_TMR_RISECE 0x0040 /* Capture rising edge */
#define MCFTIMER_TMR_ENOM 0x0020 /* Enable output toggle */
#define MCFTIMER_TMR_DISOM 0x0000 /* Do single output pulse */
#define MCFTIMER_TMR_ENORI 0x0010 /* Enable ref interrupt */
#define MCFTIMER_TMR_DISORI 0x0000 /* Disable ref interrupt */
#define MCFTIMER_TMR_RESTART 0x0008 /* Restart counter */
#define MCFTIMER_TMR_FREERUN 0x0000 /* Free running counter */
#define MCFTIMER_TMR_CLKTIN 0x0006 /* Input clock is TIN */
#define MCFTIMER_TMR_CLK16 0x0004 /* Input clock is /16 */
#define MCFTIMER_TMR_CLK1 0x0002 /* Input clock is /1 */
#define MCFTIMER_TMR_CLKSTOP 0x0000 /* Stop counter */
#define MCFTIMER_TMR_ENABLE 0x0001 /* Enable timer */
#define MCFTIMER_TMR_DISABLE 0x0000 /* Disable timer */
/*
* Bit definitions for the Timer Event Registers (TER).
*/
#define MCFTIMER_TER_CAP 0x01 /* Capture event */
#define MCFTIMER_TER_REF 0x02 /* Refernece event */
/*
* Bit definitions for the 5282 PIT Control and Status Register (PCSR).
*/
#define MCFTIMER_PCSR_EN 0x0001
#define MCFTIMER_PCSR_RLD 0x0002
#define MCFTIMER_PCSR_PIF 0x0004
#define MCFTIMER_PCSR_PIE 0x0008
#define MCFTIMER_PCSR_OVW 0x0010
#define MCFTIMER_PCSR_HALTED 0x0020
#define MCFTIMER_PCSR_DOZE 0x0040
/****************************************************************************/
#endif /* mcftimer_h */

221
include/asm-m68k/mcfuart.h
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@@ -1,221 +0,0 @@
/*
* mcfuart.h -- ColdFire internal UART support defines.
*
* File copied from mcfuart.h of uCLinux distribution:
* (C) Copyright 1999, Greg Ungerer (gerg@snapgear.com)
* (C) Copyright 2000, Lineo Inc. (www.lineo.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/****************************************************************************/
#ifndef mcfuart_h
#define mcfuart_h
/****************************************************************************/
#include <linux/config.h>
/*
* Define the base address of the UARTS within the MBAR address
* space.
*/
#if defined(CONFIG_M5272)
#define MCFUART_BASE1 0x100 /* Base address of UART1 */
#define MCFUART_BASE2 0x140 /* Base address of UART2 */
#elif defined(CONFIG_M5204) || defined(CONFIG_M5206) || defined(CONFIG_M5206e)
#if defined(CONFIG_NETtel)
#define MCFUART_BASE1 0x180 /* Base address of UART1 */
#define MCFUART_BASE2 0x140 /* Base address of UART2 */
#else
#define MCFUART_BASE1 0x140 /* Base address of UART1 */
#define MCFUART_BASE2 0x180 /* Base address of UART2 */
#endif
#elif defined(CONFIG_M5282) || defined(CONFIG_M5271)
#define MCFUART_BASE1 0x200 /* Base address of UART1 */
#define MCFUART_BASE2 0x240 /* Base address of UART2 */
#define MCFUART_BASE3 0x280 /* Base address of UART3 */
#elif defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407)
#if defined(CONFIG_NETtel) || defined(CONFIG_DISKtel) || defined(CONFIG_SECUREEDGEMP3)
#define MCFUART_BASE1 0x200 /* Base address of UART1 */
#define MCFUART_BASE2 0x1c0 /* Base address of UART2 */
#else
#define MCFUART_BASE1 0x1c0 /* Base address of UART1 */
#define MCFUART_BASE2 0x200 /* Base address of UART2 */
#endif
#endif
/*
* Define the ColdFire UART register set addresses.
*/
#define MCFUART_UMR 0x00 /* Mode register (r/w) */
#define MCFUART_USR 0x04 /* Status register (r) */
#define MCFUART_UCSR 0x04 /* Clock Select (w) */
#define MCFUART_UCR 0x08 /* Command register (w) */
#define MCFUART_URB 0x0c /* Receiver Buffer (r) */
#define MCFUART_UTB 0x0c /* Transmit Buffer (w) */
#define MCFUART_UIPCR 0x10 /* Input Port Change (r) */
#define MCFUART_UACR 0x10 /* Auxiliary Control (w) */
#define MCFUART_UISR 0x14 /* Interrup Status (r) */
#define MCFUART_UIMR 0x14 /* Interrupt Mask (w) */
#define MCFUART_UBG1 0x18 /* Baud Rate MSB (r/w) */
#define MCFUART_UBG2 0x1c /* Baud Rate LSB (r/w) */
#ifdef CONFIG_M5272
#define MCFUART_UTF 0x28 /* Transmitter FIFO (r/w) */
#define MCFUART_URF 0x2c /* Receiver FIFO (r/w) */
#define MCFUART_UFPD 0x30 /* Frac Prec. Divider (r/w) */
#else
#define MCFUART_UIVR 0x30 /* Interrupt Vector (r/w) */
#endif
#define MCFUART_UIPR 0x34 /* Input Port (r) */
#define MCFUART_UOP1 0x38 /* Output Port Bit Set (w) */
#define MCFUART_UOP0 0x3c /* Output Port Bit Reset (w) */
#ifdef CONFIG_M5249
/* Note: This isn't in the 5249 docs */
#define MCFUART_UFPD 0x30 /* Frac Prec. Divider (r/w) */
#endif
/*
* Define bit flags in Mode Register 1 (MR1).
*/
#define MCFUART_MR1_RXRTS 0x80 /* Auto RTS flow control */
#define MCFUART_MR1_RXIRQFULL 0x40 /* RX IRQ type FULL */
#define MCFUART_MR1_RXIRQRDY 0x00 /* RX IRQ type RDY */
#define MCFUART_MR1_RXERRBLOCK 0x20 /* RX block error mode */
#define MCFUART_MR1_RXERRCHAR 0x00 /* RX char error mode */
#define MCFUART_MR1_PARITYNONE 0x10 /* No parity */
#define MCFUART_MR1_PARITYEVEN 0x00 /* Even parity */
#define MCFUART_MR1_PARITYODD 0x04 /* Odd parity */
#define MCFUART_MR1_PARITYSPACE 0x08 /* Space parity */
#define MCFUART_MR1_PARITYMARK 0x0c /* Mark parity */
#define MCFUART_MR1_CS5 0x00 /* 5 bits per char */
#define MCFUART_MR1_CS6 0x01 /* 6 bits per char */
#define MCFUART_MR1_CS7 0x02 /* 7 bits per char */
#define MCFUART_MR1_CS8 0x03 /* 8 bits per char */
/*
* Define bit flags in Mode Register 2 (MR2).
*/
#define MCFUART_MR2_LOOPBACK 0x80 /* Loopback mode */
#define MCFUART_MR2_REMOTELOOP 0xc0 /* Remote loopback mode */
#define MCFUART_MR2_AUTOECHO 0x40 /* Automatic echo */
#define MCFUART_MR2_TXRTS 0x20 /* Assert RTS on TX */
#define MCFUART_MR2_TXCTS 0x10 /* Auto CTS flow control */
#define MCFUART_MR2_STOP1 0x07 /* 1 stop bit */
#define MCFUART_MR2_STOP15 0x08 /* 1.5 stop bits */
#define MCFUART_MR2_STOP2 0x0f /* 2 stop bits */
/*
* Define bit flags in Status Register (USR).
*/
#define MCFUART_USR_RXBREAK 0x80 /* Received BREAK */
#define MCFUART_USR_RXFRAMING 0x40 /* Received framing error */
#define MCFUART_USR_RXPARITY 0x20 /* Received parity error */
#define MCFUART_USR_RXOVERRUN 0x10 /* Received overrun error */
#define MCFUART_USR_TXEMPTY 0x08 /* Transmitter empty */
#define MCFUART_USR_TXREADY 0x04 /* Transmitter ready */
#define MCFUART_USR_RXFULL 0x02 /* Receiver full */
#define MCFUART_USR_RXREADY 0x01 /* Receiver ready */
#define MCFUART_USR_RXERR (MCFUART_USR_RXBREAK | MCFUART_USR_RXFRAMING | \
MCFUART_USR_RXPARITY | MCFUART_USR_RXOVERRUN)
/*
* Define bit flags in Clock Select Register (UCSR).
*/
#define MCFUART_UCSR_RXCLKTIMER 0xd0 /* RX clock is timer */
#define MCFUART_UCSR_RXCLKEXT16 0xe0 /* RX clock is external x16 */
#define MCFUART_UCSR_RXCLKEXT1 0xf0 /* RX clock is external x1 */
#define MCFUART_UCSR_TXCLKTIMER 0x0d /* TX clock is timer */
#define MCFUART_UCSR_TXCLKEXT16 0x0e /* TX clock is external x16 */
#define MCFUART_UCSR_TXCLKEXT1 0x0f /* TX clock is external x1 */
/*
* Define bit flags in Command Register (UCR).
*/
#define MCFUART_UCR_CMDNULL 0x00 /* No command */
#define MCFUART_UCR_CMDRESETMRPTR 0x10 /* Reset MR pointer */
#define MCFUART_UCR_CMDRESETRX 0x20 /* Reset receiver */
#define MCFUART_UCR_CMDRESETTX 0x30 /* Reset transmitter */
#define MCFUART_UCR_CMDRESETERR 0x40 /* Reset error status */
#define MCFUART_UCR_CMDRESETBREAK 0x50 /* Reset BREAK change */
#define MCFUART_UCR_CMDBREAKSTART 0x60 /* Start BREAK */
#define MCFUART_UCR_CMDBREAKSTOP 0x70 /* Stop BREAK */
#define MCFUART_UCR_TXNULL 0x00 /* No TX command */
#define MCFUART_UCR_TXENABLE 0x04 /* Enable TX */
#define MCFUART_UCR_TXDISABLE 0x08 /* Disable TX */
#define MCFUART_UCR_RXNULL 0x00 /* No RX command */
#define MCFUART_UCR_RXENABLE 0x01 /* Enable RX */
#define MCFUART_UCR_RXDISABLE 0x02 /* Disable RX */
/*
* Define bit flags in Input Port Change Register (UIPCR).
*/
#define MCFUART_UIPCR_CTSCOS 0x10 /* CTS change of state */
#define MCFUART_UIPCR_CTS 0x01 /* CTS value */
/*
* Define bit flags in Input Port Register (UIP).
*/
#define MCFUART_UIPR_CTS 0x01 /* CTS value */
/*
* Define bit flags in Output Port Registers (UOP).
* Clear bit by writing to UOP0, set by writing to UOP1.
*/
#define MCFUART_UOP_RTS 0x01 /* RTS set or clear */
/*
* Define bit flags in the Auxiliary Control Register (UACR).
*/
#define MCFUART_UACR_IEC 0x01 /* Input enable control */
/*
* Define bit flags in Interrupt Status Register (UISR).
* These same bits are used for the Interrupt Mask Register (UIMR).
*/
#define MCFUART_UIR_COS 0x80 /* Change of state (CTS) */
#define MCFUART_UIR_DELTABREAK 0x04 /* Break start or stop */
#define MCFUART_UIR_RXREADY 0x02 /* Receiver ready */
#define MCFUART_UIR_TXREADY 0x01 /* Transmitter ready */
#ifdef CONFIG_M5272
/*
* Define bit flags in the Transmitter FIFO Register (UTF).
*/
#define MCFUART_UTF_TXB 0x1f /* transmitter data level */
#define MCFUART_UTF_FULL 0x20 /* transmitter fifo full */
#define MCFUART_UTF_TXS 0xc0 /* transmitter status */
/*
* Define bit flags in the Receiver FIFO Register (URF).
*/
#define MCFUART_URF_RXB 0x1f /* receiver data level */
#define MCFUART_URF_FULL 0x20 /* receiver fifo full */
#define MCFUART_URF_RXS 0xc0 /* receiver status */
#endif
/****************************************************************************/
#endif /* mcfuart_h */

44
include/asm-m68k/ptrace.h
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@@ -28,32 +28,32 @@
#ifndef __ASSEMBLY__
struct pt_regs {
ulong d0;
ulong d1;
ulong d2;
ulong d3;
ulong d4;
ulong d5;
ulong d6;
ulong d7;
ulong a0;
ulong a1;
ulong a2;
ulong a3;
ulong a4;
ulong a5;
ulong a6;
#if defined(CONFIG_M5272) || defined(CONFIG_M5282) || defined(CONFIG_M5249) || defined(CONFIG_M5271)
unsigned format : 4; /* frame format specifier */
unsigned vector : 12; /* vector offset */
ulong d0;
ulong d1;
ulong d2;
ulong d3;
ulong d4;
ulong d5;
ulong d6;
ulong d7;
ulong a0;
ulong a1;
ulong a2;
ulong a3;
ulong a4;
ulong a5;
ulong a6;
#if defined(__M68K__)
unsigned format:4; /* frame format specifier */
unsigned vector:12; /* vector offset */
unsigned short sr;
unsigned long pc;
unsigned long pc;
#else
unsigned short sr;
unsigned long pc;
unsigned long pc;
#endif
};
#endif /* #ifndef __ASSEMBLY__ */
#endif /* #ifndef __ASSEMBLY__ */
#endif /* #ifndef _M68K_PTRACE_H */
#endif /* #ifndef _M68K_PTRACE_H */

109
include/asm-m68k/rtc.h Normal file
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@@ -0,0 +1,109 @@
/*
* RealTime Clock
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __MCFRTC_H__
#define __MCFRTC_H__
/* Real time Clock */
typedef struct rtc_ctrl {
u32 hourmin; /* 0x00 Hours and Minutes Counter Register */
u32 seconds; /* 0x04 Seconds Counter Register */
u32 alrm_hm; /* 0x08 Hours and Minutes Alarm Register */
u32 alrm_sec; /* 0x0C Seconds Alarm Register */
u32 cr; /* 0x10 Control Register */
u32 isr; /* 0x14 Interrupt Status Register */
u32 ier; /* 0x18 Interrupt Enable Register */
u32 stpwatch; /* 0x1C Stopwatch Minutes Register */
u32 days; /* 0x20 Days Counter Register */
u32 alrm_day; /* 0x24 Days Alarm Register */
void *extended;
} rtc_t;
/* Bit definitions and macros for HOURMIN */
#define RTC_HOURMIN_MINUTES(x) (((x)&0x0000003F))
#define RTC_HOURMIN_HOURS(x) (((x)&0x0000001F)<<8)
/* Bit definitions and macros for SECONDS */
#define RTC_SECONDS_SECONDS(x) (((x)&0x0000003F))
/* Bit definitions and macros for ALRM_HM */
#define RTC_ALRM_HM_MINUTES(x) (((x)&0x0000003F))
#define RTC_ALRM_HM_HOURS(x) (((x)&0x0000001F)<<8)
/* Bit definitions and macros for ALRM_SEC */
#define RTC_ALRM_SEC_SECONDS(x) (((x)&0x0000003F))
/* Bit definitions and macros for CR */
#define RTC_CR_SWR (0x00000001)
#define RTC_CR_XTL(x) (((x)&0x00000003)<<5)
#define RTC_CR_EN (0x00000080)
#define RTC_CR_32768 (0x0)
#define RTC_CR_32000 (0x1)
#define RTC_CR_38400 (0x2)
/* Bit definitions and macros for ISR */
#define RTC_ISR_SW (0x00000001)
#define RTC_ISR_MIN (0x00000002)
#define RTC_ISR_ALM (0x00000004)
#define RTC_ISR_DAY (0x00000008)
#define RTC_ISR_1HZ (0x00000010)
#define RTC_ISR_HR (0x00000020)
#define RTC_ISR_2HZ (0x00000080)
#define RTC_ISR_SAM0 (0x00000100)
#define RTC_ISR_SAM1 (0x00000200)
#define RTC_ISR_SAM2 (0x00000400)
#define RTC_ISR_SAM3 (0x00000800)
#define RTC_ISR_SAM4 (0x00001000)
#define RTC_ISR_SAM5 (0x00002000)
#define RTC_ISR_SAM6 (0x00004000)
#define RTC_ISR_SAM7 (0x00008000)
/* Bit definitions and macros for IER */
#define RTC_IER_SW (0x00000001)
#define RTC_IER_MIN (0x00000002)
#define RTC_IER_ALM (0x00000004)
#define RTC_IER_DAY (0x00000008)
#define RTC_IER_1HZ (0x00000010)
#define RTC_IER_HR (0x00000020)
#define RTC_IER_2HZ (0x00000080)
#define RTC_IER_SAM0 (0x00000100)
#define RTC_IER_SAM1 (0x00000200)
#define RTC_IER_SAM2 (0x00000400)
#define RTC_IER_SAM3 (0x00000800)
#define RTC_IER_SAM4 (0x00001000)
#define RTC_IER_SAM5 (0x00002000)
#define RTC_IER_SAM6 (0x00004000)
#define RTC_IER_SAM7 (0x00008000)
/* Bit definitions and macros for STPWCH */
#define RTC_STPWCH_CNT(x) (((x)&0x0000003F))
/* Bit definitions and macros for DAYS */
#define RTC_DAYS_DAYS(x) (((x)&0x0000FFFF))
/* Bit definitions and macros for ALRM_DAY */
#define RTC_ALRM_DAY_DAYS(x) (((x)&0x0000FFFF))
#endif /* __MCFRTC_H__ */

118
include/asm-m68k/timer.h Normal file
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@@ -0,0 +1,118 @@
/*
* timer.h -- ColdFire internal TIMER support defines.
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/****************************************************************************/
#ifndef timer_h
#define timer_h
/****************************************************************************/
/****************************************************************************/
/* Timer structure */
/****************************************************************************/
/* DMA Timer module registers */
typedef struct dtimer_ctrl {
#if defined(CONFIG_M5249) || defined(CONFIG_M5253)
u16 tmr; /* 0x00 Mode register */
u16 res1; /* 0x02 */
u16 trr; /* 0x04 Reference register */
u16 res2; /* 0x06 */
u16 tcr; /* 0x08 Capture register */
u16 res3; /* 0x0A */
u16 tcn; /* 0x0C Counter register */
u16 res4; /* 0x0E */
u8 res6; /* 0x10 */
u8 ter; /* 0x11 Event register */
u16 res7; /* 0x12 */
#else
u16 tmr; /* 0x00 Mode register */
u8 txmr; /* 0x02 Extended Mode register */
u8 ter; /* 0x03 Event register */
u32 trr; /* 0x04 Reference register */
u32 tcr; /* 0x08 Capture register */
u32 tcn; /* 0x0C Counter register */
#endif
} dtmr_t;
/*Programmable Interrupt Timer */
typedef struct pit_ctrl {
u16 pcsr; /* 0x00 Control and Status Register */
u16 pmr; /* 0x02 Modulus Register */
u16 pcntr; /* 0x04 Count Register */
} pit_t;
/*********************************************************************
* DMA Timers (DTIM)
*********************************************************************/
/* Bit definitions and macros for DTMR */
#define DTIM_DTMR_RST (0x0001) /* Reset */
#define DTIM_DTMR_CLK(x) (((x)&0x0003)<<1) /* Input clock source */
#define DTIM_DTMR_FRR (0x0008) /* Free run/restart */
#define DTIM_DTMR_ORRI (0x0010) /* Output reference request/interrupt enable */
#define DTIM_DTMR_OM (0x0020) /* Output Mode */
#define DTIM_DTMR_CE(x) (((x)&0x0003)<<6) /* Capture Edge */
#define DTIM_DTMR_PS(x) (((x)&0x00FF)<<8) /* Prescaler value */
#define DTIM_DTMR_RST_EN (0x0001)
#define DTIM_DTMR_RST_RST (0x0000)
#define DTIM_DTMR_CE_ANY (0x00C0)
#define DTIM_DTMR_CE_FALL (0x0080)
#define DTIM_DTMR_CE_RISE (0x0040)
#define DTIM_DTMR_CE_NONE (0x0000)
#define DTIM_DTMR_CLK_DTIN (0x0006)
#define DTIM_DTMR_CLK_DIV16 (0x0004)
#define DTIM_DTMR_CLK_DIV1 (0x0002)
#define DTIM_DTMR_CLK_STOP (0x0000)
/* Bit definitions and macros for DTXMR */
#define DTIM_DTXMR_MODE16 (0x01) /* Increment Mode */
#define DTIM_DTXMR_DMAEN (0x80) /* DMA request */
/* Bit definitions and macros for DTER */
#define DTIM_DTER_CAP (0x01) /* Capture event */
#define DTIM_DTER_REF (0x02) /* Output reference event */
/*********************************************************************
*
* Programmable Interrupt Timer Modules (PIT)
*
*********************************************************************/
/* Bit definitions and macros for PCSR */
#define PIT_PCSR_EN (0x0001)
#define PIT_PCSR_RLD (0x0002)
#define PIT_PCSR_PIF (0x0004)
#define PIT_PCSR_PIE (0x0008)
#define PIT_PCSR_OVW (0x0010)
#define PIT_PCSR_HALTED (0x0020)
#define PIT_PCSR_DOZE (0x0040)
#define PIT_PCSR_PRE(x) (((x)&0x000F)<<8)
/* Bit definitions and macros for PMR */
#define PIT_PMR_PM(x) (x)
/* Bit definitions and macros for PCNTR */
#define PIT_PCNTR_PC(x) (x)
/****************************************************************************/
#endif /* timer_h */

56
include/asm-m68k/u-boot.h
View File

@@ -37,24 +37,44 @@
#ifndef __ASSEMBLY__
typedef struct bd_info {
unsigned long bi_memstart; /* start of DRAM memory */
unsigned long bi_memsize; /* size of DRAM memory in bytes */
unsigned long bi_flashstart; /* start of FLASH memory */
unsigned long bi_flashsize; /* size of FLASH memory */
unsigned long bi_flashoffset; /* reserved area for startup monitor */
unsigned long bi_sramstart; /* start of SRAM memory */
unsigned long bi_sramsize; /* size of SRAM memory */
unsigned long bi_mbar_base; /* base of internal registers */
unsigned long bi_bootflags; /* boot / reboot flag (for LynxOS) */
unsigned long bi_boot_params; /* where this board expects params */
unsigned long bi_ip_addr; /* IP Address */
unsigned char bi_enetaddr[6]; /* Ethernet adress */
unsigned short bi_ethspeed; /* Ethernet speed in Mbps */
unsigned long bi_intfreq; /* Internal Freq, in MHz */
unsigned long bi_busfreq; /* Bus Freq, in MHz */
unsigned long bi_baudrate; /* Console Baudrate */
unsigned long bi_memstart; /* start of DRAM memory */
unsigned long bi_memsize; /* size of DRAM memory in bytes */
unsigned long bi_flashstart; /* start of FLASH memory */
unsigned long bi_flashsize; /* size of FLASH memory */
unsigned long bi_flashoffset; /* reserved area for startup monitor */
unsigned long bi_sramstart; /* start of SRAM memory */
unsigned long bi_sramsize; /* size of SRAM memory */
unsigned long bi_mbar_base; /* base of internal registers */
unsigned long bi_bootflags; /* boot / reboot flag (for LynxOS) */
unsigned long bi_boot_params; /* where this board expects params */
unsigned long bi_ip_addr; /* IP Address */
unsigned char bi_enetaddr[6]; /* Ethernet adress */
unsigned short bi_ethspeed; /* Ethernet speed in Mbps */
unsigned long bi_intfreq; /* Internal Freq, in MHz */
unsigned long bi_busfreq; /* Bus Freq, in MHz */
#ifdef CONFIG_PCI
unsigned long bi_pcifreq; /* pci Freq in MHz */
#endif
#ifdef CONFIG_EXTRA_CLOCK
unsigned long bi_inpfreq; /* input Freq in MHz */
unsigned long bi_vcofreq; /* vco Freq in MHz */
unsigned long bi_flbfreq; /* Flexbus Freq in MHz */
#endif
unsigned long bi_baudrate; /* Console Baudrate */
#ifdef CONFIG_HAS_ETH1
/* second onboard ethernet port */
unsigned char bi_enet1addr[6];
#endif
#ifdef CONFIG_HAS_ETH2
/* third onboard ethernet port */
unsigned char bi_enet2addr[6];
#endif
#ifdef CONFIG_HAS_ETH3
unsigned char bi_enet3addr[6];
#endif
} bd_t;
#endif /* __ASSEMBLY__ */
#endif /* __ASSEMBLY__ */
#endif /* __U_BOOT_H__ */
#endif /* __U_BOOT_H__ */

171
include/asm-m68k/uart.h Normal file
View File

@@ -0,0 +1,171 @@
/*
* uart.h -- ColdFire internal UART support defines.
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/****************************************************************************/
#ifndef uart_h
#define uart_h
/****************************************************************************/
/* UART module registers */
/* Register read/write struct */
typedef struct uart {
u8 umr; /* 0x00 Mode Register */
u8 resv0[0x3];
union {
u8 usr; /* 0x04 Status Register */
u8 ucsr; /* 0x04 Clock Select Register */
};
u8 resv1[0x3];
u8 ucr; /* 0x08 Command Register */
u8 resv2[0x3];
union {
u8 utb; /* 0x0c Transmit Buffer */
u8 urb; /* 0x0c Receive Buffer */
};
u8 resv3[0x3];
union {
u8 uipcr; /* 0x10 Input Port Change Register */
u8 uacr; /* 0x10 Auxiliary Control reg */
};
u8 resv4[0x3];
union {
u8 uimr; /* 0x14 Interrupt Mask reg */
u8 uisr; /* 0x14 Interrupt Status reg */
};
u8 resv5[0x3];
u8 ubg1; /* 0x18 Counter Timer Upper Register */
u8 resv6[0x3];
u8 ubg2; /* 0x1c Counter Timer Lower Register */
u8 resv7[0x17];
u8 uip; /* 0x34 Input Port Register */
u8 resv8[0x3];
u8 uop1; /* 0x38 Output Port Set Register */
u8 resv9[0x3];
u8 uop0; /* 0x3c Output Port Reset Register */
} uart_t;
/*********************************************************************
* Universal Asynchronous Receiver Transmitter (UART)
*********************************************************************/
/* Bit definitions and macros for UMR */
#define UART_UMR_BC(x) (((x)&0x03))
#define UART_UMR_PT (0x04)
#define UART_UMR_PM(x) (((x)&0x03)<<3)
#define UART_UMR_ERR (0x20)
#define UART_UMR_RXIRQ (0x40)
#define UART_UMR_RXRTS (0x80)
#define UART_UMR_SB(x) (((x)&0x0F))
#define UART_UMR_TXCTS (0x10) /* Trsnsmit CTS */
#define UART_UMR_TXRTS (0x20) /* Transmit RTS */
#define UART_UMR_CM(x) (((x)&0x03)<<6) /* CM bits */
#define UART_UMR_PM_MULTI_ADDR (0x1C)
#define UART_UMR_PM_MULTI_DATA (0x18)
#define UART_UMR_PM_NONE (0x10)
#define UART_UMR_PM_FORCE_HI (0x0C)
#define UART_UMR_PM_FORCE_LO (0x08)
#define UART_UMR_PM_ODD (0x04)
#define UART_UMR_PM_EVEN (0x00)
#define UART_UMR_BC_5 (0x00)
#define UART_UMR_BC_6 (0x01)
#define UART_UMR_BC_7 (0x02)
#define UART_UMR_BC_8 (0x03)
#define UART_UMR_CM_NORMAL (0x00)
#define UART_UMR_CM_ECH (0x40)
#define UART_UMR_CM_LOCAL_LOOP (0x80)
#define UART_UMR_CM_REMOTE_LOOP (0xC0)
#define UART_UMR_SB_STOP_BITS_1 (0x07)
#define UART_UMR_SB_STOP_BITS_15 (0x08)
#define UART_UMR_SB_STOP_BITS_2 (0x0F)
/* Bit definitions and macros for USR */
#define UART_USR_RXRDY (0x01)
#define UART_USR_FFULL (0x02)
#define UART_USR_TXRDY (0x04)
#define UART_USR_TXEMP (0x08)
#define UART_USR_OE (0x10)
#define UART_USR_PE (0x20)
#define UART_USR_FE (0x40)
#define UART_USR_RB (0x80)
/* Bit definitions and macros for UCSR */
#define UART_UCSR_TCS(x) (((x)&0x0F))
#define UART_UCSR_RCS(x) (((x)&0x0F)<<4)
#define UART_UCSR_RCS_SYS_CLK (0xD0)
#define UART_UCSR_RCS_CTM16 (0xE0)
#define UART_UCSR_RCS_CTM (0xF0)
#define UART_UCSR_TCS_SYS_CLK (0x0D)
#define UART_UCSR_TCS_CTM16 (0x0E)
#define UART_UCSR_TCS_CTM (0x0F)
/* Bit definitions and macros for UCR */
#define UART_UCR_RXC(x) (((x)&0x03))
#define UART_UCR_TXC(x) (((x)&0x03)<<2)
#define UART_UCR_MISC(x) (((x)&0x07)<<4)
#define UART_UCR_NONE (0x00)
#define UART_UCR_STOP_BREAK (0x70)
#define UART_UCR_START_BREAK (0x60)
#define UART_UCR_BKCHGINT (0x50)
#define UART_UCR_RESET_ERROR (0x40)
#define UART_UCR_RESET_TX (0x30)
#define UART_UCR_RESET_RX (0x20)
#define UART_UCR_RESET_MR (0x10)
#define UART_UCR_TX_DISABLED (0x08)
#define UART_UCR_TX_ENABLED (0x04)
#define UART_UCR_RX_DISABLED (0x02)
#define UART_UCR_RX_ENABLED (0x01)
/* Bit definitions and macros for UIPCR */
#define UART_UIPCR_CTS (0x01)
#define UART_UIPCR_COS (0x10)
/* Bit definitions and macros for UACR */
#define UART_UACR_IEC (0x01)
/* Bit definitions and macros for UIMR */
#define UART_UIMR_TXRDY (0x01)
#define UART_UIMR_RXRDY_FU (0x02)
#define UART_UIMR_DB (0x04)
#define UART_UIMR_COS (0x80)
/* Bit definitions and macros for UISR */
#define UART_UISR_TXRDY (0x01)
#define UART_UISR_RXRDY_FU (0x02)
#define UART_UISR_DB (0x04)
#define UART_UISR_RXFTO (0x08)
#define UART_UISR_TXFIFO (0x10)
#define UART_UISR_RXFIFO (0x20)
#define UART_UISR_COS (0x80)
/* Bit definitions and macros for UIP */
#define UART_UIP_CTS (0x01)
/* Bit definitions and macros for UOP1 */
#define UART_UOP1_RTS (0x01)
/* Bit definitions and macros for UOP0 */
#define UART_UOP0_RTS (0x01)
/****************************************************************************/
#endif /* mcfuart_h */

156
include/asm-mips/string.h
View File

@@ -1,126 +1,31 @@
/* $Id: string.h,v 1.13 2000/02/19 14:12:14 harald Exp $
*
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (c) 1994, 1995, 1996, 1997, 1998 by Ralf Baechle
* Copyright (c) 1994, 95, 96, 97, 98, 2000, 01 Ralf Baechle
* Copyright (c) 2000 by Silicon Graphics, Inc.
* Copyright (c) 2001 MIPS Technologies, Inc.
*/
#ifndef __ASM_MIPS_STRING_H
#define __ASM_MIPS_STRING_H
#ifndef _ASM_STRING_H
#define _ASM_STRING_H
#include <linux/config.h>
/*
* We don't do inline string functions, since the
* optimised inline asm versions are not small.
*/
#define __HAVE_ARCH_STRCPY
extern __inline__ char *strcpy(char *__dest, __const__ char *__src)
{
char *__xdest = __dest;
#undef __HAVE_ARCH_STRCPY
extern char *strcpy(char *__dest, __const__ char *__src);
__asm__ __volatile__(
".set\tnoreorder\n\t"
".set\tnoat\n"
"1:\tlbu\t$1,(%1)\n\t"
"addiu\t%1,1\n\t"
"sb\t$1,(%0)\n\t"
"bnez\t$1,1b\n\t"
"addiu\t%0,1\n\t"
".set\tat\n\t"
".set\treorder"
: "=r" (__dest), "=r" (__src)
: "0" (__dest), "1" (__src)
: "$1","memory");
#undef __HAVE_ARCH_STRNCPY
extern char *strncpy(char *__dest, __const__ char *__src, size_t __n);
return __xdest;
}
#undef __HAVE_ARCH_STRCMP
extern int strcmp(__const__ char *__cs, __const__ char *__ct);
#define __HAVE_ARCH_STRNCPY
extern __inline__ char *strncpy(char *__dest, __const__ char *__src, size_t __n)
{
char *__xdest = __dest;
if (__n == 0)
return __xdest;
__asm__ __volatile__(
".set\tnoreorder\n\t"
".set\tnoat\n"
"1:\tlbu\t$1,(%1)\n\t"
"subu\t%2,1\n\t"
"sb\t$1,(%0)\n\t"
"beqz\t$1,2f\n\t"
"addiu\t%0,1\n\t"
"bnez\t%2,1b\n\t"
"addiu\t%1,1\n"
"2:\n\t"
".set\tat\n\t"
".set\treorder"
: "=r" (__dest), "=r" (__src), "=r" (__n)
: "0" (__dest), "1" (__src), "2" (__n)
: "$1","memory");
return __dest;
}
#define __HAVE_ARCH_STRCMP
extern __inline__ int strcmp(__const__ char *__cs, __const__ char *__ct)
{
int __res;
__asm__ __volatile__(
".set\tnoreorder\n\t"
".set\tnoat\n\t"
"lbu\t%2,(%0)\n"
"1:\tlbu\t$1,(%1)\n\t"
"addiu\t%0,1\n\t"
"bne\t$1,%2,2f\n\t"
"addiu\t%1,1\n\t"
"bnez\t%2,1b\n\t"
"lbu\t%2,(%0)\n\t"
#if defined(CONFIG_CPU_R3000)
"nop\n\t"
#endif
"move\t%2,$1\n"
"2:\tsubu\t%2,$1\n"
"3:\t.set\tat\n\t"
".set\treorder"
: "=r" (__cs), "=r" (__ct), "=r" (__res)
: "0" (__cs), "1" (__ct)
: "$1");
return __res;
}
#define __HAVE_ARCH_STRNCMP
extern __inline__ int
strncmp(__const__ char *__cs, __const__ char *__ct, size_t __count)
{
int __res;
__asm__ __volatile__(
".set\tnoreorder\n\t"
".set\tnoat\n"
"1:\tlbu\t%3,(%0)\n\t"
"beqz\t%2,2f\n\t"
"lbu\t$1,(%1)\n\t"
"subu\t%2,1\n\t"
"bne\t$1,%3,3f\n\t"
"addiu\t%0,1\n\t"
"bnez\t%3,1b\n\t"
"addiu\t%1,1\n"
"2:\n\t"
#if defined(CONFIG_CPU_R3000)
"nop\n\t"
#endif
"move\t%3,$1\n"
"3:\tsubu\t%3,$1\n\t"
".set\tat\n\t"
".set\treorder"
: "=r" (__cs), "=r" (__ct), "=r" (__count), "=r" (__res)
: "0" (__cs), "1" (__ct), "2" (__count)
: "$1");
return __res;
}
#undef __HAVE_ARCH_STRNCMP
extern int strncmp(__const__ char *__cs, __const__ char *__ct, size_t __count);
#undef __HAVE_ARCH_MEMSET
extern void *memset(void *__s, int __c, size_t __count);
@@ -131,27 +36,4 @@ extern void *memcpy(void *__to, __const__ void *__from, size_t __n);
#undef __HAVE_ARCH_MEMMOVE
extern void *memmove(void *__dest, __const__ void *__src, size_t __n);
/* Don't build bcopy at all ... */
#define __HAVE_ARCH_BCOPY
#define __HAVE_ARCH_MEMSCAN
extern __inline__ void *memscan(void *__addr, int __c, size_t __size)
{
char *__end = (char *)__addr + __size;
__asm__(".set\tpush\n\t"
".set\tnoat\n\t"
".set\treorder\n\t"
"1:\tbeq\t%0,%1,2f\n\t"
"addiu\t%0,1\n\t"
"lb\t$1,-1(%0)\n\t"
"bne\t$1,%4,1b\n"
"2:\t.set\tpop"
: "=r" (__addr), "=r" (__end)
: "0" (__addr), "1" (__end), "r" (__c)
: "$1");
return __addr;
}
#endif /* __ASM_MIPS_STRING_H */
#endif /* _ASM_STRING_H */

10
include/asm-ppc/global_data.h
View File

@@ -71,16 +71,16 @@ typedef struct global_data {
u32 lclk_clk;
u32 ddr_clk;
u32 pci_clk;
#if defined(CONFIG_MPC8360)
u32 ddr_sec_clk;
#endif /* CONFIG_MPC8360 */
#endif
#if defined(CONFIG_QE)
u32 qe_clk;
u32 brg_clk;
uint mp_alloc_base;
uint mp_alloc_top;
#endif /* CONFIG_QE */
#if defined (CONFIG_MPC8360)
u32 ddr_sec_clk;
#endif /* CONFIG_MPC8360 */
#endif
#if defined(CONFIG_MPC5xxx)
unsigned long ipb_clk;
unsigned long pci_clk;
@@ -133,7 +133,7 @@ typedef struct global_data {
unsigned long do_mdm_init;
unsigned long be_quiet;
#endif
#ifdef CONFIG_LWMON
#if defined(CONFIG_LWMON) || defined(CONFIG_LWMON5)
unsigned long kbd_status;
#endif
void **jt; /* jump table */

54
include/asm-ppc/immap_85xx.h
View File

@@ -1,6 +1,8 @@
/*
* MPC85xx Internal Memory Map
*
* Copyright 2007 Freescale Semiconductor.
*
* Copyright(c) 2002,2003 Motorola Inc.
* Xianghua Xiao (x.xiao@motorola.com)
*
@@ -1520,14 +1522,39 @@ typedef struct ccsr_rio {
char res58[60176];
} ccsr_rio_t;
/* Quick Engine Block Pin Muxing Registers (0xe_0100 - 0xe_01bf) */
typedef struct par_io {
uint cpodr; /* 0x100 */
uint cpdat; /* 0x104 */
uint cpdir1; /* 0x108 */
uint cpdir2; /* 0x10c */
uint cppar1; /* 0x110 */
uint cppar2; /* 0x114 */
char res[8];
}par_io_t;
/*
* Global Utilities Register Block(0xe_0000-0xf_ffff)
*/
typedef struct ccsr_gur {
uint porpllsr; /* 0xe0000 - POR PLL ratio status register */
uint porbmsr; /* 0xe0004 - POR boot mode status register */
#define MPC85xx_PORBMSR_HA 0x00070000
uint porimpscr; /* 0xe0008 - POR I/O impedance status and control register */
uint pordevsr; /* 0xe000c - POR I/O device status regsiter */
#define MPC85xx_PORDEVSR_SGMII1_DIS 0x20000000
#define MPC85xx_PORDEVSR_SGMII2_DIS 0x10000000
#define MPC85xx_PORDEVSR_SGMII3_DIS 0x08000000
#define MPC85xx_PORDEVSR_SGMII4_DIS 0x04000000
#define MPC85xx_PORDEVSR_IO_SEL 0x00380000
#define MPC85xx_PORDEVSR_PCI2_ARB 0x00040000
#define MPC85xx_PORDEVSR_PCI1_ARB 0x00020000
#define MPC85xx_PORDEVSR_PCI1_PCI32 0x00010000
#define MPC85xx_PORDEVSR_PCI1_SPD 0x00008000
#define MPC85xx_PORDEVSR_PCI2_SPD 0x00004000
#define MPC85xx_PORDEVSR_DRAM_RTYPE 0x00000060
#define MPC85xx_PORDEVSR_RIO_CTLS 0x00000008
#define MPC85xx_PORDEVSR_RIO_DEV_ID 0x00000007
uint pordbgmsr; /* 0xe0010 - POR debug mode status register */
char res1[12];
uint gpporcr; /* 0xe0020 - General-purpose POR configuration register */
@@ -1541,6 +1568,25 @@ typedef struct ccsr_gur {
uint pmuxcr; /* 0xe0060 - Alternate function signal multiplex control */
char res6[12];
uint devdisr; /* 0xe0070 - Device disable control */
#define MPC85xx_DEVDISR_PCI1 0x80000000
#define MPC85xx_DEVDISR_PCI2 0x40000000
#define MPC85xx_DEVDISR_PCIE 0x20000000
#define MPC85xx_DEVDISR_LBC 0x08000000
#define MPC85xx_DEVDISR_PCIE2 0x04000000
#define MPC85xx_DEVDISR_PCIE3 0x02000000
#define MPC85xx_DEVDISR_SEC 0x01000000
#define MPC85xx_DEVDISR_SRIO 0x00080000
#define MPC85xx_DEVDISR_RMSG 0x00040000
#define MPC85xx_DEVDISR_DDR 0x00010000
#define MPC85xx_DEVDISR_CPU 0x00008000
#define MPC85xx_DEVDISR_TB 0x00004000
#define MPC85xx_DEVDISR_DMA 0x00000400
#define MPC85xx_DEVDISR_TSEC1 0x00000080
#define MPC85xx_DEVDISR_TSEC2 0x00000040
#define MPC85xx_DEVDISR_TSEC3 0x00000020
#define MPC85xx_DEVDISR_TSEC4 0x00000010
#define MPC85xx_DEVDISR_I2C 0x00000004
#define MPC85xx_DEVDISR_DUART 0x00000002
char res7[12];
uint powmgtcsr; /* 0xe0080 - Power management status and control register */
char res8[12];
@@ -1550,7 +1596,13 @@ typedef struct ccsr_gur {
uint svr; /* 0xe00a4 - System version register */
char res10a[8];
uint rstcr; /* 0xe00b0 - Reset control register */
#ifdef CONFIG_MPC8568
char res10b[76];
par_io_t qe_par_io[7]; /* 0xe0100 - 0xe01bf */
char res10c[3136];
#else
char res10b[3404];
#endif
uint clkocr; /* 0xe0e00 - Clock out select register */
char res11[12];
uint ddrdllcr; /* 0xe0e10 - DDR DLL control register */
@@ -1562,7 +1614,7 @@ typedef struct ccsr_gur {
uint ddrioovcr; /* 0xe0f24 - DDR IO Override Control */
uint res14; /* 0xe0f28 */
uint tsec34ioovcr; /* 0xe0f2c - eTSEC 3/4 IO override control */
char res15[61651];
char res15[61648]; /* 0xe0f30 to 0xefffff */
} ccsr_gur_t;
#define PORDEVSR_PCI (0x00800000) /* PCI Mode */

16
include/asm-ppc/immap_86xx.h
View File

@@ -1257,9 +1257,12 @@ typedef struct ccsr_gur {
uint porpllsr; /* 0xe0000 - POR PLL ratio status register */
uint porbmsr; /* 0xe0004 - POR boot mode status register */
#define MPC86xx_PORBMSR_HA 0x00060000
#define MPC85xx_PORBMSR_HA 0x00070000
uint porimpscr; /* 0xe0008 - POR I/O impedance status and control register */
uint pordevsr; /* 0xe000c - POR I/O device status regsiter */
#define MPC86xx_PORDEVSR_IO_SEL 0x000F0000
#define MPC86xx_PORDEVSR_IO_SEL 0x000F0000
#define MPC85xx_PORDEVSR_IO_SEL 0x00380000 /* 85xx platform type */
#define MPC86xx_PORDEVSR_CORE1TE 0x00000080 /* ASMP (Core1 addr trans) */
uint pordbgmsr; /* 0xe0010 - POR debug mode status register */
char res1[12];
uint gpporcr; /* 0xe0020 - General-purpose POR configuration register */
@@ -1273,8 +1276,11 @@ typedef struct ccsr_gur {
uint pmuxcr; /* 0xe0060 - Alternate function signal multiplex control */
char res6[12];
uint devdisr; /* 0xe0070 - Device disable control */
#define MPC86xx_DEVDISR_PCIEX1 0x80000000
#define MPC86xx_DEVDISR_PCIEX2 0x40000000
#define MPC86xx_DEVDISR_PCIEX1 0x80000000
#define MPC86xx_DEVDISR_PCIEX2 0x40000000
#define MPC86xx_DEVDISR_PCI1 0x80000000
#define MPC86xx_DEVDISR_PCIE1 0x40000000
#define MPC86xx_DEVDISR_PCIE2 0x20000000
char res7[12];
uint powmgtcsr; /* 0xe0080 - Power management status and control register */
char res8[12];
@@ -1282,7 +1288,9 @@ typedef struct ccsr_gur {
char res9[12];
uint pvr; /* 0xe00a0 - Processor version register */
uint svr; /* 0xe00a4 - System version register */
char res10[3416];
char res10a[1880];
uint clkdvdr; /* 0xe0800 - Clock Divide register */
char res10b[1532];
uint clkocr; /* 0xe0e00 - Clock out select register */
char res11[12];
uint ddrdllcr; /* 0xe0e10 - DDR DLL control register */

20
include/asm-ppc/immap_qe.h
View File

@@ -281,6 +281,17 @@ typedef struct ucc_slow {
u8 res4[0x200 - 0x091];
} __attribute__ ((packed)) ucc_slow_t;
typedef struct ucc_mii_mng {
u32 miimcfg; /* MII management configuration reg */
u32 miimcom; /* MII management command reg */
u32 miimadd; /* MII management address reg */
u32 miimcon; /* MII management control reg */
u32 miimstat; /* MII management status reg */
u32 miimind; /* MII management indication reg */
u32 ifctl; /* interface control reg */
u32 ifstat; /* interface statux reg */
} __attribute__ ((packed))uec_mii_t;
typedef struct ucc_ethernet {
u32 maccfg1; /* mac configuration reg. 1 */
u32 maccfg2; /* mac configuration reg. 2 */
@@ -540,14 +551,21 @@ typedef struct qe_immap {
u8 res14[0x300];
u8 res15[0x3A00];
u8 res16[0x8000]; /* 0x108000 - 0x110000 */
#if defined(CONFIG_MPC8568)
u8 muram[0x10000]; /* 0x1_0000 - 0x2_0000 Multi-user RAM */
u8 res17[0x20000]; /* 0x2_0000 - 0x4_0000 */
#else
u8 muram[0xC000]; /* 0x110000 - 0x11C000 Multi-user RAM */
u8 res17[0x24000]; /* 0x11C000 - 0x140000 */
u8 res18[0xC0000]; /* 0x140000 - 0x200000 */
#endif
} __attribute__ ((packed)) qe_map_t;
extern qe_map_t *qe_immr;
#if defined(CONFIG_MPC8360)
#if defined(CONFIG_MPC8568)
#define QE_MURAM_SIZE 0x10000UL
#elif defined(CONFIG_MPC8360)
#define QE_MURAM_SIZE 0xc000UL
#elif defined(CONFIG_MPC832X)
#define QE_MURAM_SIZE 0x4000UL

3
include/asm-ppc/io.h
View File

@@ -13,6 +13,9 @@
#define SIO_CONFIG_RA 0x398
#define SIO_CONFIG_RD 0x399
#ifndef _IO_BASE
#define _IO_BASE 0
#endif
#define readb(addr) in_8((volatile u8 *)(addr))
#define writeb(b,addr) out_8((volatile u8 *)(addr), (b))

3
include/asm-ppc/mmu.h
View File

@@ -645,6 +645,9 @@ void mttlb3(unsigned long index, unsigned long value);
unsigned long mftlb1(unsigned long index);
unsigned long mftlb2(unsigned long index);
unsigned long mftlb3(unsigned long index);
void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value);
void remove_tlb(u32 vaddr, u32 size);
#endif /* __ASSEMBLY__ */
#endif /* CONFIG_440 */

8
include/asm-ppc/processor.h
View File

@@ -217,12 +217,14 @@
#define HID0_DPM (1<<20)
#define HID0_ICE (1<<HID0_ICE_SHIFT) /* Instruction Cache Enable */
#define HID0_DCE (1<<HID0_DCE_SHIFT) /* Data Cache Enable */
#define HID0_TBEN (1<<14) /* Time Base Enable */
#define HID0_ILOCK (1<<13) /* Instruction Cache Lock */
#define HID0_DLOCK (1<<HID0_DLOCK_SHIFT) /* Data Cache Lock */
#define HID0_ICFI (1<<11) /* Instr. Cache Flash Invalidate */
#define HID0_DCFI (1<<10) /* Data Cache Flash Invalidate */
#define HID0_DCI HID0_DCFI
#define HID0_SPD (1<<9) /* Speculative disable */
#define HID0_ENMAS7 (1<<7) /* Enable MAS7 Update for 36-bit phys */
#define HID0_SGE (1<<7) /* Store Gathering Enable */
#define HID0_SIED HID_SGE /* Serial Instr. Execution [Disable] */
#define HID0_DCFA (1<<6) /* Data Cache Flush Assist */
@@ -450,6 +452,7 @@
#define SPRN_PID1 0x279 /* Process ID Register 1 */
#define SPRN_PID2 0x27a /* Process ID Register 2 */
#define SPRN_MCSR 0x23c /* Machine Check Syndrome register */
#define SPRN_MCAR 0x23d /* Machine Check Address register */
#ifdef CONFIG_440
#define MCSR_MCS 0x80000000 /* Machine Check Summary */
#define MCSR_IB 0x40000000 /* Instruction PLB Error */
@@ -464,7 +467,8 @@
#define ESR_ST 0x00800000 /* Store Operation */
#if defined(CONFIG_MPC86xx)
#define SPRN_MSSCRO 0x3f6
#define SPRN_MSSCR0 0x3f6
#define SPRN_MSSSR0 0x3f7
#endif
@@ -531,7 +535,7 @@
#define LR SPRN_LR
#define MBAR SPRN_MBAR /* System memory base address */
#if defined(CONFIG_MPC86xx)
#define MSSCR0 SPRN_MSSCRO
#define MSSCR0 SPRN_MSSCR0
#endif
#if defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
#define PIR SPRN_PIR

69
include/at45.h Normal file
View File

@@ -0,0 +1,69 @@
#ifndef _AT45_H_
#define _AT45_H_
#ifdef DATAFLASH_MMC_SELECT
extern void AT91F_SelectMMC(void);
extern void AT91F_SelectSPI(void);
extern int AT91F_GetMuxStatus(void);
#endif
extern void AT91F_SpiInit(void);
extern void AT91F_SpiEnable(int cs);
extern unsigned int AT91F_SpiWrite ( AT91PS_DataflashDesc pDesc );
extern AT91S_DataFlashStatus AT91F_DataFlashSendCommand(
AT91PS_DataFlash pDataFlash,
unsigned char OpCode,
unsigned int CmdSize,
unsigned int DataflashAddress);
extern AT91S_DataFlashStatus AT91F_DataFlashGetStatus (
AT91PS_DataflashDesc pDesc);
extern AT91S_DataFlashStatus AT91F_DataFlashWaitReady (
AT91PS_DataflashDesc pDataFlashDesc,
unsigned int timeout);
extern AT91S_DataFlashStatus AT91F_DataFlashContinuousRead (
AT91PS_DataFlash pDataFlash,
int src,
unsigned char *dataBuffer,
int sizeToRead );
extern AT91S_DataFlashStatus AT91F_DataFlashPagePgmBuf(
AT91PS_DataFlash pDataFlash,
unsigned char *src,
unsigned int dest,
unsigned int SizeToWrite);
extern AT91S_DataFlashStatus AT91F_MainMemoryToBufferTransfert(
AT91PS_DataFlash pDataFlash,
unsigned char BufferCommand,
unsigned int page);
extern AT91S_DataFlashStatus AT91F_DataFlashWriteBuffer (
AT91PS_DataFlash pDataFlash,
unsigned char BufferCommand,
unsigned char *dataBuffer,
unsigned int bufferAddress,
int SizeToWrite );
extern AT91S_DataFlashStatus AT91F_PageErase(
AT91PS_DataFlash pDataFlash,
unsigned int page);
extern AT91S_DataFlashStatus AT91F_BlockErase(
AT91PS_DataFlash pDataFlash,
unsigned int block);
extern AT91S_DataFlashStatus AT91F_WriteBufferToMain (
AT91PS_DataFlash pDataFlash,
unsigned char BufferCommand,
unsigned int dest );
extern AT91S_DataFlashStatus AT91F_PartialPageWrite (
AT91PS_DataFlash pDataFlash,
unsigned char *src,
unsigned int dest,
unsigned int size);
extern AT91S_DataFlashStatus AT91F_DataFlashWrite(
AT91PS_DataFlash pDataFlash,
unsigned char *src,
int dest,
int size );
extern int AT91F_DataFlashRead(
AT91PS_DataFlash pDataFlash,
unsigned long addr,
unsigned long size,
char *buffer);
extern int AT91F_DataflashProbe(int cs, AT91PS_DataflashDesc pDesc);
#endif

9
include/common.h
View File

@@ -275,7 +275,7 @@ void pciinfo (int, int);
# endif
int is_pci_host (struct pci_controller *);
#if defined(CONFIG_440SPE)
void pcie_setup_hoses(void);
void pcie_setup_hoses(int busno);
#endif
#endif
@@ -434,6 +434,13 @@ int checkdcache (void);
void upmconfig (unsigned int, unsigned int *, unsigned int);
ulong get_tbclk (void);
void reset_cpu (ulong addr);
#if defined (CONFIG_OF_LIBFDT) && defined (CONFIG_OF_BOARD_SETUP)
void ft_cpu_setup(void *blob, bd_t *bd);
#ifdef CONFIG_PCI
void ft_pci_setup(void *blob, bd_t *bd);
#endif
#endif
/* $(CPU)/serial.c */
int serial_init (void);

1
include/config_cmd_all.h
View File

@@ -76,5 +76,6 @@
#define CONFIG_CMD_USB /* USB Support */
#define CONFIG_CMD_VFD /* VFD support (TRAB) */
#define CONFIG_CMD_XIMG /* Load part of Multi Image */
#define CONFIG_CMD_MUX /* AT91 MMC/SPI Mux Support */
#endif /* _CONFIG_CMD_ALL_H */

46
include/configs/ASH405.h
View File

@@ -53,9 +53,13 @@
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_NET_MULTI 1
#undef CONFIG_HAS_ETH1
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
@@ -144,40 +148,18 @@
* NAND-FLASH stuff
*-----------------------------------------------------------------------
*/
#define CFG_NAND_BASE_LIST { CFG_NAND_BASE }
#define NAND_MAX_CHIPS 1
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define NAND_BIG_DELAY_US 25
#define CFG_NAND_LEGACY
#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define SECTORSIZE 512
#define ADDR_COLUMN 1
#define ADDR_PAGE 2
#define ADDR_COLUMN_PAGE 3
#define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1
#define NAND_MAX_CHIPS 1
#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
#define CONFIG_MTD_NAND_VERIFY_WRITE 1 /* verify all writes!!! */
#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
#define CFG_NAND_QUIET 1
/*-----------------------------------------------------------------------
* PCI stuff

2
include/configs/CATcenter.h
View File

@@ -399,6 +399,8 @@
#define CFG_ENV_ADDR_REDUND 0xFFFFA000
#define CFG_ENV_SIZE_REDUND 0x2000
#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
#define CFG_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */
#define CFG_NVRAM_SIZE 242 /* NVRAM size */

40
include/configs/CMS700.h
View File

@@ -90,8 +90,6 @@
#define CONFIG_CMD_EEPROM
#define CFG_NAND_LEGACY
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
@@ -157,36 +155,18 @@
* NAND-FLASH stuff
*-----------------------------------------------------------------------
*/
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define SECTORSIZE 512
#define CFG_NAND_BASE_LIST { CFG_NAND_BASE }
#define NAND_MAX_CHIPS 1
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define NAND_BIG_DELAY_US 25
#define ADDR_COLUMN 1
#define ADDR_PAGE 2
#define ADDR_COLUMN_PAGE 3
#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
#define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1
#define NAND_MAX_CHIPS 1
#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
#define CFG_NAND_QUIET 1
/*-----------------------------------------------------------------------
* PCI stuff

2
include/configs/CPCI405.h
View File

@@ -92,8 +92,6 @@
#define CONFIG_SUPPORT_VFAT
#define CFG_NAND_LEGACY
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */

2
include/configs/CPCI4052.h
View File

@@ -114,8 +114,6 @@
#define CONFIG_AUTO_UPDATE 1 /* autoupdate via compactflash */
#endif
#define CFG_NAND_LEGACY
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */

3
include/configs/CPCI405AB.h
View File

@@ -100,9 +100,6 @@
#define CONFIG_SUPPORT_VFAT
#define CFG_NAND_LEGACY
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */

2
include/configs/CPCI405DT.h
View File

@@ -111,8 +111,6 @@
#undef CONFIG_AUTO_UPDATE /* autoupdate via compactflash */
#define CFG_NAND_LEGACY
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */

41
include/configs/EB+MCF-EV123.h
View File

@@ -40,9 +40,8 @@
#define CONFIG_MISC_INIT_R
#define FEC_ENET
#define CONFIG_ETHADDR 00:CF:52:82:EB:01
#define CONFIG_MCFUART
#define CFG_UART_PORT (0)
#define CONFIG_BAUDRATE 9600
#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
@@ -84,7 +83,39 @@
#include <config_cmd_default.h>
#undef CONFIG_CMD_LOADB
#define CONFIG_CMD_MII
#define CONFIG_CMD_NET
#define CONFIG_MCFFEC
#ifdef CONFIG_MCFFEC
# define CONFIG_NET_MULTI 1
# define CONFIG_MII 1
# define CFG_DISCOVER_PHY
# define CFG_RX_ETH_BUFFER 8
# define CFG_FAULT_ECHO_LINK_DOWN
# define CFG_FEC0_PINMUX 0
# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE
# define MCFFEC_TOUT_LOOP 50000
/* If CFG_DISCOVER_PHY is not defined - hardcoded */
# ifndef CFG_DISCOVER_PHY
# define FECDUPLEX FULL
# define FECSPEED _100BASET
# else
# ifndef CFG_FAULT_ECHO_LINK_DOWN
# define CFG_FAULT_ECHO_LINK_DOWN
# endif
# endif /* CFG_DISCOVER_PHY */
#endif
#ifdef CONFIG_MCFFEC
# define CONFIG_ETHADDR 00:CF:52:82:EB:01
# define CONFIG_IPADDR 192.162.1.2
# define CONFIG_NETMASK 255.255.255.0
# define CONFIG_SERVERIP 192.162.1.1
# define CONFIG_GATEWAYIP 192.162.1.1
# define CONFIG_OVERWRITE_ETHADDR_ONCE
#endif /* CONFIG_MCFFEC */
#define CONFIG_BOOTDELAY 5
#define CFG_PROMPT "\nEV123 U-Boot> "
@@ -122,9 +153,6 @@
*/
#define CFG_MBAR 0x40000000
#define CFG_DISCOVER_PHY
/* #define CFG_ENET_BD_BASE 0x380000 */
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
@@ -151,6 +179,7 @@
#define CFG_FLASH_BASE 0xFFE00000
#define CFG_INT_FLASH_BASE 0xF0000000
#define CFG_INT_FLASH_ENABLE 0x21
/* If M5282 port is fully implemented the monitor base will be behind
* the vector table. */

1
include/configs/FADS823.h
View File

@@ -206,6 +206,7 @@
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_OFFSET 0x00040000 /* Offset of Environment Sector */
#define CFG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */
#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
/*-----------------------------------------------------------------------
* Cache Configuration

1
include/configs/FADS850SAR.h
View File

@@ -156,6 +156,7 @@
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_OFFSET 0x00040000 /* Offset of Environment Sector */
#define CFG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */
#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
/*-----------------------------------------------------------------------
* Cache Configuration

60
include/configs/FPS850L.h
View File

@@ -39,28 +39,44 @@
#undef CONFIG_8xx_CONS_SMC1
#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */
#undef CONFIG_8xx_CONS_NONE
#define CONFIG_BAUDRATE 19200
#if 0
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
#else
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#endif
#define CONFIG_BOOTCOMMAND "bootm 40020000" /* autoboot command */
#define CONFIG_BAUDRATE 115200
#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
#define CONFIG_BOOTCOUNT_LIMIT
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#define CONFIG_BOARD_TYPES 1 /* support board types */
#define CONFIG_BOOTARGS "root=/dev/nfs rw " \
"nfsroot=10.0.0.2:/opt/eldk/ppc_8xx " \
"nfsaddrs=10.0.0.99:10.0.0.2"
#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
#undef CONFIG_BOOTARGS
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
"addip=setenv bootargs ${bootargs} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
":${hostname}:${netdev}:off panic=1\0" \
"flash_nfs=run nfsargs addip;" \
"bootm ${kernel_addr}\0" \
"flash_self=run ramargs addip;" \
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
"bootfile=/tftpboot/fps850L/uImage\0" \
"fdt_addr=40040000\0" \
"kernel_addr=40060000\0" \
"ramdisk_addr=40200000\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
#undef CONFIG_WATCHDOG /* watchdog disabled */
/*
* BOOTP options
*/
@@ -80,24 +96,32 @@
#define CONFIG_BOOTP_NTPSERVER
#define CONFIG_BOOTP_TIMEOFFSET
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#undef CONFIG_CMD_CONSOLE
#undef CONFIG_CMD_BDI
#undef CONFIG_CMD_LOADS
#undef CONFIG_CMD_LOADB
#undef CONFIG_CMD_CACHE
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_NFS
#define CONFIG_CMD_SNTP
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */
#ifdef CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else

46
include/configs/FPS860L.h
View File

@@ -40,18 +40,37 @@
#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */
#undef CONFIG_8xx_CONS_NONE
#define CONFIG_BAUDRATE 115200
#if 0
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
#else
#define CONFIG_BOOTCOUNT_LIMIT
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#endif
#define CONFIG_BOOTCOMMAND "bootm 40040000" /* autoboot command */
#define CONFIG_BOARD_TYPES 1 /* support board types */
#define CONFIG_BOOTARGS "root=/dev/nfs rw " \
"nfsroot=10.0.0.2:/opt/eldk/ppc_8xx " \
"nfsaddrs=10.0.0.99:10.0.0.2"
#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
#undef CONFIG_BOOTARGS
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
"addip=setenv bootargs ${bootargs} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
":${hostname}:${netdev}:off panic=1\0" \
"flash_nfs=run nfsargs addip;" \
"bootm ${kernel_addr}\0" \
"flash_self=run ramargs addip;" \
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
"bootfile=/tftpboot/fps850L/uImage\0" \
"fdt_addr=40040000\0" \
"kernel_addr=40060000\0" \
"ramdisk_addr=40200000\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
@@ -79,11 +98,11 @@
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
@@ -95,7 +114,14 @@
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */
#ifdef CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else

40
include/configs/HH405.h
View File

@@ -141,8 +141,6 @@
#define CONFIG_AUTO_UPDATE 1 /* autoupdate via compactflash */
#undef CONFIG_AUTO_UPDATE_SHOW /* use board show routine */
#define CFG_NAND_LEGACY
#undef CONFIG_BZIP2 /* include support for bzip2 compressed images */
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -209,36 +207,18 @@
* NAND-FLASH stuff
*-----------------------------------------------------------------------
*/
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define SECTORSIZE 512
#define CFG_NAND_BASE_LIST { CFG_NAND_BASE }
#define NAND_MAX_CHIPS 1
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define NAND_BIG_DELAY_US 25
#define ADDR_COLUMN 1
#define ADDR_PAGE 2
#define ADDR_COLUMN_PAGE 3
#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
#define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1
#define NAND_MAX_CHIPS 1
#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
#define CFG_NAND_QUIET 1
/*-----------------------------------------------------------------------
* PCI stuff

40
include/configs/HUB405.h
View File

@@ -147,38 +147,18 @@
* NAND-FLASH stuff
*-----------------------------------------------------------------------
*/
#define CFG_NAND_LEGACY
#define CFG_NAND_BASE_LIST { CFG_NAND_BASE }
#define NAND_MAX_CHIPS 1
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define NAND_BIG_DELAY_US 25
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define SECTORSIZE 512
#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
#define ADDR_COLUMN 1
#define ADDR_PAGE 2
#define ADDR_COLUMN_PAGE 3
#define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1
#define NAND_MAX_CHIPS 1
#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
#define CFG_NAND_QUIET 1
/*-----------------------------------------------------------------------
* PCI stuff

1
include/configs/ICU862.h
View File

@@ -234,6 +234,7 @@
#define CFG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment sector */
#define CFG_ENV_SIZE 0x4000 /* Used Size of Environment Sector */
#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
/*-----------------------------------------------------------------------
* Cache Configuration

5
include/configs/IceCube.h
View File

@@ -178,12 +178,9 @@
#endif /* CONFIG_MPC5200 */
/* pass open firmware flat tree */
#define CONFIG_OF_FLAT_TREE 1
#define CONFIG_OF_LIBFDT 1
#define CONFIG_OF_BOARD_SETUP 1
/* maximum size of the flat tree (8K) */
#define OF_FLAT_TREE_MAX_SIZE 8192
#define OF_CPU "PowerPC,5200@0"
#define OF_SOC "soc5200@f0000000"
#define OF_TBCLK (bd->bi_busfreq / 4)

261
include/configs/M5235EVB.h Normal file
View File

@@ -0,0 +1,261 @@
/*
* Configuation settings for the Freescale MCF5329 FireEngine board.
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* board/config.h - configuration options, board specific
*/
#ifndef _M5235EVB_H
#define _M5235EVB_H
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_MCF523x /* define processor family */
#define CONFIG_M5235 /* define processor type */
#undef DEBUG
#define CONFIG_MCFUART
#define CFG_UART_PORT (0)
#define CONFIG_BAUDRATE 115200
#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
#undef CONFIG_WATCHDOG
#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
/*
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
/* Command line configuration */
#include <config_cmd_default.h>
#define CONFIG_CMD_BOOTD
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ELF
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_MISC
#define CONFIG_CMD_MII
#define CONFIG_CMD_NET
#define CONFIG_CMD_PCI
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
#undef CONFIG_CMD_LOADB
#undef CONFIG_CMD_LOADS
#define CONFIG_MCFFEC
#ifdef CONFIG_MCFFEC
# define CONFIG_NET_MULTI 1
# define CONFIG_MII 1
# define CFG_DISCOVER_PHY
# define CFG_RX_ETH_BUFFER 8
# define CFG_FAULT_ECHO_LINK_DOWN
# define CFG_FEC0_PINMUX 0
# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE
# define MCFFEC_TOUT_LOOP 50000
/* If CFG_DISCOVER_PHY is not defined - hardcoded */
# ifndef CFG_DISCOVER_PHY
# define FECDUPLEX FULL
# define FECSPEED _100BASET
# else
# ifndef CFG_FAULT_ECHO_LINK_DOWN
# define CFG_FAULT_ECHO_LINK_DOWN
# endif
# endif /* CFG_DISCOVER_PHY */
#endif
/* Timer */
#define CONFIG_MCFTMR
#undef CONFIG_MCFPIT
/* I2C */
#define CONFIG_FSL_I2C
#define CONFIG_HARD_I2C /* I2C with hw support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 80000
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_OFFSET 0x00000300
#define CFG_IMMR CFG_MBAR
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
#define CONFIG_BOOTFILE "u-boot.bin"
#ifdef CONFIG_MCFFEC
# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
# define CONFIG_IPADDR 192.162.1.2
# define CONFIG_NETMASK 255.255.255.0
# define CONFIG_SERVERIP 192.162.1.1
# define CONFIG_GATEWAYIP 192.162.1.1
# define CONFIG_OVERWRITE_ETHADDR_ONCE
#endif /* FEC_ENET */
#define CONFIG_HOSTNAME M5235EVB
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"loadaddr=10000\0" \
"u-boot=u-boot.bin\0" \
"load=tftp ${loadaddr) ${u-boot}\0" \
"upd=run load; run prog\0" \
"prog=prot off ffe00000 ffe3ffff;" \
"era ffe00000 ffe3ffff;" \
"cp.b ${loadaddr} ffe00000 ${filesize};"\
"save\0" \
""
#define CONFIG_PRAM 512 /* 512 KB */
#define CFG_PROMPT "-> "
#define CFG_LONGHELP /* undef to save memory */
#if defined(CONFIG_KGDB)
# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
# define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_LOAD_ADDR (CFG_SDRAM_BASE+0x20000)
#define CFG_HZ 1000
#define CFG_CLK 75000000
#define CFG_CPU_CLK CFG_CLK * 2
#define CFG_MBAR 0x40000000
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
* You should know what you are doing if you make changes here.
*/
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CFG_INIT_RAM_ADDR 0x20000000
#define CFG_INIT_RAM_END 0x10000 /* End of used area in internal SRAM */
#define CFG_INIT_RAM_CTRL 0x21
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE - 0x10)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CFG_SDRAM_BASE _must_ start at 0
*/
#define CFG_SDRAM_BASE 0x00000000
#define CFG_SDRAM_SIZE 16 /* SDRAM size in MB */
#define CFG_MEMTEST_START CFG_SDRAM_BASE + 0x400
#define CFG_MEMTEST_END ((CFG_SDRAM_SIZE - 3) << 20)
#define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400)
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#define CFG_BOOTPARAMS_LEN 64*1024
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
/* Initial Memory map for Linux */
#define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20))
/*-----------------------------------------------------------------------
* FLASH organization
*/
#define CFG_FLASH_CFI
#ifdef CFG_FLASH_CFI
# define CFG_FLASH_CFI_DRIVER 1
# define CFG_FLASH_SIZE 0x800000 /* Max size that the board might have */
#ifdef NORFLASH_PS32BIT
# define CFG_FLASH_CFI_WIDTH FLASH_CFI_32BIT
#else
# define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT
#endif
# define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
# define CFG_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
# define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
#endif
#define CFG_FLASH_BASE (CFG_CS0_BASE << 16)
/* Configuration for environment
* Environment is embedded in u-boot in the second sector of the flash
*/
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_IS_EMBEDDED 1
#ifdef NORFLASH_PS32BIT
# define CFG_ENV_OFFSET (0x8000)
# define CFG_ENV_SIZE 0x4000
# define CFG_ENV_SECT_SIZE 0x4000
#else
# define CFG_ENV_OFFSET (0x4000)
# define CFG_ENV_SIZE 0x2000
# define CFG_ENV_SECT_SIZE 0x2000
#endif
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16
/*-----------------------------------------------------------------------
* Chipselect bank definitions
*/
/*
* CS0 - NOR Flash 1, 2, 4, or 8MB
* CS1 - Available
* CS2 - Available
* CS3 - Available
* CS4 - Available
* CS5 - Available
* CS6 - Available
* CS7 - Available
*/
#ifdef NORFLASH_PS32BIT
# define CFG_CS0_BASE 0xFFC0
# define CFG_CS0_MASK 0x003f0001
# define CFG_CS0_CTRL 0x1D00
#else
# define CFG_CS0_BASE 0xFFE0
# define CFG_CS0_MASK 0x001f0001
# define CFG_CS0_CTRL 0x1D80
#endif
#endif /* _M5329EVB_H */

194
include/configs/M5249EVB.h Normal file
View File

@@ -0,0 +1,194 @@
/*
* Configuation settings for the esd TASREG board.
*
* (C) Copyright 2004
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* board/config.h - configuration options, board specific
*/
#ifndef _M5249EVB_H
#define _M5249EVB_H
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_MCF52x2 /* define processor family */
#define CONFIG_M5249 /* define processor type */
#define CONFIG_MCFTMR
#define CONFIG_MCFUART
#define CFG_UART_PORT (0)
#define CONFIG_BAUDRATE 19200
#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
#undef CONFIG_WATCHDOG
#undef CONFIG_MONITOR_IS_IN_RAM /* no pre-loader required!!! ;-) */
/*
* BOOTP options
*/
#undef CONFIG_BOOTP_BOOTFILESIZE
#undef CONFIG_BOOTP_BOOTPATH
#undef CONFIG_BOOTP_GATEWAY
#undef CONFIG_BOOTP_HOSTNAME
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#undef CONFIG_CMD_NET
#define CFG_PROMPT "=> "
#define CFG_LONGHELP /* undef to save memory */
#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */
#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup */
#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
#define CONFIG_LOOPW 1 /* enable loopw command */
#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
#define CFG_LOAD_ADDR 0x200000 /* default load address */
#define CFG_MEMTEST_START 0x400
#define CFG_MEMTEST_END 0x380000
#define CFG_HZ 1000
/*
* Clock configuration: enable only one of the following options
*/
#undef CFG_PLL_BYPASS /* bypass PLL for test purpose */
#define CFG_FAST_CLK 1 /* MCF5249 can run at 140MHz */
#define CFG_CLK 132025600 /* MCF5249 can run at 140MHz */
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
* You should know what you are doing if you make changes here.
*/
#define CFG_MBAR 0x10000000 /* Register Base Addrs */
#define CFG_MBAR2 0x80000000
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CFG_INIT_RAM_ADDR 0x20000000
#define CFG_INIT_RAM_END 0x1000 /* End of used area in internal SRAM */
#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_OFFSET 0x4000 /* Address of Environment Sector*/
#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
#define CFG_ENV_SECT_SIZE 0x2000 /* see README - env sector total size */
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CFG_SDRAM_BASE _must_ start at 0
*/
#define CFG_SDRAM_BASE 0x00000000
#define CFG_SDRAM_SIZE 16 /* SDRAM size in MB */
#define CFG_FLASH_BASE (CFG_CSAR0 << 16)
#if 0 /* test-only */
#define CONFIG_PRAM 512 /* test-only for SDRAM problem!!!!!!!!!!!!!!!!!!!! */
#endif
#define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400)
#define CFG_MONITOR_LEN 0x20000
#define CFG_MALLOC_LEN (1 * 1024*1024) /* Reserve 1 MB for malloc() */
#define CFG_BOOTPARAMS_LEN 64*1024
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
#define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20))
/*-----------------------------------------------------------------------
* FLASH organization
*/
#define CFG_FLASH_CFI
#ifdef CFG_FLASH_CFI
# define CFG_FLASH_CFI_DRIVER 1
# define CFG_FLASH_SIZE 0x1000000 /* Max size that the board might have */
# define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT
# define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
# define CFG_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
# define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
# define CFG_FLASH_CHECKSUM
# define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
#endif
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16
/*-----------------------------------------------------------------------
* Memory bank definitions
*/
/* CS0 - AMD Flash, address 0xffc00000 */
#define CFG_CSAR0 0xffe0
#define CFG_CSCR0 0x1980 /* WS=0110, AA=1, PS=10 */
/** Note: There is a CSMR0/DRAM vector problem, need to disable C/I ***/
#define CFG_CSMR0 0x003f0021 /* 4MB, AA=0, WP=0, C/I=1, V=1 */
/* CS1 - FPGA, address 0xe0000000 */
#define CFG_CSAR1 0xe000
#define CFG_CSCR1 0x0d80 /* WS=0011, AA=1, PS=10 */
#define CFG_CSMR1 0x00010001 /* 128kB, AA=0, WP=0, C/I=0, V=1*/
/*-----------------------------------------------------------------------
* Port configuration
*/
#define CFG_GPIO_FUNC 0x00000008 /* Set gpio pins: none */
#define CFG_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54*/
#define CFG_GPIO_EN 0x00000008 /* Set gpio output enable */
#define CFG_GPIO1_EN 0x00c70000 /* Set gpio output enable */
#define CFG_GPIO_OUT 0x00000008 /* Set outputs to default state */
#define CFG_GPIO1_OUT 0x00c70000 /* Set outputs to default state */
#define CFG_GPIO1_LED 0x00400000 /* user led */
#endif /* M5249 */

212
include/configs/M5253EVBE.h Normal file
View File

@@ -0,0 +1,212 @@
/*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* Hayden Fraser (Hayden.Fraser@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _M5253EVBE_H
#define _M5253EVBE_H
#define CONFIG_MCF52x2 /* define processor family */
#define CONFIG_M5253 /* define processor type */
#define CONFIG_M5253EVBE /* define board type */
#define CONFIG_MCFTMR
#define CONFIG_MCFUART
#define CFG_UART_PORT (0)
#define CONFIG_BAUDRATE 19200
#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
#undef CONFIG_WATCHDOG /* disable watchdog */
#define CONFIG_BOOTDELAY 5
/* Configuration for environment
* Environment is embedded in u-boot in the second sector of the flash
*/
#ifndef CONFIG_MONITOR_IS_IN_RAM
#define CFG_ENV_OFFSET 0x4000
#define CFG_ENV_SECT_SIZE 0x2000
#define CFG_ENV_IS_IN_FLASH 1
#else
#define CFG_ENV_ADDR 0xffe04000
#define CFG_ENV_SECT_SIZE 0x2000
#define CFG_ENV_IS_IN_FLASH 1
#endif
/*
* BOOTP options
*/
#undef CONFIG_BOOTP_BOOTFILESIZE
#undef CONFIG_BOOTP_BOOTPATH
#undef CONFIG_BOOTP_GATEWAY
#undef CONFIG_BOOTP_HOSTNAME
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#undef CONFIG_CMD_NET
#define CONFIG_CMD_LOADB
#define CONFIG_CMD_LOADS
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#define CONFIG_CMD_IDE
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_MISC
/* ATA */
#define CONFIG_DOS_PARTITION
#define CONFIG_MAC_PARTITION
#define CONFIG_IDE_RESET 1
#define CONFIG_IDE_PREINIT 1
#define CONFIG_ATAPI
#undef CONFIG_LBA48
#define CFG_IDE_MAXBUS 1
#define CFG_IDE_MAXDEVICE 2
#define CFG_ATA_BASE_ADDR (CFG_MBAR2 + 0x800)
#define CFG_ATA_IDE0_OFFSET 0
#define CFG_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */
#define CFG_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */
#define CFG_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */
#define CFG_ATA_STRIDE 4 /* Interval between registers */
#define _IO_BASE 0
#define CFG_PROMPT "=> "
#define CFG_LONGHELP /* undef to save memory */
#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_LOAD_ADDR 0x00100000
#define CFG_MEMTEST_START 0x400
#define CFG_MEMTEST_END 0x380000
#define CFG_HZ 1000
#undef CFG_PLL_BYPASS /* bypass PLL for test purpose */
#define CFG_FAST_CLK
#ifdef CFG_FAST_CLK
# define CFG_PLLCR 0x1243E054
# define CFG_CLK 140000000
#else
# define CFG_PLLCR 0x135a4140
# define CFG_CLK 70000000
#endif
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
* You should know what you are doing if you make changes here.
*/
#define CFG_MBAR 0x10000000 /* Register Base Addrs */
#define CFG_MBAR2 0x80000000 /* Module Base Addrs 2 */
/*
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CFG_INIT_RAM_ADDR 0x20000000
#define CFG_INIT_RAM_END 0x10000 /* End of used area in internal SRAM */
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
/*
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CFG_SDRAM_BASE _must_ start at 0
*/
#define CFG_SDRAM_BASE 0x00000000
#define CFG_SDRAM_SIZE 16 /* SDRAM size in MB */
#ifdef CONFIG_MONITOR_IS_IN_RAM
#define CFG_MONITOR_BASE 0x20000
#else
#define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400)
#endif
#define CFG_MONITOR_LEN 0x40000
#define CFG_MALLOC_LEN (256 << 10)
#define CFG_BOOTPARAMS_LEN (64*1024)
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
#define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20))
/* FLASH organization */
#define CFG_FLASH_BASE 0xffe00000
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 35 /* max number of sectors on one chip */
#define CFG_FLASH_ERASE_TOUT 1000
#define CFG_FLASH_CFI 1
#define CFG_FLASH_CFI_DRIVER 1
#define CFG_FLASH_SIZE 0x200000
#define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT
/* Cache Configuration */
#define CFG_CACHELINE_SIZE 16
/* Port configuration */
#define CFG_FECI2C 0xF0
#define CFG_CSAR0 0xFFE0
#define CFG_CSMR0 0x001F0021
#define CFG_CSCR0 0x1D80
#define CFG_CSAR1 0
#define CFG_CSMR1 0
#define CFG_CSCR1 0
#define CFG_CSAR2 0
#define CFG_CSMR2 0
#define CFG_CSCR2 0
#define CFG_CSAR3 0
#define CFG_CSMR3 0
#define CFG_CSCR3 0
/*-----------------------------------------------------------------------
* Port configuration
*/
#define CFG_GPIO_FUNC 0x00000008 /* Set gpio pins: none */
#define CFG_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54 */
#define CFG_GPIO_EN 0x00000008 /* Set gpio output enable */
#define CFG_GPIO1_EN 0x00c70000 /* Set gpio output enable */
#define CFG_GPIO_OUT 0x00000008 /* Set outputs to default state */
#define CFG_GPIO1_OUT 0x00c70000 /* Set outputs to default state */
#define CFG_GPIO1_LED 0x00400000 /* user led */
#endif /* _M5253EVB_H */

105
include/configs/M5271EVB.h
View File

@@ -31,7 +31,6 @@
#ifndef _M5271EVB_H
#define _M5271EVB_H
#define DEBUG
#undef DEBUG
/*
@@ -41,29 +40,26 @@
#define CONFIG_M5271 /* define processor type */
#define CONFIG_M5271EVB /* define board type */
#define CONFIG_IPADDR 192.168.30.1
#define CONFIG_SERVERIP 192.168.1.1
#define CONFIG_ETHADDR 00:06:3b:01:41:55
#define CONFIG_MCFTMR
#define CONFIG_MCFUART
#define CFG_UART_PORT (0)
#define CONFIG_BAUDRATE 19200
#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
#undef CONFIG_WATCHDOG /* disable watchdog */
#define CONFIG_BOOTDELAY 5
/* Configuration for environment
* Environment is embedded in u-boot in the second sector of the flash
*/
#ifndef CONFIG_MONITOR_IS_IN_RAM
#define CFG_ENV_OFFSET 0x4000
#define CFG_ENV_SECT_SIZE 0x2000
#define CFG_ENV_IS_IN_FLASH 1
#else
#define CFG_ENV_ADDR 0xffe04000
#endif
#define CFG_ENV_SECT_SIZE 0x2000
#define CFG_ENV_IS_IN_FLASH 1
#endif
#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
/*
* BOOTP options
@@ -73,7 +69,6 @@
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
/*
* Command line configuration.
*/
@@ -81,22 +76,83 @@
#define CONFIG_CMD_PING
#define CONFIG_CMD_NET
#define CONFIG_CMD_MII
#define CONFIG_CMD_ELF
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_MISC
#undef CONFIG_CMD_LOADS
#undef CONFIG_CMD_LOADB
#define CONFIG_MCFFEC
#ifdef CONFIG_MCFFEC
# define CONFIG_NET_MULTI 1
# define CONFIG_MII 1
# define CFG_DISCOVER_PHY
# define CFG_RX_ETH_BUFFER 8
# define CFG_FAULT_ECHO_LINK_DOWN
# define CFG_FEC0_PINMUX 0
# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE
# define MCFFEC_TOUT_LOOP 50000
/* If CFG_DISCOVER_PHY is not defined - hardcoded */
# ifndef CFG_DISCOVER_PHY
# define FECDUPLEX FULL
# define FECSPEED _100BASET
# else
# ifndef CFG_FAULT_ECHO_LINK_DOWN
# define CFG_FAULT_ECHO_LINK_DOWN
# endif
# endif /* CFG_DISCOVER_PHY */
#endif
/* I2C */
#define CONFIG_FSL_I2C
#define CONFIG_HARD_I2C /* I2C with hw support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 80000
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_OFFSET 0x00000300
#define CFG_IMMR CFG_MBAR
#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
#define CONFIG_BOOTFILE "u-boot.bin"
#ifdef CONFIG_MCFFEC
# define CONFIG_NET_RETRY_COUNT 5
# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
# define CONFIG_IPADDR 192.162.1.2
# define CONFIG_NETMASK 255.255.255.0
# define CONFIG_SERVERIP 192.162.1.1
# define CONFIG_GATEWAYIP 192.162.1.1
# define CONFIG_OVERWRITE_ETHADDR_ONCE
#endif /* FEC_ENET */
#define CONFIG_HOSTNAME M5235EVB
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"loadaddr=10000\0" \
"u-boot=u-boot.bin\0" \
"load=tftp ${loadaddr) ${u-boot}\0" \
"upd=run load; run prog\0" \
"prog=prot off ffe00000 ffe2ffff;" \
"era ffe00000 ffe2ffff;" \
"cp.b ${loadaddr} 0 ${filesize};" \
"save\0" \
""
#define CFG_PROMPT "=> "
#define CFG_LONGHELP /* undef to save memory */
#define CFG_LONGHELP /* undef to save memory */
#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_LOAD_ADDR 0x00100000
@@ -114,16 +170,11 @@
#define CFG_MBAR 0x40000000 /* Register Base Addrs */
/* Enable FEC ethernet */
#define FEC_ENET
#define CONFIG_NET_RETRY_COUNT 5
#define CFG_ENET_BD_BASE 0x480000
/*
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CFG_INIT_RAM_ADDR 0x20000000
#define CFG_INIT_RAM_END 0x1000 /* End of used area in internal SRAM */
#define CFG_INIT_RAM_END 0x1000 /* End of used area in internal SRAM */
#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
@@ -134,7 +185,7 @@
* Please note that CFG_SDRAM_BASE _must_ start at 0
*/
#define CFG_SDRAM_BASE 0x00000000
#define CFG_SDRAM_SIZE 16 /* SDRAM size in MB */
#define CFG_SDRAM_SIZE 16 /* SDRAM size in MB */
#define CFG_FLASH_BASE 0xffe00000
#ifdef CONFIG_MONITOR_IS_IN_RAM
@@ -152,11 +203,11 @@
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
#define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20))
/* FLASH organization */
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 11 /* max number of sectors on one chip */
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 11 /* max number of sectors on one chip */
#define CFG_FLASH_ERASE_TOUT 1000
#define CFG_FLASH_CFI 1
@@ -169,4 +220,4 @@
/* Port configuration */
#define CFG_FECI2C 0xF0
#endif /* _M5271EVB_H */
#endif /* _M5271EVB_H */

105
include/configs/M5272C3.h
View File

@@ -33,18 +33,20 @@
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_MCF52x2 /* define processor family */
#define CONFIG_M5272 /* define processor type */
#define CONFIG_MCF52x2 /* define processor family */
#define CONFIG_M5272 /* define processor type */
#define FEC_ENET
#define CONFIG_MCFTMR
#define CONFIG_MCFUART
#define CFG_UART_PORT (0)
#define CONFIG_BAUDRATE 19200
#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
#define CONFIG_WATCHDOG
#undef CONFIG_WATCHDOG
#define CONFIG_WATCHDOG_TIMEOUT 10000 /* timeout in milliseconds */
#define CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */
#undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */
/* Configuration for environment
* Environment is embedded in u-boot in the second sector of the flash
@@ -60,7 +62,6 @@
#define CFG_ENV_IS_IN_FLASH 1
#endif
/*
* BOOTP options
*/
@@ -69,37 +70,82 @@
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_MII
#define CONFIG_CMD_NET
#define CONFIG_CMD_PING
#define CONFIG_CMD_MISC
#define CONFIG_CMD_ELF
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_MEMORY
#undef CONFIG_CMD_LOADS
#undef CONFIG_CMD_LOADB
#define CONFIG_BOOTDELAY 5
#define CONFIG_MCFFEC
#ifdef CONFIG_MCFFEC
# define CONFIG_NET_MULTI 1
# define CONFIG_MII 1
# define CFG_DISCOVER_PHY
# define CFG_RX_ETH_BUFFER 8
# define CFG_FAULT_ECHO_LINK_DOWN
# define CFG_FEC0_PINMUX 0
# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE
# define MCFFEC_TOUT_LOOP 50000
/* If CFG_DISCOVER_PHY is not defined - hardcoded */
# ifndef CFG_DISCOVER_PHY
# define FECDUPLEX FULL
# define FECSPEED _100BASET
# else
# ifndef CFG_FAULT_ECHO_LINK_DOWN
# define CFG_FAULT_ECHO_LINK_DOWN
# endif
# endif /* CFG_DISCOVER_PHY */
#endif
#ifdef CONFIG_MCFFEC
# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
# define CONFIG_IPADDR 192.162.1.2
# define CONFIG_NETMASK 255.255.255.0
# define CONFIG_SERVERIP 192.162.1.1
# define CONFIG_GATEWAYIP 192.162.1.1
# define CONFIG_OVERWRITE_ETHADDR_ONCE
#endif /* CONFIG_MCFFEC */
#define CONFIG_HOSTNAME M5272C3
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"loadaddr=10000\0" \
"u-boot=u-boot.bin\0" \
"load=tftp ${loadaddr) ${u-boot}\0" \
"upd=run load; run prog\0" \
"prog=prot off ffe00000 ffe3ffff;" \
"era ffe00000 ffe3ffff;" \
"cp.b ${loadaddr} ffe00000 ${filesize};"\
"save\0" \
""
#define CFG_PROMPT "-> "
#define CFG_LONGHELP /* undef to save memory */
#define CFG_LONGHELP /* undef to save memory */
#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_LOAD_ADDR 0x20000
#define CFG_MEMTEST_START 0x400
#define CFG_MEMTEST_END 0x380000
#define CFG_HZ 1000
#define CFG_CLK 66000000
@@ -108,20 +154,15 @@
* (address mappings, register initial values, etc.)
* You should know what you are doing if you make changes here.
*/
#define CFG_MBAR 0x10000000 /* Register Base Addrs */
#define CFG_SCR 0x0003;
#define CFG_SPR 0xffff;
#define CFG_DISCOVER_PHY
#define CFG_ENET_BD_BASE 0x380000
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CFG_INIT_RAM_ADDR 0x20000000
#define CFG_INIT_RAM_END 0x1000 /* End of used area in internal SRAM */
#define CFG_INIT_RAM_END 0x1000 /* End of used area in internal SRAM */
#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
@@ -132,7 +173,7 @@
* Please note that CFG_SDRAM_BASE _must_ start at 0
*/
#define CFG_SDRAM_BASE 0x00000000
#define CFG_SDRAM_SIZE 4 /* SDRAM size in MB */
#define CFG_SDRAM_SIZE 4 /* SDRAM size in MB */
#define CFG_FLASH_BASE 0xffe00000
#ifdef CONFIG_MONITOR_IS_IN_RAM
@@ -150,13 +191,13 @@
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
#define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20))
/*-----------------------------------------------------------------------
* FLASH organization
*/
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 11 /* max number of sectors on one chip */
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 11 /* max number of sectors on one chip */
#define CFG_FLASH_ERASE_TOUT 1000
/*-----------------------------------------------------------------------
@@ -169,25 +210,18 @@
*/
#define CFG_BR0_PRELIM 0xFFE00201
#define CFG_OR0_PRELIM 0xFFE00014
#define CFG_BR1_PRELIM 0
#define CFG_OR1_PRELIM 0
#define CFG_BR2_PRELIM 0x30000001
#define CFG_OR2_PRELIM 0xFFF80000
#define CFG_BR3_PRELIM 0
#define CFG_OR3_PRELIM 0
#define CFG_BR4_PRELIM 0
#define CFG_OR4_PRELIM 0
#define CFG_BR5_PRELIM 0
#define CFG_OR5_PRELIM 0
#define CFG_BR6_PRELIM 0
#define CFG_OR6_PRELIM 0
#define CFG_BR7_PRELIM 0x00000701
#define CFG_OR7_PRELIM 0xFFC0007C
@@ -197,9 +231,8 @@
#define CFG_PACNT 0x00000000
#define CFG_PADDR 0x0000
#define CFG_PADAT 0x0000
#define CFG_PBCNT 0x55554155 /* Ethernet/UART configuration */
#define CFG_PBCNT 0x55554155 /* Ethernet/UART configuration */
#define CFG_PBDDR 0x0000
#define CFG_PBDAT 0x0000
#define CFG_PDCNT 0x00000000
#endif /* _M5272C3_H */
#endif /* _M5272C3_H */

147
include/configs/M5282EVB.h
View File

@@ -33,15 +33,17 @@
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_MCF52x2 /* define processor family */
#define CONFIG_M5282 /* define processor type */
#define CONFIG_MCF52x2 /* define processor family */
#define CONFIG_M5282 /* define processor type */
#define FEC_ENET
#define CONFIG_MCFTMR
#define CONFIG_MCFUART
#define CFG_UART_PORT (0)
#define CONFIG_BAUDRATE 19200
#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
#define CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */
#undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */
/* Configuration for environment
* Environment is embedded in u-boot in the second sector of the flash
@@ -50,7 +52,6 @@
#define CFG_ENV_SIZE 0x2000
#define CFG_ENV_IS_IN_FLASH 1
/*
* BOOTP options
*/
@@ -59,29 +60,73 @@
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_NET
#define CONFIG_CMD_PING
#define CONFIG_CMD_MII
#undef CONFIG_CMD_LOADS
#undef CONFIG_CMD_LOADB
#define CONFIG_MCFFEC
#ifdef CONFIG_MCFFEC
# define CONFIG_NET_MULTI 1
# define CONFIG_MII 1
# define CFG_DISCOVER_PHY
# define CFG_RX_ETH_BUFFER 8
# define CFG_FAULT_ECHO_LINK_DOWN
# define CFG_FEC0_PINMUX 0
# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE
# define MCFFEC_TOUT_LOOP 50000
/* If CFG_DISCOVER_PHY is not defined - hardcoded */
# ifndef CFG_DISCOVER_PHY
# define FECDUPLEX FULL
# define FECSPEED _100BASET
# else
# ifndef CFG_FAULT_ECHO_LINK_DOWN
# define CFG_FAULT_ECHO_LINK_DOWN
# endif
# endif /* CFG_DISCOVER_PHY */
#endif
#define CONFIG_BOOTDELAY 5
#ifdef CONFIG_MCFFEC
# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
# define CONFIG_IPADDR 192.162.1.2
# define CONFIG_NETMASK 255.255.255.0
# define CONFIG_SERVERIP 192.162.1.1
# define CONFIG_GATEWAYIP 192.162.1.1
# define CONFIG_OVERWRITE_ETHADDR_ONCE
#endif /* CONFIG_MCFFEC */
#define CONFIG_HOSTNAME M5272C3
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"loadaddr=10000\0" \
"u-boot=u-boot.bin\0" \
"load=tftp ${loadaddr) ${u-boot}\0" \
"upd=run load; run prog\0" \
"prog=prot off ffe00000 ffe3ffff;" \
"era ffe00000 ffe3ffff;" \
"cp.b ${loadaddr} ffe00000 ${filesize};"\
"save\0" \
""
#define CFG_PROMPT "-> "
#define CFG_LONGHELP /* undef to save memory */
#define CFG_LONGHELP /* undef to save memory */
#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_LOAD_ADDR 0x20000
@@ -91,6 +136,10 @@
#define CFG_HZ 1000000
#define CFG_CLK 64000000
/* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */
#define CFG_MFD 0x02 /* PLL Multiplication Factor Devider */
#define CFG_RFD 0x00 /* PLL Reduce Frecuency Devider */
/*
* Low Level Configuration Settings
@@ -99,15 +148,12 @@
*/
#define CFG_MBAR 0x40000000
#undef CFG_DISCOVER_PHY
#define CFG_ENET_BD_BASE 0x380000
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CFG_INIT_RAM_ADDR 0x20000000
#define CFG_INIT_RAM_END 0x10000 /* End of used area in internal SRAM */
#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
#define CFG_INIT_RAM_ADDR 0x20000000
#define CFG_INIT_RAM_END 0x10000 /* End of used area in internal SRAM */
#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
@@ -117,49 +163,88 @@
* Please note that CFG_SDRAM_BASE _must_ start at 0
*/
#define CFG_SDRAM_BASE 0x00000000
#define CFG_SDRAM_SIZE 4 /* SDRAM size in MB */
#define CFG_SDRAM_SIZE 8 /* SDRAM size in MB */
#define CFG_FLASH_BASE 0xffe00000
#define CFG_INT_FLASH_BASE 0xf0000000
#define CFG_INT_FLASH_ENABLE 0x21
/* If M5282 port is fully implemented the monitor base will be behind
* the vector table. */
/* #define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400) */
#define CFG_MONITOR_BASE 0x20000
#if (TEXT_BASE != CFG_INT_FLASH_BASE)
#define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400)
#else
#define CFG_MONITOR_BASE (TEXT_BASE + 0x418) /* 24 Byte for CFM-Config */
#endif
#define CFG_MONITOR_LEN 0x20000
#define CFG_MALLOC_LEN (256 << 10)
#define CFG_BOOTPARAMS_LEN 64*1024
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
#define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20))
/*-----------------------------------------------------------------------
* FLASH organization
*/
#define CFG_MAX_FLASH_SECT 35
#define CFG_MAX_FLASH_BANKS 1
#define CFG_FLASH_ERASE_TOUT 10000000
#define CFG_FLASH_CFI
#ifdef CFG_FLASH_CFI
# define CFG_FLASH_CFI_DRIVER 1
# define CFG_FLASH_SIZE 0x1000000 /* Max size that the board might have */
# define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT
# define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
# define CFG_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
# define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
# define CFG_FLASH_CHECKSUM
# define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
#endif
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16
/*-----------------------------------------------------------------------
* Memory bank definitions
*/
#define CFG_CS0_BASE CFG_FLASH_BASE
#define CFG_CS0_SIZE 2*1024*1024
#define CFG_CS0_WIDTH 16
#define CFG_CS0_RO 0
#define CFG_CS0_WS 6
/*
#define CFG_CS3_BASE 0xE0000000
#define CFG_CS3_SIZE 1*1024*1024
#define CFG_CS3_WIDTH 16
#define CFG_CS3_RO 0
#define CFG_CS3_WS 6
*/
/*-----------------------------------------------------------------------
* Port configuration
*/
#define CFG_PACNT 0x0000000 /* Port A D[31:24] */
#define CFG_PADDR 0x0000000
#define CFG_PADAT 0x0000000
#define CFG_PBCNT 0x0000000 /* Port B D[23:16] */
#define CFG_PBDDR 0x0000000
#define CFG_PBDAT 0x0000000
#endif /* _CONFIG_M5282EVB_H */
#define CFG_PCCNT 0x0000000 /* Port C D[15:08] */
#define CFG_PCDDR 0x0000000
#define CFG_PCDAT 0x0000000
#define CFG_PDCNT 0x0000000 /* Port D D[07:00] */
#define CFG_PCDDR 0x0000000
#define CFG_PCDAT 0x0000000
#define CFG_PEHLPAR 0xC0
#define CFG_PUAPAR 0x0F /* UA0..UA3 = Uart 0 +1 */
#define CFG_DDRUA 0x05
#define CFG_PJPAR 0xFF;
#endif /* _CONFIG_M5282EVB_H */

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/*
* Configuation settings for the Freescale MCF5329 FireEngine board.
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* board/config.h - configuration options, board specific
*/
#ifndef _M5329EVB_H
#define _M5329EVB_H
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_MCF532x /* define processor family */
#define CONFIG_M5329 /* define processor type */
#undef DEBUG
#define CONFIG_MCFUART
#define CFG_UART_PORT (0)
#define CONFIG_BAUDRATE 115200
#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
#undef CONFIG_WATCHDOG
#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
/* Command line configuration */
#include <config_cmd_default.h>
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DATE
#define CONFIG_CMD_ELF
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_MISC
#define CONFIG_CMD_MII
#define CONFIG_CMD_NET
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
#ifdef NANDFLASH_SIZE
# define CONFIG_CMD_NAND
#endif
#define CFG_UNIFY_CACHE
#define CONFIG_MCFFEC
#ifdef CONFIG_MCFFEC
# define CONFIG_NET_MULTI 1
# define CONFIG_MII 1
# define CFG_DISCOVER_PHY
# define CFG_RX_ETH_BUFFER 8
# define CFG_FAULT_ECHO_LINK_DOWN
# define CFG_FEC0_PINMUX 0
# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE
# define MCFFEC_TOUT_LOOP 50000
/* If CFG_DISCOVER_PHY is not defined - hardcoded */
# ifndef CFG_DISCOVER_PHY
# define FECDUPLEX FULL
# define FECSPEED _100BASET
# else
# ifndef CFG_FAULT_ECHO_LINK_DOWN
# define CFG_FAULT_ECHO_LINK_DOWN
# endif
# endif /* CFG_DISCOVER_PHY */
#endif
#define CONFIG_MCFRTC
#undef RTC_DEBUG
/* Timer */
#define CONFIG_MCFTMR
#undef CONFIG_MCFPIT
/* I2C */
#define CONFIG_FSL_I2C
#define CONFIG_HARD_I2C /* I2C with hw support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 80000
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_OFFSET 0x58000
#define CFG_IMMR CFG_MBAR
#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
#define CONFIG_UDP_CHECKSUM
#ifdef CONFIG_MCFFEC
# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
# define CONFIG_IPADDR 192.162.1.2
# define CONFIG_NETMASK 255.255.255.0
# define CONFIG_SERVERIP 192.162.1.1
# define CONFIG_GATEWAYIP 192.162.1.1
# define CONFIG_OVERWRITE_ETHADDR_ONCE
#endif /* FEC_ENET */
#define CONFIG_HOSTNAME M5329EVB
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"loadaddr=40010000\0" \
"u-boot=u-boot.bin\0" \
"load=tftp ${loadaddr) ${u-boot}\0" \
"upd=run load; run prog\0" \
"prog=prot off 0 2ffff;" \
"era 0 2ffff;" \
"cp.b ${loadaddr} 0 ${filesize};" \
"save\0" \
""
#define CONFIG_PRAM 512 /* 512 KB */
#define CFG_PROMPT "-> "
#define CFG_LONGHELP /* undef to save memory */
#ifdef CONFIG_CMD_KGDB
# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
# define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_LOAD_ADDR 0x40010000
#define CFG_HZ 1000
#define CFG_CLK 80000000
#define CFG_CPU_CLK CFG_CLK * 3
#define CFG_MBAR 0xFC000000
#define CFG_LATCH_ADDR (CFG_CS1_BASE + 0x80000)
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
* You should know what you are doing if you make changes here.
*/
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CFG_INIT_RAM_ADDR 0x80000000
#define CFG_INIT_RAM_END 0x8000 /* End of used area in internal SRAM */
#define CFG_INIT_RAM_CTRL 0x221
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET ((CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) - 0x10)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CFG_SDRAM_BASE _must_ start at 0
*/
#define CFG_SDRAM_BASE 0x40000000
#define CFG_SDRAM_SIZE 16 /* SDRAM size in MB */
#define CFG_SDRAM_CFG1 0x53722730
#define CFG_SDRAM_CFG2 0x56670000
#define CFG_SDRAM_CTRL 0xE1092000
#define CFG_SDRAM_EMOD 0x40010000
#define CFG_SDRAM_MODE 0x018D0000
#define CFG_MEMTEST_START CFG_SDRAM_BASE + 0x400
#define CFG_MEMTEST_END ((CFG_SDRAM_SIZE - 3) << 20)
#define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400)
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#define CFG_BOOTPARAMS_LEN 64*1024
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
#define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20))
/*-----------------------------------------------------------------------
* FLASH organization
*/
#define CFG_FLASH_CFI
#ifdef CFG_FLASH_CFI
# define CFG_FLASH_CFI_DRIVER 1
# define CFG_FLASH_SIZE 0x800000 /* Max size that the board might have */
# define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT
# define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
# define CFG_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
# define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
#endif
#ifdef NANDFLASH_SIZE
# define CFG_MAX_NAND_DEVICE 1
# define CFG_NAND_BASE (CFG_CS2_BASE << 16)
# define CFG_NAND_SIZE 1
# define CFG_NAND_BASE_LIST { CFG_NAND_BASE }
# define NAND_MAX_CHIPS 1
# define NAND_ALLOW_ERASE_ALL 1
# define CONFIG_JFFS2_NAND 1
# define CONFIG_JFFS2_DEV "nand0"
# define CONFIG_JFFS2_PART_SIZE (CFG_CS2_MASK & ~1)
# define CONFIG_JFFS2_PART_OFFSET 0x00000000
#endif
#define CFG_FLASH_BASE (CFG_CS0_BASE << 16)
/* Configuration for environment
* Environment is embedded in u-boot in the second sector of the flash
*/
#define CFG_ENV_OFFSET 0x4000
#define CFG_ENV_SECT_SIZE 0x2000
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_IS_EMBEDDED 1
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16
/*-----------------------------------------------------------------------
* Chipselect bank definitions
*/
/*
* CS0 - NOR Flash 1, 2, 4, or 8MB
* CS1 - CompactFlash and registers
* CS2 - NAND Flash 16, 32, or 64MB
* CS3 - Available
* CS4 - Available
* CS5 - Available
*/
#define CFG_CS0_BASE 0
#define CFG_CS0_MASK 0x007f0001
#define CFG_CS0_CTRL 0x00001fa0
#define CFG_CS1_BASE 0x1000
#define CFG_CS1_MASK 0x001f0001
#define CFG_CS1_CTRL 0x002A3780
#ifdef NANDFLASH_SIZE
#define CFG_CS2_BASE 0x2000
#define CFG_CS2_MASK ((NANDFLASH_SIZE << 20) | 1)
#define CFG_CS2_CTRL 0x00001f60
#endif
#endif /* _M5329EVB_H */

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/*
* Configuation settings for the Freescale MCF54455 EVB board.
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* board/config.h - configuration options, board specific
*/
#ifndef _JAMICA54455_H
#define _JAMICA54455_H
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_MCF5445x /* define processor family */
#define CONFIG_M54455 /* define processor type */
#define CONFIG_M54455EVB /* M54455EVB board */
#undef DEBUG
#define CONFIG_MCFUART
#define CFG_UART_PORT (0)
#define CONFIG_BAUDRATE 115200
#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
#undef CONFIG_WATCHDOG
#define CONFIG_TIMESTAMP /* Print image info with timestamp */
/*
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
/* Command line configuration */
#include <config_cmd_default.h>
#define CONFIG_CMD_BOOTD
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ELF
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IDE
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_MISC
#define CONFIG_CMD_MII
#define CONFIG_CMD_NET
#define CONFIG_CMD_PCI
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
#undef CONFIG_CMD_LOADB
#undef CONFIG_CMD_LOADS
/* Network configuration */
#define CONFIG_MCFFEC
#ifdef CONFIG_MCFFEC
# define CONFIG_NET_MULTI 1
# define CONFIG_MII 1
# define CONFIG_CF_DOMII
# define CFG_DISCOVER_PHY
# define CFG_RX_ETH_BUFFER 8
# define CFG_FAULT_ECHO_LINK_DOWN
# define CFG_FEC0_PINMUX 0
# define CFG_FEC1_PINMUX 0
# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE
# define CFG_FEC1_MIIBASE CFG_FEC0_IOBASE
# define MCFFEC_TOUT_LOOP 50000
# define CONFIG_HAS_ETH1
# define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
# define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:5M(kernel)ro,-(jffs2)"
# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
# define CONFIG_ETH1ADDR 00:e0:0c:bc:e5:61
# define CONFIG_ETHPRIME "FEC0"
# define CONFIG_IPADDR 192.162.1.2
# define CONFIG_NETMASK 255.255.255.0
# define CONFIG_SERVERIP 192.162.1.1
# define CONFIG_GATEWAYIP 192.162.1.1
# define CONFIG_OVERWRITE_ETHADDR_ONCE
/* If CFG_DISCOVER_PHY is not defined - hardcoded */
# ifndef CFG_DISCOVER_PHY
# define FECDUPLEX FULL
# define FECSPEED _100BASET
# else
# ifndef CFG_FAULT_ECHO_LINK_DOWN
# define CFG_FAULT_ECHO_LINK_DOWN
# endif
# endif /* CFG_DISCOVER_PHY */
#endif
#define CONFIG_HOSTNAME M54455EVB
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"inpclk=" MK_STR(CFG_INPUT_CLKSRC) "\0" \
"loadaddr=40010000\0" \
"u-boot=u-boot.bin\0" \
"load=tftp ${loadaddr) ${u-boot}\0" \
"upd=run load; run prog\0" \
"prog=prot off 0 2ffff;" \
"era 0 2ffff;" \
"cp.b ${loadaddr} 0 ${filesize};" \
"save\0" \
""
/* ATA configuration */
#define CONFIG_ISO_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_IDE_RESET 1
#define CONFIG_IDE_PREINIT 1
#define CONFIG_ATAPI
#undef CONFIG_LBA48
#define CFG_IDE_MAXBUS 1
#define CFG_IDE_MAXDEVICE 2
#define CFG_ATA_BASE_ADDR 0x90000000
#define CFG_ATA_IDE0_OFFSET 0
#define CFG_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */
#define CFG_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */
#define CFG_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */
#define CFG_ATA_STRIDE 4 /* Interval between registers */
#define _IO_BASE 0
/* Realtime clock */
#define CONFIG_MCFRTC
#undef RTC_DEBUG
#define CFG_RTC_OSCILLATOR (32 * CFG_HZ)
/* Timer */
#define CONFIG_MCFTMR
#undef CONFIG_MCFPIT
/* I2c */
#define CONFIG_FSL_I2C
#define CONFIG_HARD_I2C /* I2C with hardware support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 80000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_OFFSET 0x58000
#define CFG_IMMR CFG_MBAR
/* PCI */
#define CONFIG_PCI 1
#define CFG_PCI_MEM_BUS 0xA0000000
#define CFG_PCI_MEM_PHYS CFG_PCI_MEM_BUS
#define CFG_PCI_MEM_SIZE 0x10000000
#define CFG_PCI_IO_BUS 0xB1000000
#define CFG_PCI_IO_PHYS CFG_PCI_IO_BUS
#define CFG_PCI_IO_SIZE 0x01000000
#define CFG_PCI_CFG_BUS 0xB0000000
#define CFG_PCI_CFG_PHYS CFG_PCI_CFG_BUS
#define CFG_PCI_CFG_SIZE 0x01000000
/* FPGA - Spartan 2 */
/* experiment
#define CONFIG_FPGA CFG_SPARTAN3
#define CONFIG_FPGA_COUNT 1
#define CFG_FPGA_PROG_FEEDBACK
#define CFG_FPGA_CHECK_CTRLC
*/
/* Input, PCI, Flexbus, and VCO */
#define CONFIG_EXTRA_CLOCK
#define CONFIG_PRAM 512 /* 512 KB */
#define CFG_PROMPT "-> "
#define CFG_LONGHELP /* undef to save memory */
#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x10000)
#define CFG_HZ 1000
#define CFG_MBAR 0xFC000000
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
* You should know what you are doing if you make changes here.
*/
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CFG_INIT_RAM_ADDR 0x80000000
#define CFG_INIT_RAM_END 0x8000 /* End of used area in internal SRAM */
#define CFG_INIT_RAM_CTRL 0x221
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET ((CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) - 16)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CFG_SDRAM_BASE _must_ start at 0
*/
#define CFG_SDRAM_BASE 0x40000000
#define CFG_SDRAM_BASE1 0x48000000
#define CFG_SDRAM_SIZE 256 /* SDRAM size in MB */
#define CFG_SDRAM_CFG1 0x65311610
#define CFG_SDRAM_CFG2 0x59670000
#define CFG_SDRAM_CTRL 0xEA0B2000
#define CFG_SDRAM_EMOD 0x40010000
#define CFG_SDRAM_MODE 0x00010033
#define CFG_MEMTEST_START CFG_SDRAM_BASE + 0x400
#define CFG_MEMTEST_END ((CFG_SDRAM_SIZE - 3) << 20)
#define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400)
#define CFG_BOOTPARAMS_LEN 64*1024
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
/* Initial Memory map for Linux */
#define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20))
/* Configuration for environment
* Environment is embedded in u-boot in the second sector of the flash
*/
#define CFG_ENV_OFFSET 0x4000
#define CFG_ENV_SECT_SIZE 0x2000
#define CFG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_OVERWRITE 1
#undef CFG_ENV_IS_EMBEDDED
/*-----------------------------------------------------------------------
* FLASH organization
*/
#ifdef CFG_ATMEL_BOOT
# define CFG_FLASH_BASE 0
# define CFG_FLASH0_BASE CFG_CS0_BASE
# define CFG_FLASH1_BASE CFG_CS1_BASE
#else
# define CFG_FLASH_BASE CFG_FLASH0_BASE
# define CFG_FLASH0_BASE CFG_CS1_BASE
# define CFG_FLASH1_BASE CFG_CS0_BASE
#endif
/* M54455EVB has one non CFI flash, defined CFG_FLASH_CFI will cause the system
/* M54455EVB has one non CFI flash, defined CFG_FLASH_CFI will cause the system
keep reset. */
#undef CFG_FLASH_CFI
#ifdef CFG_FLASH_CFI
# define CFG_FLASH_CFI_DRIVER 1
# define CFG_FLASH_SIZE 0x1000000 /* Max size that the board might have */
# define CFG_FLASH_CFI_WIDTH FLASH_CFI_8BIT
# define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
# define CFG_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
# define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
# define CFG_FLASH_CHECKSUM
# define CFG_FLASH_BANKS_LIST { CFG_CS0_BASE, CFG_CS1_BASE }
#else
# define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
# define CFG_ATMEL_REGION 4
# define CFG_ATMEL_TOTALSECT 11
# define CFG_ATMEL_SECT {1, 2, 1, 7}
# define CFG_ATMEL_SECTSZ {0x4000, 0x2000, 0x8000, 0x10000}
# define CFG_INTEL_SECT 137
/* max number of sectors on one chip */
# define CFG_MAX_FLASH_SECT (CFG_ATMEL_TOTALSECT + CFG_INTEL_SECT)
# define CFG_FLASH_ERASE_TOUT 2000 /* Atmel needs longer timeout */
# define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
# define CFG_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */
# define CFG_FLASH_UNLOCK_TOUT 100 /* Timeout for Flash Clear Lock Bits (in ms) */
# define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
# define CFG_FLASH_CHECKSUM
#endif
/*
* This is setting for JFFS2 support in u-boot.
* NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
*/
#ifdef CFG_ATMEL_BOOT
# define CONFIG_JFFS2_DEV "nor0"
# define CONFIG_JFFS2_PART_SIZE 0x01000000
# define CONFIG_JFFS2_PART_OFFSET CFG_FLASH1_BASE
#else
# define CONFIG_JFFS2_DEV "nor0"
# define CONFIG_JFFS2_PART_SIZE (0x01000000 - 0x500000)
# define CONFIG_JFFS2_PART_OFFSET (CFG_FLASH0_BASE + 0x500000)
#endif
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16
/*-----------------------------------------------------------------------
* Memory bank definitions
*/
/*
* CS0 - NOR Flash 1, 2, 4, or 8MB
* CS1 - CompactFlash and registers
* CS2 - CPLD
* CS3 - FPGA
* CS4 - Available
* CS5 - Available
*/
#ifdef CFG_ATMEL_BOOT
/* Atmel Flash */
#define CFG_CS0_BASE 0
#define CFG_CS0_MASK 0x00070001
#define CFG_CS0_CTRL 0x00001140
/* Intel Flash */
#define CFG_CS1_BASE 0x04000000
#define CFG_CS1_MASK 0x01FF0001
#define CFG_CS1_CTRL 0x003F3D60
#define CFG_ATMEL_BASE CFG_CS0_BASE
#else
/* Intel Flash */
#define CFG_CS0_BASE 0
#define CFG_CS0_MASK 0x01FF0001
#define CFG_CS0_CTRL 0x003F3D60
/* Atmel Flash */
#define CFG_CS1_BASE 0x04000000
#define CFG_CS1_MASK 0x00070001
#define CFG_CS1_CTRL 0x00001140
#define CFG_ATMEL_BASE CFG_CS1_BASE
#endif
/* CPLD */
#define CFG_CS2_BASE 0x08000000
#define CFG_CS2_MASK 0x00070001
#define CFG_CS2_CTRL 0x003f1140
/* FPGA */
#define CFG_CS3_BASE 0x09000000
#define CFG_CS3_MASK 0x00070001
#define CFG_CS3_CTRL 0x00000020
#endif /* _JAMICA54455_H */

12
include/configs/MPC8313ERDB.h
View File

@@ -113,12 +113,12 @@
/* 0x03200064 */
#if defined(CONFIG_DDR_2T_TIMING)
#define CFG_SDRAM_CFG ( SDRAM_CFG_SREN \
| 3 << SDRAM_CFG_SDRAM_TYPE_SHIFT \
| SDRAM_CFG_SDRAM_TYPE_DDR2 \
| SDRAM_CFG_2T_EN \
| SDRAM_CFG_DBW_32 )
#else
#define CFG_SDRAM_CFG ( SDRAM_CFG_SREN \
| 3 << SDRAM_CFG_SDRAM_TYPE_SHIFT \
| SDRAM_CFG_SDRAM_TYPE_DDR2 \
| SDRAM_CFG_32_BE )
/* 0x43080000 */
#endif
@@ -228,12 +228,9 @@
#define CFG_LBLAWAR3_PRELIM 0x8000000E /* 32KB */
/* pass open firmware flat tree */
#define CONFIG_OF_FLAT_TREE 1
#define CONFIG_OF_LIBFDT 1
#define CONFIG_OF_BOARD_SETUP 1
/* maximum size of the flat tree (8K) */
#define OF_FLAT_TREE_MAX_SIZE 8192
#define OF_CPU "PowerPC,8313@0"
#define OF_SOC "soc8313@e0000000"
#define OF_TBCLK (bd->bi_busfreq / 4)
@@ -310,6 +307,8 @@
#define CONFIG_TSEC2_NAME "TSEC1"
#define TSEC1_PHY_ADDR 0x1c
#define TSEC2_PHY_ADDR 4
#define TSEC1_FLAGS TSEC_GIGABIT
#define TSEC2_FLAGS TSEC_GIGABIT
#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
@@ -507,6 +506,7 @@
#define CONFIG_ETHADDR 00:E0:0C:00:95:01
#define CONFIG_HAS_ETH1
#define CONFIG_HAS_ETH0
#define CONFIG_ETH1ADDR 00:E0:0C:00:95:02
#define CONFIG_IPADDR 10.0.0.2

8
include/configs/MPC832XEMDS.h
View File

@@ -30,6 +30,8 @@
#define CONFIG_MPC83XX 1 /* MPC83xx family */
#define CONFIG_MPC832X 1 /* MPC832x CPU specific */
#define CONFIG_MPC832XEMDS 1 /* MPC832XEMDS board specific */
#undef CONFIG_PQ_MDS_PIB /* POWERQUICC MDS Platform IO Board */
#undef CONFIG_PQ_MDS_PIB_ATM /* QOC3 ATM card */
/*
* System Clock Setup
@@ -87,6 +89,7 @@
#define CFG_SICRL 0x00000000
#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
#define CONFIG_BOARD_EARLY_INIT_R
/*
* IMMR new address
@@ -315,12 +318,9 @@
#endif
/* pass open firmware flat tree */
#define CONFIG_OF_FLAT_TREE 1
#define CONFIG_OF_LIBFDT 1
#define CONFIG_OF_BOARD_SETUP 1
/* maximum size of the flat tree (8K) */
#define OF_FLAT_TREE_MAX_SIZE 8192
#define OF_CPU "PowerPC,8323@0"
#define OF_SOC "soc8323@e0000000"
#define OF_QE "qe@e0100000"

8
include/configs/MPC8349EMDS.h
View File

@@ -339,12 +339,9 @@
#endif
/* pass open firmware flat tree */
#define CONFIG_OF_FLAT_TREE 1
#define CONFIG_OF_LIBFDT 1
#define CONFIG_OF_BOARD_SETUP 1
/* maximum size of the flat tree (8K) */
#define OF_FLAT_TREE_MAX_SIZE 8192
#define OF_CPU "PowerPC,8349@0"
#define OF_SOC "soc8349@e0000000"
#define OF_TBCLK (bd->bi_busfreq / 4)
@@ -440,6 +437,8 @@
#define TSEC2_PHY_ADDR 1
#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
#define TSEC1_FLAGS TSEC_GIGABIT
#define TSEC2_FLAGS TSEC_GIGABIT
/* Options are: TSEC[0-1] */
#define CONFIG_ETHPRIME "TSEC0"
@@ -699,6 +698,7 @@
#if defined(CONFIG_TSEC_ENET)
#define CONFIG_ETHADDR 00:04:9f:ef:23:33
#define CONFIG_HAS_ETH1
#define CONFIG_HAS_ETH0
#define CONFIG_ETH1ADDR 00:E0:0C:00:7E:21
#endif

8
include/configs/MPC8349ITX.h
View File

@@ -296,12 +296,9 @@ boards, we say we have two, but don't display a message if we find only one. */
#define CFG_NS16550_COM2 (CFG_IMMR + 0x4600)
/* pass open firmware flat tree */
#define CONFIG_OF_FLAT_TREE
#define CONFIG_OF_LIBFDT 1
#define CONFIG_OF_BOARD_SETUP
/* maximum size of the flat tree (8K) */
#define OF_FLAT_TREE_MAX_SIZE 8192
#define OF_CPU "PowerPC,8349@0"
#define OF_SOC "soc8349@e0000000"
#define OF_TBCLK (bd->bi_busfreq / 4)
@@ -378,10 +375,12 @@ boards, we say we have two, but don't display a message if we find only one. */
#define CONFIG_TSEC1
#ifdef CONFIG_TSEC1
#define CONFIG_HAS_ETH0
#define CONFIG_TSEC1_NAME "TSEC0"
#define CFG_TSEC1_OFFSET 0x24000
#define TSEC1_PHY_ADDR 0x1c /* VSC8201 uses address 0x1c */
#define TSEC1_PHYIDX 0
#define TSEC1_FLAGS TSEC_GIGABIT
#endif
#ifdef CONFIG_TSEC2
@@ -391,6 +390,7 @@ boards, we say we have two, but don't display a message if we find only one. */
#define CONFIG_UNKNOWN_TSEC /* TSEC2 is proprietary */
#define TSEC2_PHY_ADDR 4
#define TSEC2_PHYIDX 0
#define TSEC2_FLAGS TSEC_GIGABIT
#endif
#define CONFIG_ETHPRIME "Freescale TSEC"

11
include/configs/MPC8360EMDS.h
View File

@@ -32,6 +32,8 @@
#define CONFIG_MPC83XX 1 /* MPC83XX family */
#define CONFIG_MPC8360 1 /* MPC8360 CPU specific */
#define CONFIG_MPC8360EMDS 1 /* MPC8360EMDS board specific */
#undef CONFIG_PQ_MDS_PIB /* POWERQUICC MDS Platform IO Board */
#undef CONFIG_PQ_MDS_PIB_ATM /* QOC3 ATM card */
/*
* System Clock Setup
@@ -88,6 +90,7 @@
#define CFG_SICRL 0x40000000
#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
#define CONFIG_BOARD_EARLY_INIT_R
/*
* IMMR new address
@@ -309,13 +312,13 @@
/*
* CS4 on Local Bus, to PIB
*/
#define CFG_BR4_PRELIM 0xf8008801 /* CS4 base address at 0xf8008000 */
#define CFG_BR4_PRELIM 0xf8010801 /* CS4 base address at 0xf8010000 */
#define CFG_OR4_PRELIM 0xffffe9f7 /* size 32KB, port size 8bit, GPCM */
/*
* CS5 on Local Bus, to PIB
*/
#define CFG_BR5_PRELIM 0xf8010801 /* CS5 base address at 0xf8010000 */
#define CFG_BR5_PRELIM 0xf8008801 /* CS5 base address at 0xf8008000 */
#define CFG_OR5_PRELIM 0xffffe9f7 /* size 32KB, port size 8bit, GPCM */
/*
@@ -348,10 +351,6 @@
#define CONFIG_OF_HAS_BD_T 1
#define CONFIG_OF_HAS_UBOOT_ENV 1
/* maximum size of the flat tree (8K) */
#define OF_FLAT_TREE_MAX_SIZE 8192
#define OF_CPU "PowerPC,8360@0"
#define OF_SOC "soc8360@e0000000"
#define OF_QE "qe@e0100000"

7
include/configs/MPC8540ADS.h
View File

@@ -301,9 +301,6 @@
#define CONFIG_OF_FLAT_TREE 1
#define CONFIG_OF_BOARD_SETUP 1
/* maximum size of the flat tree (8K) */
#define OF_FLAT_TREE_MAX_SIZE 8192
#define OF_CPU "PowerPC,8540@0"
#define OF_SOC "soc8540@e0000000"
#define OF_TBCLK (bd->bi_busfreq / 8)
@@ -374,6 +371,8 @@
#define TSEC2_PHY_ADDR 1
#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
#define TSEC1_FLAGS TSEC_GIGABIT
#define TSEC2_FLAGS TSEC_GIGABIT
#if CONFIG_HAS_FEC
@@ -381,6 +380,7 @@
#define CONFIG_MPC85XX_FEC_NAME "FEC"
#define FEC_PHY_ADDR 3
#define FEC_PHYIDX 0
#define FEC_FLAGS 0
#endif
/* Options are: TSEC[0-1], FEC */
@@ -489,6 +489,7 @@
/* The mac addresses for all ethernet interface */
#if defined(CONFIG_TSEC_ENET)
#define CONFIG_HAS_ETH0
#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
#define CONFIG_HAS_ETH1
#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD

7
include/configs/MPC8540EVAL.h
View File

@@ -213,10 +213,13 @@
#define CONFIG_NET_MULTI 1
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_TSEC1 1
#define CONFIG_HAS_ETH0
#define CONFIG_TSEC1_NAME "TSEC0"
#define CONFIG_TSEC2 1
#define CONFIG_HAS_ETH1
#define CONFIG_TSEC2_NAME "TSEC1"
#define CONFIG_MPC85XX_FEC 1
#define CONFIG_HAS_ETH2
#define CONFIG_MPC85XX_FEC_NAME "FEC"
#define TSEC1_PHY_ADDR 7
#define TSEC2_PHY_ADDR 4
@@ -224,6 +227,10 @@
#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
#define FEC_PHYIDX 0
#define TSEC1_FLAGS TSEC_GIGABIT
#define TSEC2_FLAGS TSEC_GIGABIT
#define FEC_FLAGS 0
/* Options are: TSEC[0-1], FEC */
#define CONFIG_ETHPRIME "TSEC0"

16
include/configs/MPC8541CDS.h
View File

@@ -312,9 +312,6 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_OF_FLAT_TREE 1
#define CONFIG_OF_BOARD_SETUP 1
/* maximum size of the flat tree (8K) */
#define OF_FLAT_TREE_MAX_SIZE 8192
#define OF_CPU "PowerPC,8541@0"
#define OF_SOC "soc8541@e0000000"
#define OF_TBCLK (bd->bi_busfreq / 8)
@@ -350,6 +347,13 @@ extern unsigned long get_clock_freq(void);
#define CFG_PCI2_IO_PHYS 0xe2100000
#define CFG_PCI2_IO_SIZE 0x100000 /* 1M */
#ifdef CONFIG_LEGACY
#define BRIDGE_ID 17
#define VIA_ID 2
#else
#define BRIDGE_ID 28
#define VIA_ID 4
#endif
#if defined(CONFIG_PCI)
@@ -377,13 +381,12 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_TSEC1_NAME "TSEC0"
#define CONFIG_TSEC2 1
#define CONFIG_TSEC2_NAME "TSEC1"
#undef CONFIG_MPC85XX_FEC
#define TSEC1_PHY_ADDR 0
#define TSEC2_PHY_ADDR 1
#define FEC_PHY_ADDR 3
#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
#define FEC_PHYIDX 0
#define TSEC1_FLAGS TSEC_GIGABIT
#define TSEC2_FLAGS TSEC_GIGABIT
/* Options are: TSEC[0-1] */
#define CONFIG_ETHPRIME "TSEC0"
@@ -475,6 +478,7 @@ extern unsigned long get_clock_freq(void);
/* The mac addresses for all ethernet interface */
#if defined(CONFIG_TSEC_ENET)
#define CONFIG_HAS_ETH0
#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
#define CONFIG_HAS_ETH1
#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD

162
include/configs/MPC8544DS.h
View File

@@ -34,14 +34,14 @@
#define CONFIG_MPC8544 1
#define CONFIG_MPC8544DS 1
#undef CONFIG_PCI /* Enable PCI/PCIE */
#undef CONFIG_PCI1 /* PCI controller 1 */
#undef CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
#undef CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */
#undef CONFIG_PCIE3 /* PCIE controler 3 (ULI bridge) */
#undef CONFIG_FSL_PCI_INIT /* Use common FSL init code */
#define CONFIG_PCI 1 /* Enable PCI/PCIE */
#define CONFIG_PCI1 1 /* PCI controller 1 */
#define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
#define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */
#define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
#undef CONFIG_DDR_DLL
@@ -52,6 +52,7 @@
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
#define CONFIG_DDR_ECC_CMD
#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
/*
* When initializing flash, if we cannot find the manufacturer ID,
@@ -70,7 +71,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
/*
* These can be toggled for performance analysis, otherwise use default.
*/
#define CONFIG_L2_CACHE /* toggle L2 cache */
#define CONFIG_L2_CACHE /* toggle L2 cache */
#define CONFIG_BTB /* toggle branch predition */
#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
#define CONFIG_CLEAR_LAW0 /* Clear LAW0 in cpu_init_r */
@@ -86,13 +87,13 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CFG_MEMTEST_START 0x00200000 /* memtest works on */
#define CFG_MEMTEST_END 0x00400000
#define CFG_ALT_MEMTEST
#define CONFIG_PANIC_HANG /* do not reset board on panic */
#define CONFIG_PANIC_HANG /* do not reset board on panic */
/*
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*/
#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
@@ -180,6 +181,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CFG_BR3_PRELIM 0xf8100801 /* port size 8bit */
#define CFG_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/
#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
#define PIXIS_BASE 0xf8100000 /* PIXIS registers */
#define PIXIS_ID 0x0 /* Board ID at offset 0 */
#define PIXIS_VER 0x1 /* Board version at offset 1 */
@@ -251,9 +253,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_OF_FLAT_TREE 1
#define CONFIG_OF_BOARD_SETUP 1
/* maximum size of the flat tree (8K) */
#define OF_FLAT_TREE_MAX_SIZE 8192
#define OF_CPU "PowerPC,8544@0"
#define OF_SOC "soc8544@e0000000"
#define OF_TBCLK (bd->bi_busfreq / 8)
@@ -281,7 +280,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
#define CFG_PCI1_IO_BASE 0x00000000
#define CFG_PCI1_IO_PHYS 0xe1000000
#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */
#define CFG_PCI1_IO_SIZE 0x00010000 /* 64k */
/* PCI view of System Memory */
#define CFG_PCI_MEMORY_BUS 0x00000000
@@ -293,27 +292,27 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CFG_PCIE2_MEM_PHYS CFG_PCIE2_MEM_BASE
#define CFG_PCIE2_MEM_SIZE 0x20000000 /* 512M */
#define CFG_PCIE2_IO_BASE 0x00000000
#define CFG_PCIE2_IO_PHYS 0xe2000000
#define CFG_PCIE2_IO_SIZE 0x00100000 /* 1M */
#define CFG_PCIE2_IO_PHYS 0xe1010000
#define CFG_PCIE2_IO_SIZE 0x00010000 /* 64k */
/* controller 1, Slot 2,tgtid 2, Base address a000 */
#define CFG_PCIE1_MEM_BASE 0xa0000000
#define CFG_PCIE1_MEM_PHYS CFG_PCIE1_MEM_BASE
#define CFG_PCIE1_MEM_SIZE 0x08000000 /* 128M */
#define CFG_PCIE1_MEM_BASE2 0xa8000000
#define CFG_PCIE1_MEM_PHYS2 CFG_PCIE1_MEM_BASE2
#define CFG_PCIE1_MEM_SIZE2 0x04000000 /* 64M */
#define CFG_PCIE1_IO_BASE 0x00000000 /* reuse mem LAW */
#define CFG_PCIE1_IO_PHYS 0xaf000000
#define CFG_PCIE1_IO_SIZE 0x00100000 /* 1M */
#define CFG_PCIE1_MEM_SIZE 0x10000000 /* 256M */
#define CFG_PCIE1_IO_BASE 0x00000000
#define CFG_PCIE1_IO_PHYS 0xe1020000
#define CFG_PCIE1_IO_SIZE 0x00010000 /* 64k */
/* controller 3, direct to uli, tgtid 3, Base address b000 */
#define CFG_PCIE3_MEM_BASE 0xb0000000
#define CFG_PCIE3_MEM_PHYS CFG_PCIE3_MEM_BASE
#define CFG_PCIE3_MEM_SIZE 0x10000000 /* 256M */
#define CFG_PCIE3_MEM_SIZE 0x00100000 /* 1M */
#define CFG_PCIE3_IO_BASE 0x00000000
#define CFG_PCIE3_IO_PHYS 0xe3000000
#define CFG_PCIE3_IO_PHYS 0xb0100000 /* reuse mem LAW */
#define CFG_PCIE3_IO_SIZE 0x00100000 /* 1M */
#define CFG_PCIE3_MEM_BASE2 0xb0200000
#define CFG_PCIE3_MEM_PHYS2 CFG_PCIE3_MEM_BASE2
#define CFG_PCIE3_MEM_SIZE2 0x00200000 /* 1M */
#if defined(CONFIG_PCI)
@@ -344,7 +343,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SATA_ULI5288
#define CFG_SCSI_MAX_SCSI_ID 4
#define CFG_SCSI_MAX_LUN 1
#define CFG_SCSI_MAX_DEVICE (CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN)
#define CFG_SCSI_MAX_DEVICE (CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN)
#define CFG_SCSI_MAXDEVICE CFG_SCSI_MAX_DEVICE
#endif /* SCSCI */
@@ -354,7 +353,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#if defined(CONFIG_TSEC_ENET)
#ifndef CONFIG_NET_MULTI
#define CONFIG_NET_MULTI 1
#define CONFIG_NET_MULTI 1
#endif
#define CONFIG_MII 1 /* MII PHY management */
@@ -363,18 +362,19 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_TSEC1_NAME "eTSEC1"
#define CONFIG_TSEC3 1
#define CONFIG_TSEC3_NAME "eTSEC3"
#undef CONFIG_MPC85XX_FEC
#define TSEC1_PHY_ADDR 0
#define TSEC3_PHY_ADDR 1
#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC1_PHYIDX 0
#define TSEC3_PHYIDX 0
#define CONFIG_ETHPRIME "eTSEC1"
#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
#endif /* CONFIG_TSEC_ENET */
/*
@@ -392,7 +392,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
/*
* BOOTP options
*/
@@ -415,6 +414,8 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_CMD_PCI
#define CONFIG_CMD_BEDBUG
#define CONFIG_CMD_NET
#define CONFIG_CMD_SCSI
#define CONFIG_CMD_EXT2
#endif
@@ -441,10 +442,10 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
/* Cache Configuration */
#define CFG_DCACHE_SIZE 32768
#define CFG_DCACHE_SIZE 32768
#define CFG_CACHELINE_SIZE 32
#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
@@ -469,6 +470,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
/* The mac addresses for all ethernet interface */
#if defined(CONFIG_TSEC_ENET)
#define CONFIG_HAS_ETH0
#define CONFIG_ETHADDR 00:E0:0C:02:00:FD
#define CONFIG_HAS_ETH1
#define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD
@@ -482,7 +484,8 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_HOSTNAME 8544ds_unknown
#define CONFIG_ROOTPATH /nfs/mpc85xx
#define CONFIG_BOOTFILE 8544ds_tmt/uImage.uboot
#define CONFIG_BOOTFILE 8544ds/uImage.uboot
#define CONFIG_UBOOTPATH 8544ds/u-boot.bin /* TFTP server */
#define CONFIG_SERVERIP 192.168.0.1
#define CONFIG_GATEWAYIP 192.168.0.1
@@ -491,7 +494,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
#define CONFIG_BAUDRATE 115200
@@ -499,10 +502,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define PCIE_ENV \
"pciereg=md ${a}000 6; md ${a}020 4; md ${a}bf8 2; echo o;md ${a}c00 25;" \
"echo i; md ${a}da0 15; echo e;md ${a}e00 e; echo d; md ${a}f00 c\0" \
"pcie1regs=setenv a e000a; run pciereg\0" \
"pcie2regs=setenv a e0009; run pciereg\0" \
"pcie3regs=setenv a e000b; run pciereg\0" \
"pcieerr=md ${a}020 1; md ${a}e00;" \
"pcieerr=md ${a}020 1; md ${a}e00 e;" \
"pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \
"pci d.w $b.0 56 1;" \
"pci d $b.0 104 1;pci d $b.0 110 1;pci d $b.0 130 1\0" \
@@ -511,12 +511,18 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
"pci w $b.0 104 ffffffff; pci w $b.0 110 ffffffff;" \
"pci w $b.0 130 ffffffff\0" \
"pciecfg=pci d $b.0 0 20; pci d $b.0 100 e; pci d $b.0 400 69\0" \
"pcie1err=setenv a e000a; run pcieerr\0" \
"pcie2err=setenv a e0009; run pcieerr\0" \
"pcie3err=setenv a e000b; run pcieerr\0" \
"pcie1errc=setenv a e000a; run pcieerrc\0" \
"pcie2errc=setenv a e0009; run pcieerrc\0" \
"pcie3errc=setenv a e000b; run pcieerrc\0"
"pcie1regs=setenv a e000a; run pciereg\0" \
"pcie2regs=setenv a e0009; run pciereg\0" \
"pcie3regs=setenv a e000b; run pciereg\0" \
"pcie1cfg=setenv b 3; run pciecfg\0" \
"pcie2cfg=setenv b 5; run pciecfg\0" \
"pcie3cfg=setenv b 0; run pciecfg\0" \
"pcie1err=setenv a e000a; setenv b 3; run pcieerr\0" \
"pcie2err=setenv a e0009; setenv b 5; run pcieerr\0" \
"pcie3err=setenv a e000b; setenv b 0; run pcieerr\0" \
"pcie1errc=setenv a e000a; setenv b 3; run pcieerrc\0" \
"pcie2errc=setenv a e0009; setenv b 5; run pcieerrc\0" \
"pcie3errc=setenv a e000b; setenv b 0; run pcieerrc\0"
#else
#define PCIE_ENV ""
#endif
@@ -524,14 +530,14 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#if defined(CONFIG_PCI1)
#define PCI_ENV \
"pcireg=md ${a}000 3; echo o;md ${a}c00 25; echo i; md ${a}da0 15;" \
"echo e;md ${a}e00 9\0" \
"echo e;md ${a}e00 9\0" \
"pci1regs=setenv a e0008; run pcireg\0" \
"pcierr=md ${a}e00 8; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \
"pci d.w $b.0 56 1\0" \
"pcierrc=mw ${a}e00 ffffffff; pci w.b $b.0 7 ff; pci w.w $b.0 1e ffff;" \
"pci w.w $b.0 56 ffff\0" \
"pci1err=setenv a e0008; run pcierr\0" \
"pci1errc=setenv a e0008; run pcierrc\0"
"pcierrc=mw ${a}e00 ffffffff; mw ${a}e0c 0; pci w.b $b.0 7 ff;" \
"pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff\0" \
"pci1err=setenv a e0008; setenv b 7; run pcierr\0" \
"pci1errc=setenv a e0008; setenv b 7; run pcierrc\0"
#else
#define PCI_ENV ""
#endif
@@ -551,25 +557,39 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define ENET_ENV ""
#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
"tftpflash=tftpboot $loadaddr $uboot; " \
"protect off " MK_STR(TEXT_BASE) " +$filesize; " \
"erase " MK_STR(TEXT_BASE) " +$filesize; " \
"cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
"protect on " MK_STR(TEXT_BASE) " +$filesize; " \
"cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
"consoledev=ttyS0\0" \
"ramdiskaddr=2000000\0" \
"ramdiskfile=8544ds_tmt/ramdisk.uboot\0" \
"fdtaddr=400000\0" \
"fdtfile=8544ds_tmt/mpc8544ds.dtb\0" \
"eoi=mw e00400b0 0\0" \
"iack=md e00400a0 1\0" \
"ramdiskfile=8544ds/ramdisk.uboot\0" \
"dtbaddr=c00000\0" \
"dtbfile=8544ds/mpc8544ds.dtb\0" \
"bdev=sda3\0" \
"eoi=mw e00400b0 0\0" \
"iack=md e00400a0 1\0" \
"ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4; md ${a}bf0 4;" \
"md ${a}e00 3; md ${a}e20 3; md ${a}e40 7; md ${a}f00 5\0" \
"ddrregs=setenv a e0002; run ddrreg\0" \
"ddrregs=setenv a e0002; run ddrreg\0" \
"gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}b20 3;" \
"md ${a}e00 1; md ${a}e60 1; md ${a}ef0 15\0" \
"guregs=setenv a e00e0; run gureg\0" \
"md ${a}e00 1; md ${a}e60 1; md ${a}ef0 15\0" \
"guregs=setenv a e00e0; run gureg\0" \
"ecmreg=md ${a}000 1; md ${a}010 1; md ${a}bf8 2; md ${a}e00 6\0" \
"ecmregs=setenv a e0001; run ecmreg\0" \
PCIE_ENV \
PCI_ENV \
"ecmregs=setenv a e0001; run ecmreg\0" \
"lawregs=md e0000c08 4b\0" \
"lbcregs=md e0005000 36\0" \
"dma0regs=md e0021100 12\0" \
"dma1regs=md e0021180 12\0" \
"dma2regs=md e0021200 12\0" \
"dma3regs=md e0021280 12\0" \
PCIE_ENV \
PCI_ENV \
ENET_ENV
@@ -579,23 +599,23 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $loadaddr $bootfile;" \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr - $fdtaddr"
"tftp $dtbaddr $dtbfile;" \
"bootm $loadaddr - $dtbaddr"
#define CONFIG_RAMBOOTCOMMAND \
#define CONFIG_RAMBOOTCOMMAND \
"setenv bootargs root=/dev/ram rw " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $ramdiskaddr $ramdiskfile;" \
"tftp $loadaddr $bootfile;" \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr $ramdiskaddr $fdtaddr"
"tftp $dtbaddr $dtbfile;" \
"bootm $loadaddr $ramdiskaddr $dtbaddr"
#define CONFIG_BOOTCOMMAND \
"setenv bootargs root=/dev/sda3 rw " \
#define CONFIG_BOOTCOMMAND \
"setenv bootargs root=/dev/$bdev rw " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $loadaddr $bootfile;" \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr - $fdtaddr"
"tftp $dtbaddr $dtbfile;" \
"bootm $loadaddr - $dtbaddr"
#endif /* __CONFIG_H */

346
include/configs/MPC8548CDS.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright 2004 Freescale Semiconductor.
* Copyright 2004, 2007 Freescale Semiconductor.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -11,7 +11,7 @@
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
@@ -36,8 +36,14 @@
#define CONFIG_MPC8548 1 /* MPC8548 specific */
#define CONFIG_MPC8548CDS 1 /* MPC8548CDS board specific */
#define CONFIG_PCI
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_PCI /* enable any pci type devices */
#define CONFIG_PCI1 /* PCI controller 1 */
#define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
#undef CONFIG_RIO
#undef CONFIG_PCI2
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
#define CONFIG_DDR_DLL /* possible DLL fix needed */
@@ -46,6 +52,7 @@
#define CONFIG_DDR_ECC /* only for ECC DDR module */
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
/*
@@ -65,16 +72,16 @@ extern unsigned long get_clock_freq(void);
/*
* These can be toggled for performance analysis, otherwise use default.
*/
#define CONFIG_L2_CACHE /* toggle L2 cache */
#define CONFIG_BTB /* toggle branch predition */
#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
#define CONFIG_L2_CACHE /* toggle L2 cache */
#define CONFIG_BTB /* toggle branch predition */
#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
#define CONFIG_CLEAR_LAW0 /* Clear LAW0 in cpu_init_r */
/*
* Only possible on E500 Version 2 or newer cores.
*/
#define CONFIG_ENABLE_36BIT_PHYS 1
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
#undef CFG_DRAM_TEST /* memory test, takes time */
@@ -85,10 +92,14 @@ extern unsigned long get_clock_freq(void);
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*/
#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
#define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000)
#define CFG_PCI2_ADDR (CFG_CCSRBAR+0x9000)
#define CFG_PCIE1_ADDR (CFG_CCSRBAR+0xa000)
/*
* DDR Setup
*/
@@ -106,7 +117,6 @@ extern unsigned long get_clock_freq(void);
#undef CONFIG_CLOCKS_IN_MHZ
/*
* Local Bus Definitions
*/
@@ -124,9 +134,9 @@ extern unsigned long get_clock_freq(void);
* Use GPCM = BRx[24:26] = 000
* Valid = BRx[31] = 1
*
* 0 4 8 12 16 20 24 28
* 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0
* 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1
* 0 4 8 12 16 20 24 28
* 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0
* 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1
*
* OR0, OR1:
* Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
@@ -137,11 +147,12 @@ extern unsigned long get_clock_freq(void);
* TRLX = use relaxed timing = ORx[29] = 1
* EAD = use external address latch delay = OR[31] = 1
*
* 0 4 8 12 16 20 24 28
* 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx
* 0 4 8 12 16 20 24 28
* 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx
*/
#define CFG_FLASH_BASE 0xff000000 /* start of FLASH 8M */
#define CFG_BOOT_BLOCK 0xff000000 /* boot TLB block */
#define CFG_FLASH_BASE CFG_BOOT_BLOCK /* start of FLASH 16M */
#define CFG_BR0_PRELIM 0xff801001
#define CFG_BR1_PRELIM 0xff001001
@@ -156,7 +167,7 @@ extern unsigned long get_clock_freq(void);
#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
#define CFG_FLASH_CFI_DRIVER
#define CFG_FLASH_CFI
@@ -166,7 +177,12 @@ extern unsigned long get_clock_freq(void);
/*
* SDRAM on the Local Bus
*/
#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
#define CFG_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */
#define CFG_LBC_CACHE_SIZE 64
#define CFG_LBC_NONCACHE_BASE 0xf8000000 /* Localbus non-cacheable */
#define CFG_LBC_NONCACHE_SIZE 64
#define CFG_LBC_SDRAM_BASE CFG_LBC_CACHE_BASE /* Localbus SDRAM */
#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
/*
@@ -180,14 +196,14 @@ extern unsigned long get_clock_freq(void);
* SDRAM for MSEL = BR2[24:26] = 011
* Valid = BR[31] = 1
*
* 0 4 8 12 16 20 24 28
* 0 4 8 12 16 20 24 28
* 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
*
* FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into
* FIXME: the top 17 bits of BR2.
*/
#define CFG_BR2_PRELIM 0xf0001861
#define CFG_BR2_PRELIM 0xf0001861
/*
* The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
@@ -196,19 +212,19 @@ extern unsigned long get_clock_freq(void);
* 64MB mask for AM, OR2[0:7] = 1111 1100
* XAM, OR2[17:18] = 11
* 9 columns OR2[19-21] = 010
* 13 rows OR2[23-25] = 100
* 13 rows OR2[23-25] = 100
* EAD set for extra time OR[31] = 1
*
* 0 4 8 12 16 20 24 28
* 0 4 8 12 16 20 24 28
* 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
*/
#define CFG_OR2_PRELIM 0xfc006901
#define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */
#define CFG_LBC_LBCR 0x00000000 /* LB config reg */
#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
#define CFG_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
#define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */
#define CFG_LBC_LBCR 0x00000000 /* LB config reg */
#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
#define CFG_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
/*
* LSDMR masks
@@ -236,7 +252,7 @@ extern unsigned long get_clock_freq(void);
/*
* Common settings for all Local Bus SDRAM commands.
* At run time, either BSMA1516 (for CPU 1.1)
* or BSMA1617 (for CPU 1.0) (old)
* or BSMA1617 (for CPU 1.0) (old)
* is OR'ed in too.
*/
#define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFCR16 \
@@ -256,61 +272,63 @@ extern unsigned long get_clock_freq(void);
* Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
* port-size = 8-bits = BR[19:20] = 01
* no parity checking = BR[21:22] = 00
* GPMC for MSEL = BR[24:26] = 000
* Valid = BR[31] = 1
* GPMC for MSEL = BR[24:26] = 000
* Valid = BR[31] = 1
*
* 0 4 8 12 16 20 24 28
* 0 4 8 12 16 20 24 28
* 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
*
* For OR3, need:
* 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0
* 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0
* disable buffer ctrl OR[19] = 0
* CSNT OR[20] = 1
* ACS OR[21:22] = 11
* XACS OR[23] = 1
* CSNT OR[20] = 1
* ACS OR[21:22] = 11
* XACS OR[23] = 1
* SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe
* SETA OR[28] = 0
* TRLX OR[29] = 1
* EHTR OR[30] = 1
* EAD extra time OR[31] = 1
* SETA OR[28] = 0
* TRLX OR[29] = 1
* EHTR OR[30] = 1
* EAD extra time OR[31] = 1
*
* 0 4 8 12 16 20 24 28
* 0 4 8 12 16 20 24 28
* 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
*/
#define CADMUS_BASE_ADDR 0xf8000000
#define CFG_BR3_PRELIM 0xf8000801
#define CFG_OR3_PRELIM 0xfff00ff7
#define CFG_BR3_PRELIM 0xf8000801
#define CFG_OR3_PRELIM 0xfff00ff7
#define CONFIG_L1_INIT_RAM
#define CFG_INIT_RAM_LOCK 1
#define CFG_INIT_RAM_LOCK 1
#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
#define CFG_INIT_L2_ADDR 0xf8f80000 /* relocate boot L2SRAM */
#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
/* Serial Port */
#define CONFIG_CONS_INDEX 2
#define CONFIG_CONS_INDEX 2
#undef CONFIG_SERIAL_SOFTWARE_FIFO
#define CFG_NS16550
#define CFG_NS16550_SERIAL
#define CFG_NS16550_REG_SIZE 1
#define CFG_NS16550_REG_SIZE 1
#define CFG_NS16550_CLK get_bus_freq(0)
#define CFG_BAUDRATE_TABLE \
#define CFG_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
/* Use the HUSH parser */
#define CFG_HUSH_PARSER
#ifdef CFG_HUSH_PARSER
#ifdef CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
@@ -318,9 +336,6 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_OF_FLAT_TREE 1
#define CONFIG_OF_BOARD_SETUP 1
/* maximum size of the flat tree (8K) */
#define OF_FLAT_TREE_MAX_SIZE 8192
#define OF_CPU "PowerPC,8548@0"
#define OF_SOC "soc8548@e0000000"
#define OF_TBCLK (bd->bi_busfreq / 8)
@@ -331,55 +346,74 @@ extern unsigned long get_clock_freq(void);
*/
#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
#define CONFIG_HARD_I2C /* I2C with hardware support*/
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_EEPROM_ADDR 0x57
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
#define CFG_I2C_OFFSET 0x3000
/*
* General PCI
* Memory space is mapped 1-1, but I/O space must start from 0.
*/
#define CFG_PCI_PHYS 0x80000000 /* 1G PCI TLB */
#define CFG_PCI1_MEM_BASE 0x80000000
#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
#define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */
#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
#define CFG_PCI1_IO_BASE 0x00000000
#define CFG_PCI1_IO_PHYS 0xe2000000
#define CFG_PCI1_IO_SIZE 0x00800000 /* 8M */
#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */
#define CFG_PCI2_MEM_BASE 0x90000000
#ifdef CONFIG_PCI2
#define CFG_PCI2_MEM_BASE 0xa0000000
#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE
#define CFG_PCI2_MEM_SIZE 0x10000000 /* 256M */
#define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */
#define CFG_PCI2_IO_BASE 0x00000000
#define CFG_PCI2_IO_PHYS 0xe2800000
#define CFG_PCI2_IO_SIZE 0x00800000 /* 8M */
#define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */
#endif
#define CFG_PEX_MEM_BASE 0xa0000000
#define CFG_PEX_MEM_PHYS CFG_PEX_MEM_BASE
#define CFG_PEX_MEM_SIZE 0x20000000 /* 512M */
#define CFG_PEX_IO_BASE 0x00000000
#define CFG_PEX_IO_PHYS 0xe3000000
#define CFG_PEX_IO_SIZE 0x01000000 /* 16M */
#ifdef CONFIG_PCIE1
#define CFG_PCIE1_MEM_BASE 0xa0000000
#define CFG_PCIE1_MEM_PHYS CFG_PCIE1_MEM_BASE
#define CFG_PCIE1_MEM_SIZE 0x20000000 /* 512M */
#define CFG_PCIE1_IO_BASE 0x00000000
#define CFG_PCIE1_IO_PHYS 0xe3000000
#define CFG_PCIE1_IO_SIZE 0x00100000 /* 1M */
#endif
#ifdef CONFIG_RIO
/*
* RapidIO MMU
*/
#define CFG_RIO_MEM_BASE 0xC0000000
#define CFG_RIO_MEM_SIZE 0x20000000 /* 512M */
#endif
#ifdef CONFIG_LEGACY
#define BRIDGE_ID 17
#define VIA_ID 2
#else
#define BRIDGE_ID 28
#define VIA_ID 4
#endif
#if defined(CONFIG_PCI)
#define CONFIG_NET_MULTI
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_85XX_PCI2
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
/* PCI view of System Memory */
#define CFG_PCI_MEMORY_BUS 0x00000000
#define CFG_PCI_MEMORY_PHYS 0x00000000
#define CFG_PCI_MEMORY_SIZE 0x80000000
#endif /* CONFIG_PCI */
@@ -387,7 +421,7 @@ extern unsigned long get_clock_freq(void);
#if defined(CONFIG_TSEC_ENET)
#ifndef CONFIG_NET_MULTI
#define CONFIG_NET_MULTI 1
#define CONFIG_NET_MULTI 1
#endif
#define CONFIG_MII 1 /* MII PHY management */
@@ -397,7 +431,7 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_TSEC2_NAME "eTSEC1"
#define CONFIG_TSEC3 1
#define CONFIG_TSEC3_NAME "eTSEC2"
#undef CONFIG_TSEC4
#define CONFIG_TSEC4
#define CONFIG_TSEC4_NAME "eTSEC3"
#undef CONFIG_MPC85XX_FEC
@@ -410,10 +444,14 @@ extern unsigned long get_clock_freq(void);
#define TSEC2_PHYIDX 0
#define TSEC3_PHYIDX 0
#define TSEC4_PHYIDX 0
#define TSEC1_FLAGS TSEC_GIGABIT
#define TSEC2_FLAGS TSEC_GIGABIT
#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
/* Options are: eTSEC[0-3] */
#define CONFIG_ETHPRIME "eTSEC0"
#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
#endif /* CONFIG_TSEC_ENET */
/*
@@ -473,7 +511,7 @@ extern unsigned long get_clock_freq(void);
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
/* Cache Configuration */
#define CFG_DCACHE_SIZE 32768
@@ -501,58 +539,154 @@ extern unsigned long get_clock_freq(void);
/* The mac addresses for all ethernet interface */
#if defined(CONFIG_TSEC_ENET)
#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
#define CONFIG_HAS_ETH0
#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
#define CONFIG_HAS_ETH1
#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
#define CONFIG_HAS_ETH2
#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
#define CONFIG_HAS_ETH3
#define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD
#define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD
#endif
#define CONFIG_IPADDR 192.168.1.253
#define CONFIG_IPADDR 192.168.1.253
#define CONFIG_HOSTNAME unknown
#define CONFIG_ROOTPATH /nfsroot
#define CONFIG_BOOTFILE your.uImage
#define CONFIG_HOSTNAME unknown
#define CONFIG_ROOTPATH /nfsroot
#define CONFIG_BOOTFILE 8548cds/uImage.uboot
#define CONFIG_UBOOTPATH 8548cds/u-boot.bin /* TFTP server */
#define CONFIG_SERVERIP 192.168.1.1
#define CONFIG_SERVERIP 192.168.1.1
#define CONFIG_GATEWAYIP 192.168.1.1
#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/
#define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
#define CONFIG_BAUDRATE 115200
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"consoledev=ttyS1\0" \
"ramdiskaddr=600000\0" \
"ramdiskfile=your.ramdisk.u-boot\0" \
"fdtaddr=400000\0" \
"fdtfile=your.fdt.dtb\0"
#if defined(CONFIG_PCIE1)
#define PCIE_ENV \
"pciereg=md ${a}000 6; md ${a}020 4; md ${a}bf8 2; echo o;md ${a}c00 25;" \
"echo i; md ${a}da0 15; echo e;md ${a}e00 e; echo d; md ${a}f00 c\0" \
"pcieerr=md ${a}020 1; md ${a}e00 e; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \
"pci d.w $b.0 56 1; pci d $b.0 104 1; pci d $b.0 110 1;" \
"pci d $b.0 130 1\0" \
"pcieerrc=mw ${a}020 ffffffff; mw ${a}e00 ffffffff; pci w.b $b.0 7 ff;" \
"pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff; pci w $b.0 104 ffffffff;"\
"pci w $b.0 110 ffffffff; pci w $b.0 130 ffffffff\0" \
"pciecfg=pci d $b.0 0 20; pci d $b.0 100 e; pci d $b.0 400 69\0" \
"pcie1regs=setenv a e000a; run pciereg\0" \
"pcie1cfg=setenv b 3; run pciecfg\0" \
"pcie1err=setenv a e000a; setenv b 3; run pcieerr\0" \
"pcie1errc=setenv a e000a; setenv b 3; run pcieerrc\0"
#else
#define PCIE_ENV ""
#endif
#if defined(CONFIG_PCI1) || defined(CONFIG_PCI2)
#define PCI_ENV \
"pcireg=md ${a}000 3; echo o;md ${a}c00 25; echo i; md ${a}da0 15;" \
"echo e;md ${a}e00 9\0" \
"pcierr=md ${a}e00 8; pci d.b $b.0 7 1;pci d.w $b.0 1e 1;" \
"pci d.w $b.0 56 1\0" \
"pcierrc=mw ${a}e00 ffffffff; mw ${a}e0c 0; pci w.b $b.0 7 ff;" \
"pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff\0"
#else
#define PCI_ENV ""
#endif
#define CONFIG_NFSBOOTCOMMAND \
"setenv bootargs root=/dev/nfs rw " \
"nfsroot=$serverip:$rootpath " \
#if defined(CONFIG_PCI1)
#define PCI_ENV1 \
"pci1regs=setenv a e0008; run pcireg\0" \
"pci1err=setenv a e0008; setenv b 0; run pcierr\0" \
"pci1errc=setenv a e0008; setenv b 0; run pcierrc\0"
#else
#define PCI_ENV1 ""
#endif
#if defined(CONFIG_PCI2)
#define PCI_ENV2 \
"pci2regs=setenv a e0009; run pcireg\0" \
"pci2err=setenv a e0009; setenv b 123; run pcierr\0" \
"pci2errc=setenv a e0009; setenv b 123; run pcierrc\0"
#else
#define PCI_ENV2 ""
#endif
#if defined(CONFIG_TSEC_ENET)
#define ENET_ENV \
"enetreg1=md ${a}000 2; md ${a}010 9; md ${a}050 4; md ${a}08c 1;" \
"md ${a}098 2\0" \
"enetregt=echo t;md ${a}100 6; md ${a}140 2; md ${a}180 10; md ${a}200 10\0" \
"enetregr=echo r;md ${a}300 6; md ${a}330 5; md ${a}380 10; md ${a}400 10\0" \
"enetregm=echo mac;md ${a}500 5; md ${a}520 28;echo fifo;md ${a}a00 1;" \
"echo mib;md ${a}680 31\0" \
"enetreg=run enetreg1; run enetregm; run enetregt; run enetregr\0" \
"enet1regs=setenv a e0024; run enetreg\0" \
"enet2regs=setenv a e0025; run enetreg\0" \
"enet3regs=setenv a e0026; run enetreg\0" \
"enet4regs=setenv a e0027; run enetreg\0"
#else
#define ENET_ENV ""
#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
"tftpflash=tftpboot $loadaddr $uboot; " \
"protect off " MK_STR(TEXT_BASE) " +$filesize; " \
"erase " MK_STR(TEXT_BASE) " +$filesize; " \
"cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
"protect on " MK_STR(TEXT_BASE) " +$filesize; " \
"cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
"consoledev=ttyS1\0" \
"ramdiskaddr=2000000\0" \
"ramdiskfile=ramdisk.uboot\0" \
"fdtaddr=c00000\0" \
"fdtfile=mpc8548cds.dtb\0" \
"eoi=mw e00400b0 0\0" \
"iack=md e00400a0 1\0" \
"ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4; md ${a}bf0 4;" \
"md ${a}e00 3; md ${a}e20 3; md ${a}e40 7; md ${a}f00 5\0" \
"ddrregs=setenv a e0002; run ddrreg\0" \
"gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}b20 3;" \
"md ${a}e00 1; md ${a}e60 1; md ${a}ef0 15\0" \
"guregs=setenv a e00e0; run gureg\0" \
"ecmreg=md ${a}000 1; md ${a}010 1; md ${a}bf8 2; md ${a}e00 6\0" \
"ecmregs=setenv a e0001; run ecmreg\0" \
"lawregs=md e0000c08 4b\0" \
"lbcregs=md e0005000 36\0" \
"dma0regs=md e0021100 12\0" \
"dma1regs=md e0021180 12\0" \
"dma2regs=md e0021200 12\0" \
"dma3regs=md e0021280 12\0" \
PCIE_ENV \
PCI_ENV \
PCI_ENV1 \
PCI_ENV2 \
ENET_ENV
#define CONFIG_NFSBOOTCOMMAND \
"setenv bootargs root=/dev/nfs rw " \
"nfsroot=$serverip:$rootpath " \
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $loadaddr $bootfile;" \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $loadaddr $bootfile;" \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr - $fdtaddr"
#define CONFIG_RAMBOOTCOMMAND \
"setenv bootargs root=/dev/ram rw " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $ramdiskaddr $ramdiskfile;" \
"tftp $loadaddr $bootfile;" \
"bootm $loadaddr $ramdiskaddr"
"setenv bootargs root=/dev/ram rw " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $ramdiskaddr $ramdiskfile;" \
"tftp $loadaddr $bootfile;" \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr $ramdiskaddr $fdtaddr"
#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
#endif /* __CONFIG_H */

16
include/configs/MPC8555CDS.h
View File

@@ -312,9 +312,6 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_OF_FLAT_TREE 1
#define CONFIG_OF_BOARD_SETUP 1
/* maximum size of the flat tree (8K) */
#define OF_FLAT_TREE_MAX_SIZE 8192
#define OF_CPU "PowerPC,8555@0"
#define OF_SOC "soc8555@e0000000"
#define OF_TBCLK (bd->bi_busfreq / 8)
@@ -350,6 +347,13 @@ extern unsigned long get_clock_freq(void);
#define CFG_PCI2_IO_PHYS 0xe2100000
#define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */
#ifdef CONFIG_LEGACY
#define BRIDGE_ID 17
#define VIA_ID 2
#else
#define BRIDGE_ID 28
#define VIA_ID 4
#endif
#if defined(CONFIG_PCI)
@@ -377,13 +381,12 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_TSEC1_NAME "TSEC0"
#define CONFIG_TSEC2 1
#define CONFIG_TSEC2_NAME "TSEC1"
#undef CONFIG_MPC85XX_FEC
#define TSEC1_PHY_ADDR 0
#define TSEC2_PHY_ADDR 1
#define FEC_PHY_ADDR 3
#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
#define FEC_PHYIDX 0
#define TSEC1_FLAGS TSEC_GIGABIT
#define TSEC2_FLAGS TSEC_GIGABIT
/* Options are: TSEC[0-1] */
#define CONFIG_ETHPRIME "TSEC0"
@@ -475,6 +478,7 @@ extern unsigned long get_clock_freq(void);
/* The mac addresses for all ethernet interface */
#if defined(CONFIG_TSEC_ENET)
#define CONFIG_HAS_ETH0
#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
#define CONFIG_HAS_ETH1
#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD

7
include/configs/MPC8560ADS.h
View File

@@ -292,9 +292,6 @@
#define CONFIG_OF_FLAT_TREE 1
#define CONFIG_OF_BOARD_SETUP 1
/* maximum size of the flat tree (8K) */
#define OF_FLAT_TREE_MAX_SIZE 8192
#define OF_CPU "PowerPC,8560@0"
#define OF_SOC "soc8560@e0000000"
#define OF_TBCLK (bd->bi_busfreq / 8)
@@ -360,11 +357,12 @@
#define CONFIG_TSEC1_NAME "TSEC0"
#define CONFIG_TSEC2 1
#define CONFIG_TSEC2_NAME "TSEC1"
#undef CONFIG_MPC85XX_FEC
#define TSEC1_PHY_ADDR 0
#define TSEC2_PHY_ADDR 1
#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
#define TSEC1_FLAGS TSEC_GIGABIT
#define TSEC2_FLAGS TSEC_GIGABIT
/* Options are: TSEC[0-1] */
#define CONFIG_ETHPRIME "TSEC0"
@@ -521,6 +519,7 @@
/* The mac addresses for all ethernet interface */
#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
#define CONFIG_HAS_ETH0
#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
#define CONFIG_HAS_ETH1
#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD

82
include/configs/MPC8568MDS.h
View File

@@ -28,20 +28,21 @@
/* High Level Configuration Options */
#define CONFIG_BOOKE 1 /* BOOKE */
#define CONFIG_E500 1 /* BOOKE e500 family */
#define CONFIG_E500 1 /* BOOKE e500 family */
#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48/68 */
#define CONFIG_MPC8568 1 /* MPC8568 specific */
#define CONFIG_MPC8568MDS 1 /* MPC8568MDS board specific */
#undef CONFIG_PCI
#define CONFIG_PCI
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_QE /* Enable QE */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
#define CONFIG_DDR_DLL /* possible DLL fix needed */
/*#define CONFIG_DDR_2T_TIMING Sets the 2T timing bit */
/*#define CONFIG_DDR_ECC*/ /* only for ECC DDR module */
/*#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER*/ /* DDR controller or DMA? */
/*#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER*/ /* DDR controller or DMA? */
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
@@ -62,9 +63,9 @@ extern unsigned long get_clock_freq(void);
/*
* These can be toggled for performance analysis, otherwise use default.
*/
/*#define CONFIG_L2_CACHE*/ /* toggle L2 cache */
#define CONFIG_BTB /* toggle branch predition */
#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
#define CONFIG_L2_CACHE /* toggle L2 cache */
#define CONFIG_BTB /* toggle branch predition */
#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
/*
* Only possible on E500 Version 2 or newer cores.
@@ -292,11 +293,9 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_OF_FLAT_TREE 1
#define CONFIG_OF_BOARD_SETUP 1
/* maximum size of the flat tree (8K) */
#define OF_FLAT_TREE_MAX_SIZE 8192
#define OF_CPU "PowerPC,8568@0"
#define OF_SOC "soc8568@e0000000"
#define OF_QE "qe@e0080000"
#define OF_TBCLK (bd->bi_busfreq / 8)
#define OF_STDOUT_PATH "/soc8568@e0000000/serial@4600"
@@ -306,11 +305,14 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
#define CONFIG_HARD_I2C /* I2C with hardware support*/
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CONFIG_I2C_MULTI_BUS
#define CONFIG_I2C_CMD_TREE
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_EEPROM_ADDR 0x57
#define CFG_I2C_EEPROM_ADDR 0x52
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
#define CFG_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */
#define CFG_I2C_OFFSET 0x3000
#define CFG_I2C2_OFFSET 0x3100
/*
* General PCI
@@ -318,7 +320,7 @@ extern unsigned long get_clock_freq(void);
*/
#define CFG_PCI1_MEM_BASE 0x80000000
#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
#define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */
#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
#define CFG_PCI1_IO_BASE 0x00000000
#define CFG_PCI1_IO_PHYS 0xe2000000
#define CFG_PCI1_IO_SIZE 0x00800000 /* 8M */
@@ -337,6 +339,44 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_NET_MULTI
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#ifdef CONFIG_QE
/*
* QE UEC ethernet configuration
*/
#define CONFIG_UEC_ETH
#ifndef CONFIG_TSEC_ENET
#define CONFIG_ETHPRIME "FSL UEC0"
#endif
#define CONFIG_PHY_MODE_NEED_CHANGE
#define CONFIG_eTSEC_MDIO_BUS
#ifdef CONFIG_eTSEC_MDIO_BUS
#define CONFIG_MIIM_ADDRESS 0xE0024520
#endif
#define CONFIG_UEC_ETH1 /* GETH1 */
#ifdef CONFIG_UEC_ETH1
#define CFG_UEC1_UCC_NUM 0 /* UCC1 */
#define CFG_UEC1_RX_CLK QE_CLK_NONE
#define CFG_UEC1_TX_CLK QE_CLK16
#define CFG_UEC1_ETH_TYPE GIGA_ETH
#define CFG_UEC1_PHY_ADDR 7
#define CFG_UEC1_INTERFACE_MODE ENET_1000_GMII
#endif
#define CONFIG_UEC_ETH2 /* GETH2 */
#ifdef CONFIG_UEC_ETH2
#define CFG_UEC2_UCC_NUM 1 /* UCC2 */
#define CFG_UEC2_RX_CLK QE_CLK_NONE
#define CFG_UEC2_TX_CLK QE_CLK16
#define CFG_UEC2_ETH_TYPE GIGA_ETH
#define CFG_UEC2_PHY_ADDR 1
#define CFG_UEC2_INTERFACE_MODE ENET_1000_GMII
#endif
#endif /* CONFIG_QE */
#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
@@ -345,21 +385,17 @@ extern unsigned long get_clock_freq(void);
#endif /* CONFIG_PCI */
#if defined(CONFIG_TSEC_ENET)
#ifndef CONFIG_NET_MULTI
#define CONFIG_NET_MULTI 1
#endif
#if defined(CONFIG_TSEC_ENET)
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_TSEC1 1
#define CONFIG_TSEC1_NAME "eTSEC0"
#define CONFIG_TSEC2 1
#define CONFIG_TSEC2_NAME "eTSEC1"
#undef CONFIG_TSEC3
#undef CONFIG_TSEC4
#undef CONFIG_MPC85XX_FEC
#define TSEC1_PHY_ADDR 2
#define TSEC2_PHY_ADDR 3
@@ -367,7 +403,10 @@ extern unsigned long get_clock_freq(void);
#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
/* Options are: eTSEC[0-3] */
#define TSEC1_FLAGS TSEC_GIGABIT
#define TSEC2_FLAGS TSEC_GIGABIT
/* Options are: eTSEC[0-1] */
#define CONFIG_ETHPRIME "eTSEC0"
#endif /* CONFIG_TSEC_ENET */
@@ -457,12 +496,15 @@ extern unsigned long get_clock_freq(void);
*/
/* The mac addresses for all ethernet interface */
#if defined(CONFIG_TSEC_ENET)
#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_UEC_ETH)
#define CONFIG_HAS_ETH0
#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
#define CONFIG_HAS_ETH1
#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
#define CONFIG_HAS_ETH2
#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
#define CONFIG_HAS_ETH3
#define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD
#endif
#define CONFIG_IPADDR 192.168.1.253

9
include/configs/MPC8641HPCN.h
View File

@@ -185,6 +185,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CFG_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/
#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
#define PIXIS_BASE 0xf8100000 /* PIXIS registers */
#define PIXIS_ID 0x0 /* Board ID at offset 0 */
#define PIXIS_VER 0x1 /* Board version at offset 1 */
@@ -268,9 +269,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_OF_FLAT_TREE 1
#define CONFIG_OF_BOARD_SETUP 1
/* maximum size of the flat tree (8K) */
#define OF_FLAT_TREE_MAX_SIZE 8192
#define OF_CPU "PowerPC,8641@0"
#define OF_SOC "soc8641@f8000000"
#define OF_TBCLK (bd->bi_busfreq / 4)
@@ -417,6 +415,10 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define TSEC2_PHYIDX 0
#define TSEC3_PHYIDX 0
#define TSEC4_PHYIDX 0
#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
#define CONFIG_ETHPRIME "eTSEC1"
@@ -604,6 +606,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD
#endif
#define CONFIG_HAS_ETH0 1
#define CONFIG_HAS_ETH1 1
#define CONFIG_HAS_ETH2 1
#define CONFIG_HAS_ETH3 1

60
include/configs/PLU405.h
View File

@@ -96,7 +96,6 @@
#define CONFIG_SUPPORT_VFAT
#define CONFIG_AUTO_UPDATE 1 /* autoupdate via compactflash */
#define CONFIG_AUTO_UPDATE_SHOW 1 /* use board show routine */
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -168,38 +167,18 @@
* NAND-FLASH stuff
*-----------------------------------------------------------------------
*/
#define CFG_NAND_LEGACY
#define CFG_NAND_BASE_LIST { CFG_NAND_BASE }
#define NAND_MAX_CHIPS 1
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define NAND_BIG_DELAY_US 25
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define SECTORSIZE 512
#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
#define ADDR_COLUMN 1
#define ADDR_PAGE 2
#define ADDR_COLUMN_PAGE 3
#define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1
#define NAND_MAX_CHIPS 1
#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
#define CFG_NAND_QUIET 1
/*-----------------------------------------------------------------------
* PCI stuff
@@ -276,11 +255,6 @@
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
#if 0 /* test-only */
#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */
#define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */
#endif
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
@@ -306,9 +280,6 @@
#define CFG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/
/* total size of a CAT24WC16 is 2048 bytes */
#define CFG_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */
#define CFG_NVRAM_SIZE 242 /* NVRAM size */
/*-----------------------------------------------------------------------
* I2C EEPROM (CAT24WC16) for environment
*/
@@ -317,7 +288,7 @@
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT24WC08 */
#if 1 /* test-only */
/* CAT24WC08/16... */
#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
/* mask of address bits that overflow into the "EEPROM chip address" */
@@ -325,15 +296,6 @@
#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
/* 16 byte page write mode using*/
/* last 4 bits of the address */
#else
/* CAT24WC32/64... */
#define CFG_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
/* mask of address bits that overflow into the "EEPROM chip address" */
#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x01
#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* The Catalyst CAT24WC32 has */
/* 32 byte page write mode using*/
/* last 5 bits of the address */
#endif
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
#define CFG_EEPROM_PAGE_WRITE_ENABLE

4
include/configs/PM854.h
View File

@@ -270,15 +270,19 @@
#define TSEC2_PHY_ADDR 1
#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
#define TSEC1_FLAGS TSEC_GIGABIT
#define TSEC2_FLAGS TSEC_GIGABIT
#define CONFIG_MPC85XX_FEC 1
#define CONFIG_MPC85XX_FEC_NAME "FEC"
#define FEC_PHY_ADDR 3
#define FEC_PHYIDX 0
#define FEC_FLAGS 0
/* Options are: TSEC[0-1] */
#define CONFIG_ETHPRIME "TSEC0"
#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1 1
#define CONFIG_HAS_ETH2 1

4
include/configs/PM856.h
View File

@@ -262,11 +262,12 @@
#define CONFIG_TSEC1_NAME "TSEC0"
#define CONFIG_TSEC2 1
#define CONFIG_TSEC2_NAME "TSEC1"
#undef CONFIG_MPC85XX_FEC
#define TSEC1_PHY_ADDR 0
#define TSEC2_PHY_ADDR 1
#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
#define TSEC1_FLAGS TSEC_GIGABIT
#define TSEC2_FLAGS TSEC_GIGABIT
#endif /* CONFIG_TSEC_ENET */
@@ -391,6 +392,7 @@
/* The mac addresses for all ethernet interface */
#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
#define CONFIG_HAS_ETH0
#define CONFIG_ETHADDR 00:40:42:01:00:00
#define CONFIG_HAS_ETH1
#define CONFIG_ETH1ADDR 00:40:42:01:00:01

2
include/configs/PPChameleonEVB.h
View File

@@ -429,6 +429,8 @@
#define CFG_ENV_ADDR_REDUND 0xFFFFA000
#define CFG_ENV_SIZE_REDUND 0x2000
#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
#endif /* ENVIRONMENT_IN_EEPROM */

1
include/configs/R360MPI.h
View File

@@ -233,6 +233,7 @@
#define CFG_ENV_OFFSET 0x40000 /* Offset of Environment */
#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment sector */
#define CFG_ENV_SIZE 0x4000 /* Used Size of Environment sector */
#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
/*-----------------------------------------------------------------------
* Cache Configuration

2
include/configs/RRvision.h
View File

@@ -235,6 +235,8 @@
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
/*-----------------------------------------------------------------------
* Cache Configuration
*/

4
include/configs/TASREG.h
View File

@@ -43,6 +43,10 @@
#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
#define CONFIG_MCFTMR
#define CONFIG_MCFUART
#define CFG_UART_PORT (0)
#define CONFIG_BAUDRATE 19200
#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }

4
include/configs/TQM5200.h
View File

@@ -701,11 +701,9 @@
* Open firmware flat tree support
*-----------------------------------------------------------------------
*/
#define CONFIG_OF_FLAT_TREE 1
#define CONFIG_OF_LIBFDT 1
#define CONFIG_OF_BOARD_SETUP 1
/* maximum size of the flat tree (8K) */
#define OF_FLAT_TREE_MAX_SIZE 8192
#define OF_CPU "PowerPC,5200@0"
#define OF_SOC "soc5200@f0000000"
#define OF_TBCLK (bd->bi_busfreq / 4)

7
include/configs/TQM823L.h
View File

@@ -70,8 +70,9 @@
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
"bootfile=/tftpboot/TQM823L/uImage\0" \
"kernel_addr=40040000\0" \
"ramdisk_addr=40100000\0" \
"fdt_addr=40040000\0" \
"kernel_addr=40060000\0" \
"ramdisk_addr=40200000\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
@@ -205,6 +206,8 @@
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
/*-----------------------------------------------------------------------
* Hardware Information Block
*/

7
include/configs/TQM823M.h
View File

@@ -70,8 +70,9 @@
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
"bootfile=/tftpboot/TQM823M/uImage\0" \
"kernel_addr=40080000\0" \
"ramdisk_addr=40180000\0" \
"fdt_addr=40080000\0" \
"kernel_addr=400A0000\0" \
"ramdisk_addr=40280000\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
@@ -202,6 +203,8 @@
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
/*-----------------------------------------------------------------------
* Hardware Information Block
*/

3
include/configs/TQM834x.h
View File

@@ -253,6 +253,8 @@ extern int tqm834x_num_flash_banks;
#define TSEC2_PHY_ADDR 1
#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
#define TSEC1_FLAGS TSEC_GIGABIT
#define TSEC2_FLAGS TSEC_GIGABIT
/* Options are: TSEC[0-1] */
#define CONFIG_ETHPRIME "TSEC0"
@@ -499,6 +501,7 @@ extern int tqm834x_num_flash_banks;
*/
#if defined(CONFIG_TSEC_ENET)
#define CONFIG_HAS_ETH0
#define CONFIG_ETHADDR D2:DA:5E:44:BC:29
#define CONFIG_HAS_ETH1
#define CONFIG_ETH1ADDR 1E:F3:40:21:92:53

7
include/configs/TQM850L.h
View File

@@ -66,8 +66,9 @@
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
"bootfile=/tftpboot/TQM850L/uImage\0" \
"kernel_addr=40040000\0" \
"ramdisk_addr=40100000\0" \
"fdt_addr=40040000\0" \
"kernel_addr=40060000\0" \
"ramdisk_addr=40200000\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
@@ -192,6 +193,8 @@
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
/*-----------------------------------------------------------------------
* Hardware Information Block
*/

7
include/configs/TQM850M.h
View File

@@ -64,8 +64,9 @@
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
"bootfile=/tftpboot/TQM850M/uImage\0" \
"kernel_addr=40080000\0" \
"ramdisk_addr=40180000\0" \
"fdt_addr=40080000\0" \
"kernel_addr=400A0000\0" \
"ramdisk_addr=40280000\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
@@ -191,6 +192,8 @@
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
/*-----------------------------------------------------------------------
* Hardware Information Block
*/

7
include/configs/TQM855L.h
View File

@@ -69,8 +69,9 @@
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
"bootfile=/tftpboot/TQM855L/uImage\0" \
"kernel_addr=40040000\0" \
"ramdisk_addr=40100000\0" \
"fdt_addr=40040000\0" \
"kernel_addr=40060000\0" \
"ramdisk_addr=40200000\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
@@ -196,6 +197,8 @@
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
/*-----------------------------------------------------------------------
* Hardware Information Block
*/

7
include/configs/TQM855M.h
View File

@@ -69,8 +69,9 @@
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
"bootfile=/tftpboot/TQM855M/uImage\0" \
"kernel_addr=40080000\0" \
"ramdisk_addr=40180000\0" \
"fdt_addr=40080000\0" \
"kernel_addr=400A0000\0" \
"ramdisk_addr=40280000\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
@@ -231,6 +232,8 @@
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
/*-----------------------------------------------------------------------
* Hardware Information Block
*/

7
include/configs/TQM85xx.h
View File

@@ -94,7 +94,6 @@
*/
#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */
#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
#define CONFIG_ADD_RAM_INFO 1 /* print additional info*/
#if defined(CONFIG_TQM8540) || defined(CONFIG_TQM8560)
/* TQM8540 & 8560 need DLL-override */
@@ -266,8 +265,12 @@
#define TSEC2_PHY_ADDR 1
#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
#define TSEC1_FLAGS TSEC_GIGABIT
#define TSEC2_FLAGS TSEC_GIGABIT
#define FEC_PHY_ADDR 3
#define FEC_PHYIDX 0
#define FEC_FLAGS 0
#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1
#define CONFIG_HAS_ETH2
@@ -446,7 +449,7 @@
#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
#define CONFIG_EXTRA_ENV_SETTINGS \
CFG_BOOTFILE \
"bootfile="CFG_BOOTFILE_PATH"\0" \
"netdev=eth0\0" \
"consdev=ttyS0\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \

7
include/configs/TQM860L.h
View File

@@ -69,8 +69,9 @@
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
"bootfile=/tftpboot/TQM860L/uImage\0" \
"kernel_addr=40040000\0" \
"ramdisk_addr=40100000\0" \
"fdt_addr=40040000\0" \
"kernel_addr=40060000\0" \
"ramdisk_addr=40200000\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
@@ -199,6 +200,8 @@
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
/*-----------------------------------------------------------------------
* Hardware Information Block
*/

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