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Merge git://www.denx.de/git/u-boot

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	CREDITS
This commit is contained in:
Nobuhiro Iwamatsu
2007-09-23 01:29:43 +09:00
parent 69df3c4da0 66dcad3a9a
commit b8685affe6
1899 changed files with 118238 additions and 140547 deletions
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1
include/74xx_7xx.h
View File

@@ -34,6 +34,7 @@
* Exception offsets (PowerPC standard)
*/
#define EXC_OFF_SYS_RESET 0x0100 /* default system reset offset */
#define _START_OFFSET EXC_OFF_SYS_RESET
/*----------------------------------------------------------------
* l2cr values

9
include/_exports.h
View File

@@ -14,8 +14,13 @@ EXPORT_FUNC(vprintf)
EXPORT_FUNC(do_reset)
EXPORT_FUNC(getenv)
EXPORT_FUNC(setenv)
#ifdef CONFIG_HAS_UID
EXPORT_FUNC(forceenv)
#endif
EXPORT_FUNC(simple_strtoul)
#if (CONFIG_COMMANDS & CFG_CMD_I2C)
EXPORT_FUNC(simple_strtol)
EXPORT_FUNC(strcmp)
#if defined(CONFIG_CMD_I2C)
EXPORT_FUNC(i2c_write)
EXPORT_FUNC(i2c_read)
#endif /* CFG_CMD_I2C */
#endif

2
include/asm-arm/arch-arm720t/hardware.h
View File

@@ -36,8 +36,6 @@
/* include armadillo specific hardware file if there was one */
#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
/* include IntegratorCP/CM720T specific hardware file if there was one */
#elif defined(CONFIG_LPC2292)
#include <asm-arm/arch-arm720t/lpc2292_registers.h>
#else
#error No hardware file defined for this configuration
#endif

139
include/asm-arm/arch-at91rm9200/AT91RM9200.h
View File

@@ -27,9 +27,9 @@
typedef volatile unsigned int AT91_REG; /* Hardware register definition */
/******************************************************************************/
/* SOFTWARE API DEFINITION FOR Timer Counter Channel Interface */
/******************************************************************************/
/*****************************************************************************/
/* SOFTWARE API DEFINITION FOR Timer Counter Channel Interface */
/*****************************************************************************/
typedef struct _AT91S_TC
{
AT91_REG TC_CCR; /* Channel Control Register */
@@ -45,24 +45,24 @@ typedef struct _AT91S_TC
AT91_REG TC_IMR; /* Interrupt Mask Register */
} AT91S_TC, *AT91PS_TC;
#define AT91C_TC_TIMER_DIV1_CLOCK ((unsigned int) 0x0 << 0) /* (TC) MCK/2 */
#define AT91C_TC_TIMER_DIV2_CLOCK ((unsigned int) 0x1 << 0) /* (TC) MCK/8 */
#define AT91C_TC_TIMER_DIV3_CLOCK ((unsigned int) 0x2 << 0) /* (TC) MCK/32 */
#define AT91C_TC_TIMER_DIV4_CLOCK ((unsigned int) 0x3 << 0) /* (TC) MCK/128 */
#define AT91C_TC_SLOW_CLOCK ((unsigned int) 0x4 << 0) /* (TC) SLOW CLK */
#define AT91C_TC_XC0_CLOCK ((unsigned int) 0x5 << 0) /* (TC) XC0 */
#define AT91C_TC_XC1_CLOCK ((unsigned int) 0x6 << 0) /* (TC) XC1 */
#define AT91C_TC_XC2_CLOCK ((unsigned int) 0x7 << 0) /* (TC) XC2 */
#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) /* (TCB) None signal connected to XC0 */
#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) /* (TCB) None signal connected to XC1 */
#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) /* (TCB) None signal connected to XC2 */
#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) /* (TC) Counter Clock Disable Command */
#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) /* (TC) Software Trigger Command */
#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) /* (TC) Counter Clock Enable Command */
#define AT91C_TC_TIMER_DIV1_CLOCK ((unsigned int) 0x0 << 0) /* (TC) MCK/2 */
#define AT91C_TC_TIMER_DIV2_CLOCK ((unsigned int) 0x1 << 0) /* (TC) MCK/8 */
#define AT91C_TC_TIMER_DIV3_CLOCK ((unsigned int) 0x2 << 0) /* (TC) MCK/32 */
#define AT91C_TC_TIMER_DIV4_CLOCK ((unsigned int) 0x3 << 0) /* (TC) MCK/128 */
#define AT91C_TC_SLOW_CLOCK ((unsigned int) 0x4 << 0) /* (TC) SLOW CLK*/
#define AT91C_TC_XC0_CLOCK ((unsigned int) 0x5 << 0) /* (TC) XC0 */
#define AT91C_TC_XC1_CLOCK ((unsigned int) 0x6 << 0) /* (TC) XC1 */
#define AT91C_TC_XC2_CLOCK ((unsigned int) 0x7 << 0) /* (TC) XC2 */
#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) /* (TCB) None signal connected to XC0 */
#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) /* (TCB) None signal connected to XC1 */
#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) /* (TCB) None signal connected to XC2 */
#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) /* (TC) Counter Clock Disable Command */
#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) /* (TC) Software Trigger Command */
#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) /* (TC) Counter Clock Enable Command */
/******************************************************************************/
/* SOFTWARE API DEFINITION FOR Usart */
/******************************************************************************/
/*****************************************************************************/
/* SOFTWARE API DEFINITION FOR Usart */
/*****************************************************************************/
typedef struct _AT91S_USART
{
AT91_REG US_CR; /* Control Register */
@@ -94,9 +94,9 @@ typedef struct _AT91S_USART
AT91_REG US_PTSR; /* PDC Transfer Status Register */
} AT91S_USART, *AT91PS_USART;
/******************************************************************************/
/* SOFTWARE API DEFINITION FOR Clock Generator Controler */
/******************************************************************************/
/*****************************************************************************/
/* SOFTWARE API DEFINITION FOR Clock Generator Controler */
/*****************************************************************************/
typedef struct _AT91S_CKGR
{
AT91_REG CKGR_MOR; /* Main Oscillator Register */
@@ -141,9 +141,9 @@ typedef struct _AT91S_CKGR
#define AT91C_CKGR_USB_96M ((unsigned int) 0x1 << 28) /* (CKGR) Divider for USB Ports */
#define AT91C_CKGR_USB_PLL ((unsigned int) 0x1 << 29) /* (CKGR) PLL Use */
/******************************************************************************/
/* SOFTWARE API DEFINITION FOR Parallel Input Output Controler */
/******************************************************************************/
/*****************************************************************************/
/* SOFTWARE API DEFINITION FOR Parallel Input Output Controler */
/*****************************************************************************/
typedef struct _AT91S_PIO
{
AT91_REG PIO_PER; /* PIO Enable Register */
@@ -184,9 +184,9 @@ typedef struct _AT91S_PIO
} AT91S_PIO, *AT91PS_PIO;
/******************************************************************************/
/* SOFTWARE API DEFINITION FOR Debug Unit */
/******************************************************************************/
/*****************************************************************************/
/* SOFTWARE API DEFINITION FOR Debug Unit */
/*****************************************************************************/
typedef struct _AT91S_DBGU
{
AT91_REG DBGU_CR; /* Control Register */
@@ -242,9 +242,9 @@ typedef struct _AT91S_DBGU
#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) /* (DBGU) No Parity */
#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) /* (USART) 1 stop bit */
/******************************************************************************/
/* SOFTWARE API DEFINITION FOR Static Memory Controller 2 Interface */
/******************************************************************************/
/*****************************************************************************/
/* SOFTWARE API DEFINITION FOR Static Memory Controller 2 Interface */
/*****************************************************************************/
typedef struct _AT91S_SMC2
{
AT91_REG SMC2_CSR[8]; /* SMC2 Chip Select Register */
@@ -267,9 +267,9 @@ typedef struct _AT91S_SMC2
#define AT91C_SMC2_RWSETUP ((unsigned int) 0x7 << 24) /* (SMC2) Read and Write Signal Setup Time */
#define AT91C_SMC2_RWHOLD ((unsigned int) 0x7 << 29) /* (SMC2) Read and Write Signal Hold Time */
/******************************************************************************/
/* SOFTWARE API DEFINITION FOR Power Management Controler */
/******************************************************************************/
/*****************************************************************************/
/* SOFTWARE API DEFINITION FOR Power Management Controler */
/*****************************************************************************/
typedef struct _AT91S_PMC
{
AT91_REG PMC_SCER; /* System Clock Enable Register */
@@ -341,9 +341,9 @@ typedef struct _AT91S_PMC
/*-------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------*/
/*-------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------*/
/******************************************************************************/
/* SOFTWARE API DEFINITION FOR Ethernet MAC */
/******************************************************************************/
/*****************************************************************************/
/* SOFTWARE API DEFINITION FOR Ethernet MAC */
/*****************************************************************************/
typedef struct _AT91S_EMAC
{
AT91_REG EMAC_CTL; /* Network Control Register */
@@ -424,11 +424,11 @@ typedef struct _AT91S_EMAC
#define AT91C_EMAC_MDIO ((unsigned int) 0x1 << 1) /* (EMAC) */
#define AT91C_EMAC_IDLE ((unsigned int) 0x1 << 2) /* (EMAC) */
/* -------- EMAC_TCR : (EMAC Offset: 0x10) Transmit Control Register -------- */
/* -------- EMAC_TCR : (EMAC Offset: 0x10) Transmit Control Register ------- */
#define AT91C_EMAC_LEN ((unsigned int) 0x7FF << 0) /* (EMAC) */
#define AT91C_EMAC_NCRC ((unsigned int) 0x1 << 15) /* (EMAC) */
/* -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Control Register -------- */
/* -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Control Register ------- */
#define AT91C_EMAC_OVR ((unsigned int) 0x1 << 0) /* (EMAC) */
#define AT91C_EMAC_COL ((unsigned int) 0x1 << 1) /* (EMAC) */
#define AT91C_EMAC_RLE ((unsigned int) 0x1 << 2) /* (EMAC) */
@@ -442,7 +442,7 @@ typedef struct _AT91S_EMAC
#define AT91C_EMAC_REC ((unsigned int) 0x1 << 1) /* (EMAC) */
#define AT91C_EMAC_RSR_OVR ((unsigned int) 0x1 << 2) /* (EMAC) */
/* -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- */
/* -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register ------- */
#define AT91C_EMAC_DONE ((unsigned int) 0x1 << 0) /* (EMAC) */
#define AT91C_EMAC_RCOM ((unsigned int) 0x1 << 1) /* (EMAC) */
#define AT91C_EMAC_RBNA ((unsigned int) 0x1 << 2) /* (EMAC) */
@@ -456,8 +456,8 @@ typedef struct _AT91S_EMAC
#define AT91C_EMAC_ROVR ((unsigned int) 0x1 << 10) /* (EMAC) */
#define AT91C_EMAC_HRESP ((unsigned int) 0x1 << 11) /* (EMAC) */
/* -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- */
/* -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- */
/* -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register ------- */
/* -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register ------ */
/* -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- */
/* -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- */
#define AT91C_EMAC_DATA ((unsigned int) 0xFFFF << 0) /* (EMAC) */
@@ -471,9 +471,9 @@ typedef struct _AT91S_EMAC
#define AT91C_EMAC_HIGH ((unsigned int) 0x1 << 30) /* (EMAC) */
#define AT91C_EMAC_LOW ((unsigned int) 0x1 << 31) /* (EMAC) */
/******************************************************************************/
/* SOFTWARE API DEFINITION FOR Serial Parallel Interface */
/******************************************************************************/
/*****************************************************************************/
/* SOFTWARE API DEFINITION FOR Serial Parallel Interface */
/*****************************************************************************/
typedef struct _AT91S_SPI
{
AT91_REG SPI_CR; /* Control Register */
@@ -536,7 +536,7 @@ typedef struct _AT91S_SPI
#define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) /* (SPI) Enable Status */
/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */
/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */
/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register ------- */
/* -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- */
/* -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- */
#define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) /* (SPI) Clock Polarity */
@@ -555,9 +555,9 @@ typedef struct _AT91S_SPI
#define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) /* (SPI) Serial Clock Baud Rate */
#define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) /* (SPI) Delay Between Consecutive Transfers */
/******************************************************************************/
/* SOFTWARE API DEFINITION FOR Peripheral Data Controller */
/******************************************************************************/
/*****************************************************************************/
/* SOFTWARE API DEFINITION FOR Peripheral Data Controller */
/*****************************************************************************/
typedef struct _AT91S_PDC
{
AT91_REG PDC_RPR; /* Receive Pointer Register */
@@ -692,11 +692,15 @@ typedef struct _AT91S_PDC
#define AT91C_PIO_PA7 ((unsigned int) 1 << 7) /* Pin Controlled by PA7 */
#define AT91C_PA7_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PA7) /* Ethernet MAC Transmit Clock/Reference Clock */
#define AT91C_PIO_PB0 ((unsigned int) 1 << 0) /* Pin Controlled by PB3 */
#define AT91C_PIO_PB1 ((unsigned int) 1 << 1) /* Pin Controlled by PB3 */
#define AT91C_PIO_PB2 ((unsigned int) 1 << 2) /* Pin Controlled by PB3 */
#define AT91C_PIO_PB3 ((unsigned int) 1 << 3) /* Pin Controlled by PB3 */
#define AT91C_PIO_PB4 ((unsigned int) 1 << 4) /* Pin Controlled by PB4 */
#define AT91C_PIO_PB5 ((unsigned int) 1 << 5) /* Pin Controlled by PB5 */
#define AT91C_PIO_PB6 ((unsigned int) 1 << 6) /* Pin Controlled by PB6 */
#define AT91C_PIO_PB7 ((unsigned int) 1 << 7) /* Pin Controlled by PB7 */
#define AT91C_PIO_PB22 ((unsigned int) 1 << 22) /* Pin Controlled by PB22 */
#define AT91C_PIO_PB25 ((unsigned int) 1 << 25) /* Pin Controlled by PB25 */
#define AT91C_PB25_DSR1 ((unsigned int) AT91C_PIO_PB25) /* USART 1 Data Set ready */
#define AT91C_PB25_EF100 ((unsigned int) AT91C_PIO_PB25) /* Ethernet MAC Force 100 Mbits */
@@ -737,19 +741,36 @@ typedef struct _AT91S_PDC
#define AT91C_PIOC_CODR ((AT91_REG *) 0xFFFFF834) /* (PIOC) Clear Output Data Register */
#define AT91C_PIOC_PDSR ((AT91_REG *) 0xFFFFF83C) /* (PIOC) Pin Data Status Register */
#define AT91C_BASE_SPI ((AT91PS_SPI) 0xFFFE0000) /* (SPI) Base Address */
#define AT91C_BASE_EMAC ((AT91PS_EMAC) 0xFFFBC000) /* (EMAC) Base Address */
#define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) /* (PMC) Base Address */
#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) /* (TC0) Base Address */
#define AT91C_BASE_AIC ((AT91PS_AIC) 0xFFFFF000) /* (AIC) Base Address */
#define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) /* (DBGU) Base Address */
#define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) /* (CKGR) Base Address */
#define AT91C_BASE_PIOC ((AT91PS_PIO) 0xFFFFF800) /* (PIOC) Base Address */
#define AT91C_BASE_PIOB ((AT91PS_PIO) 0xFFFFF600) /* (PIOB) Base Address */
#define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) /* (PIOA) Base Address */
#define AT91C_EBI_CSA ((AT91_REG *) 0xFFFFFF60) /* (EBI) Chip Select Assignment Register */
#define AT91C_BASE_SMC2 ((AT91PS_SMC2) 0xFFFFFF70) /* (SMC2) Base Address */
#define AT91C_BASE_PIOB ((AT91PS_PIO) 0xFFFFF600) /* (PIOB) Base Address */
#define AT91C_BASE_PIOC ((AT91PS_PIO) 0xFFFFF800) /* (PIOC) Base Address */
#define AT91C_BASE_PIOD ((AT91PS_PIO) 0xFFFFFA00) /* (PIOC) Base Address */
#define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) /* (PMC) Base Address */
#if 0
#define AT91C_BASE_ST ((AT91PS_ST) 0xFFFFFD00) /* (PMC) Base Address */
#define AT91C_BASE_RTC ((AT91PS_RTC) 0xFFFFFE00) /* (PMC) Base Address */
#define AT91C_BASE_MC ((AT91PS_MC) 0xFFFFFF00) /* (PMC) Base Address */
#endif
#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) /* (TC0) Base Address */
#define AT91C_BASE_TC1 ((AT91PS_TC) 0xFFFA4000) /* (TC0) Base Address */
#if 0
#define AT91C_BASE_UDP ((AT91PS_UDP) 0xFFFB0000) /* (TC0) Base Address */
#define AT91C_BASE_MCI ((AT91PS_MCI) 0xFFFB4000) /* (TC0) Base Address */
#define AT91C_BASE_TWI ((AT91PS_TWI) 0xFFFB8000) /* (TC0) Base Address */
#endif
#define AT91C_BASE_EMAC ((AT91PS_EMAC) 0xFFFBC000) /* (EMAC) Base Address */
#define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) /* (US0) Base Address */
#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) /* (US1) Base Address */
#define AT91C_BASE_US2 ((AT91PS_USART) 0xFFFC8000) /* (US1) Base Address */
#define AT91C_BASE_US3 ((AT91PS_USART) 0xFFFCC000) /* (US1) Base Address */
#define AT91C_BASE_SPI ((AT91PS_SPI) 0xFFFE0000) /* (SPI) Base Address */
#define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) /* (CKGR) Base Address */
#define AT91C_EBI_CSA ((AT91_REG *) 0xFFFFFF60) /* (EBI) Chip Select Assignment Register */
#define AT91C_BASE_SMC2 ((AT91PS_SMC2) 0xFFFFFF70) /* (SMC2) Base Address */
#define AT91C_TCB0_BMR ((AT91_REG *) 0xFFFA00C4) /* (TCB0) TC Block Mode Register */
#define AT91C_TCB0_BCR ((AT91_REG *) 0xFFFA00C0) /* (TCB0) TC Block Control Register */
#define AT91C_PIOC_PDR ((AT91_REG *) 0xFFFFF804) /* (PIOC) PIO Disable Register */

311
include/asm-arm/arch-davinci/emac_defs.h Normal file
View File

@@ -0,0 +1,311 @@
/*
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
*
* Based on:
*
* ----------------------------------------------------------------------------
*
* dm644x_emac.h
*
* TI DaVinci (DM644X) EMAC peripheral driver header for DV-EVM
*
* Copyright (C) 2005 Texas Instruments.
*
* ----------------------------------------------------------------------------
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
* ----------------------------------------------------------------------------
* Modifications:
* ver. 1.0: Sep 2005, TI PSP Team - Created EMAC version for uBoot.
*
*/
#ifndef _DM644X_EMAC_H_
#define _DM644X_EMAC_H_
#include <asm/arch/hardware.h>
#define EMAC_BASE_ADDR (0x01c80000)
#define EMAC_WRAPPER_BASE_ADDR (0x01c81000)
#define EMAC_WRAPPER_RAM_ADDR (0x01c82000)
#define EMAC_MDIO_BASE_ADDR (0x01c84000)
/* MDIO module input frequency */
#define EMAC_MDIO_BUS_FREQ 99000000 /* PLL/6 - 99 MHz */
/* MDIO clock output frequency */
#define EMAC_MDIO_CLOCK_FREQ 2000000 /* 2.0 MHz */
/* Ethernet Min/Max packet size */
#define EMAC_MIN_ETHERNET_PKT_SIZE 60
#define EMAC_MAX_ETHERNET_PKT_SIZE 1518
#define EMAC_PKT_ALIGN 18 /* 1518 + 18 = 1536 (packet aligned on 32 byte boundry) */
/* Number of RX packet buffers
* NOTE: Only 1 buffer supported as of now
*/
#define EMAC_MAX_RX_BUFFERS 10
/***********************************************
******** Internally used macros ***************
***********************************************/
#define EMAC_CH_TX 1
#define EMAC_CH_RX 0
/* Each descriptor occupies 4 words, lets start RX desc's at 0 and
* reserve space for 64 descriptors max
*/
#define EMAC_RX_DESC_BASE 0x0
#define EMAC_TX_DESC_BASE 0x1000
/* EMAC Teardown value */
#define EMAC_TEARDOWN_VALUE 0xfffffffc
/* MII Status Register */
#define MII_STATUS_REG 1
/* Number of statistics registers */
#define EMAC_NUM_STATS 36
/* EMAC Descriptor */
typedef volatile struct _emac_desc
{
u_int32_t next; /* Pointer to next descriptor in chain */
u_int8_t *buffer; /* Pointer to data buffer */
u_int32_t buff_off_len; /* Buffer Offset(MSW) and Length(LSW) */
u_int32_t pkt_flag_len; /* Packet Flags(MSW) and Length(LSW) */
} emac_desc;
/* CPPI bit positions */
#define EMAC_CPPI_SOP_BIT (0x80000000)
#define EMAC_CPPI_EOP_BIT (0x40000000)
#define EMAC_CPPI_OWNERSHIP_BIT (0x20000000)
#define EMAC_CPPI_EOQ_BIT (0x10000000)
#define EMAC_CPPI_TEARDOWN_COMPLETE_BIT (0x08000000)
#define EMAC_CPPI_PASS_CRC_BIT (0x04000000)
#define EMAC_CPPI_RX_ERROR_FRAME (0x03fc0000)
#define EMAC_MACCONTROL_MIIEN_ENABLE (0x20)
#define EMAC_MACCONTROL_FULLDUPLEX_ENABLE (0x1)
#define EMAC_RXMBPENABLE_RXCAFEN_ENABLE (0x200000)
#define EMAC_RXMBPENABLE_RXBROADEN (0x2000)
#define MDIO_CONTROL_IDLE (0x80000000)
#define MDIO_CONTROL_ENABLE (0x40000000)
#define MDIO_CONTROL_FAULT_ENABLE (0x40000)
#define MDIO_CONTROL_FAULT (0x80000)
#define MDIO_USERACCESS0_GO (0x80000000)
#define MDIO_USERACCESS0_WRITE_READ (0x0)
#define MDIO_USERACCESS0_WRITE_WRITE (0x40000000)
#define MDIO_USERACCESS0_ACK (0x20000000)
/* Ethernet MAC Registers Structure */
typedef struct {
dv_reg TXIDVER;
dv_reg TXCONTROL;
dv_reg TXTEARDOWN;
u_int8_t RSVD0[4];
dv_reg RXIDVER;
dv_reg RXCONTROL;
dv_reg RXTEARDOWN;
u_int8_t RSVD1[100];
dv_reg TXINTSTATRAW;
dv_reg TXINTSTATMASKED;
dv_reg TXINTMASKSET;
dv_reg TXINTMASKCLEAR;
dv_reg MACINVECTOR;
u_int8_t RSVD2[12];
dv_reg RXINTSTATRAW;
dv_reg RXINTSTATMASKED;
dv_reg RXINTMASKSET;
dv_reg RXINTMASKCLEAR;
dv_reg MACINTSTATRAW;
dv_reg MACINTSTATMASKED;
dv_reg MACINTMASKSET;
dv_reg MACINTMASKCLEAR;
u_int8_t RSVD3[64];
dv_reg RXMBPENABLE;
dv_reg RXUNICASTSET;
dv_reg RXUNICASTCLEAR;
dv_reg RXMAXLEN;
dv_reg RXBUFFEROFFSET;
dv_reg RXFILTERLOWTHRESH;
u_int8_t RSVD4[8];
dv_reg RX0FLOWTHRESH;
dv_reg RX1FLOWTHRESH;
dv_reg RX2FLOWTHRESH;
dv_reg RX3FLOWTHRESH;
dv_reg RX4FLOWTHRESH;
dv_reg RX5FLOWTHRESH;
dv_reg RX6FLOWTHRESH;
dv_reg RX7FLOWTHRESH;
dv_reg RX0FREEBUFFER;
dv_reg RX1FREEBUFFER;
dv_reg RX2FREEBUFFER;
dv_reg RX3FREEBUFFER;
dv_reg RX4FREEBUFFER;
dv_reg RX5FREEBUFFER;
dv_reg RX6FREEBUFFER;
dv_reg RX7FREEBUFFER;
dv_reg MACCONTROL;
dv_reg MACSTATUS;
dv_reg EMCONTROL;
dv_reg FIFOCONTROL;
dv_reg MACCONFIG;
dv_reg SOFTRESET;
u_int8_t RSVD5[88];
dv_reg MACSRCADDRLO;
dv_reg MACSRCADDRHI;
dv_reg MACHASH1;
dv_reg MACHASH2;
dv_reg BOFFTEST;
dv_reg TPACETEST;
dv_reg RXPAUSE;
dv_reg TXPAUSE;
u_int8_t RSVD6[16];
dv_reg RXGOODFRAMES;
dv_reg RXBCASTFRAMES;
dv_reg RXMCASTFRAMES;
dv_reg RXPAUSEFRAMES;
dv_reg RXCRCERRORS;
dv_reg RXALIGNCODEERRORS;
dv_reg RXOVERSIZED;
dv_reg RXJABBER;
dv_reg RXUNDERSIZED;
dv_reg RXFRAGMENTS;
dv_reg RXFILTERED;
dv_reg RXQOSFILTERED;
dv_reg RXOCTETS;
dv_reg TXGOODFRAMES;
dv_reg TXBCASTFRAMES;
dv_reg TXMCASTFRAMES;
dv_reg TXPAUSEFRAMES;
dv_reg TXDEFERRED;
dv_reg TXCOLLISION;
dv_reg TXSINGLECOLL;
dv_reg TXMULTICOLL;
dv_reg TXEXCESSIVECOLL;
dv_reg TXLATECOLL;
dv_reg TXUNDERRUN;
dv_reg TXCARRIERSENSE;
dv_reg TXOCTETS;
dv_reg FRAME64;
dv_reg FRAME65T127;
dv_reg FRAME128T255;
dv_reg FRAME256T511;
dv_reg FRAME512T1023;
dv_reg FRAME1024TUP;
dv_reg NETOCTETS;
dv_reg RXSOFOVERRUNS;
dv_reg RXMOFOVERRUNS;
dv_reg RXDMAOVERRUNS;
u_int8_t RSVD7[624];
dv_reg MACADDRLO;
dv_reg MACADDRHI;
dv_reg MACINDEX;
u_int8_t RSVD8[244];
dv_reg TX0HDP;
dv_reg TX1HDP;
dv_reg TX2HDP;
dv_reg TX3HDP;
dv_reg TX4HDP;
dv_reg TX5HDP;
dv_reg TX6HDP;
dv_reg TX7HDP;
dv_reg RX0HDP;
dv_reg RX1HDP;
dv_reg RX2HDP;
dv_reg RX3HDP;
dv_reg RX4HDP;
dv_reg RX5HDP;
dv_reg RX6HDP;
dv_reg RX7HDP;
dv_reg TX0CP;
dv_reg TX1CP;
dv_reg TX2CP;
dv_reg TX3CP;
dv_reg TX4CP;
dv_reg TX5CP;
dv_reg TX6CP;
dv_reg TX7CP;
dv_reg RX0CP;
dv_reg RX1CP;
dv_reg RX2CP;
dv_reg RX3CP;
dv_reg RX4CP;
dv_reg RX5CP;
dv_reg RX6CP;
dv_reg RX7CP;
} emac_regs;
/* EMAC Wrapper Registers Structure */
typedef struct {
u_int8_t RSVD0[4100];
dv_reg EWCTL;
dv_reg EWINTTCNT;
} ewrap_regs;
/* EMAC MDIO Registers Structure */
typedef struct {
dv_reg VERSION;
dv_reg CONTROL;
dv_reg ALIVE;
dv_reg LINK;
dv_reg LINKINTRAW;
dv_reg LINKINTMASKED;
u_int8_t RSVD0[8];
dv_reg USERINTRAW;
dv_reg USERINTMASKED;
dv_reg USERINTMASKSET;
dv_reg USERINTMASKCLEAR;
u_int8_t RSVD1[80];
dv_reg USERACCESS0;
dv_reg USERPHYSEL0;
dv_reg USERACCESS1;
dv_reg USERPHYSEL1;
} mdio_regs;
int dm644x_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data);
int dm644x_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data);
typedef struct
{
char name[64];
int (*init)(int phy_addr);
int (*is_phy_connected)(int phy_addr);
int (*get_link_speed)(int phy_addr);
int (*auto_negotiate)(int phy_addr);
} phy_t;
#define PHY_LXT972 (0x001378e2)
int lxt972_is_phy_connected(int phy_addr);
int lxt972_get_link_speed(int phy_addr);
int lxt972_init_phy(int phy_addr);
int lxt972_auto_negotiate(int phy_addr);
#define PHY_DP83848 (0x20005c90)
int dp83848_is_phy_connected(int phy_addr);
int dp83848_get_link_speed(int phy_addr);
int dp83848_init_phy(int phy_addr);
int dp83848_auto_negotiate(int phy_addr);
#endif /* _DM644X_EMAC_H_ */

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/*
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _EMIF_DEFS_H_
#define _EMIF_DEFS_H_
#include <asm/arch/hardware.h>
typedef struct {
dv_reg ERCSR;
dv_reg AWCCR;
dv_reg SDBCR;
dv_reg SDRCR;
dv_reg AB1CR;
dv_reg AB2CR;
dv_reg AB3CR;
dv_reg AB4CR;
dv_reg SDTIMR;
dv_reg DDRSR;
dv_reg DDRPHYCR;
dv_reg DDRPHYSR;
dv_reg TOTAR;
dv_reg TOTACTR;
dv_reg DDRPHYID_REV;
dv_reg SDSRETR;
dv_reg EIRR;
dv_reg EIMR;
dv_reg EIMSR;
dv_reg EIMCR;
dv_reg IOCTRLR;
dv_reg IOSTATR;
u_int8_t RSVD0[8];
dv_reg NANDFCR;
dv_reg NANDFSR;
u_int8_t RSVD1[8];
dv_reg NANDF1ECC;
dv_reg NANDF2ECC;
dv_reg NANDF3ECC;
dv_reg NANDF4ECC;
} emif_registers;
typedef emif_registers *emifregs;
#endif

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/*
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
*
* Based on:
*
* -------------------------------------------------------------------------
*
* linux/include/asm-arm/arch-davinci/hardware.h
*
* Copyright (C) 2006 Texas Instruments.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*
*/
#ifndef __ASM_ARCH_HARDWARE_H
#define __ASM_ARCH_HARDWARE_H
#include <config.h>
#include <asm/sizes.h>
#define REG(addr) (*(volatile unsigned int *)(addr))
#define REG_P(addr) ((volatile unsigned int *)(addr))
typedef volatile unsigned int dv_reg;
typedef volatile unsigned int * dv_reg_p;
/*
* Base register addresses
*/
#define DAVINCI_DMA_3PCC_BASE (0x01c00000)
#define DAVINCI_DMA_3PTC0_BASE (0x01c10000)
#define DAVINCI_DMA_3PTC1_BASE (0x01c10400)
#define DAVINCI_UART0_BASE (0x01c20000)
#define DAVINCI_UART1_BASE (0x01c20400)
#define DAVINCI_UART2_BASE (0x01c20800)
#define DAVINCI_I2C_BASE (0x01c21000)
#define DAVINCI_TIMER0_BASE (0x01c21400)
#define DAVINCI_TIMER1_BASE (0x01c21800)
#define DAVINCI_WDOG_BASE (0x01c21c00)
#define DAVINCI_PWM0_BASE (0x01c22000)
#define DAVINCI_PWM1_BASE (0x01c22400)
#define DAVINCI_PWM2_BASE (0x01c22800)
#define DAVINCI_SYSTEM_MODULE_BASE (0x01c40000)
#define DAVINCI_PLL_CNTRL0_BASE (0x01c40800)
#define DAVINCI_PLL_CNTRL1_BASE (0x01c40c00)
#define DAVINCI_PWR_SLEEP_CNTRL_BASE (0x01c41000)
#define DAVINCI_SYSTEM_DFT_BASE (0x01c42000)
#define DAVINCI_ARM_INTC_BASE (0x01c48000)
#define DAVINCI_IEEE1394_BASE (0x01c60000)
#define DAVINCI_USB_OTG_BASE (0x01c64000)
#define DAVINCI_CFC_ATA_BASE (0x01c66000)
#define DAVINCI_SPI_BASE (0x01c66800)
#define DAVINCI_GPIO_BASE (0x01c67000)
#define DAVINCI_UHPI_BASE (0x01c67800)
#define DAVINCI_VPSS_REGS_BASE (0x01c70000)
#define DAVINCI_EMAC_CNTRL_REGS_BASE (0x01c80000)
#define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE (0x01c81000)
#define DAVINCI_EMAC_WRAPPER_RAM_BASE (0x01c82000)
#define DAVINCI_MDIO_CNTRL_REGS_BASE (0x01c84000)
#define DAVINCI_IMCOP_BASE (0x01cc0000)
#define DAVINCI_ASYNC_EMIF_CNTRL_BASE (0x01e00000)
#define DAVINCI_VLYNQ_BASE (0x01e01000)
#define DAVINCI_MCBSP_BASE (0x01e02000)
#define DAVINCI_MMC_SD_BASE (0x01e10000)
#define DAVINCI_MS_BASE (0x01e20000)
#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE (0x02000000)
#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE (0x04000000)
#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE (0x06000000)
#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE (0x08000000)
#define DAVINCI_VLYNQ_REMOTE_BASE (0x0c000000)
/* Power and Sleep Controller (PSC) Domains */
#define DAVINCI_GPSC_ARMDOMAIN 0
#define DAVINCI_GPSC_DSPDOMAIN 1
#define DAVINCI_LPSC_VPSSMSTR 0
#define DAVINCI_LPSC_VPSSSLV 1
#define DAVINCI_LPSC_TPCC 2
#define DAVINCI_LPSC_TPTC0 3
#define DAVINCI_LPSC_TPTC1 4
#define DAVINCI_LPSC_EMAC 5
#define DAVINCI_LPSC_EMAC_WRAPPER 6
#define DAVINCI_LPSC_MDIO 7
#define DAVINCI_LPSC_IEEE1394 8
#define DAVINCI_LPSC_USB 9
#define DAVINCI_LPSC_ATA 10
#define DAVINCI_LPSC_VLYNQ 11
#define DAVINCI_LPSC_UHPI 12
#define DAVINCI_LPSC_DDR_EMIF 13
#define DAVINCI_LPSC_AEMIF 14
#define DAVINCI_LPSC_MMC_SD 15
#define DAVINCI_LPSC_MEMSTICK 16
#define DAVINCI_LPSC_McBSP 17
#define DAVINCI_LPSC_I2C 18
#define DAVINCI_LPSC_UART0 19
#define DAVINCI_LPSC_UART1 20
#define DAVINCI_LPSC_UART2 21
#define DAVINCI_LPSC_SPI 22
#define DAVINCI_LPSC_PWM0 23
#define DAVINCI_LPSC_PWM1 24
#define DAVINCI_LPSC_PWM2 25
#define DAVINCI_LPSC_GPIO 26
#define DAVINCI_LPSC_TIMER0 27
#define DAVINCI_LPSC_TIMER1 28
#define DAVINCI_LPSC_TIMER2 29
#define DAVINCI_LPSC_SYSTEM_SUBSYS 30
#define DAVINCI_LPSC_ARM 31
#define DAVINCI_LPSC_SCR2 32
#define DAVINCI_LPSC_SCR3 33
#define DAVINCI_LPSC_SCR4 34
#define DAVINCI_LPSC_CROSSBAR 35
#define DAVINCI_LPSC_CFG27 36
#define DAVINCI_LPSC_CFG3 37
#define DAVINCI_LPSC_CFG5 38
#define DAVINCI_LPSC_GEM 39
#define DAVINCI_LPSC_IMCOP 40
/* Some PSC defines */
#define PSC_CHP_SHRTSW (0x01c40038)
#define PSC_GBLCTL (0x01c41010)
#define PSC_EPCPR (0x01c41070)
#define PSC_EPCCR (0x01c41078)
#define PSC_PTCMD (0x01c41120)
#define PSC_PTSTAT (0x01c41128)
#define PSC_PDSTAT (0x01c41200)
#define PSC_PDSTAT1 (0x01c41204)
#define PSC_PDCTL (0x01c41300)
#define PSC_PDCTL1 (0x01c41304)
#define PSC_MDCTL_BASE (0x01c41a00)
#define PSC_MDSTAT_BASE (0x01c41800)
#define VDD3P3V_PWDN (0x01c40048)
#define UART0_PWREMU_MGMT (0x01c20030)
#define PSC_SILVER_BULLET (0x01c41a20)
/* Some PLL defines */
#define PLL1_PLLM (0x01c40910)
#define PLL2_PLLM (0x01c40d10)
#define PLL2_DIV2 (0x01c40d1c)
/* Miscellania... */
#define VBPR (0x20000020)
#define PINMUX0 (0x01c40000)
#define PINMUX1 (0x01c40004)
#endif /* __ASM_ARCH_HARDWARE_H */

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/*
* (C) Copyright 2004
* Texas Instruments, <www.ti.com>
*
* Some changes copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _DAVINCI_I2C_H_
#define _DAVINCI_I2C_H_
#define I2C_WRITE 0
#define I2C_READ 1
#define I2C_BASE 0x01c21000
#define I2C_OA (I2C_BASE + 0x00)
#define I2C_IE (I2C_BASE + 0x04)
#define I2C_STAT (I2C_BASE + 0x08)
#define I2C_SCLL (I2C_BASE + 0x0c)
#define I2C_SCLH (I2C_BASE + 0x10)
#define I2C_CNT (I2C_BASE + 0x14)
#define I2C_DRR (I2C_BASE + 0x18)
#define I2C_SA (I2C_BASE + 0x1c)
#define I2C_DXR (I2C_BASE + 0x20)
#define I2C_CON (I2C_BASE + 0x24)
#define I2C_IV (I2C_BASE + 0x28)
#define I2C_PSC (I2C_BASE + 0x30)
/* I2C masks */
/* I2C Interrupt Enable Register (I2C_IE): */
#define I2C_IE_SCD_IE (1 << 5) /* Stop condition detect interrupt enable */
#define I2C_IE_XRDY_IE (1 << 4) /* Transmit data ready interrupt enable */
#define I2C_IE_RRDY_IE (1 << 3) /* Receive data ready interrupt enable */
#define I2C_IE_ARDY_IE (1 << 2) /* Register access ready interrupt enable */
#define I2C_IE_NACK_IE (1 << 1) /* No acknowledgment interrupt enable */
#define I2C_IE_AL_IE (1 << 0) /* Arbitration lost interrupt enable */
/* I2C Status Register (I2C_STAT): */
#define I2C_STAT_BB (1 << 12) /* Bus busy */
#define I2C_STAT_ROVR (1 << 11) /* Receive overrun */
#define I2C_STAT_XUDF (1 << 10) /* Transmit underflow */
#define I2C_STAT_AAS (1 << 9) /* Address as slave */
#define I2C_STAT_SCD (1 << 5) /* Stop condition detect */
#define I2C_STAT_XRDY (1 << 4) /* Transmit data ready */
#define I2C_STAT_RRDY (1 << 3) /* Receive data ready */
#define I2C_STAT_ARDY (1 << 2) /* Register access ready */
#define I2C_STAT_NACK (1 << 1) /* No acknowledgment interrupt enable */
#define I2C_STAT_AL (1 << 0) /* Arbitration lost interrupt enable */
/* I2C Interrupt Code Register (I2C_INTCODE): */
#define I2C_INTCODE_MASK 7
#define I2C_INTCODE_NONE 0
#define I2C_INTCODE_AL 1 /* Arbitration lost */
#define I2C_INTCODE_NAK 2 /* No acknowledgement/general call */
#define I2C_INTCODE_ARDY 3 /* Register access ready */
#define I2C_INTCODE_RRDY 4 /* Rcv data ready */
#define I2C_INTCODE_XRDY 5 /* Xmit data ready */
#define I2C_INTCODE_SCD 6 /* Stop condition detect */
/* I2C Configuration Register (I2C_CON): */
#define I2C_CON_EN (1 << 5) /* I2C module enable */
#define I2C_CON_STB (1 << 4) /* Start byte mode (master mode only) */
#define I2C_CON_MST (1 << 10) /* Master/slave mode */
#define I2C_CON_TRX (1 << 9) /* Transmitter/receiver mode (master mode only) */
#define I2C_CON_XA (1 << 8) /* Expand address */
#define I2C_CON_STP (1 << 11) /* Stop condition (master mode only) */
#define I2C_CON_STT (1 << 13) /* Start condition (master mode only) */
#define I2C_TIMEOUT 0xffff0000 /* Timeout mask for poll_i2c_irq() */
#endif

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/*
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
*
* Parts shamelesly stolen from Linux Kernel source tree.
*
* ------------------------------------------------------------
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _NAND_DEFS_H_
#define _NAND_DEFS_H_
#include <asm/arch/hardware.h>
#define MASK_CLE 0x10
#define MASK_ALE 0x0a
#define NAND_CE0CLE ((volatile u_int8_t *)(CFG_NAND_BASE + 0x10))
#define NAND_CE0ALE ((volatile u_int8_t *)(CFG_NAND_BASE + 0x0a))
#define NAND_CE0DATA ((volatile u_int8_t *)CFG_NAND_BASE)
typedef struct {
u_int32_t NRCSR;
u_int32_t AWCCR;
u_int8_t RSVD0[8];
u_int32_t AB1CR;
u_int32_t AB2CR;
u_int32_t AB3CR;
u_int32_t AB4CR;
u_int8_t RSVD1[32];
u_int32_t NIRR;
u_int32_t NIMR;
u_int32_t NIMSR;
u_int32_t NIMCR;
u_int8_t RSVD2[16];
u_int32_t NANDFCR;
u_int32_t NANDFSR;
u_int8_t RSVD3[8];
u_int32_t NANDF1ECC;
u_int32_t NANDF2ECC;
u_int32_t NANDF3ECC;
u_int32_t NANDF4ECC;
u_int8_t RSVD4[4];
u_int32_t IODFTECR;
u_int32_t IODFTGCR;
u_int8_t RSVD5[4];
u_int32_t IODFTMRLR;
u_int32_t IODFTMRMR;
u_int32_t IODFTMRMSBR;
u_int8_t RSVD6[20];
u_int32_t MODRNR;
u_int8_t RSVD7[76];
u_int32_t CE0DATA;
u_int32_t CE0ALE;
u_int32_t CE0CLE;
u_int8_t RSVD8[4];
u_int32_t CE1DATA;
u_int32_t CE1ALE;
u_int32_t CE1CLE;
u_int8_t RSVD9[4];
u_int32_t CE2DATA;
u_int32_t CE2ALE;
u_int32_t CE2CLE;
u_int8_t RSVD10[4];
u_int32_t CE3DATA;
u_int32_t CE3ALE;
u_int32_t CE3CLE;
} nand_registers;
typedef volatile nand_registers *nandregs;
#define NAND_READ_START 0x00
#define NAND_READ_END 0x30
#define NAND_STATUS 0x70
#ifdef CFG_NAND_HW_ECC
#define NAND_Ecc_P1e (1 << 0)
#define NAND_Ecc_P2e (1 << 1)
#define NAND_Ecc_P4e (1 << 2)
#define NAND_Ecc_P8e (1 << 3)
#define NAND_Ecc_P16e (1 << 4)
#define NAND_Ecc_P32e (1 << 5)
#define NAND_Ecc_P64e (1 << 6)
#define NAND_Ecc_P128e (1 << 7)
#define NAND_Ecc_P256e (1 << 8)
#define NAND_Ecc_P512e (1 << 9)
#define NAND_Ecc_P1024e (1 << 10)
#define NAND_Ecc_P2048e (1 << 11)
#define NAND_Ecc_P1o (1 << 16)
#define NAND_Ecc_P2o (1 << 17)
#define NAND_Ecc_P4o (1 << 18)
#define NAND_Ecc_P8o (1 << 19)
#define NAND_Ecc_P16o (1 << 20)
#define NAND_Ecc_P32o (1 << 21)
#define NAND_Ecc_P64o (1 << 22)
#define NAND_Ecc_P128o (1 << 23)
#define NAND_Ecc_P256o (1 << 24)
#define NAND_Ecc_P512o (1 << 25)
#define NAND_Ecc_P1024o (1 << 26)
#define NAND_Ecc_P2048o (1 << 27)
#define TF(v) (v ? 1 : 0)
#define P2048e(a) (TF(a & NAND_Ecc_P2048e) << 0)
#define P2048o(a) (TF(a & NAND_Ecc_P2048o) << 1)
#define P1e(a) (TF(a & NAND_Ecc_P1e) << 2)
#define P1o(a) (TF(a & NAND_Ecc_P1o) << 3)
#define P2e(a) (TF(a & NAND_Ecc_P2e) << 4)
#define P2o(a) (TF(a & NAND_Ecc_P2o) << 5)
#define P4e(a) (TF(a & NAND_Ecc_P4e) << 6)
#define P4o(a) (TF(a & NAND_Ecc_P4o) << 7)
#define P8e(a) (TF(a & NAND_Ecc_P8e) << 0)
#define P8o(a) (TF(a & NAND_Ecc_P8o) << 1)
#define P16e(a) (TF(a & NAND_Ecc_P16e) << 2)
#define P16o(a) (TF(a & NAND_Ecc_P16o) << 3)
#define P32e(a) (TF(a & NAND_Ecc_P32e) << 4)
#define P32o(a) (TF(a & NAND_Ecc_P32o) << 5)
#define P64e(a) (TF(a & NAND_Ecc_P64e) << 6)
#define P64o(a) (TF(a & NAND_Ecc_P64o) << 7)
#define P128e(a) (TF(a & NAND_Ecc_P128e) << 0)
#define P128o(a) (TF(a & NAND_Ecc_P128o) << 1)
#define P256e(a) (TF(a & NAND_Ecc_P256e) << 2)
#define P256o(a) (TF(a & NAND_Ecc_P256o) << 3)
#define P512e(a) (TF(a & NAND_Ecc_P512e) << 4)
#define P512o(a) (TF(a & NAND_Ecc_P512o) << 5)
#define P1024e(a) (TF(a & NAND_Ecc_P1024e) << 6)
#define P1024o(a) (TF(a & NAND_Ecc_P1024o) << 7)
#define P8e_s(a) (TF(a & NAND_Ecc_P8e) << 0)
#define P8o_s(a) (TF(a & NAND_Ecc_P8o) << 1)
#define P16e_s(a) (TF(a & NAND_Ecc_P16e) << 2)
#define P16o_s(a) (TF(a & NAND_Ecc_P16o) << 3)
#define P1e_s(a) (TF(a & NAND_Ecc_P1e) << 4)
#define P1o_s(a) (TF(a & NAND_Ecc_P1o) << 5)
#define P2e_s(a) (TF(a & NAND_Ecc_P2e) << 6)
#define P2o_s(a) (TF(a & NAND_Ecc_P2o) << 7)
#define P4e_s(a) (TF(a & NAND_Ecc_P4e) << 0)
#define P4o_s(a) (TF(a & NAND_Ecc_P4o) << 1)
#endif
#endif

33
include/asm-arm/arch-lpc2292/hardware.h Normal file
View File

@@ -0,0 +1,33 @@
#ifndef __ASM_ARCH_HARDWARE_H
#define __ASM_ARCH_HARDWARE_H
/*
* Copyright (c) 2004 Cucy Systems (http://www.cucy.com)
* Curt Brune <curt@cucy.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#if defined(CONFIG_LPC2292)
#include <asm-arm/arch-lpc2292/lpc2292_registers.h>
#else
#error No hardware file defined for this configuration
#endif
#endif /* __ASM_ARCH_HARDWARE_H */

0
include/asm-arm/arch-arm720t/lpc2292_registers.h → include/asm-arm/arch-lpc2292/lpc2292_registers.h
View File

0
include/asm-arm/arch-arm720t/mmc.h → include/asm-arm/arch-lpc2292/mmc.h
View File

82
include/asm-arm/arch-lpc2292/spi.h Normal file
View File

@@ -0,0 +1,82 @@
/*
This file defines the interface to the lpc22xx SPI module.
Copyright (C) 2006 Embedded Artists AB (www.embeddedartists.com)
This file may be included in software not adhering to the GPL.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef SPI_H
#define SPI_H
#include <config.h>
#include <common.h>
#include <asm/errno.h>
#include <asm/arch/hardware.h>
#define SPIF 0x80
#define spi_lock() disable_interrupts();
#define spi_unlock() enable_interrupts();
extern unsigned long spi_flags;
extern unsigned char spi_idle;
int spi_init(void);
static inline unsigned char spi_read(void)
{
unsigned char b;
PUT8(S0SPDR, spi_idle);
while (!(GET8(S0SPSR) & SPIF));
b = GET8(S0SPDR);
return b;
}
static inline void spi_write(unsigned char b)
{
PUT8(S0SPDR, b);
while (!(GET8(S0SPSR) & SPIF));
GET8(S0SPDR); /* this will clear the SPIF bit */
}
static inline void spi_set_clock(unsigned char clk_value)
{
PUT8(S0SPCCR, clk_value);
}
static inline void spi_set_cfg(unsigned char phase,
unsigned char polarity,
unsigned char lsbf)
{
unsigned char v = 0x20; /* master bit set */
if (phase)
v |= 0x08; /* set phase bit */
if (polarity) {
v |= 0x10; /* set polarity bit */
spi_idle = 0xFF;
} else {
spi_idle = 0x00;
}
if (lsbf)
v |= 0x40; /* set lsbf bit */
PUT8(S0SPCR, v);
}
#endif /* SPI_H */

39
include/asm-arm/arch-pxa/pxa-regs.h
View File

@@ -592,9 +592,11 @@ typedef void (*ExcpHndlr) (void) ;
#define PMC_REG_BASE __REG(0x40500400) /* Primary Modem Codec */
#define SMC_REG_BASE __REG(0x40500500) /* Secondary Modem Codec */
/*
* USB Device Controller
*/
#ifndef CONFIG_CPU_MONAHANS
#define UDC_RES1 __REG(0x40600004) /* UDC Undocumented - Reserved1 */
#define UDC_RES2 __REG(0x40600008) /* UDC Undocumented - Reserved2 */
#define UDC_RES3 __REG(0x4060000C) /* UDC Undocumented - Reserved3 */
@@ -749,11 +751,28 @@ typedef void (*ExcpHndlr) (void) ;
#define USIR1_IR13 (1 << 5) /* Interrup request ep 13 */
#define USIR1_IR14 (1 << 6) /* Interrup request ep 14 */
#define USIR1_IR15 (1 << 7) /* Interrup request ep 15 */
#endif /* ! CONFIG_CPU_MONAHANS */
#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
/*
* USB Client Controller (incomplete)
*/
#define UDCCR __REG(0x40600000)
#define UDCICR0 __REG(0x40600004)
#define UDCCIR0 __REG(0x40600008)
#define UDCISR0 __REG(0x4060000c)
#define UDCSIR1 __REG(0x40600010)
#define UDCFNR __REG(0x40600014)
#define UDCOTGICR __REG(0x40600018)
#define UDCOTGISR __REG(0x4060001c)
#define UP2OCR __REG(0x40600020)
#define UP3OCR __REG(0x40600024)
#if defined(CONFIG_PXA27X)
/*
* USB Host Controller
*/
#define OHCI_REGS_BASE 0x4C000000 /* required for ohci driver */
#define UHCREV __REG(0x4C000000)
#define UHCHCON __REG(0x4C000004)
#define UHCCOMS __REG(0x4C000008)
@@ -1269,15 +1288,15 @@ typedef void (*ExcpHndlr) (void) ;
#define _GEDR(x) __REG2(0x40E00048, ((x) & 0x60) >> 3)
#define _GAFR(x) __REG2(0x40E00054, ((x) & 0x70) >> 2)
#define GPLR(x) ((((x) & 0x7f) < 96) ? _GPLR(x) : GPLR3)
#define GPDR(x) ((((x) & 0x7f) < 96) ? _GPDR(x) : GPDR3)
#define GPSR(x) ((((x) & 0x7f) < 96) ? _GPSR(x) : GPSR3)
#define GPCR(x) ((((x) & 0x7f) < 96) ? _GPCR(x) : GPCR3)
#define GRER(x) ((((x) & 0x7f) < 96) ? _GRER(x) : GRER3)
#define GFER(x) ((((x) & 0x7f) < 96) ? _GFER(x) : GFER3)
#define GEDR(x) ((((x) & 0x7f) < 96) ? _GEDR(x) : GEDR3)
#define GAFR(x) ((((x) & 0x7f) < 96) ? _GAFR(x) : \
((((x) & 0x7f) < 112) ? GAFR3_L : GAFR3_U))
#define GPLR(x) __REG2(0x40E00000 + (((x) & 0x7f) < 96) ? 0:0x100, ((x) & 0x60) >> 3)
#define GPDR(x) __REG2(0x40E0000C + (((x) & 0x7f) < 96) ? 0:0x100, ((x) & 0x60) >> 3)
#define GPSR(x) __REG2(0x40E00018 + (((x) & 0x7f) < 96) ? 0:0x100, ((x) & 0x60) >> 3)
#define GPCR(x) __REG2(0x40E00024 + (((x) & 0x7f) < 96) ? 0:0x100, ((x) & 0x60) >> 3)
#define GRER(x) __REG2(0x40E00030 + (((x) & 0x7f) < 96) ? 0:0x100, ((x) & 0x60) >> 3)
#define GFER(x) __REG2(0x40E0003C + (((x) & 0x7f) < 96) ? 0:0x100, ((x) & 0x60) >> 3)
#define GEDR(x) __REG2(0x40E00048 + (((x) & 0x7f) < 96) ? 0:0x100, ((x) & 0x60) >> 3)
#define GAFR(x) __REG2((((x) & 0x7f) < 96) ? 0x40E00054 : \
((((x) & 0x7f) < 112) ? 0x40E0006C : 0x40E00070),((x) & 0x60) >> 3)
#else
#define GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3)

69
include/asm-arm/mach-types.h
View File

@@ -736,7 +736,11 @@ extern unsigned int __machine_arch_type;
#define MACH_TYPE_LN2410SBC 725
#define MACH_TYPE_CB3RUFC 726
#define MACH_TYPE_MP2USB 727
#define MACH_TYPE_AT91SAM9261EK 848
#define MACH_TYPE_PDNB3 1002
#define MACH_TYPE_AT91SAM9260EK 1099
#define MACH_TYPE_AT91RM9200DF 1119
#define MACH_TYPE_AT91SAM9263EK 1202
#ifdef CONFIG_ARCH_EBSA110
# ifdef machine_arch_type
@@ -9402,6 +9406,71 @@ extern unsigned int __machine_arch_type;
# define machine_is_mp2usb() (0)
#endif
#ifdef CONFIG_MACH_AT91SAM9261EK
# ifdef machine_arch_type
# undef machine_arch_type
# define machine_arch_type __machine_arch_type
# else
# define machine_arch_type MACH_TYPE_AT91SAM9261EK
# endif
# define machine_is_at91sam9261ek() \
(machine_arch_type == MACH_TYPE_AT91SAM9261EK)
#else
# define machine_is_at91sam9261ek() (0)
#endif
#ifdef CONFIG_MACH_AT91SAM9260EK
# ifdef machine_arch_type
# undef machine_arch_type
# define machine_arch_type __machine_arch_type
# else
# define machine_arch_type MACH_TYPE_AT91SAM9260EK
# endif
# define machine_is_at91sam9260ek() \
(machine_arch_type == MACH_TYPE_AT91SAM9260EK)
#else
# define machine_is_at91sam9260ek() (0)
#endif
#ifdef CONFIG_MACH_AT91SAM9263EK
# ifdef machine_arch_type
# undef machine_arch_type
# define machine_arch_type __machine_arch_type
# else
# define machine_arch_type MACH_TYPE_AT91SAM9263EK
# endif
# define machine_is_at91sam9263ek() \
(machine_arch_type == MACH_TYPE_AT91SAM9263EK)
#else
# define machine_is_at91sam9263ek() (0)
#endif
#ifdef CONFIG_MACH_AT91RM9200DF
# ifdef machine_arch_type
# undef machine_arch_type
# define machine_arch_type __machine_arch_type
# else
# define machine_arch_type MACH_TYPE_AT91RM9200DF
# endif
# define machine_is_at91rm9200df() \
(machine_arch_type == MACH_TYPE_AT91RM9200DF)
#else
# define machine_is_at91rm9200df() (0)
#endif
#ifdef CONFIG_MACH_AT91SAM9263EK
# ifdef machine_arch_type
# undef machine_arch_type
# define machine_arch_type __machine_arch_type
# else
# define machine_arch_type MACH_TYPE_AT91SAM9263EK
# endif
# define machine_is_at91sam9263ek() \
(machine_arch_type == MACH_TYPE_AT91SAM9263EK)
#else
# define machine_is_at91sam9263ek() (0)
#endif
/*
* These have not yet been registered
*/

39
include/asm-m68k/bitops.h
View File

@@ -15,4 +15,43 @@ extern int test_and_set_bit(int nr, volatile void *addr);
extern int test_and_clear_bit(int nr, volatile void *addr);
extern int test_and_change_bit(int nr, volatile void *addr);
#ifdef __KERNEL__
/*
* ffs: find first bit set. This is defined the same way as
* the libc and compiler builtin ffs routines, therefore
* differs in spirit from the above ffz (man ffs).
*/
extern __inline__ int ffs(int x)
{
int r = 1;
if (!x)
return 0;
if (!(x & 0xffff)) {
x >>= 16;
r += 16;
}
if (!(x & 0xff)) {
x >>= 8;
r += 8;
}
if (!(x & 0xf)) {
x >>= 4;
r += 4;
}
if (!(x & 3)) {
x >>= 2;
r += 2;
}
if (!(x & 1)) {
x >>= 1;
r += 1;
}
return r;
}
#define __ffs(x) (ffs(x) - 1)
#endif /* __KERNEL__ */
#endif /* _M68K_BITOPS_H */

102
include/asm-m68k/byteorder.h
View File

@@ -1,7 +1,107 @@
/*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _M68K_BYTEORDER_H
#define _M68K_BYTEORDER_H
#include <asm/types.h>
#ifdef __GNUC__
#define __sw16(x) \
((__u16)( \
(((__u16)(x) & (__u16)0x00ffU) << 8) | \
(((__u16)(x) & (__u16)0xff00U) >> 8) ))
#define __sw32(x) \
((__u32)( \
(((__u32)(x)) << 24) | \
(((__u32)(x) & (__u32)0x0000ff00UL) << 8) | \
(((__u32)(x) & (__u32)0x00ff0000UL) >> 8) | \
(((__u32)(x)) >> 24) ))
extern __inline__ unsigned ld_le16(const volatile unsigned short *addr)
{
unsigned result = *addr;
return __sw16(result);
}
extern __inline__ void st_le16(volatile unsigned short *addr,
const unsigned val)
{
*addr = __sw16(val);
}
extern __inline__ unsigned ld_le32(const volatile unsigned *addr)
{
unsigned result = *addr;
return __sw32(result);
}
extern __inline__ void st_le32(volatile unsigned *addr, const unsigned val)
{
*addr = __sw32(val);
}
#if 0
/* alas, egcs sounds like it has a bug in this code that doesn't use the
inline asm correctly, and can cause file corruption. Until I hear that
it's fixed, I can live without the extra speed. I hope. */
#if !(__GNUC__ >= 2 && __GNUC_MINOR__ >= 90)
#if 0
# define __arch_swab16(x) ld_le16(&x)
# define __arch_swab32(x) ld_le32(&x)
#else
static __inline__ __attribute__ ((const))
__u16 ___arch__swab16(__u16 value)
{
return __sw16(value);
}
static __inline__ __attribute__ ((const))
__u32 ___arch__swab32(__u32 value)
{
return __sw32(value);
}
#define __arch__swab32(x) ___arch__swab32(x)
#define __arch__swab16(x) ___arch__swab16(x)
#endif /* 0 */
#endif
/* The same, but returns converted value from the location pointer by addr. */
#define __arch__swab16p(addr) ld_le16(addr)
#define __arch__swab32p(addr) ld_le32(addr)
/* The same, but do the conversion in situ, ie. put the value back to addr. */
#define __arch__swab16s(addr) st_le16(addr,*addr)
#define __arch__swab32s(addr) st_le32(addr,*addr)
#endif
#endif /* __GNUC__ */
#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
#define __BYTEORDER_HAS_U64__
#endif
#include <linux/byteorder/big_endian.h>
#endif /* _M68K_BYTEORDER_H */
#endif /* _M68K_BYTEORDER_H */

138
include/asm-m68k/errno.h Normal file
View File

@@ -0,0 +1,138 @@
#ifndef _PPC_ERRNO_H
#define _PPC_ERRNO_H
#define EPERM 1 /* Operation not permitted */
#define ENOENT 2 /* No such file or directory */
#define ESRCH 3 /* No such process */
#define EINTR 4 /* Interrupted system call */
#define EIO 5 /* I/O error */
#define ENXIO 6 /* No such device or address */
#define E2BIG 7 /* Arg list too long */
#define ENOEXEC 8 /* Exec format error */
#define EBADF 9 /* Bad file number */
#define ECHILD 10 /* No child processes */
#define EAGAIN 11 /* Try again */
#define ENOMEM 12 /* Out of memory */
#define EACCES 13 /* Permission denied */
#define EFAULT 14 /* Bad address */
#define ENOTBLK 15 /* Block device required */
#define EBUSY 16 /* Device or resource busy */
#define EEXIST 17 /* File exists */
#define EXDEV 18 /* Cross-device link */
#define ENODEV 19 /* No such device */
#define ENOTDIR 20 /* Not a directory */
#define EISDIR 21 /* Is a directory */
#define EINVAL 22 /* Invalid argument */
#define ENFILE 23 /* File table overflow */
#define EMFILE 24 /* Too many open files */
#define ENOTTY 25 /* Not a typewriter */
#define ETXTBSY 26 /* Text file busy */
#define EFBIG 27 /* File too large */
#define ENOSPC 28 /* No space left on device */
#define ESPIPE 29 /* Illegal seek */
#define EROFS 30 /* Read-only file system */
#define EMLINK 31 /* Too many links */
#define EPIPE 32 /* Broken pipe */
#define EDOM 33 /* Math argument out of domain of func */
#define ERANGE 34 /* Math result not representable */
#define EDEADLK 35 /* Resource deadlock would occur */
#define ENAMETOOLONG 36 /* File name too long */
#define ENOLCK 37 /* No record locks available */
#define ENOSYS 38 /* Function not implemented */
#define ENOTEMPTY 39 /* Directory not empty */
#define ELOOP 40 /* Too many symbolic links encountered */
#define EWOULDBLOCK EAGAIN /* Operation would block */
#define ENOMSG 42 /* No message of desired type */
#define EIDRM 43 /* Identifier removed */
#define ECHRNG 44 /* Channel number out of range */
#define EL2NSYNC 45 /* Level 2 not synchronized */
#define EL3HLT 46 /* Level 3 halted */
#define EL3RST 47 /* Level 3 reset */
#define ELNRNG 48 /* Link number out of range */
#define EUNATCH 49 /* Protocol driver not attached */
#define ENOCSI 50 /* No CSI structure available */
#define EL2HLT 51 /* Level 2 halted */
#define EBADE 52 /* Invalid exchange */
#define EBADR 53 /* Invalid request descriptor */
#define EXFULL 54 /* Exchange full */
#define ENOANO 55 /* No anode */
#define EBADRQC 56 /* Invalid request code */
#define EBADSLT 57 /* Invalid slot */
#define EDEADLOCK 58 /* File locking deadlock error */
#define EBFONT 59 /* Bad font file format */
#define ENOSTR 60 /* Device not a stream */
#define ENODATA 61 /* No data available */
#define ETIME 62 /* Timer expired */
#define ENOSR 63 /* Out of streams resources */
#define ENONET 64 /* Machine is not on the network */
#define ENOPKG 65 /* Package not installed */
#define EREMOTE 66 /* Object is remote */
#define ENOLINK 67 /* Link has been severed */
#define EADV 68 /* Advertise error */
#define ESRMNT 69 /* Srmount error */
#define ECOMM 70 /* Communication error on send */
#define EPROTO 71 /* Protocol error */
#define EMULTIHOP 72 /* Multihop attempted */
#define EDOTDOT 73 /* RFS specific error */
#define EBADMSG 74 /* Not a data message */
#define EOVERFLOW 75 /* Value too large for defined data type */
#define ENOTUNIQ 76 /* Name not unique on network */
#define EBADFD 77 /* File descriptor in bad state */
#define EREMCHG 78 /* Remote address changed */
#define ELIBACC 79 /* Can not access a needed shared library */
#define ELIBBAD 80 /* Accessing a corrupted shared library */
#define ELIBSCN 81 /* .lib section in a.out corrupted */
#define ELIBMAX 82 /* Attempting to link in too many shared libraries */
#define ELIBEXEC 83 /* Cannot exec a shared library directly */
#define EILSEQ 84 /* Illegal byte sequence */
#define ERESTART 85 /* Interrupted system call should be restarted */
#define ESTRPIPE 86 /* Streams pipe error */
#define EUSERS 87 /* Too many users */
#define ENOTSOCK 88 /* Socket operation on non-socket */
#define EDESTADDRREQ 89 /* Destination address required */
#define EMSGSIZE 90 /* Message too long */
#define EPROTOTYPE 91 /* Protocol wrong type for socket */
#define ENOPROTOOPT 92 /* Protocol not available */
#define EPROTONOSUPPORT 93 /* Protocol not supported */
#define ESOCKTNOSUPPORT 94 /* Socket type not supported */
#define EOPNOTSUPP 95 /* Operation not supported on transport endpoint */
#define EPFNOSUPPORT 96 /* Protocol family not supported */
#define EAFNOSUPPORT 97 /* Address family not supported by protocol */
#define EADDRINUSE 98 /* Address already in use */
#define EADDRNOTAVAIL 99 /* Cannot assign requested address */
#define ENETDOWN 100 /* Network is down */
#define ENETUNREACH 101 /* Network is unreachable */
#define ENETRESET 102 /* Network dropped connection because of reset */
#define ECONNABORTED 103 /* Software caused connection abort */
#define ECONNRESET 104 /* Connection reset by peer */
#define ENOBUFS 105 /* No buffer space available */
#define EISCONN 106 /* Transport endpoint is already connected */
#define ENOTCONN 107 /* Transport endpoint is not connected */
#define ESHUTDOWN 108 /* Cannot send after transport endpoint shutdown */
#define ETOOMANYREFS 109 /* Too many references: cannot splice */
#define ETIMEDOUT 110 /* Connection timed out */
#define ECONNREFUSED 111 /* Connection refused */
#define EHOSTDOWN 112 /* Host is down */
#define EHOSTUNREACH 113 /* No route to host */
#define EALREADY 114 /* Operation already in progress */
#define EINPROGRESS 115 /* Operation now in progress */
#define ESTALE 116 /* Stale NFS file handle */
#define EUCLEAN 117 /* Structure needs cleaning */
#define ENOTNAM 118 /* Not a XENIX named type file */
#define ENAVAIL 119 /* No XENIX semaphores available */
#define EISNAM 120 /* Is a named type file */
#define EREMOTEIO 121 /* Remote I/O error */
#define EDQUOT 122 /* Quota exceeded */
#define ENOMEDIUM 123 /* No medium found */
#define EMEDIUMTYPE 124 /* Wrong medium type */
/* Should never be seen by user programs */
#define ERESTARTSYS 512
#define ERESTARTNOINTR 513
#define ERESTARTNOHAND 514 /* restart if no handler.. */
#define ENOIOCTLCMD 515 /* No ioctl command */
#define _LAST_ERRNO 515
#endif

277
include/asm-m68k/fec.h
View File

@@ -5,6 +5,10 @@
* MPC8xx Communication Processor Module.
* Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
*
* Add FEC Structure and definitions
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
@@ -30,9 +34,9 @@
/* Buffer descriptors used FEC.
*/
typedef struct cpm_buf_desc {
ushort cbd_sc; /* Status and Control */
ushort cbd_datlen; /* Data length in buffer */
uint cbd_bufaddr; /* Buffer address in host memory */
ushort cbd_sc; /* Status and Control */
ushort cbd_datlen; /* Data length in buffer */
uint cbd_bufaddr; /* Buffer address in host memory */
} cbd_t;
#define BD_SC_EMPTY ((ushort)0x8000) /* Recieve is empty */
@@ -53,28 +57,36 @@ typedef struct cpm_buf_desc {
/* Buffer descriptor control/status used by Ethernet receive.
*/
#define BD_ENET_RX_EMPTY ((ushort)0x8000)
#define BD_ENET_RX_RO1 ((ushort)0x4000)
#define BD_ENET_RX_WRAP ((ushort)0x2000)
#define BD_ENET_RX_INTR ((ushort)0x1000)
#define BD_ENET_RX_RO2 BD_ENET_RX_INTR
#define BD_ENET_RX_LAST ((ushort)0x0800)
#define BD_ENET_RX_FIRST ((ushort)0x0400)
#define BD_ENET_RX_MISS ((ushort)0x0100)
#define BD_ENET_RX_BC ((ushort)0x0080)
#define BD_ENET_RX_MC ((ushort)0x0040)
#define BD_ENET_RX_LG ((ushort)0x0020)
#define BD_ENET_RX_NO ((ushort)0x0010)
#define BD_ENET_RX_SH ((ushort)0x0008)
#define BD_ENET_RX_CR ((ushort)0x0004)
#define BD_ENET_RX_OV ((ushort)0x0002)
#define BD_ENET_RX_CL ((ushort)0x0001)
#define BD_ENET_RX_TR BD_ENET_RX_CL
#define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */
/* Buffer descriptor control/status used by Ethernet transmit.
*/
#define BD_ENET_TX_READY ((ushort)0x8000)
#define BD_ENET_TX_PAD ((ushort)0x4000)
#define BD_ENET_TX_TO1 BD_ENET_TX_PAD
#define BD_ENET_TX_WRAP ((ushort)0x2000)
#define BD_ENET_TX_INTR ((ushort)0x1000)
#define BD_ENET_TX_TO2 BD_ENET_TX_INTR_
#define BD_ENET_TX_LAST ((ushort)0x0800)
#define BD_ENET_TX_TC ((ushort)0x0400)
#define BD_ENET_TX_DEF ((ushort)0x0200)
#define BD_ENET_TX_ABC BD_ENET_TX_DEF
#define BD_ENET_TX_HB ((ushort)0x0100)
#define BD_ENET_TX_LC ((ushort)0x0080)
#define BD_ENET_TX_RL ((ushort)0x0040)
@@ -83,4 +95,261 @@ typedef struct cpm_buf_desc {
#define BD_ENET_TX_CSL ((ushort)0x0001)
#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */
#endif /* fec_h */
#ifdef CONFIG_MCFFEC
/*********************************************************************
*
* Fast Ethernet Controller (FEC)
*
*********************************************************************/
/* FEC private information */
struct fec_info_s {
int index;
u32 iobase;
u32 pinmux;
u32 miibase;
int phy_addr;
int dup_spd;
char *phy_name;
int phyname_init;
cbd_t *rxbd; /* Rx BD */
cbd_t *txbd; /* Tx BD */
uint rxIdx;
uint txIdx;
char *txbuf;
int initialized;
};
/* Register read/write struct */
typedef struct fec {
#ifdef CONFIG_M5272
u32 ecr; /* 0x00 */
u32 eir; /* 0x04 */
u32 eimr; /* 0x08 */
u32 ivsr; /* 0x0C */
u32 rdar; /* 0x10 */
u32 tdar; /* 0x14 */
u8 resv1[0x28]; /* 0x18 */
u32 mmfr; /* 0x40 */
u32 mscr; /* 0x44 */
u8 resv2[0x44]; /* 0x48 */
u32 frbr; /* 0x8C */
u32 frsr; /* 0x90 */
u8 resv3[0x10]; /* 0x94 */
u32 tfwr; /* 0xA4 */
u32 res4; /* 0xA8 */
u32 tfsr; /* 0xAC */
u8 resv4[0x50]; /* 0xB0 */
u32 opd; /* 0x100 - dummy */
u32 rcr; /* 0x104 */
u32 mibc; /* 0x108 */
u8 resv5[0x38]; /* 0x10C */
u32 tcr; /* 0x144 */
u8 resv6[0x270]; /* 0x148 */
u32 iaur; /* 0x3B8 - dummy */
u32 ialr; /* 0x3BC - dummy */
u32 palr; /* 0x3C0 */
u32 paur; /* 0x3C4 */
u32 gaur; /* 0x3C8 */
u32 galr; /* 0x3CC */
u32 erdsr; /* 0x3D0 */
u32 etdsr; /* 0x3D4 */
u32 emrbr; /* 0x3D8 */
u8 resv12[0x74]; /* 0x18C */
#else
u8 resv0[0x4];
u32 eir;
u32 eimr;
u8 resv1[0x4];
u32 rdar;
u32 tdar;
u8 resv2[0xC];
u32 ecr;
u8 resv3[0x18];
u32 mmfr;
u32 mscr;
u8 resv4[0x1C];
u32 mibc;
u8 resv5[0x1C];
u32 rcr;
u8 resv6[0x3C];
u32 tcr;
u8 resv7[0x1C];
u32 palr;
u32 paur;
u32 opd;
u8 resv8[0x28];
u32 iaur;
u32 ialr;
u32 gaur;
u32 galr;
u8 resv9[0x1C];
u32 tfwr;
u8 resv10[0x4];
u32 frbr;
u32 frsr;
u8 resv11[0x2C];
u32 erdsr;
u32 etdsr;
u32 emrbr;
u8 resv12[0x74];
#endif
u32 rmon_t_drop;
u32 rmon_t_packets;
u32 rmon_t_bc_pkt;
u32 rmon_t_mc_pkt;
u32 rmon_t_crc_align;
u32 rmon_t_undersize;
u32 rmon_t_oversize;
u32 rmon_t_frag;
u32 rmon_t_jab;
u32 rmon_t_col;
u32 rmon_t_p64;
u32 rmon_t_p65to127;
u32 rmon_t_p128to255;
u32 rmon_t_p256to511;
u32 rmon_t_p512to1023;
u32 rmon_t_p1024to2047;
u32 rmon_t_p_gte2048;
u32 rmon_t_octets;
u32 ieee_t_drop;
u32 ieee_t_frame_ok;
u32 ieee_t_1col;
u32 ieee_t_mcol;
u32 ieee_t_def;
u32 ieee_t_lcol;
u32 ieee_t_excol;
u32 ieee_t_macerr;
u32 ieee_t_cserr;
u32 ieee_t_sqe;
u32 ieee_t_fdxfc;
u32 ieee_t_octets_ok;
u8 resv13[0x8];
u32 rmon_r_drop;
u32 rmon_r_packets;
u32 rmon_r_bc_pkt;
u32 rmon_r_mc_pkt;
u32 rmon_r_crc_align;
u32 rmon_r_undersize;
u32 rmon_r_oversize;
u32 rmon_r_frag;
u32 rmon_r_jab;
u32 rmon_r_resvd_0;
u32 rmon_r_p64;
u32 rmon_r_p65to127;
u32 rmon_r_p128to255;
u32 rmon_r_p256to511;
u32 rmon_r_p512to1023;
u32 rmon_r_p1024to2047;
u32 rmon_r_p_gte2048;
u32 rmon_r_octets;
u32 ieee_r_drop;
u32 ieee_r_frame_ok;
u32 ieee_r_crc;
u32 ieee_r_align;
u32 ieee_r_macerr;
u32 ieee_r_fdxfc;
u32 ieee_r_octets_ok;
} fec_t;
/*********************************************************************
* Fast Ethernet Controller (FEC)
*********************************************************************/
/* Bit definitions and macros for FEC_EIR */
#define FEC_EIR_CLEAR_ALL (0xFFF80000)
#define FEC_EIR_HBERR (0x80000000)
#define FEC_EIR_BABR (0x40000000)
#define FEC_EIR_BABT (0x20000000)
#define FEC_EIR_GRA (0x10000000)
#define FEC_EIR_TXF (0x08000000)
#define FEC_EIR_TXB (0x04000000)
#define FEC_EIR_RXF (0x02000000)
#define FEC_EIR_RXB (0x01000000)
#define FEC_EIR_MII (0x00800000)
#define FEC_EIR_EBERR (0x00400000)
#define FEC_EIR_LC (0x00200000)
#define FEC_EIR_RL (0x00100000)
#define FEC_EIR_UN (0x00080000)
/* Bit definitions and macros for FEC_RDAR */
#define FEC_RDAR_R_DES_ACTIVE (0x01000000)
/* Bit definitions and macros for FEC_TDAR */
#define FEC_TDAR_X_DES_ACTIVE (0x01000000)
/* Bit definitions and macros for FEC_ECR */
#define FEC_ECR_ETHER_EN (0x00000002)
#define FEC_ECR_RESET (0x00000001)
/* Bit definitions and macros for FEC_MMFR */
#define FEC_MMFR_DATA(x) (((x)&0xFFFF))
#define FEC_MMFR_ST(x) (((x)&0x03)<<30)
#define FEC_MMFR_ST_01 (0x40000000)
#define FEC_MMFR_OP_RD (0x20000000)
#define FEC_MMFR_OP_WR (0x10000000)
#define FEC_MMFR_PA(x) (((x)&0x1F)<<23)
#define FEC_MMFR_RA(x) (((x)&0x1F)<<18)
#define FEC_MMFR_TA(x) (((x)&0x03)<<16)
#define FEC_MMFR_TA_10 (0x00020000)
/* Bit definitions and macros for FEC_MSCR */
#define FEC_MSCR_DIS_PREAMBLE (0x00000080)
#define FEC_MSCR_MII_SPEED(x) (((x)&0x3F)<<1)
/* Bit definitions and macros for FEC_MIBC */
#define FEC_MIBC_MIB_DISABLE (0x80000000)
#define FEC_MIBC_MIB_IDLE (0x40000000)
/* Bit definitions and macros for FEC_RCR */
#define FEC_RCR_MAX_FL(x) (((x)&0x7FF)<<16)
#define FEC_RCR_FCE (0x00000020)
#define FEC_RCR_BC_REJ (0x00000010)
#define FEC_RCR_PROM (0x00000008)
#define FEC_RCR_MII_MODE (0x00000004)
#define FEC_RCR_DRT (0x00000002)
#define FEC_RCR_LOOP (0x00000001)
/* Bit definitions and macros for FEC_TCR */
#define FEC_TCR_RFC_PAUSE (0x00000010)
#define FEC_TCR_TFC_PAUSE (0x00000008)
#define FEC_TCR_FDEN (0x00000004)
#define FEC_TCR_HBC (0x00000002)
#define FEC_TCR_GTS (0x00000001)
/* Bit definitions and macros for FEC_PAUR */
#define FEC_PAUR_PADDR2(x) (((x)&0xFFFF)<<16)
#define FEC_PAUR_TYPE(x) ((x)&0xFFFF)
/* Bit definitions and macros for FEC_OPD */
#define FEC_OPD_PAUSE_DUR(x) (((x)&0x0000FFFF)<<0)
#define FEC_OPD_OPCODE(x) (((x)&0x0000FFFF)<<16)
/* Bit definitions and macros for FEC_TFWR */
#define FEC_TFWR_X_WMRK(x) ((x)&0x03)
#define FEC_TFWR_X_WMRK_64 (0x01)
#define FEC_TFWR_X_WMRK_128 (0x02)
#define FEC_TFWR_X_WMRK_192 (0x03)
/* Bit definitions and macros for FEC_FRBR */
#define FEC_FRBR_R_BOUND(x) (((x)&0xFF)<<2)
/* Bit definitions and macros for FEC_FRSR */
#define FEC_FRSR_R_FSTART(x) (((x)&0xFF)<<2)
/* Bit definitions and macros for FEC_ERDSR */
#define FEC_ERDSR_R_DES_START(x) (((x)&0x3FFFFFFF)<<2)
/* Bit definitions and macros for FEC_ETDSR */
#define FEC_ETDSR_X_DES_START(x) (((x)&0x3FFFFFFF)<<2)
/* Bit definitions and macros for FEC_EMRBR */
#define FEC_EMRBR_R_BUF_SIZE(x) (((x)&0x7F)<<4)
#define FEC_RESET_DELAY 100
#define FEC_RX_TOUT 100
#endif /* CONFIG_MCFFEC */
#endif /* fec_h */

86
include/asm-m68k/fsl_i2c.h Normal file
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@@ -0,0 +1,86 @@
/*
* Freescale I2C Controller
*
* Copyright 2006 Freescale Semiconductor, Inc.
*
* Based on earlier versions by Gleb Natapov <gnatapov@mrv.com>,
* Xianghua Xiao <x.xiao@motorola.com>, Eran Liberty (liberty@freescale.com),
* and Jeff Brown.
* Some bits are taken from linux driver writen by adrian@humboldt.co.uk.
*
* This software may be used and distributed according to the
* terms of the GNU Public License, Version 2, incorporated
* herein by reference.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* Version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _ASM_FSL_I2C_H_
#define _ASM_FSL_I2C_H_
#include <asm/types.h>
typedef struct fsl_i2c {
u8 adr; /* I2C slave address */
u8 res0[3];
#define I2C_ADR 0xFE
#define I2C_ADR_SHIFT 1
#define I2C_ADR_RES ~(I2C_ADR)
u8 fdr; /* I2C frequency divider register */
u8 res1[3];
#define IC2_FDR 0x3F
#define IC2_FDR_SHIFT 0
#define IC2_FDR_RES ~(IC2_FDR)
u8 cr; /* I2C control redister */
u8 res2[3];
#define I2C_CR_MEN 0x80
#define I2C_CR_MIEN 0x40
#define I2C_CR_MSTA 0x20
#define I2C_CR_MTX 0x10
#define I2C_CR_TXAK 0x08
#define I2C_CR_RSTA 0x04
#define I2C_CR_BCST 0x01
u8 sr; /* I2C status register */
u8 res3[3];
#define I2C_SR_MCF 0x80
#define I2C_SR_MAAS 0x40
#define I2C_SR_MBB 0x20
#define I2C_SR_MAL 0x10
#define I2C_SR_BCSTM 0x08
#define I2C_SR_SRW 0x04
#define I2C_SR_MIF 0x02
#define I2C_SR_RXAK 0x01
u8 dr; /* I2C data register */
u8 res4[3];
#define I2C_DR 0xFF
#define I2C_DR_SHIFT 0
#define I2C_DR_RES ~(I2C_DR)
u8 dfsrr; /* I2C digital filter sampling rate register */
u8 res5[3];
#define I2C_DFSRR 0x3F
#define I2C_DFSRR_SHIFT 0
#define I2C_DFSRR_RES ~(I2C_DR)
/* Fill out the reserved block */
u8 res6[0xE8];
} fsl_i2c_t;
#endif /* _ASM_I2C_H_ */

8
include/asm-m68k/global_data.h
View File

@@ -39,6 +39,14 @@ typedef struct global_data {
unsigned long baudrate;
unsigned long cpu_clk; /* CPU clock in Hz! */
unsigned long bus_clk;
#ifdef CONFIG_PCI
unsigned long pci_clk;
#endif
#ifdef CONFIG_EXTRA_CLOCK
unsigned long inp_clk;
unsigned long vco_clk;
unsigned long flb_clk;
#endif
unsigned long ram_size; /* RAM size */
unsigned long reloc_off; /* Relocation Offset */
unsigned long reset_status; /* reset status register at boot */

242
include/asm-m68k/immap.h Normal file
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@@ -0,0 +1,242 @@
/*
* ColdFire Internal Memory Map and Defines
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __IMMAP_H
#define __IMMAP_H
#ifdef CONFIG_M5235
#include <asm/immap_5235.h>
#include <asm/m5235.h>
#define CFG_FEC0_IOBASE (MMAP_FEC)
#define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x40))
/* Timer */
#ifdef CONFIG_MCFTMR
#define CFG_UDELAY_BASE (MMAP_DTMR0)
#define CFG_TMR_BASE (MMAP_DTMR3)
#define CFG_TMRPND_REG (((volatile int0_t *)(CFG_INTR_BASE))->iprl0)
#define CFG_TMRINTR_NO (INT0_LO_DTMR3)
#define CFG_TMRINTR_MASK (INTC_IPRL_INT22)
#define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK)
#define CFG_TMRINTR_PRI (0x1E) /* Level must include inorder to work */
#define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
#endif
#ifdef CONFIG_MCFPIT
#define CFG_UDELAY_BASE (MMAP_PIT0)
#define CFG_PIT_BASE (MMAP_PIT1)
#define CFG_PIT_PRESCALE (6)
#endif
#define CFG_INTR_BASE (MMAP_INTC0)
#define CFG_NUM_IRQS (128)
#endif /* CONFIG_M5235 */
#ifdef CONFIG_M5249
#include <asm/immap_5249.h>
#include <asm/m5249.h>
#define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x40))
#define CFG_INTR_BASE (MMAP_INTC)
#define CFG_NUM_IRQS (64)
/* Timer */
#ifdef CONFIG_MCFTMR
#define CFG_UDELAY_BASE (MMAP_DTMR0)
#define CFG_TMR_BASE (MMAP_DTMR1)
#define CFG_TMRPND_REG (mbar_readLong(MCFSIM_IPR))
#define CFG_TMRINTR_NO (31)
#define CFG_TMRINTR_MASK (0x00000400)
#define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK)
#define CFG_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3)
#define CFG_TIMER_PRESCALER (((gd->bus_clk / 2000000) - 1) << 8)
#endif
#endif /* CONFIG_M5249 */
#ifdef CONFIG_M5253
#include <asm/immap_5253.h>
#include <asm/m5249.h>
#include <asm/m5253.h>
#define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x40))
#define CFG_INTR_BASE (MMAP_INTC)
#define CFG_NUM_IRQS (64)
/* Timer */
#ifdef CONFIG_MCFTMR
#define CFG_UDELAY_BASE (MMAP_DTMR0)
#define CFG_TMR_BASE (MMAP_DTMR1)
#define CFG_TMRPND_REG (mbar_readLong(MCFSIM_IPR))
#define CFG_TMRINTR_NO (27)
#define CFG_TMRINTR_MASK (0x00000400)
#define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK)
#define CFG_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL3 | MCFSIM_ICR_PRI3)
#define CFG_TIMER_PRESCALER (((gd->bus_clk / 2000000) - 1) << 8)
#endif
#endif /* CONFIG_M5253 */
#ifdef CONFIG_M5271
#include <asm/immap_5271.h>
#include <asm/m5271.h>
#define CFG_FEC0_IOBASE (MMAP_FEC)
#define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x40))
/* Timer */
#ifdef CONFIG_MCFTMR
#define CFG_UDELAY_BASE (MMAP_DTMR0)
#define CFG_TMR_BASE (MMAP_DTMR3)
#define CFG_TMRPND_REG (((volatile int0_t *)(CFG_INTR_BASE))->iprl0)
#define CFG_TMRINTR_NO (INT0_LO_DTMR3)
#define CFG_TMRINTR_MASK (INTC_IPRL_INT22)
#define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK)
#define CFG_TMRINTR_PRI (0) /* Level must include inorder to work */
#define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
#endif
#define CFG_INTR_BASE (MMAP_INTC0)
#define CFG_NUM_IRQS (128)
#endif /* CONFIG_M5271 */
#ifdef CONFIG_M5272
#include <asm/immap_5272.h>
#include <asm/m5272.h>
#define CFG_FEC0_IOBASE (MMAP_FEC)
#define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x40))
#define CFG_INTR_BASE (MMAP_INTC)
#define CFG_NUM_IRQS (64)
/* Timer */
#ifdef CONFIG_MCFTMR
#define CFG_UDELAY_BASE (MMAP_TMR0)
#define CFG_TMR_BASE (MMAP_TMR3)
#define CFG_TMRPND_REG (((volatile intctrl_t *)(CFG_INTR_BASE))->int_isr)
#define CFG_TMRINTR_NO (INT_TMR3)
#define CFG_TMRINTR_MASK (INT_ISR_INT24)
#define CFG_TMRINTR_PEND (0)
#define CFG_TMRINTR_PRI (INT_ICR1_TMR3PI | INT_ICR1_TMR3IPL(5))
#define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
#endif
#endif /* CONFIG_M5272 */
#ifdef CONFIG_M5282
#include <asm/immap_5282.h>
#include <asm/m5282.h>
#define CFG_FEC0_IOBASE (MMAP_FEC)
#define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x40))
#define CFG_INTR_BASE (MMAP_INTC0)
#define CFG_NUM_IRQS (128)
/* Timer */
#ifdef CONFIG_MCFTMR
#define CFG_UDELAY_BASE (MMAP_DTMR0)
#define CFG_TMR_BASE (MMAP_DTMR3)
#define CFG_TMRPND_REG (((volatile int0_t *)(CFG_INTR_BASE))->iprl0)
#define CFG_TMRINTR_NO (INT0_LO_DTMR3)
#define CFG_TMRINTR_MASK (1 << INT0_LO_DTMR3)
#define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK)
#define CFG_TMRINTR_PRI (0x1E) /* Level must include inorder to work */
#define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
#endif
#endif /* CONFIG_M5282 */
#ifdef CONFIG_M5329
#include <asm/immap_5329.h>
#include <asm/m5329.h>
#define CFG_FEC0_IOBASE (MMAP_FEC)
#define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x4000))
#define CFG_MCFRTC_BASE (MMAP_RTC)
/* Timer */
#ifdef CONFIG_MCFTMR
#define CFG_UDELAY_BASE (MMAP_DTMR0)
#define CFG_TMR_BASE (MMAP_DTMR1)
#define CFG_TMRPND_REG (((volatile int0_t *)(CFG_INTR_BASE))->iprh0)
#define CFG_TMRINTR_NO (INT0_HI_DTMR1)
#define CFG_TMRINTR_MASK (INTC_IPRH_INT33)
#define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK)
#define CFG_TMRINTR_PRI (6)
#define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
#endif
#ifdef CONFIG_MCFPIT
#define CFG_UDELAY_BASE (MMAP_PIT0)
#define CFG_PIT_BASE (MMAP_PIT1)
#define CFG_PIT_PRESCALE (6)
#endif
#define CFG_INTR_BASE (MMAP_INTC0)
#define CFG_NUM_IRQS (128)
#endif /* CONFIG_M5329 */
#ifdef CONFIG_M54455
#include <asm/immap_5445x.h>
#include <asm/m5445x.h>
#define CFG_FEC0_IOBASE (MMAP_FEC0)
#define CFG_FEC1_IOBASE (MMAP_FEC1)
#define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x4000))
#define CFG_MCFRTC_BASE (MMAP_RTC)
/* Timer */
#ifdef CONFIG_MCFTMR
#define CFG_UDELAY_BASE (MMAP_DTMR0)
#define CFG_TMR_BASE (MMAP_DTMR1)
#define CFG_TMRPND_REG (((volatile int0_t *)(CFG_INTR_BASE))->iprh0)
#define CFG_TMRINTR_NO (INT0_HI_DTMR1)
#define CFG_TMRINTR_MASK (INTC_IPRH_INT33)
#define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK)
#define CFG_TMRINTR_PRI (6)
#define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
#endif
#ifdef CONFIG_MCFPIT
#define CFG_UDELAY_BASE (MMAP_PIT0)
#define CFG_PIT_BASE (MMAP_PIT1)
#define CFG_PIT_PRESCALE (6)
#endif
#define CFG_INTR_BASE (MMAP_INTC0)
#define CFG_NUM_IRQS (128)
#ifdef CONFIG_PCI
#define CFG_PCI_BAR0 CFG_SDRAM_BASE
#define CFG_PCI_BAR4 CFG_SDRAM_BASE
#define CFG_PCI_TBATR0 (CFG_SDRAM_BASE)
#define CFG_PCI_TBATR4 (CFG_SDRAM_BASE)
#endif
#endif /* CONFIG_M54455 */
#endif /* __IMMAP_H */

378
include/asm-m68k/immap_5235.h Normal file
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@@ -0,0 +1,378 @@
/*
* MCF5329 Internal Memory Map
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __IMMAP_5235__
#define __IMMAP_5235__
#define MMAP_SCM (CFG_MBAR + 0x00000000)
#define MMAP_SDRAM (CFG_MBAR + 0x00000040)
#define MMAP_FBCS (CFG_MBAR + 0x00000080)
#define MMAP_DMA0 (CFG_MBAR + 0x00000100)
#define MMAP_DMA1 (CFG_MBAR + 0x00000110)
#define MMAP_DMA2 (CFG_MBAR + 0x00000120)
#define MMAP_DMA3 (CFG_MBAR + 0x00000130)
#define MMAP_UART0 (CFG_MBAR + 0x00000200)
#define MMAP_UART1 (CFG_MBAR + 0x00000240)
#define MMAP_UART2 (CFG_MBAR + 0x00000280)
#define MMAP_I2C (CFG_MBAR + 0x00000300)
#define MMAP_QSPI (CFG_MBAR + 0x00000340)
#define MMAP_DTMR0 (CFG_MBAR + 0x00000400)
#define MMAP_DTMR1 (CFG_MBAR + 0x00000440)
#define MMAP_DTMR2 (CFG_MBAR + 0x00000480)
#define MMAP_DTMR3 (CFG_MBAR + 0x000004C0)
#define MMAP_INTC0 (CFG_MBAR + 0x00000C00)
#define MMAP_INTC1 (CFG_MBAR + 0x00000D00)
#define MMAP_INTCACK (CFG_MBAR + 0x00000F00)
#define MMAP_FEC (CFG_MBAR + 0x00001000)
#define MMAP_FECFIFO (CFG_MBAR + 0x00001400)
#define MMAP_GPIO (CFG_MBAR + 0x00100000)
#define MMAP_CCM (CFG_MBAR + 0x00110000)
#define MMAP_PLL (CFG_MBAR + 0x00120000)
#define MMAP_EPORT (CFG_MBAR + 0x00130000)
#define MMAP_WDOG (CFG_MBAR + 0x00140000)
#define MMAP_PIT0 (CFG_MBAR + 0x00150000)
#define MMAP_PIT1 (CFG_MBAR + 0x00160000)
#define MMAP_PIT2 (CFG_MBAR + 0x00170000)
#define MMAP_PIT3 (CFG_MBAR + 0x00180000)
#define MMAP_MDHA (CFG_MBAR + 0x00190000)
#define MMAP_RNG (CFG_MBAR + 0x001A0000)
#define MMAP_SKHA (CFG_MBAR + 0x001B0000)
#define MMAP_CAN1 (CFG_MBAR + 0x001C0000)
#define MMAP_ETPU (CFG_MBAR + 0x001D0000)
#define MMAP_CAN2 (CFG_MBAR + 0x001F0000)
/* System Control Module register */
typedef struct scm_ctrl {
u32 ipsbar; /* 0x00 - MBAR */
u32 res1; /* 0x04 */
u32 rambar; /* 0x08 - RAMBAR */
u32 res2; /* 0x0C */
u8 crsr; /* 0x10 Core Reset Status Register */
u8 cwcr; /* 0x11 Core Watchdog Control Register */
u8 lpicr; /* 0x12 Low-Power Interrupt Control Register */
u8 cwsr; /* 0x13 Core Watchdog Service Register */
u32 dmareqc; /* 0x14 */
u32 res3; /* 0x18 */
u32 mpark; /* 0x1C */
u8 mpr; /* 0x20 */
u8 res4[3]; /* 0x21 - 0x23 */
u8 pacr0; /* 0x24 */
u8 pacr1; /* 0x25 */
u8 pacr2; /* 0x26 */
u8 pacr3; /* 0x27 */
u8 pacr4; /* 0x28 */
u32 res5; /* 0x29 */
u8 pacr5; /* 0x2a */
u8 pacr6; /* 0x2b */
u8 pacr7; /* 0x2c */
u32 res6; /* 0x2d */
u8 pacr8; /* 0x2e */
u32 res7; /* 0x2f */
u8 gpacr; /* 0x30 */
u8 res8[3]; /* 0x31 - 0x33 */
} scm_t;
/* SDRAM controller registers */
typedef struct sdram_ctrl {
u16 dcr; /* 0x00 Control register */
u16 res1[3]; /* 0x02 - 0x07 */
u32 dacr0; /* 0x08 address and control register 0 */
u32 dmr0; /* 0x0C mask register block 0 */
u32 dacr1; /* 0x10 address and control register 1 */
u32 dmr1; /* 0x14 mask register block 1 */
} sdram_t;
/* Flexbus module Chip select registers */
typedef struct fbcs_ctrl {
u16 csar0; /* 0x00 Chip-Select Address Register 0 */
u16 res0;
u32 csmr0; /* 0x04 Chip-Select Mask Register 0 */
u16 res1; /* 0x08 */
u16 cscr0; /* 0x0A Chip-Select Control Register 0 */
u16 csar1; /* 0x0C Chip-Select Address Register 1 */
u16 res2;
u32 csmr1; /* 0x10 Chip-Select Mask Register 1 */
u16 res3; /* 0x14 */
u16 cscr1; /* 0x16 Chip-Select Control Register 1 */
u16 csar2; /* 0x18 Chip-Select Address Register 2 */
u16 res4;
u32 csmr2; /* 0x1C Chip-Select Mask Register 2 */
u16 res5; /* 0x20 */
u16 cscr2; /* 0x22 Chip-Select Control Register 2 */
u16 csar3; /* 0x24 Chip-Select Address Register 3 */
u16 res6;
u32 csmr3; /* 0x28 Chip-Select Mask Register 3 */
u16 res7; /* 0x2C */
u16 cscr3; /* 0x2E Chip-Select Control Register 3 */
u16 csar4; /* 0x30 Chip-Select Address Register 4 */
u16 res8;
u32 csmr4; /* 0x34 Chip-Select Mask Register 4 */
u16 res9; /* 0x38 */
u16 cscr4; /* 0x3A Chip-Select Control Register 4 */
u16 csar5; /* 0x3C Chip-Select Address Register 5 */
u16 res10;
u32 csmr5; /* 0x40 Chip-Select Mask Register 5 */
u16 res11; /* 0x44 */
u16 cscr5; /* 0x46 Chip-Select Control Register 5 */
u16 csar6; /* 0x48 Chip-Select Address Register 5 */
u16 res12;
u32 csmr6; /* 0x4C Chip-Select Mask Register 5 */
u16 res13; /* 0x50 */
u16 cscr6; /* 0x52 Chip-Select Control Register 5 */
u16 csar7; /* 0x54 Chip-Select Address Register 5 */
u16 res14;
u32 csmr7; /* 0x58 Chip-Select Mask Register 5 */
u16 res15; /* 0x5C */
u16 cscr7; /* 0x5E Chip-Select Control Register 5 */
} fbcs_t;
/* QSPI module registers */
typedef struct qspi_ctrl {
u16 qmr; /* Mode register */
u16 res1;
u16 qdlyr; /* Delay register */
u16 res2;
u16 qwr; /* Wrap register */
u16 res3;
u16 qir; /* Interrupt register */
u16 res4;
u16 qar; /* Address register */
u16 res5;
u16 qdr; /* Data register */
u16 res6;
} qspi_t;
/* Interrupt module registers */
typedef struct int0_ctrl {
/* Interrupt Controller 0 */
u32 iprh0; /* 0x00 Pending Register High */
u32 iprl0; /* 0x04 Pending Register Low */
u32 imrh0; /* 0x08 Mask Register High */
u32 imrl0; /* 0x0C Mask Register Low */
u32 frch0; /* 0x10 Force Register High */
u32 frcl0; /* 0x14 Force Register Low */
u8 irlr; /* 0x18 */
u8 iacklpr; /* 0x19 */
u16 res1[19]; /* 0x1a - 0x3c */
u8 icr0[64]; /* 0x40 - 0x7F Control registers */
u32 res3[24]; /* 0x80 - 0xDF */
u8 swiack0; /* 0xE0 Software Interrupt Acknowledge */
u8 res4[3]; /* 0xE1 - 0xE3 */
u8 Lniack0_1; /* 0xE4 Level n interrupt acknowledge resister */
u8 res5[3]; /* 0xE5 - 0xE7 */
u8 Lniack0_2; /* 0xE8 Level n interrupt acknowledge resister */
u8 res6[3]; /* 0xE9 - 0xEB */
u8 Lniack0_3; /* 0xEC Level n interrupt acknowledge resister */
u8 res7[3]; /* 0xED - 0xEF */
u8 Lniack0_4; /* 0xF0 Level n interrupt acknowledge resister */
u8 res8[3]; /* 0xF1 - 0xF3 */
u8 Lniack0_5; /* 0xF4 Level n interrupt acknowledge resister */
u8 res9[3]; /* 0xF5 - 0xF7 */
u8 Lniack0_6; /* 0xF8 Level n interrupt acknowledge resister */
u8 resa[3]; /* 0xF9 - 0xFB */
u8 Lniack0_7; /* 0xFC Level n interrupt acknowledge resister */
u8 resb[3]; /* 0xFD - 0xFF */
} int0_t;
typedef struct int1_ctrl {
/* Interrupt Controller 1 */
u32 iprh1; /* 0x00 Pending Register High */
u32 iprl1; /* 0x04 Pending Register Low */
u32 imrh1; /* 0x08 Mask Register High */
u32 imrl1; /* 0x0C Mask Register Low */
u32 frch1; /* 0x10 Force Register High */
u32 frcl1; /* 0x14 Force Register Low */
u8 irlr; /* 0x18 */
u8 iacklpr; /* 0x19 */
u16 res1[19]; /* 0x1a - 0x3c */
u8 icr1[64]; /* 0x40 - 0x7F */
u32 res4[24]; /* 0x80 - 0xDF */
u8 swiack1; /* 0xE0 Software Interrupt Acknowledge */
u8 res5[3]; /* 0xE1 - 0xE3 */
u8 Lniack1_1; /* 0xE4 Level n interrupt acknowledge resister */
u8 res6[3]; /* 0xE5 - 0xE7 */
u8 Lniack1_2; /* 0xE8 Level n interrupt acknowledge resister */
u8 res7[3]; /* 0xE9 - 0xEB */
u8 Lniack1_3; /* 0xEC Level n interrupt acknowledge resister */
u8 res8[3]; /* 0xED - 0xEF */
u8 Lniack1_4; /* 0xF0 Level n interrupt acknowledge resister */
u8 res9[3]; /* 0xF1 - 0xF3 */
u8 Lniack1_5; /* 0xF4 Level n interrupt acknowledge resister */
u8 resa[3]; /* 0xF5 - 0xF7 */
u8 Lniack1_6; /* 0xF8 Level n interrupt acknowledge resister */
u8 resb[3]; /* 0xF9 - 0xFB */
u8 Lniack1_7; /* 0xFC Level n interrupt acknowledge resister */
u8 resc[3]; /* 0xFD - 0xFF */
} int1_t;
typedef struct intgack_ctrl1 {
/* Global IACK Registers */
u8 swiack; /* 0xE0 Global Software Interrupt Acknowledge */
u8 Lniack[7]; /* 0xE1 - 0xE7 Global Level 0 Interrupt Acknowledge */
} intgack_t;
/* GPIO port registers */
typedef struct gpio_ctrl {
/* Port Output Data Registers */
u8 podr_addr; /* 0x00 */
u8 podr_datah; /* 0x01 */
u8 podr_datal; /* 0x02 */
u8 podr_busctl; /* 0x03 */
u8 podr_bs; /* 0x04 */
u8 podr_cs; /* 0x05 */
u8 podr_sdram; /* 0x06 */
u8 podr_feci2c; /* 0x07 */
u8 podr_uarth; /* 0x08 */
u8 podr_uartl; /* 0x09 */
u8 podr_qspi; /* 0x0A */
u8 podr_timer; /* 0x0B */
u8 podr_etpu; /* 0x0C */
u8 res1[3]; /* 0x0D - 0x0F */
/* Port Data Direction Registers */
u8 pddr_addr; /* 0x10 */
u8 pddr_datah; /* 0x11 */
u8 pddr_datal; /* 0x12 */
u8 pddr_busctl; /* 0x13 */
u8 pddr_bs; /* 0x14 */
u8 pddr_cs; /* 0x15 */
u8 pddr_sdram; /* 0x16 */
u8 pddr_feci2c; /* 0x17 */
u8 pddr_uarth; /* 0x18 */
u8 pddr_uartl; /* 0x19 */
u8 pddr_qspi; /* 0x1A */
u8 pddr_timer; /* 0x1B */
u8 pddr_etpu; /* 0x1C */
u8 res2[3]; /* 0x1D - 0x1F */
/* Port Data Direction Registers */
u8 ppdsdr_addr; /* 0x20 */
u8 ppdsdr_datah; /* 0x21 */
u8 ppdsdr_datal; /* 0x22 */
u8 ppdsdr_busctl; /* 0x23 */
u8 ppdsdr_bs; /* 0x24 */
u8 ppdsdr_cs; /* 0x25 */
u8 ppdsdr_sdram; /* 0x26 */
u8 ppdsdr_feci2c; /* 0x27 */
u8 ppdsdr_uarth; /* 0x28 */
u8 ppdsdr_uartl; /* 0x29 */
u8 ppdsdr_qspi; /* 0x2A */
u8 ppdsdr_timer; /* 0x2B */
u8 ppdsdr_etpu; /* 0x2C */
u8 res3[3]; /* 0x2D - 0x2F */
/* Port Clear Output Data Registers */
u8 pclrr_addr; /* 0x30 */
u8 pclrr_datah; /* 0x31 */
u8 pclrr_datal; /* 0x32 */
u8 pclrr_busctl; /* 0x33 */
u8 pclrr_bs; /* 0x34 */
u8 pclrr_cs; /* 0x35 */
u8 pclrr_sdram; /* 0x36 */
u8 pclrr_feci2c; /* 0x37 */
u8 pclrr_uarth; /* 0x38 */
u8 pclrr_uartl; /* 0x39 */
u8 pclrr_qspi; /* 0x3A */
u8 pclrr_timer; /* 0x3B */
u8 pclrr_etpu; /* 0x3C */
u8 res4[3]; /* 0x3D - 0x3F */
/* Pin Assignment Registers */
u8 par_ad; /* 0x40 */
u8 res5; /* 0x41 */
u16 par_busctl; /* 0x42 */
u8 par_bs; /* 0x44 */
u8 par_cs; /* 0x45 */
u8 par_sdram; /* 0x46 */
u8 par_feci2c; /* 0x47 */
u16 par_uart; /* 0x48 */
u8 par_qspi; /* 0x4A */
u8 res6; /* 0x4B */
u16 par_timer; /* 0x4C */
u8 par_etpu; /* 0x4E */
u8 res7; /* 0x4F */
/* Drive Strength Control Registers */
u8 dscr_eim; /* 0x50 */
u8 dscr_etpu; /* 0x51 */
u8 dscr_feci2c; /* 0x52 */
u8 dscr_uart; /* 0x53 */
u8 dscr_qspi; /* 0x54 */
u8 dscr_timer; /* 0x55 */
u16 res8; /* 0x56 */
} gpio_t;
/*Chip configuration module registers */
typedef struct ccm_ctrl {
u8 rcr; /* 0x01 */
u8 rsr; /* 0x02 */
u16 res1; /* 0x03 */
u16 ccr; /* 0x04 Chip configuration register */
u16 lpcr; /* 0x06 Low-power Control register */
u16 rcon; /* 0x08 Rreset configuration register */
u16 cir; /* 0x0a Chip identification register */
} ccm_t;
/* Clock Module registers */
typedef struct pll_ctrl {
u32 syncr; /* 0x00 synthesizer control register */
u32 synsr; /* 0x04 synthesizer status register */
} pll_t;
/* Watchdog registers */
typedef struct wdog_ctrl {
u16 cr; /* 0x00 Control register */
u16 mr; /* 0x02 Modulus register */
u16 cntr; /* 0x04 Count register */
u16 sr; /* 0x06 Service register */
} wdog_t;
/* FlexCan module registers */
typedef struct can_ctrl {
u32 mcr; /* 0x00 Module Configuration register */
u32 ctrl; /* 0x04 Control register */
u32 timer; /* 0x08 Free Running Timer */
u32 res1; /* 0x0C */
u32 rxgmask; /* 0x10 Rx Global Mask */
u32 rx14mask; /* 0x14 RxBuffer 14 Mask */
u32 rx15mask; /* 0x18 RxBuffer 15 Mask */
u32 errcnt; /* 0x1C Error Counter Register */
u32 errstat; /* 0x20 Error and status Register */
u32 res2; /* 0x24 */
u32 imask; /* 0x28 Interrupt Mask Register */
u32 res3; /* 0x2C */
u32 iflag; /* 0x30 Interrupt Flag Register */
u32 res4[19]; /* 0x34 - 0x7F */
u32 MB0_15[2048]; /* 0x80 Message Buffer 0-15 */
} can_t;
#endif /* __IMMAP_5235__ */

22
include/asm-m68k/immap_5249.h
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@@ -25,19 +25,11 @@
#ifndef __IMMAP_5249__
#define __IMMAP_5249__
/* Timer module registers
*/
typedef struct timer_ctrl {
ushort timer_tmr;
ushort res1;
ushort timer_trr;
ushort res2;
ushort timer_tcap;
ushort res3;
ushort timer_tcn;
ushort res4;
ushort timer_ter;
uchar res5[14];
} timer_t;
#define MMAP_INTC (CFG_MBAR + 0x00000040)
#define MMAP_DTMR0 (CFG_MBAR + 0x00000140)
#define MMAP_DTMR1 (CFG_MBAR + 0x00000180)
#define MMAP_UART0 (CFG_MBAR + 0x000001C0)
#define MMAP_UART1 (CFG_MBAR + 0x00000200)
#define MMAP_QSPI (CFG_MBAR + 0x00000400)
#endif /* __IMMAP_5249__ */
#endif /* __IMMAP_5249__ */

95
include/asm-m68k/immap_5253.h Normal file
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@@ -0,0 +1,95 @@
/*
* MCF5253 Internal Memory Map
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __IMMAP_5249__
#define __IMMAP_5249__
#define MMAP_INTC (CFG_MBAR + 0x00000040)
#define MMAP_DTMR0 (CFG_MBAR + 0x00000140)
#define MMAP_DTMR1 (CFG_MBAR + 0x00000180)
#define MMAP_UART0 (CFG_MBAR + 0x000001C0)
#define MMAP_UART1 (CFG_MBAR + 0x00000200)
#define MMAP_I2C0 (CFG_MBAR + 0x00000280)
#define MMAP_QSPI (CFG_MBAR + 0x00000400)
#define MMAP_CAN0 (CFG_MBAR + 0x00010000)
#define MMAP_CAN1 (CFG_MBAR + 0x00011000)
#define MMAP_I2C1 (CFG_MBAR2 + 0x00000440)
#define MMAP_UART2 (CFG_MBAR2 + 0x00000C00)
/*********************************************************************
* ATA Module (ATAC)
*********************************************************************/
/* Register read/write struct */
typedef struct atac {
/* PIO */
u8 toff; /* 0x00 */
u8 ton; /* 0x01 */
u8 t1; /* 0x02 */
u8 t2w; /* 0x03 */
u8 t2r; /* 0x04 */
u8 ta; /* 0x05 */
u8 trd; /* 0x06 */
u8 t4; /* 0x07 */
u8 t9; /* 0x08 */
/* DMA */
u8 tm; /* 0x09 */
u8 tn; /* 0x0A */
u8 td; /* 0x0B */
u8 tk; /* 0x0C */
u8 tack; /* 0x0D */
u8 tenv; /* 0x0E */
u8 trp; /* 0x0F */
u8 tzah; /* 0x10 */
u8 tmli; /* 0x11 */
u8 tdvh; /* 0x12 */
u8 tdzfs; /* 0x13 */
u8 tdvs; /* 0x14 */
u8 tcvh; /* 0x15 */
u8 tss; /* 0x16 */
u8 tcyc; /* 0x17 */
/* FIFO */
u32 fifo32; /* 0x18 */
u16 fifo16; /* 0x1C */
u8 rsvd0[2];
u8 ffill; /* 0x20 */
u8 rsvd1[3];
/* ATA */
u8 cr; /* 0x24 */
u8 rsvd2[3];
u8 isr; /* 0x28 */
u8 rsvd3[3];
u8 ier; /* 0x2C */
u8 rsvd4[3];
u8 icr; /* 0x30 */
u8 rsvd5[3];
u8 falarm; /* 0x34 */
} atac_t;
#endif /* __IMMAP_5249__ */

136
include/asm-m68k/immap_5271.h
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@@ -26,73 +26,73 @@
#ifndef __IMMAP_5271__
#define __IMMAP_5271__
/* Interrupt module registers
*/
typedef struct int_ctrl {
uint int_icr1;
uint int_icr2;
uint int_icr3;
uint int_icr4;
uint int_isr;
uint int_pitr;
uint int_piwr;
uchar res1[3];
uchar int_pivr;
} intctrl_t;
#define MMAP_SCM (CFG_MBAR + 0x00000000)
#define MMAP_SDRAM (CFG_MBAR + 0x00000040)
#define MMAP_FBCS (CFG_MBAR + 0x00000080)
#define MMAP_DMA0 (CFG_MBAR + 0x00000100)
#define MMAP_DMA1 (CFG_MBAR + 0x00000110)
#define MMAP_DMA2 (CFG_MBAR + 0x00000120)
#define MMAP_DMA3 (CFG_MBAR + 0x00000130)
#define MMAP_UART0 (CFG_MBAR + 0x00000200)
#define MMAP_UART1 (CFG_MBAR + 0x00000240)
#define MMAP_UART2 (CFG_MBAR + 0x00000280)
#define MMAP_I2C (CFG_MBAR + 0x00000300)
#define MMAP_QSPI (CFG_MBAR + 0x00000340)
#define MMAP_DTMR0 (CFG_MBAR + 0x00000400)
#define MMAP_DTMR1 (CFG_MBAR + 0x00000440)
#define MMAP_DTMR2 (CFG_MBAR + 0x00000480)
#define MMAP_DTMR3 (CFG_MBAR + 0x000004C0)
#define MMAP_INTC0 (CFG_MBAR + 0x00000C00)
#define MMAP_INTC1 (CFG_MBAR + 0x00000D00)
#define MMAP_INTCACK (CFG_MBAR + 0x00000F00)
#define MMAP_FEC (CFG_MBAR + 0x00001000)
#define MMAP_FECFIFO (CFG_MBAR + 0x00001400)
#define MMAP_GPIO (CFG_MBAR + 0x00100000)
#define MMAP_CCM (CFG_MBAR + 0x00110000)
#define MMAP_PLL (CFG_MBAR + 0x00120000)
#define MMAP_EPORT (CFG_MBAR + 0x00130000)
#define MMAP_WDOG (CFG_MBAR + 0x00140000)
#define MMAP_PIT0 (CFG_MBAR + 0x00150000)
#define MMAP_PIT1 (CFG_MBAR + 0x00160000)
#define MMAP_PIT2 (CFG_MBAR + 0x00170000)
#define MMAP_PIT3 (CFG_MBAR + 0x00180000)
#define MMAP_MDHA (CFG_MBAR + 0x00190000)
#define MMAP_RNG (CFG_MBAR + 0x001A0000)
#define MMAP_SKHA (CFG_MBAR + 0x001B0000)
#define MMAP_CAN1 (CFG_MBAR + 0x001C0000)
#define MMAP_ETPU (CFG_MBAR + 0x001D0000)
#define MMAP_CAN2 (CFG_MBAR + 0x001F0000)
/* Timer module registers
*/
typedef struct timer_ctrl {
ushort timer_tmr;
ushort res1;
ushort timer_trr;
ushort res2;
ushort timer_tcap;
ushort res3;
ushort timer_tcn;
ushort res4;
ushort timer_ter;
uchar res5[14];
} timer_t;
/* Interrupt module registers */
typedef struct int0_ctrl {
/* Interrupt Controller 0 */
u32 iprh0; /* 0x00 Pending Register High */
u32 iprl0; /* 0x04 Pending Register Low */
u32 imrh0; /* 0x08 Mask Register High */
u32 imrl0; /* 0x0C Mask Register Low */
u32 frch0; /* 0x10 Force Register High */
u32 frcl0; /* 0x14 Force Register Low */
u8 irlr; /* 0x18 */
u8 iacklpr; /* 0x19 */
u16 res1[19]; /* 0x1a - 0x3c */
u8 icr0[64]; /* 0x40 - 0x7F Control registers */
u32 res3[24]; /* 0x80 - 0xDF */
u8 swiack0; /* 0xE0 Software Interrupt Acknowledge */
u8 res4[3]; /* 0xE1 - 0xE3 */
u8 Lniack0_1; /* 0xE4 Level n interrupt acknowledge resister */
u8 res5[3]; /* 0xE5 - 0xE7 */
u8 Lniack0_2; /* 0xE8 Level n interrupt acknowledge resister */
u8 res6[3]; /* 0xE9 - 0xEB */
u8 Lniack0_3; /* 0xEC Level n interrupt acknowledge resister */
u8 res7[3]; /* 0xED - 0xEF */
u8 Lniack0_4; /* 0xF0 Level n interrupt acknowledge resister */
u8 res8[3]; /* 0xF1 - 0xF3 */
u8 Lniack0_5; /* 0xF4 Level n interrupt acknowledge resister */
u8 res9[3]; /* 0xF5 - 0xF7 */
u8 Lniack0_6; /* 0xF8 Level n interrupt acknowledge resister */
u8 resa[3]; /* 0xF9 - 0xFB */
u8 Lniack0_7; /* 0xFC Level n interrupt acknowledge resister */
u8 resb[3]; /* 0xFD - 0xFF */
} int0_t;
/* Fast ethernet controller registers
*/
typedef struct fec {
uint res1;
uint fec_ievent;
uint fec_imask;
uint res2;
uint fec_r_des_active;
uint fec_x_des_active;
uint res3[3];
uint fec_ecntrl;
uint res4[6];
uint fec_mii_data;
uint fec_mii_speed;
uint res5[7];
uint fec_mibc;
uint res6[7];
uint fec_r_cntrl;
uint res7[15];
uint fec_x_cntrl;
uint res8[7];
uint fec_addr_low;
uint fec_addr_high;
uint fec_opd;
uint res9[10];
uint fec_ihash_table_high;
uint fec_ihash_table_low;
uint fec_ghash_table_high;
uint fec_ghash_table_low;
uint res10[7];
uint fec_tfwr;
uint res11;
uint fec_r_bound;
uint fec_r_fstart;
uint res12[11];
uint fec_r_des_start;
uint fec_x_des_start;
uint fec_r_buff_size;
} fec_t;
#endif /* __IMMAP_5271__ */
#endif /* __IMMAP_5271__ */

689
include/asm-m68k/immap_5272.h
View File

@@ -25,423 +25,326 @@
#ifndef __IMMAP_5272__
#define __IMMAP_5272__
/* System configuration registers
*/
typedef struct sys_ctrl {
uint sc_mbar;
ushort sc_scr;
ushort sc_spr;
uint sc_pmr;
char res1[2];
ushort sc_alpr;
uint sc_dir;
char res2[12];
#define MMAP_CFG (CFG_MBAR + 0x00000000)
#define MMAP_INTC (CFG_MBAR + 0x00000020)
#define MMAP_FBCS (CFG_MBAR + 0x00000040)
#define MMAP_GPIO (CFG_MBAR + 0x00000080)
#define MMAP_QSPI (CFG_MBAR + 0x000000A0)
#define MMAP_PWM (CFG_MBAR + 0x000000C0)
#define MMAP_DMA0 (CFG_MBAR + 0x000000E0)
#define MMAP_UART0 (CFG_MBAR + 0x00000100)
#define MMAP_UART1 (CFG_MBAR + 0x00000140)
#define MMAP_SDRAM (CFG_MBAR + 0x00000180)
#define MMAP_TMR0 (CFG_MBAR + 0x00000200)
#define MMAP_TMR1 (CFG_MBAR + 0x00000220)
#define MMAP_TMR2 (CFG_MBAR + 0x00000240)
#define MMAP_TMR3 (CFG_MBAR + 0x00000260)
#define MMAP_WDOG (CFG_MBAR + 0x00000280)
#define MMAP_PLIC (CFG_MBAR + 0x00000300)
#define MMAP_FEC (CFG_MBAR + 0x00000840)
#define MMAP_USB (CFG_MBAR + 0x00001000)
/* System configuration registers */
typedef struct sys_ctrl {
uint sc_mbar;
ushort sc_scr;
ushort sc_spr;
uint sc_pmr;
char res1[2];
ushort sc_alpr;
uint sc_dir;
char res2[12];
} sysctrl_t;
/* Interrupt module registers
*/
/* Interrupt module registers */
typedef struct int_ctrl {
uint int_icr1;
uint int_icr2;
uint int_icr3;
uint int_icr4;
uint int_isr;
uint int_pitr;
uint int_piwr;
uchar res1[3];
uchar int_pivr;
uint int_icr1;
uint int_icr2;
uint int_icr3;
uint int_icr4;
uint int_isr;
uint int_pitr;
uint int_piwr;
uchar res1[3];
uchar int_pivr;
} intctrl_t;
/* Chip select module registers.
*/
typedef struct cs_ctlr {
uint cs_br0;
uint cs_or0;
uint cs_br1;
uint cs_or1;
uint cs_br2;
uint cs_or2;
uint cs_br3;
uint cs_or3;
uint cs_br4;
uint cs_or4;
uint cs_br5;
uint cs_or5;
uint cs_br6;
uint cs_or6;
uint cs_br7;
uint cs_or7;
/* Chip select module registers */
typedef struct cs_ctlr {
uint cs_br0;
uint cs_or0;
uint cs_br1;
uint cs_or1;
uint cs_br2;
uint cs_or2;
uint cs_br3;
uint cs_or3;
uint cs_br4;
uint cs_or4;
uint cs_br5;
uint cs_or5;
uint cs_br6;
uint cs_or6;
uint cs_br7;
uint cs_or7;
} csctrl_t;
/* GPIO port registers
*/
typedef struct gpio_ctrl {
uint gpio_pacnt;
ushort gpio_paddr;
ushort gpio_padat;
uint gpio_pbcnt;
ushort gpio_pbddr;
ushort gpio_pbdat;
uchar res1[4];
ushort gpio_pcddr;
ushort gpio_pcdat;
uint gpio_pdcnt;
uchar res2[4];
/* GPIO port registers */
typedef struct gpio_ctrl {
uint gpio_pacnt;
ushort gpio_paddr;
ushort gpio_padat;
uint gpio_pbcnt;
ushort gpio_pbddr;
ushort gpio_pbdat;
uchar res1[4];
ushort gpio_pcddr;
ushort gpio_pcdat;
uint gpio_pdcnt;
uchar res2[4];
} gpio_t;
/* QSPI module registers
*/
typedef struct qspi_ctrl {
ushort qspi_qmr;
uchar res1[2];
ushort qspi_qdlyr;
uchar res2[2];
ushort qspi_qwr;
uchar res3[2];
ushort qspi_qir;
uchar res4[2];
ushort qspi_qar;
uchar res5[2];
ushort qspi_qdr;
uchar res6[10];
/* QSPI module registers */
typedef struct qspi_ctrl {
ushort qspi_qmr;
uchar res1[2];
ushort qspi_qdlyr;
uchar res2[2];
ushort qspi_qwr;
uchar res3[2];
ushort qspi_qir;
uchar res4[2];
ushort qspi_qar;
uchar res5[2];
ushort qspi_qdr;
uchar res6[10];
} qspi_t;
/* PWM module registers
*/
typedef struct pwm_ctrl {
uchar pwm_pwcr0;
uchar res1[3];
uchar pwm_pwcr1;
uchar res2[3];
uchar pwm_pwcr2;
uchar res3[7];
uchar pwm_pwwd0;
uchar res4[3];
uchar pwm_pwwd1;
uchar res5[3];
uchar pwm_pwwd2;
uchar res6[7];
/* PWM module registers */
typedef struct pwm_ctrl {
uchar pwm_pwcr0;
uchar res1[3];
uchar pwm_pwcr1;
uchar res2[3];
uchar pwm_pwcr2;
uchar res3[7];
uchar pwm_pwwd0;
uchar res4[3];
uchar pwm_pwwd1;
uchar res5[3];
uchar pwm_pwwd2;
uchar res6[7];
} pwm_t;
/* DMA module registers
*/
typedef struct dma_ctrl {
ulong dma_dmr;
uchar res1[2];
ushort dma_dir;
ulong dma_dbcr;
ulong dma_dsar;
ulong dma_ddar;
uchar res2[12];
/* DMA module registers */
typedef struct dma_ctrl {
ulong dma_dmr;
uchar res1[2];
ushort dma_dir;
ulong dma_dbcr;
ulong dma_dsar;
ulong dma_ddar;
uchar res2[12];
} dma_t;
/* UART module registers
*/
typedef struct uart_ctrl {
uchar uart_umr;
uchar res1[3];
uchar uart_usr_ucsr;
uchar res2[3];
uchar uart_ucr;
uchar res3[3];
uchar uart_urb_utb;
uchar res4[3];
uchar uart_uipcr_uacr;
uchar res5[3];
uchar uart_uisr_uimr;
uchar res6[3];
uchar uart_udu;
uchar res7[3];
uchar uart_udl;
uchar res8[3];
uchar uart_uabu;
uchar res9[3];
uchar uart_uabl;
uchar res10[3];
uchar uart_utf;
uchar res11[3];
uchar uart_urf;
uchar res12[3];
uchar uart_ufpd;
uchar res13[3];
uchar uart_uip;
uchar res14[3];
uchar uart_uop1;
uchar res15[3];
uchar uart_uop0;
uchar res16[3];
} uart_t;
/* SDRAM controller registers, offset: 0x180
*/
/* SDRAM controller registers, offset: 0x180 */
typedef struct sdram_ctrl {
uchar res1[2];
ushort sdram_sdcr;
uchar res2[2];
ushort sdram_sdtr;
uchar res3[120];
uchar res1[2];
ushort sdram_sdcr;
uchar res2[2];
ushort sdram_sdtr;
uchar res3[120];
} sdramctrl_t;
/* Timer module registers
*/
typedef struct timer_ctrl {
ushort timer_tmr;
ushort res1;
ushort timer_trr;
ushort res2;
ushort timer_tcap;
ushort res3;
ushort timer_tcn;
ushort res4;
ushort timer_ter;
uchar res5[14];
} timer_t;
/* Watchdog registers
*/
/* Watchdog registers */
typedef struct wdog_ctrl {
ushort wdog_wrrr;
ushort res1;
ushort wdog_wirr;
ushort res2;
ushort wdog_wcr;
ushort res3;
ushort wdog_wer;
uchar res4[114];
ushort wdog_wrrr;
ushort res1;
ushort wdog_wirr;
ushort res2;
ushort wdog_wcr;
ushort res3;
ushort wdog_wer;
uchar res4[114];
} wdog_t;
/* PLIC module registers
*/
/* PLIC module registers */
typedef struct plic_ctrl {
ulong plic_p0b1rr;
ulong plic_p1b1rr;
ulong plic_p2b1rr;
ulong plic_p3b1rr;
ulong plic_p0b2rr;
ulong plic_p1b2rr;
ulong plic_p2b2rr;
ulong plic_p3b2rr;
uchar plic_p0drr;
uchar plic_p1drr;
uchar plic_p2drr;
uchar plic_p3drr;
uchar res1[4];
ulong plic_p0b1tr;
ulong plic_p1b1tr;
ulong plic_p2b1tr;
ulong plic_p3b1tr;
ulong plic_p0b2tr;
ulong plic_p1b2tr;
ulong plic_p2b2tr;
ulong plic_p3b2tr;
uchar plic_p0dtr;
uchar plic_p1dtr;
uchar plic_p2dtr;
uchar plic_p3dtr;
uchar res2[4];
ushort plic_p0cr;
ushort plic_p1cr;
ushort plic_p2cr;
ushort plic_p3cr;
ushort plic_p0icr;
ushort plic_p1icr;
ushort plic_p2icr;
ushort plic_p3icr;
ushort plic_p0gmr;
ushort plic_p1gmr;
ushort plic_p2gmr;
ushort plic_p3gmr;
ushort plic_p0gmt;
ushort plic_p1gmt;
ushort plic_p2gmt;
ushort plic_p3gmt;
uchar res3;
uchar plic_pgmts;
uchar plic_pgmta;
uchar res4;
uchar plic_p0gcir;
uchar plic_p1gcir;
uchar plic_p2gcir;
uchar plic_p3gcir;
uchar plic_p0gcit;
uchar plic_p1gcit;
uchar plic_p2gcit;
uchar plic_p3gcit;
uchar res5[3];
uchar plic_pgcitsr;
uchar res6[3];
uchar plic_pdcsr;
ushort plic_p0psr;
ushort plic_p1psr;
ushort plic_p2psr;
ushort plic_p3psr;
ushort plic_pasr;
uchar res7;
uchar plic_plcr;
ushort res8;
ushort plic_pdrqr;
ushort plic_p0sdr;
ushort plic_p1sdr;
ushort plic_p2sdr;
ushort plic_p3sdr;
ushort res9;
ushort plic_pcsr;
uchar res10[1184];
ulong plic_p0b1rr;
ulong plic_p1b1rr;
ulong plic_p2b1rr;
ulong plic_p3b1rr;
ulong plic_p0b2rr;
ulong plic_p1b2rr;
ulong plic_p2b2rr;
ulong plic_p3b2rr;
uchar plic_p0drr;
uchar plic_p1drr;
uchar plic_p2drr;
uchar plic_p3drr;
uchar res1[4];
ulong plic_p0b1tr;
ulong plic_p1b1tr;
ulong plic_p2b1tr;
ulong plic_p3b1tr;
ulong plic_p0b2tr;
ulong plic_p1b2tr;
ulong plic_p2b2tr;
ulong plic_p3b2tr;
uchar plic_p0dtr;
uchar plic_p1dtr;
uchar plic_p2dtr;
uchar plic_p3dtr;
uchar res2[4];
ushort plic_p0cr;
ushort plic_p1cr;
ushort plic_p2cr;
ushort plic_p3cr;
ushort plic_p0icr;
ushort plic_p1icr;
ushort plic_p2icr;
ushort plic_p3icr;
ushort plic_p0gmr;
ushort plic_p1gmr;
ushort plic_p2gmr;
ushort plic_p3gmr;
ushort plic_p0gmt;
ushort plic_p1gmt;
ushort plic_p2gmt;
ushort plic_p3gmt;
uchar res3;
uchar plic_pgmts;
uchar plic_pgmta;
uchar res4;
uchar plic_p0gcir;
uchar plic_p1gcir;
uchar plic_p2gcir;
uchar plic_p3gcir;
uchar plic_p0gcit;
uchar plic_p1gcit;
uchar plic_p2gcit;
uchar plic_p3gcit;
uchar res5[3];
uchar plic_pgcitsr;
uchar res6[3];
uchar plic_pdcsr;
ushort plic_p0psr;
ushort plic_p1psr;
ushort plic_p2psr;
ushort plic_p3psr;
ushort plic_pasr;
uchar res7;
uchar plic_plcr;
ushort res8;
ushort plic_pdrqr;
ushort plic_p0sdr;
ushort plic_p1sdr;
ushort plic_p2sdr;
ushort plic_p3sdr;
ushort res9;
ushort plic_pcsr;
uchar res10[1184];
} plic_t;
/* Fast ethernet controller registers
*/
typedef struct fec {
uint fec_ecntrl; /* ethernet control register */
uint fec_ievent; /* interrupt event register */
uint fec_imask; /* interrupt mask register */
uint fec_ivec; /* interrupt level and vector status */
uint fec_r_des_active; /* Rx ring updated flag */
uint fec_x_des_active; /* Tx ring updated flag */
uint res3[10]; /* reserved */
uint fec_mii_data; /* MII data register */
uint fec_mii_speed; /* MII speed control register */
uint res4[17]; /* reserved */
uint fec_r_bound; /* end of RAM (read-only) */
uint fec_r_fstart; /* Rx FIFO start address */
uint res5[6]; /* reserved */
uint fec_x_fstart; /* Tx FIFO start address */
uint res7[21]; /* reserved */
uint fec_r_cntrl; /* Rx control register */
uint fec_r_hash; /* Rx hash register */
uint res8[14]; /* reserved */
uint fec_x_cntrl; /* Tx control register */
uint res9[0x9e]; /* reserved */
uint fec_addr_low; /* lower 32 bits of station address */
uint fec_addr_high; /* upper 16 bits of station address */
uint fec_hash_table_high; /* upper 32-bits of hash table */
uint fec_hash_table_low; /* lower 32-bits of hash table */
uint fec_r_des_start; /* beginning of Rx descriptor ring */
uint fec_x_des_start; /* beginning of Tx descriptor ring */
uint fec_r_buff_size; /* Rx buffer size */
uint res2[9]; /* reserved */
uchar fec_fifo[960]; /* fifo RAM */
} fec_t;
/* USB module registers
*/
/* USB module registers */
typedef struct usb {
ushort res1;
ushort usb_fnr;
ushort res2;
ushort usb_fnmr;
ushort res3;
ushort usb_rfmr;
ushort res4;
ushort usb_rfmmr;
uchar res5[3];
uchar usb_far;
ulong usb_asr;
ulong usb_drr1;
ulong usb_drr2;
ushort res6;
ushort usb_specr;
ushort res7;
ushort usb_ep0sr;
ulong usb_iep0cfg;
ulong usb_oep0cfg;
ulong usb_ep1cfg;
ulong usb_ep2cfg;
ulong usb_ep3cfg;
ulong usb_ep4cfg;
ulong usb_ep5cfg;
ulong usb_ep6cfg;
ulong usb_ep7cfg;
ulong usb_ep0ctl;
ushort res8;
ushort usb_ep1ctl;
ushort res9;
ushort usb_ep2ctl;
ushort res10;
ushort usb_ep3ctl;
ushort res11;
ushort usb_ep4ctl;
ushort res12;
ushort usb_ep5ctl;
ushort res13;
ushort usb_ep6ctl;
ushort res14;
ushort usb_ep7ctl;
ulong usb_ep0isr;
ushort res15;
ushort usb_ep1isr;
ushort res16;
ushort usb_ep2isr;
ushort res17;
ushort usb_ep3isr;
ushort res18;
ushort usb_ep4isr;
ushort res19;
ushort usb_ep5isr;
ushort res20;
ushort usb_ep6isr;
ushort res21;
ushort usb_ep7isr;
ulong usb_ep0imr;
ushort res22;
ushort usb_ep1imr;
ushort res23;
ushort usb_ep2imr;
ushort res24;
ushort usb_ep3imr;
ushort res25;
ushort usb_ep4imr;
ushort res26;
ushort usb_ep5imr;
ushort res27;
ushort usb_ep6imr;
ushort res28;
ushort usb_ep7imr;
ulong usb_ep0dr;
ulong usb_ep1dr;
ulong usb_ep2dr;
ulong usb_ep3dr;
ulong usb_ep4dr;
ulong usb_ep5dr;
ulong usb_ep6dr;
ulong usb_ep7dr;
ushort res29;
ushort usb_ep0dpr;
ushort res30;
ushort usb_ep1dpr;
ushort res31;
ushort usb_ep2dpr;
ushort res32;
ushort usb_ep3dpr;
ushort res33;
ushort usb_ep4dpr;
ushort res34;
ushort usb_ep5dpr;
ushort res35;
ushort usb_ep6dpr;
ushort res36;
ushort usb_ep7dpr;
uchar res37[788];
uchar usb_cfgram[1024];
ushort res1;
ushort usb_fnr;
ushort res2;
ushort usb_fnmr;
ushort res3;
ushort usb_rfmr;
ushort res4;
ushort usb_rfmmr;
uchar res5[3];
uchar usb_far;
ulong usb_asr;
ulong usb_drr1;
ulong usb_drr2;
ushort res6;
ushort usb_specr;
ushort res7;
ushort usb_ep0sr;
ulong usb_iep0cfg;
ulong usb_oep0cfg;
ulong usb_ep1cfg;
ulong usb_ep2cfg;
ulong usb_ep3cfg;
ulong usb_ep4cfg;
ulong usb_ep5cfg;
ulong usb_ep6cfg;
ulong usb_ep7cfg;
ulong usb_ep0ctl;
ushort res8;
ushort usb_ep1ctl;
ushort res9;
ushort usb_ep2ctl;
ushort res10;
ushort usb_ep3ctl;
ushort res11;
ushort usb_ep4ctl;
ushort res12;
ushort usb_ep5ctl;
ushort res13;
ushort usb_ep6ctl;
ushort res14;
ushort usb_ep7ctl;
ulong usb_ep0isr;
ushort res15;
ushort usb_ep1isr;
ushort res16;
ushort usb_ep2isr;
ushort res17;
ushort usb_ep3isr;
ushort res18;
ushort usb_ep4isr;
ushort res19;
ushort usb_ep5isr;
ushort res20;
ushort usb_ep6isr;
ushort res21;
ushort usb_ep7isr;
ulong usb_ep0imr;
ushort res22;
ushort usb_ep1imr;
ushort res23;
ushort usb_ep2imr;
ushort res24;
ushort usb_ep3imr;
ushort res25;
ushort usb_ep4imr;
ushort res26;
ushort usb_ep5imr;
ushort res27;
ushort usb_ep6imr;
ushort res28;
ushort usb_ep7imr;
ulong usb_ep0dr;
ulong usb_ep1dr;
ulong usb_ep2dr;
ulong usb_ep3dr;
ulong usb_ep4dr;
ulong usb_ep5dr;
ulong usb_ep6dr;
ulong usb_ep7dr;
ushort res29;
ushort usb_ep0dpr;
ushort res30;
ushort usb_ep1dpr;
ushort res31;
ushort usb_ep2dpr;
ushort res32;
ushort usb_ep3dpr;
ushort res33;
ushort usb_ep4dpr;
ushort res34;
ushort usb_ep5dpr;
ushort res35;
ushort usb_ep6dpr;
ushort res36;
ushort usb_ep7dpr;
uchar res37[788];
uchar usb_cfgram[1024];
} usb_t;
/* Internal memory map.
*/
typedef struct immap {
sysctrl_t sysctrl_reg; /* System configuration registers */
intctrl_t intctrl_reg; /* Interrupt controller registers */
csctrl_t csctrl_reg; /* Chip select controller registers */
gpio_t gpio_reg; /* GPIO controller registers */
qspi_t qspi_reg; /* QSPI controller registers */
pwm_t pwm_reg; /* Pulse width modulation registers */
dma_t dma_reg; /* DMA registers */
uart_t uart_reg[2]; /* UART registers */
sdramctrl_t sdram_reg; /* SDRAM controller registers */
timer_t timer_reg[4]; /* Timer registers */
wdog_t wdog_reg; /* Watchdog registers */
plic_t plic_reg; /* Physical layer interface registers */
fec_t fec_reg; /* Fast ethernet controller registers */
usb_t usb_reg; /* USB controller registers */
} immap_t;
#endif /* __IMMAP_5272__ */
#endif /* __IMMAP_5272__ */

217
include/asm-m68k/immap_5282.h
View File

@@ -25,61 +25,168 @@
#ifndef __IMMAP_5282__
#define __IMMAP_5282__
struct sys_ctrl {
uint ipsbar;
char res1[4];
uint rambar;
char res2[4];
uchar crsr;
uchar cwcr;
uchar lpicr;
uchar cwsr;
uint dmareqc;
char res3[4];
uint mpark;
#define MMAP_SCM (CFG_MBAR + 0x00000000)
#define MMAP_SDRAMC (CFG_MBAR + 0x00000040)
#define MMAP_FBCS (CFG_MBAR + 0x00000080)
#define MMAP_DMA0 (CFG_MBAR + 0x00000100)
#define MMAP_DMA1 (CFG_MBAR + 0x00000140)
#define MMAP_DMA2 (CFG_MBAR + 0x00000180)
#define MMAP_DMA3 (CFG_MBAR + 0x000001C0)
#define MMAP_UART0 (CFG_MBAR + 0x00000200)
#define MMAP_UART1 (CFG_MBAR + 0x00000240)
#define MMAP_UART2 (CFG_MBAR + 0x00000280)
#define MMAP_I2C (CFG_MBAR + 0x00000300)
#define MMAP_QSPI (CFG_MBAR + 0x00000340)
#define MMAP_DTMR0 (CFG_MBAR + 0x00000400)
#define MMAP_DTMR1 (CFG_MBAR + 0x00000440)
#define MMAP_DTMR2 (CFG_MBAR + 0x00000480)
#define MMAP_DTMR3 (CFG_MBAR + 0x000004C0)
#define MMAP_INTC0 (CFG_MBAR + 0x00000C00)
#define MMAP_INTC1 (CFG_MBAR + 0x00000D00)
#define MMAP_INTCACK (CFG_MBAR + 0x00000F00)
#define MMAP_FEC (CFG_MBAR + 0x00001000)
#define MMAP_FECFIFO (CFG_MBAR + 0x00001400)
#define MMAP_GPIO (CFG_MBAR + 0x00100000)
#define MMAP_CCM (CFG_MBAR + 0x00110000)
#define MMAP_PLL (CFG_MBAR + 0x00120000)
#define MMAP_EPORT (CFG_MBAR + 0x00130000)
#define MMAP_WDOG (CFG_MBAR + 0x00140000)
#define MMAP_PIT0 (CFG_MBAR + 0x00150000)
#define MMAP_PIT1 (CFG_MBAR + 0x00160000)
#define MMAP_PIT2 (CFG_MBAR + 0x00170000)
#define MMAP_PIT3 (CFG_MBAR + 0x00180000)
#define MMAP_QADC (CFG_MBAR + 0x00190000)
#define MMAP_GPTMRA (CFG_MBAR + 0x001A0000)
#define MMAP_GPTMRB (CFG_MBAR + 0x001B0000)
#define MMAP_CAN (CFG_MBAR + 0x001C0000)
#define MMAP_CFMC (CFG_MBAR + 0x001D0000)
#define MMAP_CFMMEM (CFG_MBAR + 0x04000000)
/* TODO: finish these */
};
/* System Control Module */
typedef struct scm_ctrl {
u32 ipsbar;
u32 res1;
u32 rambar;
u32 res2;
u8 crsr;
u8 cwcr;
u8 lpicr;
u8 cwsr;
u32 res3;
u8 mpark;
u8 res4[3];
u8 pacr0;
u8 pacr1;
u8 pacr2;
u8 pacr3;
u8 pacr4;
u8 res5;
u8 pacr5;
u8 pacr6;
u8 pacr7;
u8 res6;
u8 pacr8;
u8 res7;
u8 gpacr0;
u8 gpacr1;
u16 res8;
} scm_t;
/* Fast ethernet controller registers
*/
typedef struct fec {
uint res1; /* reserved 1000*/
uint fec_ievent; /* interrupt event register 1004*/ /* EIR */
uint fec_imask; /* interrupt mask register 1008*/ /* EIMR */
uint res2; /* reserved 100c*/
uint fec_r_des_active; /* Rx ring updated flag 1010*/ /* RDAR */
uint fec_x_des_active; /* Tx ring updated flag 1014*/ /* XDAR */
uint res3[3]; /* reserved 1018*/
uint fec_ecntrl; /* ethernet control register 1024*/ /* ECR */
uint res4[6]; /* reserved 1028*/
uint fec_mii_data; /* MII data register 1040*/ /* MDATA */
uint fec_mii_speed; /* MII speed control register 1044*/ /* MSCR */
/*1044*/
uint res5[7]; /* reserved 1048*/
uint fec_mibc; /* MIB Control/Status register 1064*/ /* MIBC */
uint res6[7]; /* reserved 1068*/
uint fec_r_cntrl; /* Rx control register 1084*/ /* RCR */
uint res7[15]; /* reserved 1088*/
uint fec_x_cntrl; /* Tx control register 10C4*/ /* TCR */
uint res8[7]; /* reserved 10C8*/
uint fec_addr_low; /* lower 32 bits of station address */ /* PALR */
uint fec_addr_high; /* upper 16 bits of station address */ /* PAUR */
uint fec_opd; /* opcode + pause duration 10EC*/ /* OPD */
uint res9[10]; /* reserved 10F0*/
uint fec_ihash_table_high; /* upper 32-bits of individual hash */ /* IAUR */
uint fec_ihash_table_low; /* lower 32-bits of individual hash */ /* IALR */
uint fec_ghash_table_high; /* upper 32-bits of group hash */ /* GAUR */
uint fec_ghash_table_low; /* lower 32-bits of group hash */ /* GALR */
uint res10[7]; /* reserved 1128*/
uint fec_tfwr; /* Transmit FIFO watermark 1144*/ /* TFWR */
uint res11; /* reserved 1148*/
uint fec_r_bound; /* FIFO Receive Bound Register = end of */ /* FRBR */
uint fec_r_fstart; /* FIFO Receive FIfo Start Registers = */ /* FRSR */
uint res12[11]; /* reserved 1154*/
uint fec_r_des_start;/* beginning of Rx descriptor ring 1180*/ /* ERDSR */
uint fec_x_des_start;/* beginning of Tx descriptor ring 1184*/ /* ETDSR */
uint fec_r_buff_size;/* Rx buffer size 1188*/ /* EMRBR */
} fec_t;
/* Flexbus module Chip select registers */
typedef struct fbcs_ctrl {
u16 csar0; /* 0x00 Chip-Select Address Register 0 */
u16 res0;
u32 csmr0; /* 0x04 Chip-Select Mask Register 0 */
u16 res1; /* 0x08 */
u16 cscr0; /* 0x0A Chip-Select Control Register 0 */
#endif /* __IMMAP_5282__ */
u16 csar1; /* 0x0C Chip-Select Address Register 1 */
u16 res2;
u32 csmr1; /* 0x10 Chip-Select Mask Register 1 */
u16 res3; /* 0x14 */
u16 cscr1; /* 0x16 Chip-Select Control Register 1 */
u16 csar2; /* 0x18 Chip-Select Address Register 2 */
u16 res4;
u32 csmr2; /* 0x1C Chip-Select Mask Register 2 */
u16 res5; /* 0x20 */
u16 cscr2; /* 0x22 Chip-Select Control Register 2 */
u16 csar3; /* 0x24 Chip-Select Address Register 3 */
u16 res6;
u32 csmr3; /* 0x28 Chip-Select Mask Register 3 */
u16 res7; /* 0x2C */
u16 cscr3; /* 0x2E Chip-Select Control Register 3 */
u16 csar4; /* 0x30 Chip-Select Address Register 4 */
u16 res8;
u32 csmr4; /* 0x34 Chip-Select Mask Register 4 */
u16 res9; /* 0x38 */
u16 cscr4; /* 0x3A Chip-Select Control Register 4 */
u16 csar5; /* 0x3C Chip-Select Address Register 5 */
u16 res10;
u32 csmr5; /* 0x40 Chip-Select Mask Register 5 */
u16 res11; /* 0x44 */
u16 cscr5; /* 0x46 Chip-Select Control Register 5 */
u16 csar6; /* 0x48 Chip-Select Address Register 5 */
u16 res12;
u32 csmr6; /* 0x4C Chip-Select Mask Register 5 */
u16 res13; /* 0x50 */
u16 cscr6; /* 0x52 Chip-Select Control Register 5 */
u16 csar7; /* 0x54 Chip-Select Address Register 5 */
u16 res14;
u32 csmr7; /* 0x58 Chip-Select Mask Register 5 */
u16 res15; /* 0x5C */
u16 cscr7; /* 0x5E Chip-Select Control Register 5 */
} fbcs_t;
/* Interrupt module registers */
typedef struct int0_ctrl {
/* Interrupt Controller 0 */
u32 iprh0; /* 0x00 Pending Register High */
u32 iprl0; /* 0x04 Pending Register Low */
u32 imrh0; /* 0x08 Mask Register High */
u32 imrl0; /* 0x0C Mask Register Low */
u32 frch0; /* 0x10 Force Register High */
u32 frcl0; /* 0x14 Force Register Low */
u8 irlr; /* 0x18 */
u8 iacklpr; /* 0x19 */
u16 res1[19]; /* 0x1a - 0x3c */
u8 icr0[64]; /* 0x40 - 0x7F Control registers */
u32 res3[24]; /* 0x80 - 0xDF */
u8 swiack0; /* 0xE0 Software Interrupt Acknowledge */
u8 res4[3]; /* 0xE1 - 0xE3 */
u8 Lniack0_1; /* 0xE4 Level n interrupt acknowledge resister */
u8 res5[3]; /* 0xE5 - 0xE7 */
u8 Lniack0_2; /* 0xE8 Level n interrupt acknowledge resister */
u8 res6[3]; /* 0xE9 - 0xEB */
u8 Lniack0_3; /* 0xEC Level n interrupt acknowledge resister */
u8 res7[3]; /* 0xED - 0xEF */
u8 Lniack0_4; /* 0xF0 Level n interrupt acknowledge resister */
u8 res8[3]; /* 0xF1 - 0xF3 */
u8 Lniack0_5; /* 0xF4 Level n interrupt acknowledge resister */
u8 res9[3]; /* 0xF5 - 0xF7 */
u8 Lniack0_6; /* 0xF8 Level n interrupt acknowledge resister */
u8 resa[3]; /* 0xF9 - 0xFB */
u8 Lniack0_7; /* 0xFC Level n interrupt acknowledge resister */
u8 resb[3]; /* 0xFD - 0xFF */
} int0_t;
/* Clock Module registers */
typedef struct pll_ctrl {
u16 syncr; /* 0x00 synthesizer control register */
u16 synsr; /* 0x02 synthesizer status register */
} pll_t;
/* Watchdog registers */
typedef struct wdog_ctrl {
ushort wcr;
ushort wmr;
ushort wcntr;
ushort wsr;
} wdog_t;
#endif /* __IMMAP_5282__ */

793
include/asm-m68k/immap_5329.h Normal file
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/*
* MCF5329 Internal Memory Map
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __IMMAP_5329__
#define __IMMAP_5329__
#define MMAP_SCM1 0xEC000000
#define MMAP_MDHA 0xEC080000
#define MMAP_SKHA 0xEC084000
#define MMAP_RNG 0xEC088000
#define MMAP_SCM2 0xFC000000
#define MMAP_XBS 0xFC004000
#define MMAP_FBCS 0xFC008000
#define MMAP_CAN 0xFC020000
#define MMAP_FEC 0xFC030000
#define MMAP_SCM3 0xFC040000
#define MMAP_EDMA 0xFC044000
#define MMAP_TCD 0xFC045000
#define MMAP_INTC0 0xFC048000
#define MMAP_INTC1 0xFC04C000
#define MMAP_INTCACK 0xFC054000
#define MMAP_I2C 0xFC058000
#define MMAP_QSPI 0xFC05C000
#define MMAP_UART0 0xFC060000
#define MMAP_UART1 0xFC064000
#define MMAP_UART2 0xFC068000
#define MMAP_DTMR0 0xFC070000
#define MMAP_DTMR1 0xFC074000
#define MMAP_DTMR2 0xFC078000
#define MMAP_DTMR3 0xFC07C000
#define MMAP_PIT0 0xFC080000
#define MMAP_PIT1 0xFC084000
#define MMAP_PIT2 0xFC088000
#define MMAP_PIT3 0xFC08C000
#define MMAP_PWM 0xFC090000
#define MMAP_EPORT 0xFC094000
#define MMAP_WDOG 0xFC098000
#define MMAP_CCM 0xFC0A0000
#define MMAP_GPIO 0xFC0A4000
#define MMAP_RTC 0xFC0A8000
#define MMAP_LCDC 0xFC0AC000
#define MMAP_USBOTG 0xFC0B0000
#define MMAP_USBH 0xFC0B4000
#define MMAP_SDRAM 0xFC0B8000
#define MMAP_SSI 0xFC0BC000
#define MMAP_PLL 0xFC0C0000
/* System control module registers */
typedef struct scm1_ctrl {
u32 mpr0; /* 0x00 Master Privilege Register 0 */
u32 res1[15]; /* 0x04 - 0x3F */
u32 pacrh; /* 0x40 Peripheral Access Control Register H */
u32 res2[3]; /* 0x44 - 0x53 */
u32 bmt0; /*0x54 Bus Monitor Timeout 0 */
} scm1_t;
/* Message Digest Hardware Accelerator */
typedef struct mdha_ctrl {
u32 mdmr; /* 0x00 MDHA Mode Register */
u32 mdcr; /* 0x04 Control register */
u32 mdcmr; /* 0x08 Command Register */
u32 mdsr; /* 0x0C Status Register */
u32 mdisr; /* 0x10 Interrupt Status Register */
u32 mdimr; /* 0x14 Interrupt Mask Register */
u32 mddsr; /* 0x1C Data Size Register */
u32 mdin; /* 0x20 Input FIFO */
u32 res1[3]; /* 0x24 - 0x2F */
u32 mdao; /* 0x30 Message Digest AO Register */
u32 mdbo; /* 0x34 Message Digest BO Register */
u32 mdco; /* 0x38 Message Digest CO Register */
u32 mddo; /* 0x3C Message Digest DO Register */
u32 mdeo; /* 0x40 Message Digest EO Register */
u32 mdmds; /* 0x44 Message Data Size Register */
u32 res[10]; /* 0x48 - 0x6F */
u32 mda1; /* 0x70 Message Digest A1 Register */
u32 mdb1; /* 0x74 Message Digest B1 Register */
u32 mdc1; /* 0x78 Message Digest C1 Register */
u32 mdd1; /* 0x7C Message Digest D1 Register */
u32 mde1; /* 0x80 Message Digest E1 Register */
} mdha_t;
/* Symmetric Key Hardware Accelerator */
typedef struct skha_ctrl {
u32 mr; /* 0x00 Mode Register */
u32 cr; /* 0x04 Control Register */
u32 cmr; /* 0x08 Command Register */
u32 sr; /* 0x0C Status Register */
u32 esr; /* 0x10 Error Status Register */
u32 emr; /* 0x14 Error Status Mask Register) */
u32 ksr; /* 0x18 Key Size Register */
u32 dsr; /* 0x1C Data Size Register */
u32 in; /* 0x20 Input FIFO */
u32 out; /* 0x24 Output FIFO */
u32 res1[2]; /* 0x28 - 0x2F */
u32 kdr1; /* 0x30 Key Data Register 1 */
u32 kdr2; /* 0x34 Key Data Register 2 */
u32 kdr3; /* 0x38 Key Data Register 3 */
u32 kdr4; /* 0x3C Key Data Register 4 */
u32 kdr5; /* 0x40 Key Data Register 5 */
u32 kdr6; /* 0x44 Key Data Register 6 */
u32 res2[10]; /* 0x48 - 0x6F */
u32 c1; /* 0x70 Context 1 */
u32 c2; /* 0x74 Context 2 */
u32 c3; /* 0x78 Context 3 */
u32 c4; /* 0x7C Context 4 */
u32 c5; /* 0x80 Context 5 */
u32 c6; /* 0x84 Context 6 */
u32 c7; /* 0x88 Context 7 */
u32 c8; /* 0x8C Context 8 */
u32 c9; /* 0x90 Context 9 */
u32 c10; /* 0x94 Context 10 */
u32 c11; /* 0x98 Context 11 */
} skha_t;
/* Random Number Generator */
typedef struct rng_ctrl {
u32 rngcr; /* 0x00 RNG Control Register */
u32 rngsr; /* 0x04 RNG Status Register */
u32 rnger; /* 0x08 RNG Entropy Register */
u32 rngout; /* 0x0C RNG Output FIFO */
} rng_t;
/* System control module registers 2 */
typedef struct scm2_ctrl {
u32 mpr1; /* 0x00 Master Privilege Register */
u32 res1[7]; /* 0x04 - 0x1F */
u32 pacra; /* 0x20 Peripheral Access Control Register A */
u32 pacrb; /* 0x24 Peripheral Access Control Register B */
u32 pacrc; /* 0x28 Peripheral Access Control Register C */
u32 pacrd; /* 0x2C Peripheral Access Control Register D */
u32 res2[4]; /* 0x30 - 0x3F */
u32 pacre; /* 0x40 Peripheral Access Control Register E */
u32 pacrf; /* 0x44 Peripheral Access Control Register F */
u32 pacrg; /* 0x48 Peripheral Access Control Register G */
u32 res3[2]; /* 0x4C - 0x53 */
u32 bmt1; /* 0x54 Bus Monitor Timeout 1 */
} scm2_t;
/* Cross-Bar Switch Module */
typedef struct xbs_ctrl {
u32 prs1; /* 0x100 Priority Register Slave 1 */
u32 res1[3]; /* 0x104 - 0F */
u32 crs1; /* 0x110 Control Register Slave 1 */
u32 res2[187]; /* 0x114 - 0x3FF */
u32 prs4; /* 0x400 Priority Register Slave 4 */
u32 res3[3]; /* 0x404 - 0F */
u32 crs4; /* 0x410 Control Register Slave 4 */
u32 res4[123]; /* 0x414 - 0x5FF */
u32 prs6; /* 0x600 Priority Register Slave 6 */
u32 res5[3]; /* 0x604 - 0F */
u32 crs6; /* 0x610 Control Register Slave 6 */
u32 res6[59]; /* 0x614 - 0x6FF */
u32 prs7; /* 0x700 Priority Register Slave 7 */
u32 res7[3]; /* 0x704 - 0F */
u32 crs7; /* 0x710 Control Register Slave 7 */
} xbs_t;
/* Flexbus module Chip select registers */
typedef struct fbcs_ctrl {
u16 csar0; /* 0x00 Chip-Select Address Register 0 */
u16 res0;
u32 csmr0; /* 0x04 Chip-Select Mask Register 0 */
u32 cscr0; /* 0x08 Chip-Select Control Register 0 */
u16 csar1; /* 0x0C Chip-Select Address Register 1 */
u16 res1;
u32 csmr1; /* 0x10 Chip-Select Mask Register 1 */
u32 cscr1; /* 0x14 Chip-Select Control Register 1 */
u16 csar2; /* 0x18 Chip-Select Address Register 2 */
u16 res2;
u32 csmr2; /* 0x1C Chip-Select Mask Register 2 */
u32 cscr2; /* 0x20 Chip-Select Control Register 2 */
u16 csar3; /* 0x24 Chip-Select Address Register 3 */
u16 res3;
u32 csmr3; /* 0x28 Chip-Select Mask Register 3 */
u32 cscr3; /* 0x2C Chip-Select Control Register 3 */
u16 csar4; /* 0x30 Chip-Select Address Register 4 */
u16 res4;
u32 csmr4; /* 0x34 Chip-Select Mask Register 4 */
u32 cscr4; /* 0x38 Chip-Select Control Register 4 */
u16 csar5; /* 0x3C Chip-Select Address Register 5 */
u16 res5;
u32 csmr5; /* 0x40 Chip-Select Mask Register 5 */
u32 cscr5; /* 0x44 Chip-Select Control Register 5 */
} fbcs_t;
/* FlexCan module registers */
typedef struct can_ctrl {
u32 mcr; /* 0x00 Module Configuration register */
u32 ctrl; /* 0x04 Control register */
u32 timer; /* 0x08 Free Running Timer */
u32 res1; /* 0x0C */
u32 rxgmask; /* 0x10 Rx Global Mask */
u32 rx14mask; /* 0x14 RxBuffer 14 Mask */
u32 rx15mask; /* 0x18 RxBuffer 15 Mask */
u32 errcnt; /* 0x1C Error Counter Register */
u32 errstat; /* 0x20 Error and status Register */
u32 res2; /* 0x24 */
u32 imask; /* 0x28 Interrupt Mask Register */
u32 res3; /* 0x2C */
u32 iflag; /* 0x30 Interrupt Flag Register */
u32 res4[19]; /* 0x34 - 0x7F */
u32 MB0_15[2048]; /* 0x80 Message Buffer 0-15 */
} can_t;
/* System Control Module register 3 */
typedef struct scm3_ctrl {
u8 res1[19]; /* 0x00 - 0x12 */
u8 wcr; /* 0x13 wakeup control register */
u16 res2; /* 0x14 - 0x15 */
u16 cwcr; /* 0x16 Core Watchdog Control Register */
u8 res3[3]; /* 0x18 - 0x1A */
u8 cwsr; /* 0x1B Core Watchdog Service Register */
u8 res4[2]; /* 0x1C - 0x1D */
u8 scmisr; /* 0x1F Interrupt Status Register */
u32 res5; /* 0x20 */
u32 bcr; /* 0x24 Burst Configuration Register */
u32 res6[18]; /* 0x28 - 0x6F */
u32 cfadr; /* 0x70 Core Fault Address Register */
u8 res7[4]; /* 0x71 - 0x74 */
u8 cfier; /* 0x75 Core Fault Interrupt Enable Register */
u8 cfloc; /* 0x76 Core Fault Location Register */
u8 cfatr; /* 0x77 Core Fault Attributes Register */
u32 res8; /* 0x78 */
u32 cfdtr; /* 0x7C Core Fault Data Register */
} scm3_t;
/* eDMA module registers */
typedef struct edma_ctrl {
u32 cr; /* 0x00 Control Register */
u32 es; /* 0x04 Error Status Register */
u16 res1[3]; /* 0x08 - 0x0D */
u16 erq; /* 0x0E Enable Request Register */
u16 res2[3]; /* 0x10 - 0x15 */
u16 eei; /* 0x16 Enable Error Interrupt Request */
u8 serq; /* 0x18 Set Enable Request */
u8 cerq; /* 0x19 Clear Enable Request */
u8 seei; /* 0x1A Set Enable Error Interrupt Request */
u8 ceei; /* 0x1B Clear Enable Error Interrupt Request */
u8 cint; /* 0x1C Clear Interrupt Enable Register */
u8 cerr; /* 0x1D Clear Error Register */
u8 ssrt; /* 0x1E Set START Bit Register */
u8 cdne; /* 0x1F Clear DONE Status Bit Register */
u16 res3[3]; /* 0x20 - 0x25 */
u16 intr; /* 0x26 Interrupt Request Register */
u16 res4[3]; /* 0x28 - 0x2D */
u16 err; /* 0x2E Error Register */
u32 res5[52]; /* 0x30 - 0xFF */
u8 dchpri0; /* 0x100 Channel 0 Priority Register */
u8 dchpri1; /* 0x101 Channel 1 Priority Register */
u8 dchpri2; /* 0x102 Channel 2 Priority Register */
u8 dchpri3; /* 0x103 Channel 3 Priority Register */
u8 dchpri4; /* 0x104 Channel 4 Priority Register */
u8 dchpri5; /* 0x105 Channel 5 Priority Register */
u8 dchpri6; /* 0x106 Channel 6 Priority Register */
u8 dchpri7; /* 0x107 Channel 7 Priority Register */
u8 dchpri8; /* 0x108 Channel 8 Priority Register */
u8 dchpri9; /* 0x109 Channel 9 Priority Register */
u8 dchpri10; /* 0x110 Channel 10 Priority Register */
u8 dchpri11; /* 0x111 Channel 11 Priority Register */
u8 dchpri12; /* 0x112 Channel 12 Priority Register */
u8 dchpri13; /* 0x113 Channel 13 Priority Register */
u8 dchpri14; /* 0x114 Channel 14 Priority Register */
u8 dchpri15; /* 0x115 Channel 15 Priority Register */
} edma_t;
/* TCD - eDMA*/
typedef struct tcd_ctrl {
u32 saddr; /* 0x00 Source Address */
u16 attr; /* 0x04 Transfer Attributes */
u16 soff; /* 0x06 Signed Source Address Offset */
u32 nbytes; /* 0x08 Minor Byte Count */
u32 slast; /* 0x0C Last Source Address Adjustment */
u32 daddr; /* 0x10 Destination address */
u16 citer; /* 0x14 Current Minor Loop Link, Major Loop Count */
u16 doff; /* 0x16 Signed Destination Address Offset */
u32 dlast_sga; /* 0x18 Last Destination Address Adjustment/Scatter Gather Address */
u16 biter; /* 0x1C Beginning Minor Loop Link, Major Loop Count */
u16 csr; /* 0x1E Control and Status */
} tcd_st;
typedef struct tcd_multiple {
tcd_st tcd[16];
} tcd_t;
/* Interrupt module registers */
typedef struct int0_ctrl {
/* Interrupt Controller 0 */
u32 iprh0; /* 0x00 Pending Register High */
u32 iprl0; /* 0x04 Pending Register Low */
u32 imrh0; /* 0x08 Mask Register High */
u32 imrl0; /* 0x0C Mask Register Low */
u32 frch0; /* 0x10 Force Register High */
u32 frcl0; /* 0x14 Force Register Low */
u16 res1; /* 0x18 - 0x19 */
u16 icfg0; /* 0x1A Configuration Register */
u8 simr0; /* 0x1C Set Interrupt Mask */
u8 cimr0; /* 0x1D Clear Interrupt Mask */
u8 clmask0; /* 0x1E Current Level Mask */
u8 slmask; /* 0x1F Saved Level Mask */
u32 res2[8]; /* 0x20 - 0x3F */
u8 icr0[64]; /* 0x40 - 0x7F Control registers */
u32 res3[24]; /* 0x80 - 0xDF */
u8 swiack0; /* 0xE0 Software Interrupt Acknowledge */
u8 res4[3]; /* 0xE1 - 0xE3 */
u8 Lniack0_1; /* 0xE4 Level n interrupt acknowledge resister */
u8 res5[3]; /* 0xE5 - 0xE7 */
u8 Lniack0_2; /* 0xE8 Level n interrupt acknowledge resister */
u8 res6[3]; /* 0xE9 - 0xEB */
u8 Lniack0_3; /* 0xEC Level n interrupt acknowledge resister */
u8 res7[3]; /* 0xED - 0xEF */
u8 Lniack0_4; /* 0xF0 Level n interrupt acknowledge resister */
u8 res8[3]; /* 0xF1 - 0xF3 */
u8 Lniack0_5; /* 0xF4 Level n interrupt acknowledge resister */
u8 res9[3]; /* 0xF5 - 0xF7 */
u8 Lniack0_6; /* 0xF8 Level n interrupt acknowledge resister */
u8 resa[3]; /* 0xF9 - 0xFB */
u8 Lniack0_7; /* 0xFC Level n interrupt acknowledge resister */
u8 resb[3]; /* 0xFD - 0xFF */
} int0_t;
typedef struct int1_ctrl {
/* Interrupt Controller 1 */
u32 iprh1; /* 0x00 Pending Register High */
u32 iprl1; /* 0x04 Pending Register Low */
u32 imrh1; /* 0x08 Mask Register High */
u32 imrl1; /* 0x0C Mask Register Low */
u32 frch1; /* 0x10 Force Register High */
u32 frcl1; /* 0x14 Force Register Low */
u16 res1; /* 0x18 */
u16 icfg1; /* 0x1A Configuration Register */
u8 simr1; /* 0x1C Set Interrupt Mask */
u8 cimr1; /* 0x1D Clear Interrupt Mask */
u16 res2; /* 0x1E - 0x1F */
u32 res3[8]; /* 0x20 - 0x3F */
u8 icr1[64]; /* 0x40 - 0x7F */
u32 res4[24]; /* 0x80 - 0xDF */
u8 swiack1; /* 0xE0 Software Interrupt Acknowledge */
u8 res5[3]; /* 0xE1 - 0xE3 */
u8 Lniack1_1; /* 0xE4 Level n interrupt acknowledge resister */
u8 res6[3]; /* 0xE5 - 0xE7 */
u8 Lniack1_2; /* 0xE8 Level n interrupt acknowledge resister */
u8 res7[3]; /* 0xE9 - 0xEB */
u8 Lniack1_3; /* 0xEC Level n interrupt acknowledge resister */
u8 res8[3]; /* 0xED - 0xEF */
u8 Lniack1_4; /* 0xF0 Level n interrupt acknowledge resister */
u8 res9[3]; /* 0xF1 - 0xF3 */
u8 Lniack1_5; /* 0xF4 Level n interrupt acknowledge resister */
u8 resa[3]; /* 0xF5 - 0xF7 */
u8 Lniack1_6; /* 0xF8 Level n interrupt acknowledge resister */
u8 resb[3]; /* 0xF9 - 0xFB */
u8 Lniack1_7; /* 0xFC Level n interrupt acknowledge resister */
u8 resc[3]; /* 0xFD - 0xFF */
} int1_t;
typedef struct intgack_ctrl1 {
/* Global IACK Registers */
u8 swiack; /* 0xE0 Global Software Interrupt Acknowledge */
u8 Lniack[7]; /* 0xE1 - 0xE7 Global Level 0 Interrupt Acknowledge */
} intgack_t;
/*I2C module registers */
typedef struct i2c_ctrl {
u8 adr; /* 0x00 address register */
u8 res1[3]; /* 0x01 - 0x03 */
u8 fdr; /* 0x04 frequency divider register */
u8 res2[3]; /* 0x05 - 0x07 */
u8 cr; /* 0x08 control register */
u8 res3[3]; /* 0x09 - 0x0B */
u8 sr; /* 0x0C status register */
u8 res4[3]; /* 0x0D - 0x0F */
u8 dr; /* 0x10 data register */
u8 res5[3]; /* 0x11 - 0x13 */
} i2c_t;
/* QSPI module registers */
typedef struct qspi_ctrl {
u16 qmr; /* Mode register */
u16 res1;
u16 qdlyr; /* Delay register */
u16 res2;
u16 qwr; /* Wrap register */
u16 res3;
u16 qir; /* Interrupt register */
u16 res4;
u16 qar; /* Address register */
u16 res5;
u16 qdr; /* Data register */
u16 res6;
} qspi_t;
/* PWM module registers */
typedef struct pwm_ctrl {
u8 en; /* 0x00 PWM Enable Register */
u8 pol; /* 0x01 Polarity Register */
u8 clk; /* 0x02 Clock Select Register */
u8 prclk; /* 0x03 Prescale Clock Select Register */
u8 cae; /* 0x04 Center Align Enable Register */
u8 ctl; /* 0x05 Control Register */
u8 res1[2]; /* 0x06 - 0x07 */
u8 scla; /* 0x08 Scale A register */
u8 sclb; /* 0x09 Scale B register */
u8 res2[2]; /* 0x0A - 0x0B */
u8 cnt0; /* 0x0C Channel 0 Counter register */
u8 cnt1; /* 0x0D Channel 1 Counter register */
u8 cnt2; /* 0x0E Channel 2 Counter register */
u8 cnt3; /* 0x0F Channel 3 Counter register */
u8 cnt4; /* 0x10 Channel 4 Counter register */
u8 cnt5; /* 0x11 Channel 5 Counter register */
u8 cnt6; /* 0x12 Channel 6 Counter register */
u8 cnt7; /* 0x13 Channel 7 Counter register */
u8 per0; /* 0x14 Channel 0 Period register */
u8 per1; /* 0x15 Channel 1 Period register */
u8 per2; /* 0x16 Channel 2 Period register */
u8 per3; /* 0x17 Channel 3 Period register */
u8 per4; /* 0x18 Channel 4 Period register */
u8 per5; /* 0x19 Channel 5 Period register */
u8 per6; /* 0x1A Channel 6 Period register */
u8 per7; /* 0x1B Channel 7 Period register */
u8 dty0; /* 0x1C Channel 0 Duty register */
u8 dty1; /* 0x1D Channel 1 Duty register */
u8 dty2; /* 0x1E Channel 2 Duty register */
u8 dty3; /* 0x1F Channel 3 Duty register */
u8 dty4; /* 0x20 Channel 4 Duty register */
u8 dty5; /* 0x21 Channel 5 Duty register */
u8 dty6; /* 0x22 Channel 6 Duty register */
u8 dty7; /* 0x23 Channel 7 Duty register */
u8 sdn; /* 0x24 Shutdown register */
u8 res3[3]; /* 0x25 - 0x27 */
} pwm_t;
/* Edge Port module registers */
typedef struct eport_ctrl {
u16 par; /* 0x00 Pin Assignment Register */
u8 ddar; /* 0x02 Data Direction Register */
u8 ier; /* 0x03 Interrupt Enable Register */
u8 dr; /* 0x04 Data Register */
u8 pdr; /* 0x05 Pin Data Register */
u8 fr; /* 0x06 Flag_Register */
u8 res1;
} eport_t;
/* Watchdog registers */
typedef struct wdog_ctrl {
u16 cr; /* 0x00 Control register */
u16 mr; /* 0x02 Modulus register */
u16 cntr; /* 0x04 Count register */
u16 sr; /* 0x06 Service register */
} wdog_t;
/*Chip configuration module registers */
typedef struct ccm_ctrl {
u8 rstctrl; /* 0x00 Reset Controller register */
u8 rststat; /* 0x01 Reset Status register */
u16 res1; /* 0x02 - 0x03 */
u16 ccr; /* 0x04 Chip configuration register */
u16 res2; /* 0x06 */
u16 rcon; /* 0x08 Rreset configuration register */
u16 cir; /* 0x0A Chip identification register */
u32 res3; /* 0x0C */
u16 misccr; /* 0x10 Miscellaneous control register */
u16 cdr; /* 0x12 Clock divider register */
u16 uhcsr; /* 0x14 USB Host controller status register */
u16 uocsr; /* 0x16 USB On-the-Go Controller Status Register */
} ccm_t;
/* GPIO port registers */
typedef struct gpio_ctrl {
/* Port Output Data Registers */
u8 podr_fech; /* 0x00 */
u8 podr_fecl; /* 0x01 */
u8 podr_ssi; /* 0x02 */
u8 podr_busctl; /* 0x03 */
u8 podr_be; /* 0x04 */
u8 podr_cs; /* 0x05 */
u8 podr_pwm; /* 0x06 */
u8 podr_feci2c; /* 0x07 */
u8 res1; /* 0x08 */
u8 podr_uart; /* 0x09 */
u8 podr_qspi; /* 0x0A */
u8 podr_timer; /* 0x0B */
u8 res2; /* 0x0C */
u8 podr_lcddatah; /* 0x0D */
u8 podr_lcddatam; /* 0x0E */
u8 podr_lcddatal; /* 0x0F */
u8 podr_lcdctlh; /* 0x10 */
u8 podr_lcdctll; /* 0x11 */
/* Port Data Direction Registers */
u16 res3; /* 0x12 - 0x13 */
u8 pddr_fech; /* 0x14 */
u8 pddr_fecl; /* 0x15 */
u8 pddr_ssi; /* 0x16 */
u8 pddr_busctl; /* 0x17 */
u8 pddr_be; /* 0x18 */
u8 pddr_cs; /* 0x19 */
u8 pddr_pwm; /* 0x1A */
u8 pddr_feci2c; /* 0x1B */
u8 res4; /* 0x1C */
u8 pddr_uart; /* 0x1D */
u8 pddr_qspi; /* 0x1E */
u8 pddr_timer; /* 0x1F */
u8 res5; /* 0x20 */
u8 pddr_lcddatah; /* 0x21 */
u8 pddr_lcddatam; /* 0x22 */
u8 pddr_lcddatal; /* 0x23 */
u8 pddr_lcdctlh; /* 0x24 */
u8 pddr_lcdctll; /* 0x25 */
u16 res6; /* 0x26 - 0x27 */
/* Port Data Direction Registers */
u8 ppd_fech; /* 0x28 */
u8 ppd_fecl; /* 0x29 */
u8 ppd_ssi; /* 0x2A */
u8 ppd_busctl; /* 0x2B */
u8 ppd_be; /* 0x2C */
u8 ppd_cs; /* 0x2D */
u8 ppd_pwm; /* 0x2E */
u8 ppd_feci2c; /* 0x2F */
u8 res7; /* 0x30 */
u8 ppd_uart; /* 0x31 */
u8 ppd_qspi; /* 0x32 */
u8 ppd_timer; /* 0x33 */
u8 res8; /* 0x34 */
u8 ppd_lcddatah; /* 0x35 */
u8 ppd_lcddatam; /* 0x36 */
u8 ppd_lcddatal; /* 0x37 */
u8 ppd_lcdctlh; /* 0x38 */
u8 ppd_lcdctll; /* 0x39 */
u16 res9; /* 0x3A - 0x3B */
/* Port Clear Output Data Registers */
u8 pclrr_fech; /* 0x3C */
u8 pclrr_fecl; /* 0x3D */
u8 pclrr_ssi; /* 0x3E */
u8 pclrr_busctl; /* 0x3F */
u8 pclrr_be; /* 0x40 */
u8 pclrr_cs; /* 0x41 */
u8 pclrr_pwm; /* 0x42 */
u8 pclrr_feci2c; /* 0x43 */
u8 res10; /* 0x44 */
u8 pclrr_uart; /* 0x45 */
u8 pclrr_qspi; /* 0x46 */
u8 pclrr_timer; /* 0x47 */
u8 res11; /* 0x48 */
u8 pclrr_lcddatah; /* 0x49 */
u8 pclrr_lcddatam; /* 0x4A */
u8 pclrr_lcddatal; /* 0x4B */
u8 pclrr_lcdctlh; /* 0x4C */
u8 pclrr_lcdctll; /* 0x4D */
u16 res12; /* 0x4E - 0x4F */
/* Pin Assignment Registers */
u8 par_fec; /* 0x50 */
u8 par_pwm; /* 0x51 */
u8 par_busctl; /* 0x52 */
u8 par_feci2c; /* 0x53 */
u8 par_be; /* 0x54 */
u8 par_cs; /* 0x55 */
u16 par_ssi; /* 0x56 */
u16 par_uart; /* 0x58 */
u16 par_qspi; /* 0x5A */
u8 par_timer; /* 0x5C */
u8 par_lcddata; /* 0x5D */
u16 par_lcdctl; /* 0x5E */
u16 par_irq; /* 0x60 */
u16 res16; /* 0x62 - 0x63 */
/* Mode Select Control Registers */
u8 mscr_flexbus; /* 0x64 */
u8 mscr_sdram; /* 0x65 */
u16 res17; /* 0x66 - 0x67 */
/* Drive Strength Control Registers */
u8 dscr_i2c; /* 0x68 */
u8 dscr_pwm; /* 0x69 */
u8 dscr_fec; /* 0x6A */
u8 dscr_uart; /* 0x6B */
u8 dscr_qspi; /* 0x6C */
u8 dscr_timer; /* 0x6D */
u8 dscr_ssi; /* 0x6E */
u8 dscr_lcd; /* 0x6F */
u8 dscr_debug; /* 0x70 */
u8 dscr_clkrst; /* 0x71 */
u8 dscr_irq; /* 0x72 */
} gpio_t;
/* LCD module registers */
typedef struct lcd_ctrl {
u32 ssar; /* 0x00 Screen Start Address Register */
u32 sr; /* 0x04 LCD Size Register */
u32 vpw; /* 0x08 Virtual Page Width Register */
u32 cpr; /* 0x0C Cursor Position Register */
u32 cwhb; /* 0x10 Cursor Width Height and Blink Register */
u32 ccmr; /* 0x14 Color Cursor Mapping Register */
u32 pcr; /* 0x18 Panel Configuration Register */
u32 hcr; /* 0x1C Horizontal Configuration Register */
u32 vcr; /* 0x20 Vertical Configuration Register */
u32 por; /* 0x24 Panning Offset Register */
u32 scr; /* 0x28 Sharp Configuration Register */
u32 pccr; /* 0x2C PWM Contrast Control Register */
u32 dcr; /* 0x30 DMA Control Register */
u32 rmcr; /* 0x34 Refresh Mode Control Register */
u32 icr; /* 0x38 Refresh Mode Control Register */
u32 ier; /* 0x3C Interrupt Enable Register */
u32 isr; /* 0x40 Interrupt Status Register */
u32 res[4];
u32 gwsar; /* 0x50 Graphic Window Start Address Register */
u32 gwsr; /* 0x54 Graphic Window Size Register */
u32 gwvpw; /* 0x58 Graphic Window Virtual Page Width Register */
u32 gwpor; /* 0x5C Graphic Window Panning Offset Register */
u32 gwpr; /* 0x60 Graphic Window Position Register */
u32 gwcr; /* 0x64 Graphic Window Control Register */
u32 gwdcr; /* 0x68 Graphic Window DMA Control Register */
} lcd_t;
typedef struct lcdbg_ctrl {
u32 bglut[255];
} lcdbg_t;
typedef struct lcdgw_ctrl {
u32 gwlut[255];
} lcdgw_t;
/* USB OTG module registers */
typedef struct usb_otg {
u32 id; /* 0x000 Identification Register */
u32 hwgeneral; /* 0x004 General HW Parameters */
u32 hwhost; /* 0x008 Host HW Parameters */
u32 hwdev; /* 0x00C Device HW parameters */
u32 hwtxbuf; /* 0x010 TX Buffer HW Parameters */
u32 hwrxbuf; /* 0x014 RX Buffer HW Parameters */
u32 res1[58]; /* 0x18 - 0xFF */
u8 caplength; /* 0x100 Capability Register Length */
u8 res2; /* 0x101 */
u16 hciver; /* 0x102 Host Interface Version Number */
u32 hcsparams; /* 0x104 Host Structural Parameters */
u32 hccparams; /* 0x108 Host Capability Parameters */
u32 res3[5]; /* 0x10C - 0x11F */
u16 dciver; /* 0x120 Device Interface Version Number */
u16 res4; /* 0x122 */
u32 dccparams; /* 0x124 Device Capability Parameters */
u32 res5[6]; /* 0x128 - 0x13F */
u32 cmd; /* 0x140 USB Command */
u32 sts; /* 0x144 USB Status */
u32 intr; /* 0x148 USB Interrupt Enable */
u32 frindex; /* 0x14C USB Frame Index */
u32 res6; /* 0x150 */
u32 prd_dev; /* 0x154 Periodic Frame List Base or Device Address */
u32 aync_ep; /* 0x158 Current Asynchronous List or Address at Endpoint List Address */
u32 ttctrl; /* 0x15C Host TT Asynchronous Buffer Control */
u32 burstsize; /* 0x160 Master Interface Data Burst Size */
u32 txfill; /* 0x164 Host Transmit FIFO Tuning Control */
u32 res7[6]; /* 0x168 - 0x17F */
u32 cfgflag; /* 0x180 Configure Flag Register */
u32 portsc1; /* 0x184 Port Status/Control */
u32 res8[7]; /* 0x188 - 0x1A3 */
u32 otgsc; /* 0x1A4 On The Go Status and Control */
u32 mode; /* 0x1A8 USB mode register */
u32 eptsetstat; /* 0x1AC Endpoint Setup status */
u32 eptprime; /* 0x1B0 Endpoint initialization */
u32 eptflush; /* 0x1B4 Endpoint de-initialize */
u32 eptstat; /* 0x1B8 Endpoint status */
u32 eptcomplete; /* 0x1BC Endpoint Complete */
u32 eptctrl0; /* 0x1C0 Endpoint control 0 */
u32 eptctrl1; /* 0x1C4 Endpoint control 1 */
u32 eptctrl2; /* 0x1C8 Endpoint control 2 */
u32 eptctrl3; /* 0x1CC Endpoint control 3 */
} usbotg_t;
/* USB Host module registers */
typedef struct usb_host {
u32 id; /* 0x000 Identification Register */
u32 hwgeneral; /* 0x004 General HW Parameters */
u32 hwhost; /* 0x008 Host HW Parameters */
u32 res1; /* 0x0C */
u32 hwtxbuf; /* 0x010 TX Buffer HW Parameters */
u32 hwrxbuf; /* 0x014 RX Buffer HW Parameters */
u32 res2[58]; /* 0x18 - 0xFF */
/* Host Controller Capability Register */
u8 caplength; /* 0x100 Capability Register Length */
u8 res3; /* 0x101 */
u16 hciver; /* 0x102 Host Interface Version Number */
u32 hcsparams; /* 0x104 Host Structural Parameters */
u32 hccparams; /* 0x108 Host Capability Parameters */
u32 res4[13]; /* 0x10C - 0x13F */
/* Host Controller Operational Register */
u32 cmd; /* 0x140 USB Command */
u32 sts; /* 0x144 USB Status */
u32 intr; /* 0x148 USB Interrupt Enable */
u32 frindex; /* 0x14C USB Frame Index */
u32 res5; /* 0x150 (ctrl segment register in EHCI spec) */
u32 prdlst; /* 0x154 Periodic Frame List Base Address */
u32 aynclst; /* 0x158 Current Asynchronous List Address */
u32 ttctrl; /* 0x15C Host TT Asynchronous Buffer Control (non-ehci) */
u32 burstsize; /* 0x160 Master Interface Data Burst Size (non-ehci) */
u32 txfill; /* 0x164 Host Transmit FIFO Tuning Control (non-ehci) */
u32 res6[6]; /* 0x168 - 0x17F */
u32 cfgflag; /* 0x180 Configure Flag Register */
u32 portsc1; /* 0x184 Port Status/Control */
u32 res7[8]; /* 0x188 - 0x1A7 */
/* non-ehci registers */
u32 mode; /* 0x1A8 USB mode register */
u32 eptsetstat; /* 0x1AC Endpoint Setup status */
u32 eptprime; /* 0x1B0 Endpoint initialization */
u32 eptflush; /* 0x1B4 Endpoint de-initialize */
u32 eptstat; /* 0x1B8 Endpoint status */
u32 eptcomplete; /* 0x1BC Endpoint Complete */
u32 eptctrl0; /* 0x1C0 Endpoint control 0 */
u32 eptctrl1; /* 0x1C4 Endpoint control 1 */
u32 eptctrl2; /* 0x1C8 Endpoint control 2 */
u32 eptctrl3; /* 0x1CC Endpoint control 3 */
} usbhost_t;
/* SDRAM controller registers */
typedef struct sdram_ctrl {
u32 mode; /* 0x00 Mode/Extended Mode register */
u32 ctrl; /* 0x04 Control register */
u32 cfg1; /* 0x08 Configuration register 1 */
u32 cfg2; /* 0x0C Configuration register 2 */
u32 res1[64]; /* 0x10 - 0x10F */
u32 cs0; /* 0x110 Chip Select 0 Configuration */
u32 cs1; /* 0x114 Chip Select 1 Configuration */
} sdram_t;
/* Synchronous serial interface */
typedef struct ssi_ctrl {
u32 tx0; /* 0x00 Transmit Data Register 0 */
u32 tx1; /* 0x04 Transmit Data Register 1 */
u32 rx0; /* 0x08 Receive Data Register 0 */
u32 rx1; /* 0x0C Receive Data Register 1 */
u32 cr; /* 0x10 Control Register */
u32 isr; /* 0x14 Interrupt Status Register */
u32 ier; /* 0x18 Interrupt Enable Register */
u32 tcr; /* 0x1C Transmit Configuration Register */
u32 rcr; /* 0x20 Receive Configuration Register */
u32 ccr; /* 0x24 Clock Control Register */
u32 res1; /* 0x28 */
u32 fcsr; /* 0x2C FIFO Control/Status Register */
u32 res2[2]; /* 0x30 - 0x37 */
u32 acr; /* 0x38 AC97 Control Register */
u32 acadd; /* 0x3C AC97 Command Address Register */
u32 acdat; /* 0x40 AC97 Command Data Register */
u32 atag; /* 0x44 AC97 Tag Register */
u32 tmask; /* 0x48 Transmit Time Slot Mask Register */
u32 rmask; /* 0x4C Receive Time Slot Mask Register */
} ssi_t;
/* Clock Module registers */
typedef struct pll_ctrl {
u8 podr; /* 0x00 Output Divider Register */
u8 res1[3];
u8 pcr; /* 0x04 Control Register */
u8 res2[3];
u8 pmdr; /* 0x08 Modulation Divider Register */
u8 res3[3];
u8 pfdr; /* 0x0C Feedback Divider Register */
u8 res4[3];
} pll_t;
#endif /* __IMMAP_5329__ */

937
include/asm-m68k/immap_5445x.h Normal file
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/*
* MCF5445x Internal Memory Map
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __IMMAP_5445X__
#define __IMMAP_5445X__
/* Module Base Addresses */
#define MMAP_SCM1 0xFC000000
#define MMAP_XBS 0xFC004000
#define MMAP_FBCS 0xFC008000
#define MMAP_FEC0 0xFC030000
#define MMAP_FEC1 0xFC034000
#define MMAP_RTC 0xFC03C000
#define MMAP_EDMA 0xFC044000
#define MMAP_INTC0 0xFC048000
#define MMAP_INTC1 0xFC04C000
#define MMAP_IACK 0xFC054000
#define MMAP_I2C 0xFC058000
#define MMAP_DSPI 0xFC05C000
#define MMAP_UART0 0xFC060000
#define MMAP_UART1 0xFC064000
#define MMAP_UART2 0xFC068000
#define MMAP_DTMR0 0xFC070000
#define MMAP_DTMR1 0xFC074000
#define MMAP_DTMR2 0xFC078000
#define MMAP_DTMR3 0xFC07C000
#define MMAP_PIT0 0xFC080000
#define MMAP_PIT1 0xFC084000
#define MMAP_PIT2 0xFC088000
#define MMAP_PIT3 0xFC08C000
#define MMAP_EPORT 0xFC094000
#define MMAP_WTM 0xFC098000
#define MMAP_SBF 0xFC0A0000
#define MMAP_RCM 0xFC0A0000
#define MMAP_CCM 0xFC0A0000
#define MMAP_GPIO 0xFC0A4000
#define MMAP_PCI 0xFC0A8000
#define MMAP_PCIARB 0xFC0AC000
#define MMAP_RNG 0xFC0B4000
#define MMAP_SDRAM 0xFC0B8000
#define MMAP_SSI 0xFC0BC000
#define MMAP_PLL 0xFC0C4000
#define MMAP_ATA 0x90000000
/*********************************************************************
* ATA
*********************************************************************/
typedef struct atac {
/* PIO */
u8 toff; /* 0x00 */
u8 ton; /* 0x01 */
u8 t1; /* 0x02 */
u8 t2w; /* 0x03 */
u8 t2r; /* 0x04 */
u8 ta; /* 0x05 */
u8 trd; /* 0x06 */
u8 t4; /* 0x07 */
u8 t9; /* 0x08 */
/* DMA */
u8 tm; /* 0x09 */
u8 tn; /* 0x0A */
u8 td; /* 0x0B */
u8 tk; /* 0x0C */
u8 tack; /* 0x0D */
u8 tenv; /* 0x0E */
u8 trp; /* 0x0F */
u8 tzah; /* 0x10 */
u8 tmli; /* 0x11 */
u8 tdvh; /* 0x12 */
u8 tdzfs; /* 0x13 */
u8 tdvs; /* 0x14 */
u8 tcvh; /* 0x15 */
u8 tss; /* 0x16 */
u8 tcyc; /* 0x17 */
/* FIFO */
u32 fifo32; /* 0x18 */
u16 fifo16; /* 0x1C */
u8 rsvd0[2];
u8 ffill; /* 0x20 */
u8 rsvd1[3];
/* ATA */
u8 cr; /* 0x24 */
u8 rsvd2[3];
u8 isr; /* 0x28 */
u8 rsvd3[3];
u8 ier; /* 0x2C */
u8 rsvd4[3];
u8 icr; /* 0x30 */
u8 rsvd5[3];
u8 falarm; /* 0x34 */
u8 rsvd6[106];
} atac_t;
/*********************************************************************
* Cross-bar switch (XBS)
*********************************************************************/
typedef struct xbs {
u8 resv0[0x100];
u32 prs1; /* XBS Priority Register */
u8 resv1[0xC];
u32 crs1; /* XBS Control Register */
u8 resv2[0xEC];
u32 prs2; /* XBS Priority Register */
u8 resv3[0xC];
u32 crs2; /* XBS Control Register */
u8 resv4[0xEC];
u32 prs3; /* XBS Priority Register */
u8 resv5[0xC];
u32 crs3; /* XBS Control Register */
u8 resv6[0xEC];
u32 prs4; /* XBS Priority Register */
u8 resv7[0xC];
u32 crs4; /* XBS Control Register */
u8 resv8[0xEC];
u32 prs5; /* XBS Priority Register */
u8 resv9[0xC];
u32 crs5; /* XBS Control Register */
u8 resv10[0xEC];
u32 prs6; /* XBS Priority Register */
u8 resv11[0xC];
u32 crs6; /* XBS Control Register */
u8 resv12[0xEC];
u32 prs7; /* XBS Priority Register */
u8 resv13[0xC];
u32 crs7; /* XBS Control Register */
} xbs_t;
/*********************************************************************
* FlexBus Chip Selects (FBCS)
*********************************************************************/
typedef struct fbcs {
u32 csar0; /* Chip-select Address Register */
u32 csmr0; /* Chip-select Mask Register */
u32 cscr0; /* Chip-select Control Register */
u32 csar1; /* Chip-select Address Register */
u32 csmr1; /* Chip-select Mask Register */
u32 cscr1; /* Chip-select Control Register */
u32 csar2; /* Chip-select Address Register */
u32 csmr2; /* Chip-select Mask Register */
u32 cscr2; /* Chip-select Control Register */
u32 csar3; /* Chip-select Address Register */
u32 csmr3; /* Chip-select Mask Register */
u32 cscr3; /* Chip-select Control Register */
} fbcs_t;
/*********************************************************************
* Enhanced DMA (EDMA)
*********************************************************************/
typedef struct edma {
u32 cr;
u32 es;
u8 resv0[0x6];
u16 erq;
u8 resv1[0x6];
u16 eei;
u8 serq;
u8 cerq;
u8 seei;
u8 ceei;
u8 cint;
u8 cerr;
u8 ssrt;
u8 cdne;
u8 resv2[0x6];
u16 intr;
u8 resv3[0x6];
u16 err;
u8 resv4[0xD0];
u8 dchpri0;
u8 dchpri1;
u8 dchpri2;
u8 dchpri3;
u8 dchpri4;
u8 dchpri5;
u8 dchpri6;
u8 dchpri7;
u8 dchpri8;
u8 dchpri9;
u8 dchpri10;
u8 dchpri11;
u8 dchpri12;
u8 dchpri13;
u8 dchpri14;
u8 dchpri15;
u8 resv5[0xEF0];
u32 tcd0_saddr;
u16 tcd0_attr;
u16 tcd0_soff;
u32 tcd0_nbytes;
u32 tcd0_slast;
u32 tcd0_daddr;
union {
u16 tcd0_citer_elink;
u16 tcd0_citer;
};
u16 tcd0_doff;
u32 tcd0_dlast_sga;
union {
u16 tcd0_biter_elink;
u16 tcd0_biter;
};
u16 tcd0_csr;
u32 tcd1_saddr;
u16 tcd1_attr;
u16 tcd1_soff;
u32 tcd1_nbytes;
u32 tcd1_slast;
u32 tcd1_daddr;
union {
u16 tcd1_citer_elink;
u16 tcd1_citer;
};
u16 tcd1_doff;
u32 tcd1_dlast_sga;
union {
u16 tcd1_biter;
u16 tcd1_biter_elink;
};
u16 tcd1_csr;
u32 tcd2_saddr;
u16 tcd2_attr;
u16 tcd2_soff;
u32 tcd2_nbytes;
u32 tcd2_slast;
u32 tcd2_daddr;
union {
u16 tcd2_citer;
u16 tcd2_citer_elink;
};
u16 tcd2_doff;
u32 tcd2_dlast_sga;
union {
u16 tcd2_biter_elink;
u16 tcd2_biter;
};
u16 tcd2_csr;
u32 tcd3_saddr;
u16 tcd3_attr;
u16 tcd3_soff;
u32 tcd3_nbytes;
u32 tcd3_slast;
u32 tcd3_daddr;
union {
u16 tcd3_citer;
u16 tcd3_citer_elink;
};
u16 tcd3_doff;
u32 tcd3_dlast_sga;
union {
u16 tcd3_biter_elink;
u16 tcd3_biter;
};
u16 tcd3_csr;
u32 tcd4_saddr;
u16 tcd4_attr;
u16 tcd4_soff;
u32 tcd4_nbytes;
u32 tcd4_slast;
u32 tcd4_daddr;
union {
u16 tcd4_citer;
u16 tcd4_citer_elink;
};
u16 tcd4_doff;
u32 tcd4_dlast_sga;
union {
u16 tcd4_biter;
u16 tcd4_biter_elink;
};
u16 tcd4_csr;
u32 tcd5_saddr;
u16 tcd5_attr;
u16 tcd5_soff;
u32 tcd5_nbytes;
u32 tcd5_slast;
u32 tcd5_daddr;
union {
u16 tcd5_citer;
u16 tcd5_citer_elink;
};
u16 tcd5_doff;
u32 tcd5_dlast_sga;
union {
u16 tcd5_biter_elink;
u16 tcd5_biter;
};
u16 tcd5_csr;
u32 tcd6_saddr;
u16 tcd6_attr;
u16 tcd6_soff;
u32 tcd6_nbytes;
u32 tcd6_slast;
u32 tcd6_daddr;
union {
u16 tcd6_citer;
u16 tcd6_citer_elink;
};
u16 tcd6_doff;
u32 tcd6_dlast_sga;
union {
u16 tcd6_biter_elink;
u16 tcd6_biter;
};
u16 tcd6_csr;
u32 tcd7_saddr;
u16 tcd7_attr;
u16 tcd7_soff;
u32 tcd7_nbytes;
u32 tcd7_slast;
u32 tcd7_daddr;
union {
u16 tcd7_citer;
u16 tcd7_citer_elink;
};
u16 tcd7_doff;
u32 tcd7_dlast_sga;
union {
u16 tcd7_biter_elink;
u16 tcd7_biter;
};
u16 tcd7_csr;
u32 tcd8_saddr;
u16 tcd8_attr;
u16 tcd8_soff;
u32 tcd8_nbytes;
u32 tcd8_slast;
u32 tcd8_daddr;
union {
u16 tcd8_citer;
u16 tcd8_citer_elink;
};
u16 tcd8_doff;
u32 tcd8_dlast_sga;
union {
u16 tcd8_biter_elink;
u16 tcd8_biter;
};
u16 tcd8_csr;
u32 tcd9_saddr;
u16 tcd9_attr;
u16 tcd9_soff;
u32 tcd9_nbytes;
u32 tcd9_slast;
u32 tcd9_daddr;
union {
u16 tcd9_citer_elink;
u16 tcd9_citer;
};
u16 tcd9_doff;
u32 tcd9_dlast_sga;
union {
u16 tcd9_biter_elink;
u16 tcd9_biter;
};
u16 tcd9_csr;
u32 tcd10_saddr;
u16 tcd10_attr;
u16 tcd10_soff;
u32 tcd10_nbytes;
u32 tcd10_slast;
u32 tcd10_daddr;
union {
u16 tcd10_citer_elink;
u16 tcd10_citer;
};
u16 tcd10_doff;
u32 tcd10_dlast_sga;
union {
u16 tcd10_biter;
u16 tcd10_biter_elink;
};
u16 tcd10_csr;
u32 tcd11_saddr;
u16 tcd11_attr;
u16 tcd11_soff;
u32 tcd11_nbytes;
u32 tcd11_slast;
u32 tcd11_daddr;
union {
u16 tcd11_citer;
u16 tcd11_citer_elink;
};
u16 tcd11_doff;
u32 tcd11_dlast_sga;
union {
u16 tcd11_biter;
u16 tcd11_biter_elink;
};
u16 tcd11_csr;
u32 tcd12_saddr;
u16 tcd12_attr;
u16 tcd12_soff;
u32 tcd12_nbytes;
u32 tcd12_slast;
u32 tcd12_daddr;
union {
u16 tcd12_citer;
u16 tcd12_citer_elink;
};
u16 tcd12_doff;
u32 tcd12_dlast_sga;
union {
u16 tcd12_biter;
u16 tcd12_biter_elink;
};
u16 tcd12_csr;
u32 tcd13_saddr;
u16 tcd13_attr;
u16 tcd13_soff;
u32 tcd13_nbytes;
u32 tcd13_slast;
u32 tcd13_daddr;
union {
u16 tcd13_citer_elink;
u16 tcd13_citer;
};
u16 tcd13_doff;
u32 tcd13_dlast_sga;
union {
u16 tcd13_biter_elink;
u16 tcd13_biter;
};
u16 tcd13_csr;
u32 tcd14_saddr;
u16 tcd14_attr;
u16 tcd14_soff;
u32 tcd14_nbytes;
u32 tcd14_slast;
u32 tcd14_daddr;
union {
u16 tcd14_citer;
u16 tcd14_citer_elink;
};
u16 tcd14_doff;
u32 tcd14_dlast_sga;
union {
u16 tcd14_biter_elink;
u16 tcd14_biter;
};
u16 tcd14_csr;
u32 tcd15_saddr;
u16 tcd15_attr;
u16 tcd15_soff;
u32 tcd15_nbytes;
u32 tcd15_slast;
u32 tcd15_daddr;
union {
u16 tcd15_citer_elink;
u16 tcd15_citer;
};
u16 tcd15_doff;
u32 tcd15_dlast_sga;
union {
u16 tcd15_biter;
u16 tcd15_biter_elink;
};
u16 tcd15_csr;
} edma_t;
/*********************************************************************
* Interrupt Controller (INTC)
*********************************************************************/
typedef struct int0_ctrl {
u32 iprh0; /* 0x00 Pending Register High */
u32 iprl0; /* 0x04 Pending Register Low */
u32 imrh0; /* 0x08 Mask Register High */
u32 imrl0; /* 0x0C Mask Register Low */
u32 frch0; /* 0x10 Force Register High */
u32 frcl0; /* 0x14 Force Register Low */
u16 res1; /* 0x18 - 0x19 */
u16 icfg0; /* 0x1A Configuration Register */
u8 simr0; /* 0x1C Set Interrupt Mask */
u8 cimr0; /* 0x1D Clear Interrupt Mask */
u8 clmask0; /* 0x1E Current Level Mask */
u8 slmask; /* 0x1F Saved Level Mask */
u32 res2[8]; /* 0x20 - 0x3F */
u8 icr0[64]; /* 0x40 - 0x7F Control registers */
u32 res3[24]; /* 0x80 - 0xDF */
u8 swiack0; /* 0xE0 Software Interrupt Acknowledge */
u8 res4[3]; /* 0xE1 - 0xE3 */
u8 Lniack0_1; /* 0xE4 Level n interrupt acknowledge resister */
u8 res5[3]; /* 0xE5 - 0xE7 */
u8 Lniack0_2; /* 0xE8 Level n interrupt acknowledge resister */
u8 res6[3]; /* 0xE9 - 0xEB */
u8 Lniack0_3; /* 0xEC Level n interrupt acknowledge resister */
u8 res7[3]; /* 0xED - 0xEF */
u8 Lniack0_4; /* 0xF0 Level n interrupt acknowledge resister */
u8 res8[3]; /* 0xF1 - 0xF3 */
u8 Lniack0_5; /* 0xF4 Level n interrupt acknowledge resister */
u8 res9[3]; /* 0xF5 - 0xF7 */
u8 Lniack0_6; /* 0xF8 Level n interrupt acknowledge resister */
u8 resa[3]; /* 0xF9 - 0xFB */
u8 Lniack0_7; /* 0xFC Level n interrupt acknowledge resister */
u8 resb[3]; /* 0xFD - 0xFF */
} int0_t;
typedef struct int1_ctrl {
/* Interrupt Controller 1 */
u32 iprh1; /* 0x00 Pending Register High */
u32 iprl1; /* 0x04 Pending Register Low */
u32 imrh1; /* 0x08 Mask Register High */
u32 imrl1; /* 0x0C Mask Register Low */
u32 frch1; /* 0x10 Force Register High */
u32 frcl1; /* 0x14 Force Register Low */
u16 res1; /* 0x18 */
u16 icfg1; /* 0x1A Configuration Register */
u8 simr1; /* 0x1C Set Interrupt Mask */
u8 cimr1; /* 0x1D Clear Interrupt Mask */
u16 res2; /* 0x1E - 0x1F */
u32 res3[8]; /* 0x20 - 0x3F */
u8 icr1[64]; /* 0x40 - 0x7F */
u32 res4[24]; /* 0x80 - 0xDF */
u8 swiack1; /* 0xE0 Software Interrupt Acknowledge */
u8 res5[3]; /* 0xE1 - 0xE3 */
u8 Lniack1_1; /* 0xE4 Level n interrupt acknowledge resister */
u8 res6[3]; /* 0xE5 - 0xE7 */
u8 Lniack1_2; /* 0xE8 Level n interrupt acknowledge resister */
u8 res7[3]; /* 0xE9 - 0xEB */
u8 Lniack1_3; /* 0xEC Level n interrupt acknowledge resister */
u8 res8[3]; /* 0xED - 0xEF */
u8 Lniack1_4; /* 0xF0 Level n interrupt acknowledge resister */
u8 res9[3]; /* 0xF1 - 0xF3 */
u8 Lniack1_5; /* 0xF4 Level n interrupt acknowledge resister */
u8 resa[3]; /* 0xF5 - 0xF7 */
u8 Lniack1_6; /* 0xF8 Level n interrupt acknowledge resister */
u8 resb[3]; /* 0xF9 - 0xFB */
u8 Lniack1_7; /* 0xFC Level n interrupt acknowledge resister */
u8 resc[3]; /* 0xFD - 0xFF */
} int1_t;
/*********************************************************************
* Global Interrupt Acknowledge (IACK)
*********************************************************************/
typedef struct iack {
u8 resv0[0xE0];
u8 gswiack;
u8 resv1[0x3];
u8 gl1iack;
u8 resv2[0x3];
u8 gl2iack;
u8 resv3[0x3];
u8 gl3iack;
u8 resv4[0x3];
u8 gl4iack;
u8 resv5[0x3];
u8 gl5iack;
u8 resv6[0x3];
u8 gl6iack;
u8 resv7[0x3];
u8 gl7iack;
} iack_t;
/*********************************************************************
* DMA Serial Peripheral Interface (DSPI)
*********************************************************************/
typedef struct dspi {
u32 dmcr;
u8 resv0[0x4];
u32 dtcr;
u32 dctar0;
u32 dctar1;
u32 dctar2;
u32 dctar3;
u32 dctar4;
u32 dctar5;
u32 dctar6;
u32 dctar7;
u32 dsr;
u32 dirsr;
u32 dtfr;
u32 drfr;
u32 dtfdr0;
u32 dtfdr1;
u32 dtfdr2;
u32 dtfdr3;
u8 resv1[0x30];
u32 drfdr0;
u32 drfdr1;
u32 drfdr2;
u32 drfdr3;
} dspi_t;
/*********************************************************************
* Edge Port Module (EPORT)
*********************************************************************/
typedef struct eport {
u16 eppar;
u8 epddr;
u8 epier;
u8 epdr;
u8 eppdr;
u8 epfr;
} eport_t;
/*********************************************************************
* Watchdog Timer Modules (WTM)
*********************************************************************/
typedef struct wtm {
u16 wcr;
u16 wmr;
u16 wcntr;
u16 wsr;
} wtm_t;
/*********************************************************************
* Serial Boot Facility (SBF)
*********************************************************************/
typedef struct sbf {
u8 resv0[0x18];
u16 sbfsr; /* Serial Boot Facility Status Register */
u8 resv1[0x6];
u16 sbfcr; /* Serial Boot Facility Control Register */
} sbf_t;
/*********************************************************************
* Reset Controller Module (RCM)
*********************************************************************/
typedef struct rcm {
u8 rcr;
u8 rsr;
} rcm_t;
/*********************************************************************
* Chip Configuration Module (CCM)
*********************************************************************/
typedef struct ccm {
u8 ccm_resv0[0x4];
u16 ccr; /* Chip Configuration Register (256 TEPBGA, Read-only) */
u8 resv1[0x2];
u16 rcon; /* Reset Configuration (256 TEPBGA, Read-only) */
u16 cir; /* Chip Identification Register (Read-only) */
u8 resv2[0x4];
u16 misccr; /* Miscellaneous Control Register */
u16 cdr; /* Clock Divider Register */
u16 uocsr; /* USB On-the-Go Controller Status Register */
} ccm_t;
/*********************************************************************
* General Purpose I/O Module (GPIO)
*********************************************************************/
typedef struct gpio {
u8 podr_fec0h; /* FEC0 High Port Output Data Register */
u8 podr_fec0l; /* FEC0 Low Port Output Data Register */
u8 podr_ssi; /* SSI Port Output Data Register */
u8 podr_fbctl; /* Flexbus Control Port Output Data Register */
u8 podr_be; /* Flexbus Byte Enable Port Output Data Register */
u8 podr_cs; /* Flexbus Chip-Select Port Output Data Register */
u8 podr_dma; /* DMA Port Output Data Register */
u8 podr_feci2c; /* FEC1 / I2C Port Output Data Register */
u8 resv0[0x1];
u8 podr_uart; /* UART Port Output Data Register */
u8 podr_dspi; /* DSPI Port Output Data Register */
u8 podr_timer; /* Timer Port Output Data Register */
u8 podr_pci; /* PCI Port Output Data Register */
u8 podr_usb; /* USB Port Output Data Register */
u8 podr_atah; /* ATA High Port Output Data Register */
u8 podr_atal; /* ATA Low Port Output Data Register */
u8 podr_fec1h; /* FEC1 High Port Output Data Register */
u8 podr_fec1l; /* FEC1 Low Port Output Data Register */
u8 resv1[0x2];
u8 podr_fbadh; /* Flexbus AD High Port Output Data Register */
u8 podr_fbadmh; /* Flexbus AD Med-High Port Output Data Register */
u8 podr_fbadml; /* Flexbus AD Med-Low Port Output Data Register */
u8 podr_fbadl; /* Flexbus AD Low Port Output Data Register */
u8 pddr_fec0h; /* FEC0 High Port Data Direction Register */
u8 pddr_fec0l; /* FEC0 Low Port Data Direction Register */
u8 pddr_ssi; /* SSI Port Data Direction Register */
u8 pddr_fbctl; /* Flexbus Control Port Data Direction Register */
u8 pddr_be; /* Flexbus Byte Enable Port Data Direction Register */
u8 pddr_cs; /* Flexbus Chip-Select Port Data Direction Register */
u8 pddr_dma; /* DMA Port Data Direction Register */
u8 pddr_feci2c; /* FEC1 / I2C Port Data Direction Register */
u8 resv2[0x1];
u8 pddr_uart; /* UART Port Data Direction Register */
u8 pddr_dspi; /* DSPI Port Data Direction Register */
u8 pddr_timer; /* Timer Port Data Direction Register */
u8 pddr_pci; /* PCI Port Data Direction Register */
u8 pddr_usb; /* USB Port Data Direction Register */
u8 pddr_atah; /* ATA High Port Data Direction Register */
u8 pddr_atal; /* ATA Low Port Data Direction Register */
u8 pddr_fec1h; /* FEC1 High Port Data Direction Register */
u8 pddr_fec1l; /* FEC1 Low Port Data Direction Register */
u8 resv3[0x2];
u8 pddr_fbadh; /* Flexbus AD High Port Data Direction Register */
u8 pddr_fbadmh; /* Flexbus AD Med-High Port Data Direction Register */
u8 pddr_fbadml; /* Flexbus AD Med-Low Port Data Direction Register */
u8 pddr_fbadl; /* Flexbus AD Low Port Data Direction Register */
u8 ppdsdr_fec0h; /* FEC0 High Port Pin Data/Set Data Register */
u8 ppdsdr_fec0l; /* FEC0 Low Port Clear Output Data Register */
u8 ppdsdr_ssi; /* SSI Port Pin Data/Set Data Register */
u8 ppdsdr_fbctl; /* Flexbus Control Port Pin Data/Set Data Register */
u8 ppdsdr_be; /* Flexbus Byte Enable Port Pin Data/Set Data Register */
u8 ppdsdr_cs; /* Flexbus Chip-Select Port Pin Data/Set Data Register */
u8 ppdsdr_dma; /* DMA Port Pin Data/Set Data Register */
u8 ppdsdr_feci2c; /* FEC1 / I2C Port Pin Data/Set Data Register */
u8 resv4[0x1];
u8 ppdsdr_uart; /* UART Port Pin Data/Set Data Register */
u8 ppdsdr_dspi; /* DSPI Port Pin Data/Set Data Register */
u8 ppdsdr_timer; /* FTimer Port Pin Data/Set Data Register */
u8 ppdsdr_pci; /* PCI Port Pin Data/Set Data Register */
u8 ppdsdr_usb; /* USB Port Pin Data/Set Data Register */
u8 ppdsdr_atah; /* ATA High Port Pin Data/Set Data Register */
u8 ppdsdr_atal; /* ATA Low Port Pin Data/Set Data Register */
u8 ppdsdr_fec1h; /* FEC1 High Port Pin Data/Set Data Register */
u8 ppdsdr_fec1l; /* FEC1 Low Port Pin Data/Set Data Register */
u8 resv5[0x2];
u8 ppdsdr_fbadh; /* Flexbus AD High Port Pin Data/Set Data Register */
u8 ppdsdr_fbadmh; /* Flexbus AD Med-High Port Pin Data/Set Data Register */
u8 ppdsdr_fbadml; /* Flexbus AD Med-Low Port Pin Data/Set Data Register */
u8 ppdsdr_fbadl; /* Flexbus AD Low Port Pin Data/Set Data Register */
u8 pclrr_fec0h; /* FEC0 High Port Clear Output Data Register */
u8 pclrr_fec0l; /* FEC0 Low Port Pin Data/Set Data Register */
u8 pclrr_ssi; /* SSI Port Clear Output Data Register */
u8 pclrr_fbctl; /* Flexbus Control Port Clear Output Data Register */
u8 pclrr_be; /* Flexbus Byte Enable Port Clear Output Data Register */
u8 pclrr_cs; /* Flexbus Chip-Select Port Clear Output Data Register */
u8 pclrr_dma; /* DMA Port Clear Output Data Register */
u8 pclrr_feci2c; /* FEC1 / I2C Port Clear Output Data Register */
u8 resv6[0x1];
u8 pclrr_uart; /* UART Port Clear Output Data Register */
u8 pclrr_dspi; /* DSPI Port Clear Output Data Register */
u8 pclrr_timer; /* Timer Port Clear Output Data Register */
u8 pclrr_pci; /* PCI Port Clear Output Data Register */
u8 pclrr_usb; /* USB Port Clear Output Data Register */
u8 pclrr_atah; /* ATA High Port Clear Output Data Register */
u8 pclrr_atal; /* ATA Low Port Clear Output Data Register */
u8 pclrr_fec1h; /* FEC1 High Port Clear Output Data Register */
u8 pclrr_fec1l; /* FEC1 Low Port Clear Output Data Register */
u8 resv7[0x2];
u8 pclrr_fbadh; /* Flexbus AD High Port Clear Output Data Register */
u8 pclrr_fbadmh; /* Flexbus AD Med-High Port Clear Output Data Register */
u8 pclrr_fbadml; /* Flexbus AD Med-Low Port Clear Output Data Register */
u8 pclrr_fbadl; /* Flexbus AD Low Port Clear Output Data Register */
u8 par_fec; /* FEC Pin Assignment Register */
u8 par_dma; /* DMA Pin Assignment Register */
u8 par_fbctl; /* Flexbus Control Pin Assignment Register */
u8 par_dspi; /* DSPI Pin Assignment Register */
u8 par_be; /* Flexbus Byte-Enable Pin Assignment Register */
u8 par_cs; /* Flexbus Chip-Select Pin Assignment Register */
u8 par_timer; /* Time Pin Assignment Register */
u8 par_usb; /* USB Pin Assignment Register */
u8 resv8[0x1];
u8 par_uart; /* UART Pin Assignment Register */
u16 par_feci2c; /* FEC / I2C Pin Assignment Register */
u16 par_ssi; /* SSI Pin Assignment Register */
u16 par_ata; /* ATA Pin Assignment Register */
u8 par_irq; /* IRQ Pin Assignment Register */
u8 resv9[0x1];
u16 par_pci; /* PCI Pin Assignment Register */
u8 mscr_sdram; /* SDRAM Mode Select Control Register */
u8 mscr_pci; /* PCI Mode Select Control Register */
u8 resv10[0x2];
u8 dscr_i2c; /* I2C Drive Strength Control Register */
u8 dscr_flexbus; /* FLEXBUS Drive Strength Control Register */
u8 dscr_fec; /* FEC Drive Strength Control Register */
u8 dscr_uart; /* UART Drive Strength Control Register */
u8 dscr_dspi; /* DSPI Drive Strength Control Register */
u8 dscr_timer; /* TIMER Drive Strength Control Register */
u8 dscr_ssi; /* SSI Drive Strength Control Register */
u8 dscr_dma; /* DMA Drive Strength Control Register */
u8 dscr_debug; /* DEBUG Drive Strength Control Register */
u8 dscr_reset; /* RESET Drive Strength Control Register */
u8 dscr_irq; /* IRQ Drive Strength Control Register */
u8 dscr_usb; /* USB Drive Strength Control Register */
u8 dscr_ata; /* ATA Drive Strength Control Register */
} gpio_t;
/*********************************************************************
* Random Number Generator (RNG)
*********************************************************************/
typedef struct rng {
u32 rngcr;
u32 rngsr;
u32 rnger;
u32 rngout;
} rng_t;
/*********************************************************************
* SDRAM Controller (SDRAMC)
*********************************************************************/
typedef struct sdramc {
u32 sdmr; /* SDRAM Mode/Extended Mode Register */
u32 sdcr; /* SDRAM Control Register */
u32 sdcfg1; /* SDRAM Configuration Register 1 */
u32 sdcfg2; /* SDRAM Chip Select Register */
u8 resv0[0x100];
u32 sdcs0; /* SDRAM Mode/Extended Mode Register */
u32 sdcs1; /* SDRAM Mode/Extended Mode Register */
} sdramc_t;
/*********************************************************************
* Synchronous Serial Interface (SSI)
*********************************************************************/
typedef struct ssi {
u32 tx0;
u32 tx1;
u32 rx0;
u32 rx1;
u32 cr;
u32 isr;
u32 ier;
u32 tcr;
u32 rcr;
u32 ccr;
u8 resv0[0x4];
u32 fcsr;
u8 resv1[0x8];
u32 acr;
u32 acadd;
u32 acdat;
u32 atag;
u32 tmask;
u32 rmask;
} ssi_t;
/*********************************************************************
* Phase Locked Loop (PLL)
*********************************************************************/
typedef struct pll {
u32 pcr; /* PLL Control Register */
u32 psr; /* PLL Status Register */
} pll_t;
typedef struct pci {
u32 idr; /* 0x00 Device Id / Vendor Id Register */
u32 scr; /* 0x04 Status / command Register */
u32 ccrir; /* 0x08 Class Code / Revision Id Register */
u32 cr1; /* 0x0c Configuration 1 Register */
u32 bar0; /* 0x10 Base address register 0 Register */
u32 bar1; /* 0x14 Base address register 1 Register */
u32 bar2; /* 0x18 Base address register 2 Register */
u32 bar3; /* 0x1c Base address register 3 Register */
u32 bar4; /* 0x20 Base address register 4 Register */
u32 bar5; /* 0x24 Base address register 5 Register */
u32 ccpr; /* 0x28 Cardbus CIS Pointer Register */
u32 sid; /* 0x2c Subsystem ID / Subsystem Vendor ID Register */
u32 erbar; /* 0x30 Expansion ROM Base Address Register */
u32 cpr; /* 0x34 Capabilities Pointer Register */
u32 rsvd1; /* 0x38 */
u32 cr2; /* 0x3c Configuration Register 2 */
u32 rsvd2[8]; /* 0x40 - 0x5f */
/* General control / status registers */
u32 gscr; /* 0x60 Global Status / Control Register */
u32 tbatr0a; /* 0x64 Target Base Address Translation Register 0 */
u32 tbatr1a; /* 0x68 Target Base Address Translation Register 1 */
u32 tcr1; /* 0x6c Target Control 1 Register */
u32 iw0btar; /* 0x70 Initiator Window 0 Base/Translation addr */
u32 iw1btar; /* 0x74 Initiator Window 1 Base/Translation addr */
u32 iw2btar; /* 0x78 Initiator Window 2 Base/Translation addr */
u32 rsvd3; /* 0x7c */
u32 iwcr; /* 0x80 Initiator Window Configuration Register */
u32 icr; /* 0x84 Initiator Control Register */
u32 isr; /* 0x88 Initiator Status Register */
u32 tcr2; /* 0x8c Target Control 2 Register */
u32 tbatr0; /* 0x90 Target Base Address Translation Register 0 */
u32 tbatr1; /* 0x94 Target Base Address Translation Register 1 */
u32 tbatr2; /* 0x98 Target Base Address Translation Register 2 */
u32 tbatr3; /* 0x9c Target Base Address Translation Register 3 */
u32 tbatr4; /* 0xa0 Target Base Address Translation Register 4 */
u32 tbatr5; /* 0xa4 Target Base Address Translation Register 5 */
u32 intr; /* 0xa8 Interrupt Register */
u32 rsvd4[19]; /* 0xac - 0xf7 */
u32 car; /* 0xf8 Configuration Address Register */
} pci_t;
typedef struct pci_arbiter {
/* Pci Arbiter Registers */
union {
u32 acr; /* Arbiter Control Register */
u32 asr; /* Arbiter Status Register */
};
} pciarb_t;
/* Register read/write struct */
typedef struct scm1 {
u32 mpr; /* 0x00 Master Privilege Register */
u32 rsvd1[7];
u32 pacra; /* 0x20 Peripheral Access Control Register A */
u32 pacrb; /* 0x24 Peripheral Access Control Register B */
u32 pacrc; /* 0x28 Peripheral Access Control Register C */
u32 pacrd; /* 0x2C Peripheral Access Control Register D */
u32 rsvd2[4];
u32 pacre; /* 0x40 Peripheral Access Control Register E */
u32 pacrf; /* 0x44 Peripheral Access Control Register F */
u32 pacrg; /* 0x48 Peripheral Access Control Register G */
} scm1_t;
/********************************************************************/
typedef struct rtcex {
u32 rsvd1[3];
u32 gocu;
u32 gocl;
} rtcex_t;
#endif /* __IMMAP_5445X__ */

221
include/asm-m68k/io.h
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@@ -1,8 +1,221 @@
#ifndef __ASM_M68K_IO_H_
#define __ASM_M68K_IO_H_
/*
* IO header file
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __ASM_M68K_IO_H__
#define __ASM_M68K_IO_H__
#include <asm/byteorder.h>
#define readb(addr) in_8((volatile u8 *)(addr))
#define writeb(b,addr) out_8((volatile u8 *)(addr), (b))
#if !defined(__BIG_ENDIAN)
#define readw(addr) (*(volatile u16 *) (addr))
#define readl(addr) (*(volatile u32 *) (addr))
#define writew(b,addr) ((*(volatile u16 *) (addr)) = (b))
#define writel(b,addr) ((*(volatile u32 *) (addr)) = (b))
#else
#define readw(addr) in_le16((volatile u16 *)(addr))
#define readl(addr) in_le32((volatile u32 *)(addr))
#define writew(b,addr) out_le16((volatile u16 *)(addr),(b))
#define writel(b,addr) out_le32((volatile u32 *)(addr),(b))
#endif
/*
* The insw/outsw/insl/outsl macros don't do byte-swapping.
* They are only used in practice for transferring buffers which
* are arrays of bytes, and byte-swapping is not appropriate in
* that case. - paulus
*/
#define insb(port, buf, ns) _insb((u8 *)((port)+_IO_BASE), (buf), (ns))
#define outsb(port, buf, ns) _outsb((u8 *)((port)+_IO_BASE), (buf), (ns))
#define insw(port, buf, ns) _insw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
#define outsw(port, buf, ns) _outsw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
#define insl(port, buf, nl) _insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
#define outsl(port, buf, nl) _outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
#define inb(port) in_8((u8 *)((port)+_IO_BASE))
#define outb(val, port) out_8((u8 *)((port)+_IO_BASE), (val))
#if !defined(__BIG_ENDIAN)
#define inw(port) in_be16((u16 *)((port)+_IO_BASE))
#define outw(val, port) out_be16((u16 *)((port)+_IO_BASE), (val))
#define inl(port) in_be32((u32 *)((port)+_IO_BASE))
#define outl(val, port) out_be32((u32 *)((port)+_IO_BASE), (val))
#else
#define inw(port) in_le16((u16 *)((port)+_IO_BASE))
#define outw(val, port) out_le16((u16 *)((port)+_IO_BASE), (val))
#define inl(port) in_le32((u32 *)((port)+_IO_BASE))
#define outl(val, port) out_le32((u32 *)((port)+_IO_BASE), (val))
#endif
extern inline void _insb(volatile u8 * port, void *buf, int ns)
{
u8 *data = (u8 *) buf;
while (ns--)
*data++ = *port;
}
extern inline void _outsb(volatile u8 * port, const void *buf, int ns)
{
u8 *data = (u8 *) buf;
while (ns--)
*port = *data++;
}
extern inline void _insw(volatile u16 * port, void *buf, int ns)
{
u16 *data = (u16 *) buf;
while (ns--)
*data++ = __sw16(*port);
}
extern inline void _outsw(volatile u16 * port, const void *buf, int ns)
{
u16 *data = (u16 *) buf;
while (ns--) {
*port = __sw16(*data);
data++;
}
}
extern inline void _insl(volatile u32 * port, void *buf, int nl)
{
u32 *data = (u32 *) buf;
while (nl--)
*data++ = __sw32(*port);
}
extern inline void _outsl(volatile u32 * port, const void *buf, int nl)
{
u32 *data = (u32 *) buf;
while (nl--) {
*port = __sw32(*data);
data++;
}
}
extern inline void _insw_ns(volatile u16 * port, void *buf, int ns)
{
u16 *data = (u16 *) buf;
while (ns--)
*data++ = *port;
}
extern inline void _outsw_ns(volatile u16 * port, const void *buf, int ns)
{
u16 *data = (u16 *) buf;
while (ns--) {
*port = *data++;
}
}
extern inline void _insl_ns(volatile u32 * port, void *buf, int nl)
{
u32 *data = (u32 *) buf;
while (nl--)
*data++ = *port;
}
extern inline void _outsl_ns(volatile u32 * port, const void *buf, int nl)
{
u32 *data = (u32 *) buf;
while (nl--) {
*port = *data;
data++;
}
}
/*
* The *_ns versions below don't do byte-swapping.
* Neither do the standard versions now, these are just here
* for older code.
*/
#define insw_ns(port, buf, ns) _insw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
#define outsw_ns(port, buf, ns) _outsw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
#define insl_ns(port, buf, nl) _insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
#define outsl_ns(port, buf, nl) _outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
#define IO_SPACE_LIMIT ~0
/*
* 8, 16 and 32 bit, big and little endian I/O operations, with barrier.
*/
extern inline int in_8(volatile u8 * addr)
{
return (int)*addr;
}
extern inline void out_8(volatile u8 * addr, int val)
{
*addr = (u8) val;
}
extern inline int in_le16(volatile u16 * addr)
{
return __sw16(*addr);
}
extern inline int in_be16(volatile u16 * addr)
{
return (*addr & 0xFFFF);
}
extern inline void out_le16(volatile u16 * addr, int val)
{
*addr = __sw16(val);
}
extern inline void out_be16(volatile u16 * addr, int val)
{
*addr = (u16) val;
}
extern inline unsigned in_le32(volatile u32 * addr)
{
return __sw32(*addr);
}
extern inline unsigned in_be32(volatile u32 * addr)
{
return (*addr);
}
extern inline void out_le32(volatile unsigned *addr, int val)
{
*addr = __sw32(val);
}
extern inline void out_be32(volatile unsigned *addr, int val)
{
*addr = val;
}
static inline void sync(void)
{
/* This sync function is for PowerPC or other architecture instruction
* ColdFire does not have this instruction. Dummy function, added for
* compatibility (CFI driver)
*/
}
#endif /* __ASM_M68K_IO_H_ */
#endif /* __ASM_M68K_IO_H__ */

905
include/asm-m68k/m5235.h Normal file
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@@ -0,0 +1,905 @@
/*
* mcf5329.h -- Definitions for Freescale Coldfire 5329
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef mcf5235_h
#define mcf5235_h
/****************************************************************************/
/*********************************************************************
* System Control Module (SCM)
*********************************************************************/
/* Bit definition and macros for SCM_IPSBAR */
#define SCM_IPSBAR_BA(x) (((x)&0x03)<<30)
#define SCM_IPSBAR_V (0x00000001)
/* Bit definition and macros for SCM_RAMBAR */
#define SCM_RAMBAR_BA(x) (((x)&0xFFFF)<<16)
#define SCM_RAMBAR_BDE (0x00000200)
/* Bit definition and macros for SCM_CRSR */
#define SCM_CRSR_EXT (0x80)
/* Bit definitions and macros for SCM_CWCR */
#define SCM_CWCR_CWE (0x80)
#define SCM_CWCR_CWRI (0x40)
#define SCM_CWCR_CWT(x) (((x)&0x07)<<3)
#define SCM_CWCR_CWTA (0x04)
#define SCM_CWCR_CWTAVAL (0x02)
#define SCM_CWCR_CWTIC (0x01)
/* Bit definitions and macros for SCM_LPICR */
#define SCM_LPICR_ENBSTOP (0x80)
#define SCM_LPICR_XLPM_IPL(x) (((x)&0x07)<<4)
#define SCM_LPICR_XLPM_IPL_ANY (0x00)
#define SCM_LPICR_XLPM_IPL_L2_7 (0x10)
#define SCM_LPICR_XLPM_IPL_L3_7 (0x20)
#define SCM_LPICR_XLPM_IPL_L4_7 (0x30)
#define SCM_LPICR_XLPM_IPL_L5_7 (0x40)
#define SCM_LPICR_XLPM_IPL_L6_7 (0x50)
#define SCM_LPICR_XLPM_IPL_L7 (0x70)
/* Bit definitions and macros for SCM_DMAREQC */
#define SCM_DMAREQC_EXT(x) (((x)&0x0F)<<16)
#define SCM_DMAREQC_EXT_ETPU (0x00080000)
#define SCM_DMAREQC_EXT_EXTDREQ2 (0x00040000)
#define SCM_DMAREQC_EXT_EXTDREQ1 (0x00020000)
#define SCM_DMAREQC_EXT_EXTDREQ0 (0x00010000)
#define SCM_DMAREQC_DMAC3(x) (((x)&0x0F)<<12)
#define SCM_DMAREQC_DMAC2(x) (((x)&0x0F)<<8)
#define SCM_DMAREQC_DMAC1(x) (((x)&0x0F)<<4)
#define SCM_DMAREQC_DMAC0(x) (((x)&0x0F))
#define SCM_DMAREQC_DMACn_DTMR0 (0x04)
#define SCM_DMAREQC_DMACn_DTMR1 (0x05)
#define SCM_DMAREQC_DMACn_DTMR2 (0x06)
#define SCM_DMAREQC_DMACn_DTMR3 (0x07)
#define SCM_DMAREQC_DMACn_UART0RX (0x08)
#define SCM_DMAREQC_DMACn_UART1RX (0x09)
#define SCM_DMAREQC_DMACn_UART2RX (0x0A)
#define SCM_DMAREQC_DMACn_UART0TX (0x0C)
#define SCM_DMAREQC_DMACn_UART1TX (0x0D)
#define SCM_DMAREQC_DMACn_UART3TX (0x0E)
/* Bit definitions and macros for SCM_MPARK */
#define SCM_MPARK_M2_P_EN (0x02000000)
#define SCM_MPARK_M3_PRTY_MSK (0x00C00000)
#define SCM_MPARK_M3_PRTY_4TH (0x00000000)
#define SCM_MPARK_M3_PRTY_3RD (0x00400000)
#define SCM_MPARK_M3_PRTY_2ND (0x00800000)
#define SCM_MPARK_M3_PRTY_1ST (0x00C00000)
#define SCM_MPARK_M2_PRTY_MSK (0x00300000)
#define SCM_MPARK_M2_PRTY_4TH (0x00000000)
#define SCM_MPARK_M2_PRTY_3RD (0x00100000)
#define SCM_MPARK_M2_PRTY_2ND (0x00200000)
#define SCM_MPARK_M2_PRTY_1ST (0x00300000)
#define SCM_MPARK_M0_PRTY_MSK (0x000C0000)
#define SCM_MPARK_M0_PRTY_4TH (0x00000000)
#define SCM_MPARK_M0_PRTY_3RD (0x00040000)
#define SCM_MPARK_M0_PRTY_2ND (0x00080000)
#define SCM_MPARK_M0_PRTY_1ST (0x000C0000)
#define SCM_MPARK_FIXED (0x00004000)
#define SCM_MPARK_TIMEOUT (0x00002000)
#define SCM_MPARK_PRKLAST (0x00001000)
#define SCM_MPARK_LCKOUT_TIME(x) (((x)&0x0F)<<8)
/* Bit definitions and macros for SCM_MPR */
#define SCM_MPR_MPR3 (0x08)
#define SCM_MPR_MPR2 (0x04)
#define SCM_MPR_MPR1 (0x02)
#define SCM_MPR_MPR0 (0x01)
/* Bit definitions and macros for SCM_PACRn */
#define SCM_PACRn_LOCK1 (0x80)
#define SCM_PACRn_ACCESSCTRL1(x) (((x)&0x07)<<4)
#define SCM_PACRn_LOCK0 (0x08)
#define SCM_PACRn_ACCESSCTRL0(x) (((x)&0x07))
/* Bit definitions and macros for SCM_GPACR */
#define SCM_PACRn_LOCK (0x80)
#define SCM_PACRn_ACCESSCTRL0(x) (((x)&0x07))
/*********************************************************************
* SDRAM Controller (SDRAMC)
*********************************************************************/
/* Bit definitions and macros for SDRAMC_DCR */
#define SDRAMC_DCR_NAM (0x2000)
#define SDRAMC_DCR_COC (0x1000)
#define SDRAMC_DCR_IS (0x0800)
#define SDRAMC_DCR_RTIM_MASK (0x0C00)
#define SDRAMC_DCR_RTIM_3CLKS (0x0000)
#define SDRAMC_DCR_RTIM_6CLKS (0x0200)
#define SDRAMC_DCR_RTIM_9CLKS (0x0400)
#define SDRAMC_DCR_RC(x) (((x)&0xFF)<<8)
/* Bit definitions and macros for SDRAMC_DARCn */
#define SDRAMC_DARCn_BA(x) (((x)&0xFFFC)<<18)
#define SDRAMC_DARCn_RE (0x00008000)
#define SDRAMC_DARCn_CASL_MASK (0x00003000)
#define SDRAMC_DARCn_CASL_C0 (0x00000000)
#define SDRAMC_DARCn_CASL_C1 (0x00001000)
#define SDRAMC_DARCn_CASL_C2 (0x00002000)
#define SDRAMC_DARCn_CASL_C3 (0x00003000)
#define SDRAMC_DARCn_CBM_MASK (0x00000700)
#define SDRAMC_DARCn_CBM_CMD17 (0x00000000)
#define SDRAMC_DARCn_CBM_CMD18 (0x00000100)
#define SDRAMC_DARCn_CBM_CMD19 (0x00000200)
#define SDRAMC_DARCn_CBM_CMD20 (0x00000300)
#define SDRAMC_DARCn_CBM_CMD21 (0x00000400)
#define SDRAMC_DARCn_CBM_CMD22 (0x00000500)
#define SDRAMC_DARCn_CBM_CMD23 (0x00000600)
#define SDRAMC_DARCn_CBM_CMD24 (0x00000700)
#define SDRAMC_DARCn_IMRS (0x00000040)
#define SDRAMC_DARCn_PS_MASK (0x00000030)
#define SDRAMC_DARCn_PS_32 (0x00000000)
#define SDRAMC_DARCn_PS_16 (0x00000010)
#define SDRAMC_DARCn_PS_8 (0x00000020)
#define SDRAMC_DARCn_IP (0x00000008)
/* Bit definitions and macros for SDRAMC_DMRn */
#define SDRAMC_DMRn_BAM(x) (((x)&0x3FFF)<<18)
#define SDRAMC_DMRn_WP (0x00000100)
#define SDRAMC_DMRn_V (0x00000001)
/*********************************************************************
* FlexBus Chip Selects (FBCS)
*********************************************************************/
/* Bit definitions and macros for FBCS_CSMR */
#define FBCS_CSMR_BAM(x) (((x)&0xFFFF)<<16)
#define FBCS_CSMR_BAM_4G (0xFFFF0000)
#define FBCS_CSMR_BAM_2G (0x7FFF0000)
#define FBCS_CSMR_BAM_1G (0x3FFF0000)
#define FBCS_CSMR_BAM_1024M (0x3FFF0000)
#define FBCS_CSMR_BAM_512M (0x1FFF0000)
#define FBCS_CSMR_BAM_256M (0x0FFF0000)
#define FBCS_CSMR_BAM_128M (0x07FF0000)
#define FBCS_CSMR_BAM_64M (0x03FF0000)
#define FBCS_CSMR_BAM_32M (0x01FF0000)
#define FBCS_CSMR_BAM_16M (0x00FF0000)
#define FBCS_CSMR_BAM_8M (0x007F0000)
#define FBCS_CSMR_BAM_4M (0x003F0000)
#define FBCS_CSMR_BAM_2M (0x001F0000)
#define FBCS_CSMR_BAM_1M (0x000F0000)
#define FBCS_CSMR_BAM_1024K (0x000F0000)
#define FBCS_CSMR_BAM_512K (0x00070000)
#define FBCS_CSMR_BAM_256K (0x00030000)
#define FBCS_CSMR_BAM_128K (0x00010000)
#define FBCS_CSMR_BAM_64K (0x00000000)
#define FBCS_CSMR_WP (0x00000100)
#define FBCS_CSMR_V (0x00000001)
/* Bit definitions and macros for FBCS_CSCR */
#define FBCS_CSCR_SRWS(x) (((x)&0x03)<<14)
#define FBCS_CSCR_IWS(x) (((x)&0x0F)<<10)
#define FBCS_CSCR_AA (0x0100)
#define FBCS_CSCR_PS_MASK (0x00C0)
#define FBCS_CSCR_PS_32 (0x0000)
#define FBCS_CSCR_PS_16 (0x0080)
#define FBCS_CSCR_PS_8 (0x0040)
#define FBCS_CSCR_BEM (0x0020)
#define FBCS_CSCR_BSTR (0x0010)
#define FBCS_CSCR_BSTW (0x0008)
#define FBCS_CSCR_SWWS(x) ((x)&0x07)
/*********************************************************************
* Queued Serial Peripheral Interface (QSPI)
*********************************************************************/
/* Bit definitions and macros for QSPI_QMR */
#define QSPI_QMR_MSTR (0x8000)
#define QSPI_QMR_DOHIE (0x4000)
#define QSPI_QMR_BITS(x) (((x)&0x000F)<<10)
#define QSPI_QMR_CPOL (0x0200)
#define QSPI_QMR_CPHA (0x0100)
#define QSPI_QMR_BAUD(x) ((x)&0x00FF)
/* Bit definitions and macros for QSPI_QDLYR */
#define QSPI_QDLYR_SPE (0x8000)
#define QSPI_QDLYR_QCD(x) (((x)&0x007F)<<8)
#define QSPI_QDLYR_DTL(x) ((x)&0x00FF)
/* Bit definitions and macros for QSPI_QWR */
#define QSPI_QWR_HALT (0x8000)
#define QSPI_QWR_WREN (0x4000)
#define QSPI_QWR_WRTO (0x2000)
#define QSPI_QWR_CSIV (0x1000)
#define QSPI_QWR_ENDQP(x) (((x)&0x000F)<<8)
#define QSPI_QWR_NEWQP(x) ((x)&0x000F)
/* Bit definitions and macros for QSPI_QIR */
#define QSPI_QIR_WCEFB (0x8000)
#define QSPI_QIR_ABRTB (0x4000)
#define QSPI_QIR_ABRTL (0x1000)
#define QSPI_QIR_WCEFE (0x0800)
#define QSPI_QIR_ABRTE (0x0400)
#define QSPI_QIR_SPIFE (0x0100)
#define QSPI_QIR_WCEF (0x0008)
#define QSPI_QIR_ABRT (0x0004)
#define QSPI_QIR_SPIF (0x0001)
/* Bit definitions and macros for QSPI_QAR */
#define QSPI_QAR_ADDR(x) ((x)&0x003F)
/* Bit definitions and macros for QSPI_QDR */
#define QSPI_QDR_CONT (0x8000)
#define QSPI_QDR_BITSE (0x4000)
#define QSPI_QDR_DT (0x2000)
#define QSPI_QDR_DSCK (0x1000)
#define QSPI_QDR_QSPI_CS3 (0x0800)
#define QSPI_QDR_QSPI_CS2 (0x0400)
#define QSPI_QDR_QSPI_CS1 (0x0200)
#define QSPI_QDR_QSPI_CS0 (0x0100)
/*********************************************************************
* Interrupt Controller (INTC)
*********************************************************************/
#define INT0_LO_RSVD0 (0)
#define INT0_LO_EPORT1 (1)
#define INT0_LO_EPORT2 (2)
#define INT0_LO_EPORT3 (3)
#define INT0_LO_EPORT4 (4)
#define INT0_LO_EPORT5 (5)
#define INT0_LO_EPORT6 (6)
#define INT0_LO_EPORT7 (7)
#define INT0_LO_SCM (8)
#define INT0_LO_DMA0 (9)
#define INT0_LO_DMA1 (10)
#define INT0_LO_DMA2 (11)
#define INT0_LO_DMA3 (12)
#define INT0_LO_UART0 (13)
#define INT0_LO_UART1 (14)
#define INT0_LO_UART2 (15)
#define INT0_LO_RSVD1 (16)
#define INT0_LO_I2C (17)
#define INT0_LO_QSPI (18)
#define INT0_LO_DTMR0 (19)
#define INT0_LO_DTMR1 (20)
#define INT0_LO_DTMR2 (21)
#define INT0_LO_DTMR3 (22)
#define INT0_LO_FEC_TXF (23)
#define INT0_LO_FEC_TXB (24)
#define INT0_LO_FEC_UN (25)
#define INT0_LO_FEC_RL (26)
#define INT0_LO_FEC_RXF (27)
#define INT0_LO_FEC_RXB (28)
#define INT0_LO_FEC_MII (29)
#define INT0_LO_FEC_LC (30)
#define INT0_LO_FEC_HBERR (31)
#define INT0_HI_FEC_GRA (32)
#define INT0_HI_FEC_EBERR (33)
#define INT0_HI_FEC_BABT (34)
#define INT0_HI_FEC_BABR (35)
#define INT0_HI_PIT0 (36)
#define INT0_HI_PIT1 (37)
#define INT0_HI_PIT2 (38)
#define INT0_HI_PIT3 (39)
#define INT0_HI_RNG (40)
#define INT0_HI_SKHA (41)
#define INT0_HI_MDHA (42)
#define INT0_HI_CAN1_BUF0I (43)
#define INT0_HI_CAN1_BUF1I (44)
#define INT0_HI_CAN1_BUF2I (45)
#define INT0_HI_CAN1_BUF3I (46)
#define INT0_HI_CAN1_BUF4I (47)
#define INT0_HI_CAN1_BUF5I (48)
#define INT0_HI_CAN1_BUF6I (49)
#define INT0_HI_CAN1_BUF7I (50)
#define INT0_HI_CAN1_BUF8I (51)
#define INT0_HI_CAN1_BUF9I (52)
#define INT0_HI_CAN1_BUF10I (53)
#define INT0_HI_CAN1_BUF11I (54)
#define INT0_HI_CAN1_BUF12I (55)
#define INT0_HI_CAN1_BUF13I (56)
#define INT0_HI_CAN1_BUF14I (57)
#define INT0_HI_CAN1_BUF15I (58)
#define INT0_HI_CAN1_ERRINT (59)
#define INT0_HI_CAN1_BOFFINT (60)
/* 60-63 Reserved */
/* 0 - 7 Reserved */
#define INT1_LO_CAN1_BUF0I (8)
#define INT1_LO_CAN1_BUF1I (9)
#define INT1_LO_CAN1_BUF2I (10)
#define INT1_LO_CAN1_BUF3I (11)
#define INT1_LO_CAN1_BUF4I (12)
#define INT1_LO_CAN1_BUF5I (13)
#define INT1_LO_CAN1_BUF6I (14)
#define INT1_LO_CAN1_BUF7I (15)
#define INT1_LO_CAN1_BUF8I (16)
#define INT1_LO_CAN1_BUF9I (17)
#define INT1_LO_CAN1_BUF10I (18)
#define INT1_LO_CAN1_BUF11I (19)
#define INT1_LO_CAN1_BUF12I (20)
#define INT1_LO_CAN1_BUF13I (21)
#define INT1_LO_CAN1_BUF14I (22)
#define INT1_LO_CAN1_BUF15I (23)
#define INT1_LO_CAN1_ERRINT (24)
#define INT1_LO_CAN1_BOFFINT (25)
/* 26 Reserved */
#define INT1_LO_ETPU_TC0F (27)
#define INT1_LO_ETPU_TC1F (28)
#define INT1_LO_ETPU_TC2F (29)
#define INT1_LO_ETPU_TC3F (30)
#define INT1_LO_ETPU_TC4F (31)
#define INT1_HI_ETPU_TC5F (32)
#define INT1_HI_ETPU_TC6F (33)
#define INT1_HI_ETPU_TC7F (34)
#define INT1_HI_ETPU_TC8F (35)
#define INT1_HI_ETPU_TC9F (36)
#define INT1_HI_ETPU_TC10F (37)
#define INT1_HI_ETPU_TC11F (38)
#define INT1_HI_ETPU_TC12F (39)
#define INT1_HI_ETPU_TC13F (40)
#define INT1_HI_ETPU_TC14F (41)
#define INT1_HI_ETPU_TC15F (42)
#define INT1_HI_ETPU_TC16F (43)
#define INT1_HI_ETPU_TC17F (44)
#define INT1_HI_ETPU_TC18F (45)
#define INT1_HI_ETPU_TC19F (46)
#define INT1_HI_ETPU_TC20F (47)
#define INT1_HI_ETPU_TC21F (48)
#define INT1_HI_ETPU_TC22F (49)
#define INT1_HI_ETPU_TC23F (50)
#define INT1_HI_ETPU_TC24F (51)
#define INT1_HI_ETPU_TC25F (52)
#define INT1_HI_ETPU_TC26F (53)
#define INT1_HI_ETPU_TC27F (54)
#define INT1_HI_ETPU_TC28F (55)
#define INT1_HI_ETPU_TC29F (56)
#define INT1_HI_ETPU_TC30F (57)
#define INT1_HI_ETPU_TC31F (58)
#define INT1_HI_ETPU_TGIF (59)
/* Bit definitions and macros for INTC_IPRH */
#define INTC_IPRH_INT63 (0x80000000)
#define INTC_IPRH_INT62 (0x40000000)
#define INTC_IPRH_INT61 (0x20000000)
#define INTC_IPRH_INT60 (0x10000000)
#define INTC_IPRH_INT59 (0x08000000)
#define INTC_IPRH_INT58 (0x04000000)
#define INTC_IPRH_INT57 (0x02000000)
#define INTC_IPRH_INT56 (0x01000000)
#define INTC_IPRH_INT55 (0x00800000)
#define INTC_IPRH_INT54 (0x00400000)
#define INTC_IPRH_INT53 (0x00200000)
#define INTC_IPRH_INT52 (0x00100000)
#define INTC_IPRH_INT51 (0x00080000)
#define INTC_IPRH_INT50 (0x00040000)
#define INTC_IPRH_INT49 (0x00020000)
#define INTC_IPRH_INT48 (0x00010000)
#define INTC_IPRH_INT47 (0x00008000)
#define INTC_IPRH_INT46 (0x00004000)
#define INTC_IPRH_INT45 (0x00002000)
#define INTC_IPRH_INT44 (0x00001000)
#define INTC_IPRH_INT43 (0x00000800)
#define INTC_IPRH_INT42 (0x00000400)
#define INTC_IPRH_INT41 (0x00000200)
#define INTC_IPRH_INT40 (0x00000100)
#define INTC_IPRH_INT39 (0x00000080)
#define INTC_IPRH_INT38 (0x00000040)
#define INTC_IPRH_INT37 (0x00000020)
#define INTC_IPRH_INT36 (0x00000010)
#define INTC_IPRH_INT35 (0x00000008)
#define INTC_IPRH_INT34 (0x00000004)
#define INTC_IPRH_INT33 (0x00000002)
#define INTC_IPRH_INT32 (0x00000001)
/* Bit definitions and macros for INTC_IPRL */
#define INTC_IPRL_INT31 (0x80000000)
#define INTC_IPRL_INT30 (0x40000000)
#define INTC_IPRL_INT29 (0x20000000)
#define INTC_IPRL_INT28 (0x10000000)
#define INTC_IPRL_INT27 (0x08000000)
#define INTC_IPRL_INT26 (0x04000000)
#define INTC_IPRL_INT25 (0x02000000)
#define INTC_IPRL_INT24 (0x01000000)
#define INTC_IPRL_INT23 (0x00800000)
#define INTC_IPRL_INT22 (0x00400000)
#define INTC_IPRL_INT21 (0x00200000)
#define INTC_IPRL_INT20 (0x00100000)
#define INTC_IPRL_INT19 (0x00080000)
#define INTC_IPRL_INT18 (0x00040000)
#define INTC_IPRL_INT17 (0x00020000)
#define INTC_IPRL_INT16 (0x00010000)
#define INTC_IPRL_INT15 (0x00008000)
#define INTC_IPRL_INT14 (0x00004000)
#define INTC_IPRL_INT13 (0x00002000)
#define INTC_IPRL_INT12 (0x00001000)
#define INTC_IPRL_INT11 (0x00000800)
#define INTC_IPRL_INT10 (0x00000400)
#define INTC_IPRL_INT9 (0x00000200)
#define INTC_IPRL_INT8 (0x00000100)
#define INTC_IPRL_INT7 (0x00000080)
#define INTC_IPRL_INT6 (0x00000040)
#define INTC_IPRL_INT5 (0x00000020)
#define INTC_IPRL_INT4 (0x00000010)
#define INTC_IPRL_INT3 (0x00000008)
#define INTC_IPRL_INT2 (0x00000004)
#define INTC_IPRL_INT1 (0x00000002)
#define INTC_IPRL_INT0 (0x00000001)
/* Bit definitions and macros for INTC_IRLR */
#define INTC_IRLRn(x) (((x)&0x7F)<<1)
/* Bit definitions and macros for INTC_IACKLPRn */
#define INTC_IACKLPRn_LEVEL(x) (((x)&0x07)<<4)
#define INTC_IACKLPRn_PRI(x) ((x)&0x0F)
/* Bit definitions and macros for INTC_ICRnx */
#define INTC_ICRnx_IL(x) (((x)&0x07)<<3)
#define INTC_ICRnx_IP(x) ((x)&0x07)
/*********************************************************************
* General Purpose I/O (GPIO)
*********************************************************************/
/* Bit definitions and macros for GPIO_PODR */
#define GPIO_PODR_ADDR(x) (((x)&0x07)<<5)
#define GPIO_PODR_ADDR_MASK (0xE0)
#define GPIO_PODR_BS(x) ((x)&0x0F)
#define GPIO_PODR_BS_MASK (0x0F)
#define GPIO_PODR_CS(x) (((x)&0x7F)<<1)
#define GPIO_PODR_CS_MASK (0xFE)
#define GPIO_PODR_SDRAM(X) ((x)&0x3F)
#define GPIO_PODR_SDRAM_MASK (0x3F)
#define GPIO_PODR_FECI2C(x) GPIO_PODR_BS(x)
#define GPIO_PODR_FECI2C_MASK GPIO_PODR_BS_MASK
#define GPIO_PODR_UARTH(x) ((x)&0x03)
#define GPIO_PODR_UARTH_MASK (0x03)
#define GPIO_PODR_QSPI(x) ((x)&0x1F)
#define GPIO_PODR_QSPI_MASK (0x1F)
#define GPIO_PODR_ETPU(x) ((x)&0x07)
#define GPIO_PODR_ETPU_MASK (0x07)
/* Bit definitions and macros for GPIO_PDDR */
#define GPIO_PDDR_ADDR(x) GPIO_PODR_ADDR(x)
#define GPIO_PDDR_ADDR_MASK GPIO_PODR_ADDR_MASK
#define GPIO_PDDR_BS(x) GPIO_PODR_BS(x)
#define GPIO_PDDR_BS_MASK GPIO_PODR_BS_MASK
#define GPIO_PDDR_CS(x) GPIO_PODR_CS(x)
#define GPIO_PDDR_CS_MASK GPIO_PODR_CS_MASK
#define GPIO_PDDR_SDRAM(X) GPIO_PODR_SDRAM(X)
#define GPIO_PDDR_SDRAM_MASK GPIO_PODR_SDRAM_MASK
#define GPIO_PDDR_FECI2C(x) GPIO_PDDR_BS(x)
#define GPIO_PDDR_FECI2C_MASK GPIO_PDDR_BS_MASK
#define GPIO_PDDR_UARTH(x) GPIO_PODR_UARTH(x)
#define GPIO_PDDR_UARTH_MASK GPIO_PODR_UARTH_MASK
#define GPIO_PDDR_QSPI(x) GPIO_PODR_QSPI(x)
#define GPIO_PDDR_QSPI_MASK GPIO_PODR_QSPI_MASK
#define GPIO_PDDR_ETPU(x) GPIO_PODR_ETPU(x)
#define GPIO_PDDR_ETPU_MASK GPIO_PODR_ETPU_MASK
/* Bit definitions and macros for GPIO_PPDSDR */
#define GPIO_PPDSDR_ADDR(x) GPIO_PODR_ADDR(x)
#define GPIO_PPDSDR_ADDR_MASK GPIO_PODR_ADDR_MASK
#define GPIO_PPDSDR_BS(x) GPIO_PODR_BS(x)
#define GPIO_PPDSDR_BS_MASK GPIO_PODR_BS_MASK
#define GPIO_PPDSDR_CS(x) GPIO_PODR_CS(x)
#define GPIO_PPDSDR_CS_MASK GPIO_PODR_CS_MASK
#define GPIO_PPDSDR_SDRAM(X) GPIO_PODR_SDRAM(X)
#define GPIO_PPDSDR_SDRAM_MASK GPIO_PODR_SDRAM_MASK
#define GPIO_PPDSDR_FECI2C(x) GPIO_PPDSDR_BS(x)
#define GPIO_PPDSDR_FECI2C_MASK GPIO_PPDSDR_BS_MASK
#define GPIO_PPDSDR_UARTH(x) GPIO_PODR_UARTH(x)
#define GPIO_PPDSDR_UARTH_MASK GPIO_PODR_UARTH_MASK
#define GPIO_PPDSDR_QSPI(x) GPIO_PODR_QSPI(x)
#define GPIO_PPDSDR_QSPI_MASK GPIO_PODR_QSPI_MASK
#define GPIO_PPDSDR_ETPU(x) GPIO_PODR_ETPU(x)
#define GPIO_PPDSDR_ETPU_MASK GPIO_PODR_ETPU_MASK
/* Bit definitions and macros for GPIO_PCLRR */
#define GPIO_PCLRR_ADDR(x) GPIO_PODR_ADDR(x)
#define GPIO_PCLRR_ADDR_MASK GPIO_PODR_ADDR_MASK
#define GPIO_PCLRR_BS(x) GPIO_PODR_BS(x)
#define GPIO_PCLRR_BS_MASK GPIO_PODR_BS_MASK
#define GPIO_PCLRR_CS(x) GPIO_PODR_CS(x)
#define GPIO_PCLRR_CS_MASK GPIO_PODR_CS_MASK
#define GPIO_PCLRR_SDRAM(X) GPIO_PODR_SDRAM(X)
#define GPIO_PCLRR_SDRAM_MASK GPIO_PODR_SDRAM_MASK
#define GPIO_PCLRR_FECI2C(x) GPIO_PCLRR_BS(x)
#define GPIO_PCLRR_FECI2C_MASK GPIO_PCLRR_BS_MASK
#define GPIO_PCLRR_UARTH(x) GPIO_PODR_UARTH(x)
#define GPIO_PCLRR_UARTH_MASK GPIO_PODR_UARTH_MASK
#define GPIO_PCLRR_QSPI(x) GPIO_PODR_QSPI(x)
#define GPIO_PCLRR_QSPI_MASK GPIO_PODR_QSPI_MASK
#define GPIO_PCLRR_ETPU(x) GPIO_PODR_ETPU(x)
#define GPIO_PCLRR_ETPU_MASK GPIO_PODR_ETPU_MASK
/* Bit definitions and macros for GPIO_PAR */
#define GPIO_PAR_AD_ADDR23 (0x80)
#define GPIO_PAR_AD_ADDR22 (0x40)
#define GPIO_PAR_AD_ADDR21 (0x20)
#define GPIO_PAR_AD_DATAL (0x01)
#define GPIO_PAR_BUSCTL_OE (0x4000)
#define GPIO_PAR_BUSCTL_TA (0x1000)
#define GPIO_PAR_BUSCTL_TEA(x) (((x)&0x03)<<10)
#define GPIO_PAR_BUSCTL_TEA_MASK (0x0C00)
#define GPIO_PAR_BUSCTL_TEA_GPIO (0x0400)
#define GPIO_PAR_BUSCTL_TEA_DREQ1 (0x0800)
#define GPIO_PAR_BUSCTL_TEA_EXTBUS (0x0C00)
#define GPIO_PAR_BUSCTL_RWB (0x0100)
#define GPIO_PAR_BUSCTL_TSIZ1 (0x0040)
#define GPIO_PAR_BUSCTL_TSIZ0 (0x0010)
#define GPIO_PAR_BUSCTL_TS(x) (((x)&0x03)<<2)
#define GPIO_PAR_BUSCTL_TS_MASK (0x0C)
#define GPIO_PAR_BUSCTL_TS_GPIO (0x04)
#define GPIO_PAR_BUSCTL_TS_DACK2 (0x08)
#define GPIO_PAR_BUSCTL_TS_EXTBUS (0x0C)
#define GPIO_PAR_BUSCTL_TIP(x) ((x)&0x03)
#define GPIO_PAR_BUSCTL_TIP_MASK (0x03)
#define GPIO_PAR_BUSCTL_TIP_GPIO (0x01)
#define GPIO_PAR_BUSCTL_TIP_DREQ0 (0x02)
#define GPIO_PAR_BUSCTL_TIP_EXTBUS (0x03)
#define GPIO_PAR_BS(x) ((x)&0x0F)
#define GPIO_PAR_BS_MASK (0x0F)
#define GPIO_PAR_CS(x) (((x)&0x7F)<<1)
#define GPIO_PAR_CS_MASK (0xFE)
#define GPIO_PAR_CS_CS7 (0x80)
#define GPIO_PAR_CS_CS6 (0x40)
#define GPIO_PAR_CS_CS5 (0x20)
#define GPIO_PAR_CS_CS4 (0x10)
#define GPIO_PAR_CS_CS3 (0x08)
#define GPIO_PAR_CS_CS2 (0x04)
#define GPIO_PAR_CS_CS1 (0x02)
#define GPIO_PAR_CS_SD3 GPIO_PAR_CS_CS3
#define GPIO_PAR_CS_SD2 GPIO_PAR_CS_CS2
#define GPIO_PAR_SDRAM_CSSDCS(x) (((x)&0x03)<<6)
#define GPIO_PAR_SDRAM_CSSDCS_MASK (0xC0)
#define GPIO_PAR_SDRAM_SDWE (0x20)
#define GPIO_PAR_SDRAM_SCAS (0x10)
#define GPIO_PAR_SDRAM_SRAS (0x08)
#define GPIO_PAR_SDRAM_SCKE (0x04)
#define GPIO_PAR_SDRAM_SDCS(x) ((x)&0x03)
#define GPIO_PAR_SDRAM_SDCS_MASK (0x03)
#define GPIO_PAR_FECI2C_EMDC(x) (((x)&0x03)<<6)
#define GPIO_PAR_FECI2C_EMDC_MASK (0xC0)
#define GPIO_PAR_FECI2C_EMDC_U2TXD (0x40)
#define GPIO_PAR_FECI2C_EMDC_I2CSCL (0x80)
#define GPIO_PAR_FECI2C_EMDC_FECEMDC (0xC0)
#define GPIO_PAR_FECI2C_EMDIO(x) (((x)&0x03)<<4)
#define GPIO_PAR_FECI2C_EMDIO_MASK (0x30)
#define GPIO_PAR_FECI2C_EMDIO_U2RXD (0x10)
#define GPIO_PAR_FECI2C_EMDIO_I2CSDA (0x20)
#define GPIO_PAR_FECI2C_EMDIO_FECEMDIO (0x30)
#define GPIO_PAR_FECI2C_SCL(x) (((x)&0x03)<<2)
#define GPIO_PAR_FECI2C_SCL_MASK (0x0C)
#define GPIO_PAR_FECI2C_SCL_CAN0RX (0x08)
#define GPIO_PAR_FECI2C_SCL_I2CSCL (0x0C)
#define GPIO_PAR_FECI2C_SDA(x) ((x)&0x03)
#define GPIO_PAR_FECI2C_SDA_MASK (0x03)
#define GPIO_PAR_FECI2C_SDA_CAN0TX (0x02)
#define GPIO_PAR_FECI2C_SDA_I2CSDA (0x03)
#define GPIO_PAR_UART_DREQ2 (0x8000)
#define GPIO_PAR_UART_CAN1EN (0x4000)
#define GPIO_PAR_UART_U2RXD (0x2000)
#define GPIO_PAR_UART_U2TXD (0x1000)
#define GPIO_PAR_UART_U1RXD(x) (((x)&0x03)<<10)
#define GPIO_PAR_UART_U1RXD_MASK (0x0C00)
#define GPIO_PAR_UART_U1RXD_CAN0RX (0x0800)
#define GPIO_PAR_UART_U1RXD_U1RXD (0x0C00)
#define GPIO_PAR_UART_U1TXD(x) (((x)&0x03)<<8)
#define GPIO_PAR_UART_U1TXD_MASK (0x0300)
#define GPIO_PAR_UART_U1TXD_CAN0TX (0x0200)
#define GPIO_PAR_UART_U1TXD_U1TXD (0x0300)
#define GPIO_PAR_UART_U1CTS(x) (((x)&0x03)<<6)
#define GPIO_PAR_UART_U1CTS_MASK (0x00C0)
#define GPIO_PAR_UART_U1CTS_U2CTS (0x0080)
#define GPIO_PAR_UART_U1CTS_U1CTS (0x00C0)
#define GPIO_PAR_UART_U1RTS(x) (((x)&0x03)<<4)
#define GPIO_PAR_UART_U1RTS_MASK (0x0030)
#define GPIO_PAR_UART_U1RTS_U2RTS (0x0020)
#define GPIO_PAR_UART_U1RTS_U1RTS (0x0030)
#define GPIO_PAR_UART_U0RXD (0x0008)
#define GPIO_PAR_UART_U0TXD (0x0004)
#define GPIO_PAR_UART_U0CTS (0x0002)
#define GPIO_PAR_UART_U0RTS (0x0001)
#define GPIO_PAR_QSPI_CS1(x) (((x)&0x03)<<6)
#define GPIO_PAR_QSPI_CS1_MASK (0xC0)
#define GPIO_PAR_QSPI_CS1_SDRAMSCKE (0x80)
#define GPIO_PAR_QSPI_CS1_QSPICS1 (0xC0)
#define GPIO_PAR_QSPI_CS0 (0x20)
#define GPIO_PAR_QSPI_DIN(x) (((x)&0x03)<<3)
#define GPIO_PAR_QSPI_DIN_MASK (0x18)
#define GPIO_PAR_QSPI_DIN_I2CSDA (0x10)
#define GPIO_PAR_QSPI_DIN_QSPIDIN (0x18)
#define GPIO_PAR_QSPI_DOUT (0x04)
#define GPIO_PAR_QSPI_SCK(x) ((x)&0x03)
#define GPIO_PAR_QSPI_SCK_MASK (0x03)
#define GPIO_PAR_QSPI_SCK_I2CSCL (0x02)
#define GPIO_PAR_QSPI_SCK_QSPISCK (0x03)
#define GPIO_PAR_DT3IN(x) (((x)&0x03)<<14)
#define GPIO_PAR_DT3IN_MASK (0xC000)
#define GPIO_PAR_DT3IN_QSPICS2 (0x4000)
#define GPIO_PAR_DT3IN_U2CTS (0x8000)
#define GPIO_PAR_DT3IN_DT3IN (0xC000)
#define GPIO_PAR_DT2IN(x) (((x)&0x03)<<12)
#define GPIO_PAR_DT2IN_MASK (0x3000)
#define GPIO_PAR_DT2IN_DT2OUT (0x1000)
#define GPIO_PAR_DT2IN_DREQ2 (0x2000)
#define GPIO_PAR_DT2IN_DT2IN (0x3000)
#define GPIO_PAR_DT1IN(x) (((x)&0x03)<<10)
#define GPIO_PAR_DT1IN_MASK (0x0C00)
#define GPIO_PAR_DT1IN_DT1OUT (0x0400)
#define GPIO_PAR_DT1IN_DREQ1 (0x0800)
#define GPIO_PAR_DT1IN_DT1IN (0x0C00)
#define GPIO_PAR_DT0IN(x) (((x)&0x03)<<8)
#define GPIO_PAR_DT0IN_MASK (0x0300)
#define GPIO_PAR_DT0IN_DREQ0 (0x0200)
#define GPIO_PAR_DT0IN_DT0IN (0x0300)
#define GPIO_PAR_DT3OUT(x) (((x)&0x03)<<6)
#define GPIO_PAR_DT3OUT_MASK (0x00C0)
#define GPIO_PAR_DT3OUT_QSPICS3 (0x0040)
#define GPIO_PAR_DT3OUT_U2RTS (0x0080)
#define GPIO_PAR_DT3OUT_DT3OUT (0x00C0)
#define GPIO_PAR_DT2OUT(x) (((x)&0x03)<<4)
#define GPIO_PAR_DT2OUT_MASK (0x0030)
#define GPIO_PAR_DT2OUT_DACK2 (0x0020)
#define GPIO_PAR_DT2OUT_DT2OUT (0x0030)
#define GPIO_PAR_DT1OUT(x) (((x)&0x03)<<2)
#define GPIO_PAR_DT1OUT_MASK (0x000C)
#define GPIO_PAR_DT1OUT_DACK1 (0x0008)
#define GPIO_PAR_DT1OUT_DT1OUT (0x000C)
#define GPIO_PAR_DT0OUT(x) ((x)&0x03)
#define GPIO_PAR_DT0OUT_MASK (0x0003)
#define GPIO_PAR_DT0OUT_DACK0 (0x0002)
#define GPIO_PAR_DT0OUT_DT0OUT (0x0003)
#define GPIO_PAR_ETPU_TCRCLK (0x04)
#define GPIO_PAR_ETPU_UTPU_ODIS (0x02)
#define GPIO_PAR_ETPU_LTPU_ODIS (0x01)
/* Bit definitions and macros for GPIO_DSCR */
#define GPIO_DSCR_EIM_EIM1 (0x10)
#define GPIO_DSCR_EIM_EIM0 (0x01)
#define GPIO_DSCR_ETPU_ETPU31_24 (0x40)
#define GPIO_DSCR_ETPU_ETPU23_16 (0x10)
#define GPIO_DSCR_ETPU_ETPU15_8 (0x04)
#define GPIO_DSCR_ETPU_ETPU7_0 (0x01)
#define GPIO_DSCR_FECI2C_FEC (0x10)
#define GPIO_DSCR_FECI2C_I2C (0x01)
#define GPIO_DSCR_UART_IRQ (0x40)
#define GPIO_DSCR_UART_UART2 (0x10)
#define GPIO_DSCR_UART_UART1 (0x04)
#define GPIO_DSCR_UART_UART0 (0x01)
#define GPIO_DSCR_QSPI_QSPI (0x01)
#define GPIO_DSCR_TIMER (0x01)
/*********************************************************************
* Chip Configuration Module (CCM)
*********************************************************************/
/* Bit definitions and macros for CCM_RCR */
#define CCM_RCR_SOFTRST (0x80)
#define CCM_RCR_FRCRSTOUT (0x40)
/* Bit definitions and macros for CCM_RSR */
#define CCM_RSR_SOFT (0x20)
#define CCM_RSR_WDR (0x10)
#define CCM_RSR_POR (0x08)
#define CCM_RSR_EXT (0x04)
#define CCM_RSR_LOC (0x02)
#define CCM_RSR_LOL (0x01)
/* Bit definitions and macros for CCM_CCR */
#define CCM_CCR_LOAD (0x8000)
#define CCM_CCR_SZEN (0x0040)
#define CCM_CCR_PSTEN (0x0020)
#define CCM_CCR_BME (0x0008)
#define CCM_CCR_BMT(x) ((x)&0x07)
#define CCM_CCR_BMT_MASK (0x0007)
#define CCM_CCR_BMT_64K (0x0000)
#define CCM_CCR_BMT_32K (0x0001)
#define CCM_CCR_BMT_16K (0x0002)
#define CCM_CCR_BMT_8K (0x0003)
#define CCM_CCR_BMT_4K (0x0004)
#define CCM_CCR_BMT_2K (0x0005)
#define CCM_CCR_BMT_1K (0x0006)
#define CCM_CCR_BMT_512 (0x0007)
/* Bit definitions and macros for CCM_RCON */
#define CCM_RCON_RCSC(x) (((x)&0x0003)<<8)
#define CCM_RCON_RLOAD (0x0020)
#define CCM_RCON_BOOTPS(x) (((x)&0x0003)<<3)
#define CCM_RCON_BOOTPS_MASK (0x0018)
#define CCM_RCON_BOOTPS_32 (0x0018)
#define CCM_RCON_BOOTPS_16 (0x0008)
#define CCM_RCON_BOOTPS_8 (0x0010)
#define CCM_RCON_MODE (0x0001)
/* Bit definitions and macros for CCM_CIR */
#define CCM_CIR_PIN(x) (((x)&0x03FF)<<6)
#define CCM_CIR_PRN(x) ((x)&0x003F)
/*********************************************************************
* PLL Clock Module
*********************************************************************/
/* Bit definitions and macros for PLL_SYNCR */
#define PLL_SYNCR_MFD(x) (((x)&0x07)<<24)
#define PLL_SYNCR_MFD_MASK (0x07000000)
#define PLL_SYNCR_RFC(x) (((x)&0x07)<<19)
#define PLL_SYNCR_RFC_MASK (0x00380000)
#define PLL_SYNCR_LOCEN (0x00040000)
#define PLL_SYNCR_LOLRE (0x00020000)
#define PLL_SYNCR_LOCRE (0x00010000)
#define PLL_SYNCR_DISCLK (0x00008000)
#define PLL_SYNCR_LOLIRQ (0x00004000)
#define PLL_SYNCR_LOCIRQ (0x00002000)
#define PLL_SYNCR_RATE (0x00001000)
#define PLL_SYNCR_DEPTH(x) (((x)&0x03)<<10)
#define PLL_SYNCR_EXP(x) ((x)&0x03FF)
/* Bit definitions and macros for PLL_SYNSR */
#define PLL_SYNSR_LOLF (0x00000200)
#define PLL_SYNSR_LOC (0x00000100)
#define PLL_SYNSR_MODE (0x00000080)
#define PLL_SYNSR_PLLSEL (0x00000040)
#define PLL_SYNSR_PLLREF (0x00000020)
#define PLL_SYNSR_LOCKS (0x00000010)
#define PLL_SYNSR_LOCK (0x00000008)
#define PLL_SYNSR_LOCF (0x00000004)
#define PLL_SYNSR_CALDONE (0x00000002)
#define PLL_SYNSR_CALPASS (0x00000001)
/*********************************************************************
* Edge Port
*********************************************************************/
#define EPORT_EPPAR_EPPA7(x) (((x)&0x03)<<14)
#define EPORT_EPPAR_EPPA6(x) (((x)&0x03)<<12)
#define EPORT_EPPAR_EPPA5(x) (((x)&0x03)<<10)
#define EPORT_EPPAR_EPPA4(x) (((x)&0x03)<<8)
#define EPORT_EPPAR_EPPA3(x) (((x)&0x03)<<6)
#define EPORT_EPPAR_EPPA2(x) (((x)&0x03)<<4)
#define EPORT_EPPAR_EPPA1(x) (((x)&0x03)<<2)
#define EPORT_EPDDR_EPDD7(x) EPORT_EPPAR_EPPA7(x)
#define EPORT_EPDDR_EPDD6(x) EPORT_EPPAR_EPPA6(x)
#define EPORT_EPDDR_EPDD5(x) EPORT_EPPAR_EPPA5(x)
#define EPORT_EPDDR_EPDD4(x) EPORT_EPPAR_EPPA4(x)
#define EPORT_EPDDR_EPDD3(x) EPORT_EPPAR_EPPA3(x)
#define EPORT_EPDDR_EPDD2(x) EPORT_EPPAR_EPPA2(x)
#define EPORT_EPDDR_EPDD1(x) EPORT_EPPAR_EPPA1(x)
#define EPORT_EPIER_EPIE7 (0x80)
#define EPORT_EPIER_EPIE6 (0x40)
#define EPORT_EPIER_EPIE5 (0x20)
#define EPORT_EPIER_EPIE4 (0x10)
#define EPORT_EPIER_EPIE3 (0x08)
#define EPORT_EPIER_EPIE2 (0x04)
#define EPORT_EPIER_EPIE1 (0x02)
#define EPORT_EPDR_EPDR7 EPORT_EPIER_EPIE7
#define EPORT_EPDR_EPDR6 EPORT_EPIER_EPIE6
#define EPORT_EPDR_EPDR5 EPORT_EPIER_EPIE5
#define EPORT_EPDR_EPDR4 EPORT_EPIER_EPIE4
#define EPORT_EPDR_EPDR3 EPORT_EPIER_EPIE3
#define EPORT_EPDR_EPDR2 EPORT_EPIER_EPIE2
#define EPORT_EPDR_EPDR1 EPORT_EPIER_EPIE1
#define EPORT_EPPDR_EPPDR7 EPORT_EPIER_EPIE7
#define EPORT_EPPDR_EPPDR6 EPORT_EPIER_EPIE6
#define EPORT_EPPDR_EPPDR5 EPORT_EPIER_EPIE5
#define EPORT_EPPDR_EPPDR4 EPORT_EPIER_EPIE4
#define EPORT_EPPDR_EPPDR3 EPORT_EPIER_EPIE3
#define EPORT_EPPDR_EPPDR2 EPORT_EPIER_EPIE2
#define EPORT_EPPDR_EPPDR1 EPORT_EPIER_EPIE1
/*********************************************************************
* Watchdog Timer Modules (WTM)
*********************************************************************/
/* Bit definitions and macros for WTM_WCR */
#define WTM_WCR_WAIT (0x0008)
#define WTM_WCR_DOZE (0x0004)
#define WTM_WCR_HALTED (0x0002)
#define WTM_WCR_EN (0x0001)
/*********************************************************************
* FlexCAN Module (CAN)
*********************************************************************/
/* Bit definitions and macros for CAN_CANMCR */
#define CANMCR_MDIS (0x80000000)
#define CANMCR_FRZ (0x40000000)
#define CANMCR_HALT (0x10000000)
#define CANMCR_NORDY (0x08000000)
#define CANMCR_SOFTRST (0x02000000)
#define CANMCR_FRZACK (0x01000000)
#define CANMCR_SUPV (0x00800000)
#define CANMCR_LPMACK (0x00100000)
#define CANMCR_MAXMB(x) (((x)&0x0F))
/* Bit definitions and macros for CAN_CANCTRL */
#define CANCTRL_PRESDIV(x) (((x)&0xFF)<<24)
#define CANCTRL_RJW(x) (((x)&0x03)<<22)
#define CANCTRL_PSEG1(x) (((x)&0x07)<<19)
#define CANCTRL_PSEG2(x) (((x)&0x07)<<16)
#define CANCTRL_BOFFMSK (0x00008000)
#define CANCTRL_ERRMSK (0x00004000)
#define CANCTRL_CLKSRC (0x00002000)
#define CANCTRL_LPB (0x00001000)
#define CANCTRL_SMP (0x00000080)
#define CANCTRL_BOFFREC (0x00000040)
#define CANCTRL_TSYNC (0x00000020)
#define CANCTRL_LBUF (0x00000010)
#define CANCTRL_LOM (0x00000008)
#define CANCTRL_PROPSEG(x) (((x)&0x07))
/* Bit definitions and macros for CAN_TIMER */
#define TIMER_TIMER(x) ((x)&0xFFFF)
/* Bit definitions and macros for CAN_RXGMASK */
#define RXGMASK_MI(x) ((x)&0x1FFFFFFF)
/* Bit definitions and macros for CAN_ERRCNT */
#define ERRCNT_TXECTR(x) (((x)&0xFF))
#define ERRCNT_RXECTR(x) (((x)&0xFF)<<8)
/* Bit definitions and macros for CAN_ERRSTAT */
#define ERRSTAT_BITERR1 (0x00008000)
#define ERRSTAT_BITERR0 (0x00004000)
#define ERRSTAT_ACKERR (0x00002000)
#define ERRSTAT_CRCERR (0x00001000)
#define ERRSTAT_FRMERR (0x00000800)
#define ERRSTAT_STFERR (0x00000400)
#define ERRSTAT_TXWRN (0x00000200)
#define ERRSTAT_RXWRN (0x00000100)
#define ERRSTAT_IDLE (0x00000080)
#define ERRSTAT_TXRX (0x00000040)
#define ERRSTAT_FLT_BUSOFF (0x00000020)
#define ERRSTAT_FLT_PASSIVE (0x00000010)
#define ERRSTAT_FLT_ACTIVE (0x00000000)
#define ERRSTAT_BOFFINT (0x00000004)
#define ERRSTAT_ERRINT (0x00000002)
/* Bit definitions and macros for CAN_IMASK */
#define IMASK_BUF15M (0x00008000)
#define IMASK_BUF14M (0x00004000)
#define IMASK_BUF13M (0x00002000)
#define IMASK_BUF12M (0x00001000)
#define IMASK_BUF11M (0x00000800)
#define IMASK_BUF10M (0x00000400)
#define IMASK_BUF9M (0x00000200)
#define IMASK_BUF8M (0x00000100)
#define IMASK_BUF7M (0x00000080)
#define IMASK_BUF6M (0x00000040)
#define IMASK_BUF5M (0x00000020)
#define IMASK_BUF4M (0x00000010)
#define IMASK_BUF3M (0x00000008)
#define IMASK_BUF2M (0x00000004)
#define IMASK_BUF1M (0x00000002)
#define IMASK_BUF0M (0x00000001)
/* Bit definitions and macros for CAN_IFLAG */
#define IFLAG_BUF15I (0x00008000)
#define IFLAG_BUF14I (0x00004000)
#define IFLAG_BUF13I (0x00002000)
#define IFLAG_BUF12I (0x00001000)
#define IFLAG_BUF11I (0x00000800)
#define IFLAG_BUF10I (0x00000400)
#define IFLAG_BUF9I (0x00000200)
#define IFLAG_BUF8I (0x00000100)
#define IFLAG_BUF7I (0x00000080)
#define IFLAG_BUF6I (0x00000040)
#define IFLAG_BUF5I (0x00000020)
#define IFLAG_BUF4I (0x00000010)
#define IFLAG_BUF3I (0x00000008)
#define IFLAG_BUF2I (0x00000004)
#define IFLAG_BUF1I (0x00000002)
#define IFLAG_BUF0I (0x00000001)
#endif /* mcf5235_h */

183
include/asm-m68k/m5249.h
View File

@@ -24,7 +24,6 @@
* MA 02111-1307 USA
*/
#ifndef mcf5249_h
#define mcf5249_h
/****************************************************************************/
@@ -32,22 +31,21 @@
/*
* useful definitions for reading/writing MBAR offset memory
*/
#define mbar_readLong(x) *((volatile unsigned long *) (CFG_MBAR + x))
#define mbar_writeLong(x,y) *((volatile unsigned long *) (CFG_MBAR + x)) = y
#define mbar_writeShort(x,y) *((volatile unsigned short *) (CFG_MBAR + x)) = y
#define mbar_writeByte(x,y) *((volatile unsigned char *) (CFG_MBAR + x)) = y
#define mbar2_readLong(x) *((volatile unsigned long *) (CFG_MBAR2 + x))
#define mbar2_writeLong(x,y) *((volatile unsigned long *) (CFG_MBAR2 + x)) = y
#define mbar2_writeShort(x,y) *((volatile unsigned short *) (CFG_MBAR2 + x)) = y
#define mbar2_writeByte(x,y) *((volatile unsigned char *) (CFG_MBAR2 + x)) = y
#define mbar_readLong(x) *((volatile unsigned long *) (CFG_MBAR + x))
#define mbar_writeLong(x,y) *((volatile unsigned long *) (CFG_MBAR + x)) = y
#define mbar_writeShort(x,y) *((volatile unsigned short *) (CFG_MBAR + x)) = y
#define mbar_writeByte(x,y) *((volatile unsigned char *) (CFG_MBAR + x)) = y
#define mbar2_readLong(x) *((volatile unsigned long *) (CFG_MBAR2 + x))
#define mbar2_writeLong(x,y) *((volatile unsigned long *) (CFG_MBAR2 + x)) = y
#define mbar2_writeShort(x,y) *((volatile unsigned short *) (CFG_MBAR2 + x)) = y
#define mbar2_writeByte(x,y) *((volatile unsigned char *) (CFG_MBAR2 + x)) = y
/*
* Size of internal RAM
*/
#define INT_RAM_SIZE 32768 /* RAMBAR0 - 32k */
#define INT_RAM_SIZE2 65536 /* RAMBAR1 - 64k */
#define INT_RAM_SIZE 32768 /* RAMBAR0 - 32k */
#define INT_RAM_SIZE2 65536 /* RAMBAR1 - 64k */
/*
* Define the 5249 SIM register set addresses.
@@ -56,51 +54,47 @@
/*****************
***** MBAR1 *****
*****************/
#define MCFSIM_RSR 0x00 /* Reset Status reg (r/w) */
#define MCFSIM_SYPCR 0x01 /* System Protection reg (r/w)*/
#define MCFSIM_SWIVR 0x02 /* SW Watchdog intr reg (r/w) */
#define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */
#define MCFSIM_MPARK 0x0c /* Bus master park register (r/w) */
#define MCFSIM_RSR 0x00 /* Reset Status reg (r/w) */
#define MCFSIM_SYPCR 0x01 /* System Protection reg (r/w) */
#define MCFSIM_SWIVR 0x02 /* SW Watchdog intr reg (r/w) */
#define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */
#define MCFSIM_MPARK 0x0c /* Bus master park register (r/w) */
#define MCFSIM_SIMR 0x00 /* SIM Config reg (r/w) */
#define MCFSIM_ICR0 0x4c /* Intr Ctrl reg 0 (r/w) */
#define MCFSIM_ICR1 0x4d /* Intr Ctrl reg 1 (r/w) */
#define MCFSIM_ICR2 0x4e /* Intr Ctrl reg 2 (r/w) */
#define MCFSIM_ICR3 0x4f /* Intr Ctrl reg 3 (r/w) */
#define MCFSIM_ICR4 0x50 /* Intr Ctrl reg 4 (r/w) */
#define MCFSIM_ICR5 0x51 /* Intr Ctrl reg 5 (r/w) */
#define MCFSIM_ICR6 0x52 /* Intr Ctrl reg 6 (r/w) */
#define MCFSIM_ICR7 0x53 /* Intr Ctrl reg 7 (r/w) */
#define MCFSIM_ICR8 0x54 /* Intr Ctrl reg 8 (r/w) */
#define MCFSIM_ICR9 0x55 /* Intr Ctrl reg 9 (r/w) */
#define MCFSIM_ICR10 0x56 /* Intr Ctrl reg 10 (r/w) */
#define MCFSIM_ICR11 0x57 /* Intr Ctrl reg 11 (r/w) */
#define MCFSIM_SIMR 0x00 /* SIM Config reg (r/w) */
#define MCFSIM_ICR0 0x4c /* Intr Ctrl reg 0 (r/w) */
#define MCFSIM_ICR1 0x4d /* Intr Ctrl reg 1 (r/w) */
#define MCFSIM_ICR2 0x4e /* Intr Ctrl reg 2 (r/w) */
#define MCFSIM_ICR3 0x4f /* Intr Ctrl reg 3 (r/w) */
#define MCFSIM_ICR4 0x50 /* Intr Ctrl reg 4 (r/w) */
#define MCFSIM_ICR5 0x51 /* Intr Ctrl reg 5 (r/w) */
#define MCFSIM_ICR6 0x52 /* Intr Ctrl reg 6 (r/w) */
#define MCFSIM_ICR7 0x53 /* Intr Ctrl reg 7 (r/w) */
#define MCFSIM_ICR8 0x54 /* Intr Ctrl reg 8 (r/w) */
#define MCFSIM_ICR9 0x55 /* Intr Ctrl reg 9 (r/w) */
#define MCFSIM_ICR10 0x56 /* Intr Ctrl reg 10 (r/w) */
#define MCFSIM_ICR11 0x57 /* Intr Ctrl reg 11 (r/w) */
#define MCFSIM_IPR 0x40 /* Interrupt Pend reg (r/w) */
#define MCFSIM_IMR 0x44 /* Interrupt Mask reg (r/w) */
#define MCFSIM_IPR 0x40 /* Interrupt Pend reg (r/w) */
#define MCFSIM_IMR 0x44 /* Interrupt Mask reg (r/w) */
#define MCFSIM_CSAR0 0x80 /* CS 0 Address 0 reg (r/w) */
#define MCFSIM_CSMR0 0x84 /* CS 0 Mask 0 reg (r/w) */
#define MCFSIM_CSCR0 0x8a /* CS 0 Control reg (r/w) */
#define MCFSIM_CSAR1 0x8c /* CS 1 Address reg (r/w) */
#define MCFSIM_CSMR1 0x90 /* CS 1 Mask reg (r/w) */
#define MCFSIM_CSCR1 0x96 /* CS 1 Control reg (r/w) */
#define MCFSIM_CSAR2 0x98 /* CS 2 Address reg (r/w) */
#define MCFSIM_CSMR2 0x9c /* CS 2 Mask reg (r/w) */
#define MCFSIM_CSCR2 0xa2 /* CS 2 Control reg (r/w) */
#define MCFSIM_CSAR3 0xa4 /* CS 3 Address reg (r/w) */
#define MCFSIM_CSMR3 0xa8 /* CS 3 Mask reg (r/w) */
#define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */
#define MCFSIM_CSAR0 0x80 /* CS 0 Address 0 reg (r/w) */
#define MCFSIM_CSMR0 0x84 /* CS 0 Mask 0 reg (r/w) */
#define MCFSIM_CSCR0 0x8a /* CS 0 Control reg (r/w) */
#define MCFSIM_CSAR1 0x8c /* CS 1 Address reg (r/w) */
#define MCFSIM_CSMR1 0x90 /* CS 1 Mask reg (r/w) */
#define MCFSIM_CSCR1 0x96 /* CS 1 Control reg (r/w) */
#define MCFSIM_CSAR2 0x98 /* CS 2 Address reg (r/w) */
#define MCFSIM_CSMR2 0x9c /* CS 2 Mask reg (r/w) */
#define MCFSIM_CSCR2 0xa2 /* CS 2 Control reg (r/w) */
#define MCFSIM_CSAR3 0xa4 /* CS 3 Address reg (r/w) */
#define MCFSIM_CSMR3 0xa8 /* CS 3 Mask reg (r/w) */
#define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */
#define MCFSIM_DCR 0x100 /* DRAM Control reg (r/w) */
#define MCFSIM_DACR0 0x108 /* DRAM 0 Addr and Ctrl (r/w) */
#define MCFSIM_DMR0 0x10c /* DRAM 0 Mask reg (r/w) */
#define MCFSIM_DACR1 0x110 /* DRAM 1 Addr and Ctrl (r/w) */
#define MCFSIM_DMR1 0x114 /* DRAM 1 Mask reg (r/w) */
/** UART Bases **/
#define MCFUART_BASE1 0x1c0 /* Base address of UART1 */
#define MCFUART_BASE2 0x200 /* Base address of UART2 */
#define MCFSIM_DCR 0x100 /* DRAM Control reg (r/w) */
#define MCFSIM_DACR0 0x108 /* DRAM 0 Addr and Ctrl (r/w) */
#define MCFSIM_DMR0 0x10c /* DRAM 0 Mask reg (r/w) */
#define MCFSIM_DACR1 0x110 /* DRAM 1 Addr and Ctrl (r/w) */
#define MCFSIM_DMR1 0x114 /* DRAM 1 Mask reg (r/w) */
/*****************
***** MBAR2 *****
@@ -109,39 +103,39 @@
/* GPIO Addresses
* Note: These are offset from MBAR2!
*/
#define MCFSIM_GPIO_READ 0x00 /* Read-Only access to gpio 0-31 (MBAR2) (r) */
#define MCFSIM_GPIO_OUT 0x04 /* Output register for gpio 0-31 (MBAR2) (r/w)*/
#define MCFSIM_GPIO_EN 0x08 /* gpio 0-31 enable (r/w)*/
#define MCFSIM_GPIO_FUNC 0x0c /* gpio 0-31 function select (r/w) */
#define MCFSIM_GPIO1_READ 0xb0 /* Read-Only access to gpio 32-63 (MBAR2) (r) */
#define MCFSIM_GPIO1_OUT 0xb4 /* Output register for gpio 32-63 (MBAR2) (r/w) */
#define MCFSIM_GPIO1_EN 0xb8 /* gpio 32-63 enable (r/w) */
#define MCFSIM_GPIO1_FUNC 0xbc /* gpio 32-63 function select (r/w) */
#define MCFSIM_GPIO_READ 0x00 /* Read-Only access to gpio 0-31 (MBAR2) (r) */
#define MCFSIM_GPIO_OUT 0x04 /* Output register for gpio 0-31 (MBAR2) (r/w) */
#define MCFSIM_GPIO_EN 0x08 /* gpio 0-31 enable (r/w) */
#define MCFSIM_GPIO_FUNC 0x0c /* gpio 0-31 function select (r/w) */
#define MCFSIM_GPIO1_READ 0xb0 /* Read-Only access to gpio 32-63 (MBAR2) (r) */
#define MCFSIM_GPIO1_OUT 0xb4 /* Output register for gpio 32-63 (MBAR2) (r/w) */
#define MCFSIM_GPIO1_EN 0xb8 /* gpio 32-63 enable (r/w) */
#define MCFSIM_GPIO1_FUNC 0xbc /* gpio 32-63 function select (r/w) */
#define MCFSIM_GPIO_INT_STAT 0xc0 /* Secondary Interrupt status (r) */
#define MCFSIM_GPIO_INT_CLEAR 0xc0 /* Secondary Interrupt status (w) */
#define MCFSIM_GPIO_INT_EN 0xc4 /* Secondary Interrupt status (r/w) */
#define MCFSIM_GPIO_INT_STAT 0xc0 /* Secondary Interrupt status (r) */
#define MCFSIM_GPIO_INT_CLEAR 0xc0 /* Secondary Interrupt status (w) */
#define MCFSIM_GPIO_INT_EN 0xc4 /* Secondary Interrupt status (r/w) */
#define MCFSIM_INT_STAT3 0xe0 /* 3rd Interrupt ctrl status (r) */
#define MCFSIM_INT_CLEAR3 0xe0 /* 3rd Interrupt ctrl clear (w) */
#define MCFSIM_INT_EN3 0xe4 /* 3rd Interrupt ctrl enable (r/w) */
#define MCFSIM_INT_STAT3 0xe0 /* 3rd Interrupt ctrl status (r) */
#define MCFSIM_INT_CLEAR3 0xe0 /* 3rd Interrupt ctrl clear (w) */
#define MCFSIM_INT_EN3 0xe4 /* 3rd Interrupt ctrl enable (r/w) */
#define MCFSIM_INTLEV1 0x140 /* Interrupts 0 - 7 (r/w) */
#define MCFSIM_INTLEV2 0x144 /* Interrupts 8 -15 (r/w) */
#define MCFSIM_INTLEV3 0x148 /* Interrupts 16-23 (r/w) */
#define MCFSIM_INTLEV4 0x14c /* Interrupts 24-31 (r/w) */
#define MCFSIM_INTLEV5 0x150 /* Interrupts 32-39 (r/w) */
#define MCFSIM_INTLEV6 0x154 /* Interrupts 40-47 (r/w) */
#define MCFSIM_INTLEV7 0x158 /* Interrupts 48-55 (r/w) */
#define MCFSIM_INTLEV8 0x15c /* Interrupts 56-63 (r/w) */
#define MCFSIM_INTLEV1 0x140 /* Interrupts 0 - 7 (r/w) */
#define MCFSIM_INTLEV2 0x144 /* Interrupts 8 -15 (r/w) */
#define MCFSIM_INTLEV3 0x148 /* Interrupts 16-23 (r/w) */
#define MCFSIM_INTLEV4 0x14c /* Interrupts 24-31 (r/w) */
#define MCFSIM_INTLEV5 0x150 /* Interrupts 32-39 (r/w) */
#define MCFSIM_INTLEV6 0x154 /* Interrupts 40-47 (r/w) */
#define MCFSIM_INTLEV7 0x158 /* Interrupts 48-55 (r/w) */
#define MCFSIM_INTLEV8 0x15c /* Interrupts 56-63 (r/w) */
#define MCFSIM_SPURVEC 0x167 /* Spurious Vector Register (r/w) */
#define MCFSIM_INTBASE 0x16b /* Software interrupt base address (r/w) */
#define MCFSIM_SPURVEC 0x167 /* Spurious Vector Register (r/w) */
#define MCFSIM_INTBASE 0x16b /* Software interrupt base address (r/w) */
#define MCFSIM_IDECONFIG1 0x18c /* IDE config register 1 (r/w) */
#define MCFSIM_IDECONFIG2 0x190 /* IDE config register 1 (r/w) */
#define MCFSIM_IDECONFIG1 0x18c /* IDE config register 1 (r/w) */
#define MCFSIM_IDECONFIG2 0x190 /* IDE config register 1 (r/w) */
#define MCFSIM_PLLCR 0x180 /* PLL Control register */
#define MCFSIM_PLLCR 0x180 /* PLL Control register */
/*
* Some symbol defines for the above...
@@ -158,21 +152,20 @@
/*
* Bit definitions for the ICR family of registers.
*/
#define MCFSIM_ICR_AUTOVEC 0x80 /* Auto-vectored intr */
#define MCFSIM_ICR_LEVEL0 0x00 /* Level 0 intr */
#define MCFSIM_ICR_LEVEL1 0x04 /* Level 1 intr */
#define MCFSIM_ICR_LEVEL2 0x08 /* Level 2 intr */
#define MCFSIM_ICR_LEVEL3 0x0c /* Level 3 intr */
#define MCFSIM_ICR_LEVEL4 0x10 /* Level 4 intr */
#define MCFSIM_ICR_LEVEL5 0x14 /* Level 5 intr */
#define MCFSIM_ICR_LEVEL6 0x18 /* Level 6 intr */
#define MCFSIM_ICR_LEVEL7 0x1c /* Level 7 intr */
#define MCFSIM_ICR_PRI0 0x00 /* Priority 0 intr */
#define MCFSIM_ICR_PRI1 0x01 /* Priority 1 intr */
#define MCFSIM_ICR_PRI2 0x02 /* Priority 2 intr */
#define MCFSIM_ICR_PRI3 0x03 /* Priority 3 intr */
#define MCFSIM_ICR_AUTOVEC 0x80 /* Auto-vectored intr */
#define MCFSIM_ICR_LEVEL0 0x00 /* Level 0 intr */
#define MCFSIM_ICR_LEVEL1 0x04 /* Level 1 intr */
#define MCFSIM_ICR_LEVEL2 0x08 /* Level 2 intr */
#define MCFSIM_ICR_LEVEL3 0x0c /* Level 3 intr */
#define MCFSIM_ICR_LEVEL4 0x10 /* Level 4 intr */
#define MCFSIM_ICR_LEVEL5 0x14 /* Level 5 intr */
#define MCFSIM_ICR_LEVEL6 0x18 /* Level 6 intr */
#define MCFSIM_ICR_LEVEL7 0x1c /* Level 7 intr */
#define MCFSIM_ICR_PRI0 0x00 /* Priority 0 intr */
#define MCFSIM_ICR_PRI1 0x01 /* Priority 1 intr */
#define MCFSIM_ICR_PRI2 0x02 /* Priority 2 intr */
#define MCFSIM_ICR_PRI3 0x03 /* Priority 3 intr */
/*
* Macros to read/set IMR register. It is 32 bits on the 5249.
@@ -184,4 +177,4 @@
#define mcf_setimr(imr) \
*((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR)) = (imr);
#endif /* mcf5249_h */
#endif /* mcf5249_h */

73
include/asm-m68k/m5253.h Normal file
View File

@@ -0,0 +1,73 @@
/*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef m5253_h
#define m5253_h
/****************************************************************************/
/*
* PLL Module (PLL)
*/
/* Register read/write macros */
#define PLL_PLLCR (0x000180)
#define SIM_RSR (0x000000)
#define SIM_SYPCR (0x000001)
#define SIM_SWIVR (0x000002)
#define SIM_SWSR (0x000003)
#define SIM_MPARK (0x00000C)
/* Bit definitions and macros for RSR */
#define SIM_RSR_SWTR (0x20)
#define SIM_RSR_HRST (0x80)
/* Register read/write macros */
#define CIM_MISCCR (0x000500)
#define CIM_ATA_DADDR (0x000504)
#define CIM_ATA_DCOUNT (0x000508)
#define CIM_RTC_TIME (0x00050C)
#define CIM_USB_CANCLK (0x000510)
/* Bit definitions and macros for MISCCR */
#define CIM_MISCCR_ADTA (0x00000001)
#define CIM_MISCCR_ADTD (0x00000002)
#define CIM_MISCCR_ADIE (0x00000004)
#define CIM_MISCCR_ADIC (0x00000008)
#define CIM_MISCCR_ADIP (0x00000010)
#define CIM_MISCCR_CPUEND (0x00000020)
#define CIM_MISCCR_DMAEND (0x00000040)
#define CIM_MISCCR_RTCCLR (0x00000080)
#define CIM_MISCCR_RTCPL (0x00000100)
#define CIM_MISCCR_URIE (0x00000800)
#define CIM_MISCCR_URIC (0x00001000)
#define CIM_MISCCR_URIP (0x00002000)
/* Bit definitions and macros for ATA_DADDR */
#define CIM_ATA_DADDR_ATAADDR(x) (((x)&0x00003FFF)<<2)
#define CIM_ATA_DADDR_RAMADDR(x) (((x)&0x00003FFF)<<18)
/* Bit definitions and macros for ATA_DCOUNT */
#define CIM_ATA_DCOUNT_COUNT(x) (((x)&0x0000FFFF))
#endif /* m5253_h */

105
include/asm-m68k/m5271.h
View File

@@ -25,7 +25,6 @@
* MA 02111-1307 USA
*/
#ifndef _MCF5271_H_
#define _MCF5271_H_
@@ -91,7 +90,7 @@
#define MCF_GPIO_PAR_UART_U1RXD_UART1 0x0C00
#define MCF_GPIO_PAR_UART_U1TXD_UART1 0x0300
#define MCF_GPIO_PAR_SDRAM_PAR_CSSDCS(x) (((x)&0x03)<<6)
#define MCF_GPIO_PAR_SDRAM_PAR_CSSDCS(x) (((x)&0x03)<<6)
#define MCF_SDRAMC_DCR 0x000040
#define MCF_SDRAMC_DACR0 0x000048
@@ -117,4 +116,104 @@
#define MCFSIM_ICR1 0x000C41
#endif /* _MCF5271_H_ */
/*********************************************************************
* Interrupt Controller (INTC)
*********************************************************************/
#define INT0_LO_RSVD0 (0)
#define INT0_LO_EPORT1 (1)
#define INT0_LO_EPORT2 (2)
#define INT0_LO_EPORT3 (3)
#define INT0_LO_EPORT4 (4)
#define INT0_LO_EPORT5 (5)
#define INT0_LO_EPORT6 (6)
#define INT0_LO_EPORT7 (7)
#define INT0_LO_SCM (8)
#define INT0_LO_DMA0 (9)
#define INT0_LO_DMA1 (10)
#define INT0_LO_DMA2 (11)
#define INT0_LO_DMA3 (12)
#define INT0_LO_UART0 (13)
#define INT0_LO_UART1 (14)
#define INT0_LO_UART2 (15)
#define INT0_LO_RSVD1 (16)
#define INT0_LO_I2C (17)
#define INT0_LO_QSPI (18)
#define INT0_LO_DTMR0 (19)
#define INT0_LO_DTMR1 (20)
#define INT0_LO_DTMR2 (21)
#define INT0_LO_DTMR3 (22)
#define INT0_LO_FEC_TXF (23)
#define INT0_LO_FEC_TXB (24)
#define INT0_LO_FEC_UN (25)
#define INT0_LO_FEC_RL (26)
#define INT0_LO_FEC_RXF (27)
#define INT0_LO_FEC_RXB (28)
#define INT0_LO_FEC_MII (29)
#define INT0_LO_FEC_LC (30)
#define INT0_LO_FEC_HBERR (31)
#define INT0_HI_FEC_GRA (32)
#define INT0_HI_FEC_EBERR (33)
#define INT0_HI_FEC_BABT (34)
#define INT0_HI_FEC_BABR (35)
#define INT0_HI_PIT0 (36)
#define INT0_HI_PIT1 (37)
#define INT0_HI_PIT2 (38)
#define INT0_HI_PIT3 (39)
#define INT0_HI_RNG (40)
#define INT0_HI_SKHA (41)
#define INT0_HI_MDHA (42)
#define INT0_HI_CAN1_BUF0I (43)
#define INT0_HI_CAN1_BUF1I (44)
#define INT0_HI_CAN1_BUF2I (45)
#define INT0_HI_CAN1_BUF3I (46)
#define INT0_HI_CAN1_BUF4I (47)
#define INT0_HI_CAN1_BUF5I (48)
#define INT0_HI_CAN1_BUF6I (49)
#define INT0_HI_CAN1_BUF7I (50)
#define INT0_HI_CAN1_BUF8I (51)
#define INT0_HI_CAN1_BUF9I (52)
#define INT0_HI_CAN1_BUF10I (53)
#define INT0_HI_CAN1_BUF11I (54)
#define INT0_HI_CAN1_BUF12I (55)
#define INT0_HI_CAN1_BUF13I (56)
#define INT0_HI_CAN1_BUF14I (57)
#define INT0_HI_CAN1_BUF15I (58)
#define INT0_HI_CAN1_ERRINT (59)
#define INT0_HI_CAN1_BOFFINT (60)
/* 60-63 Reserved */
/* Bit definitions and macros for INTC_IPRL */
#define INTC_IPRL_INT31 (0x80000000)
#define INTC_IPRL_INT30 (0x40000000)
#define INTC_IPRL_INT29 (0x20000000)
#define INTC_IPRL_INT28 (0x10000000)
#define INTC_IPRL_INT27 (0x08000000)
#define INTC_IPRL_INT26 (0x04000000)
#define INTC_IPRL_INT25 (0x02000000)
#define INTC_IPRL_INT24 (0x01000000)
#define INTC_IPRL_INT23 (0x00800000)
#define INTC_IPRL_INT22 (0x00400000)
#define INTC_IPRL_INT21 (0x00200000)
#define INTC_IPRL_INT20 (0x00100000)
#define INTC_IPRL_INT19 (0x00080000)
#define INTC_IPRL_INT18 (0x00040000)
#define INTC_IPRL_INT17 (0x00020000)
#define INTC_IPRL_INT16 (0x00010000)
#define INTC_IPRL_INT15 (0x00008000)
#define INTC_IPRL_INT14 (0x00004000)
#define INTC_IPRL_INT13 (0x00002000)
#define INTC_IPRL_INT12 (0x00001000)
#define INTC_IPRL_INT11 (0x00000800)
#define INTC_IPRL_INT10 (0x00000400)
#define INTC_IPRL_INT9 (0x00000200)
#define INTC_IPRL_INT8 (0x00000100)
#define INTC_IPRL_INT7 (0x00000080)
#define INTC_IPRL_INT6 (0x00000040)
#define INTC_IPRL_INT5 (0x00000020)
#define INTC_IPRL_INT4 (0x00000010)
#define INTC_IPRL_INT3 (0x00000008)
#define INTC_IPRL_INT2 (0x00000004)
#define INTC_IPRL_INT1 (0x00000002)
#define INTC_IPRL_INT0 (0x00000001)
#endif /* _MCF5271_H_ */

221
include/asm-m68k/m5272.h
View File

@@ -24,7 +24,6 @@
* MA 02111-1307 USA
*/
#ifndef mcf5272_h
#define mcf5272_h
/****************************************************************************/
@@ -35,65 +34,173 @@
#define INT_RAM_SIZE 4096
#define GPIO_PACNT_PA15MSK (0xC0000000)
#define GPIO_PACNT_DGNT1 (0x40000000)
#define GPIO_PACNT_PA14MSK (0x30000000)
#define GPIO_PACNT_DREQ1 (0x10000000)
#define GPIO_PACNT_PA13MSK (0x0C000000)
#define GPIO_PACNT_DFSC3 (0x04000000)
#define GPIO_PACNT_PA12MSK (0x03000000)
#define GPIO_PACNT_DFSC2 (0x01000000)
#define GPIO_PACNT_PA11MSK (0x00C00000)
#define GPIO_PACNT_QSPI_CS1 (0x00800000)
#define GPIO_PACNT_PA10MSK (0x00300000)
#define GPIO_PACNT_DREQ0 (0x00100000)
#define GPIO_PACNT_PA9MSK (0x000C0000)
#define GPIO_PACNT_DGNT0 (0x00040000)
#define GPIO_PACNT_PA8MSK (0x00030000)
#define GPIO_PACNT_FSC0 (0x00010000)
#define GPIO_PACNT_FSR0 (0x00010000)
#define GPIO_PACNT_PA7MSK (0x0000C000)
#define GPIO_PACNT_DOUT3 (0x00008000)
#define GPIO_PACNT_QSPI_CS3 (0x00004000)
#define GPIO_PACNT_PA6MSK (0x00003000)
#define GPIO_PACNT_USB_RXD (0x00001000)
#define GPIO_PACNT_PA5MSK (0x00000C00)
#define GPIO_PACNT_USB_TXEN (0x00000400)
#define GPIO_PACNT_PA4MSK (0x00000300)
#define GPIO_PACNT_USB_SUSP (0x00000100)
#define GPIO_PACNT_PA3MSK (0x000000C0)
#define GPIO_PACNT_USB_TN (0x00000040)
#define GPIO_PACNT_PA2MSK (0x00000030)
#define GPIO_PACNT_USB_RN (0x00000010)
#define GPIO_PACNT_PA1MSK (0x0000000C)
#define GPIO_PACNT_USB_RP (0x00000004)
#define GPIO_PACNT_PA0MSK (0x00000003)
#define GPIO_PACNT_USB_TP (0x00000001)
/*
* Define the 5272 SIM register set addresses.
*/
#define MCFSIM_SCR 0x04 /* SIM Config reg (r/w) */
#define MCFSIM_SPR 0x06 /* System Protection reg (r/w)*/
#define MCFSIM_PMR 0x08 /* Power Management reg (r/w) */
#define MCFSIM_APMR 0x0e /* Active Low Power reg (r/w) */
#define MCFSIM_DIR 0x10 /* Device Identity reg (r/w) */
#define GPIO_PBCNT_PB15MSK (0xC0000000)
#define GPIO_PBCNT_E_MDC (0x40000000)
#define GPIO_PBCNT_PB14MSK (0x30000000)
#define GPIO_PBCNT_E_RXER (0x10000000)
#define GPIO_PBCNT_PB13MSK (0x0C000000)
#define GPIO_PBCNT_E_RXD1 (0x04000000)
#define GPIO_PBCNT_PB12MSK (0x03000000)
#define GPIO_PBCNT_E_RXD2 (0x01000000)
#define GPIO_PBCNT_PB11MSK (0x00C00000)
#define GPIO_PBCNT_E_RXD3 (0x00400000)
#define GPIO_PBCNT_PB10MSK (0x00300000)
#define GPIO_PBCNT_E_TXD1 (0x00100000)
#define GPIO_PBCNT_PB9MSK (0x000C0000)
#define GPIO_PBCNT_E_TXD2 (0x00040000)
#define GPIO_PBCNT_PB8MSK (0x00030000)
#define GPIO_PBCNT_E_TXD3 (0x00010000)
#define GPIO_PBCNT_PB7MSK (0x0000C000)
#define GPIO_PBCNT_TOUT0 (0x00004000)
#define GPIO_PBCNT_PB6MSK (0x00003000)
#define GPIO_PBCNT_TA (0x00001000)
#define GPIO_PBCNT_PB4MSK (0x00000300)
#define GPIO_PBCNT_URT0_CLK (0x00000100)
#define GPIO_PBCNT_PB3MSK (0x000000C0)
#define GPIO_PBCNT_URT0_RTS (0x00000040)
#define GPIO_PBCNT_PB2MSK (0x00000030)
#define GPIO_PBCNT_URT0_CTS (0x00000010)
#define GPIO_PBCNT_PB1MSK (0x0000000C)
#define GPIO_PBCNT_URT0_RXD (0x00000004)
#define GPIO_PBCNT_URT0_TIN2 (0x00000004)
#define GPIO_PBCNT_PB0MSK (0x00000003)
#define GPIO_PBCNT_URT0_TXD (0x00000001)
#define MCFSIM_ICR1 0x20 /* Intr Ctrl reg 1 (r/w) */
#define MCFSIM_ICR2 0x24 /* Intr Ctrl reg 2 (r/w) */
#define MCFSIM_ICR3 0x28 /* Intr Ctrl reg 3 (r/w) */
#define MCFSIM_ICR4 0x2c /* Intr Ctrl reg 4 (r/w) */
#define GPIO_PDCNT_PD7MSK (0x0000C000)
#define GPIO_PDCNT_TIN1 (0x00008000)
#define GPIO_PDCNT_PWM_OUT2 (0x00004000)
#define GPIO_PDCNT_PD6MSK (0x00003000)
#define GPIO_PDCNT_TOUT1 (0x00002000)
#define GPIO_PDCNT_PWM_OUT1 (0x00001000)
#define GPIO_PDCNT_PD5MSK (0x00000C00)
#define GPIO_PDCNT_INT4 (0x00000C00)
#define GPIO_PDCNT_DIN3 (0x00000800)
#define GPIO_PDCNT_PD4MSK (0x00000300)
#define GPIO_PDCNT_URT1_TXD (0x00000200)
#define GPIO_PDCNT_DOUT0 (0x00000100)
#define GPIO_PDCNT_PD3MSK (0x000000C0)
#define GPIO_PDCNT_INT5 (0x000000C0)
#define GPIO_PDCNT_URT1_RTS (0x00000080)
#define GPIO_PDCNT_PD2MSK (0x00000030)
#define GPIO_PDCNT_QSPI_CS2 (0x00000030)
#define GPIO_PDCNT_URT1_CTS (0x00000020)
#define GPIO_PDCNT_PD1MSK (0x0000000C)
#define GPIO_PDCNT_URT1_RXD (0x00000008)
#define GPIO_PDCNT_URT1_TIN3 (0x00000008)
#define GPIO_PDCNT_DIN0 (0x00000004)
#define GPIO_PDCNT_PD0MSK (0x00000003)
#define GPIO_PDCNT_URT1_CLK (0x00000002)
#define GPIO_PDCNT_DCL0 (0x00000001)
#define MCFSIM_ISR 0x30 /* Interrupt Source reg (r/w) */
#define MCFSIM_PITR 0x34 /* Interrupt Transition (r/w) */
#define MCFSIM_PIWR 0x38 /* Interrupt Wakeup reg (r/w) */
#define MCFSIM_PIVR 0x3f /* Interrupt Vector reg (r/w( */
#define INT_RSVD0 (0)
#define INT_INT1 (1)
#define INT_INT2 (2)
#define INT_INT3 (3)
#define INT_INT4 (4)
#define INT_TMR0 (5)
#define INT_TMR1 (6)
#define INT_TMR2 (7)
#define INT_TMR3 (8)
#define INT_UART1 (9)
#define INT_UART2 (10)
#define INT_PLIP (11)
#define INT_PLIA (12)
#define INT_USB0 (13)
#define INT_USB1 (14)
#define INT_USB2 (15)
#define INT_USB3 (16)
#define INT_USB4 (17)
#define INT_USB5 (18)
#define INT_USB6 (19)
#define INT_USB7 (20)
#define INT_DMA (21)
#define INT_ERX (22)
#define INT_ETX (23)
#define INT_ENTC (24)
#define INT_QSPI (25)
#define INT_INT5 (26)
#define INT_INT6 (27)
#define INT_SWTO (28)
#define MCFSIM_WRRR 0x280 /* Watchdog reference (r/w) */
#define MCFSIM_WIRR 0x284 /* Watchdog interrupt (r/w) */
#define MCFSIM_WCR 0x288 /* Watchdog counter (r/w) */
#define MCFSIM_WER 0x28c /* Watchdog event (r/w) */
#define INT_ICR1_TMR0MASK (0x000F000)
#define INT_ICR1_TMR0PI (0x0008000)
#define INT_ICR1_TMR0IPL(x) (((x)&0x7)<<12)
#define INT_ICR1_TMR1MASK (0x0000F00)
#define INT_ICR1_TMR1PI (0x0000800)
#define INT_ICR1_TMR1IPL(x) (((x)&0x7)<<8)
#define INT_ICR1_TMR2MASK (0x00000F0)
#define INT_ICR1_TMR2PI (0x0000080)
#define INT_ICR1_TMR2IPL(x) (((x)&0x7)<<4)
#define INT_ICR1_TMR3MASK (0x000000F)
#define INT_ICR1_TMR3PI (0x0000008)
#define INT_ICR1_TMR3IPL(x) (((x)&0x7))
#define MCFSIM_CSBR0 0x40 /* CS0 Base Address (r/w) */
#define MCFSIM_CSOR0 0x44 /* CS0 Option (r/w) */
#define MCFSIM_CSBR1 0x48 /* CS1 Base Address (r/w) */
#define MCFSIM_CSOR1 0x4c /* CS1 Option (r/w) */
#define MCFSIM_CSBR2 0x50 /* CS2 Base Address (r/w) */
#define MCFSIM_CSOR2 0x54 /* CS2 Option (r/w) */
#define MCFSIM_CSBR3 0x58 /* CS3 Base Address (r/w) */
#define MCFSIM_CSOR3 0x5c /* CS3 Option (r/w) */
#define MCFSIM_CSBR4 0x60 /* CS4 Base Address (r/w) */
#define MCFSIM_CSOR4 0x64 /* CS4 Option (r/w) */
#define MCFSIM_CSBR5 0x68 /* CS5 Base Address (r/w) */
#define MCFSIM_CSOR5 0x6c /* CS5 Option (r/w) */
#define MCFSIM_CSBR6 0x70 /* CS6 Base Address (r/w) */
#define MCFSIM_CSOR6 0x74 /* CS6 Option (r/w) */
#define MCFSIM_CSBR7 0x78 /* CS7 Base Address (r/w) */
#define MCFSIM_CSOR7 0x7c /* CS7 Option (r/w) */
#define INT_ISR_INT31 (0x80000000)
#define INT_ISR_INT30 (0x40000000)
#define INT_ISR_INT29 (0x20000000)
#define INT_ISR_INT28 (0x10000000)
#define INT_ISR_INT27 (0x08000000)
#define INT_ISR_INT26 (0x04000000)
#define INT_ISR_INT25 (0x02000000)
#define INT_ISR_INT24 (0x01000000)
#define INT_ISR_INT23 (0x00800000)
#define INT_ISR_INT22 (0x00400000)
#define INT_ISR_INT21 (0x00200000)
#define INT_ISR_INT20 (0x00100000)
#define INT_ISR_INT19 (0x00080000)
#define INT_ISR_INT18 (0x00040000)
#define INT_ISR_INT17 (0x00020000)
#define INT_ISR_INT16 (0x00010000)
#define INT_ISR_INT15 (0x00008000)
#define INT_ISR_INT14 (0x00004000)
#define INT_ISR_INT13 (0x00002000)
#define INT_ISR_INT12 (0x00001000)
#define INT_ISR_INT11 (0x00000800)
#define INT_ISR_INT10 (0x00000400)
#define INT_ISR_INT9 (0x00000200)
#define INT_ISR_INT8 (0x00000100)
#define INT_ISR_INT7 (0x00000080)
#define INT_ISR_INT6 (0x00000040)
#define INT_ISR_INT5 (0x00000020)
#define INT_ISR_INT4 (0x00000010)
#define INT_ISR_INT3 (0x00000008)
#define INT_ISR_INT2 (0x00000004)
#define INT_ISR_INT1 (0x00000002)
#define INT_ISR_INT0 (0x00000001)
#define MCFSIM_SDCR 0x180 /* SDRAM Configuration (r/w) */
#define MCFSIM_SDTR 0x184 /* SDRAM Timing (r/w) */
#define MCFSIM_DCAR0 0x4c /* DRAM 0 Address reg(r/w) */
#define MCFSIM_DCMR0 0x50 /* DRAM 0 Mask reg (r/w) */
#define MCFSIM_DCCR0 0x57 /* DRAM 0 Control reg (r/w) */
#define MCFSIM_DCAR1 0x58 /* DRAM 1 Address reg (r/w) */
#define MCFSIM_DCMR1 0x5c /* DRAM 1 Mask reg (r/w) */
#define MCFSIM_DCCR1 0x63 /* DRAM 1 Control reg (r/w) */
#define MCFSIM_PACNT 0x80 /* Port A Control (r/w) */
#define MCFSIM_PADDR 0x84 /* Port A Direction (r/w) */
#define MCFSIM_PADAT 0x86 /* Port A Data (r/w) */
#define MCFSIM_PBCNT 0x88 /* Port B Control (r/w) */
#define MCFSIM_PBDDR 0x8c /* Port B Direction (r/w) */
#define MCFSIM_PBDAT 0x8e /* Port B Data (r/w) */
#define MCFSIM_PCDDR 0x94 /* Port C Direction (r/w) */
#define MCFSIM_PCDAT 0x96 /* Port C Data (r/w) */
#define MCFSIM_PDCNT 0x98 /* Port D Control (r/w) */
#endif /* mcf5272_h */
#endif /* mcf5272_h */

262
include/asm-m68k/m5282.h
View File

@@ -23,7 +23,99 @@
/****************************************************************************/
#ifndef m5282_h
#define m5282_h
/****************************************************************************/
/*********************************************************************
* PLL Clock Module
*********************************************************************/
/* Bit definitions and macros for PLL_SYNCR */
#define PLL_SYNCR_LOLRE (0x8000)
#define PLL_SYNCR_MFD2 (0x4000)
#define PLL_SYNCR_MFD1 (0x2000)
#define PLL_SYNCR_MFD0 (0x1000)
#define PLL_SYNCR_LOCRE (0x0800)
#define PLL_SYNCR_RFC2 (0x0400)
#define PLL_SYNCR_RFC1 (0x0200)
#define PLL_SYNCR_RFC0 (0x0100)
#define PLL_SYNCR_LOCEN (0x0080)
#define PLL_SYNCR_DISCLK (0x0040)
#define PLL_SYNCR_FWKUP (0x0020)
#define PLL_SYNCR_STPMD1 (0x0008)
#define PLL_SYNCR_STPMD0 (0x0004)
/* Bit definitions and macros for PLL_SYNSR */
#define PLL_SYNSR_MODE (0x0080)
#define PLL_SYNSR_PLLSEL (0x0040)
#define PLL_SYNSR_PLLREF (0x0020)
#define PLL_SYNSR_LOCKS (0x0010)
#define PLL_SYNSR_LOCK (0x0008)
#define PLL_SYNSR_LOCS (0x0004)
/*********************************************************************
* Interrupt Controller (INTC)
*********************************************************************/
#define INT0_LO_RSVD0 (0)
#define INT0_LO_EPORT1 (1)
#define INT0_LO_EPORT2 (2)
#define INT0_LO_EPORT3 (3)
#define INT0_LO_EPORT4 (4)
#define INT0_LO_EPORT5 (5)
#define INT0_LO_EPORT6 (6)
#define INT0_LO_EPORT7 (7)
#define INT0_LO_SCM_SWT1 (8)
#define INT0_LO_DMA_00 (9)
#define INT0_LO_DMA_01 (10)
#define INT0_LO_DMA_02 (11)
#define INT0_LO_DMA_03 (12)
#define INT0_LO_UART0 (13)
#define INT0_LO_UART1 (14)
#define INT0_LO_UART2 (15)
#define INT0_LO_RSVD1 (16)
#define INT0_LO_I2C (17)
#define INT0_LO_QSPI (18)
#define INT0_LO_DTMR0 (19)
#define INT0_LO_DTMR1 (20)
#define INT0_LO_DTMR2 (21)
#define INT0_LO_DTMR3 (22)
#define INT0_LO_FEC_TXF (23)
#define INT0_LO_FEC_TXB (24)
#define INT0_LO_FEC_UN (25)
#define INT0_LO_FEC_RL (26)
#define INT0_LO_FEC_RXF (27)
#define INT0_LO_FEC_RXB (28)
#define INT0_LO_FEC_MII (29)
#define INT0_LO_FEC_LC (30)
#define INT0_LO_FEC_HBERR (31)
#define INT0_HI_FEC_GRA (32)
#define INT0_HI_FEC_EBERR (33)
#define INT0_HI_FEC_BABT (34)
#define INT0_HI_FEC_BABR (35)
#define INT0_HI_PMM_LVDF (36)
#define INT0_HI_QADC_CF1 (37)
#define INT0_HI_QADC_CF2 (38)
#define INT0_HI_QADC_PF1 (39)
#define INT0_HI_QADC_PF2 (40)
#define INT0_HI_GPTA_TOF (41)
#define INT0_HI_GPTA_PAIF (42)
#define INT0_HI_GPTA_PAOVF (43)
#define INT0_HI_GPTA_C0F (44)
#define INT0_HI_GPTA_C1F (45)
#define INT0_HI_GPTA_C2F (46)
#define INT0_HI_GPTA_C3F (47)
#define INT0_HI_GPTB_TOF (48)
#define INT0_HI_GPTB_PAIF (49)
#define INT0_HI_GPTB_PAOVF (50)
#define INT0_HI_GPTB_C0F (51)
#define INT0_HI_GPTB_C1F (52)
#define INT0_HI_GPTB_C2F (53)
#define INT0_HI_GPTB_C3F (54)
#define INT0_HI_PIT0 (55)
#define INT0_HI_PIT1 (56)
#define INT0_HI_PIT2 (57)
#define INT0_HI_PIT3 (58)
#define INT0_HI_CFM_CBEIF (59)
#define INT0_HI_CFM_CCIF (60)
#define INT0_HI_CFM_PVIF (61)
#define INT0_HI_CFM_AEIF (62)
/*
* Size of internal RAM
@@ -96,49 +188,49 @@
#define MCFGPIO_SETD (*(vu_char *) (CFG_MBAR+0x10002B))
#define MCFGPIO_SETE (*(vu_char *) (CFG_MBAR+0x10002C))
#define MCFGPIO_SETF (*(vu_char *) (CFG_MBAR+0x10002D))
#define MCFGPIO_SETG (*(vu_char *) (CFG_MBAR+0x10002E))
#define MCFGPIO_SETH (*(vu_char *) (CFG_MBAR+0x10002F))
#define MCFGPIO_SETJ (*(vu_char *) (CFG_MBAR+0x100030))
#define MCFGPIO_SETDD (*(vu_char *) (CFG_MBAR+0x100031))
#define MCFGPIO_SETEH (*(vu_char *) (CFG_MBAR+0x100032))
#define MCFGPIO_SETEL (*(vu_char *) (CFG_MBAR+0x100033))
#define MCFGPIO_SETAS (*(vu_char *) (CFG_MBAR+0x100034))
#define MCFGPIO_SETQS (*(vu_char *) (CFG_MBAR+0x100035))
#define MCFGPIO_SETSD (*(vu_char *) (CFG_MBAR+0x100036))
#define MCFGPIO_SETTC (*(vu_char *) (CFG_MBAR+0x100037))
#define MCFGPIO_SETTD (*(vu_char *) (CFG_MBAR+0x100038))
#define MCFGPIO_SETUA (*(vu_char *) (CFG_MBAR+0x100039))
#define MCFGPIO_SETG (*(vu_char *) (CFG_MBAR+0x10002E))
#define MCFGPIO_SETH (*(vu_char *) (CFG_MBAR+0x10002F))
#define MCFGPIO_SETJ (*(vu_char *) (CFG_MBAR+0x100030))
#define MCFGPIO_SETDD (*(vu_char *) (CFG_MBAR+0x100031))
#define MCFGPIO_SETEH (*(vu_char *) (CFG_MBAR+0x100032))
#define MCFGPIO_SETEL (*(vu_char *) (CFG_MBAR+0x100033))
#define MCFGPIO_SETAS (*(vu_char *) (CFG_MBAR+0x100034))
#define MCFGPIO_SETQS (*(vu_char *) (CFG_MBAR+0x100035))
#define MCFGPIO_SETSD (*(vu_char *) (CFG_MBAR+0x100036))
#define MCFGPIO_SETTC (*(vu_char *) (CFG_MBAR+0x100037))
#define MCFGPIO_SETTD (*(vu_char *) (CFG_MBAR+0x100038))
#define MCFGPIO_SETUA (*(vu_char *) (CFG_MBAR+0x100039))
#define MCFGPIO_CLRA (*(vu_char *) (CFG_MBAR+0x10003C))
#define MCFGPIO_CLRB (*(vu_char *) (CFG_MBAR+0x10003D))
#define MCFGPIO_CLRC (*(vu_char *) (CFG_MBAR+0x10003E))
#define MCFGPIO_CLRD (*(vu_char *) (CFG_MBAR+0x10003F))
#define MCFGPIO_CLRE (*(vu_char *) (CFG_MBAR+0x100040))
#define MCFGPIO_CLRF (*(vu_char *) (CFG_MBAR+0x100041))
#define MCFGPIO_CLRG (*(vu_char *) (CFG_MBAR+0x100042))
#define MCFGPIO_CLRH (*(vu_char *) (CFG_MBAR+0x100043))
#define MCFGPIO_CLRJ (*(vu_char *) (CFG_MBAR+0x100044))
#define MCFGPIO_CLRDD (*(vu_char *) (CFG_MBAR+0x100045))
#define MCFGPIO_CLREH (*(vu_char *) (CFG_MBAR+0x100046))
#define MCFGPIO_CLREL (*(vu_char *) (CFG_MBAR+0x100047))
#define MCFGPIO_CLRAS (*(vu_char *) (CFG_MBAR+0x100048))
#define MCFGPIO_CLRQS (*(vu_char *) (CFG_MBAR+0x100049))
#define MCFGPIO_CLRSD (*(vu_char *) (CFG_MBAR+0x10004A))
#define MCFGPIO_CLRTC (*(vu_char *) (CFG_MBAR+0x10004B))
#define MCFGPIO_CLRTD (*(vu_char *) (CFG_MBAR+0x10004C))
#define MCFGPIO_CLRUA (*(vu_char *) (CFG_MBAR+0x10004D))
#define MCFGPIO_CLRA (*(vu_char *) (CFG_MBAR+0x10003C))
#define MCFGPIO_CLRB (*(vu_char *) (CFG_MBAR+0x10003D))
#define MCFGPIO_CLRC (*(vu_char *) (CFG_MBAR+0x10003E))
#define MCFGPIO_CLRD (*(vu_char *) (CFG_MBAR+0x10003F))
#define MCFGPIO_CLRE (*(vu_char *) (CFG_MBAR+0x100040))
#define MCFGPIO_CLRF (*(vu_char *) (CFG_MBAR+0x100041))
#define MCFGPIO_CLRG (*(vu_char *) (CFG_MBAR+0x100042))
#define MCFGPIO_CLRH (*(vu_char *) (CFG_MBAR+0x100043))
#define MCFGPIO_CLRJ (*(vu_char *) (CFG_MBAR+0x100044))
#define MCFGPIO_CLRDD (*(vu_char *) (CFG_MBAR+0x100045))
#define MCFGPIO_CLREH (*(vu_char *) (CFG_MBAR+0x100046))
#define MCFGPIO_CLREL (*(vu_char *) (CFG_MBAR+0x100047))
#define MCFGPIO_CLRAS (*(vu_char *) (CFG_MBAR+0x100048))
#define MCFGPIO_CLRQS (*(vu_char *) (CFG_MBAR+0x100049))
#define MCFGPIO_CLRSD (*(vu_char *) (CFG_MBAR+0x10004A))
#define MCFGPIO_CLRTC (*(vu_char *) (CFG_MBAR+0x10004B))
#define MCFGPIO_CLRTD (*(vu_char *) (CFG_MBAR+0x10004C))
#define MCFGPIO_CLRUA (*(vu_char *) (CFG_MBAR+0x10004D))
#define MCFGPIO_PBCDPAR (*(vu_char *) (CFG_MBAR+0x100050))
#define MCFGPIO_PFPAR (*(vu_char *) (CFG_MBAR+0x100051))
#define MCFGPIO_PEPAR (*(vu_short *)(CFG_MBAR+0x100052))
#define MCFGPIO_PJPAR (*(vu_char *) (CFG_MBAR+0x100054))
#define MCFGPIO_PSDPAR (*(vu_char *) (CFG_MBAR+0x100055))
#define MCFGPIO_PASPAR (*(vu_short *)(CFG_MBAR+0x100056))
#define MCFGPIO_PEHLPAR (*(vu_char *) (CFG_MBAR+0x100058))
#define MCFGPIO_PQSPAR (*(vu_char *) (CFG_MBAR+0x100059))
#define MCFGPIO_PTCPAR (*(vu_char *) (CFG_MBAR+0x10005A))
#define MCFGPIO_PTDPAR (*(vu_char *) (CFG_MBAR+0x10005B))
#define MCFGPIO_PUAPAR (*(vu_char *) (CFG_MBAR+0x10005C))
#define MCFGPIO_PBCDPAR (*(vu_char *) (CFG_MBAR+0x100050))
#define MCFGPIO_PFPAR (*(vu_char *) (CFG_MBAR+0x100051))
#define MCFGPIO_PEPAR (*(vu_short *)(CFG_MBAR+0x100052))
#define MCFGPIO_PJPAR (*(vu_char *) (CFG_MBAR+0x100054))
#define MCFGPIO_PSDPAR (*(vu_char *) (CFG_MBAR+0x100055))
#define MCFGPIO_PASPAR (*(vu_short *)(CFG_MBAR+0x100056))
#define MCFGPIO_PEHLPAR (*(vu_char *) (CFG_MBAR+0x100058))
#define MCFGPIO_PQSPAR (*(vu_char *) (CFG_MBAR+0x100059))
#define MCFGPIO_PTCPAR (*(vu_char *) (CFG_MBAR+0x10005A))
#define MCFGPIO_PTDPAR (*(vu_char *) (CFG_MBAR+0x10005B))
#define MCFGPIO_PUAPAR (*(vu_char *) (CFG_MBAR+0x10005C))
/* Bit level definitions and macros */
#define MCFGPIO_PORT7 (0x80)
@@ -171,7 +263,6 @@
#define MCFGPIO_Px0 (0x01)
#define MCFGPIO_Px(x) (0x01<<x)
#define MCFGPIO_PBCDPAR_PBPA (0x80)
#define MCFGPIO_PBCDPAR_PCDPA (0x40)
@@ -236,7 +327,7 @@
/* System Conrol Module SCM */
#define MCFSCM_RAMBAR (*(vu_long *) (CFG_MBAR+0x00000008))
#define MCFSCM_RAMBAR (*(vu_long *) (CFG_MBAR+0x00000008))
#define MCFSCM_CRSR (*(vu_char *) (CFG_MBAR+0x00000010))
#define MCFSCM_CWCR (*(vu_char *) (CFG_MBAR+0x00000011))
#define MCFSCM_LPICR (*(vu_char *) (CFG_MBAR+0x00000012))
@@ -256,34 +347,33 @@
#define MCFSCM_GPACR0 (*(vu_char *) (CFG_MBAR+0x00000030))
#define MCFSCM_GPACR1 (*(vu_char *) (CFG_MBAR+0x00000031))
#define MCFSCM_CRSR_EXT (0x80)
#define MCFSCM_CRSR_CWDR (0x20)
#define MCFSCM_RAMBAR_BA(x) ((x)&0xFFFF0000)
#define MCFSCM_RAMBAR_BDE (0x00000200)
#define MCFSCM_RAMBAR_BA(x) ((x)&0xFFFF0000)
#define MCFSCM_RAMBAR_BDE (0x00000200)
/* Reset Controller Module RCM */
#define MCFRESET_RCR (*(vu_char *) (CFG_MBAR+0x00110000))
#define MCFRESET_RSR (*(vu_char *) (CFG_MBAR+0x00110001))
#define MCFRESET_RCR_SOFTRST (0x80)
#define MCFRESET_RCR_FRCRSTOUT (0x40)
#define MCFRESET_RCR_LVDF (0x10)
#define MCFRESET_RCR_LVDIE (0x08)
#define MCFRESET_RCR_LVDRE (0x04)
#define MCFRESET_RCR_LVDE (0x01)
#define MCFRESET_RCR_SOFTRST (0x80)
#define MCFRESET_RCR_FRCRSTOUT (0x40)
#define MCFRESET_RCR_LVDF (0x10)
#define MCFRESET_RCR_LVDIE (0x08)
#define MCFRESET_RCR_LVDRE (0x04)
#define MCFRESET_RCR_LVDE (0x01)
#define MCFRESET_RSR_LVD (0x40)
#define MCFRESET_RSR_SOFT (0x20)
#define MCFRESET_RSR_WDR (0x10)
#define MCFRESET_RSR_POR (0x08)
#define MCFRESET_RSR_EXT (0x04)
#define MCFRESET_RSR_LOC (0x02)
#define MCFRESET_RSR_LOL (0x01)
#define MCFRESET_RSR_ALL (0x7F)
#define MCFRESET_RCR_SOFTRST (0x80)
#define MCFRESET_RCR_FRCRSTOUT (0x40)
#define MCFRESET_RSR_LVD (0x40)
#define MCFRESET_RSR_SOFT (0x20)
#define MCFRESET_RSR_WDR (0x10)
#define MCFRESET_RSR_POR (0x08)
#define MCFRESET_RSR_EXT (0x04)
#define MCFRESET_RSR_LOC (0x02)
#define MCFRESET_RSR_LOL (0x01)
#define MCFRESET_RSR_ALL (0x7F)
#define MCFRESET_RCR_SOFTRST (0x80)
#define MCFRESET_RCR_FRCRSTOUT (0x40)
/* Chip Configuration Module CCM */
@@ -291,26 +381,25 @@
#define MCFCCM_RCON (*(vu_short *)(CFG_MBAR+0x00110008))
#define MCFCCM_CIR (*(vu_short *)(CFG_MBAR+0x0011000A))
/* Bit level definitions and macros */
#define MCFCCM_CCR_LOAD (0x8000)
#define MCFCCM_CCR_MODE(x) (((x)&0x0007)<<8)
#define MCFCCM_CCR_SZEN (0x0040)
#define MCFCCM_CCR_PSTEN (0x0020)
#define MCFCCM_CCR_SZEN (0x0040)
#define MCFCCM_CCR_PSTEN (0x0020)
#define MCFCCM_CCR_BME (0x0008)
#define MCFCCM_CCR_BMT(x) (((x)&0x0007))
#define MCFCCM_CCR_BMT(x) (((x)&0x0007))
#define MCFCCM_CIR_PIN_MASK (0xFF00)
#define MCFCCM_CIR_PRN_MASK (0x00FF)
/* Clock Module */
#define MCFCLOCK_SYNCR (*(vu_short *)(CFG_MBAR+0x120000))
#define MCFCLOCK_SYNSR (*(vu_char *) (CFG_MBAR+0x120002))
#define MCFCLOCK_SYNCR (*(vu_short *)(CFG_MBAR+0x120000))
#define MCFCLOCK_SYNSR (*(vu_char *) (CFG_MBAR+0x120002))
#define MCFCLOCK_SYNCR_MFD(x) (((x)&0x0007)<<12)
#define MCFCLOCK_SYNCR_RFD(x) (((x)&0x0007)<<8)
#define MCFCLOCK_SYNSR_LOCK 0x08
#define MCFCLOCK_SYNCR_MFD(x) (((x)&0x0007)<<12)
#define MCFCLOCK_SYNCR_RFD(x) (((x)&0x0007)<<8)
#define MCFCLOCK_SYNSR_LOCK 0x08
#define MCFSDRAMC_DCR (*(vu_short *)(CFG_MBAR+0x00000040))
#define MCFSDRAMC_DACR0 (*(vu_long *) (CFG_MBAR+0x00000048))
@@ -337,19 +426,19 @@
#define MCFSDRAMC_DACR_IMRS (0x00000040)
#define MCFSDRAMC_DMR_BAM_16M (0x00FC0000)
#define MCFSDRAMC_DMR_WP (0x00000100)
#define MCFSDRAMC_DMR_CI (0x00000040)
#define MCFSDRAMC_DMR_AM (0x00000020)
#define MCFSDRAMC_DMR_SC (0x00000010)
#define MCFSDRAMC_DMR_SD (0x00000008)
#define MCFSDRAMC_DMR_UC (0x00000004)
#define MCFSDRAMC_DMR_UD (0x00000002)
#define MCFSDRAMC_DMR_V (0x00000001)
#define MCFSDRAMC_DMR_WP (0x00000100)
#define MCFSDRAMC_DMR_CI (0x00000040)
#define MCFSDRAMC_DMR_AM (0x00000020)
#define MCFSDRAMC_DMR_SC (0x00000010)
#define MCFSDRAMC_DMR_SD (0x00000008)
#define MCFSDRAMC_DMR_UC (0x00000004)
#define MCFSDRAMC_DMR_UD (0x00000002)
#define MCFSDRAMC_DMR_V (0x00000001)
#define MCFWTM_WCR (*(vu_short *)(CFG_MBAR+0x00140000))
#define MCFWTM_WMR (*(vu_short *)(CFG_MBAR+0x00140002))
#define MCFWTM_WCNTR (*(vu_short *)(CFG_MBAR+0x00140004))
#define MCFWTM_WSR (*(vu_short *)(CFG_MBAR+0x00140006))
#define MCFWTM_WCR (*(vu_short *)(CFG_MBAR+0x00140000))
#define MCFWTM_WMR (*(vu_short *)(CFG_MBAR+0x00140002))
#define MCFWTM_WCNTR (*(vu_short *)(CFG_MBAR+0x00140004))
#define MCFWTM_WSR (*(vu_short *)(CFG_MBAR+0x00140006))
/* Chip SELECT Module CSM */
#define MCFCSM_CSAR0 (*(vu_short *)(CFG_MBAR+0x00000080))
@@ -375,9 +464,7 @@
#define MCFCSM_CSCR_PS_16 (0x0080)
/*********************************************************************
*
* General Purpose Timer (GPT) Module
*
*********************************************************************/
#define MCFGPTA_GPTIOS (*(vu_char *)(CFG_MBAR+0x1A0000))
@@ -403,7 +490,6 @@
#define MCFGPTA_GPTPORT (*(vu_char *)(CFG_MBAR+0x1A001D))
#define MCFGPTA_GPTDDR (*(vu_char *)(CFG_MBAR+0x1A001E))
#define MCFGPTB_GPTIOS (*(vu_char *)(CFG_MBAR+0x1B0000))
#define MCFGPTB_GPTCFORC (*(vu_char *)(CFG_MBAR+0x1B0001))
#define MCFGPTB_GPTOC3M (*(vu_char *)(CFG_MBAR+0x1B0002))
@@ -542,4 +628,4 @@
#define MCFCFM_CMD_MASERS 0x41
/****************************************************************************/
#endif /* m5282_h */
#endif /* m5282_h */

1658
include/asm-m68k/m5329.h Normal file
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1541
include/asm-m68k/m5445x.h Normal file
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File diff suppressed because it is too large Load Diff

113
include/asm-m68k/mcftimer.h
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@@ -1,113 +0,0 @@
/*
* mcftimer.h -- ColdFire internal TIMER support defines.
*
* Based on mcftimer.h of uCLinux distribution:
* (C) Copyright 1999-2002, Greg Ungerer (gerg@snapgear.com)
* (C) Copyright 2000, Lineo Inc. (www.lineo.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/****************************************************************************/
#ifndef mcftimer_h
#define mcftimer_h
/****************************************************************************/
#include <linux/config.h>
/*
* Get address specific defines for this ColdFire member.
*/
#if defined(CONFIG_M5204) || defined(CONFIG_M5206) || defined(CONFIG_M5206e)
#define MCFTIMER_BASE1 0x100 /* Base address of TIMER1 */
#define MCFTIMER_BASE2 0x120 /* Base address of TIMER2 */
#elif defined(CONFIG_M5272)
#define MCFTIMER_BASE1 0x200 /* Base address of TIMER1 */
#define MCFTIMER_BASE2 0x220 /* Base address of TIMER2 */
#define MCFTIMER_BASE3 0x240 /* Base address of TIMER4 */
#define MCFTIMER_BASE4 0x260 /* Base address of TIMER3 */
#elif defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407)
#define MCFTIMER_BASE1 0x140 /* Base address of TIMER1 */
#define MCFTIMER_BASE2 0x180 /* Base address of TIMER2 */
#elif defined(CONFIG_M5282) | defined(CONFIG_M5271)
#define MCFTIMER_BASE1 0x150000 /* Base address of TIMER1 */
#define MCFTIMER_BASE2 0x160000 /* Base address of TIMER2 */
#define MCFTIMER_BASE3 0x170000 /* Base address of TIMER4 */
#define MCFTIMER_BASE4 0x180000 /* Base address of TIMER3 */
#endif
/*
* Define the TIMER register set addresses.
*/
#define MCFTIMER_TMR 0x00 /* Timer Mode reg (r/w) */
#define MCFTIMER_TRR 0x02 /* Timer Reference (r/w) */
#define MCFTIMER_TCR 0x04 /* Timer Capture reg (r/w) */
#define MCFTIMER_TCN 0x06 /* Timer Counter reg (r/w) */
#define MCFTIMER_TER 0x11 /* Timer Event reg (r/w) */
/*
* Define the TIMER register set addresses for 5282.
*/
#define MCFTIMER_PCSR 0
#define MCFTIMER_PMR 1
#define MCFTIMER_PCNTR 2
/*
* Bit definitions for the Timer Mode Register (TMR).
* Register bit flags are common accross ColdFires.
*/
#define MCFTIMER_TMR_PREMASK 0xff00 /* Prescalar mask */
#define MCFTIMER_TMR_DISCE 0x0000 /* Disable capture */
#define MCFTIMER_TMR_ANYCE 0x00c0 /* Capture any edge */
#define MCFTIMER_TMR_FALLCE 0x0080 /* Capture fallingedge */
#define MCFTIMER_TMR_RISECE 0x0040 /* Capture rising edge */
#define MCFTIMER_TMR_ENOM 0x0020 /* Enable output toggle */
#define MCFTIMER_TMR_DISOM 0x0000 /* Do single output pulse */
#define MCFTIMER_TMR_ENORI 0x0010 /* Enable ref interrupt */
#define MCFTIMER_TMR_DISORI 0x0000 /* Disable ref interrupt */
#define MCFTIMER_TMR_RESTART 0x0008 /* Restart counter */
#define MCFTIMER_TMR_FREERUN 0x0000 /* Free running counter */
#define MCFTIMER_TMR_CLKTIN 0x0006 /* Input clock is TIN */
#define MCFTIMER_TMR_CLK16 0x0004 /* Input clock is /16 */
#define MCFTIMER_TMR_CLK1 0x0002 /* Input clock is /1 */
#define MCFTIMER_TMR_CLKSTOP 0x0000 /* Stop counter */
#define MCFTIMER_TMR_ENABLE 0x0001 /* Enable timer */
#define MCFTIMER_TMR_DISABLE 0x0000 /* Disable timer */
/*
* Bit definitions for the Timer Event Registers (TER).
*/
#define MCFTIMER_TER_CAP 0x01 /* Capture event */
#define MCFTIMER_TER_REF 0x02 /* Refernece event */
/*
* Bit definitions for the 5282 PIT Control and Status Register (PCSR).
*/
#define MCFTIMER_PCSR_EN 0x0001
#define MCFTIMER_PCSR_RLD 0x0002
#define MCFTIMER_PCSR_PIF 0x0004
#define MCFTIMER_PCSR_PIE 0x0008
#define MCFTIMER_PCSR_OVW 0x0010
#define MCFTIMER_PCSR_HALTED 0x0020
#define MCFTIMER_PCSR_DOZE 0x0040
/****************************************************************************/
#endif /* mcftimer_h */

221
include/asm-m68k/mcfuart.h
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@@ -1,221 +0,0 @@
/*
* mcfuart.h -- ColdFire internal UART support defines.
*
* File copied from mcfuart.h of uCLinux distribution:
* (C) Copyright 1999, Greg Ungerer (gerg@snapgear.com)
* (C) Copyright 2000, Lineo Inc. (www.lineo.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/****************************************************************************/
#ifndef mcfuart_h
#define mcfuart_h
/****************************************************************************/
#include <linux/config.h>
/*
* Define the base address of the UARTS within the MBAR address
* space.
*/
#if defined(CONFIG_M5272)
#define MCFUART_BASE1 0x100 /* Base address of UART1 */
#define MCFUART_BASE2 0x140 /* Base address of UART2 */
#elif defined(CONFIG_M5204) || defined(CONFIG_M5206) || defined(CONFIG_M5206e)
#if defined(CONFIG_NETtel)
#define MCFUART_BASE1 0x180 /* Base address of UART1 */
#define MCFUART_BASE2 0x140 /* Base address of UART2 */
#else
#define MCFUART_BASE1 0x140 /* Base address of UART1 */
#define MCFUART_BASE2 0x180 /* Base address of UART2 */
#endif
#elif defined(CONFIG_M5282) || defined(CONFIG_M5271)
#define MCFUART_BASE1 0x200 /* Base address of UART1 */
#define MCFUART_BASE2 0x240 /* Base address of UART2 */
#define MCFUART_BASE3 0x280 /* Base address of UART3 */
#elif defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407)
#if defined(CONFIG_NETtel) || defined(CONFIG_DISKtel) || defined(CONFIG_SECUREEDGEMP3)
#define MCFUART_BASE1 0x200 /* Base address of UART1 */
#define MCFUART_BASE2 0x1c0 /* Base address of UART2 */
#else
#define MCFUART_BASE1 0x1c0 /* Base address of UART1 */
#define MCFUART_BASE2 0x200 /* Base address of UART2 */
#endif
#endif
/*
* Define the ColdFire UART register set addresses.
*/
#define MCFUART_UMR 0x00 /* Mode register (r/w) */
#define MCFUART_USR 0x04 /* Status register (r) */
#define MCFUART_UCSR 0x04 /* Clock Select (w) */
#define MCFUART_UCR 0x08 /* Command register (w) */
#define MCFUART_URB 0x0c /* Receiver Buffer (r) */
#define MCFUART_UTB 0x0c /* Transmit Buffer (w) */
#define MCFUART_UIPCR 0x10 /* Input Port Change (r) */
#define MCFUART_UACR 0x10 /* Auxiliary Control (w) */
#define MCFUART_UISR 0x14 /* Interrup Status (r) */
#define MCFUART_UIMR 0x14 /* Interrupt Mask (w) */
#define MCFUART_UBG1 0x18 /* Baud Rate MSB (r/w) */
#define MCFUART_UBG2 0x1c /* Baud Rate LSB (r/w) */
#ifdef CONFIG_M5272
#define MCFUART_UTF 0x28 /* Transmitter FIFO (r/w) */
#define MCFUART_URF 0x2c /* Receiver FIFO (r/w) */
#define MCFUART_UFPD 0x30 /* Frac Prec. Divider (r/w) */
#else
#define MCFUART_UIVR 0x30 /* Interrupt Vector (r/w) */
#endif
#define MCFUART_UIPR 0x34 /* Input Port (r) */
#define MCFUART_UOP1 0x38 /* Output Port Bit Set (w) */
#define MCFUART_UOP0 0x3c /* Output Port Bit Reset (w) */
#ifdef CONFIG_M5249
/* Note: This isn't in the 5249 docs */
#define MCFUART_UFPD 0x30 /* Frac Prec. Divider (r/w) */
#endif
/*
* Define bit flags in Mode Register 1 (MR1).
*/
#define MCFUART_MR1_RXRTS 0x80 /* Auto RTS flow control */
#define MCFUART_MR1_RXIRQFULL 0x40 /* RX IRQ type FULL */
#define MCFUART_MR1_RXIRQRDY 0x00 /* RX IRQ type RDY */
#define MCFUART_MR1_RXERRBLOCK 0x20 /* RX block error mode */
#define MCFUART_MR1_RXERRCHAR 0x00 /* RX char error mode */
#define MCFUART_MR1_PARITYNONE 0x10 /* No parity */
#define MCFUART_MR1_PARITYEVEN 0x00 /* Even parity */
#define MCFUART_MR1_PARITYODD 0x04 /* Odd parity */
#define MCFUART_MR1_PARITYSPACE 0x08 /* Space parity */
#define MCFUART_MR1_PARITYMARK 0x0c /* Mark parity */
#define MCFUART_MR1_CS5 0x00 /* 5 bits per char */
#define MCFUART_MR1_CS6 0x01 /* 6 bits per char */
#define MCFUART_MR1_CS7 0x02 /* 7 bits per char */
#define MCFUART_MR1_CS8 0x03 /* 8 bits per char */
/*
* Define bit flags in Mode Register 2 (MR2).
*/
#define MCFUART_MR2_LOOPBACK 0x80 /* Loopback mode */
#define MCFUART_MR2_REMOTELOOP 0xc0 /* Remote loopback mode */
#define MCFUART_MR2_AUTOECHO 0x40 /* Automatic echo */
#define MCFUART_MR2_TXRTS 0x20 /* Assert RTS on TX */
#define MCFUART_MR2_TXCTS 0x10 /* Auto CTS flow control */
#define MCFUART_MR2_STOP1 0x07 /* 1 stop bit */
#define MCFUART_MR2_STOP15 0x08 /* 1.5 stop bits */
#define MCFUART_MR2_STOP2 0x0f /* 2 stop bits */
/*
* Define bit flags in Status Register (USR).
*/
#define MCFUART_USR_RXBREAK 0x80 /* Received BREAK */
#define MCFUART_USR_RXFRAMING 0x40 /* Received framing error */
#define MCFUART_USR_RXPARITY 0x20 /* Received parity error */
#define MCFUART_USR_RXOVERRUN 0x10 /* Received overrun error */
#define MCFUART_USR_TXEMPTY 0x08 /* Transmitter empty */
#define MCFUART_USR_TXREADY 0x04 /* Transmitter ready */
#define MCFUART_USR_RXFULL 0x02 /* Receiver full */
#define MCFUART_USR_RXREADY 0x01 /* Receiver ready */
#define MCFUART_USR_RXERR (MCFUART_USR_RXBREAK | MCFUART_USR_RXFRAMING | \
MCFUART_USR_RXPARITY | MCFUART_USR_RXOVERRUN)
/*
* Define bit flags in Clock Select Register (UCSR).
*/
#define MCFUART_UCSR_RXCLKTIMER 0xd0 /* RX clock is timer */
#define MCFUART_UCSR_RXCLKEXT16 0xe0 /* RX clock is external x16 */
#define MCFUART_UCSR_RXCLKEXT1 0xf0 /* RX clock is external x1 */
#define MCFUART_UCSR_TXCLKTIMER 0x0d /* TX clock is timer */
#define MCFUART_UCSR_TXCLKEXT16 0x0e /* TX clock is external x16 */
#define MCFUART_UCSR_TXCLKEXT1 0x0f /* TX clock is external x1 */
/*
* Define bit flags in Command Register (UCR).
*/
#define MCFUART_UCR_CMDNULL 0x00 /* No command */
#define MCFUART_UCR_CMDRESETMRPTR 0x10 /* Reset MR pointer */
#define MCFUART_UCR_CMDRESETRX 0x20 /* Reset receiver */
#define MCFUART_UCR_CMDRESETTX 0x30 /* Reset transmitter */
#define MCFUART_UCR_CMDRESETERR 0x40 /* Reset error status */
#define MCFUART_UCR_CMDRESETBREAK 0x50 /* Reset BREAK change */
#define MCFUART_UCR_CMDBREAKSTART 0x60 /* Start BREAK */
#define MCFUART_UCR_CMDBREAKSTOP 0x70 /* Stop BREAK */
#define MCFUART_UCR_TXNULL 0x00 /* No TX command */
#define MCFUART_UCR_TXENABLE 0x04 /* Enable TX */
#define MCFUART_UCR_TXDISABLE 0x08 /* Disable TX */
#define MCFUART_UCR_RXNULL 0x00 /* No RX command */
#define MCFUART_UCR_RXENABLE 0x01 /* Enable RX */
#define MCFUART_UCR_RXDISABLE 0x02 /* Disable RX */
/*
* Define bit flags in Input Port Change Register (UIPCR).
*/
#define MCFUART_UIPCR_CTSCOS 0x10 /* CTS change of state */
#define MCFUART_UIPCR_CTS 0x01 /* CTS value */
/*
* Define bit flags in Input Port Register (UIP).
*/
#define MCFUART_UIPR_CTS 0x01 /* CTS value */
/*
* Define bit flags in Output Port Registers (UOP).
* Clear bit by writing to UOP0, set by writing to UOP1.
*/
#define MCFUART_UOP_RTS 0x01 /* RTS set or clear */
/*
* Define bit flags in the Auxiliary Control Register (UACR).
*/
#define MCFUART_UACR_IEC 0x01 /* Input enable control */
/*
* Define bit flags in Interrupt Status Register (UISR).
* These same bits are used for the Interrupt Mask Register (UIMR).
*/
#define MCFUART_UIR_COS 0x80 /* Change of state (CTS) */
#define MCFUART_UIR_DELTABREAK 0x04 /* Break start or stop */
#define MCFUART_UIR_RXREADY 0x02 /* Receiver ready */
#define MCFUART_UIR_TXREADY 0x01 /* Transmitter ready */
#ifdef CONFIG_M5272
/*
* Define bit flags in the Transmitter FIFO Register (UTF).
*/
#define MCFUART_UTF_TXB 0x1f /* transmitter data level */
#define MCFUART_UTF_FULL 0x20 /* transmitter fifo full */
#define MCFUART_UTF_TXS 0xc0 /* transmitter status */
/*
* Define bit flags in the Receiver FIFO Register (URF).
*/
#define MCFUART_URF_RXB 0x1f /* receiver data level */
#define MCFUART_URF_FULL 0x20 /* receiver fifo full */
#define MCFUART_URF_RXS 0xc0 /* receiver status */
#endif
/****************************************************************************/
#endif /* mcfuart_h */

44
include/asm-m68k/ptrace.h
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@@ -28,32 +28,32 @@
#ifndef __ASSEMBLY__
struct pt_regs {
ulong d0;
ulong d1;
ulong d2;
ulong d3;
ulong d4;
ulong d5;
ulong d6;
ulong d7;
ulong a0;
ulong a1;
ulong a2;
ulong a3;
ulong a4;
ulong a5;
ulong a6;
#if defined(CONFIG_M5272) || defined(CONFIG_M5282) || defined(CONFIG_M5249) || defined(CONFIG_M5271)
unsigned format : 4; /* frame format specifier */
unsigned vector : 12; /* vector offset */
ulong d0;
ulong d1;
ulong d2;
ulong d3;
ulong d4;
ulong d5;
ulong d6;
ulong d7;
ulong a0;
ulong a1;
ulong a2;
ulong a3;
ulong a4;
ulong a5;
ulong a6;
#if defined(__M68K__)
unsigned format:4; /* frame format specifier */
unsigned vector:12; /* vector offset */
unsigned short sr;
unsigned long pc;
unsigned long pc;
#else
unsigned short sr;
unsigned long pc;
unsigned long pc;
#endif
};
#endif /* #ifndef __ASSEMBLY__ */
#endif /* #ifndef __ASSEMBLY__ */
#endif /* #ifndef _M68K_PTRACE_H */
#endif /* #ifndef _M68K_PTRACE_H */

109
include/asm-m68k/rtc.h Normal file
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@@ -0,0 +1,109 @@
/*
* RealTime Clock
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __MCFRTC_H__
#define __MCFRTC_H__
/* Real time Clock */
typedef struct rtc_ctrl {
u32 hourmin; /* 0x00 Hours and Minutes Counter Register */
u32 seconds; /* 0x04 Seconds Counter Register */
u32 alrm_hm; /* 0x08 Hours and Minutes Alarm Register */
u32 alrm_sec; /* 0x0C Seconds Alarm Register */
u32 cr; /* 0x10 Control Register */
u32 isr; /* 0x14 Interrupt Status Register */
u32 ier; /* 0x18 Interrupt Enable Register */
u32 stpwatch; /* 0x1C Stopwatch Minutes Register */
u32 days; /* 0x20 Days Counter Register */
u32 alrm_day; /* 0x24 Days Alarm Register */
void *extended;
} rtc_t;
/* Bit definitions and macros for HOURMIN */
#define RTC_HOURMIN_MINUTES(x) (((x)&0x0000003F))
#define RTC_HOURMIN_HOURS(x) (((x)&0x0000001F)<<8)
/* Bit definitions and macros for SECONDS */
#define RTC_SECONDS_SECONDS(x) (((x)&0x0000003F))
/* Bit definitions and macros for ALRM_HM */
#define RTC_ALRM_HM_MINUTES(x) (((x)&0x0000003F))
#define RTC_ALRM_HM_HOURS(x) (((x)&0x0000001F)<<8)
/* Bit definitions and macros for ALRM_SEC */
#define RTC_ALRM_SEC_SECONDS(x) (((x)&0x0000003F))
/* Bit definitions and macros for CR */
#define RTC_CR_SWR (0x00000001)
#define RTC_CR_XTL(x) (((x)&0x00000003)<<5)
#define RTC_CR_EN (0x00000080)
#define RTC_CR_32768 (0x0)
#define RTC_CR_32000 (0x1)
#define RTC_CR_38400 (0x2)
/* Bit definitions and macros for ISR */
#define RTC_ISR_SW (0x00000001)
#define RTC_ISR_MIN (0x00000002)
#define RTC_ISR_ALM (0x00000004)
#define RTC_ISR_DAY (0x00000008)
#define RTC_ISR_1HZ (0x00000010)
#define RTC_ISR_HR (0x00000020)
#define RTC_ISR_2HZ (0x00000080)
#define RTC_ISR_SAM0 (0x00000100)
#define RTC_ISR_SAM1 (0x00000200)
#define RTC_ISR_SAM2 (0x00000400)
#define RTC_ISR_SAM3 (0x00000800)
#define RTC_ISR_SAM4 (0x00001000)
#define RTC_ISR_SAM5 (0x00002000)
#define RTC_ISR_SAM6 (0x00004000)
#define RTC_ISR_SAM7 (0x00008000)
/* Bit definitions and macros for IER */
#define RTC_IER_SW (0x00000001)
#define RTC_IER_MIN (0x00000002)
#define RTC_IER_ALM (0x00000004)
#define RTC_IER_DAY (0x00000008)
#define RTC_IER_1HZ (0x00000010)
#define RTC_IER_HR (0x00000020)
#define RTC_IER_2HZ (0x00000080)
#define RTC_IER_SAM0 (0x00000100)
#define RTC_IER_SAM1 (0x00000200)
#define RTC_IER_SAM2 (0x00000400)
#define RTC_IER_SAM3 (0x00000800)
#define RTC_IER_SAM4 (0x00001000)
#define RTC_IER_SAM5 (0x00002000)
#define RTC_IER_SAM6 (0x00004000)
#define RTC_IER_SAM7 (0x00008000)
/* Bit definitions and macros for STPWCH */
#define RTC_STPWCH_CNT(x) (((x)&0x0000003F))
/* Bit definitions and macros for DAYS */
#define RTC_DAYS_DAYS(x) (((x)&0x0000FFFF))
/* Bit definitions and macros for ALRM_DAY */
#define RTC_ALRM_DAY_DAYS(x) (((x)&0x0000FFFF))
#endif /* __MCFRTC_H__ */

118
include/asm-m68k/timer.h Normal file
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@@ -0,0 +1,118 @@
/*
* timer.h -- ColdFire internal TIMER support defines.
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/****************************************************************************/
#ifndef timer_h
#define timer_h
/****************************************************************************/
/****************************************************************************/
/* Timer structure */
/****************************************************************************/
/* DMA Timer module registers */
typedef struct dtimer_ctrl {
#if defined(CONFIG_M5249) || defined(CONFIG_M5253)
u16 tmr; /* 0x00 Mode register */
u16 res1; /* 0x02 */
u16 trr; /* 0x04 Reference register */
u16 res2; /* 0x06 */
u16 tcr; /* 0x08 Capture register */
u16 res3; /* 0x0A */
u16 tcn; /* 0x0C Counter register */
u16 res4; /* 0x0E */
u8 res6; /* 0x10 */
u8 ter; /* 0x11 Event register */
u16 res7; /* 0x12 */
#else
u16 tmr; /* 0x00 Mode register */
u8 txmr; /* 0x02 Extended Mode register */
u8 ter; /* 0x03 Event register */
u32 trr; /* 0x04 Reference register */
u32 tcr; /* 0x08 Capture register */
u32 tcn; /* 0x0C Counter register */
#endif
} dtmr_t;
/*Programmable Interrupt Timer */
typedef struct pit_ctrl {
u16 pcsr; /* 0x00 Control and Status Register */
u16 pmr; /* 0x02 Modulus Register */
u16 pcntr; /* 0x04 Count Register */
} pit_t;
/*********************************************************************
* DMA Timers (DTIM)
*********************************************************************/
/* Bit definitions and macros for DTMR */
#define DTIM_DTMR_RST (0x0001) /* Reset */
#define DTIM_DTMR_CLK(x) (((x)&0x0003)<<1) /* Input clock source */
#define DTIM_DTMR_FRR (0x0008) /* Free run/restart */
#define DTIM_DTMR_ORRI (0x0010) /* Output reference request/interrupt enable */
#define DTIM_DTMR_OM (0x0020) /* Output Mode */
#define DTIM_DTMR_CE(x) (((x)&0x0003)<<6) /* Capture Edge */
#define DTIM_DTMR_PS(x) (((x)&0x00FF)<<8) /* Prescaler value */
#define DTIM_DTMR_RST_EN (0x0001)
#define DTIM_DTMR_RST_RST (0x0000)
#define DTIM_DTMR_CE_ANY (0x00C0)
#define DTIM_DTMR_CE_FALL (0x0080)
#define DTIM_DTMR_CE_RISE (0x0040)
#define DTIM_DTMR_CE_NONE (0x0000)
#define DTIM_DTMR_CLK_DTIN (0x0006)
#define DTIM_DTMR_CLK_DIV16 (0x0004)
#define DTIM_DTMR_CLK_DIV1 (0x0002)
#define DTIM_DTMR_CLK_STOP (0x0000)
/* Bit definitions and macros for DTXMR */
#define DTIM_DTXMR_MODE16 (0x01) /* Increment Mode */
#define DTIM_DTXMR_DMAEN (0x80) /* DMA request */
/* Bit definitions and macros for DTER */
#define DTIM_DTER_CAP (0x01) /* Capture event */
#define DTIM_DTER_REF (0x02) /* Output reference event */
/*********************************************************************
*
* Programmable Interrupt Timer Modules (PIT)
*
*********************************************************************/
/* Bit definitions and macros for PCSR */
#define PIT_PCSR_EN (0x0001)
#define PIT_PCSR_RLD (0x0002)
#define PIT_PCSR_PIF (0x0004)
#define PIT_PCSR_PIE (0x0008)
#define PIT_PCSR_OVW (0x0010)
#define PIT_PCSR_HALTED (0x0020)
#define PIT_PCSR_DOZE (0x0040)
#define PIT_PCSR_PRE(x) (((x)&0x000F)<<8)
/* Bit definitions and macros for PMR */
#define PIT_PMR_PM(x) (x)
/* Bit definitions and macros for PCNTR */
#define PIT_PCNTR_PC(x) (x)
/****************************************************************************/
#endif /* timer_h */

56
include/asm-m68k/u-boot.h
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@@ -37,24 +37,44 @@
#ifndef __ASSEMBLY__
typedef struct bd_info {
unsigned long bi_memstart; /* start of DRAM memory */
unsigned long bi_memsize; /* size of DRAM memory in bytes */
unsigned long bi_flashstart; /* start of FLASH memory */
unsigned long bi_flashsize; /* size of FLASH memory */
unsigned long bi_flashoffset; /* reserved area for startup monitor */
unsigned long bi_sramstart; /* start of SRAM memory */
unsigned long bi_sramsize; /* size of SRAM memory */
unsigned long bi_mbar_base; /* base of internal registers */
unsigned long bi_bootflags; /* boot / reboot flag (for LynxOS) */
unsigned long bi_boot_params; /* where this board expects params */
unsigned long bi_ip_addr; /* IP Address */
unsigned char bi_enetaddr[6]; /* Ethernet adress */
unsigned short bi_ethspeed; /* Ethernet speed in Mbps */
unsigned long bi_intfreq; /* Internal Freq, in MHz */
unsigned long bi_busfreq; /* Bus Freq, in MHz */
unsigned long bi_baudrate; /* Console Baudrate */
unsigned long bi_memstart; /* start of DRAM memory */
unsigned long bi_memsize; /* size of DRAM memory in bytes */
unsigned long bi_flashstart; /* start of FLASH memory */
unsigned long bi_flashsize; /* size of FLASH memory */
unsigned long bi_flashoffset; /* reserved area for startup monitor */
unsigned long bi_sramstart; /* start of SRAM memory */
unsigned long bi_sramsize; /* size of SRAM memory */
unsigned long bi_mbar_base; /* base of internal registers */
unsigned long bi_bootflags; /* boot / reboot flag (for LynxOS) */
unsigned long bi_boot_params; /* where this board expects params */
unsigned long bi_ip_addr; /* IP Address */
unsigned char bi_enetaddr[6]; /* Ethernet adress */
unsigned short bi_ethspeed; /* Ethernet speed in Mbps */
unsigned long bi_intfreq; /* Internal Freq, in MHz */
unsigned long bi_busfreq; /* Bus Freq, in MHz */
#ifdef CONFIG_PCI
unsigned long bi_pcifreq; /* pci Freq in MHz */
#endif
#ifdef CONFIG_EXTRA_CLOCK
unsigned long bi_inpfreq; /* input Freq in MHz */
unsigned long bi_vcofreq; /* vco Freq in MHz */
unsigned long bi_flbfreq; /* Flexbus Freq in MHz */
#endif
unsigned long bi_baudrate; /* Console Baudrate */
#ifdef CONFIG_HAS_ETH1
/* second onboard ethernet port */
unsigned char bi_enet1addr[6];
#endif
#ifdef CONFIG_HAS_ETH2
/* third onboard ethernet port */
unsigned char bi_enet2addr[6];
#endif
#ifdef CONFIG_HAS_ETH3
unsigned char bi_enet3addr[6];
#endif
} bd_t;
#endif /* __ASSEMBLY__ */
#endif /* __ASSEMBLY__ */
#endif /* __U_BOOT_H__ */
#endif /* __U_BOOT_H__ */

171
include/asm-m68k/uart.h Normal file
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@@ -0,0 +1,171 @@
/*
* uart.h -- ColdFire internal UART support defines.
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/****************************************************************************/
#ifndef uart_h
#define uart_h
/****************************************************************************/
/* UART module registers */
/* Register read/write struct */
typedef struct uart {
u8 umr; /* 0x00 Mode Register */
u8 resv0[0x3];
union {
u8 usr; /* 0x04 Status Register */
u8 ucsr; /* 0x04 Clock Select Register */
};
u8 resv1[0x3];
u8 ucr; /* 0x08 Command Register */
u8 resv2[0x3];
union {
u8 utb; /* 0x0c Transmit Buffer */
u8 urb; /* 0x0c Receive Buffer */
};
u8 resv3[0x3];
union {
u8 uipcr; /* 0x10 Input Port Change Register */
u8 uacr; /* 0x10 Auxiliary Control reg */
};
u8 resv4[0x3];
union {
u8 uimr; /* 0x14 Interrupt Mask reg */
u8 uisr; /* 0x14 Interrupt Status reg */
};
u8 resv5[0x3];
u8 ubg1; /* 0x18 Counter Timer Upper Register */
u8 resv6[0x3];
u8 ubg2; /* 0x1c Counter Timer Lower Register */
u8 resv7[0x17];
u8 uip; /* 0x34 Input Port Register */
u8 resv8[0x3];
u8 uop1; /* 0x38 Output Port Set Register */
u8 resv9[0x3];
u8 uop0; /* 0x3c Output Port Reset Register */
} uart_t;
/*********************************************************************
* Universal Asynchronous Receiver Transmitter (UART)
*********************************************************************/
/* Bit definitions and macros for UMR */
#define UART_UMR_BC(x) (((x)&0x03))
#define UART_UMR_PT (0x04)
#define UART_UMR_PM(x) (((x)&0x03)<<3)
#define UART_UMR_ERR (0x20)
#define UART_UMR_RXIRQ (0x40)
#define UART_UMR_RXRTS (0x80)
#define UART_UMR_SB(x) (((x)&0x0F))
#define UART_UMR_TXCTS (0x10) /* Trsnsmit CTS */
#define UART_UMR_TXRTS (0x20) /* Transmit RTS */
#define UART_UMR_CM(x) (((x)&0x03)<<6) /* CM bits */
#define UART_UMR_PM_MULTI_ADDR (0x1C)
#define UART_UMR_PM_MULTI_DATA (0x18)
#define UART_UMR_PM_NONE (0x10)
#define UART_UMR_PM_FORCE_HI (0x0C)
#define UART_UMR_PM_FORCE_LO (0x08)
#define UART_UMR_PM_ODD (0x04)
#define UART_UMR_PM_EVEN (0x00)
#define UART_UMR_BC_5 (0x00)
#define UART_UMR_BC_6 (0x01)
#define UART_UMR_BC_7 (0x02)
#define UART_UMR_BC_8 (0x03)
#define UART_UMR_CM_NORMAL (0x00)
#define UART_UMR_CM_ECH (0x40)
#define UART_UMR_CM_LOCAL_LOOP (0x80)
#define UART_UMR_CM_REMOTE_LOOP (0xC0)
#define UART_UMR_SB_STOP_BITS_1 (0x07)
#define UART_UMR_SB_STOP_BITS_15 (0x08)
#define UART_UMR_SB_STOP_BITS_2 (0x0F)
/* Bit definitions and macros for USR */
#define UART_USR_RXRDY (0x01)
#define UART_USR_FFULL (0x02)
#define UART_USR_TXRDY (0x04)
#define UART_USR_TXEMP (0x08)
#define UART_USR_OE (0x10)
#define UART_USR_PE (0x20)
#define UART_USR_FE (0x40)
#define UART_USR_RB (0x80)
/* Bit definitions and macros for UCSR */
#define UART_UCSR_TCS(x) (((x)&0x0F))
#define UART_UCSR_RCS(x) (((x)&0x0F)<<4)
#define UART_UCSR_RCS_SYS_CLK (0xD0)
#define UART_UCSR_RCS_CTM16 (0xE0)
#define UART_UCSR_RCS_CTM (0xF0)
#define UART_UCSR_TCS_SYS_CLK (0x0D)
#define UART_UCSR_TCS_CTM16 (0x0E)
#define UART_UCSR_TCS_CTM (0x0F)
/* Bit definitions and macros for UCR */
#define UART_UCR_RXC(x) (((x)&0x03))
#define UART_UCR_TXC(x) (((x)&0x03)<<2)
#define UART_UCR_MISC(x) (((x)&0x07)<<4)
#define UART_UCR_NONE (0x00)
#define UART_UCR_STOP_BREAK (0x70)
#define UART_UCR_START_BREAK (0x60)
#define UART_UCR_BKCHGINT (0x50)
#define UART_UCR_RESET_ERROR (0x40)
#define UART_UCR_RESET_TX (0x30)
#define UART_UCR_RESET_RX (0x20)
#define UART_UCR_RESET_MR (0x10)
#define UART_UCR_TX_DISABLED (0x08)
#define UART_UCR_TX_ENABLED (0x04)
#define UART_UCR_RX_DISABLED (0x02)
#define UART_UCR_RX_ENABLED (0x01)
/* Bit definitions and macros for UIPCR */
#define UART_UIPCR_CTS (0x01)
#define UART_UIPCR_COS (0x10)
/* Bit definitions and macros for UACR */
#define UART_UACR_IEC (0x01)
/* Bit definitions and macros for UIMR */
#define UART_UIMR_TXRDY (0x01)
#define UART_UIMR_RXRDY_FU (0x02)
#define UART_UIMR_DB (0x04)
#define UART_UIMR_COS (0x80)
/* Bit definitions and macros for UISR */
#define UART_UISR_TXRDY (0x01)
#define UART_UISR_RXRDY_FU (0x02)
#define UART_UISR_DB (0x04)
#define UART_UISR_RXFTO (0x08)
#define UART_UISR_TXFIFO (0x10)
#define UART_UISR_RXFIFO (0x20)
#define UART_UISR_COS (0x80)
/* Bit definitions and macros for UIP */
#define UART_UIP_CTS (0x01)
/* Bit definitions and macros for UOP1 */
#define UART_UOP1_RTS (0x01)
/* Bit definitions and macros for UOP0 */
#define UART_UOP0_RTS (0x01)
/****************************************************************************/
#endif /* mcfuart_h */

98
include/asm-microblaze/asm.h Normal file
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@@ -0,0 +1,98 @@
/*
* (C) Copyright 2007 Michal Simek
*
* Michal SIMEK <monstr@monstr.eu>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/* FSL macros */
#define NGET(val, fslnum) \
__asm__ __volatile__ ("nget %0, rfsl" #fslnum :"=r" (val));
#define GET(val, fslnum) \
__asm__ __volatile__ ("get %0, rfsl" #fslnum :"=r" (val));
#define NCGET(val, fslnum) \
__asm__ __volatile__ ("ncget %0, rfsl" #fslnum :"=r" (val));
#define CGET(val, fslnum) \
__asm__ __volatile__ ("cget %0, rfsl" #fslnum :"=r" (val));
#define NPUT(val, fslnum) \
__asm__ __volatile__ ("nput %0, rfsl" #fslnum ::"r" (val));
#define PUT(val, fslnum) \
__asm__ __volatile__ ("put %0, rfsl" #fslnum ::"r" (val));
#define NCPUT(val, fslnum) \
__asm__ __volatile__ ("ncput %0, rfsl" #fslnum ::"r" (val));
#define CPUT(val, fslnum) \
__asm__ __volatile__ ("cput %0, rfsl" #fslnum ::"r" (val));
/* CPU dependent */
/* machine status register */
#define MFS(val, reg) \
__asm__ __volatile__ ("mfs %0," #reg :"=r" (val));
#define MTS(val, reg) \
__asm__ __volatile__ ("mts " #reg ", %0"::"r" (val));
/* get return address from interrupt */
#define R14(val) \
__asm__ __volatile__ ("addi %0, r14, 0":"=r" (val));
#define NOP __asm__ __volatile__ ("nop");
/* use machine status registe USE_MSR_REG */
#ifdef XILINX_USE_MSR_INSTR
#define MSRSET(val) \
__asm__ __volatile__ ("msrset r0," #val );
#define MSRCLR(val) \
__asm__ __volatile__ ("msrclr r0," #val );
#else
#define MSRSET(val) \
{ \
register unsigned tmp; \
__asm__ __volatile__ (" \
mfs %0, rmsr; \
ori %0, %0, "#val"; \
mts rmsr, %0; \
nop;" \
: "=r" (tmp) \
: "d" (val) \
: "memory"); \
}
#define MSRCLR(val) \
{ \
register unsigned tmp; \
__asm__ __volatile__ (" \
mfs %0, rmsr; \
andi %0, %0, ~"#val"; \
mts rmsr, %0; \
nop;" \
: "=r" (tmp) \
: "d" (val) \
: "memory"); \
}
#endif

3
include/asm-microblaze/microblaze_intc.h
View File

@@ -38,3 +38,6 @@ struct irq_action {
void *arg;
int count; /* number of interrupt */
};
void install_interrupt_handler (int irq, interrupt_handler_t * hdlr,
void *arg);

156
include/asm-mips/string.h
View File

@@ -1,126 +1,31 @@
/* $Id: string.h,v 1.13 2000/02/19 14:12:14 harald Exp $
*
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (c) 1994, 1995, 1996, 1997, 1998 by Ralf Baechle
* Copyright (c) 1994, 95, 96, 97, 98, 2000, 01 Ralf Baechle
* Copyright (c) 2000 by Silicon Graphics, Inc.
* Copyright (c) 2001 MIPS Technologies, Inc.
*/
#ifndef __ASM_MIPS_STRING_H
#define __ASM_MIPS_STRING_H
#ifndef _ASM_STRING_H
#define _ASM_STRING_H
#include <linux/config.h>
/*
* We don't do inline string functions, since the
* optimised inline asm versions are not small.
*/
#define __HAVE_ARCH_STRCPY
extern __inline__ char *strcpy(char *__dest, __const__ char *__src)
{
char *__xdest = __dest;
#undef __HAVE_ARCH_STRCPY
extern char *strcpy(char *__dest, __const__ char *__src);
__asm__ __volatile__(
".set\tnoreorder\n\t"
".set\tnoat\n"
"1:\tlbu\t$1,(%1)\n\t"
"addiu\t%1,1\n\t"
"sb\t$1,(%0)\n\t"
"bnez\t$1,1b\n\t"
"addiu\t%0,1\n\t"
".set\tat\n\t"
".set\treorder"
: "=r" (__dest), "=r" (__src)
: "0" (__dest), "1" (__src)
: "$1","memory");
#undef __HAVE_ARCH_STRNCPY
extern char *strncpy(char *__dest, __const__ char *__src, size_t __n);
return __xdest;
}
#undef __HAVE_ARCH_STRCMP
extern int strcmp(__const__ char *__cs, __const__ char *__ct);
#define __HAVE_ARCH_STRNCPY
extern __inline__ char *strncpy(char *__dest, __const__ char *__src, size_t __n)
{
char *__xdest = __dest;
if (__n == 0)
return __xdest;
__asm__ __volatile__(
".set\tnoreorder\n\t"
".set\tnoat\n"
"1:\tlbu\t$1,(%1)\n\t"
"subu\t%2,1\n\t"
"sb\t$1,(%0)\n\t"
"beqz\t$1,2f\n\t"
"addiu\t%0,1\n\t"
"bnez\t%2,1b\n\t"
"addiu\t%1,1\n"
"2:\n\t"
".set\tat\n\t"
".set\treorder"
: "=r" (__dest), "=r" (__src), "=r" (__n)
: "0" (__dest), "1" (__src), "2" (__n)
: "$1","memory");
return __dest;
}
#define __HAVE_ARCH_STRCMP
extern __inline__ int strcmp(__const__ char *__cs, __const__ char *__ct)
{
int __res;
__asm__ __volatile__(
".set\tnoreorder\n\t"
".set\tnoat\n\t"
"lbu\t%2,(%0)\n"
"1:\tlbu\t$1,(%1)\n\t"
"addiu\t%0,1\n\t"
"bne\t$1,%2,2f\n\t"
"addiu\t%1,1\n\t"
"bnez\t%2,1b\n\t"
"lbu\t%2,(%0)\n\t"
#if defined(CONFIG_CPU_R3000)
"nop\n\t"
#endif
"move\t%2,$1\n"
"2:\tsubu\t%2,$1\n"
"3:\t.set\tat\n\t"
".set\treorder"
: "=r" (__cs), "=r" (__ct), "=r" (__res)
: "0" (__cs), "1" (__ct)
: "$1");
return __res;
}
#define __HAVE_ARCH_STRNCMP
extern __inline__ int
strncmp(__const__ char *__cs, __const__ char *__ct, size_t __count)
{
int __res;
__asm__ __volatile__(
".set\tnoreorder\n\t"
".set\tnoat\n"
"1:\tlbu\t%3,(%0)\n\t"
"beqz\t%2,2f\n\t"
"lbu\t$1,(%1)\n\t"
"subu\t%2,1\n\t"
"bne\t$1,%3,3f\n\t"
"addiu\t%0,1\n\t"
"bnez\t%3,1b\n\t"
"addiu\t%1,1\n"
"2:\n\t"
#if defined(CONFIG_CPU_R3000)
"nop\n\t"
#endif
"move\t%3,$1\n"
"3:\tsubu\t%3,$1\n\t"
".set\tat\n\t"
".set\treorder"
: "=r" (__cs), "=r" (__ct), "=r" (__count), "=r" (__res)
: "0" (__cs), "1" (__ct), "2" (__count)
: "$1");
return __res;
}
#undef __HAVE_ARCH_STRNCMP
extern int strncmp(__const__ char *__cs, __const__ char *__ct, size_t __count);
#undef __HAVE_ARCH_MEMSET
extern void *memset(void *__s, int __c, size_t __count);
@@ -131,27 +36,4 @@ extern void *memcpy(void *__to, __const__ void *__from, size_t __n);
#undef __HAVE_ARCH_MEMMOVE
extern void *memmove(void *__dest, __const__ void *__src, size_t __n);
/* Don't build bcopy at all ... */
#define __HAVE_ARCH_BCOPY
#define __HAVE_ARCH_MEMSCAN
extern __inline__ void *memscan(void *__addr, int __c, size_t __size)
{
char *__end = (char *)__addr + __size;
__asm__(".set\tpush\n\t"
".set\tnoat\n\t"
".set\treorder\n\t"
"1:\tbeq\t%0,%1,2f\n\t"
"addiu\t%0,1\n\t"
"lb\t$1,-1(%0)\n\t"
"bne\t$1,%4,1b\n"
"2:\t.set\tpop"
: "=r" (__addr), "=r" (__end)
: "0" (__addr), "1" (__end), "r" (__c)
: "$1");
return __addr;
}
#endif /* __ASM_MIPS_STRING_H */
#endif /* _ASM_STRING_H */

17
include/asm-ppc/e300.h
View File

@@ -6,19 +6,10 @@
#ifndef __E300_H__
#define __E300_H__
/*
* e300 Processor Version & Revision Numbers
*/
#define PVR_83xx 0x80830000
#define PVR_8349_REV10 (PVR_83xx | 0x0010)
#define PVR_8349_REV11 (PVR_83xx | 0x0011)
#define PVR_8360_REV10 (PVR_83xx | 0x0020)
#define PVR_8360_REV11 (PVR_83xx | 0x0020)
#if defined(CONFIG_MPC832X)
#undef PVR_83xx
#define PVR_83xx 0x80840000
#endif
#define PVR_E300C1 0x80830000
#define PVR_E300C2 0x80840000
#define PVR_E300C3 0x80850000
#define PVR_E300C4 0x80860000
/*
* Hardware Implementation-Dependent Register 0 (HID0)

20
include/asm-ppc/global_data.h
View File

@@ -55,11 +55,13 @@ typedef struct global_data {
#if defined(CONFIG_MPC83XX)
/* There are other clocks in the MPC83XX */
u32 csb_clk;
#if defined (CONFIG_MPC834X)
#if defined (CONFIG_MPC834X) || defined(CONFIG_MPC831X)
u32 tsec1_clk;
u32 tsec2_clk;
u32 usbmph_clk;
u32 usbdr_clk;
#endif
#if defined (CONFIG_MPC834X)
u32 usbmph_clk;
#endif /* CONFIG_MPC834X */
u32 core_clk;
u32 i2c1_clk;
@@ -69,20 +71,24 @@ typedef struct global_data {
u32 lclk_clk;
u32 ddr_clk;
u32 pci_clk;
#if defined(CONFIG_MPC8360)
u32 ddr_sec_clk;
#endif /* CONFIG_MPC8360 */
#endif
#if defined(CONFIG_QE)
u32 qe_clk;
u32 brg_clk;
uint mp_alloc_base;
uint mp_alloc_top;
#endif /* CONFIG_QE */
#if defined (CONFIG_MPC8360)
u32 ddr_sec_clk;
#endif /* CONFIG_MPC8360 */
#endif
#if defined(CONFIG_MPC5xxx)
unsigned long ipb_clk;
unsigned long pci_clk;
#endif
#if defined(CONFIG_MPC512X)
u32 ipb_clk;
u32 csb_clk;
#endif /* CONFIG_MPC512X */
#if defined(CONFIG_MPC8220)
unsigned long bExtUart;
unsigned long inp_clk;
@@ -127,7 +133,7 @@ typedef struct global_data {
unsigned long do_mdm_init;
unsigned long be_quiet;
#endif
#ifdef CONFIG_LWMON
#if defined(CONFIG_LWMON) || defined(CONFIG_LWMON5)
unsigned long kbd_status;
#endif
void **jt; /* jump table */

8
include/asm-ppc/gpio.h
View File

@@ -45,12 +45,14 @@ typedef enum gpio_driver { GPIO_DIS, GPIO_IN, GPIO_OUT, GPIO_BI } gpio_driver_t;
typedef enum gpio_out { GPIO_OUT_0, GPIO_OUT_1, GPIO_OUT_NO_CHG } gpio_out_t;
typedef struct {
unsigned long add; /* gpio core base address */
gpio_driver_t in_out; /* Driver Setting */
gpio_select_t alt_nb; /* Selected Alternate */
unsigned long add; /* gpio core base address */
gpio_driver_t in_out; /* Driver Setting */
gpio_select_t alt_nb; /* Selected Alternate */
gpio_out_t out_val;/* Default Output Value */
} gpio_param_s;
#endif
void gpio_config(int pin, int in_out, int gpio_alt, int out_val);
void gpio_write_bit(int pin, int val);
int gpio_read_out_bit(int pin);
void gpio_set_chip_configuration(void);

569
include/asm-ppc/immap_512x.h Normal file
View File

@@ -0,0 +1,569 @@
/*
* (C) Copyright 2007 DENX Software Engineering
*
* MPC512x Internal Memory Map
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* Based on the MPC83xx header.
*/
#ifndef __IMMAP_512x__
#define __IMMAP_512x__
#include <asm/types.h>
typedef struct law512x {
u32 bar; /* Base Addr Register */
u32 ar; /* Attributes Register */
} law521x_t;
/*
* System configuration registers
*/
typedef struct sysconf512x {
u32 immrbar; /* Internal memory map base address register */
u8 res0[0x1c];
u32 lpbaw; /* LP Boot Access Window */
u32 lpcs0aw; /* LP CS0 Access Window */
u32 lpcs1aw; /* LP CS1 Access Window */
u32 lpcs2aw; /* LP CS2 Access Window */
u32 lpcs3aw; /* LP CS3 Access Window */
u32 lpcs4aw; /* LP CS4 Access Window */
u32 lpcs5aw; /* LP CS5 Access Window */
u32 lpcs6aw; /* LP CS6 Access Window */
u32 lpcs7aw; /* LP CS7 Access Window */
u8 res1[0x1c];
law521x_t pcilaw[3]; /* PCI Local Access Window 0-2 Registers */
u8 res2[0x28];
law521x_t ddrlaw; /* DDR Local Access Window */
u8 res3[0x18];
u32 mbxbar; /* MBX Base Address */
u32 srambar; /* SRAM Base Address */
u32 nfcbar; /* NFC Base Address */
u8 res4[0x34];
u32 spridr; /* System Part and Revision ID Register */
u32 spcr; /* System Priority Configuration Register */
u8 res5[0xf8];
} sysconf512x_t;
/*
* Watch Dog Timer (WDT) Registers
*/
typedef struct wdt512x {
u8 res0[4];
u32 swcrr; /* System watchdog control register */
u32 swcnr; /* System watchdog count register */
u8 res1[2];
u16 swsrr; /* System watchdog service register */
u8 res2[0xF0];
} wdt512x_t;
/*
* RTC Module Registers
*/
typedef struct rtclk512x {
u8 fixme[0x100];
} rtclk512x_t;
/*
* General Purpose Timer
*/
typedef struct gpt512x {
u8 fixme[0x100];
} gpt512x_t;
/*
* Integrated Programmable Interrupt Controller
*/
typedef struct ipic512x {
u8 fixme[0x100];
} ipic512x_t;
/*
* System Arbiter Registers
*/
typedef struct arbiter512x {
u32 acr; /* Arbiter Configuration Register */
u32 atr; /* Arbiter Timers Register */
u32 ater; /* Arbiter Transfer Error Register */
u32 aer; /* Arbiter Event Register */
u32 aidr; /* Arbiter Interrupt Definition Register */
u32 amr; /* Arbiter Mask Register */
u32 aeatr; /* Arbiter Event Attributes Register */
u32 aeadr; /* Arbiter Event Address Register */
u32 aerr; /* Arbiter Event Response Register */
u8 res1[0xDC];
} arbiter512x_t;
/*
* Reset Module
*/
typedef struct reset512x {
u32 rcwl; /* Reset Configuration Word Low Register */
u32 rcwh; /* Reset Configuration Word High Register */
u8 res0[8];
u32 rsr; /* Reset Status Register */
u32 rmr; /* Reset Mode Register */
u32 rpr; /* Reset protection Register */
u32 rcr; /* Reset Control Register */
u32 rcer; /* Reset Control Enable Register */
u8 res1[0xDC];
} reset512x_t;
/*
* Clock Module
*/
typedef struct clk512x {
u32 spmr; /* System PLL Mode Register */
u32 sccr[2]; /* System Clock Control Registers */
u32 scfr[2]; /* System Clock Frequency Registers */
u8 res0[4];
u32 bcr; /* Bread Crumb Register */
u32 pscccr[12]; /* PSC0-11 Clock Control Registers */
u32 spccr; /* SPDIF Clock Control Registers */
u32 cccr; /* CFM Clock Control Registers */
u32 dccr; /* DIU Clock Control Registers */
u8 res1[0xa8];
} clk512x_t;
/*
* Power Management Control Module
*/
typedef struct pmc512x {
u8 fixme[0x100];
} pmc512x_t;
/*
* General purpose I/O module
*/
typedef struct gpio512x {
u8 fixme[0x100];
} gpio512x_t;
/*
* DDR Memory Controller Memory Map
*/
typedef struct ddr512x {
u32 ddr_sys_config; /* System Configuration Register */
u32 ddr_time_config0; /* Timing Configuration Register */
u32 ddr_time_config1; /* Timing Configuration Register */
u32 ddr_time_config2; /* Timing Configuration Register */
u32 ddr_command; /* Command Register */
u32 ddr_compact_command; /* Compact Command Register */
u32 self_refresh_cmd_0; /* Enter/Exit Self Refresh Registers */
u32 self_refresh_cmd_1; /* Enter/Exit Self Refresh Registers */
u32 self_refresh_cmd_2; /* Enter/Exit Self Refresh Registers */
u32 self_refresh_cmd_3; /* Enter/Exit Self Refresh Registers */
u32 self_refresh_cmd_4; /* Enter/Exit Self Refresh Registers */
u32 self_refresh_cmd_5; /* Enter/Exit Self Refresh Registers */
u32 self_refresh_cmd_6; /* Enter/Exit Self Refresh Registers */
u32 self_refresh_cmd_7; /* Enter/Exit Self Refresh Registers */
u32 DQS_config_offset_count; /* DQS Config Offset Count */
u32 DQS_config_offset_time; /* DQS Config Offset Time */
u32 DQS_delay_status; /* DQS Delay Status */
u32 res0[0xF];
u32 prioman_config1; /* Priority Manager Configuration */
u32 prioman_config2; /* Priority Manager Configuration */
u32 hiprio_config; /* High Priority Configuration */
u32 lut_table0_main_upper; /* LUT0 Main Upper */
u32 lut_table1_main_upper; /* LUT1 Main Upper */
u32 lut_table2_main_upper; /* LUT2 Main Upper */
u32 lut_table3_main_upper; /* LUT3 Main Upper */
u32 lut_table4_main_upper; /* LUT4 Main Upper */
u32 lut_table0_main_lower; /* LUT0 Main Lower */
u32 lut_table1_main_lower; /* LUT1 Main Lower */
u32 lut_table2_main_lower; /* LUT2 Main Lower */
u32 lut_table3_main_lower; /* LUT3 Main Lower */
u32 lut_table4_main_lower; /* LUT4 Main Lower */
u32 lut_table0_alternate_upper; /* LUT0 Alternate Upper */
u32 lut_table1_alternate_upper; /* LUT1 Alternate Upper */
u32 lut_table2_alternate_upper; /* LUT2 Alternate Upper */
u32 lut_table3_alternate_upper; /* LUT3 Alternate Upper */
u32 lut_table4_alternate_upper; /* LUT4 Alternate Upper */
u32 lut_table0_alternate_lower; /* LUT0 Alternate Lower */
u32 lut_table1_alternate_lower; /* LUT1 Alternate Lower */
u32 lut_table2_alternate_lower; /* LUT2 Alternate Lower */
u32 lut_table3_alternate_lower; /* LUT3 Alternate Lower */
u32 lut_table4_alternate_lower; /* LUT4 Alternate Lower */
u32 performance_monitor_config;
u32 event_time_counter;
u32 event_time_preset;
u32 performance_monitor1_address_low;
u32 performance_monitor2_address_low;
u32 performance_monitor1_address_hi;
u32 performance_monitor2_address_hi;
u32 res1[2];
u32 performance_monitor1_read_counter;
u32 performance_monitor2_read_counter;
u32 performance_monitor1_write_counter;
u32 performance_monitor2_write_counter;
u32 granted_ack_counter0;
u32 granted_ack_counter1;
u32 granted_ack_counter2;
u32 granted_ack_counter3;
u32 granted_ack_counter4;
u32 cumulative_wait_counter0;
u32 cumulative_wait_counter1;
u32 cumulative_wait_counter2;
u32 cumulative_wait_counter3;
u32 cumulative_wait_counter4;
u32 summed_priority_counter0;
u32 summed_priority_counter1;
u32 summed_priority_counter2;
u32 summed_priority_counter3;
u32 summed_priority_counter4;
u32 res2[0x3AD];
} ddr512x_t;
/*
* DMA/Messaging Unit
*/
typedef struct dma512x {
u8 fixme[0x1800];
} dma512x_t;
/*
* PCI Software Configuration Registers
*/
typedef struct pciconf512x {
u8 fixme[0x80];
} pciconf512x_t;
/*
* Sequencer
*/
typedef struct ios512x {
u8 fixme[0x100];
} ios512x_t;
/*
* PCI Controller
*/
typedef struct pcictrl512x {
u8 fixme[0x100];
} pcictrl512x_t;
/*
* MSCAN
*/
typedef struct mscan512x {
u8 fixme[0x100];
} mscan512x_t;
/*
* BDLC
*/
typedef struct bdlc512x {
u8 fixme[0x100];
} bdlc512x_t;
/*
* SDHC
*/
typedef struct sdhc512x {
u8 fixme[0x100];
} sdhc512x_t;
/*
* SPDIF
*/
typedef struct spdif512x {
u8 fixme[0x100];
} spdif512x_t;
/*
* I2C
*/
typedef struct i2c512x_dev {
volatile u32 madr; /* I2Cn + 0x00 */
volatile u32 mfdr; /* I2Cn + 0x04 */
volatile u32 mcr; /* I2Cn + 0x08 */
volatile u32 msr; /* I2Cn + 0x0C */
volatile u32 mdr; /* I2Cn + 0x10 */
u8 res0[0x0C];
} i2c512x_dev_t;
typedef struct i2c512x {
i2c512x_dev_t dev[3];
volatile u32 icr;
volatile u32 mifr;
u8 res0[0x98];
} i2c512x_t;
/*
* AXE
*/
typedef struct axe512x {
u8 fixme[0x100];
} axe512x_t;
/*
* DIU
*/
typedef struct diu512x {
u8 fixme[0x100];
} diu512x_t;
/*
* CFM
*/
typedef struct cfm512x {
u8 fixme[0x100];
} cfm512x_t;
/*
* FEC
*/
typedef struct fec512x {
u8 fixme[0x800];
} fec512x_t;
/*
* ULPI
*/
typedef struct ulpi512x {
u8 fixme[0x600];
} ulpi512x_t;
/*
* UTMI
*/
typedef struct utmi512x {
u8 fixme[0x3000];
} utmi512x_t;
/*
* PCI DMA
*/
typedef struct pcidma512x {
u8 fixme[0x300];
} pcidma512x_t;
/*
* IO Control
*/
typedef struct ioctrl512x {
u32 regs[0x400];
} ioctrl512x_t;
/*
* IIM
*/
typedef struct iim512x {
u8 fixme[0x1000];
} iim512x_t;
/*
* LPC
*/
typedef struct lpc512x {
u32 cs_cfg[8]; /* Chip Select N Configuration Registers
No dedicated entry for CS Boot as == CS0 */
u32 cs_cr; /* Chip Select Control Register */
u32 cs_sr; /* Chip Select Status Register */
u32 cs_bcr; /* Chip Select Burst Control Register */
u32 cs_dccr; /* Chip Select Deadcycle Control Register */
u32 cs_hccr; /* Chip Select Holdcycle Control Register */
u8 res0[0xcc];
u32 sclpc_psr; /* SCLPC Packet Size Register */
u32 sclpc_sar; /* SCLPC Start Address Register */
u32 sclpc_cr; /* SCLPC Control Register */
u32 sclpc_er; /* SCLPC Enable Register */
u32 sclpc_nar; /* SCLPC NextAddress Register */
u32 sclpc_sr; /* SCLPC Status Register */
u32 sclpc_bdr; /* SCLPC Bytes Done Register */
u32 emb_scr; /* EMB Share Counter Register */
u32 emb_pcr; /* EMB Pause Control Register */
u8 res1[0x1c];
u32 lpc_fdwr; /* LPC RX/TX FIFO Data Word Register */
u32 lpc_fsr; /* LPC RX/TX FIFO Status Register */
u32 lpc_cr; /* LPC RX/TX FIFO Control Register */
u32 lpc_ar; /* LPC RX/TX FIFO Alarm Register */
u8 res2[0xb0];
} lpc512x_t;
/*
* PATA
*/
typedef struct pata512x {
u8 fixme[0x100];
} pata512x_t;
/*
* PSC
*/
typedef struct psc512x {
volatile u8 mode; /* PSC + 0x00 */
volatile u8 res0[3];
union { /* PSC + 0x04 */
volatile u16 status;
volatile u16 clock_select;
} sr_csr;
#define psc_status sr_csr.status
#define psc_clock_select sr_csr.clock_select
volatile u16 res1;
volatile u8 command; /* PSC + 0x08 */
volatile u8 res2[3];
union { /* PSC + 0x0c */
volatile u8 buffer_8;
volatile u16 buffer_16;
volatile u32 buffer_32;
} buffer;
#define psc_buffer_8 buffer.buffer_8
#define psc_buffer_16 buffer.buffer_16
#define psc_buffer_32 buffer.buffer_32
union { /* PSC + 0x10 */
volatile u8 ipcr;
volatile u8 acr;
} ipcr_acr;
#define psc_ipcr ipcr_acr.ipcr
#define psc_acr ipcr_acr.acr
volatile u8 res3[3];
union { /* PSC + 0x14 */
volatile u16 isr;
volatile u16 imr;
} isr_imr;
#define psc_isr isr_imr.isr
#define psc_imr isr_imr.imr
volatile u16 res4;
volatile u8 ctur; /* PSC + 0x18 */
volatile u8 res5[3];
volatile u8 ctlr; /* PSC + 0x1c */
volatile u8 res6[3];
volatile u32 ccr; /* PSC + 0x20 */
volatile u8 res7[12];
volatile u8 ivr; /* PSC + 0x30 */
volatile u8 res8[3];
volatile u8 ip; /* PSC + 0x34 */
volatile u8 res9[3];
volatile u8 op1; /* PSC + 0x38 */
volatile u8 res10[3];
volatile u8 op0; /* PSC + 0x3c */
volatile u8 res11[3];
volatile u32 sicr; /* PSC + 0x40 */
volatile u8 res12[60];
volatile u32 tfcmd; /* PSC + 0x80 */
volatile u32 tfalarm; /* PSC + 0x84 */
volatile u32 tfstat; /* PSC + 0x88 */
volatile u32 tfintstat; /* PSC + 0x8C */
volatile u32 tfintmask; /* PSC + 0x90 */
volatile u32 tfcount; /* PSC + 0x94 */
volatile u16 tfwptr; /* PSC + 0x98 */
volatile u16 tfrptr; /* PSC + 0x9A */
volatile u32 tfsize; /* PSC + 0x9C */
volatile u8 res13[28];
union { /* PSC + 0xBC */
volatile u8 buffer_8;
volatile u16 buffer_16;
volatile u32 buffer_32;
} tfdata_buffer;
#define tfdata_8 tfdata_buffer.buffer_8
#define tfdata_16 tfdata_buffer.buffer_16
#define tfdata_32 tfdata_buffer.buffer_32
volatile u32 rfcmd; /* PSC + 0xC0 */
volatile u32 rfalarm; /* PSC + 0xC4 */
volatile u32 rfstat; /* PSC + 0xC8 */
volatile u32 rfintstat; /* PSC + 0xCC */
volatile u32 rfintmask; /* PSC + 0xD0 */
volatile u32 rfcount; /* PSC + 0xD4 */
volatile u16 rfwptr; /* PSC + 0xD8 */
volatile u16 rfrptr; /* PSC + 0xDA */
volatile u32 rfsize; /* PSC + 0xDC */
volatile u8 res18[28];
union { /* PSC + 0xFC */
volatile u8 buffer_8;
volatile u16 buffer_16;
volatile u32 buffer_32;
} rfdata_buffer;
#define rfdata_8 rfdata_buffer.buffer_8
#define rfdata_16 rfdata_buffer.buffer_16
#define rfdata_32 rfdata_buffer.buffer_32
} psc512x_t;
/*
* FIFOC
*/
typedef struct fifoc512x {
u32 fifoc_cmd;
u32 fifoc_int;
u32 fifoc_dma;
u32 fifoc_axe;
u32 fifoc_debug;
u8 fixme[0xEC];
} fifoc512x_t;
/*
* SATA
*/
typedef struct sata512x {
u8 fixme[0x2000];
} sata512x_t;
typedef struct immap {
sysconf512x_t sysconf; /* System configuration */
u8 res0[0x700];
wdt512x_t wdt; /* Watch Dog Timer (WDT) */
rtclk512x_t rtc; /* Real Time Clock Module */
gpt512x_t gpt; /* General Purpose Timer */
ipic512x_t ipic; /* Integrated Programmable Interrupt Controller */
arbiter512x_t arbiter; /* CSB Arbiter */
reset512x_t reset; /* Reset Module */
clk512x_t clk; /* Clock Module */
pmc512x_t pmc; /* Power Management Control Module */
gpio512x_t gpio; /* General purpose I/O module */
u8 res1[0x100];
mscan512x_t mscan; /* MSCAN */
bdlc512x_t bdlc; /* BDLC */
sdhc512x_t sdhc; /* SDHC */
spdif512x_t spdif; /* SPDIF */
i2c512x_t i2c; /* I2C Controllers */
u8 res2[0x800];
axe512x_t axe; /* AXE */
diu512x_t diu; /* Display Interface Unit */
cfm512x_t cfm; /* Clock Frequency Measurement */
u8 res3[0x500];
fec512x_t fec; /* Fast Ethernet Controller */
ulpi512x_t ulpi; /* USB ULPI */
u8 res4[0xa00];
utmi512x_t utmi; /* USB UTMI */
u8 res5[0x1000];
pcidma512x_t pci_dma; /* PCI DMA */
pciconf512x_t pci_conf; /* PCI Configuration */
u8 res6[0x80];
ios512x_t ios; /* PCI Sequencer */
pcictrl512x_t pci_ctrl; /* PCI Controller Control and Status */
u8 res7[0xa00];
ddr512x_t mddrc; /* Multi-port DDR Memory Controller */
ioctrl512x_t io_ctrl; /* IO Control */
iim512x_t iim; /* IC Identification module */
u8 res8[0x4000];
lpc512x_t lpc; /* LocalPlus Controller */
pata512x_t pata; /* Parallel ATA */
u8 res9[0xd00];
psc512x_t psc[12]; /* PSCs */
u8 res10[0x300];
fifoc512x_t fifoc; /* FIFO Controller */
u8 res11[0x2000];
dma512x_t dma; /* DMA */
u8 res12[0xa800];
sata512x_t sata; /* Serial ATA */
u8 res13[0xde000];
} immap_t;
#endif /* __IMMAP_512x__ */

56
include/asm-ppc/immap_83xx.h
View File

@@ -206,7 +206,9 @@ typedef struct pmc83xx {
u32 pmccr; /* PMC Configuration Register */
u32 pmcer; /* PMC Event Register */
u32 pmcmr; /* PMC Mask Register */
u8 res0[0xF4];
u32 pmccr1; /* PMC Configuration Register 1 */
u32 pmccr2; /* PMC Configuration Register 2 */
u8 res0[0xEC];
} pmc83xx_t;
/*
@@ -355,7 +357,8 @@ typedef struct lbus83xx {
u8 res2[0x8];
u32 mrtpr; /* Memory Refresh Timer Prescaler Register */
u32 mdr; /* UPM Data Register */
u8 res3[0x8];
u8 res3[0x4];
u32 lsor; /* Special Operation Initiation Register */
u32 lsdmr; /* SDRAM Mode Register */
u8 res4[0x8];
u32 lurt; /* UPM Refresh Timer */
@@ -369,8 +372,14 @@ typedef struct lbus83xx {
u8 res6[0xC];
u32 lbcr; /* Configuration Register */
u32 lcrr; /* Clock Ratio Register */
u8 res7[0x28];
u8 res8[0xF00];
u8 res7[0x8];
u32 fmr; /* Flash Mode Register */
u32 fir; /* Flash Instruction Register */
u32 fcr; /* Flash Command Register */
u32 fbar; /* Flash Block Addr Register */
u32 fpar; /* Flash Page Addr Register */
u32 fbcr; /* Flash Byte Count Register */
u8 res8[0xF08];
} lbus83xx_t;
/*
@@ -527,7 +536,7 @@ typedef struct pcictrl83xx {
* USB
*/
typedef struct usb83xx {
u8 fixme[0x2000];
u8 fixme[0x1000];
} usb83xx_t;
/*
@@ -574,7 +583,42 @@ typedef struct immap {
ios83xx_t ios; /* Sequencer */
pcictrl83xx_t pci_ctrl[2]; /* PCI Controller Control and Status Registers */
u8 res5[0x19900];
usb83xx_t usb;
usb83xx_t usb[2];
tsec83xx_t tsec[2];
u8 res6[0xA000];
security83xx_t security;
u8 res7[0xC0000];
} immap_t;
#elif defined(CONFIG_MPC831X)
typedef struct immap {
sysconf83xx_t sysconf; /* System configuration */
wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
rtclk83xx_t rtc; /* Real Time Clock Module Registers */
rtclk83xx_t pit; /* Periodic Interval Timer */
gtm83xx_t gtm[2]; /* Global Timers Module */
ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
arbiter83xx_t arbiter; /* System Arbiter Registers */
reset83xx_t reset; /* Reset Module */
clk83xx_t clk; /* System Clock Module */
pmc83xx_t pmc; /* Power Management Control Module */
gpio83xx_t gpio[1]; /* General purpose I/O module */
u8 res0[0x1300];
ddr83xx_t ddr; /* DDR Memory Controller Memory */
fsl_i2c_t i2c[2]; /* I2C Controllers */
u8 res1[0x1300];
duart83xx_t duart[2]; /* DUART */
u8 res2[0x900];
lbus83xx_t lbus; /* Local Bus Controller Registers */
u8 res3[0x1000];
spi83xx_t spi; /* Serial Peripheral Interface */
dma83xx_t dma; /* DMA */
pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */
u8 res4[0x80];
ios83xx_t ios; /* Sequencer */
pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */
u8 res5[0x1aa00];
usb83xx_t usb[1];
tsec83xx_t tsec[2];
u8 res6[0xA000];
security83xx_t security;

58
include/asm-ppc/immap_85xx.h
View File

@@ -1,6 +1,8 @@
/*
* MPC85xx Internal Memory Map
*
* Copyright 2007 Freescale Semiconductor.
*
* Copyright(c) 2002,2003 Motorola Inc.
* Xianghua Xiao (x.xiao@motorola.com)
*
@@ -1520,14 +1522,39 @@ typedef struct ccsr_rio {
char res58[60176];
} ccsr_rio_t;
/* Quick Engine Block Pin Muxing Registers (0xe_0100 - 0xe_01bf) */
typedef struct par_io {
uint cpodr; /* 0x100 */
uint cpdat; /* 0x104 */
uint cpdir1; /* 0x108 */
uint cpdir2; /* 0x10c */
uint cppar1; /* 0x110 */
uint cppar2; /* 0x114 */
char res[8];
}par_io_t;
/*
* Global Utilities Register Block(0xe_0000-0xf_ffff)
*/
typedef struct ccsr_gur {
uint porpllsr; /* 0xe0000 - POR PLL ratio status register */
uint porbmsr; /* 0xe0004 - POR boot mode status register */
#define MPC85xx_PORBMSR_HA 0x00070000
uint porimpscr; /* 0xe0008 - POR I/O impedance status and control register */
uint pordevsr; /* 0xe000c - POR I/O device status regsiter */
#define MPC85xx_PORDEVSR_SGMII1_DIS 0x20000000
#define MPC85xx_PORDEVSR_SGMII2_DIS 0x10000000
#define MPC85xx_PORDEVSR_SGMII3_DIS 0x08000000
#define MPC85xx_PORDEVSR_SGMII4_DIS 0x04000000
#define MPC85xx_PORDEVSR_IO_SEL 0x00380000
#define MPC85xx_PORDEVSR_PCI2_ARB 0x00040000
#define MPC85xx_PORDEVSR_PCI1_ARB 0x00020000
#define MPC85xx_PORDEVSR_PCI1_PCI32 0x00010000
#define MPC85xx_PORDEVSR_PCI1_SPD 0x00008000
#define MPC85xx_PORDEVSR_PCI2_SPD 0x00004000
#define MPC85xx_PORDEVSR_DRAM_RTYPE 0x00000060
#define MPC85xx_PORDEVSR_RIO_CTLS 0x00000008
#define MPC85xx_PORDEVSR_RIO_DEV_ID 0x00000007
uint pordbgmsr; /* 0xe0010 - POR debug mode status register */
char res1[12];
uint gpporcr; /* 0xe0020 - General-purpose POR configuration register */
@@ -1541,6 +1568,25 @@ typedef struct ccsr_gur {
uint pmuxcr; /* 0xe0060 - Alternate function signal multiplex control */
char res6[12];
uint devdisr; /* 0xe0070 - Device disable control */
#define MPC85xx_DEVDISR_PCI1 0x80000000
#define MPC85xx_DEVDISR_PCI2 0x40000000
#define MPC85xx_DEVDISR_PCIE 0x20000000
#define MPC85xx_DEVDISR_LBC 0x08000000
#define MPC85xx_DEVDISR_PCIE2 0x04000000
#define MPC85xx_DEVDISR_PCIE3 0x02000000
#define MPC85xx_DEVDISR_SEC 0x01000000
#define MPC85xx_DEVDISR_SRIO 0x00080000
#define MPC85xx_DEVDISR_RMSG 0x00040000
#define MPC85xx_DEVDISR_DDR 0x00010000
#define MPC85xx_DEVDISR_CPU 0x00008000
#define MPC85xx_DEVDISR_TB 0x00004000
#define MPC85xx_DEVDISR_DMA 0x00000400
#define MPC85xx_DEVDISR_TSEC1 0x00000080
#define MPC85xx_DEVDISR_TSEC2 0x00000040
#define MPC85xx_DEVDISR_TSEC3 0x00000020
#define MPC85xx_DEVDISR_TSEC4 0x00000010
#define MPC85xx_DEVDISR_I2C 0x00000004
#define MPC85xx_DEVDISR_DUART 0x00000002
char res7[12];
uint powmgtcsr; /* 0xe0080 - Power management status and control register */
char res8[12];
@@ -1548,7 +1594,15 @@ typedef struct ccsr_gur {
char res9[12];
uint pvr; /* 0xe00a0 - Processor version register */
uint svr; /* 0xe00a4 - System version register */
char res10[3416];
char res10a[8];
uint rstcr; /* 0xe00b0 - Reset control register */
#ifdef CONFIG_MPC8568
char res10b[76];
par_io_t qe_par_io[7]; /* 0xe0100 - 0xe01bf */
char res10c[3136];
#else
char res10b[3404];
#endif
uint clkocr; /* 0xe0e00 - Clock out select register */
char res11[12];
uint ddrdllcr; /* 0xe0e10 - DDR DLL control register */
@@ -1560,7 +1614,7 @@ typedef struct ccsr_gur {
uint ddrioovcr; /* 0xe0f24 - DDR IO Override Control */
uint res14; /* 0xe0f28 */
uint tsec34ioovcr; /* 0xe0f2c - eTSEC 3/4 IO override control */
char res15[61651];
char res15[61648]; /* 0xe0f30 to 0xefffff */
} ccsr_gur_t;
#define PORDEVSR_PCI (0x00800000) /* PCI Mode */

16
include/asm-ppc/immap_86xx.h
View File

@@ -1257,9 +1257,12 @@ typedef struct ccsr_gur {
uint porpllsr; /* 0xe0000 - POR PLL ratio status register */
uint porbmsr; /* 0xe0004 - POR boot mode status register */
#define MPC86xx_PORBMSR_HA 0x00060000
#define MPC85xx_PORBMSR_HA 0x00070000
uint porimpscr; /* 0xe0008 - POR I/O impedance status and control register */
uint pordevsr; /* 0xe000c - POR I/O device status regsiter */
#define MPC86xx_PORDEVSR_IO_SEL 0x000F0000
#define MPC86xx_PORDEVSR_IO_SEL 0x000F0000
#define MPC85xx_PORDEVSR_IO_SEL 0x00380000 /* 85xx platform type */
#define MPC86xx_PORDEVSR_CORE1TE 0x00000080 /* ASMP (Core1 addr trans) */
uint pordbgmsr; /* 0xe0010 - POR debug mode status register */
char res1[12];
uint gpporcr; /* 0xe0020 - General-purpose POR configuration register */
@@ -1273,8 +1276,11 @@ typedef struct ccsr_gur {
uint pmuxcr; /* 0xe0060 - Alternate function signal multiplex control */
char res6[12];
uint devdisr; /* 0xe0070 - Device disable control */
#define MPC86xx_DEVDISR_PCIEX1 0x80000000
#define MPC86xx_DEVDISR_PCIEX2 0x40000000
#define MPC86xx_DEVDISR_PCIEX1 0x80000000
#define MPC86xx_DEVDISR_PCIEX2 0x40000000
#define MPC86xx_DEVDISR_PCI1 0x80000000
#define MPC86xx_DEVDISR_PCIE1 0x40000000
#define MPC86xx_DEVDISR_PCIE2 0x20000000
char res7[12];
uint powmgtcsr; /* 0xe0080 - Power management status and control register */
char res8[12];
@@ -1282,7 +1288,9 @@ typedef struct ccsr_gur {
char res9[12];
uint pvr; /* 0xe00a0 - Processor version register */
uint svr; /* 0xe00a4 - System version register */
char res10[3416];
char res10a[1880];
uint clkdvdr; /* 0xe0800 - Clock Divide register */
char res10b[1532];
uint clkocr; /* 0xe0e00 - Clock out select register */
char res11[12];
uint ddrdllcr; /* 0xe0e10 - DDR DLL control register */

150
include/asm-ppc/immap_fsl_pci.h Normal file
View File

@@ -0,0 +1,150 @@
/* (C) Copyright 2007 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#ifndef __IMMAP_85xx_fsl_pci__
#define __IMMAP_85xx_fsl_pci__
/*
* Common PCI/PCIE Register structure for mpc85xx and mpc86xx
*/
/*
* PCI Translation Registers
*/
typedef struct pci_outbound_window {
u32 potar; /* 0x00 - Address */
u32 potear; /* 0x04 - Address Extended */
u32 powbar; /* 0x08 - Window Base Address */
u32 res1;
u32 powar; /* 0x10 - Window Attributes */
#define POWAR_EN 0x80000000
#define POWAR_IO_READ 0x00080000
#define POWAR_MEM_READ 0x00040000
#define POWAR_IO_WRITE 0x00008000
#define POWAR_MEM_WRITE 0x00004000
u32 res2[3];
} pot_t;
typedef struct pci_inbound_window {
u32 pitar; /* 0x00 - Address */
u32 res1;
u32 piwbar; /* 0x08 - Window Base Address */
u32 piwbear; /* 0x0c - Window Base Address Extended */
u32 piwar; /* 0x10 - Window Attributes */
#define PIWAR_EN 0x80000000
#define PIWAR_PF 0x20000000
#define PIWAR_LOCAL 0x00f00000
#define PIWAR_READ_SNOOP 0x00050000
#define PIWAR_WRITE_SNOOP 0x00005000
u32 res2[3];
} pit_t;
/* PCI/PCI Express Registers */
typedef struct ccsr_pci {
u32 cfg_addr; /* 0x000 - PCI Configuration Address Register */
u32 cfg_data; /* 0x004 - PCI Configuration Data Register */
u32 int_ack; /* 0x008 - PCI Interrupt Acknowledge Register */
u32 out_comp_to; /* 0x00C - PCI Outbound Completion Timeout Register */
u32 out_conf_to; /* 0x010 - PCI Configuration Timeout Register */
u32 config; /* 0x014 - PCIE CONFIG Register */
char res2[8];
u32 pme_msg_det; /* 0x020 - PCIE PME & message detect register */
u32 pme_msg_dis; /* 0x024 - PCIE PME & message disable register */
u32 pme_msg_int_en; /* 0x028 - PCIE PME & message interrupt enable register */
u32 pm_command; /* 0x02c - PCIE PM Command register */
char res4[3016]; /* (- #xbf8 #x30)3016 */
u32 block_rev1; /* 0xbf8 - PCIE Block Revision register 1 */
u32 block_rev2; /* 0xbfc - PCIE Block Revision register 2 */
pot_t pot[5]; /* 0xc00 - 0xc9f Outbound ATMU's 0, 1, 2, 3, and 4 */
u32 res5[64];
pit_t pit[3]; /* 0xda0 - 0xdff Inbound ATMU's 3, 2, and 1 */
#define PIT3 0
#define PIT2 1
#define PIT1 2
#if 0
u32 potar0; /* 0xc00 - PCI Outbound Transaction Address Register 0 */
u32 potear0; /* 0xc04 - PCI Outbound Translation Extended Address Register 0 */
char res5[8];
u32 powar0; /* 0xc10 - PCI Outbound Window Attributes Register 0 */
char res6[12];
u32 potar1; /* 0xc20 - PCI Outbound Transaction Address Register 1 */
u32 potear1; /* 0xc24 - PCI Outbound Translation Extended Address Register 1 */
u32 powbar1; /* 0xc28 - PCI Outbound Window Base Address Register 1 */
char res7[4];
u32 powar1; /* 0xc30 - PCI Outbound Window Attributes Register 1 */
char res8[12];
u32 potar2; /* 0xc40 - PCI Outbound Transaction Address Register 2 */
u32 potear2; /* 0xc44 - PCI Outbound Translation Extended Address Register 2 */
u32 powbar2; /* 0xc48 - PCI Outbound Window Base Address Register 2 */
char res9[4];
u32 powar2; /* 0xc50 - PCI Outbound Window Attributes Register 2 */
char res10[12];
u32 potar3; /* 0xc60 - PCI Outbound Transaction Address Register 3 */
u32 potear3; /* 0xc64 - PCI Outbound Translation Extended Address Register 3 */
u32 powbar3; /* 0xc68 - PCI Outbound Window Base Address Register 3 */
char res11[4];
u32 powar3; /* 0xc70 - PCI Outbound Window Attributes Register 3 */
char res12[12];
u32 potar4; /* 0xc80 - PCI Outbound Transaction Address Register 4 */
u32 potear4; /* 0xc84 - PCI Outbound Translation Extended Address Register 4 */
u32 powbar4; /* 0xc88 - PCI Outbound Window Base Address Register 4 */
char res13[4];
u32 powar4; /* 0xc90 - PCI Outbound Window Attributes Register 4 */
char res14[268];
u32 pitar3; /* 0xda0 - PCI Inbound Translation Address Register 3 */
char res15[4];
u32 piwbar3; /* 0xda8 - PCI Inbound Window Base Address Register 3 */
u32 piwbear3; /* 0xdac - PCI Inbound Window Base Extended Address Register 3 */
u32 piwar3; /* 0xdb0 - PCI Inbound Window Attributes Register 3 */
char res16[12];
u32 pitar2; /* 0xdc0 - PCI Inbound Translation Address Register 2 */
char res17[4];
u32 piwbar2; /* 0xdc8 - PCI Inbound Window Base Address Register 2 */
u32 piwbear2; /* 0xdcc - PCI Inbound Window Base Extended Address Register 2 */
u32 piwar2; /* 0xdd0 - PCI Inbound Window Attributes Register 2 */
char res18[12];
u32 pitar1; /* 0xde0 - PCI Inbound Translation Address Register 1 */
char res19[4];
u32 piwbar1; /* 0xde8 - PCI Inbound Window Base Address Register 1 */
char res20[4];
u32 piwar1; /* 0xdf0 - PCI Inbound Window Attributes Register 1 */
char res21[12];
#endif
u32 pedr; /* 0xe00 - PCI Error Detect Register */
u32 pecdr; /* 0xe04 - PCI Error Capture Disable Register */
u32 peer; /* 0xe08 - PCI Error Interrupt Enable Register */
u32 peattrcr; /* 0xe0c - PCI Error Attributes Capture Register */
u32 peaddrcr; /* 0xe10 - PCI Error Address Capture Register */
/* u32 perr_disr * 0xe10 - PCIE Erorr Disable Register */
u32 peextaddrcr; /* 0xe14 - PCI Error Extended Address Capture Register */
u32 pedlcr; /* 0xe18 - PCI Error Data Low Capture Register */
u32 pedhcr; /* 0xe1c - PCI Error Error Data High Capture Register */
u32 gas_timr; /* 0xe20 - PCI Gasket Timer Register */
/* u32 perr_cap_stat; * 0xe20 - PCIE Error Capture Status Register */
char res22[4];
u32 perr_cap0; /* 0xe28 - PCIE Error Capture Register 0 */
u32 perr_cap1; /* 0xe2c - PCIE Error Capture Register 1 */
u32 perr_cap2; /* 0xe30 - PCIE Error Capture Register 2 */
u32 perr_cap3; /* 0xe34 - PCIE Error Capture Register 3 */
char res23[456]; /* (- #x1000 #xe38) 456 */
} ccsr_fsl_pci_t;
#endif /*__IMMAP_fsl_pci__*/

20
include/asm-ppc/immap_qe.h
View File

@@ -281,6 +281,17 @@ typedef struct ucc_slow {
u8 res4[0x200 - 0x091];
} __attribute__ ((packed)) ucc_slow_t;
typedef struct ucc_mii_mng {
u32 miimcfg; /* MII management configuration reg */
u32 miimcom; /* MII management command reg */
u32 miimadd; /* MII management address reg */
u32 miimcon; /* MII management control reg */
u32 miimstat; /* MII management status reg */
u32 miimind; /* MII management indication reg */
u32 ifctl; /* interface control reg */
u32 ifstat; /* interface statux reg */
} __attribute__ ((packed))uec_mii_t;
typedef struct ucc_ethernet {
u32 maccfg1; /* mac configuration reg. 1 */
u32 maccfg2; /* mac configuration reg. 2 */
@@ -540,14 +551,21 @@ typedef struct qe_immap {
u8 res14[0x300];
u8 res15[0x3A00];
u8 res16[0x8000]; /* 0x108000 - 0x110000 */
#if defined(CONFIG_MPC8568)
u8 muram[0x10000]; /* 0x1_0000 - 0x2_0000 Multi-user RAM */
u8 res17[0x20000]; /* 0x2_0000 - 0x4_0000 */
#else
u8 muram[0xC000]; /* 0x110000 - 0x11C000 Multi-user RAM */
u8 res17[0x24000]; /* 0x11C000 - 0x140000 */
u8 res18[0xC0000]; /* 0x140000 - 0x200000 */
#endif
} __attribute__ ((packed)) qe_map_t;
extern qe_map_t *qe_immr;
#if defined(CONFIG_MPC8360)
#if defined(CONFIG_MPC8568)
#define QE_MURAM_SIZE 0x10000UL
#elif defined(CONFIG_MPC8360)
#define QE_MURAM_SIZE 0xc000UL
#elif defined(CONFIG_MPC832X)
#define QE_MURAM_SIZE 0x4000UL

92
include/asm-ppc/io.h
View File

@@ -13,6 +13,9 @@
#define SIO_CONFIG_RA 0x398
#define SIO_CONFIG_RD 0x399
#ifndef _IO_BASE
#define _IO_BASE 0
#endif
#define readb(addr) in_8((volatile u8 *)(addr))
#define writeb(b,addr) out_8((volatile u8 *)(addr), (b))
@@ -105,6 +108,11 @@ static inline void sync(void)
__asm__ __volatile__ ("sync" : : : "memory");
}
static inline void isync(void)
{
__asm__ __volatile__ ("isync" : : : "memory");
}
/* Enforce in-order execution of data I/O.
* No distinction between read/write on PPC; use eieio for all three.
*/
@@ -114,74 +122,90 @@ static inline void sync(void)
/*
* 8, 16 and 32 bit, big and little endian I/O operations, with barrier.
*
* Read operations have additional twi & isync to make sure the read
* is actually performed (i.e. the data has come back) before we start
* executing any following instructions.
*/
extern inline int in_8(volatile u8 *addr)
#define __iomem
extern inline int in_8(const volatile unsigned char __iomem *addr)
{
int ret;
int ret;
__asm__ __volatile__("lbz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr));
return ret;
__asm__ __volatile__(
"sync; lbz%U1%X1 %0,%1;\n"
"twi 0,%0,0;\n"
"isync" : "=r" (ret) : "m" (*addr));
return ret;
}
extern inline void out_8(volatile u8 *addr, int val)
extern inline void out_8(volatile unsigned char __iomem *addr, int val)
{
__asm__ __volatile__("stb%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
__asm__ __volatile__("stb%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
}
extern inline int in_le16(volatile u16 *addr)
extern inline int in_le16(const volatile unsigned short __iomem *addr)
{
int ret;
int ret;
__asm__ __volatile__("lhbrx %0,0,%1; eieio" : "=r" (ret) :
"r" (addr), "m" (*addr));
return ret;
__asm__ __volatile__("sync; lhbrx %0,0,%1;\n"
"twi 0,%0,0;\n"
"isync" : "=r" (ret) :
"r" (addr), "m" (*addr));
return ret;
}
extern inline int in_be16(volatile u16 *addr)
extern inline int in_be16(const volatile unsigned short __iomem *addr)
{
int ret;
int ret;
__asm__ __volatile__("lhz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr));
return ret;
__asm__ __volatile__("sync; lhz%U1%X1 %0,%1;\n"
"twi 0,%0,0;\n"
"isync" : "=r" (ret) : "m" (*addr));
return ret;
}
extern inline void out_le16(volatile u16 *addr, int val)
extern inline void out_le16(volatile unsigned short __iomem *addr, int val)
{
__asm__ __volatile__("sthbrx %1,0,%2; eieio" : "=m" (*addr) :
"r" (val), "r" (addr));
__asm__ __volatile__("sync; sthbrx %1,0,%2" : "=m" (*addr) :
"r" (val), "r" (addr));
}
extern inline void out_be16(volatile u16 *addr, int val)
extern inline void out_be16(volatile unsigned short __iomem *addr, int val)
{
__asm__ __volatile__("sth%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
__asm__ __volatile__("sync; sth%U0%X0 %1,%0" : "=m" (*addr) : "r" (val));
}
extern inline unsigned in_le32(volatile u32 *addr)
extern inline unsigned in_le32(const volatile unsigned __iomem *addr)
{
unsigned ret;
unsigned ret;
__asm__ __volatile__("lwbrx %0,0,%1; eieio" : "=r" (ret) :
"r" (addr), "m" (*addr));
return ret;
__asm__ __volatile__("sync; lwbrx %0,0,%1;\n"
"twi 0,%0,0;\n"
"isync" : "=r" (ret) :
"r" (addr), "m" (*addr));
return ret;
}
extern inline unsigned in_be32(volatile u32 *addr)
extern inline unsigned in_be32(const volatile unsigned __iomem *addr)
{
unsigned ret;
unsigned ret;
__asm__ __volatile__("lwz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr));
return ret;
__asm__ __volatile__("sync; lwz%U1%X1 %0,%1;\n"
"twi 0,%0,0;\n"
"isync" : "=r" (ret) : "m" (*addr));
return ret;
}
extern inline void out_le32(volatile unsigned *addr, int val)
extern inline void out_le32(volatile unsigned __iomem *addr, int val)
{
__asm__ __volatile__("stwbrx %1,0,%2; eieio" : "=m" (*addr) :
"r" (val), "r" (addr));
__asm__ __volatile__("sync; stwbrx %1,0,%2" : "=m" (*addr) :
"r" (val), "r" (addr));
}
extern inline void out_be32(volatile unsigned *addr, int val)
extern inline void out_be32(volatile unsigned __iomem *addr, int val)
{
__asm__ __volatile__("stw%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
__asm__ __volatile__("sync; stw%U0%X0 %1,%0" : "=m" (*addr) : "r" (val));
}
#endif

3
include/asm-ppc/mmu.h
View File

@@ -645,6 +645,9 @@ void mttlb3(unsigned long index, unsigned long value);
unsigned long mftlb1(unsigned long index);
unsigned long mftlb2(unsigned long index);
unsigned long mftlb3(unsigned long index);
void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value);
void remove_tlb(u32 vaddr, u32 size);
#endif /* __ASSEMBLY__ */
#endif /* CONFIG_440 */

76
include/asm-ppc/processor.h
View File

@@ -35,18 +35,18 @@
#define MSR_DWE (1<<10) /* Debug Wait Enable (4xx) */
#define MSR_UBLE (1<<10) /* BTB lock enable (e500) */
#define MSR_BE (1<<9) /* Branch Trace */
#define MSR_DE (1<<9) /* Debug Exception Enable */
#define MSR_DE (1<<9) /* Debug Exception Enable */
#define MSR_FE1 (1<<8) /* Floating Exception mode 1 */
#define MSR_IP (1<<6) /* Exception prefix 0x000/0xFFF */
#define MSR_IR (1<<5) /* Instruction Relocate */
#define MSR_IR (1<<5) /* Instruction Relocate */
#define MSR_IS (1<<5) /* Book E Instruction space */
#define MSR_DR (1<<4) /* Data Relocate */
#define MSR_DR (1<<4) /* Data Relocate */
#define MSR_DS (1<<4) /* Book E Data space */
#define MSR_PE (1<<3) /* Protection Enable */
#define MSR_PX (1<<2) /* Protection Exclusive Mode */
#define MSR_PMM (1<<2) /* Performance monitor mark bit (e500) */
#define MSR_RI (1<<1) /* Recoverable Exception */
#define MSR_LE (1<<0) /* Little Endian */
#define MSR_LE (1<<0) /* Little Endian */
#ifdef CONFIG_APUS_FAST_EXCEPT
#define MSR_ MSR_ME|MSR_IP|MSR_RI
@@ -58,7 +58,6 @@
#else
#define MSR_KERNEL MSR_ME
#endif
#define MSR_USER MSR_KERNEL|MSR_PR|MSR_EE
/* Floating Point Status and Control Register (FPSCR) Fields */
@@ -123,9 +122,9 @@
#define DBCR_EDM 0x80000000
#define DBCR_IDM 0x40000000
#define DBCR_RST(x) (((x) & 0x3) << 28)
#define DBCR_RST_NONE 0
#define DBCR_RST_CORE 1
#define DBCR_RST_CHIP 2
#define DBCR_RST_NONE 0
#define DBCR_RST_CORE 1
#define DBCR_RST_CHIP 2
#define DBCR_RST_SYSTEM 3
#define DBCR_IC 0x08000000 /* Instruction Completion Debug Evnt */
#define DBCR_BT 0x04000000 /* Branch Taken Debug Event */
@@ -218,12 +217,14 @@
#define HID0_DPM (1<<20)
#define HID0_ICE (1<<HID0_ICE_SHIFT) /* Instruction Cache Enable */
#define HID0_DCE (1<<HID0_DCE_SHIFT) /* Data Cache Enable */
#define HID0_TBEN (1<<14) /* Time Base Enable */
#define HID0_ILOCK (1<<13) /* Instruction Cache Lock */
#define HID0_DLOCK (1<<HID0_DLOCK_SHIFT) /* Data Cache Lock */
#define HID0_ICFI (1<<11) /* Instr. Cache Flash Invalidate */
#define HID0_DCFI (1<<10) /* Data Cache Flash Invalidate */
#define HID0_DCI HID0_DCFI
#define HID0_SPD (1<<9) /* Speculative disable */
#define HID0_ENMAS7 (1<<7) /* Enable MAS7 Update for 36-bit phys */
#define HID0_SGE (1<<7) /* Store Gathering Enable */
#define HID0_SIED HID_SGE /* Serial Instr. Execution [Disable] */
#define HID0_DCFA (1<<6) /* Data Cache Flush Assist */
@@ -266,7 +267,7 @@
#define SPRN_ICMP 0x3D5 /* Instruction TLB Compare Register */
#define SPRN_ICTC 0x3FB /* Instruction Cache Throttling Control Reg */
#define SPRN_IMISS 0x3D4 /* Instruction TLB Miss Register */
#define SPRN_IMMR 0x27E /* Internal Memory Map Register */
#define SPRN_IMMR 0x27E /* Internal Memory Map Register */
#define SPRN_LDSTCR 0x3F8 /* Load/Store Control Register */
#define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Regsiter */
#define SPRN_LR 0x008 /* Link Register */
@@ -308,7 +309,7 @@
#define SPRN_SRR0 0x01A /* Save/Restore Register 0 */
#define SPRN_SRR1 0x01B /* Save/Restore Register 1 */
#define SPRN_SRR2 0x3DE /* Save/Restore Register 2 */
#define SPRN_SRR3 0x3DF /* Save/Restore Register 3 */
#define SPRN_SRR3 0x3DF /* Save/Restore Register 3 */
#ifdef CONFIG_BOOKE
#define SPRN_SVR 0x3FF /* System Version Register */
#else
@@ -451,10 +452,23 @@
#define SPRN_PID1 0x279 /* Process ID Register 1 */
#define SPRN_PID2 0x27a /* Process ID Register 2 */
#define SPRN_MCSR 0x23c /* Machine Check Syndrome register */
#define SPRN_MCAR 0x23d /* Machine Check Address register */
#ifdef CONFIG_440
#define MCSR_MCS 0x80000000 /* Machine Check Summary */
#define MCSR_IB 0x40000000 /* Instruction PLB Error */
#define MCSR_DRB 0x20000000 /* Data Read PLB Error */
#define MCSR_DWB 0x10000000 /* Data Write PLB Error */
#define MCSR_TLBP 0x08000000 /* TLB Parity Error */
#define MCSR_ICP 0x04000000 /* I-Cache Parity Error */
#define MCSR_DCSP 0x02000000 /* D-Cache Search Parity Error */
#define MCSR_DCFP 0x01000000 /* D-Cache Flush Parity Error */
#define MCSR_IMPE 0x00800000 /* Imprecise Machine Check Exception */
#endif
#define ESR_ST 0x00800000 /* Store Operation */
#if defined(CONFIG_MPC86xx)
#define SPRN_MSSCRO 0x3f6
#define SPRN_MSSCR0 0x3f6
#define SPRN_MSSSR0 0x3f7
#endif
@@ -484,17 +498,17 @@
#define DBCR0 SPRN_DBCR0 /* Debug Control Register 0 */
#define DBCR1 SPRN_DBCR1 /* Debug Control Register 1 */
#define DBSR SPRN_DBSR /* Debug Status Register */
#define DCMP SPRN_DCMP /* Data TLB Compare Register */
#define DEC SPRN_DEC /* Decrement Register */
#define DMISS SPRN_DMISS /* Data TLB Miss Register */
#define DCMP SPRN_DCMP /* Data TLB Compare Register */
#define DEC SPRN_DEC /* Decrement Register */
#define DMISS SPRN_DMISS /* Data TLB Miss Register */
#define DSISR SPRN_DSISR /* Data Storage Interrupt Status Register */
#define EAR SPRN_EAR /* External Address Register */
#define EAR SPRN_EAR /* External Address Register */
#define ESR SPRN_ESR /* Exception Syndrome Register */
#define HASH1 SPRN_HASH1 /* Primary Hash Address Register */
#define HASH2 SPRN_HASH2 /* Secondary Hash Address Register */
#define HID0 SPRN_HID0 /* Hardware Implementation Register 0 */
#define HID1 SPRN_HID1 /* Hardware Implementation Register 1 */
#define IABR SPRN_IABR /* Instruction Address Breakpoint Register */
#define IABR SPRN_IABR /* Instruction Address Breakpoint Register */
#define IAC1 SPRN_IAC1 /* Instruction Address Register 1 */
#define IAC2 SPRN_IAC2 /* Instruction Address Register 2 */
#define IBAT0L SPRN_IBAT0L /* Instruction BAT 0 Lower Register */
@@ -511,17 +525,17 @@
#define IBAT5U SPRN_IBAT5U /* Instruction BAT 5 Upper Register */
#define IBAT6L SPRN_IBAT6L /* Instruction BAT 6 Lower Register */
#define IBAT6U SPRN_IBAT6U /* Instruction BAT 6 Upper Register */
#define IBAT7L SPRN_IBAT7L /* Instruction BAT 7 Lower Register */
#define IBAT7L SPRN_IBAT7L /* Instruction BAT 7 Lower Register */
#define IBAT7U SPRN_IBAT7U /* Instruction BAT 7 Lower Register */
#define ICMP SPRN_ICMP /* Instruction TLB Compare Register */
#define IMISS SPRN_IMISS /* Instruction TLB Miss Register */
#define IMMR SPRN_IMMR /* PPC 860/821 Internal Memory Map Register */
#define IMMR SPRN_IMMR /* PPC 860/821 Internal Memory Map Register */
#define LDSTCR SPRN_LDSTCR /* Load/Store Control Register */
#define L2CR SPRN_L2CR /* PPC 750 L2 control register */
#define L2CR SPRN_L2CR /* PPC 750 L2 control register */
#define LR SPRN_LR
#define MBAR SPRN_MBAR /* System memory base address */
#if defined(CONFIG_MPC86xx)
#define MSSCR0 SPRN_MSSCRO
#define MSSCR0 SPRN_MSSCR0
#endif
#if defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
#define PIR SPRN_PIR
@@ -529,7 +543,7 @@
#define SVR SPRN_SVR /* System-On-Chip Version Register */
#define PVR SPRN_PVR /* Processor Version */
#define RPA SPRN_RPA /* Required Physical Address Register */
#define SDR1 SPRN_SDR1 /* MMU hash base register */
#define SDR1 SPRN_SDR1 /* MMU hash base register */
#define SPR0 SPRN_SPRG0 /* Supervisor Private Registers */
#define SPR1 SPRN_SPRG1
#define SPR2 SPRN_SPRG2
@@ -544,6 +558,8 @@
#define SPRG7 SPRN_SPRG7
#define SRR0 SPRN_SRR0 /* Save and Restore Register 0 */
#define SRR1 SPRN_SRR1 /* Save and Restore Register 1 */
#define SRR2 SPRN_SRR2 /* Save and Restore Register 2 */
#define SRR3 SPRN_SRR3 /* Save and Restore Register 3 */
#define SVR SPRN_SVR /* System Version Register */
#define TBRL SPRN_TBRL /* Time Base Read Lower Register */
#define TBRU SPRN_TBRU /* Time Base Read Upper Register */
@@ -598,7 +614,7 @@
#define IVOR35 SPRN_IVOR35
#define MCSRR0 SPRN_MCSRR0
#define MCSRR1 SPRN_MCSRR1
#define L1CSR0 SPRN_L1CSR0
#define L1CSR0 SPRN_L1CSR0
#define L1CSR1 SPRN_L1CSR1
#define MCSR SPRN_MCSR
#define MMUCSR0 SPRN_MMUCSR0
@@ -607,7 +623,7 @@
#define PID1 SPRN_PID1
#define PID2 SPRN_PID2
#define MAS0 SPRN_MAS0
#define MAS1 SPRN_MAS1
#define MAS1 SPRN_MAS1
#define MAS2 SPRN_MAS2
#define MAS3 SPRN_MAS3
#define MAS4 SPRN_MAS4
@@ -615,11 +631,17 @@
#define MAS6 SPRN_MAS6
#define MAS7 SPRN_MAS7
#if defined(CONFIG_4xx) || defined(CONFIG_44x) || defined(CONFIG_MPC85xx)
#define DAR_DEAR DEAR
#else
#define DAR_DEAR DAR
#endif
/* Device Control Registers */
#define DCRN_BEAR 0x090 /* Bus Error Address Register */
#define DCRN_BESR 0x091 /* Bus Error Syndrome Register */
#define BESR_DSES 0x80000000 /* Data-Side Error Status */
#define BESR_DSES 0x80000000 /* Data-Side Error Status */
#define BESR_DMES 0x40000000 /* DMA Error Status */
#define BESR_RWS 0x20000000 /* Read/Write Status */
#define BESR_ETMASK 0x1C000000 /* Error Type */
@@ -676,8 +698,8 @@
#define IOCR_E3LP 0x01000000
#define IOCR_E4TE 0x00800000
#define IOCR_E4LP 0x00400000
#define IOCR_EDT 0x00080000
#define IOCR_SOR 0x00040000
#define IOCR_EDT 0x00080000
#define IOCR_SOR 0x00040000
#define IOCR_EDO 0x00008000
#define IOCR_2XC 0x00004000
#define IOCR_ATC 0x00002000
@@ -802,7 +824,7 @@
#define PVR_823 PVR_821
#define PVR_850 PVR_821
#define PVR_860 PVR_821
#define PVR_7400 0x000C0000
#define PVR_7400 0x000C0000
#define PVR_8240 0x00810100
/*

69
include/at45.h Normal file
View File

@@ -0,0 +1,69 @@
#ifndef _AT45_H_
#define _AT45_H_
#ifdef DATAFLASH_MMC_SELECT
extern void AT91F_SelectMMC(void);
extern void AT91F_SelectSPI(void);
extern int AT91F_GetMuxStatus(void);
#endif
extern void AT91F_SpiInit(void);
extern void AT91F_SpiEnable(int cs);
extern unsigned int AT91F_SpiWrite ( AT91PS_DataflashDesc pDesc );
extern AT91S_DataFlashStatus AT91F_DataFlashSendCommand(
AT91PS_DataFlash pDataFlash,
unsigned char OpCode,
unsigned int CmdSize,
unsigned int DataflashAddress);
extern AT91S_DataFlashStatus AT91F_DataFlashGetStatus (
AT91PS_DataflashDesc pDesc);
extern AT91S_DataFlashStatus AT91F_DataFlashWaitReady (
AT91PS_DataflashDesc pDataFlashDesc,
unsigned int timeout);
extern AT91S_DataFlashStatus AT91F_DataFlashContinuousRead (
AT91PS_DataFlash pDataFlash,
int src,
unsigned char *dataBuffer,
int sizeToRead );
extern AT91S_DataFlashStatus AT91F_DataFlashPagePgmBuf(
AT91PS_DataFlash pDataFlash,
unsigned char *src,
unsigned int dest,
unsigned int SizeToWrite);
extern AT91S_DataFlashStatus AT91F_MainMemoryToBufferTransfert(
AT91PS_DataFlash pDataFlash,
unsigned char BufferCommand,
unsigned int page);
extern AT91S_DataFlashStatus AT91F_DataFlashWriteBuffer (
AT91PS_DataFlash pDataFlash,
unsigned char BufferCommand,
unsigned char *dataBuffer,
unsigned int bufferAddress,
int SizeToWrite );
extern AT91S_DataFlashStatus AT91F_PageErase(
AT91PS_DataFlash pDataFlash,
unsigned int page);
extern AT91S_DataFlashStatus AT91F_BlockErase(
AT91PS_DataFlash pDataFlash,
unsigned int block);
extern AT91S_DataFlashStatus AT91F_WriteBufferToMain (
AT91PS_DataFlash pDataFlash,
unsigned char BufferCommand,
unsigned int dest );
extern AT91S_DataFlashStatus AT91F_PartialPageWrite (
AT91PS_DataFlash pDataFlash,
unsigned char *src,
unsigned int dest,
unsigned int size);
extern AT91S_DataFlashStatus AT91F_DataFlashWrite(
AT91PS_DataFlash pDataFlash,
unsigned char *src,
int dest,
int size );
extern int AT91F_DataFlashRead(
AT91PS_DataFlash pDataFlash,
unsigned long addr,
unsigned long size,
char *buffer);
extern int AT91F_DataflashProbe(int cs, AT91PS_DataflashDesc pDesc);
#endif

60
include/ata.h
View File

@@ -83,6 +83,66 @@
#define ATA_DEVICE(x) ((x & 1)<<4)
#define ATA_LBA 0xE0
enum {
ATA_MAX_DEVICES = 1, /* per bus/port */
ATA_MAX_PRD = 256, /* we could make these 256/256 */
ATA_SECT_SIZE = 256, /*256 words per sector */
/* bits in ATA command block registers */
ATA_HOB = (1 << 7), /* LBA48 selector */
ATA_NIEN = (1 << 1), /* disable-irq flag */
/*ATA_LBA = (1 << 6), */ /* LBA28 selector */
ATA_DEV1 = (1 << 4), /* Select Device 1 (slave) */
ATA_DEVICE_OBS = (1 << 7) | (1 << 5), /* obs bits in dev reg */
ATA_DEVCTL_OBS = (1 << 3), /* obsolete bit in devctl reg */
ATA_BUSY = (1 << 7), /* BSY status bit */
ATA_DRDY = (1 << 6), /* device ready */
ATA_DF = (1 << 5), /* device fault */
ATA_DRQ = (1 << 3), /* data request i/o */
ATA_ERR = (1 << 0), /* have an error */
ATA_SRST = (1 << 2), /* software reset */
ATA_ABORTED = (1 << 2), /* command aborted */
/* ATA command block registers */
ATA_REG_DATA = 0x00,
ATA_REG_ERR = 0x01,
ATA_REG_NSECT = 0x02,
ATA_REG_LBAL = 0x03,
ATA_REG_LBAM = 0x04,
ATA_REG_LBAH = 0x05,
ATA_REG_DEVICE = 0x06,
ATA_REG_STATUS = 0x07,
ATA_PCI_CTL_OFS = 0x02,
/* and their aliases */
ATA_REG_FEATURE = ATA_REG_ERR,
ATA_REG_CMD = ATA_REG_STATUS,
ATA_REG_BYTEL = ATA_REG_LBAM,
ATA_REG_BYTEH = ATA_REG_LBAH,
ATA_REG_DEVSEL = ATA_REG_DEVICE,
ATA_REG_IRQ = ATA_REG_NSECT,
/* SETFEATURES stuff */
SETFEATURES_XFER = 0x03,
XFER_UDMA_7 = 0x47,
XFER_UDMA_6 = 0x46,
XFER_UDMA_5 = 0x45,
XFER_UDMA_4 = 0x44,
XFER_UDMA_3 = 0x43,
XFER_UDMA_2 = 0x42,
XFER_UDMA_1 = 0x41,
XFER_UDMA_0 = 0x40,
XFER_MW_DMA_2 = 0x22,
XFER_MW_DMA_1 = 0x21,
XFER_MW_DMA_0 = 0x20,
XFER_PIO_4 = 0x0C,
XFER_PIO_3 = 0x0B,
XFER_PIO_2 = 0x0A,
XFER_PIO_1 = 0x09,
XFER_PIO_0 = 0x08,
XFER_SW_DMA_2 = 0x12,
XFER_SW_DMA_1 = 0x11,
XFER_SW_DMA_0 = 0x10,
XFER_PIO_SLOW = 0x00
};
/*
* ATA Commands (only mandatory commands listed here)
*/

185
include/cmd_confdefs.h
View File

@@ -1,185 +0,0 @@
/*
* (C) Copyright 2000-2002
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* Definitions for Configuring the monitor commands
*/
#ifndef _CMD_CONFIG_H
#define _CMD_CONFIG_H
/*
* Configurable monitor commands
*/
#define CFG_CMD_BDI 0x00000001ULL /* bdinfo */
#define CFG_CMD_LOADS 0x00000002ULL /* loads */
#define CFG_CMD_LOADB 0x00000004ULL /* loadb */
#define CFG_CMD_IMI 0x00000008ULL /* iminfo */
#define CFG_CMD_CACHE 0x00000010ULL /* icache, dcache */
#define CFG_CMD_FLASH 0x00000020ULL /* flinfo, erase, protect */
#define CFG_CMD_MEMORY 0x00000040ULL /* md, mm, nm, mw, cp, cmp, */
/* crc, base, loop, mtest */
#define CFG_CMD_NET 0x00000080ULL /* bootp, tftpboot, rarpboot */
#define CFG_CMD_ENV 0x00000100ULL /* saveenv */
#define CFG_CMD_KGDB 0x0000000000000200ULL /* kgdb */
#define CFG_CMD_PCMCIA 0x00000400ULL /* PCMCIA support */
#define CFG_CMD_IDE 0x00000800ULL /* IDE harddisk support */
#define CFG_CMD_PCI 0x00001000ULL /* pciinfo */
#define CFG_CMD_IRQ 0x00002000ULL /* irqinfo */
#define CFG_CMD_BOOTD 0x00004000ULL /* bootd */
#define CFG_CMD_CONSOLE 0x00008000ULL /* coninfo */
#define CFG_CMD_EEPROM 0x00010000ULL /* EEPROM read/write support */
#define CFG_CMD_ASKENV 0x00020000ULL /* ask for env variable */
#define CFG_CMD_RUN 0x00040000ULL /* run command in env variable */
#define CFG_CMD_ECHO 0x00080000ULL /* echo arguments */
#define CFG_CMD_I2C 0x00100000ULL /* I2C serial bus support */
#define CFG_CMD_REGINFO 0x00200000ULL /* Register dump */
#define CFG_CMD_IMMAP 0x00400000ULL /* IMMR dump support */
#define CFG_CMD_DATE 0x00800000ULL /* support for RTC, date/time...*/
#define CFG_CMD_DHCP 0x01000000ULL /* DHCP Support */
#define CFG_CMD_BEDBUG 0x02000000ULL /* Include BedBug Debugger */
#define CFG_CMD_FDC 0x04000000ULL /* Floppy Disk Support */
#define CFG_CMD_SCSI 0x08000000ULL /* SCSI Support */
#define CFG_CMD_AUTOSCRIPT 0x10000000ULL /* Autoscript Support */
#define CFG_CMD_MII 0x20000000ULL /* MII support */
#define CFG_CMD_SETGETDCR 0x40000000ULL /* DCR support on 4xx */
#define CFG_CMD_BSP 0x80000000ULL /* Board Specific functions */
#define CFG_CMD_ELF 0x0000000100000000ULL /* ELF (VxWorks) load/boot cmd */
#define CFG_CMD_MISC 0x0000000200000000ULL /* Misc functions like sleep etc*/
#define CFG_CMD_USB 0x0000000400000000ULL /* USB Support */
#define CFG_CMD_DOC 0x0000000800000000ULL /* Disk-On-Chip Support */
#define CFG_CMD_JFFS2 0x0000001000000000ULL /* JFFS2 Support */
#define CFG_CMD_DTT 0x0000002000000000ULL /* Digital Therm and Thermostat */
#define CFG_CMD_SDRAM 0x0000004000000000ULL /* SDRAM DIMM SPD info printout */
#define CFG_CMD_DIAG 0x0000008000000000ULL /* Diagnostics */
#define CFG_CMD_FPGA 0x0000010000000000ULL /* FPGA configuration Support */
#define CFG_CMD_HWFLOW 0x0000020000000000ULL /* RTS/CTS hw flow control */
#define CFG_CMD_SAVES 0x0000040000000000ULL /* save S record dump */
#define CFG_CMD_SPI 0x0000100000000000ULL /* SPI utility */
#define CFG_CMD_FDOS 0x0000200000000000ULL /* Floppy DOS support */
#define CFG_CMD_VFD 0x0000400000000000ULL /* VFD support (TRAB) */
#define CFG_CMD_NAND 0x0000800000000000ULL /* NAND support */
#define CFG_CMD_BMP 0x0001000000000000ULL /* BMP support */
#define CFG_CMD_PORTIO 0x0002000000000000ULL /* Port I/O */
#define CFG_CMD_PING 0x0004000000000000ULL /* ping support */
#define CFG_CMD_MMC 0x0008000000000000ULL /* MMC support */
#define CFG_CMD_FAT 0x0010000000000000ULL /* FAT support */
#define CFG_CMD_IMLS 0x0020000000000000ULL /* List all found images */
#define CFG_CMD_ITEST 0x0040000000000000ULL /* Integer (and string) test */
#define CFG_CMD_NFS 0x0080000000000000ULL /* NFS support */
#define CFG_CMD_REISER 0x0100000000000000ULL /* Reiserfs support */
#define CFG_CMD_CDP 0x0200000000000000ULL /* Cisco Discovery Protocol */
#define CFG_CMD_XIMG 0x0400000000000000ULL /* Load part of Multi Image */
#define CFG_CMD_UNIVERSE 0x0800000000000000ULL /* Tundra Universe Support */
#define CFG_CMD_EXT2 0x1000000000000000ULL /* EXT2 Support */
#define CFG_CMD_SNTP 0x2000000000000000ULL /* SNTP support */
#define CFG_CMD_DISPLAY 0x4000000000000000ULL /* Display support */
#define CFG_CMD_ALL 0xFFFFFFFFFFFFFFFFULL /* ALL commands */
/* Commands that are considered "non-standard" for some reason
* (memory hogs, requires special hardware, not fully tested, etc.)
*/
#define CFG_CMD_NONSTD (CFG_CMD_ASKENV | \
CFG_CMD_BEDBUG | \
CFG_CMD_BMP | \
CFG_CMD_BSP | \
CFG_CMD_CACHE | \
CFG_CMD_CDP | \
CFG_CMD_DATE | \
CFG_CMD_DHCP | \
CFG_CMD_DIAG | \
CFG_CMD_DISPLAY | \
CFG_CMD_DOC | \
CFG_CMD_DTT | \
CFG_CMD_EEPROM | \
CFG_CMD_ELF | \
CFG_CMD_EXT2 | \
CFG_CMD_FDC | \
CFG_CMD_FAT | \
CFG_CMD_FDOS | \
CFG_CMD_HWFLOW | \
CFG_CMD_I2C | \
CFG_CMD_IDE | \
CFG_CMD_IMMAP | \
CFG_CMD_IRQ | \
CFG_CMD_JFFS2 | \
CFG_CMD_KGDB | \
CFG_CMD_MII | \
CFG_CMD_MMC | \
CFG_CMD_NAND | \
CFG_CMD_PCI | \
CFG_CMD_PCMCIA | \
CFG_CMD_PING | \
CFG_CMD_PORTIO | \
CFG_CMD_REGINFO | \
CFG_CMD_REISER | \
CFG_CMD_SAVES | \
CFG_CMD_SCSI | \
CFG_CMD_SDRAM | \
CFG_CMD_SNTP | \
CFG_CMD_SPI | \
CFG_CMD_UNIVERSE | \
CFG_CMD_USB | \
CFG_CMD_VFD )
/* Default configuration
*/
#define CONFIG_CMD_DFL (CFG_CMD_ALL & ~CFG_CMD_NONSTD)
#ifndef CONFIG_COMMANDS
#define CONFIG_COMMANDS CONFIG_CMD_DFL
#endif
/*
* optional BOOTP fields
*/
#define CONFIG_BOOTP_SUBNETMASK 0x00000001
#define CONFIG_BOOTP_GATEWAY 0x00000002
#define CONFIG_BOOTP_HOSTNAME 0x00000004
#define CONFIG_BOOTP_NISDOMAIN 0x00000008
#define CONFIG_BOOTP_BOOTPATH 0x00000010
#define CONFIG_BOOTP_BOOTFILESIZE 0x00000020
#define CONFIG_BOOTP_DNS 0x00000040
#define CONFIG_BOOTP_DNS2 0x00000080
#define CONFIG_BOOTP_SEND_HOSTNAME 0x00000100
#define CONFIG_BOOTP_NTPSERVER 0x00000200
#define CONFIG_BOOTP_TIMEOFFSET 0x00000400
#define CONFIG_BOOTP_VENDOREX 0x80000000
#define CONFIG_BOOTP_ALL (~CONFIG_BOOTP_VENDOREX)
#define CONFIG_BOOTP_DEFAULT (CONFIG_BOOTP_SUBNETMASK | \
CONFIG_BOOTP_GATEWAY | \
CONFIG_BOOTP_HOSTNAME | \
CONFIG_BOOTP_BOOTPATH)
#ifndef CONFIG_BOOTP_MASK
#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT
#endif
#endif /* _CMD_CONFIG_H */

6
include/command.h
View File

@@ -84,12 +84,6 @@ typedef void command_t (cmd_tbl_t *, int, int, char *[]);
#define CMD_FLAG_REPEAT 0x0001 /* repeat last command */
#define CMD_FLAG_BOOTD 0x0002 /* command is from bootd */
/*
* Configurable monitor commands definitions have been moved
* to include/cmd_confdefs.h
*/
#define Struct_Section __attribute__ ((unused,section (".u_boot_cmd")))
#ifdef CFG_LONGHELP

53
include/common.h
View File

@@ -1,5 +1,5 @@
/*
* (C) Copyright 2000-2004
* (C) Copyright 2000-2007
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
@@ -38,7 +38,7 @@ typedef volatile unsigned char vu_char;
#include <linux/string.h>
#include <asm/ptrace.h>
#include <stdarg.h>
#if defined(CONFIG_PCI) && defined(CONFIG_440)
#if defined(CONFIG_PCI) && (defined(CONFIG_4xx) && !defined(CONFIG_AP1000))
#include <pci.h>
#endif
#if defined(CONFIG_8xx)
@@ -63,10 +63,19 @@ typedef volatile unsigned char vu_char;
#endif
#elif defined(CONFIG_5xx)
#include <asm/5xx_immap.h>
#define CONFIG_RELOC_FIXUP_WORKS
#elif defined(CONFIG_MPC5xxx)
#include <mpc5xxx.h>
#define CONFIG_RELOC_FIXUP_WORKS
#elif defined(CONFIG_MPC512X)
#include <mpc512x.h>
#include <asm/immap_512x.h>
#define CONFIG_RELOC_FIXUP_WORKS
#elif defined(CONFIG_MPC8220)
#include <asm/immap_8220.h>
#define CONFIG_RELOC_FIXUP_WORKS
#elif defined(CONFIG_824X)
#define CONFIG_RELOC_FIXUP_WORKS
#elif defined(CONFIG_8260)
#if defined(CONFIG_MPC8247) \
|| defined(CONFIG_MPC8248) \
@@ -78,6 +87,7 @@ typedef volatile unsigned char vu_char;
#define CONFIG_MPC8260 1
#endif
#include <asm/immap_8260.h>
#define CONFIG_RELOC_FIXUP_WORKS
#endif
#ifdef CONFIG_MPC86xx
#include <mpc86xx.h>
@@ -90,6 +100,7 @@ typedef volatile unsigned char vu_char;
#ifdef CONFIG_MPC83XX
#include <mpc83xx.h>
#include <asm/immap_83xx.h>
#define CONFIG_RELOC_FIXUP_WORKS
#endif
#ifdef CONFIG_4xx
#include <ppc4xx.h>
@@ -230,6 +241,9 @@ int saveenv (void);
void inline setenv (char *, char *);
#else
void setenv (char *, char *);
#ifdef CONFIG_HAS_UID
void forceenv (char *, char *);
#endif
#endif /* CONFIG_PPC */
#ifdef CONFIG_ARM
# include <asm/mach-types.h>
@@ -248,10 +262,11 @@ void pci_init (void);
void pci_init_board(void);
void pciinfo (int, int);
#if defined(CONFIG_PCI) && defined(CONFIG_440)
# if defined(CFG_PCI_PRE_INIT)
#if defined(CONFIG_PCI) && (defined(CONFIG_4xx) && !defined(CONFIG_AP1000))
int pci_pre_init (struct pci_controller * );
# endif
#endif
#if defined(CONFIG_PCI) && defined(CONFIG_440)
# if defined(CFG_PCI_TARGET_INIT)
void pci_target_init (struct pci_controller *);
# endif
@@ -260,7 +275,7 @@ void pciinfo (int, int);
# endif
int is_pci_host (struct pci_controller *);
#if defined(CONFIG_440SPE)
void pcie_setup_hoses(void);
void pcie_setup_hoses(int busno);
#endif
#endif
@@ -402,6 +417,10 @@ void ppcDcbi(unsigned long value);
void ppcSync(void);
void ppcDcbz(unsigned long value);
#endif
#if defined (CONFIG_MICROBLAZE)
unsigned short in16(unsigned int);
void out16(unsigned int, unsigned short value);
#endif
#if defined (CONFIG_MPC83XX)
void ppcDWload(unsigned int *addr, unsigned int *ret);
@@ -415,6 +434,13 @@ int checkdcache (void);
void upmconfig (unsigned int, unsigned int *, unsigned int);
ulong get_tbclk (void);
void reset_cpu (ulong addr);
#if defined (CONFIG_OF_LIBFDT) && defined (CONFIG_OF_BOARD_SETUP)
void ft_cpu_setup(void *blob, bd_t *bd);
#ifdef CONFIG_PCI
void ft_pci_setup(void *blob, bd_t *bd);
#endif
#endif
/* $(CPU)/serial.c */
int serial_init (void);
@@ -440,11 +466,12 @@ int sdram_adjust_866 (void);
int adjust_sdram_tbs_8xx (void);
#if defined(CONFIG_8260)
int prt_8260_clks (void);
#elif defined(CONFIG_MPC83XX)
int print_clock_conf(void);
#elif defined(CONFIG_MPC5xxx)
int prt_mpc5xxx_clks (void);
#endif
#if defined(CONFIG_MPC512x)
int prt_mpc512xxx_clks (void);
#endif
#if defined(CONFIG_MPC8220)
int prt_mpc8220_clks (void);
#endif
@@ -509,6 +536,8 @@ void cpu_init_f (void);
int cpu_init_r (void);
#if defined(CONFIG_8260)
int prt_8260_rsr (void);
#elif defined(CONFIG_MPC83XX)
int prt_83xx_rsr (void);
#endif
/* $(CPU)/interrupts.c */
@@ -623,9 +652,13 @@ int fgetc(int file);
int pcmcia_init (void);
#ifdef CONFIG_SHOW_BOOT_PROGRESS
void show_boot_progress (int status);
#ifdef CONFIG_STATUS_LED
# include <status_led.h>
#endif
/*
* Board-specific Platform code can reimplement show_boot_progress () if needed
*/
void inline show_boot_progress (int val);
#ifdef CONFIG_INIT_CRITICAL
#error CONFIG_INIT_CRITICAL is deprecated!

81
include/config_cmd_all.h Normal file
View File

@@ -0,0 +1,81 @@
/*
* Copyright 2007 Freescale Semiconductor, Inc.
*
* This file is licensed under the terms of the GNU General Public
* License Version 2. This file is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef _CONFIG_CMD_ALL_H
#define _CONFIG_CMD_ALL_H
/*
* Alphabetical list of all possible commands.
*/
#define CONFIG_CMD_ASKENV /* ask for env variable */
#define CONFIG_CMD_AUTOSCRIPT /* Autoscript Support */
#define CONFIG_CMD_BDI /* bdinfo */
#define CONFIG_CMD_BEDBUG /* Include BedBug Debugger */
#define CONFIG_CMD_BMP /* BMP support */
#define CONFIG_CMD_BOOTD /* bootd */
#define CONFIG_CMD_BSP /* Board Specific functions */
#define CONFIG_CMD_CACHE /* icache, dcache */
#define CONFIG_CMD_CDP /* Cisco Discovery Protocol */
#define CONFIG_CMD_CONSOLE /* coninfo */
#define CONFIG_CMD_DATE /* support for RTC, date/time...*/
#define CONFIG_CMD_DHCP /* DHCP Support */
#define CONFIG_CMD_DIAG /* Diagnostics */
#define CONFIG_CMD_DISPLAY /* Display support */
#define CONFIG_CMD_DOC /* Disk-On-Chip Support */
#define CONFIG_CMD_DTT /* Digital Therm and Thermostat */
#define CONFIG_CMD_ECHO /* echo arguments */
#define CONFIG_CMD_EEPROM /* EEPROM read/write support */
#define CONFIG_CMD_ELF /* ELF (VxWorks) load/boot cmd */
#define CONFIG_CMD_ENV /* saveenv */
#define CONFIG_CMD_EXT2 /* EXT2 Support */
#define CONFIG_CMD_FAT /* FAT support */
#define CONFIG_CMD_FDC /* Floppy Disk Support */
#define CONFIG_CMD_FDOS /* Floppy DOS support */
#define CONFIG_CMD_FLASH /* flinfo, erase, protect */
#define CONFIG_CMD_FPGA /* FPGA configuration Support */
#define CONFIG_CMD_HWFLOW /* RTS/CTS hw flow control */
#define CONFIG_CMD_I2C /* I2C serial bus support */
#define CONFIG_CMD_IDE /* IDE harddisk support */
#define CONFIG_CMD_IMI /* iminfo */
#define CONFIG_CMD_IMLS /* List all found images */
#define CONFIG_CMD_IMMAP /* IMMR dump support */
#define CONFIG_CMD_IRQ /* irqinfo */
#define CONFIG_CMD_ITEST /* Integer (and string) test */
#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
#define CONFIG_CMD_KGDB /* kgdb */
#define CONFIG_CMD_LOADB /* loadb */
#define CONFIG_CMD_LOADS /* loads */
#define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest */
#define CONFIG_CMD_MFSL /* FSL support for Microblaze */
#define CONFIG_CMD_MII /* MII support */
#define CONFIG_CMD_MISC /* Misc functions like sleep etc*/
#define CONFIG_CMD_MMC /* MMC support */
#define CONFIG_CMD_NAND /* NAND support */
#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
#define CONFIG_CMD_NFS /* NFS support */
#define CONFIG_CMD_PCI /* pciinfo */
#define CONFIG_CMD_PCMCIA /* PCMCIA support */
#define CONFIG_CMD_PING /* ping support */
#define CONFIG_CMD_PORTIO /* Port I/O */
#define CONFIG_CMD_REGINFO /* Register dump */
#define CONFIG_CMD_REISER /* Reiserfs support */
#define CONFIG_CMD_RUN /* run command in env variable */
#define CONFIG_CMD_SAVES /* save S record dump */
#define CONFIG_CMD_SCSI /* SCSI Support */
#define CONFIG_CMD_SDRAM /* SDRAM DIMM SPD info printout */
#define CONFIG_CMD_SETGETDCR /* DCR support on 4xx */
#define CONFIG_CMD_SNTP /* SNTP support */
#define CONFIG_CMD_SPI /* SPI utility */
#define CONFIG_CMD_UNIVERSE /* Tundra Universe Support */
#define CONFIG_CMD_USB /* USB Support */
#define CONFIG_CMD_VFD /* VFD support (TRAB) */
#define CONFIG_CMD_XIMG /* Load part of Multi Image */
#define CONFIG_CMD_MUX /* AT91 MMC/SPI Mux Support */
#endif /* _CONFIG_CMD_ALL_H */

40
include/config_cmd_default.h Normal file
View File

@@ -0,0 +1,40 @@
/*
* Copyright 2007 Freescale Semiconductor, Inc.
*
* This file is licensed under the terms of the GNU General Public
* License Version 2. This file is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef _CONFIG_CMD_DEFAULT_H
#define _CONFIG_CMD_DEFAULT_H
/*
* Alphabetical list of all commands that are configured by default.
* This is essentially all commands minus those that are considered
* "non-standard" for some reason (memory hogs, requires special
* hardware, not fully tested, etc.).
*/
#define CONFIG_CMD_AUTOSCRIPT /* Autoscript Support */
#define CONFIG_CMD_BDI /* bdinfo */
#define CONFIG_CMD_BOOTD /* bootd */
#define CONFIG_CMD_CONSOLE /* coninfo */
#define CONFIG_CMD_ECHO /* echo arguments */
#define CONFIG_CMD_ENV /* saveenv */
#define CONFIG_CMD_FLASH /* flinfo, erase, protect */
#define CONFIG_CMD_FPGA /* FPGA configuration Support */
#define CONFIG_CMD_IMI /* iminfo */
#define CONFIG_CMD_IMLS /* List all found images */
#define CONFIG_CMD_ITEST /* Integer (and string) test */
#define CONFIG_CMD_LOADB /* loadb */
#define CONFIG_CMD_LOADS /* loads */
#define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest */
#define CONFIG_CMD_MISC /* Misc functions like sleep etc*/
#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
#define CONFIG_CMD_NFS /* NFS support */
#define CONFIG_CMD_RUN /* run command in env variable */
#define CONFIG_CMD_SETGETDCR /* DCR support on 4xx */
#define CONFIG_CMD_XIMG /* Load part of Multi Image */
#endif /* _CONFIG_CMD_DEFAULT_H */

27
include/configs/A3000.h
View File

@@ -52,23 +52,20 @@
#define CONFIG_BOOTDELAY 5
#if 0
#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
CFG_CMD_BEDBUG | \
CFG_CMD_BSP | \
CFG_CMD_ELF | \
CFG_CMD_I2C | \
CFG_CMD_FLASH | \
CFG_CMD_BEDBUG | \
CFG_CMD_NET | \
CFG_CMD_PCI )
#endif
#define CONFIG_COMMANDS ( CONFIG_CMD_DFL )
/*
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
/*
@@ -309,7 +306,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif

29
include/configs/ADCIOP.h
View File

@@ -59,21 +59,32 @@
#define CONFIG_IPADDR 10.0.18.222
#define CONFIG_SERVERIP 10.0.18.190
#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
CFG_CMD_DHCP | \
CFG_CMD_IRQ | \
CFG_CMD_ELF | \
CFG_CMD_ASKENV )
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
/*
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_ELF
#define CONFIG_CMD_ASKENV
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -185,7 +196,7 @@
*/
#define CFG_DCACHE_SIZE 2048 /* For PLX IOP480 */
#define CFG_CACHELINE_SIZE 16 /* For AMCC 401/403 CPUs */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif

84
include/configs/ADNPESC1.h
View File

@@ -401,15 +401,8 @@
#define CONFIG_RTC_DS1306 1 /* Dallas 1306 real time clock */
#define CFG_SPI_RTC_DEVID 0 /* as 1st SPI device */
#define __SPI_CMD_OFF 0 /* allow default commands: */
/* CFG_CMD_SPI */
/* CFG_CMD_DATE */
#else
#undef CONFIG_NIOS_SPI /* NO SPI support */
#define __SPI_CMD_OFF ( CFG_CMD_SPI \
| CFG_CMD_DATE \
)
#endif
/*------------------------------------------------------------------------
@@ -570,45 +563,55 @@
#define CONFIG_POST CFG_POST_RTC
#define CFG_NIOS_POST_WORD_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
/*------------------------------------------------------------------------
* COMMANDS
*----------------------------------------------------------------------*/
#define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \
CFG_CMD_ASKENV | \
CFG_CMD_BEDBUG | \
CFG_CMD_BMP | \
CFG_CMD_CACHE | \
CFG_CMD_DOC | \
CFG_CMD_DTT | \
CFG_CMD_EEPROM | \
CFG_CMD_ELF | \
CFG_CMD_FAT | \
CFG_CMD_FDC | \
CFG_CMD_FDOS | \
CFG_CMD_HWFLOW | \
CFG_CMD_IDE | \
CFG_CMD_I2C | \
CFG_CMD_JFFS2 | \
CFG_CMD_KGDB | \
CFG_CMD_NAND | \
CFG_CMD_NFS | \
CFG_CMD_MMC | \
CFG_CMD_MII | \
CFG_CMD_PCI | \
CFG_CMD_PCMCIA | \
CFG_CMD_SCSI | \
CFG_CMD_VFD | \
CFG_CMD_USB | \
CFG_CMD_XIMG | \
__SPI_CMD_OFF ) )
/*
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
/*
* Command line configuration.
*/
#include <config_cmd_all.h>
#include <cmd_confdefs.h>
#undef CONFIG_CMD_ASKENV
#undef CONFIG_CMD_BEDBUG
#undef CONFIG_CMD_BMP
#undef CONFIG_CMD_CACHE
#undef CONFIG_CMD_DOC
#undef CONFIG_CMD_DTT
#undef CONFIG_CMD_EEPROM
#undef CONFIG_CMD_ELF
#undef CONFIG_CMD_FAT
#undef CONFIG_CMD_FDC
#undef CONFIG_CMD_FDOS
#undef CONFIG_CMD_HWFLOW
#undef CONFIG_CMD_IDE
#undef CONFIG_CMD_I2C
#undef CONFIG_CMD_JFFS2
#undef CONFIG_CMD_KGDB
#undef CONFIG_CMD_NAND
#undef CONFIG_CMD_NFS
#undef CONFIG_CMD_MMC
#undef CONFIG_CMD_MII
#undef CONFIG_CMD_PCI
#undef CONFIG_CMD_PCMCIA
#undef CONFIG_CMD_SCSI
#undef CONFIG_CMD_VFD
#undef CONFIG_CMD_USB
#undef CONFIG_CMD_XIMG
#if (CFG_NIOS_CPU_SPI_NUMS != 1)
#undef CONFIG_CMD_SPI
#undef CONFIG_CMD_DATE
#endif
/*------------------------------------------------------------------------
* KGDB
*----------------------------------------------------------------------*/
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 9600
#endif
@@ -651,7 +654,6 @@
#undef CFG_LOAD_ADDR /* force error break */
#endif
/* MEM test area */
#if (CFG_SDRAM_SIZE != 0)

18
include/configs/ADS860.h
View File

@@ -37,13 +37,19 @@
#define CONFIG_DRAM_50MHZ 1
#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
| CFG_CMD_DHCP \
| CFG_CMD_IMMAP \
| CFG_CMD_PCMCIA \
| CFG_CMD_PING \
)
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_IMMAP
#define CONFIG_CMD_PCMCIA
#define CONFIG_CMD_PING
/* This is picked up again in fads.h */
#define FADS_COMMANDS_ALREADY_DEFINED
#include "fads.h"

47
include/configs/AMX860.h
View File

@@ -61,7 +61,25 @@
#undef CONFIG_BOOTARGS
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_SCC1_ENET 1 /* use SCC1 ethernet */
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DATE
#define CONFIG_CMD_NFS
#define CONFIG_CMD_SNTP
#if defined(CONFIG_CMD_KGDB)
#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
#undef CONFIG_KGDB_NONE /* define if kgdb on something else */
@@ -70,29 +88,22 @@
#endif
#undef CONFIG_WATCHDOG /* watchdog disabled */
/*
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_SCC1_ENET 1 /* use SCC1 ethernet */
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
CFG_CMD_DHCP | \
CFG_CMD_DATE | \
CFG_CMD_NFS | \
CFG_CMD_SNTP )
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -196,7 +207,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif

38
include/configs/AP1000.h
View File

@@ -66,18 +66,28 @@
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
CFG_CMD_ASKENV | \
CFG_CMD_DHCP | \
CFG_CMD_ELF | \
CFG_CMD_IRQ | \
CFG_CMD_MVENV | \
CFG_CMD_PCI | \
CFG_CMD_PING \
)
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
/*
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ELF
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_MVENV
#define CONFIG_CMD_PCI
#define CONFIG_CMD_PING
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -89,7 +99,7 @@
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -188,7 +198,7 @@
*/
#define CFG_DCACHE_SIZE 16384
#define CFG_CACHELINE_SIZE 32
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
@@ -228,7 +238,7 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif

45
include/configs/APC405.h
View File

@@ -67,27 +67,38 @@
#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
CFG_CMD_DHCP | \
CFG_CMD_PCI | \
CFG_CMD_IRQ | \
CFG_CMD_IDE | \
CFG_CMD_FAT | \
CFG_CMD_ELF | \
CFG_CMD_DATE | \
CFG_CMD_I2C | \
CFG_CMD_MII | \
CFG_CMD_PING | \
CFG_CMD_EEPROM )
/*
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PCI
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_IDE
#define CONFIG_CMD_FAT
#define CONFIG_CMD_ELF
#define CONFIG_CMD_DATE
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_EEPROM
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_SUPPORT_VFAT
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/
@@ -106,7 +117,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -266,7 +277,7 @@
#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
/* have only 8kB, 16kB is save here */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif

36
include/configs/AR405.h
View File

@@ -71,17 +71,29 @@
#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
CFG_CMD_DHCP | \
CFG_CMD_PCI | \
CFG_CMD_IRQ | \
CFG_CMD_ELF | \
CFG_CMD_MII | \
CFG_CMD_PING | \
CFG_CMD_BSP )
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
/*
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PCI
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_ELF
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_BSP
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -92,7 +104,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -207,7 +219,7 @@
#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
/* have only 8kB, 16kB is save here */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif

86
include/configs/ASH405.h
View File

@@ -53,25 +53,41 @@
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_NET_MULTI 1
#undef CONFIG_HAS_ETH1
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
CFG_CMD_DHCP | \
CFG_CMD_IRQ | \
CFG_CMD_ELF | \
CFG_CMD_NAND | \
CFG_CMD_DATE | \
CFG_CMD_I2C | \
CFG_CMD_MII | \
CFG_CMD_PING | \
CFG_CMD_EEPROM )
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
/*
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_ELF
#define CONFIG_CMD_NAND
#define CONFIG_CMD_DATE
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_EEPROM
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -91,7 +107,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -132,40 +148,18 @@
* NAND-FLASH stuff
*-----------------------------------------------------------------------
*/
#define CFG_NAND_BASE_LIST { CFG_NAND_BASE }
#define NAND_MAX_CHIPS 1
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define NAND_BIG_DELAY_US 25
#define CFG_NAND_LEGACY
#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define SECTORSIZE 512
#define ADDR_COLUMN 1
#define ADDR_PAGE 2
#define ADDR_COLUMN_PAGE 3
#define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1
#define NAND_MAX_CHIPS 1
#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
#define CONFIG_MTD_NAND_VERIFY_WRITE 1 /* verify all writes!!! */
#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
#define CFG_NAND_QUIET 1
/*-----------------------------------------------------------------------
* PCI stuff
@@ -270,7 +264,7 @@
#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
/* have only 8kB, 16kB is save here */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif

27
include/configs/Adder.h
View File

@@ -52,15 +52,26 @@
#define CFG_8xx_CPUCLK_MAX 133000000
#endif /* CONFIG_MPC852T */
#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
| CFG_CMD_DHCP \
| CFG_CMD_IMMAP \
| CFG_CMD_MII \
| CFG_CMD_PING \
)
/* This must be included AFTER the definition of CONFIG_COMMANDS */
#include <cmd_confdefs.h>
/*
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_IMMAP
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_BOOTDELAY 5 /* Autoboot after 5 seconds */
#define CONFIG_BOOTCOMMAND "bootm fe040000" /* Autoboot command */

51
include/configs/AdderUSB.h Normal file
View File

@@ -0,0 +1,51 @@
/*
* Copyright (C) 2006 CodeHermit.
* Bryan O'Donoghue <bodonoghue@codehermit.ie>
*
* Provides support for USB console on the Analogue & Micro Adder87x
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __ADDERUSB__
#define __ADDERUSB__
/* Include the board port */
#include "Adder.h"
#define CONFIG_USB_DEVICE /* Include UDC driver */
#define CONFIG_USB_TTY /* Bind the TTY driver to UDC */
#define CFG_USB_EXTC_CLK 0x02 /* Oscillator on EXTC_CLK 2 */
#define CFG_USB_BRG_CLK 0x04 /* or use Baud rate generator 0x04 */
#define CFG_CONSOLE_IS_IN_ENV /* Console is in env */
/* If you have a USB-IF assigned VendorID then you may wish to define
* your own vendor specific values either in BoardName.h or directly in
* usbd_vendor_info.h
*/
/*
#define CONFIG_USBD_MANUFACTURER "CodeHermit.ie"
#define CONFIG_USBD_PRODUCT_NAME "Das U-Boot"
#define CONFIG_USBD_VENDORID 0xFFFF
#define CONFIG_USBD_PRODUCTID_GSERIAL 0xFFFF
#define CONFIG_USBD_PRODUCTID_CDCACM 0xFFFE
*/
#endif /* __ADDERUSB_H__ */

60
include/configs/Alaska8220.h
View File

@@ -39,12 +39,6 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#define CFG_CACHELINE_SIZE 32 /* For MPC8220 CPUs */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
/*
* Serial console configuration
*/
@@ -70,31 +64,40 @@
#define CONFIG_TIMESTAMP /* Print image info with timestamp */
/*
* Supported commands
* BOOTP options
*/
#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
CFG_CMD_BOOTD | \
CFG_CMD_CACHE | \
CFG_CMD_DHCP | \
CFG_CMD_DIAG | \
CFG_CMD_EEPROM | \
CFG_CMD_ELF | \
CFG_CMD_I2C | \
CFG_CMD_NET | \
CFG_CMD_NFS | \
CFG_CMD_PCI | \
CFG_CMD_PING | \
CFG_CMD_REGINFO | \
CFG_CMD_SDRAM | \
CFG_CMD_SNTP )
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_BOOTD
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DIAG
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_ELF
#define CONFIG_CMD_I2C
#define CONFIG_CMD_NET
#define CONFIG_CMD_NFS
#define CONFIG_CMD_PCI
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_SNTP
#define CONFIG_NET_MULTI
#define CONFIG_MII
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
/*
* Autobooting
*/
@@ -282,7 +285,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -298,6 +301,11 @@
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
#define CFG_CACHELINE_SIZE 32 /* For MPC8220 CPUs */
#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
/*
* Various low-level settings
*/

54
include/configs/AmigaOneG3SE.h
View File

@@ -56,38 +56,46 @@
#define CONFIG_BOOTARGS "root=/dev/ram rw ramdisk=4096"
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
CONFIG_BOOTP_BOOTFILESIZE)
/*
* BOOTP options
*/
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_AMIGA_PARTITION
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
CFG_CMD_ASKENV | \
CFG_CMD_BSP | \
CFG_CMD_DATE | \
CFG_CMD_DHCP | \
CFG_CMD_ELF | \
CFG_CMD_NET | \
CFG_CMD_IDE | \
CFG_CMD_FDC | \
CFG_CMD_CACHE | \
CFG_CMD_CONSOLE| \
CFG_CMD_USB | \
CFG_CMD_BSP | \
CFG_CMD_PCI )
/* CFG_CMD_MII | \ */
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_BSP
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ELF
#define CONFIG_CMD_NET
#define CONFIG_CMD_IDE
#define CONFIG_CMD_FDC
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_CONSOLE|
#define CONFIG_CMD_USB
#define CONFIG_CMD_BSP
#define CONFIG_CMD_PCI
#define CONFIG_PCI 1
/* #define CONFIG_PCI_SCAN_SHOW 1 */
#define CONFIG_PCI_PNP 1 /* PCI plug-and-play */
/* This must be included AFTER the definition of CONFIG_COMMANDS (if any)
*/
#include <cmd_confdefs.h>
#define atoi(x) simple_strtoul(x,NULL,10)
/*
* Miscellaneous configurable options
@@ -247,7 +255,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
@@ -348,8 +356,6 @@
#define CONFIG_3COM
/* #define CONFIG_BOOTP_RANDOM_DELAY */
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
CONFIG_BOOTP_BOOTFILESIZE)
/*
* USB configuration

26
include/configs/B2.h
View File

@@ -72,16 +72,26 @@
#define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
/*
* BOOTP options
*/
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
CFG_CMD_DATE | \
CFG_CMD_ELF | \
CFG_CMD_EEPROM | \
CFG_CMD_I2C )
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_DATE
#define CONFIG_CMD_ELF
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_I2C
#define CONFIG_BOOTDELAY 5
#define CONFIG_ETHADDR 00:50:c2:1e:af:fb

32
include/configs/BAB7xx.h
View File

@@ -66,14 +66,30 @@
#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
#define CFG_LOADS_BAUD_CHANGE /* allow baudrate changes */
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
/*
* BOOTP options
*/
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_JFFS2 |\
CFG_CMD_SCSI | CFG_CMD_IDE | CFG_CMD_DATE |\
CFG_CMD_FDC | CFG_CMD_ELF)
#define CONFIG_BOOTP_BOOTFILESIZE
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_PCI
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_SCSI
#define CONFIG_CMD_IDE
#define CONFIG_CMD_DATE
#define CONFIG_CMD_FDC
#define CONFIG_CMD_ELF
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
/*
* Miscellaneous configurable options
@@ -86,7 +102,7 @@
*/
#define CONFIG_CONS_INDEX 1
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -436,7 +452,7 @@ extern unsigned long bab7xx_get_gclk_freq (void);
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif

143
include/configs/BC3450.h
View File

@@ -61,11 +61,6 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
/*
* Serial console configuration
*/
@@ -106,12 +101,6 @@
#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
#define CONFIG_NS8382X 1
#ifdef CONFIG_PCI
# define ADD_PCI_CMD CFG_CMD_PCI
#else
# define ADD_PCI_CMD 0
#endif
/*
* Video console
*/
@@ -126,12 +115,6 @@
# define CONFIG_SPLASH_SCREEN
# define CFG_CONSOLE_IS_IN_ENV
#ifdef CONFIG_VIDEO
# define ADD_BMP_CMD CFG_CMD_BMP
#else
# define ADD_BMP_CMD 0
#endif
/*
* Partitions
*/
@@ -144,10 +127,7 @@
*/
#ifdef CONFIG_BC3450_USB
# define CONFIG_USB_OHCI
# define ADD_USB_CMD CFG_CMD_USB
# define CONFIG_USB_STORAGE
#else /* !CONFIG_BC3450_USB */
# define ADD_USB_CMD 0
#endif /* CONFIG_BC3450_USB */
/*
@@ -158,66 +138,69 @@
CFG_POST_I2C)
#ifdef CONFIG_POST
# define CFG_CMD_POST_DIAG CFG_CMD_DIAG
/* preserve space for the post_word at end of on-chip SRAM */
# define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
#else
# define CFG_CMD_POST_DIAG 0
#endif /* CONFIG_POST */
/*
* IDE
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ECHO
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_I2C
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_MII
#define CONFIG_CMD_NFS
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_SNTP
#define CONFIG_CMD_BSP
#ifdef CONFIG_VIDEO
#define CONFIG_CMD_BMP
#endif
#ifdef CONFIG_BC3450_IDE
# define ADD_IDE_CMD CFG_CMD_IDE
#else
# define ADD_IDE_CMD 0
#endif /* CONFIG_BC3450_IDE */
#define CONFIG_CMD_IDE
#endif
/*
* Filesystem support
*/
#if defined (CONFIG_BC3450_IDE) || defined (CONFIG_BC3450_USB)
#ifdef CONFIG_FAT
# define ADD_FAT_CMD CFG_CMD_FAT
#else
# define ADD_FAT_CMD 0
#endif /* CONFIG_FAT */
#if defined(CONFIG_BC3450_IDE) || defined(CONFIG_BC3450_USB)
#ifdef CONFIG_FAT
#define CONFIG_CMD_FAT
#endif
#ifdef CONFIG_EXT2
# define ADD_EXT2_CMD CFG_CMD_EXT2
#else
# define ADD_EXT2_CMD 0
#endif /* CONFIG_EXT2 */
#endif /* CONFIG_BC3450_IDE / _USB */
#ifdef CONFIG_EXT2
#define CONFIG_CMD_EXT2
#endif
#endif
/*
* Supported commands
*/
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
ADD_BMP_CMD | \
ADD_IDE_CMD | \
ADD_FAT_CMD | \
ADD_EXT2_CMD | \
ADD_PCI_CMD | \
ADD_USB_CMD | \
CFG_CMD_ASKENV | \
CFG_CMD_DATE | \
CFG_CMD_DHCP | \
CFG_CMD_ECHO | \
CFG_CMD_EEPROM | \
CFG_CMD_I2C | \
CFG_CMD_JFFS2 | \
CFG_CMD_MII | \
CFG_CMD_NFS | \
CFG_CMD_PING | \
CFG_CMD_POST_DIAG | \
CFG_CMD_REGINFO | \
CFG_CMD_SNTP | \
CFG_CMD_BSP)
#ifdef CONFIG_BC3450_USB
#define CONFIG_CMD_USB
#endif
#ifdef CONFIG_PCI
#define CONFIG_CMD_PCI
#endif
#ifdef CONFIG_POST
#define CONFIG_CMD_DIAG
#endif
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
#define CONFIG_TIMESTAMP /* display image timestamps */
@@ -282,17 +265,17 @@
/*
* IPB Bus clocking configuration.
*/
#define CFG_IPBSPEED_133 /* define for 133MHz speed */
#define CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
/*
* PCI Bus clocking configuration
*
* Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
* CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet
* hasn't been tested with a IPB Bus Clock of 66 MHz.
* CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
* of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
*/
#if defined(CFG_IPBSPEED_133)
# define CFG_PCISPEED_66 /* define for 66MHz speed */
#if defined(CFG_IPBCLK_EQUALS_XLBCLK)
# define CFG_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */
#endif
/*
@@ -450,7 +433,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -469,9 +452,13 @@
#define CFG_HZ 1000 /* dec freq: 1ms ticks */
#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
/*
* Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined,
* which is normally part of the default commands (CFV_CMD_DFL)
* Enable loopw command.
*/
#define CONFIG_LOOPW
@@ -488,7 +475,7 @@
#define CFG_BOOTCS_START CFG_FLASH_BASE
#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
#ifdef CFG_PCISPEED_66
#ifdef CFG_PCICLK_EQUALS_IPBCLK_DIV2
# define CFG_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */
#else
# define CFG_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */

37
include/configs/BMW.h
View File

@@ -64,28 +64,35 @@
#define CFG_DOC_SUPPORT_2000 1
#define CFG_DOC_SUPPORT_MILLENNIUM 1
#define CFG_DOC_SHORT_TIMEOUT 1
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
CFG_CMD_DATE | \
CFG_CMD_DOC | \
CFG_CMD_ELF | \
0 )
/* CFG_CMD_DOC required legacy NAND support */
/*
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DOC
#define CONFIG_CMD_ELF
/* CONFIG_CMD_DOC required legacy NAND support */
#define CFG_NAND_LEGACY
#if 0
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DHCP | \
CFG_CMD_PCI | CFG_CMD_DOC | CFG_CMD_DATE)
#define CONFIG_PCI 1
#define CONFIG_PCI_PNP 1 /* PCI plug-and-play */
#endif
/* This must be included AFTER the definition of CONFIG_COMMANDS (if any)
*/
#include <cmd_confdefs.h>
/*
* Miscellaneous configurable options
*/
@@ -293,7 +300,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif

29
include/configs/CANBT.h
View File

@@ -56,13 +56,26 @@
#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_COMMANDS (( CONFIG_CMD_DFL | \
CFG_CMD_IRQ | \
CFG_CMD_EEPROM ) & \
~CFG_CMD_NET)
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
/*
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_EEPROM
#undef CONFIG_CMD_NET
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -73,7 +86,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -173,7 +186,7 @@
*/
#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif

46
include/configs/CATcenter.h
View File

@@ -119,24 +119,36 @@
#define CONFIG_TIMESTAMP /* Print image info with timestamp */
#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
CFG_CMD_DHCP | \
CFG_CMD_ELF | \
CFG_CMD_EEPROM | \
CFG_CMD_I2C | \
CFG_CMD_IRQ | \
CFG_CMD_JFFS2 | \
CFG_CMD_MII | \
CFG_CMD_NAND | \
CFG_CMD_NFS | \
CFG_CMD_SNTP )
/*
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ELF
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_MII
#define CONFIG_CMD_NAND
#define CONFIG_CMD_NFS
#define CONFIG_CMD_SNTP
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/
@@ -155,7 +167,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -387,6 +399,8 @@
#define CFG_ENV_ADDR_REDUND 0xFFFFA000
#define CFG_ENV_SIZE_REDUND 0x2000
#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
#define CFG_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */
#define CFG_NVRAM_SIZE 242 /* NVRAM size */
@@ -413,7 +427,7 @@
#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
/* have only 8kB, 16kB is save here */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif

32
include/configs/CCM.h
View File

@@ -94,27 +94,35 @@
#define CONFIG_MAC_PARTITION /* nod used yet */
#define CONFIG_DOS_PARTITION
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
/*
* BOOTP options
*/
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
CFG_CMD_BSP | \
CFG_CMD_DHCP | \
CFG_CMD_DATE | \
CFG_CMD_EEPROM | \
CFG_CMD_NFS | \
CFG_CMD_SNTP )
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_BSP
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DATE
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_NFS
#define CONFIG_CMD_SNTP
/*----------------------------------------------------------------------*/
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */

87
include/configs/CMS700.h
View File

@@ -60,28 +60,35 @@
#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
CONFIG_BOOTP_DNS | \
CONFIG_BOOTP_DNS2 | \
CONFIG_BOOTP_SEND_HOSTNAME )
/*
* BOOTP options
*/
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
CFG_CMD_DHCP | \
CFG_CMD_BSP | \
CFG_CMD_PCI | \
CFG_CMD_IRQ | \
CFG_CMD_ELF | \
CFG_CMD_NAND | \
CFG_CMD_I2C | \
CFG_CMD_DATE | \
CFG_CMD_MII | \
CFG_CMD_PING | \
CFG_CMD_EEPROM )
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_BSP
#define CONFIG_CMD_PCI
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_ELF
#define CONFIG_CMD_NAND
#define CONFIG_CMD_I2C
#define CONFIG_CMD_DATE
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_EEPROM
#define CFG_NAND_LEGACY
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -100,7 +107,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -148,36 +155,18 @@
* NAND-FLASH stuff
*-----------------------------------------------------------------------
*/
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define SECTORSIZE 512
#define CFG_NAND_BASE_LIST { CFG_NAND_BASE }
#define NAND_MAX_CHIPS 1
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define NAND_BIG_DELAY_US 25
#define ADDR_COLUMN 1
#define ADDR_PAGE 2
#define ADDR_COLUMN_PAGE 3
#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
#define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1
#define NAND_MAX_CHIPS 1
#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
#define CFG_NAND_QUIET 1
/*-----------------------------------------------------------------------
* PCI stuff
@@ -289,7 +278,7 @@
#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
/* have only 8kB, 16kB is save here */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif

51
include/configs/CPC45.h
View File

@@ -54,27 +54,36 @@
#define CONFIG_BOOTDELAY 5
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
CFG_CMD_BEDBUG | \
CFG_CMD_DATE | \
CFG_CMD_DHCP | \
CFG_CMD_EEPROM | \
CFG_CMD_EXT2 | \
CFG_CMD_FAT | \
CFG_CMD_FLASH | \
CFG_CMD_I2C | \
CFG_CMD_IDE | \
CFG_CMD_NFS | \
CFG_CMD_PCI | \
CFG_CMD_PING | \
CFG_CMD_SDRAM | \
CFG_CMD_SNTP )
/* This must be included AFTER the definition of CONFIG_COMMANDS (if any)
/*
* BOOTP options
*/
#include <cmd_confdefs.h>
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_BEDBUG
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IDE
#define CONFIG_CMD_NFS
#define CONFIG_CMD_PCI
#define CONFIG_CMD_PING
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_SNTP
/*
@@ -325,7 +334,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif

35
include/configs/CPCI2DP.h
View File

@@ -54,16 +54,29 @@
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_COMMANDS ( (CONFIG_CMD_DFL & ~CFG_CMD_NET) | \
CFG_CMD_PCI | \
CFG_CMD_IRQ | \
CFG_CMD_ELF | \
CFG_CMD_I2C | \
CFG_CMD_BSP | \
CFG_CMD_EEPROM )
/*
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_PCI
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_ELF
#define CONFIG_CMD_I2C
#define CONFIG_CMD_BSP
#define CONFIG_CMD_EEPROM
#undef CONFIG_CMD_NET
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -80,7 +93,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -216,7 +229,7 @@
#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
/* have only 8kB, 16kB is save here */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif

51
include/configs/CPCI405.h
View File

@@ -55,32 +55,43 @@
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
CONFIG_BOOTP_DNS | \
CONFIG_BOOTP_DNS2 | \
CONFIG_BOOTP_SEND_HOSTNAME )
#define CONFIG_NET_MULTI 1
#undef CONFIG_HAS_ETH1
/*
* BOOTP options
*/
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PCI
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_IDE
#define CONFIG_CMD_FAT
#define CONFIG_CMD_ELF
#define CONFIG_CMD_MII
#define CONFIG_CMD_EEPROM
#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
CFG_CMD_DHCP | \
CFG_CMD_PCI | \
CFG_CMD_IRQ | \
CFG_CMD_IDE | \
CFG_CMD_FAT | \
CFG_CMD_ELF | \
CFG_CMD_MII | \
CFG_CMD_EEPROM )
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_SUPPORT_VFAT
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
#define CFG_NAND_LEGACY
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
@@ -96,7 +107,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -260,7 +271,7 @@
*/
#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif

62
include/configs/CPCI4052.h
View File

@@ -37,6 +37,7 @@
#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_CPCI405 1 /* ...on a CPCI405 board */
#define CONFIG_CPCI405_VER2 1 /* ...version 2 */
#undef CONFIG_CPCI405_6U /* enable this for 6U boards */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
@@ -56,28 +57,44 @@
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
#define CONFIG_NET_MULTI 1
#undef CONFIG_HAS_ETH1
#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
CONFIG_BOOTP_DNS | \
CONFIG_BOOTP_DNS2 | \
CONFIG_BOOTP_SEND_HOSTNAME )
/*
* BOOTP options
*/
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PCI
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_IDE
#define CONFIG_CMD_FAT
#define CONFIG_CMD_ELF
#define CONFIG_CMD_DATE
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_BSP
#define CONFIG_CMD_EEPROM
#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
CFG_CMD_DHCP | \
CFG_CMD_PCI | \
CFG_CMD_IRQ | \
CFG_CMD_IDE | \
CFG_CMD_FAT | \
CFG_CMD_ELF | \
CFG_CMD_DATE | \
CFG_CMD_JFFS2 | \
CFG_CMD_I2C | \
CFG_CMD_MII | \
CFG_CMD_PING | \
CFG_CMD_BSP | \
CFG_CMD_EEPROM )
#if 0 /* test-only */
#define CONFIG_NETCONSOLE
@@ -97,11 +114,6 @@
#define CONFIG_AUTO_UPDATE 1 /* autoupdate via compactflash */
#endif
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
#define CFG_NAND_LEGACY
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
@@ -117,7 +129,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -311,7 +323,7 @@
#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
/* have only 8kB, 16kB is save here */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif

60
include/configs/CPCI405AB.h
View File

@@ -57,39 +57,49 @@
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
#define CONFIG_NET_MULTI 1
#undef CONFIG_HAS_ETH1
#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
CONFIG_BOOTP_DNS | \
CONFIG_BOOTP_DNS2 | \
CONFIG_BOOTP_SEND_HOSTNAME )
/*
* BOOTP options
*/
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PCI
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_IDE
#define CONFIG_CMD_FAT
#define CONFIG_CMD_ELF
#define CONFIG_CMD_DATE
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_EEPROM
#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
CFG_CMD_DHCP | \
CFG_CMD_PCI | \
CFG_CMD_IRQ | \
CFG_CMD_IDE | \
CFG_CMD_FAT | \
CFG_CMD_ELF | \
CFG_CMD_DATE | \
CFG_CMD_JFFS2 | \
CFG_CMD_I2C | \
CFG_CMD_MII | \
CFG_CMD_PING | \
CFG_CMD_EEPROM )
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_SUPPORT_VFAT
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
#define CFG_NAND_LEGACY
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
@@ -105,7 +115,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -284,7 +294,7 @@
#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
/* have only 8kB, 16kB is save here */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif

61
include/configs/CPCI405DT.h
View File

@@ -56,28 +56,44 @@
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
#define CONFIG_NET_MULTI 1
#undef CONFIG_HAS_ETH1
#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
CONFIG_BOOTP_DNS | \
CONFIG_BOOTP_DNS2 | \
CONFIG_BOOTP_SEND_HOSTNAME )
/*
* BOOTP options
*/
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PCI
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_IDE
#define CONFIG_CMD_FAT
#define CONFIG_CMD_ELF
#define CONFIG_CMD_DATE
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_BSP
#define CONFIG_CMD_EEPROM
#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
CFG_CMD_DHCP | \
CFG_CMD_PCI | \
CFG_CMD_IRQ | \
CFG_CMD_IDE | \
CFG_CMD_FAT | \
CFG_CMD_ELF | \
CFG_CMD_DATE | \
CFG_CMD_JFFS2 | \
CFG_CMD_I2C | \
CFG_CMD_MII | \
CFG_CMD_PING | \
CFG_CMD_BSP | \
CFG_CMD_EEPROM )
#if 0 /* test-only */
#define CONFIG_NETCONSOLE
@@ -95,11 +111,6 @@
#undef CONFIG_AUTO_UPDATE /* autoupdate via compactflash */
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
#define CFG_NAND_LEGACY
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
@@ -115,7 +126,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -314,7 +325,7 @@
#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
/* have only 8kB, 16kB is save here */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif

49
include/configs/CPCI440.h
View File

@@ -33,6 +33,7 @@
*----------------------------------------------------------------------*/
#define CONFIG_CPCI440 1 /* Board is ebony */
#define CONFIG_440GP 1 /* Specifc GP support */
#define CONFIG_440 1 /* ... PPC440 family */
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
#undef CFG_DRAM_TEST /* Disable-takes long time! */
@@ -171,29 +172,27 @@
#define CONFIG_PHY_ADDR 1 /* PHY address */
#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
#if 0 /* test-only */
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
CFG_CMD_IRQ | \
CFG_CMD_I2C | \
CFG_CMD_KGDB | \
CFG_CMD_DHCP | \
CFG_CMD_DATE | \
CFG_CMD_BEDBUG | \
CFG_CMD_ELF )
#else
#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
CFG_CMD_IRQ | \
CFG_CMD_ELF | \
CFG_CMD_DATE | \
CFG_CMD_I2C | \
CFG_CMD_EEPROM )
/* test-only: support fehlt bisher... */
/* CFG_CMD_IDE | \*/
/* CFG_CMD_PCI | \*/
#endif
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
/*
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_ELF
#define CONFIG_CMD_DATE
#define CONFIG_CMD_I2C
#define CONFIG_CMD_EEPROM
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -204,7 +203,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -268,7 +267,7 @@
*/
#define CFG_DCACHE_SIZE 32768 /* For AMCC 440 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
@@ -290,7 +289,7 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif

49
include/configs/CPCI750.h
View File

@@ -133,30 +133,37 @@
#undef CONFIG_WATCHDOG /* watchdog disabled */
#undef CONFIG_ALTIVEC /* undef to disable */
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
CONFIG_BOOTP_BOOTFILESIZE)
/*
* BOOTP options
*/
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
| CFG_CMD_ASKENV \
| CFG_CMD_I2C \
| CFG_CMD_CACHE \
| CFG_CMD_EEPROM \
| CFG_CMD_PCI \
| CFG_CMD_ELF \
| CFG_CMD_DATE \
| CFG_CMD_NET \
| CFG_CMD_PING \
| CFG_CMD_IDE \
| CFG_CMD_FAT \
| CFG_CMD_EXT2 \
)
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_I2C
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_PCI
#define CONFIG_CMD_ELF
#define CONFIG_CMD_DATE
#define CONFIG_CMD_NET
#define CONFIG_CMD_PING
#define CONFIG_CMD_IDE
#define CONFIG_CMD_FAT
#define CONFIG_CMD_EXT2
#define CONFIG_DOS_PARTITION
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
#define CONFIG_USE_CPCIDVI
#ifdef CONFIG_USE_CPCIDVI
@@ -179,7 +186,7 @@
#define CFG_GT_DUAL_CPU /* also for JTAG even with one cpu */
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -585,7 +592,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif

41
include/configs/CPCIISER4.h
View File

@@ -54,15 +54,36 @@
#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
CFG_CMD_PCI | \
CFG_CMD_IRQ | \
CFG_CMD_MII | \
CFG_CMD_ELF | \
CFG_CMD_EEPROM )
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
/*
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
/*
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_PCI
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_MII
#define CONFIG_CMD_ELF
#define CONFIG_CMD_EEPROM
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -73,7 +94,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -189,7 +210,7 @@
*/
#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif

42
include/configs/CPU86.h
View File

@@ -68,9 +68,7 @@
* for FCC)
*
* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
* defined elsewhere (as for the console), or CFG_CMD_NET must be removed
* from CONFIG_COMMANDS to remove support for networking.
*
* defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
*/
#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
@@ -163,27 +161,37 @@
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
/*
* BOOTP options
*/
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
CFG_CMD_BEDBUG | \
CFG_CMD_DATE | \
CFG_CMD_DHCP | \
CFG_CMD_DOC | \
CFG_CMD_EEPROM | \
CFG_CMD_I2C | \
CFG_CMD_NFS | \
CFG_CMD_SNTP )
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_BEDBUG
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DOC
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_I2C
#define CONFIG_CMD_NFS
#define CONFIG_CMD_SNTP
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -348,7 +356,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif

48
include/configs/CPU87.h
View File

@@ -69,9 +69,7 @@
* for FCC)
*
* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
* defined elsewhere (as for the console), or CFG_CMD_NET must be removed
* from CONFIG_COMMANDS to remove support for networking.
*
* defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
*/
#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
@@ -167,27 +165,31 @@
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
/*
* BOOTP options
*/
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_BEDBUG
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DOC
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_I2C
#ifdef CONFIG_PCI
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
CFG_CMD_BEDBUG | \
CFG_CMD_DATE | \
CFG_CMD_DOC | \
CFG_CMD_EEPROM | \
CFG_CMD_I2C | \
CFG_CMD_PCI)
#else /* ! PCI */
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
CFG_CMD_BEDBUG | \
CFG_CMD_DATE | \
CFG_CMD_DOC | \
CFG_CMD_EEPROM | \
CFG_CMD_I2C )
#endif /* CONFIG_PCI */
#define CONFIG_CMD_PCI
#endif
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
#define CFG_NAND_LEGACY
@@ -196,7 +198,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -369,7 +371,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif

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