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armv8: LS1046AQDS: Add NOR Secure Boot Target

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Add NOR secure boot target. Also enable sec init.

Signed-off-by: Vinitha Pillai <vinitha.pillai@nxp.com>
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
This commit is contained in:
Sumit Garg
2017-03-23 13:48:17 +05:30
committed by York Sun
parent b3635f57d9
commit b7c19ea1ca
3 changed files with 62 additions and 0 deletions
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4
board/freescale/ls1046aqds/MAINTAINERS
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@@ -8,3 +8,7 @@ F: configs/ls1046aqds_nand_defconfig
F: configs/ls1046aqds_sdcard_ifc_defconfig
F: configs/ls1046aqds_sdcard_qspi_defconfig
F: configs/ls1046aqds_qspi_defconfig
M: Sumit Garg <sumit.garg@nxp.com>
S: Maintained
F: configs/ls1046aqds_SECURE_BOOT_defconfig

19
board/freescale/ls1046aqds/ls1046aqds.c
View File

@@ -22,6 +22,7 @@
#include <fsl_csu.h>
#include <fsl_esdhc.h>
#include <fsl_ifc.h>
#include <fsl_sec.h>
#include <spl.h>
#include "../common/vid.h"
@@ -266,6 +267,24 @@ int board_init(void)
if (adjust_vdd(0))
printf("Warning: Adjusting core voltage failed.\n");
#ifdef CONFIG_SECURE_BOOT
/*
* In case of Secure Boot, the IBR configures the SMMU
* to allow only Secure transactions.
* SMMU must be reset in bypass mode.
* Set the ClientPD bit and Clear the USFCFG Bit
*/
u32 val;
val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
out_le32(SMMU_SCR0, val);
val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
out_le32(SMMU_NSCR0, val);
#endif
#ifdef CONFIG_FSL_CAAM
sec_init();
#endif
return 0;
}