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Merge branch 'master' of git://git.denx.de/u-boot

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This commit is contained in:
Stefano Babic
2020-05-10 13:03:56 +02:00
parent 8142a97d54 c5c657644b
commit b77d0292ca
845 changed files with 12206 additions and 6812 deletions
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2
include/bedbug/type.h
View File

@@ -3,7 +3,7 @@
/* Supporting routines */
int bedbug_puts (const char *);
void bedbug_init (void);
int bedbug_init(void);
void bedbug860_init (void);
void do_bedbug_breakpoint (struct pt_regs *);
void bedbug_main_loop (unsigned long, struct pt_regs *);

5
include/configs/10m50_devboard.h
View File

@@ -69,10 +69,5 @@
*/
#define CONFIG_SYS_LOAD_ADDR 0xcc000000 /* Half of RAM */
#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MONITOR_BASE - \
CONFIG_ENV_SIZE - \
CONFIG_SYS_MALLOC_LEN - \
0x10000)
#endif /* __CONFIG_H */

5
include/configs/3c120_devboard.h
View File

@@ -69,10 +69,5 @@
*/
#define CONFIG_SYS_LOAD_ADDR 0xd4000000 /* Half of RAM */
#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MONITOR_BASE - \
CONFIG_ENV_SIZE - \
CONFIG_SYS_MALLOC_LEN - \
0x10000)
#endif /* __CONFIG_H */

2
include/configs/B4860QDS.h
View File

@@ -128,8 +128,6 @@ unsigned long get_board_ddr_clk(void);
#if 0
#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
#endif
#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x00400000
/*
* Config the L3 Cache as L3 SRAM

3
include/configs/BSC9131RDB.h
View File

@@ -56,9 +56,6 @@
#define CONFIG_L2_CACHE /* toggle L2 cache */
#define CONFIG_BTB /* enable branch predition */
#define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x01ffffff
/* DDR Setup */
#undef CONFIG_SYS_DDR_RAW_TIMING
#undef CONFIG_DDR_SPD

3
include/configs/BSC9132QDS.h
View File

@@ -94,9 +94,6 @@
#define CONFIG_L2_CACHE /* toggle L2 cache */
#define CONFIG_BTB /* enable branch predition */
#define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x01ffffff
/* DDR Setup */
#define CONFIG_SYS_SPD_BUS_NUM 0
#define SPD_EEPROM_ADDRESS1 0x54 /* I2C access */

3
include/configs/C29XPCIE.h
View File

@@ -105,9 +105,6 @@
#define CONFIG_ADDR_MAP 1
#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
#define CONFIG_SYS_MEMTEST_START 0x00200000
#define CONFIG_SYS_MEMTEST_END 0x00400000
/* DDR Setup */
#define CONFIG_DDR_SPD
#define CONFIG_SYS_SPD_BUS_NUM 0

3
include/configs/M5208EVBE.h
View File

@@ -104,9 +104,6 @@
#define CONFIG_SYS_SDRAM_EMOD 0x80010000
#define CONFIG_SYS_SDRAM_MODE 0x00CD0000
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */

3
include/configs/M52277EVB.h
View File

@@ -144,9 +144,6 @@
#define CONFIG_SYS_SDRAM_MODE 0x00CD0000
#define CONFIG_SYS_SDRAM_DRV_STRENGTH 0x00
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
#ifdef CONFIG_CF_SBF
# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400)
#else

3
include/configs/M5235EVB.h
View File

@@ -112,9 +112,6 @@
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */

3
include/configs/M5249EVB.h
View File

@@ -39,9 +39,6 @@
#define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */
#define CONFIG_SYS_MEMTEST_START 0x400
#define CONFIG_SYS_MEMTEST_END 0x380000
/*
* Clock configuration: enable only one of the following options
*/

3
include/configs/M5253DEMO.h
View File

@@ -84,9 +84,6 @@
#define CONFIG_SYS_LOAD_ADDR 0x00100000
#define CONFIG_SYS_MEMTEST_START 0x400
#define CONFIG_SYS_MEMTEST_END 0x380000
#undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */
#define CONFIG_SYS_FAST_CLK
#ifdef CONFIG_SYS_FAST_CLK

2
include/configs/M5272C3.h
View File

@@ -79,8 +79,6 @@
""
#define CONFIG_SYS_LOAD_ADDR 0x20000
#define CONFIG_SYS_MEMTEST_START 0x400
#define CONFIG_SYS_MEMTEST_END 0x380000
#define CONFIG_SYS_CLK 66000000
/*

2
include/configs/M5275EVB.h
View File

@@ -72,8 +72,6 @@
#define CONFIG_SYS_LOAD_ADDR 0x800000
#define CONFIG_BOOTCOMMAND "bootm ffe40000"
#define CONFIG_SYS_MEMTEST_START 0x400
#define CONFIG_SYS_MEMTEST_END 0x380000
#ifdef CONFIG_MCFFEC
# define CONFIG_NET_RETRY_COUNT 5

3
include/configs/M5282EVB.h
View File

@@ -77,9 +77,6 @@
#define CONFIG_SYS_LOAD_ADDR 0x20000
#define CONFIG_SYS_MEMTEST_START 0x400
#define CONFIG_SYS_MEMTEST_END 0x380000
#define CONFIG_SYS_CLK 64000000
/* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */

3
include/configs/M53017EVB.h
View File

@@ -120,9 +120,6 @@
#define CONFIG_SYS_SDRAM_EMOD 0x80010000
#define CONFIG_SYS_SDRAM_MODE 0x00CD0000
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */

3
include/configs/M5329EVB.h
View File

@@ -116,9 +116,6 @@
#define CONFIG_SYS_SDRAM_EMOD 0x40010000
#define CONFIG_SYS_SDRAM_MODE 0x018D0000
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */

3
include/configs/M5373EVB.h
View File

@@ -116,9 +116,6 @@
#define CONFIG_SYS_SDRAM_EMOD 0x40010000
#define CONFIG_SYS_SDRAM_MODE 0x018D0000
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */

2
include/configs/M54418TWR.h
View File

@@ -178,8 +178,6 @@
#define CONFIG_SYS_SDRAM_BASE 0x40000000
#define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */
#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x400)
#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
#define CONFIG_SYS_DRAM_TEST
#if defined(CONFIG_CF_SBF) || defined(CONFIG_SYS_NAND_BOOT)

3
include/configs/M54451EVB.h
View File

@@ -152,9 +152,6 @@
#define CONFIG_SYS_SDRAM_MODE 0x008D0000
#define CONFIG_SYS_SDRAM_DRV_STRENGTH 0x44
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
#ifdef CONFIG_CF_SBF
# define CONFIG_SERIAL_BOOT
# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400)

3
include/configs/M54455EVB.h
View File

@@ -201,9 +201,6 @@
#define CONFIG_SYS_SDRAM_MODE 0x00010033
#define CONFIG_SYS_SDRAM_DRV_STRENGTH 0xAA
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
#ifdef CONFIG_CF_SBF
# define CONFIG_SERIAL_BOOT
# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400)

3
include/configs/M5475EVB.h
View File

@@ -159,9 +159,6 @@
# define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_DRAMSZ
#endif
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */

3
include/configs/M5485EVB.h
View File

@@ -147,9 +147,6 @@
# define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_DRAMSZ
#endif
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */

3
include/configs/MCR3000.h
View File

@@ -60,9 +60,6 @@
/* Miscellaneous configurable options */
#define CONFIG_SYS_MEMTEST_START 0x00002000
#define CONFIG_SYS_MEMTEST_END 0x00800000
#define CONFIG_SYS_LOAD_ADDR 0x200000
#define CONFIG_SYS_HZ 1000

2
include/configs/MPC8308RDB.h
View File

@@ -101,8 +101,6 @@
/*
* Memory test
*/
#define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */
#define CONFIG_SYS_MEMTEST_END 0x07f00000
/*
* The reserved memory

3
include/configs/MPC8313ERDB_NAND.h
View File

@@ -57,9 +57,6 @@
#define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR
#endif
#define CONFIG_SYS_MEMTEST_START 0x00001000
#define CONFIG_SYS_MEMTEST_END 0x07f00000
/* Early revs of this board will lock up hard when attempting
* to access the PMC registers, unless a JTAG debugger is
* connected, or some resistor modifications are made.

3
include/configs/MPC8313ERDB_NOR.h
View File

@@ -29,9 +29,6 @@
#define CONFIG_VSC7385_ENET
#define CONFIG_TSEC2
#define CONFIG_SYS_MEMTEST_START 0x00001000
#define CONFIG_SYS_MEMTEST_END 0x07f00000
/* Early revs of this board will lock up hard when attempting
* to access the PMC registers, unless a JTAG debugger is
* connected, or some resistor modifications are made.

2
include/configs/MPC8315ERDB.h
View File

@@ -98,8 +98,6 @@
* Memory test
*/
#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
#define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest region */
#define CONFIG_SYS_MEMTEST_END 0x00140000
/*
* The reserved memory

2
include/configs/MPC8323ERDB.h
View File

@@ -85,8 +85,6 @@
* Memory test
*/
#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
#define CONFIG_SYS_MEMTEST_START 0x00030000 /* memtest region */
#define CONFIG_SYS_MEMTEST_END 0x03f00000
/*
* The reserved memory

2
include/configs/MPC832XEMDS.h
View File

@@ -85,8 +85,6 @@
* Memory test
*/
#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
#define CONFIG_SYS_MEMTEST_END 0x00100000
/*
* The reserved memory

2
include/configs/MPC8349EMDS.h
View File

@@ -18,8 +18,6 @@
#define CONFIG_E300 1 /* E300 Family */
#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
#define CONFIG_SYS_MEMTEST_END 0x00100000
/*
* DDR Setup

2
include/configs/MPC8349EMDS_SDRAM.h
View File

@@ -18,8 +18,6 @@
#define CONFIG_E300 1 /* E300 Family */
#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
#define CONFIG_SYS_MEMTEST_END 0x00100000
/*
* DDR Setup

2
include/configs/MPC8349ITX.h
View File

@@ -144,8 +144,6 @@
*/
#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/
#define CONFIG_SYS_83XX_DDR_USES_CS0
#define CONFIG_SYS_MEMTEST_START 0x1000 /* memtest region */
#define CONFIG_SYS_MEMTEST_END 0x2000
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
| DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)

2
include/configs/MPC837XEMDS.h
View File

@@ -107,8 +107,6 @@
* Memory test
*/
#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
#define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest region */
#define CONFIG_SYS_MEMTEST_END 0x00140000
/*
* The reserved memory

2
include/configs/MPC837XERDB.h
View File

@@ -132,8 +132,6 @@
* Memory test
*/
#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
#define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest region */
#define CONFIG_SYS_MEMTEST_END 0x0ef70010
/*
* The reserved memory

3
include/configs/MPC8536DS.h
View File

@@ -58,9 +58,6 @@
#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
#endif
#define CONFIG_SYS_MEMTEST_START 0x00010000 /* skip exception vectors */
#define CONFIG_SYS_MEMTEST_END 0x1f000000 /* skip u-boot at top of RAM */
/*
* Config the L2 Cache as L2 SRAM
*/

3
include/configs/MPC8540ADS.h
View File

@@ -58,9 +58,6 @@
#define CONFIG_L2_CACHE /* toggle L2 cache */
#define CONFIG_BTB /* toggle branch predition */
#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
#define CONFIG_SYS_MEMTEST_END 0x00400000
#define CONFIG_SYS_CCSRBAR 0xe0000000
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR

3
include/configs/MPC8541CDS.h
View File

@@ -32,9 +32,6 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_L2_CACHE /* toggle L2 cache */
#define CONFIG_BTB /* toggle branch predition */
#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x00400000
#define CONFIG_SYS_CCSRBAR 0xe0000000
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR

3
include/configs/MPC8544DS.h
View File

@@ -37,9 +37,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
*/
#define CONFIG_ENABLE_36BIT_PHYS 1
#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x00400000
#define CONFIG_SYS_CCSRBAR 0xe0000000
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR

12
include/configs/MPC8548CDS.h
View File

@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2004, 2007, 2010-2011 Freescale Semiconductor.
* Copyright 2020 NXP
*/
/*
@@ -46,9 +47,6 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
#endif
#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x00400000
#define CONFIG_SYS_CCSRBAR 0xe0000000
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
@@ -304,12 +302,18 @@ extern unsigned long get_clock_freq(void);
/*
* I2C
*/
#ifndef CONFIG_DM_I2C
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED 400000
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
#else
#define CONFIG_SYS_SPD_BUS_NUM 0
#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
#endif
#define CONFIG_SYS_I2C_FSL
/* EEPROM */
#define CONFIG_ID_EEPROM

3
include/configs/MPC8555CDS.h
View File

@@ -32,9 +32,6 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_L2_CACHE /* toggle L2 cache */
#define CONFIG_BTB /* toggle branch predition */
#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x00400000
#define CONFIG_SYS_CCSRBAR 0xe0000000
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR

3
include/configs/MPC8560ADS.h
View File

@@ -57,9 +57,6 @@
#define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */
#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
#define CONFIG_SYS_MEMTEST_END 0x00400000
#define CONFIG_SYS_CCSRBAR 0xe0000000
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR

3
include/configs/MPC8568MDS.h
View File

@@ -35,9 +35,6 @@ extern unsigned long get_clock_freq(void);
*/
#define CONFIG_ENABLE_36BIT_PHYS 1
#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x00400000
#define CONFIG_SYS_CCSRBAR 0xe0000000
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR

3
include/configs/MPC8569MDS.h
View File

@@ -47,9 +47,6 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_HWCONFIG
#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x00400000
/*
* Config the L2 Cache as L2 SRAM
*/

3
include/configs/MPC8572DS.h
View File

@@ -48,9 +48,6 @@
#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
#endif
#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x7fffffff
/*
* Config the L2 Cache as L2 SRAM
*/

3
include/configs/MPC8610HPCD.h
View File

@@ -56,9 +56,6 @@
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
#endif
#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
#define CONFIG_SYS_MEMTEST_END 0x00400000
/*
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)

3
include/configs/MPC8641HPCN.h
View File

@@ -63,9 +63,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
#endif
#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
#define CONFIG_SYS_MEMTEST_END 0x00400000
/*
* With the exception of PCI Memory and Rapid IO, most devices will simply
* add CONFIG_SYS_PHYS_ADDR_HIGH to the front of the 32-bit VA to get the PA

4
include/configs/MigoR.h
View File

@@ -27,12 +27,8 @@
/* SCIF */
#define CONFIG_CONS_SCIF0 1
#define CONFIG_SYS_MEMTEST_START (MIGO_R_SDRAM_BASE)
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
/* Enable alternate, more extensive, memory test */
/* Scratch address used by the alternate memory test */
#undef CONFIG_SYS_MEMTEST_SCRATCH
/* Enable temporary baudrate change while serial download */
#undef CONFIG_SYS_LOADS_BAUD_CHANGE

53
include/configs/P1010RDB.h
View File

@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2010-2011 Freescale Semiconductor, Inc.
* Copyright 2020 NXP
*/
/*
@@ -113,8 +114,6 @@
#if defined(CONFIG_PCI)
#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
/*
@@ -122,19 +121,13 @@
* Memory space is mapped 1-1, but I/O space must start from 0.
*/
/* controller 1, Slot 1, tgtid 1, Base address a000 */
#define CONFIG_SYS_PCIE1_NAME "mini PCIe Slot"
#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
#else
#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
#endif
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
#else
@@ -142,27 +135,45 @@
#endif
/* controller 2, Slot 2, tgtid 2, Base address 9000 */
#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
#else
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
#endif
#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
#else
#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
#endif
#if !defined(CONFIG_DM_PCI)
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_SYS_PCIE1_NAME "mini PCIe Slot"
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
#else
#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
#endif
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
#if defined(CONFIG_TARGET_P1010RDB_PA)
#define CONFIG_SYS_PCIE2_NAME "PCIe Slot"
#elif defined(CONFIG_TARGET_P1010RDB_PB)
#define CONFIG_SYS_PCIE2_NAME "mini PCIe Slot"
#endif
#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
#else
#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
#endif
#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
#else
#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
#endif
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
@@ -188,9 +199,6 @@
#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
#endif
#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x1fffffff
/* DDR Setup */
#define CONFIG_SYS_DDR_RAW_TIMING
#define CONFIG_DDR_SPD
@@ -522,17 +530,22 @@ extern unsigned long get_sdram_size(void);
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
/* I2C */
#ifndef CONFIG_DM_I2C
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED 400000
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
#define CONFIG_SYS_FSL_I2C2_SPEED 400000
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
#else
#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
#endif
#define I2C_PCA9557_ADDR1 0x18
#define I2C_PCA9557_ADDR2 0x19
#define I2C_PCA9557_BUS_NUM 0
#define CONFIG_SYS_I2C_FSL
/* I2C EEPROM */
#if defined(CONFIG_TARGET_P1010RDB_PB)

7
include/configs/P1022DS.h
View File

@@ -100,9 +100,6 @@
#define CONFIG_L2_CACHE
#define CONFIG_BTB
#define CONFIG_SYS_MEMTEST_START 0x00000000
#define CONFIG_SYS_MEMTEST_END 0x7fffffff
#define CONFIG_SYS_CCSRBAR 0xffe00000
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
@@ -359,8 +356,8 @@
#endif
/* I2C */
#ifndef CONFIG_DM_I2C
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED 400000
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
@@ -368,6 +365,8 @@
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
#define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}}
#endif
#define CONFIG_SYS_I2C_FSL
/*
* I2C2 EEPROM

3
include/configs/P1023RDB.h
View File

@@ -42,9 +42,6 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_ENABLE_36BIT_PHYS
#define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x02000000
/* Implement conversion of addresses in the LBC */
#define CONFIG_SYS_LBC_LBCR 0x00000000
#define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8

11
include/configs/P2041RDB.h
View File

@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2011-2012 Freescale Semiconductor, Inc.
* Copyright 2020 NXP
*/
/*
@@ -74,8 +75,6 @@ unsigned long get_board_sys_clk(unsigned long dummy);
#endif
#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x00400000
/*
* Config the L3 Cache as L3 SRAM
@@ -267,14 +266,20 @@ unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
/* I2C */
#ifndef CONFIG_DM_I2C
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED 400000
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
#define CONFIG_SYS_FSL_I2C2_SPEED 400000
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
#else
#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
#endif
#define CONFIG_SYS_I2C_FSL
/*
* RapidIO

2
include/configs/SBx81LIFKW.h
View File

@@ -80,8 +80,6 @@
/*
* Other required minimal configurations
*/
#define CONFIG_SYS_MEMTEST_START 0x00400000 /* 4M */
#define CONFIG_SYS_MEMTEST_END 0x007fffff /*(_8M -1) */
#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */
/*

2
include/configs/SBx81LIFXCAT.h
View File

@@ -80,8 +80,6 @@
/*
* Other required minimal configurations
*/
#define CONFIG_SYS_MEMTEST_START 0x00400000 /* 4M */
#define CONFIG_SYS_MEMTEST_END 0x007fffff /*(_8M -1) */
#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */
/*

13
include/configs/T102xQDS.h
View File

@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2014 Freescale Semiconductor, Inc.
* Copyright 2020 NXP
*/
/*
@@ -147,9 +148,6 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#endif
#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x00400000
/*
* Config the L3 Cache as L3 SRAM
*/
@@ -437,14 +435,20 @@ unsigned long get_board_ddr_clk(void);
#endif
/* I2C */
#ifndef CONFIG_DM_I2C
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
#define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
#define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
#else
#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
#endif
#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
#define I2C_MUX_PCA_ADDR 0x77
#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
@@ -460,6 +464,7 @@ unsigned long get_board_ddr_clk(void);
/* LDI/DVI Encoder for display */
#define CONFIG_SYS_I2C_LDI_ADDR 0x38
#define CONFIG_SYS_I2C_DVI_ADDR 0x75
#define CONFIG_SYS_I2C_DVI_BUS_NUM 0
/*
* RTC configuration

11
include/configs/T102xRDB.h
View File

@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2014 Freescale Semiconductor, Inc.
* Copyright 2020 NXP
*/
/*
@@ -162,9 +163,6 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#endif
#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x00400000
/*
* Config the L3 Cache as L3 SRAM
*/
@@ -434,15 +432,20 @@ unsigned long get_board_ddr_clk(void);
#endif
/* I2C */
#ifndef CONFIG_DM_I2C
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
#define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
#define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
#else
#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
#endif
#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
#define I2C_PCA6408_BUS_NUM 1
#define I2C_PCA6408_ADDR 0x20

10
include/configs/T1040QDS.h
View File

@@ -1,5 +1,6 @@
/*
* Copyright 2013-2014 Freescale Semiconductor, Inc.
* Copyright 2020 NXP
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -90,9 +91,6 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_ADDR_MAP
#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x00400000
/*
* Config the L3 Cache as L3 SRAM
*/
@@ -360,6 +358,8 @@ unsigned long get_board_ddr_clk(void);
#endif
/* I2C */
#ifndef CONFIG_DM_I2C
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
#define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */
@@ -374,6 +374,9 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
#endif
#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
#define I2C_MUX_PCA_ADDR 0x77
#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
@@ -385,6 +388,7 @@ unsigned long get_board_ddr_clk(void);
/* LDI/DVI Encoder for display */
#define CONFIG_SYS_I2C_LDI_ADDR 0x38
#define CONFIG_SYS_I2C_DVI_ADDR 0x75
#define CONFIG_SYS_I2C_DVI_BUS_NUM 0
/*
* RTC configuration

13
include/configs/T104xRDB.h
View File

@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2014 Freescale Semiconductor, Inc.
* Copyright 2020 NXP
*/
#ifndef __CONFIG_H
@@ -27,6 +28,7 @@
#define CONFIG_SPL_SKIP_RELOCATE
#define CONFIG_SPL_COMMON_INIT_DDR
#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
#undef CONFIG_DM_I2C
#endif
#define RESET_VECTOR_OFFSET 0x27FFC
#define BOOT_PAGE_OFFSET 0x27000
@@ -185,9 +187,6 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg
#define CONFIG_ADDR_MAP
#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x00400000
/*
* Config the L3 Cache as L3 SRAM
*/
@@ -459,8 +458,8 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg
#endif
/* I2C */
#ifndef CONFIG_DM_I2C
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */
#define CONFIG_SYS_FSL_I2C2_SPEED 400000
#define CONFIG_SYS_FSL_I2C3_SPEED 400000
@@ -473,7 +472,12 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
#else
#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
#endif
#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
/* I2C bus multiplexer */
#define I2C_MUX_PCA_ADDR 0x70
#define I2C_MUX_CH_DEFAULT 0x8
@@ -484,6 +488,7 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg
/* LDI/DVI Encoder for display */
#define CONFIG_SYS_I2C_LDI_ADDR 0x38
#define CONFIG_SYS_I2C_DVI_ADDR 0x75
#define CONFIG_SYS_I2C_DVI_BUS_NUM 0
/*
* RTC configuration

7
include/configs/T208xQDS.h
View File

@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2011-2013 Freescale Semiconductor, Inc.
* Copyright 2020 NXP
*/
/*
@@ -385,8 +386,8 @@ unsigned long get_board_ddr_clk(void);
/*
* I2C
*/
#ifndef CONFIG_DM_I2C
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
#define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
@@ -399,6 +400,10 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_SYS_FSL_I2C2_SPEED 100000
#define CONFIG_SYS_FSL_I2C3_SPEED 100000
#define CONFIG_SYS_FSL_I2C4_SPEED 100000
#endif
#define CONFIG_SYS_I2C_FSL
#define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
#define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */
#define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */

13
include/configs/T208xRDB.h
View File

@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2014 Freescale Semiconductor, Inc.
* Copyright 2020 NXP
*/
/*
@@ -99,9 +100,6 @@
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#endif
#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x00400000
#if defined(CONFIG_SPIFLASH)
#elif defined(CONFIG_SDCARD)
#define CONFIG_SYS_MMC_ENV_DEV 0
@@ -333,8 +331,8 @@ unsigned long get_board_ddr_clk(void);
/*
* I2C
*/
#ifndef CONFIG_DM_I2C
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
#define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
@@ -347,6 +345,13 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_SYS_FSL_I2C2_SPEED 100000
#define CONFIG_SYS_FSL_I2C3_SPEED 100000
#define CONFIG_SYS_FSL_I2C4_SPEED 100000
#else
#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
#endif
#define CONFIG_SYS_I2C_FSL
#define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
#define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */
#define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */

13
include/configs/T4240QDS.h
View File

@@ -280,6 +280,19 @@ unsigned long get_board_ddr_clk(void);
#endif
/* I2C */
#ifndef CONFIG_DM_I2C
#define CONFIG_SYS_I2C
#else
#undef CONFIG_SYS_I2C
#undef CONFIG_SYS_FSL_I2C2_OFFSET
#undef CONFIG_SYS_FSL_I2C2_SLAVE
#undef CONFIG_SYS_FSL_I2C2_SPEED
#undef CONFIG_SYS_FSL_I2C_SLAVE
#undef CONFIG_SYS_FSL_I2C_SPEED
#undef CONFIG_SYS_FSL_I2C_OFFSET
#endif
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */
#define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */
#define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */

12
include/configs/T4240RDB.h
View File

@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2014 Freescale Semiconductor, Inc.
* Copyright 2020 NXP
*/
/*
@@ -80,9 +81,6 @@
#define CONFIG_ADDR_MAP
#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x00400000
/*
* Config the L3 Cache as L3 SRAM
*/
@@ -159,12 +157,18 @@
#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
/* I2C */
#ifndef CONFIG_DM_I2C
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
#else
#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
#endif
#define CONFIG_SYS_I2C_FSL
/*
* General PCI

2
include/configs/TQM834x.h
View File

@@ -30,8 +30,6 @@
#undef CONFIG_SPD_EEPROM /* do not use SPD EEPROM for DDR setup */
#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
#define CONFIG_SYS_MEMTEST_END 0x00100000
/*
* FLASH on the Local Bus

3
include/configs/UCP1020.h
View File

@@ -164,9 +164,6 @@
#define CONFIG_ENABLE_36BIT_PHYS
#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x1fffffff
#define CONFIG_SYS_CCSRBAR 0xffe00000
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR

2
include/configs/adp-ae3xx.h
View File

@@ -112,8 +112,6 @@
#define CONFIG_SYS_LOAD_ADDR 0x300000
/* memtest works on 63 MB in DRAM */
#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0
#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + 0x03F00000)
/*
* Static memory controller configuration

2
include/configs/adp-ag101p.h
View File

@@ -224,8 +224,6 @@
#define CONFIG_SYS_LOAD_ADDR 0x300000
/* memtest works on 63 MB in DRAM */
#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0
#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + 0x03F00000)
/*
* Static memory controller configuration

4
include/configs/advantech_dms-ba16.h
View File

@@ -183,10 +183,6 @@
/* Miscellaneous configurable options */
#define CONFIG_SYS_MEMTEST_START 0x10000000
#define CONFIG_SYS_MEMTEST_END 0x10010000
#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
/* Physical Memory Map */

3
include/configs/am3517_crane.h
View File

@@ -145,9 +145,6 @@
#define CONFIG_SYS_MAXARGS 32 /* max number of command */
/* args */
/* memtest works on */
#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
0x01F00000) /* 31MB */
#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */
/* address */

3
include/configs/am3517_evm.h
View File

@@ -153,9 +153,6 @@
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
/* memtest works on */
#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
0x01F00000) /* 31MB */
/* Physical Memory Map */
#define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024)

3
include/configs/amcore.h
View File

@@ -32,9 +32,6 @@
#define CONFIG_SYS_LOAD_ADDR 0x20000 /* default load address */
#define CONFIG_SYS_MEMTEST_START 0x0
#define CONFIG_SYS_MEMTEST_END 0x1000000
#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_CLK 45000000

2
include/configs/ap121.h
View File

@@ -35,7 +35,5 @@
/*
* Diagnostics
*/
#define CONFIG_SYS_MEMTEST_START 0x80100000
#define CONFIG_SYS_MEMTEST_END 0x83f00000
#endif /* __CONFIG_H */

2
include/configs/ap143.h
View File

@@ -39,7 +39,5 @@
/*
* Diagnostics
*/
#define CONFIG_SYS_MEMTEST_START 0x80100000
#define CONFIG_SYS_MEMTEST_END 0x83f00000
#endif /* __CONFIG_H */

2
include/configs/ap152.h
View File

@@ -41,7 +41,5 @@
/*
* Diagnostics
*/
#define CONFIG_SYS_MEMTEST_START 0x80100000
#define CONFIG_SYS_MEMTEST_END 0x83f00000
#endif /* __CONFIG_H */

3
include/configs/apalis-imx8.h
View File

@@ -83,9 +83,6 @@
#define CONFIG_SYS_INIT_SP_ADDR 0x80200000
#define CONFIG_SYS_MEMTEST_START 0x88000000
#define CONFIG_SYS_MEMTEST_END 0x89000000
/* Environment in eMMC, before config block at the end of 1st "boot sector" */
#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 eMMC */
#define CONFIG_SYS_MMC_ENV_PART 1

4
include/configs/apalis_imx6.h
View File

@@ -210,10 +210,6 @@
#undef CONFIG_SYS_MAXARGS
#define CONFIG_SYS_MAXARGS 48
#define CONFIG_SYS_MEMTEST_START 0x10000000
#define CONFIG_SYS_MEMTEST_END 0x10010000
#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
/* Physical Memory Map */

2
include/configs/apf27.h
View File

@@ -54,8 +54,6 @@
#define PHYS_SDRAM_2 0xB0000000
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (512<<10))
#define CONFIG_SYS_MEMTEST_START 0xA0000000 /* memtest test area */
#define CONFIG_SYS_MEMTEST_END 0xA0300000 /* 3 MiB RAM test */
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE \
+ PHYS_SDRAM_1_SIZE - 0x0100000)

4
include/configs/aristainetos2.h
View File

@@ -407,10 +407,6 @@
#define CONFIG_ARP_TIMEOUT 200UL
#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x100000)
#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR

4
include/configs/armadillo-800eva.h
View File

@@ -40,10 +40,6 @@
#define SCIF4_BASE 0xe6c80000
#define CONFIG_SCIF_A
#define CONFIG_SYS_MEMTEST_START (ARMADILLO_800EVA_SDRAM_BASE)
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
504 * 1024 * 1024)
#undef CONFIG_SYS_MEMTEST_SCRATCH
#undef CONFIG_SYS_LOADS_BAUD_CHANGE
#define CONFIG_SYS_SDRAM_BASE (ARMADILLO_800EVA_SDRAM_BASE)

3
include/configs/astro_mcf5373l.h
View File

@@ -171,9 +171,6 @@
/* Defines memory range for test */
#define CONFIG_SYS_MEMTEST_START 0x40020000
#define CONFIG_SYS_MEMTEST_END 0x41ffffff
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)

4
include/configs/at91rm9200ek.h
View File

@@ -57,10 +57,6 @@
#define CONFIG_SYS_SDRAM_BASE 0x20000000
#define CONFIG_SYS_SDRAM_SIZE SZ_32M
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END \
(CONFIG_SYS_MEMTEST_START + CONFIG_SYS_SDRAM_SIZE - SZ_256K)
/*
* LowLevel Init
*/

3
include/configs/at91sam9260ek.h
View File

@@ -108,9 +108,6 @@
#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END 0x23e00000
#ifdef CONFIG_SYS_USE_DATAFLASH_CS0
/* bootstrap + u-boot + env + linux in dataflash on CS0 */

3
include/configs/at91sam9261ek.h
View File

@@ -95,9 +95,6 @@
#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END 0x23e00000
#ifdef CONFIG_SYS_USE_DATAFLASH_CS0
/* bootstrap + u-boot + env + linux in dataflash on CS0 */

3
include/configs/at91sam9263ek.h
View File

@@ -208,9 +208,6 @@
#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END 0x23e00000
#ifdef CONFIG_SYS_USE_DATAFLASH
/* bootstrap + u-boot + env + linux in dataflash on CS0 */

3
include/configs/at91sam9m10g45ek.h
View File

@@ -69,9 +69,6 @@
#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END 0x23e00000
#ifdef CONFIG_NAND_BOOT
/* bootstrap + u-boot + env in nandflash */

3
include/configs/at91sam9n12ek.h
View File

@@ -68,9 +68,6 @@
#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END 0x26e00000
/* USB host */
#ifdef CONFIG_CMD_USB
#define CONFIG_USB_ATMEL

3
include/configs/at91sam9rlek.h
View File

@@ -66,9 +66,6 @@
#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END 0x23e00000
#ifdef CONFIG_SYS_USE_DATAFLASH
/* bootstrap + u-boot + env + linux in dataflash on CS0 */

3
include/configs/at91sam9x5ek.h
View File

@@ -67,9 +67,6 @@
#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END 0x26e00000
#ifdef CONFIG_NAND_BOOT
/* bootstrap + u-boot + env + linux in nandflash */
#define CONFIG_BOOTCOMMAND "nand read " \

2
include/configs/ax25-ae350.h
View File

@@ -91,8 +91,6 @@
/*
* memtest works on 512 MB in DRAM
*/
#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0
#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE)
/*
* FLASH and environment organization

3
include/configs/bk4r1.h
View File

@@ -241,9 +241,6 @@
/* Miscellaneous configurable options */
#define CONFIG_SYS_MEMTEST_START 0x80010000
#define CONFIG_SYS_MEMTEST_END 0x87C00000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
/* Physical memory map */

1
include/configs/blanche.h
View File

@@ -22,7 +22,6 @@
#define RCAR_GEN2_SDRAM_SIZE (1024u * 1024 * 1024)
#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024)
#undef CONFIG_SYS_MEMTEST_SCRATCH
#undef CONFIG_SYS_LOADS_BAUD_CHANGE
/* FLASH */

3
include/configs/boston.h
View File

@@ -35,9 +35,6 @@
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x08000000)
#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0)
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x10000000)
#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
/*

2
include/configs/brppt2.h
View File

@@ -90,8 +90,6 @@ BUR_COMMON_ENV \
/* RAM */
#define PHYS_SDRAM_1 MMDC0_ARB_BASE_ADDR
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_MEMTEST_START 0x10000000
#define CONFIG_SYS_MEMTEST_END 0x10010000
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
#define CONFIG_SYS_INIT_SP_OFFSET \

2
include/configs/caddy2.h
View File

@@ -26,8 +26,6 @@
#undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */
#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
#define CONFIG_SYS_MEMTEST_END 0x00100000
/*
* DDR Setup

4
include/configs/capricorn-common.h
View File

@@ -167,10 +167,6 @@
#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1 GB */
#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 GB */
#define CONFIG_SYS_MEMTEST_START 0xA0000000
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
(PHYS_SDRAM_1_SIZE >> 2))
/* Console buffer and boot args */
#define CONFIG_SYS_CBSIZE 2048
#define CONFIG_SYS_MAXARGS 64

4
include/configs/cgtqmx6eval.h
View File

@@ -187,10 +187,6 @@
"fi; " \
"else run netboot; fi"
#define CONFIG_SYS_MEMTEST_START 0x10000000
#define CONFIG_SYS_MEMTEST_END 0x10010000
#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR

2
include/configs/ci20.h
View File

@@ -25,8 +25,6 @@
#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
#define CONFIG_SYS_LOAD_ADDR 0x81000000
#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
#define CONFIG_SYS_MEMTEST_START 0x80000000
#define CONFIG_SYS_MEMTEST_END 0x88000000
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE

3
include/configs/cl-som-imx7.h
View File

@@ -111,9 +111,6 @@
"echo eMMC boot attempt ...; run emmcbootscript; run emmcboot; " \
"echo USB boot attempt ...; run usbbootscript; "
#define CONFIG_SYS_MEMTEST_START 0x80000000
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x20000000)
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_SYS_HZ 1000

2
include/configs/cm_fx6.h
View File

@@ -24,8 +24,6 @@
#define PHYS_SDRAM_1 MMDC0_ARB_BASE_ADDR
#define PHYS_SDRAM_2 MMDC1_ARB_BASE_ADDR
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_MEMTEST_START 0x10000000
#define CONFIG_SYS_MEMTEST_END 0x10010000
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
#define CONFIG_SYS_INIT_SP_OFFSET \

3
include/configs/cm_t35.h
View File

@@ -148,10 +148,7 @@
#define CONFIG_TIMESTAMP
#define CONFIG_SYS_AUTOLOAD "no"
#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */
/* works on */
#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
0x01F00000) /* 31MB */
#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */
/* load address */

3
include/configs/cobra5272.h
View File

@@ -155,9 +155,6 @@ from which user programs will be started */
* ---
*/
#define CONFIG_SYS_MEMTEST_START 0x400
#define CONFIG_SYS_MEMTEST_END 0x380000
/* ---
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)

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