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Minor coding style cleanup. Update CHANGELOG.

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This commit is contained in:
Wolfgang Denk
2007-07-05 11:12:16 +02:00
parent dca3b3d6d6
commit b6b4684546
11 changed files with 474 additions and 67 deletions
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2
include/configs/MPC8260ADS.h
View File

@@ -246,8 +246,6 @@
#endif /* CONFIG_ADSTYPE >= CFG_PQ2FADS */
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#define CONFIG_BOOTCOMMAND "bootm fff80000" /* autoboot command */
#define CONFIG_BOOTARGS "root=/dev/mtdblock2"

9
include/configs/MPC8266ADS.h
View File

@@ -141,11 +141,9 @@
*/
#define SPD_EEPROM_ADDRESS 0x50
#define CONFIG_8260_CLKIN 66000000 /* in Hz */
#define CONFIG_BAUDRATE 115200
/*
* Command line configuration.
*/
@@ -214,8 +212,6 @@
CONFIG_BOOTP_BOOTFILESIZE | \
CONFIG_BOOTP_DNS)
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#if defined(CONFIG_CMD_KGDB)
@@ -285,7 +281,6 @@
#define SDRAM_SPD_ADDR 0x50
/*-----------------------------------------------------------------------
* BR2,BR3 - Base Register
* Ref: Section 10.3.1 on page 10-14
@@ -383,7 +378,6 @@
#error "INVALID SDRAM CONFIGURATION"
#endif
#define RS232EN_1 0x02000002
#define RS232EN_2 0x01000001
#define FETHIEN 0x08000008
@@ -395,7 +389,6 @@
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
/* Use this HRCW for booting from address 0xfe00000 (JP3 in setting 1-2) */
/* 0x0EB2B645 */
#define CFG_HRCW_MASTER (( HRCW_BPS11 | HRCW_CIP ) |\
@@ -452,13 +445,11 @@
# define CFG_ENV_SIZE 0x200
#endif /* CFG_RAMBOOT */
#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
/*-----------------------------------------------------------------------
* HIDx - Hardware Implementation-dependent Registers 2-11
*-----------------------------------------------------------------------

6
include/configs/TQM834x.h
View File

@@ -281,7 +281,6 @@ extern int tqm834x_num_flash_banks;
#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
#undef CONFIG_EEPRO100
#define CONFIG_EEPRO100
#undef CONFIG_TULIP
@@ -316,7 +315,6 @@ extern int tqm834x_num_flash_banks;
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
/*
* Command line configuration.
*/
@@ -339,10 +337,6 @@ extern int tqm834x_num_flash_banks;
#undef CONFIG_CMD_LOADS
#endif
/*
* Miscellaneous configurable options
*/

3
include/configs/acadia.h
View File

@@ -299,7 +299,6 @@
#define CONFIG_SUPPORT_VFAT
/*
* Command line configuration.
*/
@@ -331,8 +330,6 @@
#undef CONFIG_CMD_IMLS
#endif
#undef CONFIG_WATCHDOG /* watchdog disabled */
/*-----------------------------------------------------------------------

3
include/configs/atstk1002.h
View File

@@ -111,7 +111,6 @@
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_SUBNETMASK \
| CONFIG_BOOTP_GATEWAY)
/*
* Command line configuration.
*/
@@ -129,8 +128,6 @@
#undef CONFIG_CMD_SETGETDCR
#undef CONFIG_CMD_XIMG
#define CONFIG_ATMEL_USART 1
#define CONFIG_MACB 1
#define CONFIG_PIO2 1

5
include/configs/bf537-stamp.h
View File

@@ -166,8 +166,6 @@
#define CONFIG_NETCONSOLE 1
#define CONFIG_NET_MULTI 1
/*
* Command line configuration.
*/
@@ -196,7 +194,6 @@
#endif
#if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT)
#define CONFIG_CMD_DHCP
@@ -209,8 +206,6 @@
#endif
#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw console=ttyBF0,57600"
#define CONFIG_LOADADDR 0x1000000

3
include/configs/cpci5200.h
View File

@@ -99,7 +99,6 @@
#define CONFIG_USB_STORAGE
#endif
/*
* Command line configuration.
*/
@@ -118,8 +117,6 @@
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_DATE
#if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
# define CFG_LOWBOOT 1
# define CFG_LOWBOOT16 1

3
include/configs/csb472.h
View File

@@ -80,8 +80,6 @@
CONFIG_BOOTP_DNS2 | \
CONFIG_BOOTP_BOOTFILESIZE )
/*
* Command line configuration.
*/
@@ -98,7 +96,6 @@
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
/*
* Serial download configuration
*

4
include/configs/ml401.h
View File

@@ -145,8 +145,6 @@
#define CFG_FLASH_PROTECTION /* hardware flash protection */
#endif /* !FLASH */
/*
* Command line configuration.
*/
@@ -181,8 +179,6 @@
#endif
#endif
#if defined(CONFIG_CMD_JFFS2)
/* JFFS2 partitions */
#define CONFIG_JFFS2_CMDLINE /* mtdparts command line support */

11
include/configs/sc520_cdp.h
View File

@@ -64,10 +64,8 @@
*/
#define CONFIG_MALLOC_SIZE (CFG_ENV_SIZE + 128*1024)
#define CONFIG_BAUDRATE 9600
/*
* Command line configuration.
*/
@@ -79,8 +77,6 @@
#define CONFIG_CMD_NET
#define CONFIG_CMD_EEPROM
#define CONFIG_BOOTDELAY 15
#define CONFIG_BOOTARGS "root=/dev/mtdblock0 console=ttyS0,9600"
/* #define CONFIG_BOOTCOMMAND "bootm 38000000" */
@@ -90,7 +86,6 @@
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
/*
* Miscellaneous configurable options
*/
@@ -113,7 +108,6 @@
/* valid baudrates */
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
@@ -122,8 +116,6 @@
/*-----------------------------------------------------------------------
* FLASH and environment organization
*/
#define CFG_MAX_FLASH_BANKS 3 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
@@ -134,11 +126,9 @@
#define CONFIG_SPI_EEPROM /* Support for SPI EEPROMs (AT25128) */
#define CONFIG_MW_EEPROM /* Support for MicroWire EEPROMs (AT93LC46) */
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
/* Environment in EEPROM */
#define CFG_ENV_IS_IN_EEPROM 1
#define CONFIG_SPI
@@ -218,7 +208,6 @@
#define CONFIG_I8042_KBD
#define CFG_ISA_IO 0
/************************************************************
* RTC
***********************************************************/