ppc4xx: Move ppc4xx headers to powerpc include directory
This patch moves some ppc4xx related headers from the common include directory (include/) to the powerpc specific one (arch/powerpc/include/asm/). This way to common include directory is not so cluttered with files. Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Stefan Roese
@@ -1,129 +0,0 @@
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/* include/mal.h, openbios_walnut, walnut_bios 8/6/99 08:48:40 */
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/*----------------------------------------------------------------------------+
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| This source code is dual-licensed. You may use it under the terms of the
|
||||
| GNU General Public License version 2, or under the license below.
|
||||
|
|
||||
| This source code has been made available to you by IBM on an AS-IS
|
||||
| basis. Anyone receiving this source is licensed under IBM
|
||||
| copyrights to use it in any way he or she deems fit, including
|
||||
| copying it, modifying it, compiling it, and redistributing it either
|
||||
| with or without modifications. No license under IBM patents or
|
||||
| patent applications is to be implied by the copyright license.
|
||||
|
|
||||
| Any user of this software should understand that IBM cannot provide
|
||||
| technical support for this software and will not be responsible for
|
||||
| any consequences resulting from the use of this software.
|
||||
|
|
||||
| Any person who transfers this source code or any derivative work
|
||||
| must include the IBM copyright notice, this paragraph, and the
|
||||
| preceding two paragraphs in the transferred software.
|
||||
|
|
||||
| COPYRIGHT I B M CORPORATION 1999
|
||||
| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
|
||||
+----------------------------------------------------------------------------*/
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/*----------------------------------------------------------------------------+
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|
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| File Name: mal.h
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|
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| Function: Header file for the MAL (MADMAL) macro on the 405GP.
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|
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| Author: Mark Wisner
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|
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| Change Activity-
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|
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| Date Description of Change BY
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| --------- --------------------- ---
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| 29-Apr-99 Created MKW
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|
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+----------------------------------------------------------------------------*/
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/*----------------------------------------------------------------------------+
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| 17-Nov-03 Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
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| Added register bit definitions to support multiple channels
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+----------------------------------------------------------------------------*/
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#ifndef _mal_h_
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#define _mal_h_
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/* MADMAL transmit and receive status/control bits */
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/* for COMMAC bits, refer to the COMMAC header file */
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#define MAL_TX_CTRL_READY 0x8000
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#define MAL_TX_CTRL_WRAP 0x4000
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#define MAL_TX_CTRL_CM 0x2000
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#define MAL_TX_CTRL_LAST 0x1000
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#define MAL_TX_CTRL_INTR 0x0400
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#define MAL_RX_CTRL_EMPTY 0x8000
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#define MAL_RX_CTRL_WRAP 0x4000
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#define MAL_RX_CTRL_CM 0x2000
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#define MAL_RX_CTRL_LAST 0x1000
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#define MAL_RX_CTRL_FIRST 0x0800
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#define MAL_RX_CTRL_INTR 0x0400
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/* Configuration Reg */
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#define MAL_CR_MMSR 0x80000000
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#define MAL_CR_PLBP_1 0x00400000 /* lowsest is 00 */
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#define MAL_CR_PLBP_2 0x00800000
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#define MAL_CR_PLBP_3 0x00C00000 /* highest */
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#define MAL_CR_GA 0x00200000
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#define MAL_CR_OA 0x00100000
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#define MAL_CR_PLBLE 0x00080000
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#define MAL_CR_PLBLT_1 0x00040000
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#define MAL_CR_PLBLT_2 0x00020000
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#define MAL_CR_PLBLT_3 0x00010000
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#define MAL_CR_PLBLT_4 0x00008000
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#define MAL_CR_PLBLT_DEFAULT 0x00078000 /* ????? */
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#define MAL_CR_PLBB 0x00004000
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#define MAL_CR_OPBBL 0x00000080
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#define MAL_CR_EOPIE 0x00000004
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#define MAL_CR_LEA 0x00000002
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#define MAL_CR_MSD 0x00000001
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/* Error Status Reg */
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#define MAL_ESR_EVB 0x80000000
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#define MAL_ESR_CID 0x40000000
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#define MAL_ESR_DE 0x00100000
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#define MAL_ESR_ONE 0x00080000
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#define MAL_ESR_OTE 0x00040000
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#define MAL_ESR_OSE 0x00020000
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#define MAL_ESR_PEIN 0x00010000
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/* same bit position as the IER */
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/* VV VV */
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#define MAL_ESR_DEI 0x00000010
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#define MAL_ESR_ONEI 0x00000008
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#define MAL_ESR_OTEI 0x00000004
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#define MAL_ESR_OSEI 0x00000002
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#define MAL_ESR_PBEI 0x00000001
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/* ^^ ^^ */
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/* Mal IER */
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#if defined(CONFIG_440SPE) || \
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defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
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defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
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defined(CONFIG_405EX)
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#define MAL_IER_PT 0x00000080
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#define MAL_IER_PRE 0x00000040
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#define MAL_IER_PWE 0x00000020
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#define MAL_IER_DE 0x00000010
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#define MAL_IER_OTE 0x00000004
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#define MAL_IER_OE 0x00000002
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#define MAL_IER_PE 0x00000001
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#else
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#define MAL_IER_DE 0x00000010
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#define MAL_IER_NE 0x00000008
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#define MAL_IER_TE 0x00000004
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#define MAL_IER_OPBE 0x00000002
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#define MAL_IER_PLBE 0x00000001
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#endif
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/* MAL Channel Active Set and Reset Registers */
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#define MAL_TXRX_CASR (0x80000000)
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#define MAL_TXRX_CASR_V(__x) (__x) /* Channel 0 shifts 0, channel 1 shifts 1, etc */
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/* MAL Buffer Descriptor structure */
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typedef struct {
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short ctrl; /* MAL / Commac status control bits */
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short data_len; /* Max length is 4K-1 (12 bits) */
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char *data_ptr; /* pointer to actual data buffer */
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} mal_desc_t;
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#endif
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@@ -1,127 +0,0 @@
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/*
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* (C) Copyright 2007-2009
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _4xx_i2c_h_
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#define _4xx_i2c_h_
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#define IIC_OK 0
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#define IIC_NOK 1
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#define IIC_NOK_LA 2 /* Lost arbitration */
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#define IIC_NOK_ICT 3 /* Incomplete transfer */
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#define IIC_NOK_XFRA 4 /* Transfer aborted */
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#define IIC_NOK_DATA 5 /* No data in buffer */
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#define IIC_NOK_TOUT 6 /* Transfer timeout */
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#define IIC_TIMEOUT 1 /* 1 second */
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#if defined(CONFIG_I2C_MULTI_BUS)
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#define I2C_BUS_OFFS (i2c_bus_num * 0x100)
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#else
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#define I2C_BUS_OFFS (0x000)
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#endif /* CONFIG_I2C_MULTI_BUS */
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#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
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defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
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defined(CONFIG_460EX) || defined(CONFIG_460GT)
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#define I2C_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x00000700 + I2C_BUS_OFFS)
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#elif defined(CONFIG_440) || defined(CONFIG_405EX)
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/* all remaining 440 variants */
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#define I2C_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x00000400 + I2C_BUS_OFFS)
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#else
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/* all 405 variants */
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#define I2C_BASE_ADDR (0xEF600500 + I2C_BUS_OFFS)
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#endif
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struct ppc4xx_i2c {
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u8 mdbuf;
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u8 res1;
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u8 sdbuf;
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u8 res2;
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u8 lmadr;
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u8 hmadr;
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u8 cntl;
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u8 mdcntl;
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u8 sts;
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u8 extsts;
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u8 lsadr;
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u8 hsadr;
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u8 clkdiv;
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u8 intrmsk;
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u8 xfrcnt;
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u8 xtcntlss;
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u8 directcntl;
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u8 intr;
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};
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/* MDCNTL Register Bit definition */
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#define IIC_MDCNTL_HSCL 0x01
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#define IIC_MDCNTL_EUBS 0x02
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#define IIC_MDCNTL_EINT 0x04
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#define IIC_MDCNTL_ESM 0x08
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#define IIC_MDCNTL_FSM 0x10
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#define IIC_MDCNTL_EGC 0x20
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#define IIC_MDCNTL_FMDB 0x40
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#define IIC_MDCNTL_FSDB 0x80
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/* CNTL Register Bit definition */
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#define IIC_CNTL_PT 0x01
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#define IIC_CNTL_READ 0x02
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#define IIC_CNTL_CHT 0x04
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#define IIC_CNTL_RPST 0x08
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/* bit 2/3 for Transfer count*/
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#define IIC_CNTL_AMD 0x40
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#define IIC_CNTL_HMT 0x80
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/* STS Register Bit definition */
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#define IIC_STS_PT 0x01
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#define IIC_STS_IRQA 0x02
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#define IIC_STS_ERR 0x04
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#define IIC_STS_SCMP 0x08
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#define IIC_STS_MDBF 0x10
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#define IIC_STS_MDBS 0x20
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#define IIC_STS_SLPR 0x40
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#define IIC_STS_SSS 0x80
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/* EXTSTS Register Bit definition */
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#define IIC_EXTSTS_XFRA 0x01
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#define IIC_EXTSTS_ICT 0x02
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#define IIC_EXTSTS_LA 0x04
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/* XTCNTLSS Register Bit definition */
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#define IIC_XTCNTLSS_SRST 0x01
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#define IIC_XTCNTLSS_EPI 0x02
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#define IIC_XTCNTLSS_SDBF 0x04
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#define IIC_XTCNTLSS_SBDD 0x08
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#define IIC_XTCNTLSS_SWS 0x10
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#define IIC_XTCNTLSS_SWC 0x20
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#define IIC_XTCNTLSS_SRS 0x40
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#define IIC_XTCNTLSS_SRC 0x80
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/* IICx_DIRECTCNTL register */
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#define IIC_DIRCNTL_SDAC 0x08
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#define IIC_DIRCNTL_SCC 0x04
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#define IIC_DIRCNTL_MSDA 0x02
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#define IIC_DIRCNTL_MSC 0x01
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#define DIRCTNL_FREE(v) (((v) & 0x0f) == 0x0f)
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#endif
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@@ -96,7 +96,7 @@ typedef volatile unsigned char vu_char;
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#include <asm/immap_83xx.h>
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#endif
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#ifdef CONFIG_4xx
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#include <ppc4xx.h>
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#include <asm/ppc4xx.h>
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#endif
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#ifdef CONFIG_HYMOD
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#include <board/hymod/hymod.h>
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832
include/ppc405.h
832
include/ppc405.h
@@ -1,832 +0,0 @@
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/*----------------------------------------------------------------------------+
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||||
| This source code is dual-licensed. You may use it under the terms of the
|
||||
| GNU General Public License version 2, or under the license below.
|
||||
|
|
||||
| This source code has been made available to you by IBM on an AS-IS
|
||||
| basis. Anyone receiving this source is licensed under IBM
|
||||
| copyrights to use it in any way he or she deems fit, including
|
||||
| copying it, modifying it, compiling it, and redistributing it either
|
||||
| with or without modifications. No license under IBM patents or
|
||||
| patent applications is to be implied by the copyright license.
|
||||
|
|
||||
| Any user of this software should understand that IBM cannot provide
|
||||
| technical support for this software and will not be responsible for
|
||||
| any consequences resulting from the use of this software.
|
||||
|
|
||||
| Any person who transfers this source code or any derivative work
|
||||
| must include the IBM copyright notice, this paragraph, and the
|
||||
| preceding two paragraphs in the transferred software.
|
||||
|
|
||||
| COPYRIGHT I B M CORPORATION 1999
|
||||
| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
|
||||
+----------------------------------------------------------------------------*/
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#ifndef __PPC405_H__
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#define __PPC405_H__
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/* Define bits and masks for real-mode storage attribute control registers */
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#define PPC_128MB_SACR_BIT(addr) ((addr) >> 27)
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#define PPC_128MB_SACR_VALUE(addr) PPC_REG_VAL(PPC_128MB_SACR_BIT(addr),1)
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#ifndef CONFIG_IOP480
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#define CONFIG_SYS_DCACHE_SIZE (16 << 10) /* For AMCC 405 CPUs */
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#else
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#define CONFIG_SYS_DCACHE_SIZE (2 << 10) /* For PLX IOP480(403)*/
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#endif
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/******************************************************************************
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* Special for PPC405GP
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******************************************************************************/
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/******************************************************************************
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* DMA
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******************************************************************************/
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#define DMA_DCR_BASE 0x100
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#define DMACR0 (DMA_DCR_BASE+0x00) /* DMA channel control register 0 */
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#define DMACT0 (DMA_DCR_BASE+0x01) /* DMA count register 0 */
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#define DMADA0 (DMA_DCR_BASE+0x02) /* DMA destination address register 0 */
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#define DMASA0 (DMA_DCR_BASE+0x03) /* DMA source address register 0 */
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#define DMASB0 (DMA_DCR_BASE+0x04) /* DMA scatter/gather descriptor addr 0 */
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#define DMACR1 (DMA_DCR_BASE+0x08) /* DMA channel control register 1 */
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#define DMACT1 (DMA_DCR_BASE+0x09) /* DMA count register 1 */
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#define DMADA1 (DMA_DCR_BASE+0x0a) /* DMA destination address register 1 */
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#define DMASA1 (DMA_DCR_BASE+0x0b) /* DMA source address register 1 */
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#define DMASB1 (DMA_DCR_BASE+0x0c) /* DMA scatter/gather descriptor addr 1 */
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#define DMACR2 (DMA_DCR_BASE+0x10) /* DMA channel control register 2 */
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#define DMACT2 (DMA_DCR_BASE+0x11) /* DMA count register 2 */
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#define DMADA2 (DMA_DCR_BASE+0x12) /* DMA destination address register 2 */
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#define DMASA2 (DMA_DCR_BASE+0x13) /* DMA source address register 2 */
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#define DMASB2 (DMA_DCR_BASE+0x14) /* DMA scatter/gather descriptor addr 2 */
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#define DMACR3 (DMA_DCR_BASE+0x18) /* DMA channel control register 3 */
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#define DMACT3 (DMA_DCR_BASE+0x19) /* DMA count register 3 */
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#define DMADA3 (DMA_DCR_BASE+0x1a) /* DMA destination address register 3 */
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#define DMASA3 (DMA_DCR_BASE+0x1b) /* DMA source address register 3 */
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#define DMASB3 (DMA_DCR_BASE+0x1c) /* DMA scatter/gather descriptor addr 3 */
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#define DMASR (DMA_DCR_BASE+0x20) /* DMA status register */
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#define DMASGC (DMA_DCR_BASE+0x23) /* DMA scatter/gather command register */
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#define DMAADR (DMA_DCR_BASE+0x24) /* DMA address decode register */
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#ifndef CONFIG_405EP
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/******************************************************************************
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* Decompression Controller
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******************************************************************************/
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#define DECOMP_DCR_BASE 0x14
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#define KIAR (DECOMP_DCR_BASE+0x0) /* Decompression controller addr reg */
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#define KIDR (DECOMP_DCR_BASE+0x1) /* Decompression controller data reg */
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/* values for kiar register - indirect addressing of these regs */
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#define KCONF 0x40 /* decompression core config register */
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#endif
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/******************************************************************************
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* Power Management
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******************************************************************************/
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#ifdef CONFIG_405EX
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#define POWERMAN_DCR_BASE 0xb0
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#else
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#define POWERMAN_DCR_BASE 0xb8
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#endif
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#define CPMSR (POWERMAN_DCR_BASE+0x0) /* Power management status */
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#define CPMER (POWERMAN_DCR_BASE+0x1) /* Power management enable */
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#define CPMFR (POWERMAN_DCR_BASE+0x2) /* Power management force */
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/******************************************************************************
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* Extrnal Bus Controller
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******************************************************************************/
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/* values for EBC0_CFGADDR register - indirect addressing of these regs */
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#define PB0CR 0x00 /* periph bank 0 config reg */
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#define PB1CR 0x01 /* periph bank 1 config reg */
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#define PB2CR 0x02 /* periph bank 2 config reg */
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#define PB3CR 0x03 /* periph bank 3 config reg */
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#define PB4CR 0x04 /* periph bank 4 config reg */
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#ifndef CONFIG_405EP
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#define PB5CR 0x05 /* periph bank 5 config reg */
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#define PB6CR 0x06 /* periph bank 6 config reg */
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#define PB7CR 0x07 /* periph bank 7 config reg */
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#endif
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#define PB0AP 0x10 /* periph bank 0 access parameters */
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#define PB1AP 0x11 /* periph bank 1 access parameters */
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#define PB2AP 0x12 /* periph bank 2 access parameters */
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#define PB3AP 0x13 /* periph bank 3 access parameters */
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#define PB4AP 0x14 /* periph bank 4 access parameters */
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#ifndef CONFIG_405EP
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#define PB5AP 0x15 /* periph bank 5 access parameters */
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#define PB6AP 0x16 /* periph bank 6 access parameters */
|
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#define PB7AP 0x17 /* periph bank 7 access parameters */
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#endif
|
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#define PBEAR 0x20 /* periph bus error addr reg */
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#define PBESR0 0x21 /* periph bus error status reg 0 */
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#define PBESR1 0x22 /* periph bus error status reg 1 */
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||||
#define EBC0_CFG 0x23 /* external bus configuration reg */
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|
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#ifdef CONFIG_405EP
|
||||
/******************************************************************************
|
||||
* Control
|
||||
******************************************************************************/
|
||||
#define CNTRL_DCR_BASE 0x0f0
|
||||
#define CPC0_PLLMR0 (CNTRL_DCR_BASE+0x0) /* PLL mode register 0 */
|
||||
#define CPC0_BOOT (CNTRL_DCR_BASE+0x1) /* Clock status register */
|
||||
#define CPC0_EPCTL (CNTRL_DCR_BASE+0x3) /* EMAC to PHY control register */
|
||||
#define CPC0_PLLMR1 (CNTRL_DCR_BASE+0x4) /* PLL mode register 1 */
|
||||
#define CPC0_UCR (CNTRL_DCR_BASE+0x5) /* UART control register */
|
||||
#define CPC0_PCI (CNTRL_DCR_BASE+0x9) /* PCI control register */
|
||||
|
||||
#define CPC0_PLLMR0 (CNTRL_DCR_BASE+0x0) /* PLL mode 0 register */
|
||||
#define CPC0_BOOT (CNTRL_DCR_BASE+0x1) /* Chip Clock Status register */
|
||||
#define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* Chip Control 1 register */
|
||||
#define CPC0_EPRCSR (CNTRL_DCR_BASE+0x3) /* EMAC PHY Rcv Clk Src register */
|
||||
#define CPC0_PLLMR1 (CNTRL_DCR_BASE+0x4) /* PLL mode 1 register */
|
||||
#define CPC0_UCR (CNTRL_DCR_BASE+0x5) /* UART Control register */
|
||||
#define CPC0_SRR (CNTRL_DCR_BASE+0x6) /* Soft Reset register */
|
||||
#define CPC0_JTAGID (CNTRL_DCR_BASE+0x7) /* JTAG ID register */
|
||||
#define CPC0_SPARE (CNTRL_DCR_BASE+0x8) /* Spare DCR */
|
||||
#define CPC0_PCI (CNTRL_DCR_BASE+0x9) /* PCI Control register */
|
||||
|
||||
/* Bit definitions */
|
||||
#define PLLMR0_CPU_DIV_MASK 0x00300000 /* CPU clock divider */
|
||||
#define PLLMR0_CPU_DIV_BYPASS 0x00000000
|
||||
#define PLLMR0_CPU_DIV_2 0x00100000
|
||||
#define PLLMR0_CPU_DIV_3 0x00200000
|
||||
#define PLLMR0_CPU_DIV_4 0x00300000
|
||||
|
||||
#define PLLMR0_CPU_TO_PLB_MASK 0x00030000 /* CPU:PLB Frequency Divisor */
|
||||
#define PLLMR0_CPU_PLB_DIV_1 0x00000000
|
||||
#define PLLMR0_CPU_PLB_DIV_2 0x00010000
|
||||
#define PLLMR0_CPU_PLB_DIV_3 0x00020000
|
||||
#define PLLMR0_CPU_PLB_DIV_4 0x00030000
|
||||
|
||||
#define PLLMR0_OPB_TO_PLB_MASK 0x00003000 /* OPB:PLB Frequency Divisor */
|
||||
#define PLLMR0_OPB_PLB_DIV_1 0x00000000
|
||||
#define PLLMR0_OPB_PLB_DIV_2 0x00001000
|
||||
#define PLLMR0_OPB_PLB_DIV_3 0x00002000
|
||||
#define PLLMR0_OPB_PLB_DIV_4 0x00003000
|
||||
|
||||
#define PLLMR0_EXB_TO_PLB_MASK 0x00000300 /* External Bus:PLB Divisor */
|
||||
#define PLLMR0_EXB_PLB_DIV_2 0x00000000
|
||||
#define PLLMR0_EXB_PLB_DIV_3 0x00000100
|
||||
#define PLLMR0_EXB_PLB_DIV_4 0x00000200
|
||||
#define PLLMR0_EXB_PLB_DIV_5 0x00000300
|
||||
|
||||
#define PLLMR0_MAL_TO_PLB_MASK 0x00000030 /* MAL:PLB Divisor */
|
||||
#define PLLMR0_MAL_PLB_DIV_1 0x00000000
|
||||
#define PLLMR0_MAL_PLB_DIV_2 0x00000010
|
||||
#define PLLMR0_MAL_PLB_DIV_3 0x00000020
|
||||
#define PLLMR0_MAL_PLB_DIV_4 0x00000030
|
||||
|
||||
#define PLLMR0_PCI_TO_PLB_MASK 0x00000003 /* PCI:PLB Frequency Divisor */
|
||||
#define PLLMR0_PCI_PLB_DIV_1 0x00000000
|
||||
#define PLLMR0_PCI_PLB_DIV_2 0x00000001
|
||||
#define PLLMR0_PCI_PLB_DIV_3 0x00000002
|
||||
#define PLLMR0_PCI_PLB_DIV_4 0x00000003
|
||||
|
||||
#define PLLMR1_SSCS_MASK 0x80000000 /* Select system clock source */
|
||||
#define PLLMR1_PLLR_MASK 0x40000000 /* PLL reset */
|
||||
#define PLLMR1_FBMUL_MASK 0x00F00000 /* PLL feedback multiplier value */
|
||||
#define PLLMR1_FBMUL_DIV_16 0x00000000
|
||||
#define PLLMR1_FBMUL_DIV_1 0x00100000
|
||||
#define PLLMR1_FBMUL_DIV_2 0x00200000
|
||||
#define PLLMR1_FBMUL_DIV_3 0x00300000
|
||||
#define PLLMR1_FBMUL_DIV_4 0x00400000
|
||||
#define PLLMR1_FBMUL_DIV_5 0x00500000
|
||||
#define PLLMR1_FBMUL_DIV_6 0x00600000
|
||||
#define PLLMR1_FBMUL_DIV_7 0x00700000
|
||||
#define PLLMR1_FBMUL_DIV_8 0x00800000
|
||||
#define PLLMR1_FBMUL_DIV_9 0x00900000
|
||||
#define PLLMR1_FBMUL_DIV_10 0x00A00000
|
||||
#define PLLMR1_FBMUL_DIV_11 0x00B00000
|
||||
#define PLLMR1_FBMUL_DIV_12 0x00C00000
|
||||
#define PLLMR1_FBMUL_DIV_13 0x00D00000
|
||||
#define PLLMR1_FBMUL_DIV_14 0x00E00000
|
||||
#define PLLMR1_FBMUL_DIV_15 0x00F00000
|
||||
|
||||
#define PLLMR1_FWDVA_MASK 0x00070000 /* PLL forward divider A value */
|
||||
#define PLLMR1_FWDVA_DIV_8 0x00000000
|
||||
#define PLLMR1_FWDVA_DIV_7 0x00010000
|
||||
#define PLLMR1_FWDVA_DIV_6 0x00020000
|
||||
#define PLLMR1_FWDVA_DIV_5 0x00030000
|
||||
#define PLLMR1_FWDVA_DIV_4 0x00040000
|
||||
#define PLLMR1_FWDVA_DIV_3 0x00050000
|
||||
#define PLLMR1_FWDVA_DIV_2 0x00060000
|
||||
#define PLLMR1_FWDVA_DIV_1 0x00070000
|
||||
#define PLLMR1_FWDVB_MASK 0x00007000 /* PLL forward divider B value */
|
||||
#define PLLMR1_TUNING_MASK 0x000003FF /* PLL tune bits */
|
||||
|
||||
/* Defines for CPC0_EPRCSR register */
|
||||
#define CPC0_EPRCSR_E0NFE 0x80000000
|
||||
#define CPC0_EPRCSR_E1NFE 0x40000000
|
||||
#define CPC0_EPRCSR_E1RPP 0x00000080
|
||||
#define CPC0_EPRCSR_E0RPP 0x00000040
|
||||
#define CPC0_EPRCSR_E1ERP 0x00000020
|
||||
#define CPC0_EPRCSR_E0ERP 0x00000010
|
||||
#define CPC0_EPRCSR_E1PCI 0x00000002
|
||||
#define CPC0_EPRCSR_E0PCI 0x00000001
|
||||
|
||||
/* Defines for CPC0_PCI Register */
|
||||
#define CPC0_PCI_SPE 0x00000010 /* PCIINT/WE select */
|
||||
#define CPC0_PCI_HOST_CFG_EN 0x00000008 /* PCI host config Enable */
|
||||
#define CPC0_PCI_ARBIT_EN 0x00000001 /* PCI Internal Arb Enabled */
|
||||
|
||||
/* Defines for CPC0_BOOR Register */
|
||||
#define CPC0_BOOT_SEP 0x00000002 /* serial EEPROM present */
|
||||
|
||||
/* Defines for CPC0_PLLMR1 Register fields */
|
||||
#define PLL_ACTIVE 0x80000000
|
||||
#define CPC0_PLLMR1_SSCS 0x80000000
|
||||
#define PLL_RESET 0x40000000
|
||||
#define CPC0_PLLMR1_PLLR 0x40000000
|
||||
/* Feedback multiplier */
|
||||
#define PLL_FBKDIV 0x00F00000
|
||||
#define CPC0_PLLMR1_FBDV 0x00F00000
|
||||
#define PLL_FBKDIV_16 0x00000000
|
||||
#define PLL_FBKDIV_1 0x00100000
|
||||
#define PLL_FBKDIV_2 0x00200000
|
||||
#define PLL_FBKDIV_3 0x00300000
|
||||
#define PLL_FBKDIV_4 0x00400000
|
||||
#define PLL_FBKDIV_5 0x00500000
|
||||
#define PLL_FBKDIV_6 0x00600000
|
||||
#define PLL_FBKDIV_7 0x00700000
|
||||
#define PLL_FBKDIV_8 0x00800000
|
||||
#define PLL_FBKDIV_9 0x00900000
|
||||
#define PLL_FBKDIV_10 0x00A00000
|
||||
#define PLL_FBKDIV_11 0x00B00000
|
||||
#define PLL_FBKDIV_12 0x00C00000
|
||||
#define PLL_FBKDIV_13 0x00D00000
|
||||
#define PLL_FBKDIV_14 0x00E00000
|
||||
#define PLL_FBKDIV_15 0x00F00000
|
||||
/* Forward A divisor */
|
||||
#define PLL_FWDDIVA 0x00070000
|
||||
#define CPC0_PLLMR1_FWDVA 0x00070000
|
||||
#define PLL_FWDDIVA_8 0x00000000
|
||||
#define PLL_FWDDIVA_7 0x00010000
|
||||
#define PLL_FWDDIVA_6 0x00020000
|
||||
#define PLL_FWDDIVA_5 0x00030000
|
||||
#define PLL_FWDDIVA_4 0x00040000
|
||||
#define PLL_FWDDIVA_3 0x00050000
|
||||
#define PLL_FWDDIVA_2 0x00060000
|
||||
#define PLL_FWDDIVA_1 0x00070000
|
||||
/* Forward B divisor */
|
||||
#define PLL_FWDDIVB 0x00007000
|
||||
#define CPC0_PLLMR1_FWDVB 0x00007000
|
||||
#define PLL_FWDDIVB_8 0x00000000
|
||||
#define PLL_FWDDIVB_7 0x00001000
|
||||
#define PLL_FWDDIVB_6 0x00002000
|
||||
#define PLL_FWDDIVB_5 0x00003000
|
||||
#define PLL_FWDDIVB_4 0x00004000
|
||||
#define PLL_FWDDIVB_3 0x00005000
|
||||
#define PLL_FWDDIVB_2 0x00006000
|
||||
#define PLL_FWDDIVB_1 0x00007000
|
||||
/* PLL tune bits */
|
||||
#define PLL_TUNE_MASK 0x000003FF
|
||||
#define PLL_TUNE_2_M_3 0x00000133 /* 2 <= M <= 3 */
|
||||
#define PLL_TUNE_4_M_6 0x00000134 /* 3 < M <= 6 */
|
||||
#define PLL_TUNE_7_M_10 0x00000138 /* 6 < M <= 10 */
|
||||
#define PLL_TUNE_11_M_14 0x0000013C /* 10 < M <= 14 */
|
||||
#define PLL_TUNE_15_M_40 0x0000023E /* 14 < M <= 40 */
|
||||
#define PLL_TUNE_VCO_LOW 0x00000000 /* 500MHz <= VCO <= 800MHz */
|
||||
#define PLL_TUNE_VCO_HI 0x00000080 /* 800MHz < VCO <= 1000MHz */
|
||||
|
||||
/* Defines for CPC0_PLLMR0 Register fields */
|
||||
/* CPU divisor */
|
||||
#define PLL_CPUDIV 0x00300000
|
||||
#define CPC0_PLLMR0_CCDV 0x00300000
|
||||
#define PLL_CPUDIV_1 0x00000000
|
||||
#define PLL_CPUDIV_2 0x00100000
|
||||
#define PLL_CPUDIV_3 0x00200000
|
||||
#define PLL_CPUDIV_4 0x00300000
|
||||
/* PLB divisor */
|
||||
#define PLL_PLBDIV 0x00030000
|
||||
#define CPC0_PLLMR0_CBDV 0x00030000
|
||||
#define PLL_PLBDIV_1 0x00000000
|
||||
#define PLL_PLBDIV_2 0x00010000
|
||||
#define PLL_PLBDIV_3 0x00020000
|
||||
#define PLL_PLBDIV_4 0x00030000
|
||||
/* OPB divisor */
|
||||
#define PLL_OPBDIV 0x00003000
|
||||
#define CPC0_PLLMR0_OPDV 0x00003000
|
||||
#define PLL_OPBDIV_1 0x00000000
|
||||
#define PLL_OPBDIV_2 0x00001000
|
||||
#define PLL_OPBDIV_3 0x00002000
|
||||
#define PLL_OPBDIV_4 0x00003000
|
||||
/* EBC divisor */
|
||||
#define PLL_EXTBUSDIV 0x00000300
|
||||
#define CPC0_PLLMR0_EPDV 0x00000300
|
||||
#define PLL_EXTBUSDIV_2 0x00000000
|
||||
#define PLL_EXTBUSDIV_3 0x00000100
|
||||
#define PLL_EXTBUSDIV_4 0x00000200
|
||||
#define PLL_EXTBUSDIV_5 0x00000300
|
||||
/* MAL divisor */
|
||||
#define PLL_MALDIV 0x00000030
|
||||
#define CPC0_PLLMR0_MPDV 0x00000030
|
||||
#define PLL_MALDIV_1 0x00000000
|
||||
#define PLL_MALDIV_2 0x00000010
|
||||
#define PLL_MALDIV_3 0x00000020
|
||||
#define PLL_MALDIV_4 0x00000030
|
||||
/* PCI divisor */
|
||||
#define PLL_PCIDIV 0x00000003
|
||||
#define CPC0_PLLMR0_PPFD 0x00000003
|
||||
#define PLL_PCIDIV_1 0x00000000
|
||||
#define PLL_PCIDIV_2 0x00000001
|
||||
#define PLL_PCIDIV_3 0x00000002
|
||||
#define PLL_PCIDIV_4 0x00000003
|
||||
|
||||
/*
|
||||
*------------------------------------------------------------------------------
|
||||
* PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI,
|
||||
* assuming a 33.3MHz input clock to the 405EP.
|
||||
*------------------------------------------------------------------------------
|
||||
*/
|
||||
#define PLLMR0_266_133_66 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
|
||||
PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
|
||||
PLL_MALDIV_1 | PLL_PCIDIV_4)
|
||||
#define PLLMR1_266_133_66 (PLL_FBKDIV_8 | \
|
||||
PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
|
||||
PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
|
||||
|
||||
#define PLLMR0_133_66_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \
|
||||
PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
|
||||
PLL_MALDIV_1 | PLL_PCIDIV_4)
|
||||
#define PLLMR1_133_66_66_33 (PLL_FBKDIV_4 | \
|
||||
PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \
|
||||
PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
|
||||
#define PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
|
||||
PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
|
||||
PLL_MALDIV_1 | PLL_PCIDIV_4)
|
||||
#define PLLMR1_200_100_50_33 (PLL_FBKDIV_6 | \
|
||||
PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \
|
||||
PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
|
||||
#define PLLMR0_266_133_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
|
||||
PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
|
||||
PLL_MALDIV_1 | PLL_PCIDIV_4)
|
||||
#define PLLMR1_266_133_66_33 (PLL_FBKDIV_8 | \
|
||||
PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
|
||||
PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
|
||||
#define PLLMR0_266_66_33_33 (PLL_CPUDIV_1 | PLL_PLBDIV_4 | \
|
||||
PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
|
||||
PLL_MALDIV_1 | PLL_PCIDIV_2)
|
||||
#define PLLMR1_266_66_33_33 (PLL_FBKDIV_8 | \
|
||||
PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
|
||||
PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
|
||||
#define PLLMR0_333_111_55_37 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
|
||||
PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
|
||||
PLL_MALDIV_1 | PLL_PCIDIV_3)
|
||||
#define PLLMR1_333_111_55_37 (PLL_FBKDIV_10 | \
|
||||
PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
|
||||
PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
|
||||
#define PLLMR0_333_111_55_111 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
|
||||
PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
|
||||
PLL_MALDIV_1 | PLL_PCIDIV_1)
|
||||
#define PLLMR1_333_111_55_111 (PLL_FBKDIV_10 | \
|
||||
PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
|
||||
PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
|
||||
|
||||
/*
|
||||
* PLL Voltage Controlled Oscillator (VCO) definitions
|
||||
* Maximum and minimum values (in MHz) for correct PLL operation.
|
||||
*/
|
||||
#define VCO_MIN 500
|
||||
#define VCO_MAX 1000
|
||||
#elif defined(CONFIG_405EZ)
|
||||
#define SDR0_NAND0 0x4000
|
||||
#define SDR0_ULTRA0 0x4040
|
||||
#define SDR0_ULTRA1 0x4050
|
||||
#define SDR0_ICINTSTAT 0x4510
|
||||
|
||||
#define SDR_NAND0_NDEN 0x80000000
|
||||
#define SDR_NAND0_NDBTEN 0x40000000
|
||||
#define SDR_NAND0_NDBADR_MASK 0x30000000
|
||||
#define SDR_NAND0_NDBPG_MASK 0x0f000000
|
||||
#define SDR_NAND0_NDAREN 0x00800000
|
||||
#define SDR_NAND0_NDRBEN 0x00400000
|
||||
|
||||
#define SDR_ULTRA0_NDGPIOBP 0x80000000
|
||||
#define SDR_ULTRA0_CSN_MASK 0x78000000
|
||||
#define SDR_ULTRA0_CSNSEL0 0x40000000
|
||||
#define SDR_ULTRA0_CSNSEL1 0x20000000
|
||||
#define SDR_ULTRA0_CSNSEL2 0x10000000
|
||||
#define SDR_ULTRA0_CSNSEL3 0x08000000
|
||||
#define SDR_ULTRA0_EBCRDYEN 0x04000000
|
||||
#define SDR_ULTRA0_SPISSINEN 0x02000000
|
||||
#define SDR_ULTRA0_NFSRSTEN 0x01000000
|
||||
|
||||
#define SDR_ULTRA1_LEDNENABLE 0x40000000
|
||||
|
||||
#define SDR_ICRX_STAT 0x80000000
|
||||
#define SDR_ICTX0_STAT 0x40000000
|
||||
#define SDR_ICTX1_STAT 0x20000000
|
||||
|
||||
#define SDR0_PINSTP 0x40
|
||||
|
||||
/******************************************************************************
|
||||
* Control
|
||||
******************************************************************************/
|
||||
/* CPR Registers */
|
||||
#define CPR0_CLKUP 0x020 /* CPR_CLKUPD */
|
||||
#define CPR0_PLLC 0x040 /* CPR_PLLC */
|
||||
#define CPR0_PLLD 0x060 /* CPR_PLLD */
|
||||
#define CPC0_PRIMAD 0x080 /* CPR_PRIMAD */
|
||||
#define CPC0_PERD0 0x0e0 /* CPR_PERD0 */
|
||||
#define CPC0_PERD1 0x0e1 /* CPR_PERD1 */
|
||||
#define CPC0_PERC0 0x180 /* CPR_PERC0 */
|
||||
|
||||
#define CPR_CLKUPD_ENPLLCH_EN 0x40000000 /* Enable CPR PLL Changes */
|
||||
#define CPR_CLKUPD_ENDVCH_EN 0x20000000 /* Enable CPR Sys. Div. Changes */
|
||||
#define CPR_PERD0_SPIDV_MASK 0x000F0000 /* SPI Clock Divider */
|
||||
|
||||
#define PLLC_SRC_MASK 0x20000000 /* PLL feedback source */
|
||||
|
||||
#define PLLD_FBDV_MASK 0x1F000000 /* PLL feedback divider value */
|
||||
#define PLLD_FWDVA_MASK 0x000F0000 /* PLL forward divider A value */
|
||||
#define PLLD_FWDVB_MASK 0x00000700 /* PLL forward divider B value */
|
||||
|
||||
#define PRIMAD_CPUDV_MASK 0x0F000000 /* CPU Clock Divisor Mask */
|
||||
#define PRIMAD_PLBDV_MASK 0x000F0000 /* PLB Clock Divisor Mask */
|
||||
#define PRIMAD_OPBDV_MASK 0x00000F00 /* OPB Clock Divisor Mask */
|
||||
#define PRIMAD_EBCDV_MASK 0x0000000F /* EBC Clock Divisor Mask */
|
||||
|
||||
#define PERD0_PWMDV_MASK 0xFF000000 /* PWM Divider Mask */
|
||||
#define PERD0_SPIDV_MASK 0x000F0000 /* SPI Divider Mask */
|
||||
#define PERD0_U0DV_MASK 0x0000FF00 /* UART 0 Divider Mask */
|
||||
#define PERD0_U1DV_MASK 0x000000FF /* UART 1 Divider Mask */
|
||||
|
||||
#else /* #ifdef CONFIG_405EP */
|
||||
/******************************************************************************
|
||||
* Control
|
||||
******************************************************************************/
|
||||
#define CNTRL_DCR_BASE 0x0b0
|
||||
#define CPC0_PLLMR (CNTRL_DCR_BASE + 0x0) /* PLL mode register */
|
||||
#define CPC0_CR0 (CNTRL_DCR_BASE + 0x1) /* chip control register 0 */
|
||||
#define CPC0_CR1 (CNTRL_DCR_BASE + 0x2) /* chip control register 1 */
|
||||
#define CPC0_PSR (CNTRL_DCR_BASE + 0x4) /* chip pin strapping reg */
|
||||
|
||||
/* CPC0_ECR/CPC0_EIRR: PPC405GPr only */
|
||||
#define CPC0_EIRR (CNTRL_DCR_BASE + 0x6) /* ext interrupt routing reg */
|
||||
#define CPC0_ECR 0xaa /* edge conditioner register */
|
||||
|
||||
/* Bit definitions */
|
||||
#define PLLMR_FWD_DIV_MASK 0xE0000000 /* Forward Divisor */
|
||||
#define PLLMR_FWD_DIV_BYPASS 0xE0000000
|
||||
#define PLLMR_FWD_DIV_3 0xA0000000
|
||||
#define PLLMR_FWD_DIV_4 0x80000000
|
||||
#define PLLMR_FWD_DIV_6 0x40000000
|
||||
|
||||
#define PLLMR_FB_DIV_MASK 0x1E000000 /* Feedback Divisor */
|
||||
#define PLLMR_FB_DIV_1 0x02000000
|
||||
#define PLLMR_FB_DIV_2 0x04000000
|
||||
#define PLLMR_FB_DIV_3 0x06000000
|
||||
#define PLLMR_FB_DIV_4 0x08000000
|
||||
|
||||
#define PLLMR_TUNING_MASK 0x01F80000
|
||||
|
||||
#define PLLMR_CPU_TO_PLB_MASK 0x00060000 /* CPU:PLB Frequency Divisor */
|
||||
#define PLLMR_CPU_PLB_DIV_1 0x00000000
|
||||
#define PLLMR_CPU_PLB_DIV_2 0x00020000
|
||||
#define PLLMR_CPU_PLB_DIV_3 0x00040000
|
||||
#define PLLMR_CPU_PLB_DIV_4 0x00060000
|
||||
|
||||
#define PLLMR_OPB_TO_PLB_MASK 0x00018000 /* OPB:PLB Frequency Divisor */
|
||||
#define PLLMR_OPB_PLB_DIV_1 0x00000000
|
||||
#define PLLMR_OPB_PLB_DIV_2 0x00008000
|
||||
#define PLLMR_OPB_PLB_DIV_3 0x00010000
|
||||
#define PLLMR_OPB_PLB_DIV_4 0x00018000
|
||||
|
||||
#define PLLMR_PCI_TO_PLB_MASK 0x00006000 /* PCI:PLB Frequency Divisor */
|
||||
#define PLLMR_PCI_PLB_DIV_1 0x00000000
|
||||
#define PLLMR_PCI_PLB_DIV_2 0x00002000
|
||||
#define PLLMR_PCI_PLB_DIV_3 0x00004000
|
||||
#define PLLMR_PCI_PLB_DIV_4 0x00006000
|
||||
|
||||
#define PLLMR_EXB_TO_PLB_MASK 0x00001800 /* External Bus:PLB Divisor */
|
||||
#define PLLMR_EXB_PLB_DIV_2 0x00000000
|
||||
#define PLLMR_EXB_PLB_DIV_3 0x00000800
|
||||
#define PLLMR_EXB_PLB_DIV_4 0x00001000
|
||||
#define PLLMR_EXB_PLB_DIV_5 0x00001800
|
||||
|
||||
/* definitions for PPC405GPr (new mode strapping) */
|
||||
#define PLLMR_FWDB_DIV_MASK 0x00000007 /* Forward Divisor B */
|
||||
|
||||
#define PSR_PLL_FWD_MASK 0xC0000000
|
||||
#define PSR_PLL_FDBACK_MASK 0x30000000
|
||||
#define PSR_PLL_TUNING_MASK 0x0E000000
|
||||
#define PSR_PLB_CPU_MASK 0x01800000
|
||||
#define PSR_OPB_PLB_MASK 0x00600000
|
||||
#define PSR_PCI_PLB_MASK 0x00180000
|
||||
#define PSR_EB_PLB_MASK 0x00060000
|
||||
#define PSR_ROM_WIDTH_MASK 0x00018000
|
||||
#define PSR_ROM_LOC 0x00004000
|
||||
#define PSR_PCI_ASYNC_EN 0x00001000
|
||||
#define PSR_PERCLK_SYNC_MODE_EN 0x00000800 /* PPC405GPr only */
|
||||
#define PSR_PCI_ARBIT_EN 0x00000400
|
||||
#define PSR_NEW_MODE_EN 0x00000020 /* PPC405GPr only */
|
||||
|
||||
#ifndef CONFIG_IOP480
|
||||
/*
|
||||
* PLL Voltage Controlled Oscillator (VCO) definitions
|
||||
* Maximum and minimum values (in MHz) for correct PLL operation.
|
||||
*/
|
||||
#define VCO_MIN 400
|
||||
#define VCO_MAX 800
|
||||
#endif /* #ifndef CONFIG_IOP480 */
|
||||
#endif /* #ifdef CONFIG_405EP */
|
||||
|
||||
/******************************************************************************
|
||||
* Memory Access Layer
|
||||
******************************************************************************/
|
||||
#if defined(CONFIG_405EZ)
|
||||
#define MAL_DCR_BASE 0x380
|
||||
#else
|
||||
#define MAL_DCR_BASE 0x180
|
||||
#endif
|
||||
#define MAL0_CFG (MAL_DCR_BASE + 0x00) /* MAL Config reg */
|
||||
#define MAL0_ESR (MAL_DCR_BASE + 0x01) /* Err Status (Read/Clear) */
|
||||
#define MAL0_IER (MAL_DCR_BASE + 0x02) /* Interrupt enable */
|
||||
#define MAL0_TXCASR (MAL_DCR_BASE + 0x04) /* TX Channel active (set) */
|
||||
#define MAL0_TXCARR (MAL_DCR_BASE + 0x05) /* TX Channel active (reset) */
|
||||
#define MAL0_TXEOBISR (MAL_DCR_BASE + 0x06) /* TX End of buffer int status */
|
||||
#define MAL0_TXDEIR (MAL_DCR_BASE + 0x07) /* TX Descr. Error Int reg */
|
||||
#define MAL0_RXCASR (MAL_DCR_BASE + 0x10) /* RX Channel active (set) */
|
||||
#define MAL0_RXCARR (MAL_DCR_BASE + 0x11) /* RX Channel active (reset) */
|
||||
#define MAL0_RXEOBISR (MAL_DCR_BASE + 0x12) /* RX End of buffer int status */
|
||||
#define MAL0_RXDEIR (MAL_DCR_BASE + 0x13) /* RX Descr. Error Int reg */
|
||||
#define MAL0_TXCTP0R (MAL_DCR_BASE + 0x20) /* TX 0 Channel table ptr */
|
||||
#define MAL0_TXCTP1R (MAL_DCR_BASE + 0x21) /* TX 1 Channel table ptr */
|
||||
#define MAL0_TXCTP2R (MAL_DCR_BASE + 0x22) /* TX 2 Channel table ptr */
|
||||
#define MAL0_TXCTP3R (MAL_DCR_BASE + 0x23) /* TX 3 Channel table ptr */
|
||||
#define MAL0_RXCTP0R (MAL_DCR_BASE + 0x40) /* RX 0 Channel table ptr */
|
||||
#define MAL0_RXCTP1R (MAL_DCR_BASE + 0x41) /* RX 1 Channel table ptr */
|
||||
#define MAL0_RXCTP2R (MAL_DCR_BASE + 0x42) /* RX 2 Channel table ptr */
|
||||
#define MAL0_RXCTP3R (MAL_DCR_BASE + 0x43) /* RX 3 Channel table ptr */
|
||||
#define MAL0_RXCTP8R (MAL_DCR_BASE + 0x48) /* RX 8 Channel table ptr */
|
||||
#define MAL0_RXCTP16R (MAL_DCR_BASE + 0x50) /* RX 16 Channel table ptr */
|
||||
#define MAL0_RXCTP24R (MAL_DCR_BASE + 0x58) /* RX 24 Channel table ptr */
|
||||
#define MAL0_RCBS0 (MAL_DCR_BASE + 0x60) /* RX 0 Channel buffer size */
|
||||
#define MAL0_RCBS1 (MAL_DCR_BASE + 0x61) /* RX 1 Channel buffer size */
|
||||
#define MAL0_RCBS2 (MAL_DCR_BASE + 0x62) /* RX 2 Channel buffer size */
|
||||
#define MAL0_RCBS3 (MAL_DCR_BASE + 0x63) /* RX 3 Channel buffer size */
|
||||
#define MAL0_RCBS8 (MAL_DCR_BASE + 0x68) /* RX 8 Channel buffer size */
|
||||
#define MAL0_RCBS16 (MAL_DCR_BASE + 0x70) /* RX 16 Channel buffer size */
|
||||
#define MAL0_RCBS24 (MAL_DCR_BASE + 0x78) /* RX 24 Channel buffer size */
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
| UART Register Offsets
|
||||
'----------------------------------------------------------------------------*/
|
||||
#define DATA_REG 0x00
|
||||
#define DL_LSB 0x00
|
||||
#define DL_MSB 0x01
|
||||
#define INT_ENABLE 0x01
|
||||
#define FIFO_CONTROL 0x02
|
||||
#define LINE_CONTROL 0x03
|
||||
#define MODEM_CONTROL 0x04
|
||||
#define LINE_STATUS 0x05
|
||||
#define MODEM_STATUS 0x06
|
||||
#define SCRATCH 0x07
|
||||
|
||||
/******************************************************************************
|
||||
* On Chip Memory
|
||||
******************************************************************************/
|
||||
#if defined(CONFIG_405EZ)
|
||||
#define OCM_DCR_BASE 0x020
|
||||
#define OCM0_PLBCR1 (OCM_DCR_BASE + 0x00) /* OCM PLB3 Bank 1 Config */
|
||||
#define OCM0_PLBCR2 (OCM_DCR_BASE + 0x01) /* OCM PLB3 Bank 2 Config */
|
||||
#define OCM0_PLBBEAR (OCM_DCR_BASE + 0x02) /* OCM PLB3 Bus Error Add */
|
||||
#define OCM0_DSRC1 (OCM_DCR_BASE + 0x08) /* OCM D-side Bank 1 Config */
|
||||
#define OCM0_DSRC2 (OCM_DCR_BASE + 0x09) /* OCM D-side Bank 2 Config */
|
||||
#define OCM0_ISRC1 (OCM_DCR_BASE + 0x0A) /* OCM I-side Bank 1Config */
|
||||
#define OCM0_ISRC2 (OCM_DCR_BASE + 0x0B) /* OCM I-side Bank 2 Config */
|
||||
#define OCM0_DISDPC (OCM_DCR_BASE + 0x0C) /* OCM D-/I-side Data Par Chk */
|
||||
#else
|
||||
#define OCM_DCR_BASE 0x018
|
||||
#define OCM0_ISCNTL (OCM_DCR_BASE+0x01) /* OCM I-side control reg */
|
||||
#define OCM0_DSARC (OCM_DCR_BASE+0x02) /* OCM D-side address compare */
|
||||
#define OCM0_DSCNTL (OCM_DCR_BASE+0x03) /* OCM D-side control */
|
||||
#endif /* CONFIG_405EZ */
|
||||
|
||||
/******************************************************************************
|
||||
* GPIO macro register defines
|
||||
******************************************************************************/
|
||||
#if defined(CONFIG_405EZ)
|
||||
/* Only the 405EZ has 2 GPIOs */
|
||||
#define GPIO_BASE 0xEF600700
|
||||
#define GPIO0_OR (GPIO_BASE+0x0)
|
||||
#define GPIO0_TCR (GPIO_BASE+0x4)
|
||||
#define GPIO0_OSRL (GPIO_BASE+0x8)
|
||||
#define GPIO0_OSRH (GPIO_BASE+0xC)
|
||||
#define GPIO0_TSRL (GPIO_BASE+0x10)
|
||||
#define GPIO0_TSRH (GPIO_BASE+0x14)
|
||||
#define GPIO0_ODR (GPIO_BASE+0x18)
|
||||
#define GPIO0_IR (GPIO_BASE+0x1C)
|
||||
#define GPIO0_RR1 (GPIO_BASE+0x20)
|
||||
#define GPIO0_RR2 (GPIO_BASE+0x24)
|
||||
#define GPIO0_RR3 (GPIO_BASE+0x28)
|
||||
#define GPIO0_ISR1L (GPIO_BASE+0x30)
|
||||
#define GPIO0_ISR1H (GPIO_BASE+0x34)
|
||||
#define GPIO0_ISR2L (GPIO_BASE+0x38)
|
||||
#define GPIO0_ISR2H (GPIO_BASE+0x3C)
|
||||
#define GPIO0_ISR3L (GPIO_BASE+0x40)
|
||||
#define GPIO0_ISR3H (GPIO_BASE+0x44)
|
||||
|
||||
#define GPIO1_BASE 0xEF600800
|
||||
#define GPIO1_OR (GPIO1_BASE+0x0)
|
||||
#define GPIO1_TCR (GPIO1_BASE+0x4)
|
||||
#define GPIO1_OSRL (GPIO1_BASE+0x8)
|
||||
#define GPIO1_OSRH (GPIO1_BASE+0xC)
|
||||
#define GPIO1_TSRL (GPIO1_BASE+0x10)
|
||||
#define GPIO1_TSRH (GPIO1_BASE+0x14)
|
||||
#define GPIO1_ODR (GPIO1_BASE+0x18)
|
||||
#define GPIO1_IR (GPIO1_BASE+0x1C)
|
||||
#define GPIO1_RR1 (GPIO1_BASE+0x20)
|
||||
#define GPIO1_RR2 (GPIO1_BASE+0x24)
|
||||
#define GPIO1_RR3 (GPIO1_BASE+0x28)
|
||||
#define GPIO1_ISR1L (GPIO1_BASE+0x30)
|
||||
#define GPIO1_ISR1H (GPIO1_BASE+0x34)
|
||||
#define GPIO1_ISR2L (GPIO1_BASE+0x38)
|
||||
#define GPIO1_ISR2H (GPIO1_BASE+0x3C)
|
||||
#define GPIO1_ISR3L (GPIO1_BASE+0x40)
|
||||
#define GPIO1_ISR3H (GPIO1_BASE+0x44)
|
||||
|
||||
#elif defined(CONFIG_405EX)
|
||||
#define GPIO_BASE 0xEF600800
|
||||
#define GPIO0_OR (GPIO_BASE+0x0)
|
||||
#define GPIO0_TCR (GPIO_BASE+0x4)
|
||||
#define GPIO0_OSRL (GPIO_BASE+0x8)
|
||||
#define GPIO0_OSRH (GPIO_BASE+0xC)
|
||||
#define GPIO0_TSRL (GPIO_BASE+0x10)
|
||||
#define GPIO0_TSRH (GPIO_BASE+0x14)
|
||||
#define GPIO0_ODR (GPIO_BASE+0x18)
|
||||
#define GPIO0_IR (GPIO_BASE+0x1C)
|
||||
#define GPIO0_RR1 (GPIO_BASE+0x20)
|
||||
#define GPIO0_RR2 (GPIO_BASE+0x24)
|
||||
#define GPIO0_ISR1L (GPIO_BASE+0x30)
|
||||
#define GPIO0_ISR1H (GPIO_BASE+0x34)
|
||||
#define GPIO0_ISR2L (GPIO_BASE+0x38)
|
||||
#define GPIO0_ISR2H (GPIO_BASE+0x3C)
|
||||
#define GPIO0_ISR3L (GPIO_BASE+0x40)
|
||||
#define GPIO0_ISR3H (GPIO_BASE+0x44)
|
||||
|
||||
#else /* !405EZ */
|
||||
|
||||
#define GPIO_BASE 0xEF600700
|
||||
#define GPIO0_OR (GPIO_BASE+0x0)
|
||||
#define GPIO0_TCR (GPIO_BASE+0x4)
|
||||
#define GPIO0_OSRH (GPIO_BASE+0x8)
|
||||
#define GPIO0_OSRL (GPIO_BASE+0xC)
|
||||
#define GPIO0_TSRH (GPIO_BASE+0x10)
|
||||
#define GPIO0_TSRL (GPIO_BASE+0x14)
|
||||
#define GPIO0_ODR (GPIO_BASE+0x18)
|
||||
#define GPIO0_IR (GPIO_BASE+0x1C)
|
||||
#define GPIO0_RR1 (GPIO_BASE+0x20)
|
||||
#define GPIO0_RR2 (GPIO_BASE+0x24)
|
||||
#define GPIO0_ISR1H (GPIO_BASE+0x30)
|
||||
#define GPIO0_ISR1L (GPIO_BASE+0x34)
|
||||
#define GPIO0_ISR2H (GPIO_BASE+0x38)
|
||||
#define GPIO0_ISR2L (GPIO_BASE+0x3C)
|
||||
|
||||
#endif /* CONFIG_405EZ */
|
||||
|
||||
#define GPIO0_BASE GPIO_BASE
|
||||
|
||||
#if defined(CONFIG_405EX)
|
||||
#define SDR0_SRST 0x0200
|
||||
|
||||
/*
|
||||
* Software Reset Register
|
||||
*/
|
||||
#define SDR0_SRST_BGO PPC_REG_VAL(0, 1)
|
||||
#define SDR0_SRST_PLB4 PPC_REG_VAL(1, 1)
|
||||
#define SDR0_SRST_EBC PPC_REG_VAL(2, 1)
|
||||
#define SDR0_SRST_OPB PPC_REG_VAL(3, 1)
|
||||
#define SDR0_SRST_UART0 PPC_REG_VAL(4, 1)
|
||||
#define SDR0_SRST_UART1 PPC_REG_VAL(5, 1)
|
||||
#define SDR0_SRST_IIC0 PPC_REG_VAL(6, 1)
|
||||
#define SDR0_SRST_BGI PPC_REG_VAL(7, 1)
|
||||
#define SDR0_SRST_GPIO PPC_REG_VAL(8, 1)
|
||||
#define SDR0_SRST_GPT PPC_REG_VAL(9, 1)
|
||||
#define SDR0_SRST_DMC PPC_REG_VAL(10, 1)
|
||||
#define SDR0_SRST_RGMII PPC_REG_VAL(11, 1)
|
||||
#define SDR0_SRST_EMAC0 PPC_REG_VAL(12, 1)
|
||||
#define SDR0_SRST_EMAC1 PPC_REG_VAL(13, 1)
|
||||
#define SDR0_SRST_CPM PPC_REG_VAL(14, 1)
|
||||
#define SDR0_SRST_EPLL PPC_REG_VAL(15, 1)
|
||||
#define SDR0_SRST_UIC PPC_REG_VAL(16, 1)
|
||||
#define SDR0_SRST_UPRST PPC_REG_VAL(17, 1)
|
||||
#define SDR0_SRST_IIC1 PPC_REG_VAL(18, 1)
|
||||
#define SDR0_SRST_SCP PPC_REG_VAL(19, 1)
|
||||
#define SDR0_SRST_UHRST PPC_REG_VAL(20, 1)
|
||||
#define SDR0_SRST_DMA PPC_REG_VAL(21, 1)
|
||||
#define SDR0_SRST_DMAC PPC_REG_VAL(22, 1)
|
||||
#define SDR0_SRST_MAL PPC_REG_VAL(23, 1)
|
||||
#define SDR0_SRST_EBM PPC_REG_VAL(24, 1)
|
||||
#define SDR0_SRST_GPTR PPC_REG_VAL(25, 1)
|
||||
#define SDR0_SRST_PE0 PPC_REG_VAL(26, 1)
|
||||
#define SDR0_SRST_PE1 PPC_REG_VAL(27, 1)
|
||||
#define SDR0_SRST_CRYP PPC_REG_VAL(28, 1)
|
||||
#define SDR0_SRST_PKP PPC_REG_VAL(29, 1)
|
||||
#define SDR0_SRST_AHB PPC_REG_VAL(30, 1)
|
||||
#define SDR0_SRST_NDFC PPC_REG_VAL(31, 1)
|
||||
|
||||
#define SDR0_UART0 0x0120 /* UART0 Config */
|
||||
#define SDR0_UART1 0x0121 /* UART1 Config */
|
||||
#define SDR0_MFR 0x4300 /* SDR0_MFR reg */
|
||||
|
||||
/* Defines for CPC0_EPRCSR register */
|
||||
#define CPC0_EPRCSR_E0NFE 0x80000000
|
||||
#define CPC0_EPRCSR_E1NFE 0x40000000
|
||||
#define CPC0_EPRCSR_E1RPP 0x00000080
|
||||
#define CPC0_EPRCSR_E0RPP 0x00000040
|
||||
#define CPC0_EPRCSR_E1ERP 0x00000020
|
||||
#define CPC0_EPRCSR_E0ERP 0x00000010
|
||||
#define CPC0_EPRCSR_E1PCI 0x00000002
|
||||
#define CPC0_EPRCSR_E0PCI 0x00000001
|
||||
|
||||
#define CPR0_CLKUPD 0x020
|
||||
#define CPR0_PLLC 0x040
|
||||
#define CPR0_PLLD 0x060
|
||||
#define CPR0_CPUD 0x080
|
||||
#define CPR0_PLBD 0x0a0
|
||||
#define CPR0_OPBD0 0x0c0
|
||||
#define CPR0_PERD 0x0e0
|
||||
|
||||
#define SDR0_PINSTP 0x0040
|
||||
#define SDR0_SDCS0 0x0060
|
||||
|
||||
#define SDR0_SDCS_SDD (0x80000000 >> 31)
|
||||
|
||||
/* CUST0 Customer Configuration Register0 */
|
||||
#define SDR0_CUST0 0x4000
|
||||
#define SDR0_CUST0_MUX_E_N_G_MASK 0xC0000000 /* Mux_Emac_NDFC_GPIO */
|
||||
#define SDR0_CUST0_MUX_EMAC_SEL 0x40000000 /* Emac Selection */
|
||||
#define SDR0_CUST0_MUX_NDFC_SEL 0x80000000 /* NDFC Selection */
|
||||
#define SDR0_CUST0_MUX_GPIO_SEL 0xC0000000 /* GPIO Selection */
|
||||
|
||||
#define SDR0_CUST0_NDFC_EN_MASK 0x20000000 /* NDFC Enable Mask */
|
||||
#define SDR0_CUST0_NDFC_ENABLE 0x20000000 /* NDFC Enable */
|
||||
#define SDR0_CUST0_NDFC_DISABLE 0x00000000 /* NDFC Disable */
|
||||
|
||||
#define SDR0_CUST0_NDFC_BW_MASK 0x10000000 /* NDFC Boot Width */
|
||||
#define SDR0_CUST0_NDFC_BW_16_BIT 0x10000000 /* NDFC Boot Width= 16 Bit */
|
||||
#define SDR0_CUST0_NDFC_BW_8_BIT 0x00000000 /* NDFC Boot Width= 8 Bit */
|
||||
|
||||
#define SDR0_CUST0_NDFC_BP_MASK 0x0F000000 /* NDFC Boot Page */
|
||||
#define SDR0_CUST0_NDFC_BP_ENCODE(n) ((((unsigned long)(n))&0xF)<<24)
|
||||
#define SDR0_CUST0_NDFC_BP_DECODE(n) ((((unsigned long)(n))>>24)&0x0F)
|
||||
|
||||
#define SDR0_CUST0_NDFC_BAC_MASK 0x00C00000 /* NDFC Boot Address Cycle */
|
||||
#define SDR0_CUST0_NDFC_BAC_ENCODE(n) ((((unsigned long)(n))&0x3)<<22)
|
||||
#define SDR0_CUST0_NDFC_BAC_DECODE(n) ((((unsigned long)(n))>>22)&0x03)
|
||||
|
||||
#define SDR0_CUST0_NDFC_ARE_MASK 0x00200000 /* NDFC Auto Read Enable */
|
||||
#define SDR0_CUST0_NDFC_ARE_ENABLE 0x00200000 /* NDFC Auto Read Enable */
|
||||
#define SDR0_CUST0_NDFC_ARE_DISABLE 0x00000000 /* NDFC Auto Read Disable */
|
||||
|
||||
#define SDR0_CUST0_NRB_MASK 0x00100000 /* NDFC Ready / Busy */
|
||||
#define SDR0_CUST0_NRB_BUSY 0x00100000 /* Busy */
|
||||
#define SDR0_CUST0_NRB_READY 0x00000000 /* Ready */
|
||||
|
||||
#define SDR0_CUST0_NDRSC_MASK 0x0000FFF0 /* NDFC Device Reset Count Mask */
|
||||
#define SDR0_CUST0_NDRSC_ENCODE(n) ((((unsigned long)(n))&0xFFF)<<4)
|
||||
#define SDR0_CUST0_NDRSC_DECODE(n) ((((unsigned long)(n))>>4)&0xFFF)
|
||||
|
||||
#define SDR0_CUST0_CHIPSELGAT_MASK 0x0000000F /* Chip Sel Gating Mask */
|
||||
#define SDR0_CUST0_CHIPSELGAT_DIS 0x00000000 /* Chip Sel Gating Disable */
|
||||
#define SDR0_CUST0_CHIPSELGAT_ENALL 0x0000000F /* All Chip Sel Gating Enable */
|
||||
#define SDR0_CUST0_CHIPSELGAT_EN0 0x00000008 /* Chip Sel0 Gating Enable */
|
||||
#define SDR0_CUST0_CHIPSELGAT_EN1 0x00000004 /* Chip Sel1 Gating Enable */
|
||||
#define SDR0_CUST0_CHIPSELGAT_EN2 0x00000002 /* Chip Sel2 Gating Enable */
|
||||
#define SDR0_CUST0_CHIPSELGAT_EN3 0x00000001 /* Chip Sel3 Gating Enable */
|
||||
|
||||
#define SDR0_PFC0 0x4100
|
||||
#define SDR0_PFC1 0x4101
|
||||
#define SDR0_PFC1_U1ME 0x02000000
|
||||
#define SDR0_PFC1_U0ME 0x00080000
|
||||
#define SDR0_PFC1_U0IM 0x00040000
|
||||
#define SDR0_PFC1_SIS 0x00020000
|
||||
#define SDR0_PFC1_DMAAEN 0x00010000
|
||||
#define SDR0_PFC1_DMADEN 0x00008000
|
||||
#define SDR0_PFC1_USBEN 0x00004000
|
||||
#define SDR0_PFC1_AHBSWAP 0x00000020
|
||||
#define SDR0_PFC1_USBBIGEN 0x00000010
|
||||
#define SDR0_PFC1_GPT_FREQ 0x0000000f
|
||||
#endif
|
||||
|
||||
/* General Purpose Timer (GPT) Register Offsets */
|
||||
#define GPT0_TBC 0x00000000
|
||||
#define GPT0_IM 0x00000018
|
||||
#define GPT0_ISS 0x0000001C
|
||||
#define GPT0_ISC 0x00000020
|
||||
#define GPT0_IE 0x00000024
|
||||
#define GPT0_COMP0 0x00000080
|
||||
#define GPT0_COMP1 0x00000084
|
||||
#define GPT0_COMP2 0x00000088
|
||||
#define GPT0_COMP3 0x0000008C
|
||||
#define GPT0_COMP4 0x00000090
|
||||
#define GPT0_COMP5 0x00000094
|
||||
#define GPT0_COMP6 0x00000098
|
||||
#define GPT0_MASK0 0x000000C0
|
||||
#define GPT0_MASK1 0x000000C4
|
||||
#define GPT0_MASK2 0x000000C8
|
||||
#define GPT0_MASK3 0x000000CC
|
||||
#define GPT0_MASK4 0x000000D0
|
||||
#define GPT0_MASK5 0x000000D4
|
||||
#define GPT0_MASK6 0x000000D8
|
||||
#define GPT0_DCT0 0x00000110
|
||||
#define GPT0_DCIS 0x0000011C
|
||||
|
||||
#endif /* __PPC405_H__ */
|
||||
1958
include/ppc440.h
1958
include/ppc440.h
File diff suppressed because it is too large
Load Diff
225
include/ppc4xx.h
225
include/ppc4xx.h
@@ -1,225 +0,0 @@
|
||||
/*----------------------------------------------------------------------------+
|
||||
| This source code is dual-licensed. You may use it under the terms of
|
||||
| the GNU General Public License version 2, or under the license below.
|
||||
|
|
||||
| This source code has been made available to you by IBM on an AS-IS
|
||||
| basis. Anyone receiving this source is licensed under IBM
|
||||
| copyrights to use it in any way he or she deems fit, including
|
||||
| copying it, modifying it, compiling it, and redistributing it either
|
||||
| with or without modifications. No license under IBM patents or
|
||||
| patent applications is to be implied by the copyright license.
|
||||
|
|
||||
| Any user of this software should understand that IBM cannot provide
|
||||
| technical support for this software and will not be responsible for
|
||||
| any consequences resulting from the use of this software.
|
||||
|
|
||||
| Any person who transfers this source code or any derivative work
|
||||
| must include the IBM copyright notice, this paragraph, and the
|
||||
| preceding two paragraphs in the transferred software.
|
||||
|
|
||||
| COPYRIGHT I B M CORPORATION 1999
|
||||
| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
|
||||
+----------------------------------------------------------------------------*/
|
||||
|
||||
#ifndef __PPC4XX_H__
|
||||
#define __PPC4XX_H__
|
||||
|
||||
/*
|
||||
* Configure which SDRAM/DDR/DDR2 controller is equipped
|
||||
*/
|
||||
#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405EP) || \
|
||||
defined(CONFIG_AP1000) || defined(CONFIG_ML2)
|
||||
#define CONFIG_SDRAM_PPC4xx_IBM_SDRAM /* IBM SDRAM controller */
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_440GP) || defined(CONFIG_440GX) || \
|
||||
defined(CONFIG_440EP) || defined(CONFIG_440GR)
|
||||
#define CONFIG_SDRAM_PPC4xx_IBM_DDR /* IBM DDR controller */
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
|
||||
#define CONFIG_SDRAM_PPC4xx_DENALI_DDR2 /* Denali DDR(2) controller */
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_405EX) || \
|
||||
defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
|
||||
defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
|
||||
defined(CONFIG_460SX)
|
||||
#define CONFIG_SDRAM_PPC4xx_IBM_DDR2 /* IBM DDR(2) controller */
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
|
||||
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
|
||||
defined(CONFIG_405EZ) || defined(CONFIG_405EX) || \
|
||||
defined(CONFIG_460EX) || defined(CONFIG_460GT)
|
||||
#define CONFIG_NAND_NDFC
|
||||
#endif
|
||||
|
||||
/* PLB4 CrossBar Arbiter Core supported across PPC4xx families */
|
||||
#if defined(CONFIG_405EX) || \
|
||||
defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
|
||||
defined(CONFIG_440GR) || defined(CONFIG_440GRX) || \
|
||||
defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
|
||||
defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
|
||||
defined(CONFIG_460SX)
|
||||
|
||||
#define PLB_ARBITER_BASE 0x80
|
||||
|
||||
#define PLB0_ACR (PLB_ARBITER_BASE + 0x01)
|
||||
#define PLB0_ACR_PPM_MASK 0xF0000000
|
||||
#define PLB0_ACR_PPM_FIXED 0x00000000
|
||||
#define PLB0_ACR_PPM_FAIR 0xD0000000
|
||||
#define PLB0_ACR_HBU_MASK 0x08000000
|
||||
#define PLB0_ACR_HBU_DISABLED 0x00000000
|
||||
#define PLB0_ACR_HBU_ENABLED 0x08000000
|
||||
#define PLB0_ACR_RDP_MASK 0x06000000
|
||||
#define PLB0_ACR_RDP_DISABLED 0x00000000
|
||||
#define PLB0_ACR_RDP_2DEEP 0x02000000
|
||||
#define PLB0_ACR_RDP_3DEEP 0x04000000
|
||||
#define PLB0_ACR_RDP_4DEEP 0x06000000
|
||||
#define PLB0_ACR_WRP_MASK 0x01000000
|
||||
#define PLB0_ACR_WRP_DISABLED 0x00000000
|
||||
#define PLB0_ACR_WRP_2DEEP 0x01000000
|
||||
|
||||
#define PLB1_ACR (PLB_ARBITER_BASE + 0x09)
|
||||
#define PLB1_ACR_PPM_MASK 0xF0000000
|
||||
#define PLB1_ACR_PPM_FIXED 0x00000000
|
||||
#define PLB1_ACR_PPM_FAIR 0xD0000000
|
||||
#define PLB1_ACR_HBU_MASK 0x08000000
|
||||
#define PLB1_ACR_HBU_DISABLED 0x00000000
|
||||
#define PLB1_ACR_HBU_ENABLED 0x08000000
|
||||
#define PLB1_ACR_RDP_MASK 0x06000000
|
||||
#define PLB1_ACR_RDP_DISABLED 0x00000000
|
||||
#define PLB1_ACR_RDP_2DEEP 0x02000000
|
||||
#define PLB1_ACR_RDP_3DEEP 0x04000000
|
||||
#define PLB1_ACR_RDP_4DEEP 0x06000000
|
||||
#define PLB1_ACR_WRP_MASK 0x01000000
|
||||
#define PLB1_ACR_WRP_DISABLED 0x00000000
|
||||
#define PLB1_ACR_WRP_2DEEP 0x01000000
|
||||
|
||||
#endif /* 440EP/EPX 440GR/GRX 440SP/SPE 460EX/GT/SX 405EX*/
|
||||
|
||||
#if defined(CONFIG_440)
|
||||
#include <ppc440.h>
|
||||
#else
|
||||
#include <ppc405.h>
|
||||
#endif
|
||||
|
||||
#include <asm/ppc4xx-sdram.h>
|
||||
#include <asm/ppc4xx-ebc.h>
|
||||
#if !defined(CONFIG_XILINX_440)
|
||||
#include <asm/ppc4xx-uic.h>
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Macro for generating register field mnemonics
|
||||
*/
|
||||
#define PPC_REG_BITS 32
|
||||
#define PPC_REG_VAL(bit, value) ((value) << ((PPC_REG_BITS - 1) - (bit)))
|
||||
|
||||
/*
|
||||
* Elide casts when assembling register mnemonics
|
||||
*/
|
||||
#ifndef __ASSEMBLY__
|
||||
#define static_cast(type, val) (type)(val)
|
||||
#else
|
||||
#define static_cast(type, val) (val)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Common stuff for 4xx (405 and 440)
|
||||
*/
|
||||
|
||||
#define EXC_OFF_SYS_RESET 0x0100 /* System reset */
|
||||
#define _START_OFFSET (EXC_OFF_SYS_RESET + 0x2000)
|
||||
|
||||
#define RESET_VECTOR 0xfffffffc
|
||||
#define CACHELINE_MASK (CONFIG_SYS_CACHELINE_SIZE - 1) /* Address mask for
|
||||
cache line aligned data. */
|
||||
|
||||
#define CPR0_DCR_BASE 0x0C
|
||||
#define CPR0_CFGADDR (CPR0_DCR_BASE + 0x0)
|
||||
#define CPR0_CFGDATA (CPR0_DCR_BASE + 0x1)
|
||||
|
||||
#define SDR_DCR_BASE 0x0E
|
||||
#define SDR0_CFGADDR (SDR_DCR_BASE + 0x0)
|
||||
#define SDR0_CFGDATA (SDR_DCR_BASE + 0x1)
|
||||
|
||||
#define SDRAM_DCR_BASE 0x10
|
||||
#define SDRAM0_CFGADDR (SDRAM_DCR_BASE + 0x0)
|
||||
#define SDRAM0_CFGDATA (SDRAM_DCR_BASE + 0x1)
|
||||
|
||||
#define EBC_DCR_BASE 0x12
|
||||
#define EBC0_CFGADDR (EBC_DCR_BASE + 0x0)
|
||||
#define EBC0_CFGDATA (EBC_DCR_BASE + 0x1)
|
||||
|
||||
/*
|
||||
* Macros for indirect DCR access
|
||||
*/
|
||||
#define mtcpr(reg, d) \
|
||||
do { mtdcr(CPR0_CFGADDR, reg); mtdcr(CPR0_CFGDATA, d); } while (0)
|
||||
#define mfcpr(reg, d) \
|
||||
do { mtdcr(CPR0_CFGADDR, reg); d = mfdcr(CPR0_CFGDATA); } while (0)
|
||||
|
||||
#define mtebc(reg, d) \
|
||||
do { mtdcr(EBC0_CFGADDR, reg); mtdcr(EBC0_CFGDATA, d); } while (0)
|
||||
#define mfebc(reg, d) \
|
||||
do { mtdcr(EBC0_CFGADDR, reg); d = mfdcr(EBC0_CFGDATA); } while (0)
|
||||
|
||||
#define mtsdram(reg, d) \
|
||||
do { mtdcr(SDRAM0_CFGADDR, reg); mtdcr(SDRAM0_CFGDATA, d); } while (0)
|
||||
#define mfsdram(reg, d) \
|
||||
do { mtdcr(SDRAM0_CFGADDR, reg); d = mfdcr(SDRAM0_CFGDATA); } while (0)
|
||||
|
||||
#define mtsdr(reg, d) \
|
||||
do { mtdcr(SDR0_CFGADDR, reg); mtdcr(SDR0_CFGDATA, d); } while (0)
|
||||
#define mfsdr(reg, d) \
|
||||
do { mtdcr(SDR0_CFGADDR, reg); d = mfdcr(SDR0_CFGDATA); } while (0)
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
typedef struct
|
||||
{
|
||||
unsigned long freqDDR;
|
||||
unsigned long freqEBC;
|
||||
unsigned long freqOPB;
|
||||
unsigned long freqPCI;
|
||||
unsigned long freqPLB;
|
||||
unsigned long freqTmrClk;
|
||||
unsigned long freqUART;
|
||||
unsigned long freqProcessor;
|
||||
unsigned long freqVCOHz;
|
||||
unsigned long freqVCOMhz; /* in MHz */
|
||||
unsigned long pciClkSync; /* PCI clock is synchronous */
|
||||
unsigned long pciIntArbEn; /* Internal PCI arbiter is enabled */
|
||||
unsigned long pllExtBusDiv;
|
||||
unsigned long pllFbkDiv;
|
||||
unsigned long pllFwdDiv;
|
||||
unsigned long pllFwdDivA;
|
||||
unsigned long pllFwdDivB;
|
||||
unsigned long pllOpbDiv;
|
||||
unsigned long pllPciDiv;
|
||||
unsigned long pllPlbDiv;
|
||||
} PPC4xx_SYS_INFO;
|
||||
|
||||
static inline u32 get_mcsr(void)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
asm volatile("mfspr %0, 0x23c" : "=r" (val) :);
|
||||
return val;
|
||||
}
|
||||
|
||||
static inline void set_mcsr(u32 val)
|
||||
{
|
||||
asm volatile("mtspr 0x23c, %0" : "=r" (val) :);
|
||||
}
|
||||
|
||||
int ppc4xx_pci_sync_clock_config(u32 async);
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
/* for multi-cpu support */
|
||||
#define NA_OR_UNKNOWN_CPU -1
|
||||
|
||||
#endif /* __PPC4XX_H__ */
|
||||
@@ -1,562 +0,0 @@
|
||||
/*----------------------------------------------------------------------------+
|
||||
| This source code is dual-licensed. You may use it under the terms of the
|
||||
| GNU General Public License version 2, or under the license below.
|
||||
|
|
||||
| This source code has been made available to you by IBM on an AS-IS
|
||||
| basis. Anyone receiving this source is licensed under IBM
|
||||
| copyrights to use it in any way he or she deems fit, including
|
||||
| copying it, modifying it, compiling it, and redistributing it either
|
||||
| with or without modifications. No license under IBM patents or
|
||||
| patent applications is to be implied by the copyright license.
|
||||
|
|
||||
| Any user of this software should understand that IBM cannot provide
|
||||
| technical support for this software and will not be responsible for
|
||||
| any consequences resulting from the use of this software.
|
||||
|
|
||||
| Any person who transfers this source code or any derivative work
|
||||
| must include the IBM copyright notice, this paragraph, and the
|
||||
| preceding two paragraphs in the transferred software.
|
||||
|
|
||||
| COPYRIGHT I B M CORPORATION 1999
|
||||
| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
|
||||
+----------------------------------------------------------------------------*/
|
||||
/*----------------------------------------------------------------------------+
|
||||
|
|
||||
| File Name: enetemac.h
|
||||
|
|
||||
| Function: Header file for the EMAC3 macro on the 405GP.
|
||||
|
|
||||
| Author: Mark Wisner
|
||||
|
|
||||
| Change Activity-
|
||||
|
|
||||
| Date Description of Change BY
|
||||
| --------- --------------------- ---
|
||||
| 29-Apr-99 Created MKW
|
||||
|
|
||||
+----------------------------------------------------------------------------*/
|
||||
/*----------------------------------------------------------------------------+
|
||||
| 19-Nov-03 Travis Sawyer, Sandburst Corporation, tsawyer@sandburst.com
|
||||
| ported to handle 440GP and 440GX multiple EMACs
|
||||
+----------------------------------------------------------------------------*/
|
||||
|
||||
#ifndef _PPC4XX_ENET_H_
|
||||
#define _PPC4XX_ENET_H_
|
||||
|
||||
#include <net.h>
|
||||
#include "405_mal.h"
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------------+
|
||||
| General enternet defines. 802 frames are not supported.
|
||||
+-----------------------------------------------------------------------------*/
|
||||
#define ENET_ADDR_LENGTH 6
|
||||
#define ENET_ARPTYPE 0x806
|
||||
#define ARP_REQUEST 1
|
||||
#define ARP_REPLY 2
|
||||
#define ENET_IPTYPE 0x800
|
||||
#define ARP_CACHE_SIZE 5
|
||||
|
||||
#define NUM_TX_BUFF 1
|
||||
#define NUM_RX_BUFF PKTBUFSRX
|
||||
|
||||
struct enet_frame {
|
||||
unsigned char dest_addr[ENET_ADDR_LENGTH];
|
||||
unsigned char source_addr[ENET_ADDR_LENGTH];
|
||||
unsigned short type;
|
||||
unsigned char enet_data[1];
|
||||
};
|
||||
|
||||
struct arp_entry {
|
||||
unsigned long inet_address;
|
||||
unsigned char mac_address[ENET_ADDR_LENGTH];
|
||||
unsigned long valid;
|
||||
unsigned long sec;
|
||||
unsigned long nsec;
|
||||
};
|
||||
|
||||
|
||||
/* Statistic Areas */
|
||||
#define MAX_ERR_LOG 10
|
||||
|
||||
typedef struct emac_stats_st{ /* Statistic Block */
|
||||
int data_len_err;
|
||||
int rx_frames;
|
||||
int rx;
|
||||
int rx_prot_err;
|
||||
int int_err;
|
||||
int pkts_tx;
|
||||
int pkts_rx;
|
||||
int pkts_handled;
|
||||
short tx_err_log[MAX_ERR_LOG];
|
||||
short rx_err_log[MAX_ERR_LOG];
|
||||
} EMAC_STATS_ST, *EMAC_STATS_PST;
|
||||
|
||||
/* Structure containing variables used by the shared code (4xx_enet.c) */
|
||||
typedef struct emac_4xx_hw_st {
|
||||
uint32_t hw_addr; /* EMAC offset */
|
||||
uint32_t tah_addr; /* TAH offset */
|
||||
uint32_t phy_id;
|
||||
uint32_t phy_addr;
|
||||
uint32_t original_fc;
|
||||
uint32_t txcw;
|
||||
uint32_t autoneg_failed;
|
||||
uint32_t emac_ier;
|
||||
volatile mal_desc_t *tx;
|
||||
volatile mal_desc_t *rx;
|
||||
u32 tx_phys;
|
||||
u32 rx_phys;
|
||||
bd_t *bis; /* for eth_init upon mal error */
|
||||
mal_desc_t *alloc_tx_buf;
|
||||
mal_desc_t *alloc_rx_buf;
|
||||
char *txbuf_ptr;
|
||||
uint16_t devnum;
|
||||
int get_link_status;
|
||||
int tbi_compatibility_en;
|
||||
int tbi_compatibility_on;
|
||||
int fc_send_xon;
|
||||
int report_tx_early;
|
||||
int first_init;
|
||||
int tx_err_index;
|
||||
int rx_err_index;
|
||||
int rx_slot; /* MAL Receive Slot */
|
||||
int rx_i_index; /* Receive Interrupt Queue Index */
|
||||
int rx_u_index; /* Receive User Queue Index */
|
||||
int tx_slot; /* MAL Transmit Slot */
|
||||
int tx_i_index; /* Transmit Interrupt Queue Index */
|
||||
int tx_u_index; /* Transmit User Queue Index */
|
||||
int rx_ready[NUM_RX_BUFF]; /* Receive Ready Queue */
|
||||
int tx_run[NUM_TX_BUFF]; /* Transmit Running Queue */
|
||||
int is_receiving; /* sync with eth interrupt */
|
||||
int print_speed; /* print speed message upon start */
|
||||
EMAC_STATS_ST stats;
|
||||
} EMAC_4XX_HW_ST, *EMAC_4XX_HW_PST;
|
||||
|
||||
|
||||
#if defined(CONFIG_440GX) || defined(CONFIG_460GT)
|
||||
#define EMAC_NUM_DEV 4
|
||||
#elif (defined(CONFIG_440) || defined(CONFIG_405EP)) && \
|
||||
defined(CONFIG_NET_MULTI) && \
|
||||
!defined(CONFIG_440SP) && !defined(CONFIG_440SPE)
|
||||
#define EMAC_NUM_DEV 2
|
||||
#else
|
||||
#define EMAC_NUM_DEV 1
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_IBM_EMAC4_V4 /* EMAC4 V4 changed bit setting */
|
||||
#define EMAC_STACR_OC_MASK (0x00008000)
|
||||
#else
|
||||
#define EMAC_STACR_OC_MASK (0x00000000)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
|
||||
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
|
||||
defined(CONFIG_405EX)
|
||||
#define SDR0_PFC1_EM_1000 (0x00200000)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* XMII bridge configurations for those systems (e.g. 405EX(r)) that do
|
||||
* not have a pin function control (PFC) register to otherwise determine
|
||||
* the bridge configuration.
|
||||
*/
|
||||
#define EMAC_PHY_MODE_NONE 0
|
||||
#define EMAC_PHY_MODE_NONE_RGMII 1
|
||||
#define EMAC_PHY_MODE_RGMII_NONE 2
|
||||
#define EMAC_PHY_MODE_RGMII_RGMII 3
|
||||
#define EMAC_PHY_MODE_NONE_GMII 4
|
||||
#define EMAC_PHY_MODE_GMII_NONE 5
|
||||
#define EMAC_PHY_MODE_NONE_MII 6
|
||||
#define EMAC_PHY_MODE_MII_NONE 7
|
||||
|
||||
/* ZMII Bridge Register addresses */
|
||||
#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
|
||||
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
|
||||
defined(CONFIG_460EX) || defined(CONFIG_460GT)
|
||||
#define ZMII0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0D00)
|
||||
#else
|
||||
#define ZMII0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0780)
|
||||
#endif
|
||||
#define ZMII0_FER (ZMII0_BASE)
|
||||
#define ZMII0_SSR (ZMII0_BASE + 4)
|
||||
#define ZMII0_SMIISR (ZMII0_BASE + 8)
|
||||
|
||||
/* ZMII FER Register Bit Definitions */
|
||||
#define ZMII_FER_DIS (0x0)
|
||||
#define ZMII_FER_MDI (0x8)
|
||||
#define ZMII_FER_SMII (0x4)
|
||||
#define ZMII_FER_RMII (0x2)
|
||||
#define ZMII_FER_MII (0x1)
|
||||
|
||||
#define ZMII_FER_RSVD11 (0x00200000)
|
||||
#define ZMII_FER_RSVD10 (0x00100000)
|
||||
#define ZMII_FER_RSVD14_31 (0x0003FFFF)
|
||||
|
||||
#define ZMII_FER_V(__x) (((3 - __x) * 4) + 16)
|
||||
|
||||
|
||||
/* ZMII Speed Selection Register Bit Definitions */
|
||||
#define ZMII0_SSR_SCI (0x4)
|
||||
#define ZMII0_SSR_FSS (0x2)
|
||||
#define ZMII0_SSR_SP (0x1)
|
||||
#define ZMII0_SSR_RSVD16_31 (0x0000FFFF)
|
||||
|
||||
#define ZMII0_SSR_V(__x) (((3 - __x) * 4) + 16)
|
||||
|
||||
|
||||
/* ZMII SMII Status Register Bit Definitions */
|
||||
#define ZMII0_SMIISR_E1 (0x80)
|
||||
#define ZMII0_SMIISR_EC (0x40)
|
||||
#define ZMII0_SMIISR_EN (0x20)
|
||||
#define ZMII0_SMIISR_EJ (0x10)
|
||||
#define ZMII0_SMIISR_EL (0x08)
|
||||
#define ZMII0_SMIISR_ED (0x04)
|
||||
#define ZMII0_SMIISR_ES (0x02)
|
||||
#define ZMII0_SMIISR_EF (0x01)
|
||||
|
||||
#define ZMII0_SMIISR_V(__x) ((3 - __x) * 8)
|
||||
|
||||
/* RGMII Register Addresses */
|
||||
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
|
||||
#define RGMII_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x1000)
|
||||
#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
|
||||
#define RGMII_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x1500)
|
||||
#elif defined(CONFIG_405EX)
|
||||
#define RGMII_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0xB00)
|
||||
#else
|
||||
#define RGMII_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0790)
|
||||
#endif
|
||||
#define RGMII_FER (RGMII_BASE + 0x00)
|
||||
#define RGMII_SSR (RGMII_BASE + 0x04)
|
||||
|
||||
#if defined(CONFIG_460GT)
|
||||
#define RGMII1_BASE_OFFSET 0x100
|
||||
#endif
|
||||
|
||||
/* RGMII Function Enable (FER) Register Bit Definitions */
|
||||
#define RGMII_FER_DIS (0x00)
|
||||
#define RGMII_FER_RTBI (0x04)
|
||||
#define RGMII_FER_RGMII (0x05)
|
||||
#define RGMII_FER_TBI (0x06)
|
||||
#define RGMII_FER_GMII (0x07)
|
||||
#define RGMII_FER_MII (RGMII_FER_GMII)
|
||||
|
||||
#define RGMII_FER_V(__x) ((__x - 2) * 4)
|
||||
|
||||
#define RGMII_FER_MDIO(__x) (1 << (19 - (__x)))
|
||||
|
||||
/* RGMII Speed Selection Register Bit Definitions */
|
||||
#define RGMII_SSR_SP_10MBPS (0x00)
|
||||
#define RGMII_SSR_SP_100MBPS (0x02)
|
||||
#define RGMII_SSR_SP_1000MBPS (0x04)
|
||||
|
||||
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
|
||||
defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
|
||||
defined(CONFIG_405EX)
|
||||
#define RGMII_SSR_V(__x) ((__x) * 8)
|
||||
#else
|
||||
#define RGMII_SSR_V(__x) ((__x -2) * 8)
|
||||
#endif
|
||||
|
||||
/*---------------------------------------------------------------------------+
|
||||
| TCP/IP Acceleration Hardware (TAH) 440GX Only
|
||||
+---------------------------------------------------------------------------*/
|
||||
#if defined(CONFIG_440GX)
|
||||
#define TAH_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0B50)
|
||||
#define TAH_REVID (TAH_BASE + 0x0) /* Revision ID (RO)*/
|
||||
#define TAH_MR (TAH_BASE + 0x10) /* Mode Register (R/W) */
|
||||
#define TAH_SSR0 (TAH_BASE + 0x14) /* Segment Size Reg 0 (R/W) */
|
||||
#define TAH_SSR1 (TAH_BASE + 0x18) /* Segment Size Reg 1 (R/W) */
|
||||
#define TAH_SSR2 (TAH_BASE + 0x1C) /* Segment Size Reg 2 (R/W) */
|
||||
#define TAH_SSR3 (TAH_BASE + 0x20) /* Segment Size Reg 3 (R/W) */
|
||||
#define TAH_SSR4 (TAH_BASE + 0x24) /* Segment Size Reg 4 (R/W) */
|
||||
#define TAH_SSR5 (TAH_BASE + 0x28) /* Segment Size Reg 5 (R/W) */
|
||||
#define TAH_TSR (TAH_BASE + 0x2C) /* Transmit Status Register (RO) */
|
||||
|
||||
/* TAH Revision */
|
||||
#define TAH_REV_RN_M (0x000FFF00) /* Revision Number */
|
||||
#define TAH_REV_BN_M (0x000000FF) /* Branch Revision Number */
|
||||
|
||||
#define TAH_REV_RN_V (8)
|
||||
#define TAH_REV_BN_V (0)
|
||||
|
||||
/* TAH Mode Register */
|
||||
#define TAH_MR_CVR (0x80000000) /* Checksum verification on RX */
|
||||
#define TAH_MR_SR (0x40000000) /* Software reset */
|
||||
#define TAH_MR_ST (0x3F000000) /* Send Threshold */
|
||||
#define TAH_MR_TFS (0x00E00000) /* Transmit FIFO size */
|
||||
#define TAH_MR_DTFP (0x00100000) /* Disable TX FIFO parity */
|
||||
#define TAH_MR_DIG (0x00080000) /* Disable interrupt generation */
|
||||
#define TAH_MR_RSVD (0x0007FFFF) /* Reserved */
|
||||
|
||||
#define TAH_MR_ST_V (20)
|
||||
#define TAH_MR_TFS_V (17)
|
||||
|
||||
#define TAH_MR_TFS_2K (0x1) /* Transmit FIFO size 2Kbyte */
|
||||
#define TAH_MR_TFS_4K (0x2) /* Transmit FIFO size 4Kbyte */
|
||||
#define TAH_MR_TFS_6K (0x3) /* Transmit FIFO size 6Kbyte */
|
||||
#define TAH_MR_TFS_8K (0x4) /* Transmit FIFO size 8Kbyte */
|
||||
#define TAH_MR_TFS_10K (0x5) /* Transmit FIFO size 10Kbyte (max)*/
|
||||
|
||||
|
||||
/* TAH Segment Size Registers 0:5 */
|
||||
#define TAH_SSR_RSVD0 (0xC0000000) /* Reserved */
|
||||
#define TAH_SSR_SS (0x3FFE0000) /* Segment size in multiples of 2 */
|
||||
#define TAH_SSR_RSVD1 (0x0001FFFF) /* Reserved */
|
||||
|
||||
/* TAH Transmit Status Register */
|
||||
#define TAH_TSR_TFTS (0x80000000) /* Transmit FIFO too small */
|
||||
#define TAH_TSR_UH (0x40000000) /* Unrecognized header */
|
||||
#define TAH_TSR_NIPF (0x20000000) /* Not IPv4 */
|
||||
#define TAH_TSR_IPOP (0x10000000) /* IP option present */
|
||||
#define TAH_TSR_NISF (0x08000000) /* No IEEE SNAP format */
|
||||
#define TAH_TSR_ILTS (0x04000000) /* IP length too short */
|
||||
#define TAH_TSR_IPFP (0x02000000) /* IP fragment present */
|
||||
#define TAH_TSR_UP (0x01000000) /* Unsupported protocol */
|
||||
#define TAH_TSR_TFP (0x00800000) /* TCP flags present */
|
||||
#define TAH_TSR_SUDP (0x00400000) /* Segmentation for UDP */
|
||||
#define TAH_TSR_DLM (0x00200000) /* Data length mismatch */
|
||||
#define TAH_TSR_SIEEE (0x00100000) /* Segmentation for IEEE */
|
||||
#define TAH_TSR_TFPE (0x00080000) /* Transmit FIFO parity error */
|
||||
#define TAH_TSR_SSTS (0x00040000) /* Segment size too small */
|
||||
#define TAH_TSR_RSVD (0x0003FFFF) /* Reserved */
|
||||
#endif /* CONFIG_440GX */
|
||||
|
||||
|
||||
/* Ethernet MAC Regsiter Addresses */
|
||||
#if defined(CONFIG_440)
|
||||
#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
|
||||
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
|
||||
defined(CONFIG_460EX) || defined(CONFIG_460GT)
|
||||
#define EMAC0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0E00)
|
||||
#else
|
||||
#define EMAC0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0800)
|
||||
#endif
|
||||
#else
|
||||
#if defined(CONFIG_405EZ) || defined(CONFIG_405EX)
|
||||
#define EMAC0_BASE 0xEF600900
|
||||
#else
|
||||
#define EMAC0_BASE 0xEF600800
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_440EPX)
|
||||
#define EMAC1_BASE 0xEF600F00
|
||||
#define EMAC1_MR1 (EMAC1_BASE + 0x04)
|
||||
#endif
|
||||
|
||||
#define EMAC0_MR0 (EMAC0_BASE)
|
||||
#define EMAC0_MR1 (EMAC0_BASE + 0x04)
|
||||
#define EMAC0_TMR0 (EMAC0_BASE + 0x08)
|
||||
#define EMAC0_TMR1 (EMAC0_BASE + 0x0c)
|
||||
#define EMAC0_RXM (EMAC0_BASE + 0x10)
|
||||
#define EMAC0_ISR (EMAC0_BASE + 0x14)
|
||||
#define EMAC0_IER (EMAC0_BASE + 0x18)
|
||||
#define EMAC0_IAH (EMAC0_BASE + 0x1c)
|
||||
#define EMAC0_IAL (EMAC0_BASE + 0x20)
|
||||
#define EMAC0_PTR (EMAC0_BASE + 0x2c)
|
||||
#define EMAC0_PAUSE_TIME_REG EMAC0_PTR
|
||||
#define EMAC0_IPGVR (EMAC0_BASE + 0x58)
|
||||
#define EMAC0_I_FRAME_GAP_REG EMAC0_IPGVR
|
||||
#define EMAC0_STACR (EMAC0_BASE + 0x5c)
|
||||
#define EMAC0_TRTR (EMAC0_BASE + 0x60)
|
||||
#define EMAC0_RWMR (EMAC0_BASE + 0x64)
|
||||
#define EMAC0_RX_HI_LO_WMARK EMAC0_RWMR
|
||||
|
||||
/* bit definitions */
|
||||
/* MODE REG 0 */
|
||||
#define EMAC_MR0_RXI (0x80000000)
|
||||
#define EMAC_MR0_TXI (0x40000000)
|
||||
#define EMAC_MR0_SRST (0x20000000)
|
||||
#define EMAC_MR0_TXE (0x10000000)
|
||||
#define EMAC_MR0_RXE (0x08000000)
|
||||
#define EMAC_MR0_WKE (0x04000000)
|
||||
|
||||
/* on 440GX EMAC_MR1 has a different layout! */
|
||||
#if defined(CONFIG_440GX) || \
|
||||
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
|
||||
defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
|
||||
defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
|
||||
defined(CONFIG_405EX)
|
||||
/* MODE Reg 1 */
|
||||
#define EMAC_MR1_FDE (0x80000000)
|
||||
#define EMAC_MR1_ILE (0x40000000)
|
||||
#define EMAC_MR1_VLE (0x20000000)
|
||||
#define EMAC_MR1_EIFC (0x10000000)
|
||||
#define EMAC_MR1_APP (0x08000000)
|
||||
#define EMAC_MR1_RSVD (0x06000000)
|
||||
#define EMAC_MR1_IST (0x01000000)
|
||||
#define EMAC_MR1_MF_1000GPCS (0x00C00000)
|
||||
#define EMAC_MR1_MF_1000MBPS (0x00800000) /* 0's for 10MBPS */
|
||||
#define EMAC_MR1_MF_100MBPS (0x00400000)
|
||||
#define EMAC_MR1_RFS_MASK (0x00380000)
|
||||
#define EMAC_MR1_RFS_16K (0x00280000)
|
||||
#define EMAC_MR1_RFS_8K (0x00200000)
|
||||
#define EMAC_MR1_RFS_4K (0x00180000)
|
||||
#define EMAC_MR1_RFS_2K (0x00100000)
|
||||
#define EMAC_MR1_RFS_1K (0x00080000)
|
||||
#define EMAC_MR1_TX_FIFO_MASK (0x00070000)
|
||||
#define EMAC_MR1_TX_FIFO_16K (0x00050000)
|
||||
#define EMAC_MR1_TX_FIFO_8K (0x00040000)
|
||||
#define EMAC_MR1_TX_FIFO_4K (0x00030000)
|
||||
#define EMAC_MR1_TX_FIFO_2K (0x00020000)
|
||||
#define EMAC_MR1_TX_FIFO_1K (0x00010000)
|
||||
#define EMAC_MR1_TR_MULTI (0x00008000) /* 0'x for single packet */
|
||||
#define EMAC_MR1_MWSW (0x00007000)
|
||||
#define EMAC_MR1_JUMBO_ENABLE (0x00000800)
|
||||
#define EMAC_MR1_IPPA (0x000007c0)
|
||||
#define EMAC_MR1_IPPA_SET(id) (((id) & 0x1f) << 6)
|
||||
#define EMAC_MR1_IPPA_GET(id) (((id) >> 6) & 0x1f)
|
||||
#define EMAC_MR1_OBCI_GT100 (0x00000020)
|
||||
#define EMAC_MR1_OBCI_100 (0x00000018)
|
||||
#define EMAC_MR1_OBCI_83 (0x00000010)
|
||||
#define EMAC_MR1_OBCI_66 (0x00000008)
|
||||
#define EMAC_MR1_RSVD1 (0x00000007)
|
||||
#else /* defined(CONFIG_440GX) */
|
||||
/* EMAC_MR1 is the same on 405GP, 405GPr, 405EP, 440GP, 440EP */
|
||||
#define EMAC_MR1_FDE 0x80000000
|
||||
#define EMAC_MR1_ILE 0x40000000
|
||||
#define EMAC_MR1_VLE 0x20000000
|
||||
#define EMAC_MR1_EIFC 0x10000000
|
||||
#define EMAC_MR1_APP 0x08000000
|
||||
#define EMAC_MR1_AEMI 0x02000000
|
||||
#define EMAC_MR1_IST 0x01000000
|
||||
#define EMAC_MR1_MF_1000MBPS 0x00800000 /* 0's for 10MBPS */
|
||||
#define EMAC_MR1_MF_100MBPS 0x00400000
|
||||
#define EMAC_MR1_RFS_MASK 0x00300000
|
||||
#define EMAC_MR1_RFS_4K 0x00300000
|
||||
#define EMAC_MR1_RFS_2K 0x00200000
|
||||
#define EMAC_MR1_RFS_1K 0x00100000
|
||||
#define EMAC_MR1_RFS_512 0x00000000
|
||||
#define EMAC_MR1_TX_FIFO_MASK 0x000c0000
|
||||
#define EMAC_MR1_TX_FIFO_2K 0x00080000
|
||||
#define EMAC_MR1_TX_FIFO_1K 0x00040000
|
||||
#define EMAC_MR1_TX_FIFO_512 0x00000000
|
||||
#define EMAC_MR1_TR0_DEPEND 0x00010000 /* 0'x for single packet */
|
||||
#define EMAC_MR1_TR0_MULTI 0x00008000
|
||||
#define EMAC_MR1_TR1_DEPEND 0x00004000
|
||||
#define EMAC_MR1_TR1_MULTI 0x00002000
|
||||
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
|
||||
#define EMAC_MR1_JUMBO_ENABLE 0x00001000
|
||||
#endif /* defined(CONFIG_440EP) || defined(CONFIG_440GR) */
|
||||
#endif /* defined(CONFIG_440GX) */
|
||||
|
||||
#define EMAC_MR1_FIFO_MASK (EMAC_MR1_RFS_MASK | EMAC_MR1_TX_FIFO_MASK)
|
||||
#if defined(CONFIG_405EZ)
|
||||
/* 405EZ only supports 512 bytes fifos */
|
||||
#define EMAC_MR1_FIFO_SIZE (EMAC_MR1_RFS_512 | EMAC_MR1_TX_FIFO_512)
|
||||
#else
|
||||
/* Set receive fifo to 4k and tx fifo to 2k */
|
||||
#define EMAC_MR1_FIFO_SIZE (EMAC_MR1_RFS_4K | EMAC_MR1_TX_FIFO_2K)
|
||||
#endif
|
||||
|
||||
/* Transmit Mode Register 0 */
|
||||
#define EMAC_TMR0_GNP0 (0x80000000)
|
||||
#define EMAC_TMR0_GNP1 (0x40000000)
|
||||
#define EMAC_TMR0_GNPD (0x20000000)
|
||||
#define EMAC_TMR0_FC (0x10000000)
|
||||
|
||||
/* Receive Mode Register */
|
||||
#define EMAC_RMR_SP (0x80000000)
|
||||
#define EMAC_RMR_SFCS (0x40000000)
|
||||
#define EMAC_RMR_ARRP (0x20000000)
|
||||
#define EMAC_RMR_ARP (0x10000000)
|
||||
#define EMAC_RMR_AROP (0x08000000)
|
||||
#define EMAC_RMR_ARPI (0x04000000)
|
||||
#define EMAC_RMR_PPP (0x02000000)
|
||||
#define EMAC_RMR_PME (0x01000000)
|
||||
#define EMAC_RMR_PMME (0x00800000)
|
||||
#define EMAC_RMR_IAE (0x00400000)
|
||||
#define EMAC_RMR_MIAE (0x00200000)
|
||||
#define EMAC_RMR_BAE (0x00100000)
|
||||
#define EMAC_RMR_MAE (0x00080000)
|
||||
|
||||
/* Interrupt Status & enable Regs */
|
||||
#define EMAC_ISR_OVR (0x02000000)
|
||||
#define EMAC_ISR_PP (0x01000000)
|
||||
#define EMAC_ISR_BP (0x00800000)
|
||||
#define EMAC_ISR_RP (0x00400000)
|
||||
#define EMAC_ISR_SE (0x00200000)
|
||||
#define EMAC_ISR_SYE (0x00100000)
|
||||
#define EMAC_ISR_BFCS (0x00080000)
|
||||
#define EMAC_ISR_PTLE (0x00040000)
|
||||
#define EMAC_ISR_ORE (0x00020000)
|
||||
#define EMAC_ISR_IRE (0x00010000)
|
||||
#define EMAC_ISR_DBDM (0x00000200)
|
||||
#define EMAC_ISR_DB0 (0x00000100)
|
||||
#define EMAC_ISR_SE0 (0x00000080)
|
||||
#define EMAC_ISR_TE0 (0x00000040)
|
||||
#define EMAC_ISR_DB1 (0x00000020)
|
||||
#define EMAC_ISR_SE1 (0x00000010)
|
||||
#define EMAC_ISR_TE1 (0x00000008)
|
||||
#define EMAC_ISR_MOS (0x00000002)
|
||||
#define EMAC_ISR_MOF (0x00000001)
|
||||
|
||||
/* STA CONTROL REG */
|
||||
#define EMAC_STACR_OC (0x00008000)
|
||||
#define EMAC_STACR_PHYE (0x00004000)
|
||||
|
||||
#ifdef CONFIG_IBM_EMAC4_V4 /* EMAC4 V4 changed bit setting */
|
||||
#define EMAC_STACR_INDIRECT_MODE (0x00002000)
|
||||
#define EMAC_STACR_WRITE (0x00000800) /* $BUC */
|
||||
#define EMAC_STACR_READ (0x00001000) /* $BUC */
|
||||
#define EMAC_STACR_OP_MASK (0x00001800)
|
||||
#define EMAC_STACR_MDIO_ADDR (0x00000000)
|
||||
#define EMAC_STACR_MDIO_WRITE (0x00000800)
|
||||
#define EMAC_STACR_MDIO_READ (0x00001800)
|
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#define EMAC_STACR_MDIO_READ_INC (0x00001000)
|
||||
#else
|
||||
#define EMAC_STACR_WRITE (0x00002000)
|
||||
#define EMAC_STACR_READ (0x00001000)
|
||||
#endif
|
||||
|
||||
#define EMAC_STACR_CLK_83MHZ (0x00000800) /* 0's for 50Mhz */
|
||||
#define EMAC_STACR_CLK_66MHZ (0x00000400)
|
||||
#define EMAC_STACR_CLK_100MHZ (0x00000C00)
|
||||
|
||||
/* Transmit Request Threshold Register */
|
||||
#define EMAC_TRTR_256 (0x18000000) /* 0's for 64 Bytes */
|
||||
#define EMAC_TRTR_192 (0x10000000)
|
||||
#define EMAC_TRTR_128 (0x01000000)
|
||||
|
||||
/* the follwing defines are for the MadMAL status and control registers. */
|
||||
/* For bits 0..5 look at the mal.h file */
|
||||
#define EMAC_TX_CTRL_GFCS (0x0200)
|
||||
#define EMAC_TX_CTRL_GP (0x0100)
|
||||
#define EMAC_TX_CTRL_ISA (0x0080)
|
||||
#define EMAC_TX_CTRL_RSA (0x0040)
|
||||
#define EMAC_TX_CTRL_IVT (0x0020)
|
||||
#define EMAC_TX_CTRL_RVT (0x0010)
|
||||
|
||||
#define EMAC_TX_CTRL_DEFAULT (EMAC_TX_CTRL_GFCS |EMAC_TX_CTRL_GP)
|
||||
|
||||
#define EMAC_TX_ST_BFCS (0x0200)
|
||||
#define EMAC_TX_ST_BPP (0x0100)
|
||||
#define EMAC_TX_ST_LCS (0x0080)
|
||||
#define EMAC_TX_ST_ED (0x0040)
|
||||
#define EMAC_TX_ST_EC (0x0020)
|
||||
#define EMAC_TX_ST_LC (0x0010)
|
||||
#define EMAC_TX_ST_MC (0x0008)
|
||||
#define EMAC_TX_ST_SC (0x0004)
|
||||
#define EMAC_TX_ST_UR (0x0002)
|
||||
#define EMAC_TX_ST_SQE (0x0001)
|
||||
|
||||
#define EMAC_TX_ST_DEFAULT (0x03F3)
|
||||
|
||||
|
||||
/* madmal receive status / Control bits */
|
||||
|
||||
#define EMAC_RX_ST_OE (0x0200)
|
||||
#define EMAC_RX_ST_PP (0x0100)
|
||||
#define EMAC_RX_ST_BP (0x0080)
|
||||
#define EMAC_RX_ST_RP (0x0040)
|
||||
#define EMAC_RX_ST_SE (0x0020)
|
||||
#define EMAC_RX_ST_AE (0x0010)
|
||||
#define EMAC_RX_ST_BFCS (0x0008)
|
||||
#define EMAC_RX_ST_PTL (0x0004)
|
||||
#define EMAC_RX_ST_ORE (0x0002)
|
||||
#define EMAC_RX_ST_IRE (0x0001)
|
||||
/* all the errors we care about */
|
||||
#define EMAC_RX_ERRORS (0x03FF)
|
||||
|
||||
#endif /* _PPC4XX_ENET_H_ */
|
||||
Reference in New Issue
Block a user