arm: Remove support for s3c4510
This stuff has been rotting in the tree for a year now. Remove it. Signed-off-by: Marek Vasut <marex@denx.de>
This commit is contained in:
Marek Vasut
committed by
Albert ARIBAUD
Albert ARIBAUD
parent
6f62f42071
commit
afad40299e
@@ -46,7 +46,7 @@ int cleanup_before_linux (void)
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* and we set the CPU-speed to 73 MHz - see start.S for details
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*/
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#if defined(CONFIG_NETARM) || defined(CONFIG_S3C4510B)
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#if defined(CONFIG_NETARM)
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disable_interrupts ();
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/* Nothing more needed */
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#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
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@@ -45,28 +45,10 @@
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#define READ_TIMER (TM2STAT & NETARM_GEN_TSTAT_CTC_MASK)
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#endif
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#ifdef CONFIG_S3C4510B
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/* require interrupts for the S3C4510B */
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# ifndef CONFIG_USE_IRQ
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# error CONFIG_USE_IRQ _must_ be defined when using CONFIG_S3C4510B
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# else
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static struct _irq_handler IRQ_HANDLER[N_IRQS];
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# endif
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#endif /* CONFIG_S3C4510B */
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#ifdef CONFIG_USE_IRQ
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void do_irq (struct pt_regs *pt_regs)
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{
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#if defined(CONFIG_S3C4510B)
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unsigned int pending;
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while ( (pending = GET_REG( REG_INTOFFSET)) != 0x54) { /* sentinal value for no pending interrutps */
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IRQ_HANDLER[pending>>2].m_func( IRQ_HANDLER[pending>>2].m_data);
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/* clear pending interrupt */
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PUT_REG( REG_INTPEND, (1<<(pending>>2)));
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}
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#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
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#if defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
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/* No do_irq() for IntegratorAP/CM720T as yet */
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#else
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#error do_irq() not defined for this CPU type
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@@ -74,23 +56,6 @@ void do_irq (struct pt_regs *pt_regs)
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}
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#endif
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#ifdef CONFIG_S3C4510B
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static void default_isr( void *data) {
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printf ("default_isr(): called for IRQ %d\n", (int)data);
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}
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static void timer_isr( void *data) {
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unsigned int *pTime = (unsigned int *)data;
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(*pTime)++;
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if ( !(*pTime % (CONFIG_SYS_HZ/4))) {
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/* toggle LED 0 */
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PUT_REG( REG_IOPDATA, GET_REG(REG_IOPDATA) ^ 0x1);
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}
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}
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#endif
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#if defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
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/* Use IntegratorAP routines in board/integratorap.c */
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#else
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@@ -98,32 +63,6 @@ static void timer_isr( void *data) {
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static ulong timestamp;
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static ulong lastdec;
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#if defined(CONFIG_USE_IRQ) && defined(CONFIG_S3C4510B)
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int arch_interrupt_init (void)
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{
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int i;
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/* install default interrupt handlers */
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for ( i = 0; i < N_IRQS; i++) {
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IRQ_HANDLER[i].m_data = (void *)i;
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IRQ_HANDLER[i].m_func = default_isr;
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}
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/* configure interrupts for IRQ mode */
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PUT_REG( REG_INTMODE, 0x0);
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/* clear any pending interrupts */
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PUT_REG( REG_INTPEND, 0x1FFFFF);
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lastdec = 0;
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/* install interrupt handler for timer */
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IRQ_HANDLER[INT_TIMER0].m_data = (void *)×tamp;
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IRQ_HANDLER[INT_TIMER0].m_func = timer_isr;
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return 0;
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}
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#endif
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int timer_init (void)
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{
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#if defined(CONFIG_NETARM)
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@@ -137,29 +76,6 @@ int timer_init (void)
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/* set timer 2 counter */
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lastdec = TIMER_LOAD_VAL;
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#elif defined(CONFIG_S3C4510B)
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/* configure free running timer 0 */
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PUT_REG( REG_TMOD, 0x0);
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/* Stop timer 0 */
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CLR_REG( REG_TMOD, TM0_RUN);
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/* Configure for interval mode */
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CLR_REG( REG_TMOD, TM1_TOGGLE);
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/*
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* Load Timer data register with count down value.
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* count_down_val = CONFIG_SYS_SYS_CLK_FREQ/CONFIG_SYS_HZ
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*/
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PUT_REG( REG_TDATA0, (CONFIG_SYS_SYS_CLK_FREQ / CONFIG_SYS_HZ));
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/*
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* Enable global interrupt
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* Enable timer0 interrupt
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*/
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CLR_REG( REG_INTMASK, ((1<<INT_GLOBAL) | (1<<INT_TIMER0)));
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/* Start timer */
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SET_REG( REG_TMOD, TM0_RUN);
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#elif defined(CONFIG_TEGRA)
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/* No timer routines for tegra as yet */
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lastdec = 0;
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@@ -237,26 +153,6 @@ void udelay_masked (unsigned long usec)
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} while (diff >= 0);
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}
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#elif defined(CONFIG_S3C4510B)
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ulong get_timer (ulong base)
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{
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return timestamp - base;
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}
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void __udelay (unsigned long usec)
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{
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u32 ticks;
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ticks = (usec * CONFIG_SYS_HZ) / 1000000;
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ticks += get_timer (0);
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while (get_timer (0) < ticks)
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/*NOP*/;
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}
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#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
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/* No timer routines for IntegratorAP/CM720T as yet */
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#elif defined(CONFIG_TEGRA)
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@@ -1,45 +0,0 @@
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#
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# (C) Copyright 2000-2008
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(SOC).o
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COBJS-y += cache.o
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SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
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OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y))
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all: $(obj).depend $(LIB)
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$(LIB): $(OBJS)
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$(call cmd_link_o_target, $(OBJS))
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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@@ -1,86 +0,0 @@
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/*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Alex Zuepke <azu@sysgo.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/hardware.h>
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void icache_enable (void)
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{
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s32 i;
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/* disable all cache bits */
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CLR_REG( REG_SYSCFG, 0x3F);
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/* 8KB cache, write enable */
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SET_REG( REG_SYSCFG, CACHE_WRITE_BUFF | CACHE_MODE_01);
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/* clear TAG RAM bits */
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for ( i = 0; i < 256; i++)
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PUT_REG( CACHE_TAG_RAM + 4*i, 0x00000000);
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/* clear SET0 RAM */
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for(i=0; i < 1024; i++)
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PUT_REG( CACHE_SET0_RAM + 4*i, 0x00000000);
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/* clear SET1 RAM */
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for(i=0; i < 1024; i++)
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PUT_REG( CACHE_SET1_RAM + 4*i, 0x00000000);
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/* enable cache */
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SET_REG( REG_SYSCFG, CACHE_ENABLE);
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}
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void icache_disable (void)
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{
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/* disable all cache bits */
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CLR_REG( REG_SYSCFG, 0x3F);
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}
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int icache_status (void)
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{
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return GET_REG( REG_SYSCFG) & CACHE_ENABLE;
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}
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void dcache_enable (void)
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{
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/* we don't have seperate instruction/data caches */
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icache_enable();
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}
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void dcache_disable (void)
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{
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/* we don't have seperate instruction/data caches */
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icache_disable();
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}
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int dcache_status (void)
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{
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/* we don't have seperate instruction/data caches */
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return icache_status();
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}
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@@ -335,22 +335,6 @@ cpu_init_crit:
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ldr r0, =NETARM_GEN_MODULE_BASE
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str r1, [r0, #+NETARM_GEN_INTR_ENABLE]
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#elif defined(CONFIG_S3C4510B)
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/*
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* Mask off all IRQ sources
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*/
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ldr r1, =REG_INTMASK
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ldr r0, =0x3FFFFF
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str r0, [r1]
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/*
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* Disable Cache
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*/
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ldr r0, =REG_SYSCFG
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ldr r1, =0x83ffffa0 /* cache-disabled */
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str r1, [r0]
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#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
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/* No specific initialisation for IntegratorAP/CM720T as yet */
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#elif defined(CONFIG_TEGRA)
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@@ -569,9 +553,6 @@ reset_cpu:
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ldr r1, =NETARM_GEN_SW_SVC_RESETB
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str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
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mov pc, r0
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#elif defined(CONFIG_S3C4510B)
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/* Nothing done here as reseting the CPU is board specific, depending
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* on external peripherals such as watchdog timers, etc. */
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#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
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/* No specific reset actions for IntegratorAP/CM720T as yet */
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#elif defined(CONFIG_TEGRA)
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@@ -1,272 +0,0 @@
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#ifndef __HW_S3C4510_H
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#define __HW_S3C4510_H
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/*
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* Copyright (c) 2004 Cucy Systems (http://www.cucy.com)
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* Curt Brune <curt@cucy.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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* Description: Samsung S3C4510B register layout
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*/
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/*------------------------------------------------------------------------
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* ASIC Address Definition
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*----------------------------------------------------------------------*/
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/* L1 8KB on chip SRAM base address */
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#define SRAM_BASE (0x03fe0000)
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/* Special Register Start Address After System Reset */
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#define REG_BASE (0x03ff0000)
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#define SPSTR (REG_BASE)
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/* *********************** */
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/* System Manager Register */
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/* *********************** */
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#define REG_SYSCFG (REG_BASE+0x0000)
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#define REG_CLKCON (REG_BASE+0x3000)
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#define REG_EXTACON0 (REG_BASE+0x3008)
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#define REG_EXTACON1 (REG_BASE+0x300c)
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#define REG_EXTDBWTH (REG_BASE+0x3010)
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#define REG_ROMCON0 (REG_BASE+0x3014)
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#define REG_ROMCON1 (REG_BASE+0x3018)
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#define REG_ROMCON2 (REG_BASE+0x301c)
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#define REG_ROMCON3 (REG_BASE+0x3020)
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#define REG_ROMCON4 (REG_BASE+0x3024)
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#define REG_ROMCON5 (REG_BASE+0x3028)
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#define REG_DRAMCON0 (REG_BASE+0x302c)
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#define REG_DRAMCON1 (REG_BASE+0x3030)
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#define REG_DRAMCON2 (REG_BASE+0x3034)
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#define REG_DRAMCON3 (REG_BASE+0x3038)
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#define REG_REFEXTCON (REG_BASE+0x303c)
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/* *********************** */
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/* Ethernet BDMA Register */
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/* *********************** */
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#define REG_BDMATXCON (REG_BASE+0x9000)
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#define REG_BDMARXCON (REG_BASE+0x9004)
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#define REG_BDMATXPTR (REG_BASE+0x9008)
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#define REG_BDMARXPTR (REG_BASE+0x900c)
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#define REG_BDMARXLSZ (REG_BASE+0x9010)
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#define REG_BDMASTAT (REG_BASE+0x9014)
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/* Content Address Memory */
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#define REG_CAM_BASE (REG_BASE+0x9100)
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#define REG_BDMATXBUF (REG_BASE+0x9200)
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#define REG_BDMARXBUF (REG_BASE+0x9800)
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/* *********************** */
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/* Ethernet MAC Register */
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/* *********************** */
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#define REG_MACCON (REG_BASE+0xa000)
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#define REG_CAMCON (REG_BASE+0xa004)
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#define REG_MACTXCON (REG_BASE+0xa008)
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#define REG_MACTXSTAT (REG_BASE+0xa00c)
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#define REG_MACRXCON (REG_BASE+0xa010)
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#define REG_MACRXSTAT (REG_BASE+0xa014)
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#define REG_STADATA (REG_BASE+0xa018)
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#define REG_STACON (REG_BASE+0xa01c)
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#define REG_CAMEN (REG_BASE+0xa028)
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#define REG_EMISSCNT (REG_BASE+0xa03c)
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#define REG_EPZCNT (REG_BASE+0xa040)
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#define REG_ERMPZCNT (REG_BASE+0xa044)
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#define REG_ETXSTAT (REG_BASE+0x9040)
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#define REG_MACRXDESTR (REG_BASE+0xa064)
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#define REG_MACRXSTATEM (REG_BASE+0xa090)
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#define REG_MACRXFIFO (REG_BASE+0xa200)
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/********************/
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/* I2C Bus Register */
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/********************/
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#define REG_I2C_CON (REG_BASE+0xf000)
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#define REG_I2C_BUF (REG_BASE+0xf004)
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#define REG_I2C_PS (REG_BASE+0xf008)
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#define REG_I2C_COUNT (REG_BASE+0xf00c)
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/********************/
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/* GDMA 0 */
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/********************/
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#define REG_GDMACON0 (REG_BASE+0xb000)
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#define REG_GDMA0_RUN_ENABLE (REG_BASE+0xb020)
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#define REG_GDMASRC0 (REG_BASE+0xb004)
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#define REG_GDMADST0 (REG_BASE+0xb008)
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#define REG_GDMACNT0 (REG_BASE+0xb00c)
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/********************/
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/* GDMA 1 */
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/********************/
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#define REG_GDMACON1 (REG_BASE+0xc000)
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#define REG_GDMA1_RUN_ENABLE (REG_BASE+0xc020)
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#define REG_GDMASRC1 (REG_BASE+0xc004)
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#define REG_GDMADST1 (REG_BASE+0xc008)
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#define REG_GDMACNT1 (REG_BASE+0xc00c)
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/********************/
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/* UART 0 */
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/********************/
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#define UART0_BASE (REG_BASE+0xd000)
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#define REG_UART0_LCON (REG_BASE+0xd000)
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#define REG_UART0_CTRL (REG_BASE+0xd004)
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#define REG_UART0_STAT (REG_BASE+0xd008)
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#define REG_UART0_TXB (REG_BASE+0xd00c)
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#define REG_UART0_RXB (REG_BASE+0xd010)
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#define REG_UART0_BAUD_DIV (REG_BASE+0xd014)
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#define REG_UART0_BAUD_CNT (REG_BASE+0xd018)
|
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#define REG_UART0_BAUD_CLK (REG_BASE+0xd01C)
|
||||
|
||||
/********************/
|
||||
/* UART 1 */
|
||||
/********************/
|
||||
#define UART1_BASE (REG_BASE+0xe000)
|
||||
#define REG_UART1_LCON (REG_BASE+0xe000)
|
||||
#define REG_UART1_CTRL (REG_BASE+0xe004)
|
||||
#define REG_UART1_STAT (REG_BASE+0xe008)
|
||||
#define REG_UART1_TXB (REG_BASE+0xe00c)
|
||||
#define REG_UART1_RXB (REG_BASE+0xe010)
|
||||
#define REG_UART1_BAUD_DIV (REG_BASE+0xe014)
|
||||
#define REG_UART1_BAUD_CNT (REG_BASE+0xe018)
|
||||
#define REG_UART1_BAUD_CLK (REG_BASE+0xe01C)
|
||||
|
||||
/********************/
|
||||
/* Timer Register */
|
||||
/********************/
|
||||
#define REG_TMOD (REG_BASE+0x6000)
|
||||
#define REG_TDATA0 (REG_BASE+0x6004)
|
||||
#define REG_TDATA1 (REG_BASE+0x6008)
|
||||
#define REG_TCNT0 (REG_BASE+0x600c)
|
||||
#define REG_TCNT1 (REG_BASE+0x6010)
|
||||
|
||||
/**********************/
|
||||
/* I/O Port Interface */
|
||||
/**********************/
|
||||
#define REG_IOPMODE (REG_BASE+0x5000)
|
||||
#define REG_IOPCON (REG_BASE+0x5004)
|
||||
#define REG_IOPDATA (REG_BASE+0x5008)
|
||||
|
||||
/*********************************/
|
||||
/* Interrupt Controller Register */
|
||||
/*********************************/
|
||||
#define REG_INTMODE (REG_BASE+0x4000)
|
||||
#define REG_INTPEND (REG_BASE+0x4004)
|
||||
#define REG_INTMASK (REG_BASE+0x4008)
|
||||
|
||||
#define REG_INTPRI0 (REG_BASE+0x400c)
|
||||
#define REG_INTPRI1 (REG_BASE+0x4010)
|
||||
#define REG_INTPRI2 (REG_BASE+0x4014)
|
||||
#define REG_INTPRI3 (REG_BASE+0x4018)
|
||||
#define REG_INTPRI4 (REG_BASE+0x401c)
|
||||
#define REG_INTPRI5 (REG_BASE+0x4020)
|
||||
#define REG_INTOFFSET (REG_BASE+0x4024)
|
||||
#define REG_INTPNDPRI (REG_BASE+0x4028)
|
||||
#define REG_INTPNDTST (REG_BASE+0x402C)
|
||||
|
||||
/*********************************/
|
||||
/* CACHE CONTROL MASKS */
|
||||
/*********************************/
|
||||
#define CACHE_STALL (0x00000001)
|
||||
#define CACHE_ENABLE (0x00000002)
|
||||
#define CACHE_WRITE_BUFF (0x00000004)
|
||||
#define CACHE_MODE (0x00000030)
|
||||
#define CACHE_MODE_00 (0x00000000)
|
||||
#define CACHE_MODE_01 (0x00000010)
|
||||
#define CACHE_MODE_10 (0x00000020)
|
||||
|
||||
/*********************************/
|
||||
/* CACHE RAM BASE ADDRESSES */
|
||||
/*********************************/
|
||||
#define CACHE_SET0_RAM (0x10000000)
|
||||
#define CACHE_SET1_RAM (0x10800000)
|
||||
#define CACHE_TAG_RAM (0x11000000)
|
||||
|
||||
/*********************************/
|
||||
/* CACHE_DISABLE MASK */
|
||||
/*********************************/
|
||||
#define CACHE_DISABLE_MASK (0x04000000)
|
||||
|
||||
#define GET_REG(reg) (*((volatile u32 *)(reg)))
|
||||
#define PUT_REG(reg, val) (*((volatile u32 *)(reg)) = ((u32)(val)))
|
||||
#define SET_REG(reg, mask) (PUT_REG((reg), GET_REG((reg)) | mask))
|
||||
#define CLR_REG(reg, mask) (PUT_REG((reg), GET_REG((reg)) & ~mask))
|
||||
#define PUT_U16(reg, val) (*((volatile u16 *)(reg)) = ((u16)(val)))
|
||||
#define PUT__U8(reg, val) (*((volatile u8 *)(reg)) = (( u8)((val)&0xFF)))
|
||||
#define GET__U8(reg) (*((volatile u8 *)(reg)))
|
||||
|
||||
#define PUT_LED(val) (PUT_REG(REG_IOPDATA, (~val)&0xFF))
|
||||
#define GET_LED() ((~GET_REG( REG_IOPDATA)) & 0xFF)
|
||||
#define SET_LED(val) { u32 led = GET_LED(); led |= 1 << (val); PUT_LED( led); }
|
||||
#define CLR_LED(val) { u32 led = GET_LED(); led &= ~(1 << (val)); PUT_LED( led); }
|
||||
|
||||
/***********************************/
|
||||
/* CLOCK CONSTANTS -- 50 MHz Clock */
|
||||
/***********************************/
|
||||
|
||||
#define CLK_FREQ_MHZ (50)
|
||||
#define t_data_us(t) ((t)*CLK_FREQ_MHZ-1) /* t is time tick,unit[us] */
|
||||
#define t_data_ms(t) (t_data_us((t)*1000)) /* t is time tick,unit[ms] */
|
||||
|
||||
/*********************************************************/
|
||||
/* TIMER MODE REGISTER */
|
||||
/*********************************************************/
|
||||
#define TM0_RUN 0x01 /* Timer 0 enable */
|
||||
#define TM0_TOGGLE 0x02 /* 0, interval mode */
|
||||
#define TM0_OUT_1 0x04 /* Timer 0 Initial TOUT0 value */
|
||||
#define TM1_RUN 0x08 /* Timer 1 enable */
|
||||
#define TM1_TOGGLE 0x10 /* 0, interval mode */
|
||||
#define TM1_OUT_1 0x20 /* Timer 0 Initial TOUT0 value */
|
||||
|
||||
|
||||
/*********************************/
|
||||
/* INTERRUPT SOURCES */
|
||||
/*********************************/
|
||||
#define INT_EXTINT0 0
|
||||
#define INT_EXTINT1 1
|
||||
#define INT_EXTINT2 2
|
||||
#define INT_EXTINT3 3
|
||||
#define INT_UARTTX0 4
|
||||
#define INT_UARTRX0 5
|
||||
#define INT_UARTTX1 6
|
||||
#define INT_UARTRX1 7
|
||||
#define INT_GDMA0 8
|
||||
#define INT_GDMA1 9
|
||||
#define INT_TIMER0 10
|
||||
#define INT_TIMER1 11
|
||||
#define INT_HDLCTXA 12
|
||||
#define INT_HDLCRXA 13
|
||||
#define INT_HDLCTXB 14
|
||||
#define INT_HDLCRXB 15
|
||||
#define INT_BDMATX 16
|
||||
#define INT_BDMARX 17
|
||||
#define INT_MACTX 18
|
||||
#define INT_MACRX 19
|
||||
#define INT_IIC 20
|
||||
#define INT_GLOBAL 21
|
||||
#define N_IRQS (21)
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
struct _irq_handler {
|
||||
void *m_data;
|
||||
void (*m_func)( void *data);
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
#endif /* __S3C4510_h */
|
||||
Reference in New Issue
Block a user