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ppc4xx: Big header cleanup part 2, mostly PPC405 related

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This cleanup is done by creating header files for all SoC versions and
moving the SoC specific defines into these special headers. This way the
common header ppc405.h and ppc440.h can be cleaned up finally.

As a part from this cleanup, the GPIO definitions for PPC405EP are
corrected. The high and low parts of the registers (for example
CONFIG_SYS_GPIO0_OSRL vs. CONFIG_SYS_GPIO0_OSRH) have been defined in
the wrong order. This patch now fixes this issue by switching these
xxxH and xxxL values. This brings the GPIO 405EP port in sync with all
other PPC4xx ports.

Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Stefan Roese
2010-09-12 06:21:37 +02:00
parent 5e7abce991
commit afabb498b7
38 changed files with 713 additions and 949 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
include/configs/ASH405.h
View File

@@ -335,12 +335,12 @@
* GPIO0[28-29] - UART1 data signal input/output
* GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
*/
#define CONFIG_SYS_GPIO0_OSRH 0x40000550
#define CONFIG_SYS_GPIO0_OSRL 0x00000110
#define CONFIG_SYS_GPIO0_ISR1H 0x00000000
#define CONFIG_SYS_GPIO0_ISR1L 0x15555445
#define CONFIG_SYS_GPIO0_TSRH 0x00000000
#define CONFIG_SYS_GPIO0_OSRL 0x40000550
#define CONFIG_SYS_GPIO0_OSRH 0x00000110
#define CONFIG_SYS_GPIO0_ISR1L 0x00000000
#define CONFIG_SYS_GPIO0_ISR1H 0x15555445
#define CONFIG_SYS_GPIO0_TSRL 0x00000000
#define CONFIG_SYS_GPIO0_TSRH 0x00000000
#define CONFIG_SYS_GPIO0_TCR 0xF7FE0014
#define CONFIG_SYS_DUART_RST (0x80000000 >> 14)

12
include/configs/CATcenter.h
View File

@@ -535,13 +535,13 @@
* GPIO0[30] - EMAC0 input
* GPIO0[31] - EMAC1 reject packet as output
*/
#define CONFIG_SYS_GPIO0_OSRH 0x40000550
#define CONFIG_SYS_GPIO0_OSRL 0x00000110
#define CONFIG_SYS_GPIO0_ISR1H 0x00000000
/*#define CONFIG_SYS_GPIO0_ISR1L 0x15555445*/
#define CONFIG_SYS_GPIO0_ISR1L 0x15555444
#define CONFIG_SYS_GPIO0_TSRH 0x00000000
#define CONFIG_SYS_GPIO0_OSRL 0x40000550
#define CONFIG_SYS_GPIO0_OSRH 0x00000110
#define CONFIG_SYS_GPIO0_ISR1L 0x00000000
/*#define CONFIG_SYS_GPIO0_ISR1H 0x15555445*/
#define CONFIG_SYS_GPIO0_ISR1H 0x15555444
#define CONFIG_SYS_GPIO0_TSRL 0x00000000
#define CONFIG_SYS_GPIO0_TSRH 0x00000000
#define CONFIG_SYS_GPIO0_TCR 0xF7FF8014
/*

12
include/configs/CMS700.h
View File

@@ -301,12 +301,12 @@
/* GPIO Output: OSR=00, ISR=00, TSR=00, TCR=1 */
/* Alt. Funtion Input: OSR=00, ISR=01, TSR=00, TCR=0 */
/* Alt. Funtion Output: OSR=01, ISR=00, TSR=00, TCR=1 */
#define CONFIG_SYS_GPIO0_OSRH 0x40000500 /* 0 ... 15 */
#define CONFIG_SYS_GPIO0_OSRL 0x00000110 /* 16 ... 31 */
#define CONFIG_SYS_GPIO0_ISR1H 0x00000000 /* 0 ... 15 */
#define CONFIG_SYS_GPIO0_ISR1L 0x14000045 /* 16 ... 31 */
#define CONFIG_SYS_GPIO0_TSRH 0x00000000 /* 0 ... 15 */
#define CONFIG_SYS_GPIO0_TSRL 0x00000000 /* 16 ... 31 */
#define CONFIG_SYS_GPIO0_OSRL 0x40000500 /* 0 ... 15 */
#define CONFIG_SYS_GPIO0_OSRH 0x00000110 /* 16 ... 31 */
#define CONFIG_SYS_GPIO0_ISR1L 0x00000000 /* 0 ... 15 */
#define CONFIG_SYS_GPIO0_ISR1H 0x14000045 /* 16 ... 31 */
#define CONFIG_SYS_GPIO0_TSRL 0x00000000 /* 0 ... 15 */
#define CONFIG_SYS_GPIO0_TSRH 0x00000000 /* 16 ... 31 */
#define CONFIG_SYS_GPIO0_TCR 0xF7FE0014 /* 0 ... 31 */
#define CONFIG_SYS_EEPROM_WP (0x80000000 >> 8) /* GPIO8 */

12
include/configs/DP405.h
View File

@@ -243,12 +243,12 @@
/* GPIO Output: OSR=00, ISR=00, TSR=00, TCR=1 */
/* Alt. Funtion Input: OSR=00, ISR=01, TSR=00, TCR=0 */
/* Alt. Funtion Output: OSR=01, ISR=00, TSR=00, TCR=1 */
#define CONFIG_SYS_GPIO0_OSRH 0x40000540 /* 0 ... 15 */
#define CONFIG_SYS_GPIO0_OSRL 0x00000110 /* 16 ... 31 */
#define CONFIG_SYS_GPIO0_ISR1H 0x00000000 /* 0 ... 15 */
#define CONFIG_SYS_GPIO0_ISR1L 0x14000045 /* 16 ... 31 */
#define CONFIG_SYS_GPIO0_TSRH 0x00000000 /* 0 ... 15 */
#define CONFIG_SYS_GPIO0_TSRL 0x00000000 /* 16 ... 31 */
#define CONFIG_SYS_GPIO0_OSRL 0x40000540 /* 0 ... 15 */
#define CONFIG_SYS_GPIO0_OSRH 0x00000110 /* 16 ... 31 */
#define CONFIG_SYS_GPIO0_ISR1L 0x00000000 /* 0 ... 15 */
#define CONFIG_SYS_GPIO0_ISR1H 0x14000045 /* 16 ... 31 */
#define CONFIG_SYS_GPIO0_TSRL 0x00000000 /* 0 ... 15 */
#define CONFIG_SYS_GPIO0_TSRH 0x00000000 /* 16 ... 31 */
#define CONFIG_SYS_GPIO0_TCR 0xB7FE0014 /* 0 ... 31 */
/*

10
include/configs/G2000.h
View File

@@ -367,12 +367,12 @@
*
* following GPIO setting changed for G20000, 080304
*/
#define CONFIG_SYS_GPIO0_OSRH 0x40005555
#define CONFIG_SYS_GPIO0_OSRL 0x40000110
#define CONFIG_SYS_GPIO0_ISR1H 0x00000000
#define CONFIG_SYS_GPIO0_ISR1L 0x15555445
#define CONFIG_SYS_GPIO0_TSRH 0x00000000
#define CONFIG_SYS_GPIO0_OSRL 0x40005555
#define CONFIG_SYS_GPIO0_OSRH 0x40000110
#define CONFIG_SYS_GPIO0_ISR1L 0x00000000
#define CONFIG_SYS_GPIO0_ISR1H 0x15555445
#define CONFIG_SYS_GPIO0_TSRL 0x00000000
#define CONFIG_SYS_GPIO0_TSRH 0x00000000
#define CONFIG_SYS_GPIO0_TCR 0xF7FF8014
/*

10
include/configs/HH405.h
View File

@@ -461,12 +461,12 @@
* GPIO0[28-29] - UART1 data signal input/output
* GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
*/
#define CONFIG_SYS_GPIO0_OSRH 0x40000550
#define CONFIG_SYS_GPIO0_OSRL 0x00000110
#define CONFIG_SYS_GPIO0_ISR1H 0x00000000
#define CONFIG_SYS_GPIO0_ISR1L 0x15555440
#define CONFIG_SYS_GPIO0_TSRH 0x00000000
#define CONFIG_SYS_GPIO0_OSRL 0x40000550
#define CONFIG_SYS_GPIO0_OSRH 0x00000110
#define CONFIG_SYS_GPIO0_ISR1L 0x00000000
#define CONFIG_SYS_GPIO0_ISR1H 0x15555440
#define CONFIG_SYS_GPIO0_TSRL 0x00000000
#define CONFIG_SYS_GPIO0_TSRH 0x00000000
#define CONFIG_SYS_GPIO0_TCR 0xF7FE0017
#define CONFIG_SYS_LCD_ENDIAN (0x80000000 >> 7)

10
include/configs/HUB405.h
View File

@@ -334,12 +334,12 @@
* GPIO0[28-29] - UART1 data signal input/output
* GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
*/
#define CONFIG_SYS_GPIO0_OSRH 0x40000550
#define CONFIG_SYS_GPIO0_OSRL 0x00000110
#define CONFIG_SYS_GPIO0_ISR1H 0x00000000
#define CONFIG_SYS_GPIO0_ISR1L 0x15555445
#define CONFIG_SYS_GPIO0_TSRH 0x00000000
#define CONFIG_SYS_GPIO0_OSRL 0x40000550
#define CONFIG_SYS_GPIO0_OSRH 0x00000110
#define CONFIG_SYS_GPIO0_ISR1L 0x00000000
#define CONFIG_SYS_GPIO0_ISR1H 0x15555445
#define CONFIG_SYS_GPIO0_TSRL 0x00000000
#define CONFIG_SYS_GPIO0_TSRH 0x00000000
#define CONFIG_SYS_GPIO0_TCR 0xF7FE0014
#define CONFIG_SYS_DUART_RST (0x80000000 >> 14)

10
include/configs/PLU405.h
View File

@@ -379,12 +379,12 @@
* GPIO0[28-29] - UART1 data signal input/output
* GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
*/
#define CONFIG_SYS_GPIO0_OSRH 0x00000550
#define CONFIG_SYS_GPIO0_OSRL 0x00000110
#define CONFIG_SYS_GPIO0_ISR1H 0x00000000
#define CONFIG_SYS_GPIO0_ISR1L 0x15555445
#define CONFIG_SYS_GPIO0_TSRH 0x00000000
#define CONFIG_SYS_GPIO0_OSRL 0x00000550
#define CONFIG_SYS_GPIO0_OSRH 0x00000110
#define CONFIG_SYS_GPIO0_ISR1L 0x00000000
#define CONFIG_SYS_GPIO0_ISR1H 0x15555445
#define CONFIG_SYS_GPIO0_TSRL 0x00000000
#define CONFIG_SYS_GPIO0_TSRH 0x00000000
#define CONFIG_SYS_GPIO0_TCR 0x77FE0014
#define CONFIG_SYS_DUART_RST (0x80000000 >> 14)

12
include/configs/PPChameleonEVB.h
View File

@@ -542,13 +542,13 @@
* GPIO0[30] - EMAC0 input
* GPIO0[31] - EMAC1 reject packet as output
*/
#define CONFIG_SYS_GPIO0_OSRH 0x40000550
#define CONFIG_SYS_GPIO0_OSRL 0x00000110
#define CONFIG_SYS_GPIO0_ISR1H 0x00000000
/*#define CONFIG_SYS_GPIO0_ISR1L 0x15555445*/
#define CONFIG_SYS_GPIO0_ISR1L 0x15555444
#define CONFIG_SYS_GPIO0_TSRH 0x00000000
#define CONFIG_SYS_GPIO0_OSRL 0x40000550
#define CONFIG_SYS_GPIO0_OSRH 0x00000110
#define CONFIG_SYS_GPIO0_ISR1L 0x00000000
/*#define CONFIG_SYS_GPIO0_ISR1H 0x15555445*/
#define CONFIG_SYS_GPIO0_ISR1H 0x15555444
#define CONFIG_SYS_GPIO0_TSRL 0x00000000
#define CONFIG_SYS_GPIO0_TSRH 0x00000000
#define CONFIG_SYS_GPIO0_TCR 0xF7FF8014
/*

10
include/configs/VOH405.h
View File

@@ -388,12 +388,12 @@
* GPIO0[28-29] - UART1 data signal input/output
* GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs -> GPIO
*/
#define CONFIG_SYS_GPIO0_OSRH 0x00000550
#define CONFIG_SYS_GPIO0_OSRL 0x00000110
#define CONFIG_SYS_GPIO0_ISR1H 0x00000000
#define CONFIG_SYS_GPIO0_ISR1L 0x15555440
#define CONFIG_SYS_GPIO0_TSRH 0x00000000
#define CONFIG_SYS_GPIO0_OSRL 0x00000550
#define CONFIG_SYS_GPIO0_OSRH 0x00000110
#define CONFIG_SYS_GPIO0_ISR1L 0x00000000
#define CONFIG_SYS_GPIO0_ISR1H 0x15555440
#define CONFIG_SYS_GPIO0_TSRL 0x00000000
#define CONFIG_SYS_GPIO0_TSRH 0x00000000
#define CONFIG_SYS_GPIO0_TCR 0x777E0017
#define CONFIG_SYS_DUART_RST (0x80000000 >> 14)

12
include/configs/VOM405.h
View File

@@ -273,12 +273,12 @@
/* GPIO Output: OSR=00, ISR=00, TSR=00, TCR=1 */
/* Alt. Funtion Input: OSR=00, ISR=01, TSR=00, TCR=0 */
/* Alt. Funtion Output: OSR=01, ISR=00, TSR=00, TCR=1 */
#define CONFIG_SYS_GPIO0_OSRH 0x40000500 /* 0 ... 15 */
#define CONFIG_SYS_GPIO0_OSRL 0x00000110 /* 16 ... 31 */
#define CONFIG_SYS_GPIO0_ISR1H 0x00000000 /* 0 ... 15 */
#define CONFIG_SYS_GPIO0_ISR1L 0x14000045 /* 16 ... 31 */
#define CONFIG_SYS_GPIO0_TSRH 0x00000000 /* 0 ... 15 */
#define CONFIG_SYS_GPIO0_TSRL 0x00000000 /* 16 ... 31 */
#define CONFIG_SYS_GPIO0_OSRL 0x40000500 /* 0 ... 15 */
#define CONFIG_SYS_GPIO0_OSRH 0x00000110 /* 16 ... 31 */
#define CONFIG_SYS_GPIO0_ISR1L 0x00000000 /* 0 ... 15 */
#define CONFIG_SYS_GPIO0_ISR1H 0x14000045 /* 16 ... 31 */
#define CONFIG_SYS_GPIO0_TSRL 0x00000000 /* 0 ... 15 */
#define CONFIG_SYS_GPIO0_TSRH 0x00000000 /* 16 ... 31 */
#define CONFIG_SYS_GPIO0_TCR 0xF7FE0014 /* 0 ... 31 */
/*

10
include/configs/WUH405.h
View File

@@ -332,12 +332,12 @@
* GPIO0[28-29] - UART1 data signal input/output
* GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
*/
#define CONFIG_SYS_GPIO0_OSRH 0x40000550
#define CONFIG_SYS_GPIO0_OSRL 0x00000110
#define CONFIG_SYS_GPIO0_ISR1H 0x00000000
#define CONFIG_SYS_GPIO0_ISR1L 0x15555445
#define CONFIG_SYS_GPIO0_TSRH 0x00000000
#define CONFIG_SYS_GPIO0_OSRL 0x40000550
#define CONFIG_SYS_GPIO0_OSRH 0x00000110
#define CONFIG_SYS_GPIO0_ISR1L 0x00000000
#define CONFIG_SYS_GPIO0_ISR1H 0x15555445
#define CONFIG_SYS_GPIO0_TSRL 0x00000000
#define CONFIG_SYS_GPIO0_TSRH 0x00000000
#define CONFIG_SYS_GPIO0_TCR 0xF7FE0014
#define CONFIG_SYS_DUART_RST (0x80000000 >> 14)

10
include/configs/bubinga.h
View File

@@ -284,12 +284,12 @@
* GPIO0[28-29] - UART1 data signal input/output
* GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
*/
#define CONFIG_SYS_GPIO0_OSRH 0x55555555
#define CONFIG_SYS_GPIO0_OSRL 0x40000110
#define CONFIG_SYS_GPIO0_ISR1H 0x00000000
#define CONFIG_SYS_GPIO0_ISR1L 0x15555445
#define CONFIG_SYS_GPIO0_TSRH 0x00000000
#define CONFIG_SYS_GPIO0_OSRL 0x55555555
#define CONFIG_SYS_GPIO0_OSRH 0x40000110
#define CONFIG_SYS_GPIO0_ISR1L 0x00000000
#define CONFIG_SYS_GPIO0_ISR1H 0x15555445
#define CONFIG_SYS_GPIO0_TSRL 0x00000000
#define CONFIG_SYS_GPIO0_TSRH 0x00000000
#define CONFIG_SYS_GPIO0_TCR 0xFFFF8014
/*-----------------------------------------------------------------------

10
include/configs/quad100hd.h
View File

@@ -270,12 +270,12 @@
* Taken in part from PPCBoot board/icecube/icecube.h
*/
/* see ./arch/powerpc/cpu/ppc4xx/cpu_init.c ./cpu/ppc4xx/start.S */
#define CONFIG_SYS_GPIO0_OSRH 0x55555550
#define CONFIG_SYS_GPIO0_OSRL 0x00000110
#define CONFIG_SYS_GPIO0_ISR1H 0x00000000
#define CONFIG_SYS_GPIO0_ISR1L 0x15555445
#define CONFIG_SYS_GPIO0_TSRH 0x00000000
#define CONFIG_SYS_GPIO0_OSRL 0x55555550
#define CONFIG_SYS_GPIO0_OSRH 0x00000110
#define CONFIG_SYS_GPIO0_ISR1L 0x00000000
#define CONFIG_SYS_GPIO0_ISR1H 0x15555445
#define CONFIG_SYS_GPIO0_TSRL 0x00000000
#define CONFIG_SYS_GPIO0_TSRH 0x00000000
#define CONFIG_SYS_GPIO0_TCR 0xFFFF8097
#define CONFIG_SYS_GPIO0_ODR 0x00000000

10
include/configs/zeus.h
View File

@@ -279,12 +279,12 @@
* GPIO0[28-29] - UART1 data signal input/output
* GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
*/
#define CONFIG_SYS_GPIO0_OSRH 0x15555550 /* Chip selects */
#define CONFIG_SYS_GPIO0_OSRL 0x00000110 /* UART_DTR-pin 27 alt out */
#define CONFIG_SYS_GPIO0_ISR1H 0x10000041 /* Pin 2, 12 is input */
#define CONFIG_SYS_GPIO0_ISR1L 0x15505440 /* OUT: LEDs 22/23; IN: pin12,2, NVALID# */
#define CONFIG_SYS_GPIO0_TSRH 0x00000000
#define CONFIG_SYS_GPIO0_OSRL 0x15555550 /* Chip selects */
#define CONFIG_SYS_GPIO0_OSRH 0x00000110 /* UART_DTR-pin 27 alt out */
#define CONFIG_SYS_GPIO0_ISR1L 0x10000041 /* Pin 2, 12 is input */
#define CONFIG_SYS_GPIO0_ISR1H 0x15505440 /* OUT: LEDs 22/23; IN: pin12,2, NVALID# */
#define CONFIG_SYS_GPIO0_TSRL 0x00000000
#define CONFIG_SYS_GPIO0_TSRH 0x00000000
#define CONFIG_SYS_GPIO0_TCR 0xBFF68317 /* 3-state OUT: 22/23/29; 12,2 is not 3-state */
#define CONFIG_SYS_GPIO0_ODR 0x00000000