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pci/layerscape: add support for LS1043A PCIe LUT register access

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The endian and base address of PEX LUT register region is different
between Chassis 2 and Chassis 3, so move the base address definition
to chassis specific header file and add pex_lut_* functions to access
LUT register.

Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
This commit is contained in:
Mingkai Hu
2015-11-11 17:58:34 +08:00
committed by York Sun
parent 06b5301043
commit af523a0d56
5 changed files with 25 additions and 7 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm/include/asm/arch-fsl-layerscape/config.h
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@@ -50,6 +50,7 @@
#define CONFIG_SYS_FSL_CCSR_SCFG_LE
#define CONFIG_SYS_FSL_ESDHC_LE
#define CONFIG_SYS_FSL_IFC_LE
#define CONFIG_SYS_FSL_PEX_LUT_LE
#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
@@ -119,6 +120,7 @@
#define CONFIG_SYS_FSL_WDOG_BE
#define CONFIG_SYS_FSL_DSPI_BE
#define CONFIG_SYS_FSL_QSPI_BE
#define CONFIG_SYS_FSL_PEX_LUT_BE
#define QE_MURAM_SIZE 0x6000UL
#define MAX_QE_RISC 1

4
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
View File

@@ -60,6 +60,10 @@
#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x4000000000ULL
#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x4800000000ULL
#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x5000000000ULL
/* LUT registers */
#define PCIE_LUT_BASE 0x10000
#define PCIE_LUT_LCTRL0 0x7F8
#define PCIE_LUT_DBG 0x7FC
/* TZ Address Space Controller Definitions */
#define TZASC1_BASE 0x01100000 /* as per CCSR map. */

4
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
View File

@@ -78,6 +78,10 @@
#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x1200000000ULL
#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x1400000000ULL
#define CONFIG_SYS_PCIE4_PHYS_ADDR 0x1600000000ULL
/* LUT registers */
#define PCIE_LUT_BASE 0x80000
#define PCIE_LUT_LCTRL0 0x7F8
#define PCIE_LUT_DBG 0x7FC
/* Device Configuration */
#define DCFG_BASE 0x01e00000

8
arch/arm/include/asm/arch-fsl-layerscape/soc.h
View File

@@ -23,6 +23,14 @@
#define scfg_out32(a, v) out_be32(a, v)
#endif
#ifdef CONFIG_SYS_FSL_PEX_LUT_LE
#define pex_lut_in32(a) in_le32(a)
#define pex_lut_out32(a, v) out_le32(a, v)
#elif defined(CONFIG_SYS_FSL_PEX_LUT_BE)
#define pex_lut_in32(a) in_be32(a)
#define pex_lut_out32(a, v) out_be32(a, v)
#endif
struct cpu_type {
char name[15];
u32 soc_ver;