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Merge branch 'phylib' of git://git.denx.de/u-boot-mmc

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This commit is contained in:
Wolfgang Denk
2011-04-20 23:01:52 +02:00
parent 9dd5dad887 995daa0b81
commit aef293bc85
52 changed files with 5085 additions and 2505 deletions
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32
include/config_phylib_all_drivers.h Normal file
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@@ -0,0 +1,32 @@
/*
* Enable all PHYs
*
* This software may be used and distributed according to the
* terms of the GNU Public License, Version 2, incorporated
* herein by reference.
*
* Copyright 2011 Freescale Semiconductor, Inc.
* author Andy Fleming
*
*/
#ifndef _CONFIG_PHYLIB_ALL_H
#define _CONFIG_PHYLIB_ALL_H
#ifdef CONFIG_PHYLIB
#define CONFIG_PHY_VITESSE
#define CONFIG_PHY_MARVELL
#define CONFIG_PHY_MICREL
#define CONFIG_PHY_BROADCOM
#define CONFIG_PHY_DAVICOM
#define CONFIG_PHY_REALTEK
#define CONFIG_PHY_NATSEMI
#define CONFIG_PHY_LXT
#ifdef CONFIG_PHYLIB_10G
#define CONFIG_PHY_TERANETICS
#endif /* CONFIG_PHYLIB_10G */
#endif /* CONFIG_PHYLIB */
#endif /*_CONFIG_PHYLIB_ALL_H */

4
include/configs/MPC8323ERDB.h
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@@ -348,7 +348,7 @@
#define CONFIG_SYS_UEC1_TX_CLK QE_CLK10
#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
#define CONFIG_SYS_UEC1_PHY_ADDR 4
#define CONFIG_SYS_UEC1_INTERFACE_TYPE MII
#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
#endif
@@ -360,7 +360,7 @@
#define CONFIG_SYS_UEC2_TX_CLK QE_CLK3
#define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH
#define CONFIG_SYS_UEC2_PHY_ADDR 0
#define CONFIG_SYS_UEC2_INTERFACE_TYPE MII
#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
#define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
#endif

4
include/configs/MPC832XEMDS.h
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@@ -361,7 +361,7 @@
#define CONFIG_SYS_UEC1_TX_CLK QE_CLK10
#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
#define CONFIG_SYS_UEC1_PHY_ADDR 3
#define CONFIG_SYS_UEC1_INTERFACE_TYPE MII
#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
#endif
@@ -373,7 +373,7 @@
#define CONFIG_SYS_UEC2_TX_CLK QE_CLK8
#define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH
#define CONFIG_SYS_UEC2_PHY_ADDR 4
#define CONFIG_SYS_UEC2_INTERFACE_TYPE MII
#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
#define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
#endif

4
include/configs/MPC8360EMDS.h
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@@ -402,7 +402,7 @@
#define CONFIG_SYS_UEC1_TX_CLK QE_CLK9
#define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH
#define CONFIG_SYS_UEC1_PHY_ADDR 0
#define CONFIG_SYS_UEC1_INTERFACE_TYPE RGMII_ID
#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
#define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000
#endif
@@ -414,7 +414,7 @@
#define CONFIG_SYS_UEC2_TX_CLK QE_CLK4
#define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH
#define CONFIG_SYS_UEC2_PHY_ADDR 1
#define CONFIG_SYS_UEC2_INTERFACE_TYPE RGMII_ID
#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
#define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
#endif

4
include/configs/MPC8360ERDK.h
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@@ -319,7 +319,7 @@
#define CONFIG_SYS_UEC1_TX_CLK QE_CLK9
#define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH
#define CONFIG_SYS_UEC1_PHY_ADDR 2
#define CONFIG_SYS_UEC1_INTERFACE_TYPE RGMII_RXID
#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_RXID
#define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000
#endif
@@ -331,7 +331,7 @@
#define CONFIG_SYS_UEC2_TX_CLK QE_CLK4
#define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH
#define CONFIG_SYS_UEC2_PHY_ADDR 4
#define CONFIG_SYS_UEC2_INTERFACE_TYPE RGMII_RXID
#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_RXID
#define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
#endif

4
include/configs/MPC8568MDS.h
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@@ -334,7 +334,7 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_SYS_UEC1_TX_CLK QE_CLK16
#define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH
#define CONFIG_SYS_UEC1_PHY_ADDR 7
#define CONFIG_SYS_UEC1_INTERFACE_TYPE RGMII_ID
#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
#define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000
#endif
@@ -346,7 +346,7 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_SYS_UEC2_TX_CLK QE_CLK16
#define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH
#define CONFIG_SYS_UEC2_PHY_ADDR 1
#define CONFIG_SYS_UEC2_INTERFACE_TYPE RGMII_ID
#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
#define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
#endif
#endif /* CONFIG_QE */

20
include/configs/MPC8569MDS.h
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@@ -385,13 +385,13 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_SYS_UEC1_TX_CLK QE_CLK12
#define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH
#define CONFIG_SYS_UEC1_PHY_ADDR 7
#define CONFIG_SYS_UEC1_INTERFACE_TYPE RGMII_ID
#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
#define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000
#elif defined(CONFIG_SYS_UCC_RMII_MODE)
#define CONFIG_SYS_UEC1_TX_CLK QE_CLK16 /* CLK16 for RMII */
#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
#define CONFIG_SYS_UEC1_PHY_ADDR 8 /* 0x8 for RMII */
#define CONFIG_SYS_UEC1_INTERFACE_TYPE RMII
#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
#endif /* CONFIG_SYS_UCC_RGMII_MODE */
#endif /* CONFIG_UEC_ETH1 */
@@ -406,13 +406,13 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_SYS_UEC2_TX_CLK QE_CLK17
#define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH
#define CONFIG_SYS_UEC2_PHY_ADDR 1
#define CONFIG_SYS_UEC2_INTERFACE_TYPE RGMII_ID
#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
#define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
#elif defined(CONFIG_SYS_UCC_RMII_MODE)
#define CONFIG_SYS_UEC2_TX_CLK QE_CLK16 /* CLK 16 for RMII */
#define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH
#define CONFIG_SYS_UEC2_PHY_ADDR 0x9 /* 0x9 for RMII */
#define CONFIG_SYS_UEC2_INTERFACE_TYPE RMII
#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
#define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
#endif /* CONFIG_SYS_UCC_RGMII_MODE */
#endif /* CONFIG_UEC_ETH2 */
@@ -427,13 +427,13 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_SYS_UEC3_TX_CLK QE_CLK12
#define CONFIG_SYS_UEC3_ETH_TYPE GIGA_ETH
#define CONFIG_SYS_UEC3_PHY_ADDR 2
#define CONFIG_SYS_UEC3_INTERFACE_TYPE RGMII_ID
#define CONFIG_SYS_UEC3_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
#define CONFIG_SYS_UEC3_INTERFACE_SPEED 1000
#elif defined(CONFIG_SYS_UCC_RMII_MODE)
#define CONFIG_SYS_UEC3_TX_CLK QE_CLK16 /* CLK_16 for RMII */
#define CONFIG_SYS_UEC3_ETH_TYPE FAST_ETH
#define CONFIG_SYS_UEC3_PHY_ADDR 0xA /* 0xA for RMII */
#define CONFIG_SYS_UEC3_INTERFACE_TYPE RMII
#define CONFIG_SYS_UEC3_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
#define CONFIG_SYS_UEC3_INTERFACE_SPEED 100
#endif /* CONFIG_SYS_UCC_RGMII_MODE */
#endif /* CONFIG_UEC_ETH3 */
@@ -448,13 +448,13 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_SYS_UEC4_TX_CLK QE_CLK17
#define CONFIG_SYS_UEC4_ETH_TYPE GIGA_ETH
#define CONFIG_SYS_UEC4_PHY_ADDR 3
#define CONFIG_SYS_UEC4_INTERFACE_TYPE RGMII_ID
#define CONFIG_SYS_UEC4_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
#define CONFIG_SYS_UEC4_INTERFACE_SPEED 1000
#elif defined(CONFIG_SYS_UCC_RMII_MODE)
#define CONFIG_SYS_UEC4_TX_CLK QE_CLK16 /* CLK16 for RMII */
#define CONFIG_SYS_UEC4_ETH_TYPE FAST_ETH
#define CONFIG_SYS_UEC4_PHY_ADDR 0xB /* 0xB for RMII */
#define CONFIG_SYS_UEC4_INTERFACE_TYPE RMII
#define CONFIG_SYS_UEC4_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
#define CONFIG_SYS_UEC4_INTERFACE_SPEED 100
#endif /* CONFIG_SYS_UCC_RGMII_MODE */
#endif /* CONFIG_UEC_ETH4 */
@@ -468,7 +468,7 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_SYS_UEC6_TX_CLK QE_CLK_NONE
#define CONFIG_SYS_UEC6_ETH_TYPE GIGA_ETH
#define CONFIG_SYS_UEC6_PHY_ADDR 4
#define CONFIG_SYS_UEC6_INTERFACE_TYPE SGMII
#define CONFIG_SYS_UEC6_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII
#define CONFIG_SYS_UEC6_INTERFACE_SPEED 1000
#endif /* CONFIG_UEC_ETH6 */
@@ -481,7 +481,7 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_SYS_UEC8_TX_CLK QE_CLK_NONE
#define CONFIG_SYS_UEC8_ETH_TYPE GIGA_ETH
#define CONFIG_SYS_UEC8_PHY_ADDR 6
#define CONFIG_SYS_UEC8_INTERFACE_TYPE SGMII
#define CONFIG_SYS_UEC8_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII
#define CONFIG_SYS_UEC8_INTERFACE_SPEED 1000
#endif /* CONFIG_UEC_ETH8 */

2
include/configs/kmeter1.h
View File

@@ -295,7 +295,7 @@
#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17
#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
#define CONFIG_SYS_UEC1_PHY_ADDR 0
#define CONFIG_SYS_UEC1_INTERFACE_TYPE RMII
#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
#endif

62
include/fsl_mdio.h Normal file
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@@ -0,0 +1,62 @@
/*
* Copyright 2009-2010 Freescale Semiconductor, Inc.
* Jun-jie Zhang <b18070@freescale.com>
* Mingkai Hu <Mingkai.hu@freescale.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __FSL_PHY_H__
#define __FSL_PHY_H__
#include <net.h>
#include <miiphy.h>
#include <asm/fsl_enet.h>
/* PHY register offsets */
#define PHY_EXT_PAGE_ACCESS 0x1f
/* MII Management Configuration Register */
#define MIIMCFG_RESET_MGMT 0x80000000
#define MIIMCFG_MGMT_CLOCK_SELECT 0x00000007
#define MIIMCFG_INIT_VALUE 0x00000003
/* MII Management Command Register */
#define MIIMCOM_READ_CYCLE 0x00000001
#define MIIMCOM_SCAN_CYCLE 0x00000002
/* MII Management Address Register */
#define MIIMADD_PHY_ADDR_SHIFT 8
/* MII Management Indicator Register */
#define MIIMIND_BUSY 0x00000001
#define MIIMIND_NOTVALID 0x00000004
void tsec_local_mdio_write(struct tsec_mii_mng *phyregs, int port_addr,
int dev_addr, int reg, int value);
int tsec_local_mdio_read(struct tsec_mii_mng *phyregs, int port_addr,
int dev_addr, int regnum);
int tsec_phy_read(struct mii_dev *bus, int addr, int dev_addr, int regnum);
int tsec_phy_write(struct mii_dev *bus, int addr, int dev_addr, int regnum,
u16 value);
struct fsl_pq_mdio_info {
struct tsec_mii_mng *regs;
char *name;
};
int fsl_pq_mdio_init(bd_t *bis, struct fsl_pq_mdio_info *info);
#endif /* __FSL_PHY_H__ */

721
include/linux/ethtool.h Normal file
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@@ -0,0 +1,721 @@
/*
* ethtool.h: Defines for Linux ethtool.
*
* Copyright (C) 1998 David S. Miller (davem@redhat.com)
* Copyright 2001 Jeff Garzik <jgarzik@pobox.com>
* Portions Copyright 2001 Sun Microsystems (thockin@sun.com)
* Portions Copyright 2002 Intel (eli.kupermann@intel.com,
* christopher.leech@intel.com,
* scott.feldman@intel.com)
* Portions Copyright (C) Sun Microsystems 2008
*/
#ifndef _LINUX_ETHTOOL_H
#define _LINUX_ETHTOOL_H
#include <linux/types.h>
/* This should work for both 32 and 64 bit userland. */
struct ethtool_cmd {
__u32 cmd;
__u32 supported; /* Features this interface supports */
__u32 advertising; /* Features this interface advertises */
__u16 speed; /* The forced speed, 10Mb, 100Mb, gigabit */
__u8 duplex; /* Duplex, half or full */
__u8 port; /* Which connector port */
__u8 phy_address;
__u8 transceiver; /* Which transceiver to use */
__u8 autoneg; /* Enable or disable autonegotiation */
__u8 mdio_support;
__u32 maxtxpkt; /* Tx pkts before generating tx int */
__u32 maxrxpkt; /* Rx pkts before generating rx int */
__u16 speed_hi;
__u8 eth_tp_mdix;
__u8 reserved2;
__u32 lp_advertising; /* Features the link partner advertises */
__u32 reserved[2];
};
static inline void ethtool_cmd_speed_set(struct ethtool_cmd *ep,
__u32 speed)
{
ep->speed = (__u16)speed;
ep->speed_hi = (__u16)(speed >> 16);
}
static inline __u32 ethtool_cmd_speed(struct ethtool_cmd *ep)
{
return (ep->speed_hi << 16) | ep->speed;
}
#define ETHTOOL_FWVERS_LEN 32
#define ETHTOOL_BUSINFO_LEN 32
/* these strings are set to whatever the driver author decides... */
struct ethtool_drvinfo {
__u32 cmd;
char driver[32]; /* driver short name, "tulip", "eepro100" */
char version[32]; /* driver version string */
char fw_version[ETHTOOL_FWVERS_LEN]; /* firmware version string */
char bus_info[ETHTOOL_BUSINFO_LEN]; /* Bus info for this IF. */
/* For PCI devices, use pci_name(pci_dev). */
char reserved1[32];
char reserved2[12];
/*
* Some struct members below are filled in
* using ops->get_sset_count(). Obtaining
* this info from ethtool_drvinfo is now
* deprecated; Use ETHTOOL_GSSET_INFO
* instead.
*/
__u32 n_priv_flags; /* number of flags valid in ETHTOOL_GPFLAGS */
__u32 n_stats; /* number of u64's from ETHTOOL_GSTATS */
__u32 testinfo_len;
__u32 eedump_len; /* Size of data from ETHTOOL_GEEPROM (bytes) */
__u32 regdump_len; /* Size of data from ETHTOOL_GREGS (bytes) */
};
#define SOPASS_MAX 6
/* wake-on-lan settings */
struct ethtool_wolinfo {
__u32 cmd;
__u32 supported;
__u32 wolopts;
__u8 sopass[SOPASS_MAX]; /* SecureOn(tm) password */
};
/* for passing single values */
struct ethtool_value {
__u32 cmd;
__u32 data;
};
/* for passing big chunks of data */
struct ethtool_regs {
__u32 cmd;
__u32 version; /* driver-specific, indicates different chips/revs */
__u32 len; /* bytes */
__u8 data[0];
};
/* for passing EEPROM chunks */
struct ethtool_eeprom {
__u32 cmd;
__u32 magic;
__u32 offset; /* in bytes */
__u32 len; /* in bytes */
__u8 data[0];
};
/* for configuring coalescing parameters of chip */
struct ethtool_coalesce {
__u32 cmd; /* ETHTOOL_{G,S}COALESCE */
/* How many usecs to delay an RX interrupt after
* a packet arrives. If 0, only rx_max_coalesced_frames
* is used.
*/
__u32 rx_coalesce_usecs;
/* How many packets to delay an RX interrupt after
* a packet arrives. If 0, only rx_coalesce_usecs is
* used. It is illegal to set both usecs and max frames
* to zero as this would cause RX interrupts to never be
* generated.
*/
__u32 rx_max_coalesced_frames;
/* Same as above two parameters, except that these values
* apply while an IRQ is being serviced by the host. Not
* all cards support this feature and the values are ignored
* in that case.
*/
__u32 rx_coalesce_usecs_irq;
__u32 rx_max_coalesced_frames_irq;
/* How many usecs to delay a TX interrupt after
* a packet is sent. If 0, only tx_max_coalesced_frames
* is used.
*/
__u32 tx_coalesce_usecs;
/* How many packets to delay a TX interrupt after
* a packet is sent. If 0, only tx_coalesce_usecs is
* used. It is illegal to set both usecs and max frames
* to zero as this would cause TX interrupts to never be
* generated.
*/
__u32 tx_max_coalesced_frames;
/* Same as above two parameters, except that these values
* apply while an IRQ is being serviced by the host. Not
* all cards support this feature and the values are ignored
* in that case.
*/
__u32 tx_coalesce_usecs_irq;
__u32 tx_max_coalesced_frames_irq;
/* How many usecs to delay in-memory statistics
* block updates. Some drivers do not have an in-memory
* statistic block, and in such cases this value is ignored.
* This value must not be zero.
*/
__u32 stats_block_coalesce_usecs;
/* Adaptive RX/TX coalescing is an algorithm implemented by
* some drivers to improve latency under low packet rates and
* improve throughput under high packet rates. Some drivers
* only implement one of RX or TX adaptive coalescing. Anything
* not implemented by the driver causes these values to be
* silently ignored.
*/
__u32 use_adaptive_rx_coalesce;
__u32 use_adaptive_tx_coalesce;
/* When the packet rate (measured in packets per second)
* is below pkt_rate_low, the {rx,tx}_*_low parameters are
* used.
*/
__u32 pkt_rate_low;
__u32 rx_coalesce_usecs_low;
__u32 rx_max_coalesced_frames_low;
__u32 tx_coalesce_usecs_low;
__u32 tx_max_coalesced_frames_low;
/* When the packet rate is below pkt_rate_high but above
* pkt_rate_low (both measured in packets per second) the
* normal {rx,tx}_* coalescing parameters are used.
*/
/* When the packet rate is (measured in packets per second)
* is above pkt_rate_high, the {rx,tx}_*_high parameters are
* used.
*/
__u32 pkt_rate_high;
__u32 rx_coalesce_usecs_high;
__u32 rx_max_coalesced_frames_high;
__u32 tx_coalesce_usecs_high;
__u32 tx_max_coalesced_frames_high;
/* How often to do adaptive coalescing packet rate sampling,
* measured in seconds. Must not be zero.
*/
__u32 rate_sample_interval;
};
/* for configuring RX/TX ring parameters */
struct ethtool_ringparam {
__u32 cmd; /* ETHTOOL_{G,S}RINGPARAM */
/* Read only attributes. These indicate the maximum number
* of pending RX/TX ring entries the driver will allow the
* user to set.
*/
__u32 rx_max_pending;
__u32 rx_mini_max_pending;
__u32 rx_jumbo_max_pending;
__u32 tx_max_pending;
/* Values changeable by the user. The valid values are
* in the range 1 to the "*_max_pending" counterpart above.
*/
__u32 rx_pending;
__u32 rx_mini_pending;
__u32 rx_jumbo_pending;
__u32 tx_pending;
};
/* for configuring link flow control parameters */
struct ethtool_pauseparam {
__u32 cmd; /* ETHTOOL_{G,S}PAUSEPARAM */
/* If the link is being auto-negotiated (via ethtool_cmd.autoneg
* being true) the user may set 'autonet' here non-zero to have the
* pause parameters be auto-negotiated too. In such a case, the
* {rx,tx}_pause values below determine what capabilities are
* advertised.
*
* If 'autoneg' is zero or the link is not being auto-negotiated,
* then {rx,tx}_pause force the driver to use/not-use pause
* flow control.
*/
__u32 autoneg;
__u32 rx_pause;
__u32 tx_pause;
};
#define ETH_GSTRING_LEN 32
enum ethtool_stringset {
ETH_SS_TEST = 0,
ETH_SS_STATS,
ETH_SS_PRIV_FLAGS,
ETH_SS_NTUPLE_FILTERS,
ETH_SS_FEATURES,
};
/* for passing string sets for data tagging */
struct ethtool_gstrings {
__u32 cmd; /* ETHTOOL_GSTRINGS */
__u32 string_set; /* string set id e.c. ETH_SS_TEST, etc*/
__u32 len; /* number of strings in the string set */
__u8 data[0];
};
struct ethtool_sset_info {
__u32 cmd; /* ETHTOOL_GSSET_INFO */
__u32 reserved;
__u64 sset_mask; /* input: each bit selects an sset to query */
/* output: each bit a returned sset */
__u32 data[0]; /* ETH_SS_xxx count, in order, based on bits
in sset_mask. One bit implies one
__u32, two bits implies two
__u32's, etc. */
};
enum ethtool_test_flags {
ETH_TEST_FL_OFFLINE = (1 << 0), /* online / offline */
ETH_TEST_FL_FAILED = (1 << 1), /* test passed / failed */
};
/* for requesting NIC test and getting results*/
struct ethtool_test {
__u32 cmd; /* ETHTOOL_TEST */
__u32 flags; /* ETH_TEST_FL_xxx */
__u32 reserved;
__u32 len; /* result length, in number of u64 elements */
__u64 data[0];
};
/* for dumping NIC-specific statistics */
struct ethtool_stats {
__u32 cmd; /* ETHTOOL_GSTATS */
__u32 n_stats; /* number of u64's being returned */
__u64 data[0];
};
struct ethtool_perm_addr {
__u32 cmd; /* ETHTOOL_GPERMADDR */
__u32 size;
__u8 data[0];
};
/* boolean flags controlling per-interface behavior characteristics.
* When reading, the flag indicates whether or not a certain behavior
* is enabled/present. When writing, the flag indicates whether
* or not the driver should turn on (set) or off (clear) a behavior.
*
* Some behaviors may read-only (unconditionally absent or present).
* If such is the case, return EINVAL in the set-flags operation if the
* flag differs from the read-only value.
*/
enum ethtool_flags {
ETH_FLAG_TXVLAN = (1 << 7), /* TX VLAN offload enabled */
ETH_FLAG_RXVLAN = (1 << 8), /* RX VLAN offload enabled */
ETH_FLAG_LRO = (1 << 15), /* LRO is enabled */
ETH_FLAG_NTUPLE = (1 << 27), /* N-tuple filters enabled */
ETH_FLAG_RXHASH = (1 << 28),
};
/* The following structures are for supporting RX network flow
* classification and RX n-tuple configuration. Note, all multibyte
* fields, e.g., ip4src, ip4dst, psrc, pdst, spi, etc. are expected to
* be in network byte order.
*/
/**
* struct ethtool_tcpip4_spec - flow specification for TCP/IPv4 etc.
* @ip4src: Source host
* @ip4dst: Destination host
* @psrc: Source port
* @pdst: Destination port
* @tos: Type-of-service
*
* This can be used to specify a TCP/IPv4, UDP/IPv4 or SCTP/IPv4 flow.
*/
struct ethtool_tcpip4_spec {
__be32 ip4src;
__be32 ip4dst;
__be16 psrc;
__be16 pdst;
__u8 tos;
};
/**
* struct ethtool_ah_espip4_spec - flow specification for IPsec/IPv4
* @ip4src: Source host
* @ip4dst: Destination host
* @spi: Security parameters index
* @tos: Type-of-service
*
* This can be used to specify an IPsec transport or tunnel over IPv4.
*/
struct ethtool_ah_espip4_spec {
__be32 ip4src;
__be32 ip4dst;
__be32 spi;
__u8 tos;
};
#define ETH_RX_NFC_IP4 1
/**
* struct ethtool_usrip4_spec - general flow specification for IPv4
* @ip4src: Source host
* @ip4dst: Destination host
* @l4_4_bytes: First 4 bytes of transport (layer 4) header
* @tos: Type-of-service
* @ip_ver: Value must be %ETH_RX_NFC_IP4; mask must be 0
* @proto: Transport protocol number; mask must be 0
*/
struct ethtool_usrip4_spec {
__be32 ip4src;
__be32 ip4dst;
__be32 l4_4_bytes;
__u8 tos;
__u8 ip_ver;
__u8 proto;
};
/**
* struct ethtool_rxfh_indir - command to get or set RX flow hash indirection
* @cmd: Specific command number - %ETHTOOL_GRXFHINDIR or %ETHTOOL_SRXFHINDIR
* @size: On entry, the array size of the user buffer. On return from
* %ETHTOOL_GRXFHINDIR, the array size of the hardware indirection table.
* @ring_index: RX ring/queue index for each hash value
*/
struct ethtool_rxfh_indir {
__u32 cmd;
__u32 size;
__u32 ring_index[0];
};
#define ETHTOOL_FLASH_MAX_FILENAME 128
enum ethtool_flash_op_type {
ETHTOOL_FLASH_ALL_REGIONS = 0,
};
/* for passing firmware flashing related parameters */
struct ethtool_flash {
__u32 cmd;
__u32 region;
char data[ETHTOOL_FLASH_MAX_FILENAME];
};
/* for returning and changing feature sets */
/**
* struct ethtool_get_features_block - block with state of 32 features
* @available: mask of changeable features
* @requested: mask of features requested to be enabled if possible
* @active: mask of currently enabled features
* @never_changed: mask of features not changeable for any device
*/
struct ethtool_get_features_block {
__u32 available;
__u32 requested;
__u32 active;
__u32 never_changed;
};
/**
* struct ethtool_gfeatures - command to get state of device's features
* @cmd: command number = %ETHTOOL_GFEATURES
* @size: in: number of elements in the features[] array;
* out: number of elements in features[] needed to hold all features
* @features: state of features
*/
struct ethtool_gfeatures {
__u32 cmd;
__u32 size;
struct ethtool_get_features_block features[0];
};
/**
* struct ethtool_set_features_block - block with request for 32 features
* @valid: mask of features to be changed
* @requested: values of features to be changed
*/
struct ethtool_set_features_block {
__u32 valid;
__u32 requested;
};
/**
* struct ethtool_sfeatures - command to request change in device's features
* @cmd: command number = %ETHTOOL_SFEATURES
* @size: array size of the features[] array
* @features: feature change masks
*/
struct ethtool_sfeatures {
__u32 cmd;
__u32 size;
struct ethtool_set_features_block features[0];
};
/*
* %ETHTOOL_SFEATURES changes features present in features[].valid to the
* values of corresponding bits in features[].requested. Bits in .requested
* not set in .valid or not changeable are ignored.
*
* Returns %EINVAL when .valid contains undefined or never-changable bits
* or size is not equal to required number of features words (32-bit blocks).
* Returns >= 0 if request was completed; bits set in the value mean:
* %ETHTOOL_F_UNSUPPORTED - there were bits set in .valid that are not
* changeable (not present in %ETHTOOL_GFEATURES' features[].available)
* those bits were ignored.
* %ETHTOOL_F_WISH - some or all changes requested were recorded but the
* resulting state of bits masked by .valid is not equal to .requested.
* Probably there are other device-specific constraints on some features
* in the set. When %ETHTOOL_F_UNSUPPORTED is set, .valid is considered
* here as though ignored bits were cleared.
* %ETHTOOL_F_COMPAT - some or all changes requested were made by calling
* compatibility functions. Requested offload state cannot be properly
* managed by kernel.
*
* Meaning of bits in the masks are obtained by %ETHTOOL_GSSET_INFO (number of
* bits in the arrays - always multiple of 32) and %ETHTOOL_GSTRINGS commands
* for ETH_SS_FEATURES string set. First entry in the table corresponds to least
* significant bit in features[0] fields. Empty strings mark undefined features.
*/
enum ethtool_sfeatures_retval_bits {
ETHTOOL_F_UNSUPPORTED__BIT,
ETHTOOL_F_WISH__BIT,
ETHTOOL_F_COMPAT__BIT,
};
#define ETHTOOL_F_UNSUPPORTED (1 << ETHTOOL_F_UNSUPPORTED__BIT)
#define ETHTOOL_F_WISH (1 << ETHTOOL_F_WISH__BIT)
#define ETHTOOL_F_COMPAT (1 << ETHTOOL_F_COMPAT__BIT)
/* CMDs currently supported */
#define ETHTOOL_GSET 0x00000001 /* Get settings. */
#define ETHTOOL_SSET 0x00000002 /* Set settings. */
#define ETHTOOL_GDRVINFO 0x00000003 /* Get driver info. */
#define ETHTOOL_GREGS 0x00000004 /* Get NIC registers. */
#define ETHTOOL_GWOL 0x00000005 /* Get wake-on-lan options. */
#define ETHTOOL_SWOL 0x00000006 /* Set wake-on-lan options. */
#define ETHTOOL_GMSGLVL 0x00000007 /* Get driver message level */
#define ETHTOOL_SMSGLVL 0x00000008 /* Set driver msg level. */
#define ETHTOOL_NWAY_RST 0x00000009 /* Restart autonegotiation. */
/* Get link status for host, i.e. whether the interface *and* the
* physical port (if there is one) are up (ethtool_value). */
#define ETHTOOL_GLINK 0x0000000a
#define ETHTOOL_GEEPROM 0x0000000b /* Get EEPROM data */
#define ETHTOOL_SEEPROM 0x0000000c /* Set EEPROM data. */
#define ETHTOOL_GCOALESCE 0x0000000e /* Get coalesce config */
#define ETHTOOL_SCOALESCE 0x0000000f /* Set coalesce config. */
#define ETHTOOL_GRINGPARAM 0x00000010 /* Get ring parameters */
#define ETHTOOL_SRINGPARAM 0x00000011 /* Set ring parameters. */
#define ETHTOOL_GPAUSEPARAM 0x00000012 /* Get pause parameters */
#define ETHTOOL_SPAUSEPARAM 0x00000013 /* Set pause parameters. */
#define ETHTOOL_GRXCSUM 0x00000014 /* Get RX hw csum enable (ethtool_value) */
#define ETHTOOL_SRXCSUM 0x00000015 /* Set RX hw csum enable (ethtool_value) */
#define ETHTOOL_GTXCSUM 0x00000016 /* Get TX hw csum enable (ethtool_value) */
#define ETHTOOL_STXCSUM 0x00000017 /* Set TX hw csum enable (ethtool_value) */
#define ETHTOOL_GSG 0x00000018 /* Get scatter-gather enable
* (ethtool_value) */
#define ETHTOOL_SSG 0x00000019 /* Set scatter-gather enable
* (ethtool_value). */
#define ETHTOOL_TEST 0x0000001a /* execute NIC self-test. */
#define ETHTOOL_GSTRINGS 0x0000001b /* get specified string set */
#define ETHTOOL_PHYS_ID 0x0000001c /* identify the NIC */
#define ETHTOOL_GSTATS 0x0000001d /* get NIC-specific statistics */
#define ETHTOOL_GTSO 0x0000001e /* Get TSO enable (ethtool_value) */
#define ETHTOOL_STSO 0x0000001f /* Set TSO enable (ethtool_value) */
#define ETHTOOL_GPERMADDR 0x00000020 /* Get permanent hardware address */
#define ETHTOOL_GUFO 0x00000021 /* Get UFO enable (ethtool_value) */
#define ETHTOOL_SUFO 0x00000022 /* Set UFO enable (ethtool_value) */
#define ETHTOOL_GGSO 0x00000023 /* Get GSO enable (ethtool_value) */
#define ETHTOOL_SGSO 0x00000024 /* Set GSO enable (ethtool_value) */
#define ETHTOOL_GFLAGS 0x00000025 /* Get flags bitmap(ethtool_value) */
#define ETHTOOL_SFLAGS 0x00000026 /* Set flags bitmap(ethtool_value) */
#define ETHTOOL_GPFLAGS 0x00000027 /* Get driver-private flags bitmap */
#define ETHTOOL_SPFLAGS 0x00000028 /* Set driver-private flags bitmap */
#define ETHTOOL_GRXFH 0x00000029 /* Get RX flow hash configuration */
#define ETHTOOL_SRXFH 0x0000002a /* Set RX flow hash configuration */
#define ETHTOOL_GGRO 0x0000002b /* Get GRO enable (ethtool_value) */
#define ETHTOOL_SGRO 0x0000002c /* Set GRO enable (ethtool_value) */
#define ETHTOOL_GRXRINGS 0x0000002d /* Get RX rings available for LB */
#define ETHTOOL_GRXCLSRLCNT 0x0000002e /* Get RX class rule count */
#define ETHTOOL_GRXCLSRULE 0x0000002f /* Get RX classification rule */
#define ETHTOOL_GRXCLSRLALL 0x00000030 /* Get all RX classification rule */
#define ETHTOOL_SRXCLSRLDEL 0x00000031 /* Delete RX classification rule */
#define ETHTOOL_SRXCLSRLINS 0x00000032 /* Insert RX classification rule */
#define ETHTOOL_FLASHDEV 0x00000033 /* Flash firmware to device */
#define ETHTOOL_RESET 0x00000034 /* Reset hardware */
#define ETHTOOL_SRXNTUPLE 0x00000035 /* Add an n-tuple filter to device */
#define ETHTOOL_GRXNTUPLE 0x00000036 /* Get n-tuple filters from device */
#define ETHTOOL_GSSET_INFO 0x00000037 /* Get string set info */
#define ETHTOOL_GRXFHINDIR 0x00000038 /* Get RX flow hash indir'n table */
#define ETHTOOL_SRXFHINDIR 0x00000039 /* Set RX flow hash indir'n table */
#define ETHTOOL_GFEATURES 0x0000003a /* Get device offload settings */
#define ETHTOOL_SFEATURES 0x0000003b /* Change device offload settings */
/* compatibility with older code */
#define SPARC_ETH_GSET ETHTOOL_GSET
#define SPARC_ETH_SSET ETHTOOL_SSET
/* Indicates what features are supported by the interface. */
#define SUPPORTED_10baseT_Half (1 << 0)
#define SUPPORTED_10baseT_Full (1 << 1)
#define SUPPORTED_100baseT_Half (1 << 2)
#define SUPPORTED_100baseT_Full (1 << 3)
#define SUPPORTED_1000baseT_Half (1 << 4)
#define SUPPORTED_1000baseT_Full (1 << 5)
#define SUPPORTED_Autoneg (1 << 6)
#define SUPPORTED_TP (1 << 7)
#define SUPPORTED_AUI (1 << 8)
#define SUPPORTED_MII (1 << 9)
#define SUPPORTED_FIBRE (1 << 10)
#define SUPPORTED_BNC (1 << 11)
#define SUPPORTED_10000baseT_Full (1 << 12)
#define SUPPORTED_Pause (1 << 13)
#define SUPPORTED_Asym_Pause (1 << 14)
#define SUPPORTED_2500baseX_Full (1 << 15)
#define SUPPORTED_Backplane (1 << 16)
#define SUPPORTED_1000baseKX_Full (1 << 17)
#define SUPPORTED_10000baseKX4_Full (1 << 18)
#define SUPPORTED_10000baseKR_Full (1 << 19)
#define SUPPORTED_10000baseR_FEC (1 << 20)
/* Indicates what features are advertised by the interface. */
#define ADVERTISED_10baseT_Half (1 << 0)
#define ADVERTISED_10baseT_Full (1 << 1)
#define ADVERTISED_100baseT_Half (1 << 2)
#define ADVERTISED_100baseT_Full (1 << 3)
#define ADVERTISED_1000baseT_Half (1 << 4)
#define ADVERTISED_1000baseT_Full (1 << 5)
#define ADVERTISED_Autoneg (1 << 6)
#define ADVERTISED_TP (1 << 7)
#define ADVERTISED_AUI (1 << 8)
#define ADVERTISED_MII (1 << 9)
#define ADVERTISED_FIBRE (1 << 10)
#define ADVERTISED_BNC (1 << 11)
#define ADVERTISED_10000baseT_Full (1 << 12)
#define ADVERTISED_Pause (1 << 13)
#define ADVERTISED_Asym_Pause (1 << 14)
#define ADVERTISED_2500baseX_Full (1 << 15)
#define ADVERTISED_Backplane (1 << 16)
#define ADVERTISED_1000baseKX_Full (1 << 17)
#define ADVERTISED_10000baseKX4_Full (1 << 18)
#define ADVERTISED_10000baseKR_Full (1 << 19)
#define ADVERTISED_10000baseR_FEC (1 << 20)
/* The following are all involved in forcing a particular link
* mode for the device for setting things. When getting the
* devices settings, these indicate the current mode and whether
* it was foced up into this mode or autonegotiated.
*/
/* The forced speed, 10Mb, 100Mb, gigabit, 2.5Gb, 10GbE. */
#define SPEED_10 10
#define SPEED_100 100
#define SPEED_1000 1000
#define SPEED_2500 2500
#define SPEED_10000 10000
/* Duplex, half or full. */
#define DUPLEX_HALF 0x00
#define DUPLEX_FULL 0x01
/* Which connector port. */
#define PORT_TP 0x00
#define PORT_AUI 0x01
#define PORT_MII 0x02
#define PORT_FIBRE 0x03
#define PORT_BNC 0x04
#define PORT_DA 0x05
#define PORT_NONE 0xef
#define PORT_OTHER 0xff
/* Which transceiver to use. */
#define XCVR_INTERNAL 0x00
#define XCVR_EXTERNAL 0x01
#define XCVR_DUMMY1 0x02
#define XCVR_DUMMY2 0x03
#define XCVR_DUMMY3 0x04
/* Enable or disable autonegotiation. If this is set to enable,
* the forced link modes above are completely ignored.
*/
#define AUTONEG_DISABLE 0x00
#define AUTONEG_ENABLE 0x01
/* Mode MDI or MDI-X */
#define ETH_TP_MDI_INVALID 0x00
#define ETH_TP_MDI 0x01
#define ETH_TP_MDI_X 0x02
/* Wake-On-Lan options. */
#define WAKE_PHY (1 << 0)
#define WAKE_UCAST (1 << 1)
#define WAKE_MCAST (1 << 2)
#define WAKE_BCAST (1 << 3)
#define WAKE_ARP (1 << 4)
#define WAKE_MAGIC (1 << 5)
#define WAKE_MAGICSECURE (1 << 6) /* only meaningful if WAKE_MAGIC */
/* L2-L4 network traffic flow types */
#define TCP_V4_FLOW 0x01 /* hash or spec (tcp_ip4_spec) */
#define UDP_V4_FLOW 0x02 /* hash or spec (udp_ip4_spec) */
#define SCTP_V4_FLOW 0x03 /* hash or spec (sctp_ip4_spec) */
#define AH_ESP_V4_FLOW 0x04 /* hash only */
#define TCP_V6_FLOW 0x05 /* hash only */
#define UDP_V6_FLOW 0x06 /* hash only */
#define SCTP_V6_FLOW 0x07 /* hash only */
#define AH_ESP_V6_FLOW 0x08 /* hash only */
#define AH_V4_FLOW 0x09 /* hash or spec (ah_ip4_spec) */
#define ESP_V4_FLOW 0x0a /* hash or spec (esp_ip4_spec) */
#define AH_V6_FLOW 0x0b /* hash only */
#define ESP_V6_FLOW 0x0c /* hash only */
#define IP_USER_FLOW 0x0d /* spec only (usr_ip4_spec) */
#define IPV4_FLOW 0x10 /* hash only */
#define IPV6_FLOW 0x11 /* hash only */
#define ETHER_FLOW 0x12 /* spec only (ether_spec) */
/* L3-L4 network traffic flow hash options */
#define RXH_L2DA (1 << 1)
#define RXH_VLAN (1 << 2)
#define RXH_L3_PROTO (1 << 3)
#define RXH_IP_SRC (1 << 4)
#define RXH_IP_DST (1 << 5)
#define RXH_L4_B_0_1 (1 << 6) /* src port in case of TCP/UDP/SCTP */
#define RXH_L4_B_2_3 (1 << 7) /* dst port in case of TCP/UDP/SCTP */
#define RXH_DISCARD (1 << 31)
#define RX_CLS_FLOW_DISC 0xffffffffffffffffULL
/* Reset flags */
/* The reset() operation must clear the flags for the components which
* were actually reset. On successful return, the flags indicate the
* components which were not reset, either because they do not exist
* in the hardware or because they cannot be reset independently. The
* driver must never reset any components that were not requested.
*/
enum ethtool_reset_flags {
/* These flags represent components dedicated to the interface
* the command is addressed to. Shift any flag left by
* ETH_RESET_SHARED_SHIFT to reset a shared component of the
* same type.
*/
ETH_RESET_MGMT = 1 << 0, /* Management processor */
ETH_RESET_IRQ = 1 << 1, /* Interrupt requester */
ETH_RESET_DMA = 1 << 2, /* DMA engine */
ETH_RESET_FILTER = 1 << 3, /* Filtering/flow direction */
ETH_RESET_OFFLOAD = 1 << 4, /* Protocol offload */
ETH_RESET_MAC = 1 << 5, /* Media access controller */
ETH_RESET_PHY = 1 << 6, /* Transceiver/PHY */
ETH_RESET_RAM = 1 << 7, /* RAM shared between
* multiple components */
ETH_RESET_DEDICATED = 0x0000ffff, /* All components dedicated to
* this interface */
ETH_RESET_ALL = 0xffffffff, /* All components used by this
* interface, even if shared */
};
#define ETH_RESET_SHARED_SHIFT 16
#endif /* _LINUX_ETHTOOL_H */

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/*
* linux/mdio.h: definitions for MDIO (clause 45) transceivers
* Copyright 2006-2009 Solarflare Communications Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation, incorporated herein by reference.
*/
#ifndef __LINUX_MDIO_H__
#define __LINUX_MDIO_H__
#include <linux/mii.h>
/* MDIO Manageable Devices (MMDs). */
#define MDIO_MMD_PMAPMD 1 /* Physical Medium Attachment/
* Physical Medium Dependent */
#define MDIO_MMD_WIS 2 /* WAN Interface Sublayer */
#define MDIO_MMD_PCS 3 /* Physical Coding Sublayer */
#define MDIO_MMD_PHYXS 4 /* PHY Extender Sublayer */
#define MDIO_MMD_DTEXS 5 /* DTE Extender Sublayer */
#define MDIO_MMD_TC 6 /* Transmission Convergence */
#define MDIO_MMD_AN 7 /* Auto-Negotiation */
#define MDIO_MMD_C22EXT 29 /* Clause 22 extension */
#define MDIO_MMD_VEND1 30 /* Vendor specific 1 */
#define MDIO_MMD_VEND2 31 /* Vendor specific 2 */
/* Generic MDIO registers. */
#define MDIO_CTRL1 MII_BMCR
#define MDIO_STAT1 MII_BMSR
#define MDIO_DEVID1 MII_PHYSID1
#define MDIO_DEVID2 MII_PHYSID2
#define MDIO_SPEED 4 /* Speed ability */
#define MDIO_DEVS1 5 /* Devices in package */
#define MDIO_DEVS2 6
#define MDIO_CTRL2 7 /* 10G control 2 */
#define MDIO_STAT2 8 /* 10G status 2 */
#define MDIO_PMA_TXDIS 9 /* 10G PMA/PMD transmit disable */
#define MDIO_PMA_RXDET 10 /* 10G PMA/PMD receive signal detect */
#define MDIO_PMA_EXTABLE 11 /* 10G PMA/PMD extended ability */
#define MDIO_PKGID1 14 /* Package identifier */
#define MDIO_PKGID2 15
#define MDIO_AN_ADVERTISE 16 /* AN advertising (base page) */
#define MDIO_AN_LPA 19 /* AN LP abilities (base page) */
#define MDIO_PHYXS_LNSTAT 24 /* PHY XGXS lane state */
/* Media-dependent registers. */
#define MDIO_PMA_10GBT_SWAPPOL 130 /* 10GBASE-T pair swap & polarity */
#define MDIO_PMA_10GBT_TXPWR 131 /* 10GBASE-T TX power control */
#define MDIO_PMA_10GBT_SNR 133 /* 10GBASE-T SNR margin, lane A.
* Lanes B-D are numbered 134-136. */
#define MDIO_PMA_10GBR_FECABLE 170 /* 10GBASE-R FEC ability */
#define MDIO_PCS_10GBX_STAT1 24 /* 10GBASE-X PCS status 1 */
#define MDIO_PCS_10GBRT_STAT1 32 /* 10GBASE-R/-T PCS status 1 */
#define MDIO_PCS_10GBRT_STAT2 33 /* 10GBASE-R/-T PCS status 2 */
#define MDIO_AN_10GBT_CTRL 32 /* 10GBASE-T auto-negotiation control */
#define MDIO_AN_10GBT_STAT 33 /* 10GBASE-T auto-negotiation status */
#define MDIO_AN_EEE_ADV 60 /* EEE advertisement */
/* LASI (Link Alarm Status Interrupt) registers, defined by XENPAK MSA. */
#define MDIO_PMA_LASI_RXCTRL 0x9000 /* RX_ALARM control */
#define MDIO_PMA_LASI_TXCTRL 0x9001 /* TX_ALARM control */
#define MDIO_PMA_LASI_CTRL 0x9002 /* LASI control */
#define MDIO_PMA_LASI_RXSTAT 0x9003 /* RX_ALARM status */
#define MDIO_PMA_LASI_TXSTAT 0x9004 /* TX_ALARM status */
#define MDIO_PMA_LASI_STAT 0x9005 /* LASI status */
/* Control register 1. */
/* Enable extended speed selection */
#define MDIO_CTRL1_SPEEDSELEXT (BMCR_SPEED1000 | BMCR_SPEED100)
/* All speed selection bits */
#define MDIO_CTRL1_SPEEDSEL (MDIO_CTRL1_SPEEDSELEXT | 0x003c)
#define MDIO_CTRL1_FULLDPLX BMCR_FULLDPLX
#define MDIO_CTRL1_LPOWER BMCR_PDOWN
#define MDIO_CTRL1_RESET BMCR_RESET
#define MDIO_PMA_CTRL1_LOOPBACK 0x0001
#define MDIO_PMA_CTRL1_SPEED1000 BMCR_SPEED1000
#define MDIO_PMA_CTRL1_SPEED100 BMCR_SPEED100
#define MDIO_PCS_CTRL1_LOOPBACK BMCR_LOOPBACK
#define MDIO_PHYXS_CTRL1_LOOPBACK BMCR_LOOPBACK
#define MDIO_AN_CTRL1_RESTART BMCR_ANRESTART
#define MDIO_AN_CTRL1_ENABLE BMCR_ANENABLE
#define MDIO_AN_CTRL1_XNP 0x2000 /* Enable extended next page */
/* 10 Gb/s */
#define MDIO_CTRL1_SPEED10G (MDIO_CTRL1_SPEEDSELEXT | 0x00)
/* 10PASS-TS/2BASE-TL */
#define MDIO_CTRL1_SPEED10P2B (MDIO_CTRL1_SPEEDSELEXT | 0x04)
/* Status register 1. */
#define MDIO_STAT1_LPOWERABLE 0x0002 /* Low-power ability */
#define MDIO_STAT1_LSTATUS BMSR_LSTATUS
#define MDIO_STAT1_FAULT 0x0080 /* Fault */
#define MDIO_AN_STAT1_LPABLE 0x0001 /* Link partner AN ability */
#define MDIO_AN_STAT1_ABLE BMSR_ANEGCAPABLE
#define MDIO_AN_STAT1_RFAULT BMSR_RFAULT
#define MDIO_AN_STAT1_COMPLETE BMSR_ANEGCOMPLETE
#define MDIO_AN_STAT1_PAGE 0x0040 /* Page received */
#define MDIO_AN_STAT1_XNP 0x0080 /* Extended next page status */
/* Speed register. */
#define MDIO_SPEED_10G 0x0001 /* 10G capable */
#define MDIO_PMA_SPEED_2B 0x0002 /* 2BASE-TL capable */
#define MDIO_PMA_SPEED_10P 0x0004 /* 10PASS-TS capable */
#define MDIO_PMA_SPEED_1000 0x0010 /* 1000M capable */
#define MDIO_PMA_SPEED_100 0x0020 /* 100M capable */
#define MDIO_PMA_SPEED_10 0x0040 /* 10M capable */
#define MDIO_PCS_SPEED_10P2B 0x0002 /* 10PASS-TS/2BASE-TL capable */
/* Device present registers. */
#define MDIO_DEVS_PRESENT(devad) (1 << (devad))
#define MDIO_DEVS_PMAPMD MDIO_DEVS_PRESENT(MDIO_MMD_PMAPMD)
#define MDIO_DEVS_WIS MDIO_DEVS_PRESENT(MDIO_MMD_WIS)
#define MDIO_DEVS_PCS MDIO_DEVS_PRESENT(MDIO_MMD_PCS)
#define MDIO_DEVS_PHYXS MDIO_DEVS_PRESENT(MDIO_MMD_PHYXS)
#define MDIO_DEVS_DTEXS MDIO_DEVS_PRESENT(MDIO_MMD_DTEXS)
#define MDIO_DEVS_TC MDIO_DEVS_PRESENT(MDIO_MMD_TC)
#define MDIO_DEVS_AN MDIO_DEVS_PRESENT(MDIO_MMD_AN)
#define MDIO_DEVS_C22EXT MDIO_DEVS_PRESENT(MDIO_MMD_C22EXT)
#define MDIO_DEVS_VEND1 MDIO_DEVS_PRESENT(MDIO_MMD_VEND1)
#define MDIO_DEVS_VEND2 MDIO_DEVS_PRESENT(MDIO_MMD_VEND2)
/* Control register 2. */
#define MDIO_PMA_CTRL2_TYPE 0x000f /* PMA/PMD type selection */
#define MDIO_PMA_CTRL2_10GBCX4 0x0000 /* 10GBASE-CX4 type */
#define MDIO_PMA_CTRL2_10GBEW 0x0001 /* 10GBASE-EW type */
#define MDIO_PMA_CTRL2_10GBLW 0x0002 /* 10GBASE-LW type */
#define MDIO_PMA_CTRL2_10GBSW 0x0003 /* 10GBASE-SW type */
#define MDIO_PMA_CTRL2_10GBLX4 0x0004 /* 10GBASE-LX4 type */
#define MDIO_PMA_CTRL2_10GBER 0x0005 /* 10GBASE-ER type */
#define MDIO_PMA_CTRL2_10GBLR 0x0006 /* 10GBASE-LR type */
#define MDIO_PMA_CTRL2_10GBSR 0x0007 /* 10GBASE-SR type */
#define MDIO_PMA_CTRL2_10GBLRM 0x0008 /* 10GBASE-LRM type */
#define MDIO_PMA_CTRL2_10GBT 0x0009 /* 10GBASE-T type */
#define MDIO_PMA_CTRL2_10GBKX4 0x000a /* 10GBASE-KX4 type */
#define MDIO_PMA_CTRL2_10GBKR 0x000b /* 10GBASE-KR type */
#define MDIO_PMA_CTRL2_1000BT 0x000c /* 1000BASE-T type */
#define MDIO_PMA_CTRL2_1000BKX 0x000d /* 1000BASE-KX type */
#define MDIO_PMA_CTRL2_100BTX 0x000e /* 100BASE-TX type */
#define MDIO_PMA_CTRL2_10BT 0x000f /* 10BASE-T type */
#define MDIO_PCS_CTRL2_TYPE 0x0003 /* PCS type selection */
#define MDIO_PCS_CTRL2_10GBR 0x0000 /* 10GBASE-R type */
#define MDIO_PCS_CTRL2_10GBX 0x0001 /* 10GBASE-X type */
#define MDIO_PCS_CTRL2_10GBW 0x0002 /* 10GBASE-W type */
#define MDIO_PCS_CTRL2_10GBT 0x0003 /* 10GBASE-T type */
/* Status register 2. */
#define MDIO_STAT2_RXFAULT 0x0400 /* Receive fault */
#define MDIO_STAT2_TXFAULT 0x0800 /* Transmit fault */
#define MDIO_STAT2_DEVPRST 0xc000 /* Device present */
#define MDIO_STAT2_DEVPRST_VAL 0x8000 /* Device present value */
#define MDIO_PMA_STAT2_LBABLE 0x0001 /* PMA loopback ability */
#define MDIO_PMA_STAT2_10GBEW 0x0002 /* 10GBASE-EW ability */
#define MDIO_PMA_STAT2_10GBLW 0x0004 /* 10GBASE-LW ability */
#define MDIO_PMA_STAT2_10GBSW 0x0008 /* 10GBASE-SW ability */
#define MDIO_PMA_STAT2_10GBLX4 0x0010 /* 10GBASE-LX4 ability */
#define MDIO_PMA_STAT2_10GBER 0x0020 /* 10GBASE-ER ability */
#define MDIO_PMA_STAT2_10GBLR 0x0040 /* 10GBASE-LR ability */
#define MDIO_PMA_STAT2_10GBSR 0x0080 /* 10GBASE-SR ability */
#define MDIO_PMD_STAT2_TXDISAB 0x0100 /* PMD TX disable ability */
#define MDIO_PMA_STAT2_EXTABLE 0x0200 /* Extended abilities */
#define MDIO_PMA_STAT2_RXFLTABLE 0x1000 /* Receive fault ability */
#define MDIO_PMA_STAT2_TXFLTABLE 0x2000 /* Transmit fault ability */
#define MDIO_PCS_STAT2_10GBR 0x0001 /* 10GBASE-R capable */
#define MDIO_PCS_STAT2_10GBX 0x0002 /* 10GBASE-X capable */
#define MDIO_PCS_STAT2_10GBW 0x0004 /* 10GBASE-W capable */
#define MDIO_PCS_STAT2_RXFLTABLE 0x1000 /* Receive fault ability */
#define MDIO_PCS_STAT2_TXFLTABLE 0x2000 /* Transmit fault ability */
/* Transmit disable register. */
#define MDIO_PMD_TXDIS_GLOBAL 0x0001 /* Global PMD TX disable */
#define MDIO_PMD_TXDIS_0 0x0002 /* PMD TX disable 0 */
#define MDIO_PMD_TXDIS_1 0x0004 /* PMD TX disable 1 */
#define MDIO_PMD_TXDIS_2 0x0008 /* PMD TX disable 2 */
#define MDIO_PMD_TXDIS_3 0x0010 /* PMD TX disable 3 */
/* Receive signal detect register. */
#define MDIO_PMD_RXDET_GLOBAL 0x0001 /* Global PMD RX signal detect */
#define MDIO_PMD_RXDET_0 0x0002 /* PMD RX signal detect 0 */
#define MDIO_PMD_RXDET_1 0x0004 /* PMD RX signal detect 1 */
#define MDIO_PMD_RXDET_2 0x0008 /* PMD RX signal detect 2 */
#define MDIO_PMD_RXDET_3 0x0010 /* PMD RX signal detect 3 */
/* Extended abilities register. */
#define MDIO_PMA_EXTABLE_10GCX4 0x0001 /* 10GBASE-CX4 ability */
#define MDIO_PMA_EXTABLE_10GBLRM 0x0002 /* 10GBASE-LRM ability */
#define MDIO_PMA_EXTABLE_10GBT 0x0004 /* 10GBASE-T ability */
#define MDIO_PMA_EXTABLE_10GBKX4 0x0008 /* 10GBASE-KX4 ability */
#define MDIO_PMA_EXTABLE_10GBKR 0x0010 /* 10GBASE-KR ability */
#define MDIO_PMA_EXTABLE_1000BT 0x0020 /* 1000BASE-T ability */
#define MDIO_PMA_EXTABLE_1000BKX 0x0040 /* 1000BASE-KX ability */
#define MDIO_PMA_EXTABLE_100BTX 0x0080 /* 100BASE-TX ability */
#define MDIO_PMA_EXTABLE_10BT 0x0100 /* 10BASE-T ability */
/* PHY XGXS lane state register. */
#define MDIO_PHYXS_LNSTAT_SYNC0 0x0001
#define MDIO_PHYXS_LNSTAT_SYNC1 0x0002
#define MDIO_PHYXS_LNSTAT_SYNC2 0x0004
#define MDIO_PHYXS_LNSTAT_SYNC3 0x0008
#define MDIO_PHYXS_LNSTAT_ALIGN 0x1000
/* PMA 10GBASE-T pair swap & polarity */
#define MDIO_PMA_10GBT_SWAPPOL_ABNX 0x0001 /* Pair A/B uncrossed */
#define MDIO_PMA_10GBT_SWAPPOL_CDNX 0x0002 /* Pair C/D uncrossed */
#define MDIO_PMA_10GBT_SWAPPOL_AREV 0x0100 /* Pair A polarity reversed */
#define MDIO_PMA_10GBT_SWAPPOL_BREV 0x0200 /* Pair B polarity reversed */
#define MDIO_PMA_10GBT_SWAPPOL_CREV 0x0400 /* Pair C polarity reversed */
#define MDIO_PMA_10GBT_SWAPPOL_DREV 0x0800 /* Pair D polarity reversed */
/* PMA 10GBASE-T TX power register. */
#define MDIO_PMA_10GBT_TXPWR_SHORT 0x0001 /* Short-reach mode */
/* PMA 10GBASE-T SNR registers. */
/* Value is SNR margin in dB, clamped to range [-127, 127], plus 0x8000. */
#define MDIO_PMA_10GBT_SNR_BIAS 0x8000
#define MDIO_PMA_10GBT_SNR_MAX 127
/* PMA 10GBASE-R FEC ability register. */
#define MDIO_PMA_10GBR_FECABLE_ABLE 0x0001 /* FEC ability */
#define MDIO_PMA_10GBR_FECABLE_ERRABLE 0x0002 /* FEC error indic. ability */
/* PCS 10GBASE-R/-T status register 1. */
#define MDIO_PCS_10GBRT_STAT1_BLKLK 0x0001 /* Block lock attained */
/* PCS 10GBASE-R/-T status register 2. */
#define MDIO_PCS_10GBRT_STAT2_ERR 0x00ff
#define MDIO_PCS_10GBRT_STAT2_BER 0x3f00
/* AN 10GBASE-T control register. */
#define MDIO_AN_10GBT_CTRL_ADV10G 0x1000 /* Advertise 10GBASE-T */
/* AN 10GBASE-T status register. */
#define MDIO_AN_10GBT_STAT_LPTRR 0x0200 /* LP training reset req. */
#define MDIO_AN_10GBT_STAT_LPLTABLE 0x0400 /* LP loop timing ability */
#define MDIO_AN_10GBT_STAT_LP10G 0x0800 /* LP is 10GBT capable */
#define MDIO_AN_10GBT_STAT_REMOK 0x1000 /* Remote OK */
#define MDIO_AN_10GBT_STAT_LOCOK 0x2000 /* Local OK */
#define MDIO_AN_10GBT_STAT_MS 0x4000 /* Master/slave config */
#define MDIO_AN_10GBT_STAT_MSFLT 0x8000 /* Master/slave config fault */
/* AN EEE Advertisement register. */
#define MDIO_AN_EEE_ADV_100TX 0x0002 /* Advertise 100TX EEE cap */
#define MDIO_AN_EEE_ADV_1000T 0x0004 /* Advertise 1000T EEE cap */
/* LASI RX_ALARM control/status registers. */
#define MDIO_PMA_LASI_RX_PHYXSLFLT 0x0001 /* PHY XS RX local fault */
#define MDIO_PMA_LASI_RX_PCSLFLT 0x0008 /* PCS RX local fault */
#define MDIO_PMA_LASI_RX_PMALFLT 0x0010 /* PMA/PMD RX local fault */
#define MDIO_PMA_LASI_RX_OPTICPOWERFLT 0x0020 /* RX optical power fault */
#define MDIO_PMA_LASI_RX_WISLFLT 0x0200 /* WIS local fault */
/* LASI TX_ALARM control/status registers. */
#define MDIO_PMA_LASI_TX_PHYXSLFLT 0x0001 /* PHY XS TX local fault */
#define MDIO_PMA_LASI_TX_PCSLFLT 0x0008 /* PCS TX local fault */
#define MDIO_PMA_LASI_TX_PMALFLT 0x0010 /* PMA/PMD TX local fault */
#define MDIO_PMA_LASI_TX_LASERPOWERFLT 0x0080 /* Laser output power fault */
#define MDIO_PMA_LASI_TX_LASERTEMPFLT 0x0100 /* Laser temperature fault */
#define MDIO_PMA_LASI_TX_LASERBICURRFLT 0x0200 /* Laser bias current fault */
/* LASI control/status registers. */
#define MDIO_PMA_LASI_LSALARM 0x0001 /* LS_ALARM enable/status */
#define MDIO_PMA_LASI_TXALARM 0x0002 /* TX_ALARM enable/status */
#define MDIO_PMA_LASI_RXALARM 0x0004 /* RX_ALARM enable/status */
/* Mapping between MDIO PRTAD/DEVAD and mii_ioctl_data::phy_id */
#define MDIO_PHY_ID_C45 0x8000
#define MDIO_PHY_ID_PRTAD 0x03e0
#define MDIO_PHY_ID_DEVAD 0x001f
#define MDIO_PHY_ID_C45_MASK \
(MDIO_PHY_ID_C45 | MDIO_PHY_ID_PRTAD | MDIO_PHY_ID_DEVAD)
#define MDIO_PRTAD_NONE (-1)
#define MDIO_DEVAD_NONE (-1)
#define MDIO_EMULATE_C22 4
#endif /* __LINUX_MDIO_H__ */

53
include/miiphy.h
View File

@@ -34,35 +34,52 @@
#ifndef _miiphy_h_
#define _miiphy_h_
#include <common.h>
#include <linux/mii.h>
#include <linux/list.h>
#include <net.h>
#include <phy.h>
int miiphy_read (const char *devname, unsigned char addr, unsigned char reg,
struct legacy_mii_dev {
int (*read)(const char *devname, unsigned char addr,
unsigned char reg, unsigned short *value);
int (*write)(const char *devname, unsigned char addr,
unsigned char reg, unsigned short value);
};
int miiphy_read(const char *devname, unsigned char addr, unsigned char reg,
unsigned short *value);
int miiphy_write (const char *devname, unsigned char addr, unsigned char reg,
int miiphy_write(const char *devname, unsigned char addr, unsigned char reg,
unsigned short value);
int miiphy_info (const char *devname, unsigned char addr, unsigned int *oui,
int miiphy_info(const char *devname, unsigned char addr, unsigned int *oui,
unsigned char *model, unsigned char *rev);
int miiphy_reset (const char *devname, unsigned char addr);
int miiphy_speed (const char *devname, unsigned char addr);
int miiphy_duplex (const char *devname, unsigned char addr);
int miiphy_is_1000base_x (const char *devname, unsigned char addr);
int miiphy_reset(const char *devname, unsigned char addr);
int miiphy_speed(const char *devname, unsigned char addr);
int miiphy_duplex(const char *devname, unsigned char addr);
int miiphy_is_1000base_x(const char *devname, unsigned char addr);
#ifdef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
int miiphy_link (const char *devname, unsigned char addr);
int miiphy_link(const char *devname, unsigned char addr);
#endif
void miiphy_init (void);
void miiphy_init(void);
void miiphy_register (const char *devname,
int (*read) (const char *devname, unsigned char addr,
void miiphy_register(const char *devname,
int (*read)(const char *devname, unsigned char addr,
unsigned char reg, unsigned short *value),
int (*write) (const char *devname, unsigned char addr,
int (*write)(const char *devname, unsigned char addr,
unsigned char reg, unsigned short value));
int miiphy_set_current_dev (const char *devname);
const char *miiphy_get_current_dev (void);
int miiphy_set_current_dev(const char *devname);
const char *miiphy_get_current_dev(void);
struct mii_dev *mdio_get_current_dev(void);
struct mii_dev *miiphy_get_dev_by_name(const char *devname);
struct phy_device *mdio_phydev_for_ethname(const char *devname);
void miiphy_listdev (void);
void miiphy_listdev(void);
struct mii_dev *mdio_alloc(void);
int mdio_register(struct mii_dev *bus);
void mdio_list_devices(void);
#ifdef CONFIG_BITBANGMII
@@ -85,10 +102,10 @@ struct bb_miiphy_bus {
extern struct bb_miiphy_bus bb_miiphy_buses[];
extern int bb_miiphy_buses_num;
void bb_miiphy_init (void);
int bb_miiphy_read (const char *devname, unsigned char addr,
void bb_miiphy_init(void);
int bb_miiphy_read(const char *devname, unsigned char addr,
unsigned char reg, unsigned short *value);
int bb_miiphy_write (const char *devname, unsigned char addr,
int bb_miiphy_write(const char *devname, unsigned char addr,
unsigned char reg, unsigned short value);
#endif

229
include/phy.h Normal file
View File

@@ -0,0 +1,229 @@
/*
* Copyright 2011 Freescale Semiconductor, Inc.
* Andy Fleming <afleming@freescale.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* This file pretty much stolen from Linux's mii.h/ethtool.h/phy.h
*/
#ifndef _PHY_H
#define _PHY_H
#include <linux/list.h>
#include <linux/mii.h>
#include <linux/ethtool.h>
#include <linux/mdio.h>
#define PHY_MAX_ADDR 32
#define PHY_BASIC_FEATURES (SUPPORTED_10baseT_Half | \
SUPPORTED_10baseT_Full | \
SUPPORTED_100baseT_Half | \
SUPPORTED_100baseT_Full | \
SUPPORTED_Autoneg | \
SUPPORTED_TP | \
SUPPORTED_MII)
#define PHY_GBIT_FEATURES (PHY_BASIC_FEATURES | \
SUPPORTED_1000baseT_Half | \
SUPPORTED_1000baseT_Full)
#define PHY_10G_FEATURES (PHY_GBIT_FEATURES | \
SUPPORTED_10000baseT_Full)
#define PHY_ANEG_TIMEOUT 4000
typedef enum {
PHY_INTERFACE_MODE_MII,
PHY_INTERFACE_MODE_GMII,
PHY_INTERFACE_MODE_SGMII,
PHY_INTERFACE_MODE_TBI,
PHY_INTERFACE_MODE_RMII,
PHY_INTERFACE_MODE_RGMII,
PHY_INTERFACE_MODE_RGMII_ID,
PHY_INTERFACE_MODE_RGMII_RXID,
PHY_INTERFACE_MODE_RGMII_TXID,
PHY_INTERFACE_MODE_RTBI,
PHY_INTERFACE_MODE_XGMII,
PHY_INTERFACE_MODE_NONE /* Must be last */
} phy_interface_t;
static const char *phy_interface_strings[] = {
[PHY_INTERFACE_MODE_MII] = "mii",
[PHY_INTERFACE_MODE_GMII] = "gmii",
[PHY_INTERFACE_MODE_SGMII] = "sgmii",
[PHY_INTERFACE_MODE_TBI] = "tbi",
[PHY_INTERFACE_MODE_RMII] = "rmii",
[PHY_INTERFACE_MODE_RGMII] = "rgmii",
[PHY_INTERFACE_MODE_RGMII_ID] = "rgmii-id",
[PHY_INTERFACE_MODE_RGMII_RXID] = "rgmii-rxid",
[PHY_INTERFACE_MODE_RGMII_TXID] = "rgmii-txid",
[PHY_INTERFACE_MODE_RTBI] = "rtbi",
[PHY_INTERFACE_MODE_XGMII] = "xgmii",
[PHY_INTERFACE_MODE_NONE] = "",
};
static inline const char *phy_string_for_interface(phy_interface_t i)
{
/* Default to unknown */
if (i > PHY_INTERFACE_MODE_NONE)
i = PHY_INTERFACE_MODE_NONE;
return phy_interface_strings[i];
}
struct phy_device;
#define MDIO_NAME_LEN 32
struct mii_dev {
struct list_head link;
char name[MDIO_NAME_LEN];
void *priv;
int (*read)(struct mii_dev *bus, int addr, int devad, int reg);
int (*write)(struct mii_dev *bus, int addr, int devad, int reg,
u16 val);
int (*reset)(struct mii_dev *bus);
struct phy_device *phymap[PHY_MAX_ADDR];
u32 phy_mask;
};
/* struct phy_driver: a structure which defines PHY behavior
*
* uid will contain a number which represents the PHY. During
* startup, the driver will poll the PHY to find out what its
* UID--as defined by registers 2 and 3--is. The 32-bit result
* gotten from the PHY will be masked to
* discard any bits which may change based on revision numbers
* unimportant to functionality
*
*/
struct phy_driver {
char *name;
unsigned int uid;
unsigned int mask;
unsigned int mmds;
u32 features;
/* Called to do any driver startup necessities */
/* Will be called during phy_connect */
int (*probe)(struct phy_device *phydev);
/* Called to configure the PHY, and modify the controller
* based on the results. Should be called after phy_connect */
int (*config)(struct phy_device *phydev);
/* Called when starting up the controller */
int (*startup)(struct phy_device *phydev);
/* Called when bringing down the controller */
int (*shutdown)(struct phy_device *phydev);
struct list_head list;
};
struct phy_device {
/* Information about the PHY type */
/* And management functions */
struct mii_dev *bus;
struct phy_driver *drv;
void *priv;
struct eth_device *dev;
/* forced speed & duplex (no autoneg)
* partner speed & duplex & pause (autoneg)
*/
int speed;
int duplex;
/* The most recently read link state */
int link;
int port;
phy_interface_t interface;
u32 advertising;
u32 supported;
u32 mmds;
int autoneg;
int addr;
int pause;
int asym_pause;
u32 phy_id;
u32 flags;
};
static inline int phy_read(struct phy_device *phydev, int devad, int regnum)
{
struct mii_dev *bus = phydev->bus;
return bus->read(bus, phydev->addr, devad, regnum);
}
static inline int phy_write(struct phy_device *phydev, int devad, int regnum,
u16 val)
{
struct mii_dev *bus = phydev->bus;
return bus->write(bus, phydev->addr, devad, regnum, val);
}
#ifdef CONFIG_PHYLIB_10G
extern struct phy_driver gen10g_driver;
/* For now, XGMII is the only 10G interface */
static inline int is_10g_interface(phy_interface_t interface)
{
return interface == PHY_INTERFACE_MODE_XGMII;
}
#endif
int phy_init(void);
int phy_reset(struct phy_device *phydev);
struct phy_device *phy_connect(struct mii_dev *bus, int addr,
struct eth_device *dev,
phy_interface_t interface);
int phy_startup(struct phy_device *phydev);
int phy_config(struct phy_device *phydev);
int phy_shutdown(struct phy_device *phydev);
int phy_register(struct phy_driver *drv);
int genphy_config_aneg(struct phy_device *phydev);
int genphy_update_link(struct phy_device *phydev);
int genphy_config(struct phy_device *phydev);
int genphy_startup(struct phy_device *phydev);
int genphy_shutdown(struct phy_device *phydev);
int gen10g_config(struct phy_device *phydev);
int gen10g_startup(struct phy_device *phydev);
int gen10g_shutdown(struct phy_device *phydev);
int gen10g_discover_mmds(struct phy_device *phydev);
int phy_atheros_init(void);
int phy_broadcom_init(void);
int phy_davicom_init(void);
int phy_lxt_init(void);
int phy_marvell_init(void);
int phy_micrel_init(void);
int phy_natsemi_init(void);
int phy_realtek_init(void);
int phy_teranetics_init(void);
int phy_vitesse_init(void);
#endif

302
include/tsec.h
View File

@@ -7,7 +7,7 @@
* terms of the GNU Public License, Version 2, incorporated
* herein by reference.
*
* Copyright 2004, 2007, 2009 Freescale Semiconductor, Inc.
* Copyright 2004, 2007, 2009, 2011 Freescale Semiconductor, Inc.
* (C) Copyright 2003, Motorola, Inc.
* maintained by Xianghua Xiao (x.xiao@motorola.com)
* author Andy Fleming
@@ -19,30 +19,36 @@
#include <net.h>
#include <config.h>
#include <phy.h>
#include <asm/fsl_enet.h>
#define TSEC_SIZE 0x01000
#define TSEC_MDIO_OFFSET 0x01000
#define CONFIG_SYS_MDIO_BASE_ADDR (TSEC_BASE_ADDR + 0x520)
#define DEFAULT_MII_NAME "FSL_MDIO"
#define STD_TSEC_INFO(num) \
{ \
.regs = (tsec_t *)(TSEC_BASE_ADDR + ((num - 1) * TSEC_SIZE)), \
.miiregs = (tsec_mdio_t *)(MDIO_BASE_ADDR), \
.miiregs_sgmii = (tsec_mdio_t *)(MDIO_BASE_ADDR \
.miiregs_sgmii = (struct tsec_mii_mng *)(CONFIG_SYS_MDIO_BASE_ADDR \
+ (num - 1) * TSEC_MDIO_OFFSET), \
.devname = CONFIG_TSEC##num##_NAME, \
.phyaddr = TSEC##num##_PHY_ADDR, \
.flags = TSEC##num##_FLAGS \
.flags = TSEC##num##_FLAGS, \
.mii_devname = DEFAULT_MII_NAME \
}
#define SET_STD_TSEC_INFO(x, num) \
{ \
x.regs = (tsec_t *)(TSEC_BASE_ADDR + ((num - 1) * TSEC_SIZE)); \
x.miiregs = (tsec_mdio_t *)(MDIO_BASE_ADDR); \
x.miiregs_sgmii = (tsec_mdio_t *)(MDIO_BASE_ADDR \
x.miiregs_sgmii = (struct tsec_mii_mng *)(CONFIG_SYS_MDIO_BASE_ADDR \
+ (num - 1) * TSEC_MDIO_OFFSET); \
x.devname = CONFIG_TSEC##num##_NAME; \
x.phyaddr = TSEC##num##_PHY_ADDR; \
x.flags = TSEC##num##_FLAGS;\
x.mii_devname = DEFAULT_MII_NAME;\
}
#define MAC_ADDR_LEN 6
@@ -51,8 +57,6 @@
#define TSEC_TIMEOUT 1000
#define TOUT_LOOP 1000000
#define PHY_AUTONEGOTIATE_TIMEOUT 5000 /* in ms */
/* TBI register addresses */
#define TBI_CR 0x00
#define TBI_SR 0x01
@@ -96,204 +100,14 @@
#define ECNTRL_INIT_SETTINGS 0x00001000
#define ECNTRL_TBI_MODE 0x00000020
#define ECNTRL_REDUCED_MODE 0x00000010
#define ECNTRL_R100 0x00000008
#define ECNTRL_REDUCED_MII_MODE 0x00000004
#define ECNTRL_SGMII_MODE 0x00000002
#define miim_end -2
#define miim_read -1
#ifndef CONFIG_SYS_TBIPA_VALUE
#define CONFIG_SYS_TBIPA_VALUE 0x1f
#endif
#define MIIMCFG_INIT_VALUE 0x00000003
#define MIIMCFG_RESET 0x80000000
#define MIIMIND_BUSY 0x00000001
#define MIIMIND_NOTVALID 0x00000004
#define MIIM_CONTROL 0x00
#define MIIM_CONTROL_RESET 0x00009140
#define MIIM_CONTROL_INIT 0x00001140
#define MIIM_CONTROL_RESTART 0x00001340
#define MIIM_ANEN 0x00001000
#define MIIM_CR 0x00
#define MIIM_CR_RST 0x00008000
#define MIIM_CR_INIT 0x00001000
#define MIIM_STATUS 0x1
#define MIIM_STATUS_AN_DONE 0x00000020
#define MIIM_STATUS_LINK 0x0004
#define MIIM_PHYIR1 0x2
#define MIIM_PHYIR2 0x3
#define MIIM_ANAR 0x4
#define MIIM_ANAR_INIT 0x1e1
#define MIIM_TBI_ANLPBPA 0x5
#define MIIM_TBI_ANLPBPA_HALF 0x00000040
#define MIIM_TBI_ANLPBPA_FULL 0x00000020
#define MIIM_TBI_ANEX 0x6
#define MIIM_TBI_ANEX_NP 0x00000004
#define MIIM_TBI_ANEX_PRX 0x00000002
#define MIIM_GBIT_CONTROL 0x9
#define MIIM_GBIT_CONTROL_INIT 0xe00
#define MIIM_EXT_PAGE_ACCESS 0x1f
/* Broadcom BCM54xx -- taken from linux sungem_phy */
#define MIIM_BCM54xx_AUXCNTL 0x18
#define MIIM_BCM54xx_AUXCNTL_ENCODE(val) ((val & 0x7) << 12)|(val & 0x7)
#define MIIM_BCM54xx_AUXSTATUS 0x19
#define MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK 0x0700
#define MIIM_BCM54xx_AUXSTATUS_LINKMODE_SHIFT 8
#define MIIM_BCM54XX_SHD 0x1c /* 0x1c shadow registers */
#define MIIM_BCM54XX_SHD_WRITE 0x8000
#define MIIM_BCM54XX_SHD_VAL(x) ((x & 0x1f) << 10)
#define MIIM_BCM54XX_SHD_DATA(x) ((x & 0x3ff) << 0)
#define MIIM_BCM54XX_SHD_WR_ENCODE(val, data) \
(MIIM_BCM54XX_SHD_WRITE | MIIM_BCM54XX_SHD_VAL(val) | \
MIIM_BCM54XX_SHD_DATA(data))
#define MIIM_BCM54XX_EXP_DATA 0x15 /* Expansion register data */
#define MIIM_BCM54XX_EXP_SEL 0x17 /* Expansion register select */
#define MIIM_BCM54XX_EXP_SEL_SSD 0x0e00 /* Secondary SerDes select */
#define MIIM_BCM54XX_EXP_SEL_ER 0x0f00 /* Expansion register select */
/* Cicada Auxiliary Control/Status Register */
#define MIIM_CIS8201_AUX_CONSTAT 0x1c
#define MIIM_CIS8201_AUXCONSTAT_INIT 0x0004
#define MIIM_CIS8201_AUXCONSTAT_DUPLEX 0x0020
#define MIIM_CIS8201_AUXCONSTAT_SPEED 0x0018
#define MIIM_CIS8201_AUXCONSTAT_GBIT 0x0010
#define MIIM_CIS8201_AUXCONSTAT_100 0x0008
/* Cicada Extended Control Register 1 */
#define MIIM_CIS8201_EXT_CON1 0x17
#define MIIM_CIS8201_EXTCON1_INIT 0x0000
/* Cicada 8204 Extended PHY Control Register 1 */
#define MIIM_CIS8204_EPHY_CON 0x17
#define MIIM_CIS8204_EPHYCON_INIT 0x0006
#define MIIM_CIS8204_EPHYCON_RGMII 0x1100
/* Cicada 8204 Serial LED Control Register */
#define MIIM_CIS8204_SLED_CON 0x1b
#define MIIM_CIS8204_SLEDCON_INIT 0x1115
#define MIIM_GBIT_CON 0x09
#define MIIM_GBIT_CON_ADVERT 0x0e00
/* Entry for Vitesse VSC8244 regs starts here */
/* Vitesse VSC8244 Auxiliary Control/Status Register */
#define MIIM_VSC8244_AUX_CONSTAT 0x1c
#define MIIM_VSC8244_AUXCONSTAT_INIT 0x0000
#define MIIM_VSC8244_AUXCONSTAT_DUPLEX 0x0020
#define MIIM_VSC8244_AUXCONSTAT_SPEED 0x0018
#define MIIM_VSC8244_AUXCONSTAT_GBIT 0x0010
#define MIIM_VSC8244_AUXCONSTAT_100 0x0008
#define MIIM_CONTROL_INIT_LOOPBACK 0x4000
/* Vitesse VSC8244 Extended PHY Control Register 1 */
#define MIIM_VSC8244_EPHY_CON 0x17
#define MIIM_VSC8244_EPHYCON_INIT 0x0006
/* Vitesse VSC8244 Serial LED Control Register */
#define MIIM_VSC8244_LED_CON 0x1b
#define MIIM_VSC8244_LEDCON_INIT 0xF011
/* Entry for Vitesse VSC8601 regs starts here (Not complete) */
/* Vitesse VSC8601 Extended PHY Control Register 1 */
#define MIIM_VSC8601_EPHY_CON 0x17
#define MIIM_VSC8601_EPHY_CON_INIT_SKEW 0x1120
#define MIIM_VSC8601_SKEW_CTRL 0x1c
/* 88E1011 PHY Status Register */
#define MIIM_88E1011_PHY_STATUS 0x11
#define MIIM_88E1011_PHYSTAT_SPEED 0xc000
#define MIIM_88E1011_PHYSTAT_GBIT 0x8000
#define MIIM_88E1011_PHYSTAT_100 0x4000
#define MIIM_88E1011_PHYSTAT_DUPLEX 0x2000
#define MIIM_88E1011_PHYSTAT_SPDDONE 0x0800
#define MIIM_88E1011_PHYSTAT_LINK 0x0400
#define MIIM_88E1011_PHY_SCR 0x10
#define MIIM_88E1011_PHY_MDI_X_AUTO 0x0060
/* 88E1111 PHY LED Control Register */
#define MIIM_88E1111_PHY_LED_CONTROL 24
#define MIIM_88E1111_PHY_LED_DIRECT 0x4100
#define MIIM_88E1111_PHY_LED_COMBINE 0x411C
/* 88E1121 PHY LED Control Register */
#define MIIM_88E1121_PHY_LED_CTRL 16
#define MIIM_88E1121_PHY_LED_PAGE 3
#define MIIM_88E1121_PHY_LED_DEF 0x0030
/* 88E1121 PHY IRQ Enable/Status Register */
#define MIIM_88E1121_PHY_IRQ_EN 18
#define MIIM_88E1121_PHY_IRQ_STATUS 19
#define MIIM_88E1121_PHY_PAGE 22
/* 88E1145 Extended PHY Specific Control Register */
#define MIIM_88E1145_PHY_EXT_CR 20
#define MIIM_M88E1145_RGMII_RX_DELAY 0x0080
#define MIIM_M88E1145_RGMII_TX_DELAY 0x0002
#define MIIM_88E1145_PHY_PAGE 29
#define MIIM_88E1145_PHY_CAL_OV 30
/* RTL8211B PHY Status Register */
#define MIIM_RTL8211B_PHY_STATUS 0x11
#define MIIM_RTL8211B_PHYSTAT_SPEED 0xc000
#define MIIM_RTL8211B_PHYSTAT_GBIT 0x8000
#define MIIM_RTL8211B_PHYSTAT_100 0x4000
#define MIIM_RTL8211B_PHYSTAT_DUPLEX 0x2000
#define MIIM_RTL8211B_PHYSTAT_SPDDONE 0x0800
#define MIIM_RTL8211B_PHYSTAT_LINK 0x0400
/* DM9161 Control register values */
#define MIIM_DM9161_CR_STOP 0x0400
#define MIIM_DM9161_CR_RSTAN 0x1200
#define MIIM_DM9161_SCR 0x10
#define MIIM_DM9161_SCR_INIT 0x0610
/* DM9161 Specified Configuration and Status Register */
#define MIIM_DM9161_SCSR 0x11
#define MIIM_DM9161_SCSR_100F 0x8000
#define MIIM_DM9161_SCSR_100H 0x4000
#define MIIM_DM9161_SCSR_10F 0x2000
#define MIIM_DM9161_SCSR_10H 0x1000
/* DM9161 10BT Configuration/Status */
#define MIIM_DM9161_10BTCSR 0x12
#define MIIM_DM9161_10BTCSR_INIT 0x7800
/* LXT971 Status 2 registers */
#define MIIM_LXT971_SR2 0x11 /* Status Register 2 */
#define MIIM_LXT971_SR2_SPEED_MASK 0x4200
#define MIIM_LXT971_SR2_10HDX 0x0000 /* 10 Mbit half duplex selected */
#define MIIM_LXT971_SR2_10FDX 0x0200 /* 10 Mbit full duplex selected */
#define MIIM_LXT971_SR2_100HDX 0x4000 /* 100 Mbit half duplex selected */
#define MIIM_LXT971_SR2_100FDX 0x4200 /* 100 Mbit full duplex selected */
/* DP83865 Control register values */
#define MIIM_DP83865_CR_INIT 0x9200
/* DP83865 Link and Auto-Neg Status Register */
#define MIIM_DP83865_LANR 0x11
#define MIIM_DP83865_SPD_MASK 0x0018
#define MIIM_DP83865_SPD_1000 0x0010
#define MIIM_DP83865_SPD_100 0x0008
#define MIIM_DP83865_DPX_FULL 0x0002
#define MIIM_READ_COMMAND 0x00000001
#define MRBLR_INIT_SETTINGS PKTSIZE_ALIGN
@@ -467,22 +281,6 @@ typedef struct tsec_hash_regs
uint res2[24];
} tsec_hash_t;
typedef struct tsec_mdio {
uint res1[4];
uint ieventm;
uint imaskm;
uint res2;
uint emapm;
uint res3[320];
uint miimcfg; /* MII Management: Configuration */
uint miimcom; /* MII Management: Command */
uint miimadd; /* MII Management: Address */
uint miimcon; /* MII Management: Control */
uint miimstat; /* MII Management: Status */
uint miimind; /* MII Management: Indicators */
uint res4[690];
} tsec_mdio_t;
typedef struct tsec
{
/* General Control and Status Registers (0x2_n000) */
@@ -578,79 +376,29 @@ typedef struct tsec
uint resc00[256];
} tsec_t;
#define TSEC_GIGABIT (1)
#define TSEC_GIGABIT (1 << 0)
/* This flag currently only has
* meaning if we're using the eTSEC */
/* These flags currently only have meaning if we're using the eTSEC */
#define TSEC_REDUCED (1 << 1) /* MAC-PHY interface uses RGMII */
#define TSEC_SGMII (1 << 2) /* MAC-PHY interface uses SGMII */
#define TSEC_FIBER (1 << 3) /* PHY uses fiber, eg 1000 Base-X */
struct tsec_private {
volatile tsec_t *regs;
volatile tsec_mdio_t *phyregs;
volatile tsec_mdio_t *phyregs_sgmii;
struct phy_info *phyinfo;
tsec_t *regs;
struct tsec_mii_mng *phyregs_sgmii;
struct phy_device *phydev;
phy_interface_t interface;
struct mii_dev *bus;
uint phyaddr;
char mii_devname[16];
u32 flags;
uint link;
uint duplexity;
uint speed;
};
/*
* struct phy_cmd: A command for reading or writing a PHY register
*
* mii_reg: The register to read or write
*
* mii_data: For writes, the value to put in the register.
* A value of -1 indicates this is a read.
*
* funct: A function pointer which is invoked for each command.
* For reads, this function will be passed the value read
* from the PHY, and process it.
* For writes, the result of this function will be written
* to the PHY register
*/
struct phy_cmd {
uint mii_reg;
uint mii_data;
uint (*funct) (uint mii_reg, struct tsec_private * priv);
};
/* struct phy_info: a structure which defines attributes for a PHY
*
* id will contain a number which represents the PHY. During
* startup, the driver will poll the PHY to find out what its
* UID--as defined by registers 2 and 3--is. The 32-bit result
* gotten from the PHY will be shifted right by "shift" bits to
* discard any bits which may change based on revision numbers
* unimportant to functionality
*
* The struct phy_cmd entries represent pointers to an arrays of
* commands which tell the driver what to do to the PHY.
*/
struct phy_info {
uint id;
char *name;
uint shift;
/* Called to configure the PHY, and modify the controller
* based on the results */
struct phy_cmd *config;
/* Called when starting up the controller */
struct phy_cmd *startup;
/* Called when bringing down the controller */
struct phy_cmd *shutdown;
};
struct tsec_info_struct {
tsec_t *regs;
tsec_mdio_t *miiregs;
tsec_mdio_t *miiregs_sgmii;
struct tsec_mii_mng *miiregs_sgmii;
char *devname;
char *mii_devname;
phy_interface_t interface;
unsigned int phyaddr;
u32 flags;
};