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mtd: mxs_nand: Add support for i.MX6

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Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Scott Wood <scottwood@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
This commit is contained in:
Stefan Roese
2013-04-15 21:14:12 +00:00
committed by Stefano Babic
parent 99193e30b4
commit ae695b18df
3 changed files with 26 additions and 2 deletions
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7
arch/arm/cpu/armv7/mx6/soc.c
View File

@@ -30,6 +30,7 @@
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <asm/imx-common/boot_mode.h>
#include <asm/imx-common/dma.h>
#include <stdbool.h>
struct scu_regs {
@@ -151,6 +152,12 @@ int arch_cpu_init(void)
set_vddsoc(1200); /* Set VDDSOC to 1.2V */
imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
#ifdef CONFIG_APBH_DMA
/* Start APBH DMA */
mxs_dma_init();
#endif
return 0;
}

10
arch/arm/include/asm/imx-common/regs-bch.h
View File

@@ -136,8 +136,13 @@ struct mxs_bch_regs {
#define BCH_FLASHLAYOUT0_NBLOCKS_OFFSET 24
#define BCH_FLASHLAYOUT0_META_SIZE_MASK (0xff << 16)
#define BCH_FLASHLAYOUT0_META_SIZE_OFFSET 16
#if defined(CONFIG_MX6)
#define BCH_FLASHLAYOUT0_ECC0_MASK (0x1f << 11)
#define BCH_FLASHLAYOUT0_ECC0_OFFSET 11
#else
#define BCH_FLASHLAYOUT0_ECC0_MASK (0xf << 12)
#define BCH_FLASHLAYOUT0_ECC0_OFFSET 12
#endif
#define BCH_FLASHLAYOUT0_ECC0_NONE (0x0 << 12)
#define BCH_FLASHLAYOUT0_ECC0_ECC2 (0x1 << 12)
#define BCH_FLASHLAYOUT0_ECC0_ECC4 (0x2 << 12)
@@ -161,8 +166,13 @@ struct mxs_bch_regs {
#define BCH_FLASHLAYOUT1_PAGE_SIZE_MASK (0xffff << 16)
#define BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET 16
#if defined(CONFIG_MX6)
#define BCH_FLASHLAYOUT1_ECCN_MASK (0x1f << 11)
#define BCH_FLASHLAYOUT1_ECCN_OFFSET 11
#else
#define BCH_FLASHLAYOUT1_ECCN_MASK (0xf << 12)
#define BCH_FLASHLAYOUT1_ECCN_OFFSET 12
#endif
#define BCH_FLASHLAYOUT1_ECCN_NONE (0x0 << 12)
#define BCH_FLASHLAYOUT1_ECCN_ECC2 (0x1 << 12)
#define BCH_FLASHLAYOUT1_ECCN_ECC4 (0x2 << 12)