Convert CONFIG_LBA48 et al to Kconfig

This converts the following to Kconfig:
   CONFIG_LBA48
   CONFIG_SYS_64BIT_LBA

Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini
2022-06-10 22:59:28 -04:00
parent 0a816d92d5
commit aca1f6789a
174 changed files with 195 additions and 231 deletions

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@@ -22,7 +22,6 @@
#ifdef CONFIG_IDE
/* ATA */
# define CONFIG_IDE_PREINIT 1
# undef CONFIG_LBA48
#endif
#ifdef CONFIG_DRIVER_DM9000

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@@ -262,13 +262,6 @@
#endif
#endif
/*
* SATA
*/
#ifdef CONFIG_FSL_SATA
#define CONFIG_LBA48
#endif
/*
* Environment
*/

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@@ -472,12 +472,6 @@ extern unsigned long get_sdram_size(void);
#endif /* CONFIG_TSEC_ENET */
/* SATA */
#ifdef CONFIG_FSL_SATA
#define CONFIG_LBA48
#endif /* #ifdef CONFIG_FSL_SATA */
#ifdef CONFIG_MMC
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
#endif

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@@ -336,12 +336,6 @@
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#endif /* CONFIG_PCI */
/* SATA */
#ifdef CONFIG_FSL_SATA_V2
#define CONFIG_LBA48
#endif
#ifdef CONFIG_FMAN_ENET
#define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2
#define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x3

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@@ -11,8 +11,6 @@
#define CONFIG_PCIE3
#define CONFIG_LBA48
#define CONFIG_SYS_SRIO
#define CONFIG_SRIO1 /* SRIO port 1 */
#define CONFIG_SRIO2 /* SRIO port 2 */

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@@ -390,11 +390,6 @@
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#endif /* CONFIG_PCI */
/* SATA */
#ifdef CONFIG_FSL_SATA_V2
#define CONFIG_LBA48
#endif
/*
* USB
*/

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@@ -457,13 +457,6 @@
#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
#endif
/*
* SATA
*/
#ifdef CONFIG_FSL_SATA_V2
#define CONFIG_LBA48
#endif
/*
* USB
*/

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@@ -413,13 +413,6 @@
#define AQR113C_PHY_ADDR2 0x08
#endif
/*
* SATA
*/
#ifdef CONFIG_FSL_SATA_V2
#define CONFIG_LBA48
#endif
/*
* USB
*/

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@@ -152,11 +152,6 @@
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#endif /* CONFIG_PCI */
/* SATA */
#ifdef CONFIG_FSL_SATA_V2
#define CONFIG_LBA48
#endif
/*
* Environment
*/
@@ -425,11 +420,6 @@
#define CORTINA_PHY_ADDR4 FM2_10GEC2_PHY_ADDR
#endif
/* SATA */
#ifdef CONFIG_FSL_SATA_V2
#define CONFIG_LBA48
#endif
/*
* USB
*/

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@@ -25,13 +25,6 @@
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_USDHC_NUM 3
/*
* SATA Configs
*/
#ifdef CONFIG_CMD_SATA
#define CONFIG_LBA48
#endif
/* Network */
#define PHY_ANEG_TIMEOUT 15000 /* PHY needs longer aneg time */

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@@ -149,9 +149,6 @@
#define CONFIG_MXC_USB_FLAGS 0
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
/* SATA */
#define CONFIG_LBA48
/* Boot */
#define CONFIG_SYS_BOOTMAPSZ (8 << 20)

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@@ -337,11 +337,6 @@
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#endif /* CONFIG_PCI */
/* SATA */
#ifdef CONFIG_FSL_SATA_V2
#define CONFIG_LBA48
#endif
#ifdef CONFIG_FMAN_ENET
#define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1c
#define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x1d

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@@ -22,9 +22,6 @@
#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
/* SATA support */
#define CONFIG_LBA48
/* PCIe support */
#ifndef CONFIG_SPL_BUILD
#define CONFIG_PCI_SCAN_SHOW

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@@ -33,9 +33,6 @@
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_USDHC_NUM 3
/* SATA Configs */
#define CONFIG_LBA48
/* UART */
#define CONFIG_MXC_UART_BASE UART1_BASE

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@@ -30,9 +30,4 @@
#define CONFIG_MVGBE_PORTS {1, 1} /* enable both ports */
#define CONFIG_PHY_BASE_ADR 0
/*
* SATA Driver configuration
*/
#define CONFIG_LBA48
#endif /* _CONFIG_DREAMPLUG_H */

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@@ -101,8 +101,6 @@
#define __io
/* Data, registers and alternate blocks are at the same offset */
/* Each 8-bit ATA register is aligned to a 4-bytes address */
/* Controller supports 48-bits LBA addressing */
#define CONFIG_LBA48
/* A single bus, a single device */
/* ATA registers base is at SATA controller base */
/* ATA bus 0 is orion5x port 1 on ED Mini V2 */

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@@ -17,11 +17,6 @@
#include "mx6_common.h"
#include <linux/sizes.h>
/* SATA Configs */
#ifdef CONFIG_CMD_SATA
#define CONFIG_LBA48
#endif
#ifdef CONFIG_CMD_NFS
#define NETWORKBOOT \
"setnetworkboot=" \

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@@ -44,7 +44,4 @@
#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
#define CONFIG_PHY_BASE_ADR 0
/* SATA driver configuration */
#define CONFIG_LBA48
#endif /* _CONFIG_GOFLEXHOME_H */

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@@ -28,13 +28,6 @@
/* MMC Configs */
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
/*
* SATA Configs
*/
#ifdef CONFIG_CMD_SATA
#define CONFIG_LBA48
#endif
/*
* PCI express
*/

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@@ -20,8 +20,6 @@
* Miscellaneous configurable options
*/
#define CONFIG_SYS_64BIT_LBA
/* Environment data setup
*/
#define CONFIG_SYS_NVRAM_BASE_ADDR 0xfff88000 /* NVRAM base address */

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@@ -21,18 +21,6 @@
#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
#endif
/*
* SATA Driver configuration
*/
#ifdef CONFIG_SATA
#define CONFIG_SYS_64BIT_LBA
#define CONFIG_LBA48
#if defined(CONFIG_NETSPACE_MAX_V2) || defined(CONFIG_D2NET_V2) || \
defined(CONFIG_NET2BIG_V2)
#endif
#endif /* CONFIG_SATA */
/*
* Enable GPI0 support
*/

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@@ -94,9 +94,4 @@
#define CONFIG_PHY_BASE_ADR 7
#endif /* CONFIG_CMD_NET */
#ifdef CONFIG_SATA
#define CONFIG_SYS_64BIT_LBA
#define CONFIG_LBA48
#endif
#endif /* _CONFIG_LSXL_H */

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@@ -82,13 +82,6 @@
#define CONFIG_MXC_USB_FLAGS 0
#endif
/*
* SATA
*/
#ifdef CONFIG_CMD_SATA
#define CONFIG_LBA48
#endif
/*
* LCD
*/

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@@ -36,12 +36,6 @@
#define CONFIG_USB_MAX_CONTROLLER_COUNT (3 + 3)
/*
* SATA/SCSI/AHCI configuration
*/
#define CONFIG_LBA48
#define CONFIG_SYS_64BIT_LBA
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 1) \
func(MMC, mmc, 0) \

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@@ -31,12 +31,6 @@
/* USB ethernet */
/*
* SATA/SCSI/AHCI configuration
*/
#define CONFIG_LBA48
#define CONFIG_SYS_64BIT_LBA
/*
* PCI configuration
*/

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@@ -100,10 +100,6 @@
#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
#ifdef CONFIG_CMD_SATA
#define CONFIG_LBA48
#endif
/* Framebuffer and LCD */
#endif /* __CONFIG_H */

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@@ -16,11 +16,6 @@
/* MMC Configs */
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
/* SATA Configuration */
#ifdef CONFIG_CMD_SATA
#define CONFIG_LBA48
#endif
/* Framebuffer */
#define CONFIG_IMX_HDMI
#define CONFIG_IMX_VIDEO_SKIP

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@@ -19,13 +19,6 @@
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_USDHC_NUM 2
/*
* SATA Configs
*/
#ifdef CONFIG_CMD_SATA
#define CONFIG_LBA48
#endif
#define IMX_FEC_BASE ENET_BASE_ADDR
#define CONFIG_FEC_MXC_PHYADDR 6

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@@ -59,9 +59,6 @@
#define CONFIG_POWER_PFUZE100
#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
/* SATA Configs */
#define CONFIG_LBA48
/* UART */
#define CONFIG_MXC_UART_BASE UART2_BASE

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@@ -25,8 +25,4 @@
#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
#define CONFIG_PHY_BASE_ADR 1
/* Support large HDDs for USB and SATA */
#define CONFIG_LBA48
#define CONFIG_SYS_64BIT_LBA
#endif /* _CONFIG_NSA310S_H */

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@@ -7,15 +7,6 @@
#ifndef __CONFIG_H__
#define __CONFIG_H__
/*
* SATA/SCSI/AHCI configuration
*/
/* AHCI support Definitions */
/** Enable 48-bit SATA addressing */
#define CONFIG_LBA48
/** Enable 64-bit addressing */
#define CONFIG_SYS_64BIT_LBA
#include "octeon_common.h"
#endif /* __CONFIG_H__ */

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@@ -44,14 +44,6 @@
/** Heap size for U-Boot */
/* AHCI support Definitions */
#ifdef CONFIG_DM_SCSI
/** Enable 48-bit SATA addressing */
# define CONFIG_LBA48
/** Enable 64-bit addressing */
# define CONFIG_SYS_64BIT_LBA
#endif
#define CONFIG_SYS_MMC_MAX_BLK_COUNT 8192
/** EMMC specific defines */

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@@ -112,8 +112,6 @@
#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
#define CONFIG_LBA48
#define CONFIG_HWCONFIG
/*
* These can be toggled for performance analysis, otherwise use default.

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@@ -39,10 +39,4 @@
#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
#define CONFIG_PHY_BASE_ADR 0
/*
* Support large disk for SATA and USB
*/
#define CONFIG_SYS_64BIT_LBA
#define CONFIG_LBA48
#endif /* _CONFIG_POGO_V4_H */

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@@ -60,8 +60,6 @@ extern unsigned long long get_phys_ccsrbar_addr_early(void);
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
#define CONFIG_LBA48
/* RTC */
#define CONFIG_RTC_PT7C4338

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@@ -27,10 +27,4 @@
#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
#define CONFIG_PHY_BASE_ADR 0
/*
* Support large disk for SATA and USB
*/
#define CONFIG_SYS_64BIT_LBA
#define CONFIG_LBA48
#endif /* _CONFIG_SHEEVAPLUG_H */

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@@ -75,10 +75,6 @@
#define PHYS_SDRAM_0 CONFIG_SYS_SDRAM_BASE
#define PHYS_SDRAM_0_SIZE 0x80000000 /* 2 GiB */
#ifdef CONFIG_AHCI
#define CONFIG_SYS_64BIT_LBA
#endif
#ifdef CONFIG_NAND_SUNXI
#define CONFIG_SYS_NAND_MAX_ECCPOS 1664
#define CONFIG_SYS_MAX_NAND_DEVICE 8

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@@ -31,12 +31,6 @@
#define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(7, 12)
#endif
/* SATA */
#ifdef CONFIG_CMD_SATA
#define CONFIG_LBA48
#define CONFIG_SYS_64BIT_LBA
#endif
/* USB */
#ifdef CONFIG_CMD_USB
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)

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@@ -40,9 +40,6 @@
"fdt_high=0x10000000\0" \
"initrd_high=0x10000000\0"
/* SATA support */
#define CONFIG_LBA48
/* FPGA programming support */
#define CONFIG_FPGA_STRATIX_V

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@@ -14,9 +14,6 @@
#define CONFIG_MXC_UART_BASE UART2_BASE
/* SATA Configs */
#define CONFIG_LBA48
/* MMC Configuration */
#define CONFIG_SYS_FSL_ESDHC_ADDR 0

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@@ -14,12 +14,6 @@
#define CONFIG_MXC_UART_BASE UART1_BASE
/* SATA Configs */
#ifdef CONFIG_CMD_SATA
#define CONFIG_LBA48
#endif
/* MMC Configuration */
#define CONFIG_SYS_FSL_USDHC_NUM 2
#define CONFIG_SYS_FSL_ESDHC_ADDR 0

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@@ -16,13 +16,6 @@
*/
#define CONFIG_SYS_BOOTM_LEN (16 << 20)
/* SATA AHCI storage */
#ifdef CONFIG_SCSI_AHCI
#define CONFIG_LBA48
#define CONFIG_SYS_64BIT_LBA
#endif
/* Generic TPM interfaced through LPC bus */
#define CONFIG_TPM_TIS_BASE_ADDRESS 0xfed40000