ColdFire: Add M5373EVB platform support - 2
Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com> Signed-off by: John Rigby <jrigby@freescale.com>
This commit is contained in:
TsiChungLiew
@@ -169,7 +169,7 @@
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#endif
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#endif /* CONFIG_M5282 */
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#ifdef CONFIG_M5329
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#if defined(CONFIG_M5329) || defined(CONFIG_M5373)
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#include <asm/immap_5329.h>
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#include <asm/m5329.h>
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@@ -197,7 +197,7 @@
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#define CFG_INTR_BASE (MMAP_INTC0)
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#define CFG_NUM_IRQS (128)
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#endif /* CONFIG_M5329 */
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#endif /* CONFIG_M5329 && CONFIG_M5373 */
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#ifdef CONFIG_M54455
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#include <asm/immap_5445x.h>
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@@ -378,91 +378,133 @@ typedef struct rcm {
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/* GPIO port registers */
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typedef struct gpio_ctrl {
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/* Port Output Data Registers */
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#ifdef CONFIG_M5329
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u8 podr_fech; /* 0x00 */
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u8 podr_fecl; /* 0x01 */
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#else
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u16 res00; /* 0x00 - 0x01 */
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#endif
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u8 podr_ssi; /* 0x02 */
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u8 podr_busctl; /* 0x03 */
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u8 podr_be; /* 0x04 */
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u8 podr_cs; /* 0x05 */
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u8 podr_pwm; /* 0x06 */
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u8 podr_feci2c; /* 0x07 */
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u8 res1; /* 0x08 */
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u8 res08; /* 0x08 */
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u8 podr_uart; /* 0x09 */
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u8 podr_qspi; /* 0x0A */
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u8 podr_timer; /* 0x0B */
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u8 res2; /* 0x0C */
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#ifdef CONFIG_M5329
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u8 res0C; /* 0x0C */
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u8 podr_lcddatah; /* 0x0D */
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u8 podr_lcddatam; /* 0x0E */
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u8 podr_lcddatal; /* 0x0F */
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u8 podr_lcdctlh; /* 0x10 */
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u8 podr_lcdctll; /* 0x11 */
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#else
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u16 res0C; /* 0x0C - 0x0D */
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u8 podr_fech; /* 0x0E */
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u8 podr_fecl; /* 0x0F */
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u16 res10[3]; /* 0x10 - 0x15 */
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#endif
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/* Port Data Direction Registers */
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u16 res3; /* 0x12 - 0x13 */
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#ifdef CONFIG_M5329
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u16 res12; /* 0x12 - 0x13 */
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u8 pddr_fech; /* 0x14 */
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u8 pddr_fecl; /* 0x15 */
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#endif
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u8 pddr_ssi; /* 0x16 */
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u8 pddr_busctl; /* 0x17 */
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u8 pddr_be; /* 0x18 */
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u8 pddr_cs; /* 0x19 */
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u8 pddr_pwm; /* 0x1A */
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u8 pddr_feci2c; /* 0x1B */
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u8 res4; /* 0x1C */
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u8 res1C; /* 0x1C */
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u8 pddr_uart; /* 0x1D */
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u8 pddr_qspi; /* 0x1E */
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u8 pddr_timer; /* 0x1F */
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u8 res5; /* 0x20 */
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#ifdef CONFIG_M5329
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u8 res20; /* 0x20 */
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u8 pddr_lcddatah; /* 0x21 */
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u8 pddr_lcddatam; /* 0x22 */
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u8 pddr_lcddatal; /* 0x23 */
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u8 pddr_lcdctlh; /* 0x24 */
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u8 pddr_lcdctll; /* 0x25 */
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u16 res6; /* 0x26 - 0x27 */
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u16 res26; /* 0x26 - 0x27 */
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#else
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u16 res20; /* 0x20 - 0x21 */
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u8 pddr_fech; /* 0x22 */
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u8 pddr_fecl; /* 0x23 */
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u16 res24[3]; /* 0x24 - 0x29 */
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#endif
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/* Port Data Direction Registers */
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#ifdef CONFIG_M5329
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u8 ppd_fech; /* 0x28 */
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u8 ppd_fecl; /* 0x29 */
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#endif
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u8 ppd_ssi; /* 0x2A */
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u8 ppd_busctl; /* 0x2B */
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u8 ppd_be; /* 0x2C */
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u8 ppd_cs; /* 0x2D */
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u8 ppd_pwm; /* 0x2E */
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u8 ppd_feci2c; /* 0x2F */
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u8 res7; /* 0x30 */
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u8 res30; /* 0x30 */
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u8 ppd_uart; /* 0x31 */
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u8 ppd_qspi; /* 0x32 */
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u8 ppd_timer; /* 0x33 */
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u8 res8; /* 0x34 */
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#ifdef CONFIG_M5329
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u8 res34; /* 0x34 */
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u8 ppd_lcddatah; /* 0x35 */
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u8 ppd_lcddatam; /* 0x36 */
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u8 ppd_lcddatal; /* 0x37 */
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u8 ppd_lcdctlh; /* 0x38 */
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u8 ppd_lcdctll; /* 0x39 */
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u16 res9; /* 0x3A - 0x3B */
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u16 res3A; /* 0x3A - 0x3B */
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#else
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u16 res34; /* 0x34 - 0x35 */
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u8 ppd_fech; /* 0x36 */
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u8 ppd_fecl; /* 0x37 */
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u16 res38[3]; /* 0x38 - 0x3D */
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#endif
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/* Port Clear Output Data Registers */
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u8 pclrr_fech; /* 0x3C */
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u8 pclrr_fecl; /* 0x3D */
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#ifdef CONFIG_M5329
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u8 res3C; /* 0x3C */
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u8 pclrr_fech; /* 0x3D */
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u8 pclrr_fecl; /* 0x3E */
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#else
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u8 pclrr_ssi; /* 0x3E */
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#endif
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u8 pclrr_busctl; /* 0x3F */
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u8 pclrr_be; /* 0x40 */
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u8 pclrr_cs; /* 0x41 */
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u8 pclrr_pwm; /* 0x42 */
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u8 pclrr_feci2c; /* 0x43 */
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u8 res10; /* 0x44 */
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u8 res44; /* 0x44 */
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u8 pclrr_uart; /* 0x45 */
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u8 pclrr_qspi; /* 0x46 */
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u8 pclrr_timer; /* 0x47 */
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u8 res11; /* 0x48 */
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u8 pclrr_lcddatah; /* 0x49 */
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u8 pclrr_lcddatam; /* 0x4A */
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u8 pclrr_lcddatal; /* 0x4B */
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#ifdef CONFIG_M5329
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u8 pclrr_lcddatah; /* 0x48 */
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u8 pclrr_lcddatam; /* 0x49 */
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u8 pclrr_lcddatal; /* 0x4A */
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u8 pclrr_ssi; /* 0x4B */
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u8 pclrr_lcdctlh; /* 0x4C */
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u8 pclrr_lcdctll; /* 0x4D */
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u16 res12; /* 0x4E - 0x4F */
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u16 res4E; /* 0x4E - 0x4F */
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#else
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u16 res48; /* 0x48 - 0x49 */
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u8 pclrr_fech; /* 0x4A */
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u8 pclrr_fecl; /* 0x4B */
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u8 res4C[5]; /* 0x4C - 0x50 */
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#endif
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/* Pin Assignment Registers */
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#ifdef CONFIG_M5329
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u8 par_fec; /* 0x50 */
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#endif
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u8 par_pwm; /* 0x51 */
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u8 par_busctl; /* 0x52 */
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u8 par_feci2c; /* 0x53 */
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@@ -472,15 +514,20 @@ typedef struct gpio_ctrl {
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u16 par_uart; /* 0x58 */
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u16 par_qspi; /* 0x5A */
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u8 par_timer; /* 0x5C */
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#ifdef CONFIG_M5329
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u8 par_lcddata; /* 0x5D */
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u16 par_lcdctl; /* 0x5E */
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#else
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u8 par_fec; /* 0x5D */
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u16 res5E; /* 0x5E - 0x5F */
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#endif
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u16 par_irq; /* 0x60 */
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u16 res16; /* 0x62 - 0x63 */
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u16 res62; /* 0x62 - 0x63 */
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/* Mode Select Control Registers */
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u8 mscr_flexbus; /* 0x64 */
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u8 mscr_sdram; /* 0x65 */
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u16 res17; /* 0x66 - 0x67 */
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u16 res66; /* 0x66 - 0x67 */
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/* Drive Strength Control Registers */
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u8 dscr_i2c; /* 0x68 */
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@@ -490,7 +537,11 @@ typedef struct gpio_ctrl {
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u8 dscr_qspi; /* 0x6C */
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u8 dscr_timer; /* 0x6D */
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u8 dscr_ssi; /* 0x6E */
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#ifdef CONFIG_M5329
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u8 dscr_lcd; /* 0x6F */
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#else
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u8 res6F; /* 0x6F */
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#endif
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u8 dscr_debug; /* 0x70 */
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u8 dscr_clkrst; /* 0x71 */
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u8 dscr_irq; /* 0x72 */
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@@ -1118,6 +1118,7 @@
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#define GPIO_PCLRR_LCDCTLL7 (0x80)
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/* Bit definitions and macros for GPIO_PAR_FEC */
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#ifdef CONFIG_M5329
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#define GPIO_PAR_FEC_MII(x) (((x)&0x03)<<0)
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#define GPIO_PAR_FEC_7W(x) (((x)&0x03)<<2)
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#define GPIO_PAR_FEC_7W_GPIO (0x00)
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@@ -1126,6 +1127,10 @@
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#define GPIO_PAR_FEC_MII_GPIO (0x00)
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#define GPIO_PAR_FEC_MII_UART (0x01)
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#define GPIO_PAR_FEC_MII_FEC (0x03)
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#else
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#define GPIO_PAR_FEC_7W_FEC (0x08)
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#define GPIO_PAR_FEC_MII_FEC (0x02)
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#endif
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/* Bit definitions and macros for GPIO_PAR_PWM */
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#define GPIO_PAR_PWM1(x) (((x)&0x03)<<0)
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267
include/configs/M5373EVB.h
Normal file
267
include/configs/M5373EVB.h
Normal file
@@ -0,0 +1,267 @@
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/*
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* Configuation settings for the Freescale MCF5373 FireEngine board.
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*
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* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
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* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* board/config.h - configuration options, board specific
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*/
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#ifndef _M5373EVB_H
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#define _M5373EVB_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_MCF532x /* define processor family */
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#define CONFIG_M5373 /* define processor type */
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#undef DEBUG
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#define CONFIG_MCFUART
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#define CFG_UART_PORT (0)
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#define CONFIG_BAUDRATE 115200
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#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
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#undef CONFIG_WATCHDOG
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#define CONFIG_WATCHDOG_TIMEOUT 3360 /* timeout in ms, max is 3.36 sec */
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/* Command line configuration */
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#include <config_cmd_default.h>
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#define CONFIG_CMD_CACHE
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#define CONFIG_CMD_DATE
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#define CONFIG_CMD_ELF
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#define CONFIG_CMD_FLASH
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_MEMORY
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#define CONFIG_CMD_MISC
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_NET
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_REGINFO
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#ifdef NANDFLASH_SIZE
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# define CONFIG_CMD_NAND
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#endif
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#define CFG_UNIFY_CACHE
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#define CONFIG_MCFFEC
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#ifdef CONFIG_MCFFEC
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# define CONFIG_NET_MULTI 1
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# define CONFIG_MII 1
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# define CFG_DISCOVER_PHY
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# define CFG_RX_ETH_BUFFER 8
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# define CFG_FAULT_ECHO_LINK_DOWN
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# define CFG_FEC0_PINMUX 0
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# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE
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# define MCFFEC_TOUT_LOOP 50000
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/* If CFG_DISCOVER_PHY is not defined - hardcoded */
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# ifndef CFG_DISCOVER_PHY
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# define FECDUPLEX FULL
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# define FECSPEED _100BASET
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# else
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# ifndef CFG_FAULT_ECHO_LINK_DOWN
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# define CFG_FAULT_ECHO_LINK_DOWN
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# endif
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# endif /* CFG_DISCOVER_PHY */
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#endif
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#define CONFIG_MCFRTC
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#undef RTC_DEBUG
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/* Timer */
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#define CONFIG_MCFTMR
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#undef CONFIG_MCFPIT
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/* I2C */
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#define CONFIG_FSL_I2C
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#define CONFIG_HARD_I2C /* I2C with hw support */
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#undef CONFIG_SOFT_I2C /* I2C bit-banged */
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#define CFG_I2C_SPEED 80000
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#define CFG_I2C_SLAVE 0x7F
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#define CFG_I2C_OFFSET 0x58000
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#define CFG_IMMR CFG_MBAR
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#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
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#define CONFIG_UDP_CHECKSUM
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#ifdef CONFIG_MCFFEC
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# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
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# define CONFIG_IPADDR 192.162.1.2
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# define CONFIG_NETMASK 255.255.255.0
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# define CONFIG_SERVERIP 192.162.1.1
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# define CONFIG_GATEWAYIP 192.162.1.1
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# define CONFIG_OVERWRITE_ETHADDR_ONCE
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#endif /* FEC_ENET */
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#define CONFIG_HOSTNAME M5373EVB
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"netdev=eth0\0" \
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"loadaddr=" MK_STR(CFG_LOAD_ADDR) "\0" \
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"u-boot=u-boot.bin\0" \
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"load=tftp ${loadaddr) ${u-boot}\0" \
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"upd=run load; run prog\0" \
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"prog=prot off 0 2ffff;" \
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"era 0 2ffff;" \
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"cp.b ${loadaddr} 0 ${filesize};" \
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"save\0" \
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""
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#define CONFIG_PRAM 512 /* 512 KB */
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#define CFG_PROMPT "-> "
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#define CFG_LONGHELP /* undef to save memory */
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#ifdef CONFIG_CMD_KGDB
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# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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# define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_LOAD_ADDR 0x40010000
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#define CFG_HZ 1000
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#define CFG_CLK 80000000
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#define CFG_CPU_CLK CFG_CLK * 3
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#define CFG_MBAR 0xFC000000
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#define CFG_LATCH_ADDR (CFG_CS1_BASE + 0x80000)
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/*
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* Low Level Configuration Settings
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* (address mappings, register initial values, etc.)
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* You should know what you are doing if you make changes here.
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*/
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/*-----------------------------------------------------------------------
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* Definitions for initial stack pointer and data area (in DPRAM)
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*/
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#define CFG_INIT_RAM_ADDR 0x80000000
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#define CFG_INIT_RAM_END 0x8000 /* End of used area in internal SRAM */
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#define CFG_INIT_RAM_CTRL 0x221
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#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
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#define CFG_GBL_DATA_OFFSET ((CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) - 0x10)
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
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/*-----------------------------------------------------------------------
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CFG_SDRAM_BASE _must_ start at 0
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*/
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#define CFG_SDRAM_BASE 0x40000000
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#define CFG_SDRAM_SIZE 32 /* SDRAM size in MB */
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#define CFG_SDRAM_CFG1 0x53722730
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#define CFG_SDRAM_CFG2 0x56670000
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#define CFG_SDRAM_CTRL 0xE1092000
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#define CFG_SDRAM_EMOD 0x40010000
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#define CFG_SDRAM_MODE 0x018D0000
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#define CFG_MEMTEST_START CFG_SDRAM_BASE + 0x400
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#define CFG_MEMTEST_END ((CFG_SDRAM_SIZE - 3) << 20)
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#define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400)
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#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
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#define CFG_BOOTPARAMS_LEN 64*1024
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#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
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/*
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* For booting Linux, the board info and command line data
|
||||
* have to be in the first 8 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization ??
|
||||
*/
|
||||
#define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20))
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization
|
||||
*/
|
||||
#define CFG_FLASH_CFI
|
||||
#ifdef CFG_FLASH_CFI
|
||||
# define CFG_FLASH_CFI_DRIVER 1
|
||||
# define CFG_FLASH_SIZE 0x800000 /* Max size that the board might have */
|
||||
# define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT
|
||||
# define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
|
||||
# define CFG_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
|
||||
# define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
|
||||
#endif
|
||||
|
||||
#ifdef NANDFLASH_SIZE
|
||||
# define CFG_MAX_NAND_DEVICE 1
|
||||
# define CFG_NAND_BASE CFG_CS2_BASE
|
||||
# define CFG_NAND_SIZE 1
|
||||
# define CFG_NAND_BASE_LIST { CFG_NAND_BASE }
|
||||
# define NAND_MAX_CHIPS 1
|
||||
# define NAND_ALLOW_ERASE_ALL 1
|
||||
# define CONFIG_JFFS2_NAND 1
|
||||
# define CONFIG_JFFS2_DEV "nand0"
|
||||
# define CONFIG_JFFS2_PART_SIZE (CFG_CS2_MASK & ~1)
|
||||
# define CONFIG_JFFS2_PART_OFFSET 0x00000000
|
||||
#endif
|
||||
|
||||
#define CFG_FLASH_BASE CFG_CS0_BASE
|
||||
|
||||
/* Configuration for environment
|
||||
* Environment is embedded in u-boot in the second sector of the flash
|
||||
*/
|
||||
#define CFG_ENV_OFFSET 0x4000
|
||||
#define CFG_ENV_SECT_SIZE 0x2000
|
||||
#define CFG_ENV_IS_IN_FLASH 1
|
||||
#define CFG_ENV_IS_EMBEDDED 1
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration
|
||||
*/
|
||||
#define CFG_CACHELINE_SIZE 16
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Chipselect bank definitions
|
||||
*/
|
||||
/*
|
||||
* CS0 - NOR Flash 1, 2, 4, or 8MB
|
||||
* CS1 - CompactFlash and registers
|
||||
* CS2 - NAND Flash 16, 32, or 64MB
|
||||
* CS3 - Available
|
||||
* CS4 - Available
|
||||
* CS5 - Available
|
||||
*/
|
||||
#define CFG_CS0_BASE 0
|
||||
#define CFG_CS0_MASK 0x007f0001
|
||||
#define CFG_CS0_CTRL 0x00001fa0
|
||||
|
||||
#define CFG_CS1_BASE 0x10000000
|
||||
#define CFG_CS1_MASK 0x001f0001
|
||||
#define CFG_CS1_CTRL 0x002A3780
|
||||
|
||||
#ifdef NANDFLASH_SIZE
|
||||
#define CFG_CS2_BASE 0x20000000
|
||||
#define CFG_CS2_MASK ((NANDFLASH_SIZE << 20) | 1)
|
||||
#define CFG_CS2_CTRL 0x00001f60
|
||||
#endif
|
||||
|
||||
#endif /* _M5373EVB_H */
|
||||
Reference in New Issue
Block a user