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Merge branch 'rmobile' of git://git.denx.de/u-boot-sh

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This commit is contained in:
Tom Rini
2017-08-02 19:30:27 -04:00
parent ec7483e34e 9c552db619
commit a89302cc79
98 changed files with 6282 additions and 47 deletions
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1
include/configs/MigoR.h
View File

@@ -37,7 +37,6 @@
#define CONFIG_SYS_BAUDRATE_TABLE { 115200 } /* List of legal baudrate settings for this board */
/* SCIF */
#define CONFIG_SCIF_CONSOLE 1
#define CONFIG_CONS_SCIF0 1
#define CONFIG_SYS_MEMTEST_START (MIGO_R_SDRAM_BASE)

1
include/configs/alt.h
View File

@@ -37,7 +37,6 @@
#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024)
/* SCIF */
#define CONFIG_SCIF_CONSOLE
/* FLASH */
#define CONFIG_SPI

1
include/configs/ap325rxa.h
View File

@@ -47,7 +47,6 @@
#define CONFIG_SYS_BAUDRATE_TABLE { 38400 }
/* SCIF */
#define CONFIG_SCIF_CONSOLE 1
#define CONFIG_SCIF_A 1 /* SH7723 has SCIF and SCIFA */
#define CONFIG_CONS_SCIF5 1

1
include/configs/ap_sh4a_4a.h
View File

@@ -49,7 +49,6 @@
#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
/* SCIF */
#define CONFIG_SCIF_CONSOLE 1
#define CONFIG_SCIF 1
#define CONFIG_CONS_SCIF4 1

1
include/configs/armadillo-800eva.h
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@@ -46,7 +46,6 @@
#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
/* SCIF */
#define CONFIG_SCIF_CONSOLE
#define CONFIG_CONS_SCIF1
#define SCIF0_BASE 0xe6c40000
#define SCIF1_BASE 0xe6c50000

1
include/configs/blanche.h
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@@ -28,7 +28,6 @@
#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024)
/* SCIF */
#define CONFIG_SCIF_CONSOLE
#define CONFIG_CONS_SCIF0
#define CONFIG_SYS_MEMTEST_START (RCAR_GEN2_SDRAM_BASE)

1
include/configs/ecovec.h
View File

@@ -81,7 +81,6 @@
#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
/* SCIF */
#define CONFIG_SCIF_CONSOLE 1
#define CONFIG_SCIF 1
#define CONFIG_CONS_SCIF0 1

1
include/configs/espt.h
View File

@@ -26,7 +26,6 @@
#undef CONFIG_SHOW_BOOT_PROGRESS
/* SCIF */
#define CONFIG_SCIF_CONSOLE 1
#define CONFIG_CONS_SCIF0 1
#define CONFIG_SYS_TEXT_BASE 0x8FFC0000

1
include/configs/gose.h
View File

@@ -38,7 +38,6 @@
#define RCAR_GEN2_UBOOT_SDRAM_SIZE 0x20000000
/* SCIF */
#define CONFIG_SCIF_CONSOLE
/* FLASH */
#define CONFIG_SPI

1
include/configs/koelsch.h
View File

@@ -38,7 +38,6 @@
#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024)
/* SCIF */
#define CONFIG_SCIF_CONSOLE
/* FLASH */
#define CONFIG_SPI

1
include/configs/kzm9g.h
View File

@@ -49,7 +49,6 @@
#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
/* SCIF */
#define CONFIG_SCIF_CONSOLE
#define CONFIG_CONS_SCIF4
#define CONFIG_SYS_MEMTEST_START (KZM_SDRAM_BASE)

1
include/configs/lager.h
View File

@@ -38,7 +38,6 @@
#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024)
/* SCIF */
#define CONFIG_SCIF_CONSOLE
/* SPI */
#define CONFIG_SPI

1
include/configs/mpr2.h
View File

@@ -64,7 +64,6 @@
#define CONFIG_SYS_TMU_CLK_DIV 4 /* 4 (default), 16, 64, 256 or 1024 */
/* UART */
#define CONFIG_SCIF_CONSOLE 1
#define CONFIG_CONS_SCIF0 1
#endif /* __MPR2_H */

1
include/configs/ms7720se.h
View File

@@ -38,7 +38,6 @@
#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
/* SCIF */
#define CONFIG_SCIF_CONSOLE 1
#define CONFIG_CONS_SCIF0 1
#define CONFIG_SYS_MEMTEST_START MS7720SE_SDRAM_BASE

1
include/configs/ms7722se.h
View File

@@ -37,7 +37,6 @@
#define CONFIG_SYS_BAUDRATE_TABLE { 115200 } /* List of legal baudrate settings for this board */
/* SCIF */
#define CONFIG_SCIF_CONSOLE 1
#define CONFIG_CONS_SCIF0 1
#define CONFIG_SYS_MEMTEST_START (MS7722SE_SDRAM_BASE)

1
include/configs/ms7750se.h
View File

@@ -20,7 +20,6 @@
/*
* Command line configuration.
*/
#define CONFIG_SCIF_CONSOLE 1
#define CONFIG_CONS_SCIF1 1
#define CONFIG_BOOTARGS "console=ttySC0,38400"

1
include/configs/porter.h
View File

@@ -38,7 +38,6 @@
#define RCAR_GEN2_UBOOT_SDRAM_SIZE (1024u * 1024 * 1024)
/* SCIF */
#define CONFIG_SCIF_CONSOLE
/* FLASH */
#define CONFIG_SPI

1
include/configs/r0p7734.h
View File

@@ -54,7 +54,6 @@
#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
/* SCIF */
#define CONFIG_SCIF_CONSOLE 1
#define CONFIG_SCIF 1
#define CONFIG_CONS_SCIF3 1

1
include/configs/r2dplus.h
View File

@@ -15,7 +15,6 @@
#define CONFIG_CMD_SH_ZIMAGEBOOT
/* SCIF */
#define CONFIG_SCIF_CONSOLE 1
#define CONFIG_CONS_SCIF1 1
#define CONFIG_BOOTARGS "console=ttySC0,115200"

1
include/configs/r7780mp.h
View File

@@ -23,7 +23,6 @@
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_PCI
#define CONFIG_SCIF_CONSOLE 1
#define CONFIG_CONS_SCIF0 1
#define CONFIG_BOOTARGS "console=ttySC0,115200"

10
include/configs/rcar-gen3-common.h
View File

@@ -39,12 +39,12 @@
#define CONFIG_SH_GPIO_PFC
/* console */
#define CONFIG_SYS_CBSIZE 2048
#define CONFIG_SYS_PBSIZE \
(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_SYS_LONGHELP
#define CONFIG_SYS_CBSIZE 256
#define CONFIG_SYS_PBSIZE 256
#define CONFIG_SYS_MAXARGS 16
#define CONFIG_SYS_BARGSIZE 512
#define CONFIG_SYS_MAXARGS 64
#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400 }
/* MEMORY */

1
include/configs/rsk7203.h
View File

@@ -37,7 +37,6 @@
#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
/* SCIF */
#define CONFIG_SCIF_CONSOLE 1
#define CONFIG_CONS_SCIF0 1
#define CONFIG_SYS_MEMTEST_START RSK7203_SDRAM_BASE

1
include/configs/rsk7264.h
View File

@@ -25,7 +25,6 @@
#define CONFIG_SYS_MAXARGS 16 /* max args accepted for monitor commands */
/* Serial */
#define CONFIG_SCIF_CONSOLE 1
#define CONFIG_CONS_SCIF3 1
/* Memory */

1
include/configs/rsk7269.h
View File

@@ -24,7 +24,6 @@
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
/* Serial */
#define CONFIG_SCIF_CONSOLE
#define CONFIG_CONS_SCIF7
/* Memory */

1
include/configs/salvator-x.h
View File

@@ -17,7 +17,6 @@
#include "rcar-gen3-common.h"
/* SCIF */
#define CONFIG_SCIF_CONSOLE
#define CONFIG_CONS_SCIF2
#define CONFIG_CONS_INDEX 2
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_S3D4_CLK_FREQ

1
include/configs/sh7752evb.h
View File

@@ -35,7 +35,6 @@
#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
/* SCIF */
#define CONFIG_SCIF_CONSOLE 1
#define CONFIG_CONS_SCIF2 1
#define CONFIG_SYS_MEMTEST_START (SH7752EVB_SDRAM_BASE)

1
include/configs/sh7753evb.h
View File

@@ -35,7 +35,6 @@
#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
/* SCIF */
#define CONFIG_SCIF_CONSOLE 1
#define CONFIG_CONS_SCIF2 1
#define CONFIG_SYS_MEMTEST_START (SH7753EVB_SDRAM_BASE)

1
include/configs/sh7757lcr.h
View File

@@ -36,7 +36,6 @@
#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
/* SCIF */
#define CONFIG_SCIF_CONSOLE 1
#define CONFIG_CONS_SCIF2 1
#define CONFIG_SYS_MEMTEST_START (SH7757LCR_SDRAM_BASE)

1
include/configs/sh7763rdp.h
View File

@@ -26,7 +26,6 @@
#undef CONFIG_SHOW_BOOT_PROGRESS
/* SCIF */
#define CONFIG_SCIF_CONSOLE 1
#define CONFIG_CONS_SCIF2 1
#define CONFIG_SYS_TEXT_BASE 0x8FFC0000

1
include/configs/sh7785lcr.h
View File

@@ -53,7 +53,6 @@
#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
/* SCIF */
#define CONFIG_SCIF_CONSOLE 1
#define CONFIG_CONS_SCIF1 1
#define CONFIG_SCIF_EXT_CLOCK 1

1
include/configs/shmin.h
View File

@@ -41,7 +41,6 @@
#define CONFIG_SYS_BAUDRATE_TABLE { 9600,14400,19200,38400,57600,115200 }
/* SCIF */
#define CONFIG_SCIF_CONSOLE 1
#define CONFIG_CONS_SCIF0 1
/* memory */

1
include/configs/silk.h
View File

@@ -38,7 +38,6 @@
#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024)
/* SCIF */
#define CONFIG_SCIF_CONSOLE
/* FLASH */
#define CONFIG_SPI

1
include/configs/stout.h
View File

@@ -40,7 +40,6 @@
#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024)
/* SCIF */
#define CONFIG_SCIF_CONSOLE
#define CONFIG_SCIF_A
/* SPI */

109
include/configs/ulcb.h Normal file
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@@ -0,0 +1,109 @@
/*
* include/configs/ulcb.h
* This file is ULCB board configuration.
*
* Copyright (C) 2017 Renesas Electronics Corporation
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ULCB_H
#define __ULCB_H
#undef DEBUG
#define CONFIG_RCAR_BOARD_STRING "ULCB"
#include "rcar-gen3-common.h"
/* M3 ULCB has 2 banks, each with 1 GiB of RAM */
#if defined(CONFIG_R8A7796)
#undef PHYS_SDRAM_1_SIZE
#undef PHYS_SDRAM_2_SIZE
#define PHYS_SDRAM_1_SIZE (0x40000000u - DRAM_RSV_SIZE)
#define PHYS_SDRAM_2_SIZE 0x40000000u
#endif
/* SCIF */
#define CONFIG_CONS_SCIF2
#define CONFIG_CONS_INDEX 2
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_S3D4_CLK_FREQ
/* [A] Hyper Flash */
/* use to RPC(SPI Multi I/O Bus Controller) */
/* Ethernet RAVB */
#define CONFIG_NET_MULTI
#define CONFIG_PHY_MICREL
#define CONFIG_BITBANGMII
#define CONFIG_BITBANGMII_MULTI
/* Board Clock */
/* XTAL_CLK : 33.33MHz */
#define RCAR_XTAL_CLK 33333333u
#define CONFIG_SYS_CLK_FREQ RCAR_XTAL_CLK
/* ch0to2 CPclk, ch3to11 S3D2_PEREclk, ch12to14 S3D2_RTclk */
/* CPclk 16.66MHz, S3D2 133.33MHz , S3D4 66.66MHz */
#define CONFIG_CP_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2)
#define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 192 / 2)
#define CONFIG_S3D2_CLK_FREQ (266666666u/2)
#define CONFIG_S3D4_CLK_FREQ (266666666u/4)
/* Generic Timer Definitions (use in assembler source) */
#define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */
/* Generic Interrupt Controller Definitions */
#define CONFIG_GICV2
#define GICD_BASE 0xF1010000
#define GICC_BASE 0xF1020000
/* CPLD SPI */
#define CONFIG_CMD_SPI
#define CONFIG_SOFT_SPI
#define SPI_DELAY udelay(0)
#define SPI_SDA(val) ulcb_softspi_sda(val)
#define SPI_SCL(val) ulcb_softspi_scl(val)
#define SPI_READ ulcb_softspi_read()
#ifndef __ASSEMBLY__
void ulcb_softspi_sda(int);
void ulcb_softspi_scl(int);
unsigned char ulcb_softspi_read(void);
#endif
/* i2c */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_SH
#define CONFIG_SYS_I2C_SLAVE 0x60
#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 1
#define CONFIG_SYS_I2C_SH_SPEED0 400000
#define CONFIG_SH_I2C_DATA_HIGH 4
#define CONFIG_SH_I2C_DATA_LOW 5
#define CONFIG_SH_I2C_CLOCK 10000000
#define CONFIG_SYS_I2C_POWERIC_ADDR 0x30
/* USB */
#ifdef CONFIG_R8A7795
#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
#else
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#endif
/* SDHI */
#define CONFIG_SH_SDHI_FREQ 200000000
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
#define CONFIG_SYS_MMC_ENV_DEV 1
#define CONFIG_SYS_MMC_ENV_PART 2
/* Module stop status bits */
/* MFIS, SCIF1 */
#define CONFIG_SMSTP2_ENA 0x00002040
/* SCIF2 */
#define CONFIG_SMSTP3_ENA 0x00000400
/* INTC-AP, IRQC */
#define CONFIG_SMSTP4_ENA 0x00000180
#endif /* __ULCB_H */

70
include/dt-bindings/clock/r8a7795-cpg-mssr.h Normal file
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@@ -0,0 +1,70 @@
/*
* Copyright (C) 2015 Renesas Electronics Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__
#define __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__
#include <dt-bindings/clock/renesas-cpg-mssr.h>
/* r8a7795 CPG Core Clocks */
#define R8A7795_CLK_Z 0
#define R8A7795_CLK_Z2 1
#define R8A7795_CLK_ZR 2
#define R8A7795_CLK_ZG 3
#define R8A7795_CLK_ZTR 4
#define R8A7795_CLK_ZTRD2 5
#define R8A7795_CLK_ZT 6
#define R8A7795_CLK_ZX 7
#define R8A7795_CLK_S0D1 8
#define R8A7795_CLK_S0D4 9
#define R8A7795_CLK_S1D1 10
#define R8A7795_CLK_S1D2 11
#define R8A7795_CLK_S1D4 12
#define R8A7795_CLK_S2D1 13
#define R8A7795_CLK_S2D2 14
#define R8A7795_CLK_S2D4 15
#define R8A7795_CLK_S3D1 16
#define R8A7795_CLK_S3D2 17
#define R8A7795_CLK_S3D4 18
#define R8A7795_CLK_LB 19
#define R8A7795_CLK_CL 20
#define R8A7795_CLK_ZB3 21
#define R8A7795_CLK_ZB3D2 22
#define R8A7795_CLK_CR 23
#define R8A7795_CLK_CRD2 24
#define R8A7795_CLK_SD0H 25
#define R8A7795_CLK_SD0 26
#define R8A7795_CLK_SD1H 27
#define R8A7795_CLK_SD1 28
#define R8A7795_CLK_SD2H 29
#define R8A7795_CLK_SD2 30
#define R8A7795_CLK_SD3H 31
#define R8A7795_CLK_SD3 32
#define R8A7795_CLK_SSP2 33
#define R8A7795_CLK_SSP1 34
#define R8A7795_CLK_SSPRS 35
#define R8A7795_CLK_RPC 36
#define R8A7795_CLK_RPCD2 37
#define R8A7795_CLK_MSO 38
#define R8A7795_CLK_CANFD 39
#define R8A7795_CLK_HDMI 40
#define R8A7795_CLK_CSI0 41
#define R8A7795_CLK_CSIREF 42
#define R8A7795_CLK_CP 43
#define R8A7795_CLK_CPEX 44
#define R8A7795_CLK_R 45
#define R8A7795_CLK_OSC 46
/* r8a7795 ES2.0 CPG Core Clocks */
#define R8A7795_CLK_S0D2 47
#define R8A7795_CLK_S0D3 48
#define R8A7795_CLK_S0D6 49
#define R8A7795_CLK_S0D8 50
#define R8A7795_CLK_S0D12 51
#endif /* __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__ */

69
include/dt-bindings/clock/r8a7796-cpg-mssr.h Normal file
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@@ -0,0 +1,69 @@
/*
* Copyright (C) 2016 Renesas Electronics Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef __DT_BINDINGS_CLOCK_R8A7796_CPG_MSSR_H__
#define __DT_BINDINGS_CLOCK_R8A7796_CPG_MSSR_H__
#include <dt-bindings/clock/renesas-cpg-mssr.h>
/* r8a7796 CPG Core Clocks */
#define R8A7796_CLK_Z 0
#define R8A7796_CLK_Z2 1
#define R8A7796_CLK_ZR 2
#define R8A7796_CLK_ZG 3
#define R8A7796_CLK_ZTR 4
#define R8A7796_CLK_ZTRD2 5
#define R8A7796_CLK_ZT 6
#define R8A7796_CLK_ZX 7
#define R8A7796_CLK_S0D1 8
#define R8A7796_CLK_S0D2 9
#define R8A7796_CLK_S0D3 10
#define R8A7796_CLK_S0D4 11
#define R8A7796_CLK_S0D6 12
#define R8A7796_CLK_S0D8 13
#define R8A7796_CLK_S0D12 14
#define R8A7796_CLK_S1D1 15
#define R8A7796_CLK_S1D2 16
#define R8A7796_CLK_S1D4 17
#define R8A7796_CLK_S2D1 18
#define R8A7796_CLK_S2D2 19
#define R8A7796_CLK_S2D4 20
#define R8A7796_CLK_S3D1 21
#define R8A7796_CLK_S3D2 22
#define R8A7796_CLK_S3D4 23
#define R8A7796_CLK_LB 24
#define R8A7796_CLK_CL 25
#define R8A7796_CLK_ZB3 26
#define R8A7796_CLK_ZB3D2 27
#define R8A7796_CLK_ZB3D4 28
#define R8A7796_CLK_CR 29
#define R8A7796_CLK_CRD2 30
#define R8A7796_CLK_SD0H 31
#define R8A7796_CLK_SD0 32
#define R8A7796_CLK_SD1H 33
#define R8A7796_CLK_SD1 34
#define R8A7796_CLK_SD2H 35
#define R8A7796_CLK_SD2 36
#define R8A7796_CLK_SD3H 37
#define R8A7796_CLK_SD3 38
#define R8A7796_CLK_SSP2 39
#define R8A7796_CLK_SSP1 40
#define R8A7796_CLK_SSPRS 41
#define R8A7796_CLK_RPC 42
#define R8A7796_CLK_RPCD2 43
#define R8A7796_CLK_MSO 44
#define R8A7796_CLK_CANFD 45
#define R8A7796_CLK_HDMI 46
#define R8A7796_CLK_CSI0 47
#define R8A7796_CLK_CSIREF 48
#define R8A7796_CLK_CP 49
#define R8A7796_CLK_CPEX 50
#define R8A7796_CLK_R 51
#define R8A7796_CLK_OSC 52
#endif /* __DT_BINDINGS_CLOCK_R8A7796_CPG_MSSR_H__ */

15
include/dt-bindings/clock/renesas-cpg-mssr.h Normal file
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@@ -0,0 +1,15 @@
/*
* Copyright (C) 2015 Renesas Electronics Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef __DT_BINDINGS_CLOCK_RENESAS_CPG_MSSR_H__
#define __DT_BINDINGS_CLOCK_RENESAS_CPG_MSSR_H__
#define CPG_CORE 0 /* Core Clock */
#define CPG_MOD 1 /* Module Clock */
#endif /* __DT_BINDINGS_CLOCK_RENESAS_CPG_MSSR_H__ */

42
include/dt-bindings/power/r8a7795-sysc.h Normal file
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@@ -0,0 +1,42 @@
/*
* Copyright (C) 2016 Glider bvba
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*/
#ifndef __DT_BINDINGS_POWER_R8A7795_SYSC_H__
#define __DT_BINDINGS_POWER_R8A7795_SYSC_H__
/*
* These power domain indices match the numbers of the interrupt bits
* representing the power areas in the various Interrupt Registers
* (e.g. SYSCISR, Interrupt Status Register)
*/
#define R8A7795_PD_CA57_CPU0 0
#define R8A7795_PD_CA57_CPU1 1
#define R8A7795_PD_CA57_CPU2 2
#define R8A7795_PD_CA57_CPU3 3
#define R8A7795_PD_CA53_CPU0 5
#define R8A7795_PD_CA53_CPU1 6
#define R8A7795_PD_CA53_CPU2 7
#define R8A7795_PD_CA53_CPU3 8
#define R8A7795_PD_A3VP 9
#define R8A7795_PD_CA57_SCU 12
#define R8A7795_PD_CR7 13
#define R8A7795_PD_A3VC 14
#define R8A7795_PD_3DG_A 17
#define R8A7795_PD_3DG_B 18
#define R8A7795_PD_3DG_C 19
#define R8A7795_PD_3DG_D 20
#define R8A7795_PD_CA53_SCU 21
#define R8A7795_PD_3DG_E 22
#define R8A7795_PD_A3IR 24
#define R8A7795_PD_A2VC0 25 /* ES1.x only */
#define R8A7795_PD_A2VC1 26
/* Always-on power area */
#define R8A7795_PD_ALWAYS_ON 32
#endif /* __DT_BINDINGS_POWER_R8A7795_SYSC_H__ */

36
include/dt-bindings/power/r8a7796-sysc.h Normal file
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@@ -0,0 +1,36 @@
/*
* Copyright (C) 2016 Glider bvba
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*/
#ifndef __DT_BINDINGS_POWER_R8A7796_SYSC_H__
#define __DT_BINDINGS_POWER_R8A7796_SYSC_H__
/*
* These power domain indices match the numbers of the interrupt bits
* representing the power areas in the various Interrupt Registers
* (e.g. SYSCISR, Interrupt Status Register)
*/
#define R8A7796_PD_CA57_CPU0 0
#define R8A7796_PD_CA57_CPU1 1
#define R8A7796_PD_CA53_CPU0 5
#define R8A7796_PD_CA53_CPU1 6
#define R8A7796_PD_CA53_CPU2 7
#define R8A7796_PD_CA53_CPU3 8
#define R8A7796_PD_CA57_SCU 12
#define R8A7796_PD_CR7 13
#define R8A7796_PD_A3VC 14
#define R8A7796_PD_3DG_A 17
#define R8A7796_PD_3DG_B 18
#define R8A7796_PD_CA53_SCU 21
#define R8A7796_PD_A3IR 24
#define R8A7796_PD_A2VC0 25
#define R8A7796_PD_A2VC1 26
/* Always-on power area */
#define R8A7796_PD_ALWAYS_ON 32
#endif /* __DT_BINDINGS_POWER_R8A7796_SYSC_H__ */