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mtd: spi-nor-core: Add support for volatile QE bit

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Some of Spansion/Cypress chips support volatile version of configuration
registers and it is recommended to update volatile registers in the field
application due to a risk of the non-volatile registers corruption by
power interrupt. This patch adds a function to set Quad Enable bit in CFR1
volatile.

Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
This commit is contained in:
Takahiro Kuwano
2021-06-29 15:00:59 +09:00
committed by Jagan Teki
parent 2d20f34485
commit a4aa9b7522
2 changed files with 56 additions and 0 deletions
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1
include/linux/mtd/spi-nor.h
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@@ -125,6 +125,7 @@
#define SPINOR_OP_CLSR 0x30 /* Clear status register 1 */
#define SPINOR_OP_RDAR 0x65 /* Read any register */
#define SPINOR_OP_WRAR 0x71 /* Write any register */
#define SPINOR_REG_ADDR_CFR1V 0x00800002
/* Used for Micron flashes only. */
#define SPINOR_OP_RD_EVCR 0x65 /* Read EVCR register */