From cf8df34015fcbd6b85a8ebadd22382d68c57f4e5 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Tue, 7 Apr 2020 16:07:46 +0200 Subject: [PATCH 1/3] arm: stm32mp: cleanup test on eth_env_set_enetaddr result Remove the unnecessary inversion on the eth_env_set_enetaddr() result which only make complex the code of setup_mac_address() and display an invalid value in the associated pr_err. Signed-off-by: Patrick Delaunay Reviewed-by: Marek Vasut --- arch/arm/mach-stm32mp/cpu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-stm32mp/cpu.c b/arch/arm/mach-stm32mp/cpu.c index b7fcee2b36..f19e5c3f33 100644 --- a/arch/arm/mach-stm32mp/cpu.c +++ b/arch/arm/mach-stm32mp/cpu.c @@ -580,8 +580,8 @@ __weak int setup_mac_address(void) return -EINVAL; } pr_debug("OTP MAC address = %pM\n", enetaddr); - ret = !eth_env_set_enetaddr("ethaddr", enetaddr); - if (!ret) + ret = eth_env_set_enetaddr("ethaddr", enetaddr); + if (ret) pr_err("Failed to set mac address %pM from OTP: %d\n", enetaddr, ret); #endif From 43e2d1dd47a7e9b126659dc17a10f351e49bc53b Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 22 Aug 2020 22:45:36 +0200 Subject: [PATCH 2/3] ARM: dts: stm32: Pull UART4 RX high on AV96 There is no dedicated pull resistor on the AV96 UART4 (console UART) pin. In case there is no UART adapter installed on the AV96, the line is floating and can trigger reception of garbage characters, which in turn can abort U-Boot autoboot. Add default pull up to mitigate this problem. Signed-off-by: Marek Vasut Cc: Patrick Delaunay Cc: Patrice Chotard Reviewed-by: Patrick Delaunay --- arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi index cb92fc9c14..1ae57e1854 100644 --- a/arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi @@ -75,6 +75,8 @@ }; pins2 { u-boot,dm-pre-reloc; + /delete-property/ bias-disable; + bias-pull-up; }; }; From b6055945d66d0f4e3b1ecb82af476232067a4ee4 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 22 Aug 2020 22:45:25 +0200 Subject: [PATCH 3/3] ARM: dts: stm32: Adjust PLL4 settings on AV96 again PLL4Q is supplying both FDCAN and LTDC. In case HDMI is in use, the 50 MHz generated from PLL4Q cannot be divided well enough to produce accurate clock for HDMI pixel clock. Adjust it to generate 74.25 MHz instead. The PLL4P/PLL4R are generating 99 MHz instead of 100 MHz, which is in tolerance for the SDMMC. Signed-off-by: Marek Vasut Cc: Gerald Baeza Cc: Patrick Delaunay Cc: Patrice Chotard Reviewed-by: Patrick Delaunay --- arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi index 7529068c51..c73318488d 100644 --- a/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi @@ -132,11 +132,11 @@ u-boot,dm-pre-reloc; }; - /* VCO = 600.0 MHz => P = 100, Q = 50, R = 100 */ + /* VCO = 600.0 MHz => P = 99, Q = 74, R = 99 */ pll4: st,pll@3 { compatible = "st,stm32mp1-pll"; reg = <3>; - cfg = < 1 49 5 11 5 PQR(1,1,1) >; + cfg = < 3 98 5 7 5 PQR(1,1,1) >; u-boot,dm-pre-reloc; }; };