Merge commit 'ef5ba2cef4a08b68caaa9215fcac142d3025bbf7' of https://github.com/tienfong/uboot_mainline

drivers/clk/altera/clk-mem-n5x.c

@@ -1,6 +1,6 @@
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
 /*
- * Copyright (C) 2020-2021 Intel Corporation <www.intel.com>
+ * Copyright (C) 2020-2022 Intel Corporation <www.intel.com>
  */
 
 #include <common.h>

drivers/clk/altera/clk-mem-n5x.h

@@ -1,6 +1,6 @@
-/* SPDX-License-Identifier: GPL-2.0 */
+/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
 /*
- * Copyright (C) 2020-2021 Intel Corporation <www.intel.com>
+ * Copyright (C) 2020-2022 Intel Corporation <www.intel.com>
  */
 
 #ifndef	_CLK_MEM_N5X_

drivers/clk/altera/clk-n5x.c

@@ -1,6 +1,6 @@
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
 /*
- * Copyright (C) 2020-2021 Intel Corporation <www.intel.com>
+ * Copyright (C) 2020-2022 Intel Corporation <www.intel.com>
  */
 
 #include <common.h>

drivers/clk/altera/clk-n5x.h

@@ -1,6 +1,6 @@
-/* SPDX-License-Identifier: GPL-2.0 */
+/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
 /*
- * Copyright (C) 2020-2021 Intel Corporation <www.intel.com>
+ * Copyright (C) 2020-2022 Intel Corporation <www.intel.com>
  */
 
 #ifndef	_CLK_N5X_

drivers/fpga/socfpga_arria10.c

@@ -30,6 +30,14 @@
 #define FPGA_TIMEOUT_MSEC	1000  /* timeout in ms */
 #define FPGA_TIMEOUT_CNT	0x1000000
 #define DEFAULT_DDR_LOAD_ADDRESS	0x400
+#define DDR_BUFFER_SIZE		0x100000
+
+/* When reading bitstream from a filesystem, the size of the first read is
+ * changed so that the subsequent reads are aligned to this value. This value
+ * was chosen so that in subsequent reads the fat fs driver doesn't have to
+ * allocate a temporary buffer in get_contents (assuming 8KiB clusters).
+ */
+#define MAX_FIRST_LOAD_SIZE	0x2000
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -72,6 +80,13 @@ static int wait_for_user_mode(void)
 		1, FPGA_TIMEOUT_MSEC, false);
 }
 
+static int wait_for_fifo_empty(void)
+{
+	return wait_for_bit_le32(&fpga_manager_base->imgcfg_stat,
+		ALT_FPGAMGR_IMGCFG_STAT_F2S_IMGCFG_FIFOEMPTY_SET_MSK,
+		1, FPGA_TIMEOUT_MSEC, false);
+}
+
 int is_fpgamgr_early_user_mode(void)
 {
 	return (readl(&fpga_manager_base->imgcfg_stat) &
@@ -526,7 +541,8 @@ static void get_rbf_image_info(struct rbf_info *rbf, u16 *buffer)
 #ifdef CONFIG_FS_LOADER
 static int first_loading_rbf_to_buffer(struct udevice *dev,
 				struct fpga_loadfs_info *fpga_loadfs,
-				u32 *buffer, size_t *buffer_bsize)
+				u32 *buffer, size_t *buffer_bsize,
+				size_t *buffer_bsize_ori)
 {
 	u32 *buffer_p = (u32 *)*buffer;
 	u32 *loadable = buffer_p;
@@ -674,6 +690,7 @@ static int first_loading_rbf_to_buffer(struct udevice *dev,
 		}
 
 		buffer_size = rbf_size;
+		*buffer_bsize_ori = DDR_BUFFER_SIZE;
 	}
 
 	debug("FPGA: External data: offset = 0x%x, size = 0x%x.\n",
@@ -686,11 +703,16 @@ static int first_loading_rbf_to_buffer(struct udevice *dev,
 	 * chunk by chunk transfer is required due to smaller buffer size
 	 * compare to bitstream
 	 */
+
+	if (buffer_size > MAX_FIRST_LOAD_SIZE)
+		buffer_size = MAX_FIRST_LOAD_SIZE;
+
 	if (rbf_size <= buffer_size) {
 		/* Loading whole bitstream into buffer */
 		buffer_size = rbf_size;
 		fpga_loadfs->remaining = 0;
 	} else {
+		buffer_size -= rbf_offset % buffer_size;
 		fpga_loadfs->remaining -= buffer_size;
 	}
 
@@ -806,7 +828,8 @@ int socfpga_loadfs(fpga_fs_info *fpga_fsinfo, const void *buf, size_t bsize,
 	 * function below.
 	 */
 	ret = first_loading_rbf_to_buffer(dev, &fpga_loadfs, &buffer,
-					   &buffer_sizebytes);
+					   &buffer_sizebytes,
+					   &buffer_sizebytes_ori);
 	if (ret == 1) {
 		printf("FPGA: Skipping configuration ...\n");
 		return 0;
@@ -858,6 +881,7 @@ int socfpga_loadfs(fpga_fs_info *fpga_fsinfo, const void *buf, size_t bsize,
 
 		WATCHDOG_RESET();
 	}
+	wait_for_fifo_empty();
 
 	if (fpga_loadfs.rbfinfo.section == periph_section) {
 		if (fpgamgr_wait_early_user_mode() != -ETIMEDOUT) {

drivers/misc/atsha204a-i2c.c

@@ -21,7 +21,8 @@
 #include <linux/bitrev.h>
 #include <u-boot/crc.h>
 
-#define ATSHA204A_TWLO			60
+#define ATSHA204A_TWLO_US		60
+#define ATSHA204A_TWHI_US		2500
 #define ATSHA204A_TRANSACTION_TIMEOUT	100000
 #define ATSHA204A_TRANSACTION_RETRY	5
 #define ATSHA204A_EXECTIME		5000
@@ -109,7 +110,7 @@ int atsha204a_wakeup(struct udevice *dev)
 			continue;
 		}
 
-		udelay(ATSHA204A_TWLO);
+		udelay(ATSHA204A_TWLO_US + ATSHA204A_TWHI_US);
 
 		res = atsha204a_recv_resp(dev, &resp);
 		if (res) {

drivers/sysreset/sysreset_socfpga.c

@@ -40,7 +40,7 @@ static int socfpga_sysreset_probe(struct udevice *dev)
 {
 	struct socfpga_sysreset_data *data = dev_get_priv(dev);
 
-	data->rstmgr_base = dev_read_addr_ptr(dev);
+	data->rstmgr_base = dev_read_addr_ptr(dev_get_parent(dev));
 	return 0;
 }