Drop PCMCIA
This is no-longer used in U-Boot and has not been converted to driver model. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Simon Glass
Tom Rini
@@ -339,8 +339,6 @@ static inline struct in_addr env_get_ip(char *var)
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return string_to_ip(env_get(var));
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}
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int pcmcia_init (void);
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#ifdef CONFIG_LED_STATUS
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# include <status_led.h>
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#endif
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137
include/pcmcia.h
137
include/pcmcia.h
@@ -1,137 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2000-2004
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*/
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#ifndef _PCMCIA_H
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#define _PCMCIA_H
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#include <common.h>
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#include <config.h>
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/*
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* Allow configuration to select PCMCIA slot,
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* or try to generate a useful default
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*/
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#if defined(CONFIG_CMD_PCMCIA)
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#if !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B)
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# error "PCMCIA Slot not configured"
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#endif /* !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B) */
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/* Make sure exactly one slot is defined - we support only one for now */
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#if !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B)
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#error Neither CONFIG_PCMCIA_SLOT_A nor CONFIG_PCMCIA_SLOT_B configured
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#endif
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#if defined(CONFIG_PCMCIA_SLOT_A) && defined(CONFIG_PCMCIA_SLOT_B)
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#error Both CONFIG_PCMCIA_SLOT_A and CONFIG_PCMCIA_SLOT_B configured
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#endif
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#ifndef PCMCIA_SOCKETS_NO
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#define PCMCIA_SOCKETS_NO 1
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#endif
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#ifndef PCMCIA_MEM_WIN_NO
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#define PCMCIA_MEM_WIN_NO 4
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#endif
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#define PCMCIA_IO_WIN_NO 2
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/* define _slot_ to be able to optimize macros */
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#ifdef CONFIG_PCMCIA_SLOT_A
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# define _slot_ 0
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# define PCMCIA_SLOT_MSG "slot A"
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# define PCMCIA_SLOT_x PCMCIA_PSLOT_A
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#else
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# define _slot_ 1
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# define PCMCIA_SLOT_MSG "slot B"
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# define PCMCIA_SLOT_x PCMCIA_PSLOT_B
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#endif
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/*
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* This structure is used to address each window in the PCMCIA controller.
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*
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* Keep in mind that we assume that pcmcia_win_t[n+1] is mapped directly
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* after pcmcia_win_t[n]...
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*/
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typedef struct {
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ulong br;
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ulong or;
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} pcmcia_win_t;
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/**********************************************************************/
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/*
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* CIS Tupel codes
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*/
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#define CISTPL_NULL 0x00
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#define CISTPL_DEVICE 0x01
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#define CISTPL_LONGLINK_CB 0x02
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#define CISTPL_INDIRECT 0x03
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#define CISTPL_CONFIG_CB 0x04
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#define CISTPL_CFTABLE_ENTRY_CB 0x05
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#define CISTPL_LONGLINK_MFC 0x06
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#define CISTPL_BAR 0x07
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#define CISTPL_PWR_MGMNT 0x08
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#define CISTPL_EXTDEVICE 0x09
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#define CISTPL_CHECKSUM 0x10
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#define CISTPL_LONGLINK_A 0x11
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#define CISTPL_LONGLINK_C 0x12
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#define CISTPL_LINKTARGET 0x13
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#define CISTPL_NO_LINK 0x14
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#define CISTPL_VERS_1 0x15
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#define CISTPL_ALTSTR 0x16
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#define CISTPL_DEVICE_A 0x17
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#define CISTPL_JEDEC_C 0x18
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#define CISTPL_JEDEC_A 0x19
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#define CISTPL_CONFIG 0x1a
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#define CISTPL_CFTABLE_ENTRY 0x1b
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#define CISTPL_DEVICE_OC 0x1c
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#define CISTPL_DEVICE_OA 0x1d
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#define CISTPL_DEVICE_GEO 0x1e
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#define CISTPL_DEVICE_GEO_A 0x1f
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#define CISTPL_MANFID 0x20
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#define CISTPL_FUNCID 0x21
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#define CISTPL_FUNCE 0x22
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#define CISTPL_SWIL 0x23
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#define CISTPL_END 0xff
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/*
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* CIS Function ID codes
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*/
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#define CISTPL_FUNCID_MULTI 0x00
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#define CISTPL_FUNCID_MEMORY 0x01
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#define CISTPL_FUNCID_SERIAL 0x02
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#define CISTPL_FUNCID_PARALLEL 0x03
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#define CISTPL_FUNCID_FIXED 0x04
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#define CISTPL_FUNCID_VIDEO 0x05
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#define CISTPL_FUNCID_NETWORK 0x06
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#define CISTPL_FUNCID_AIMS 0x07
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#define CISTPL_FUNCID_SCSI 0x08
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/*
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* Fixed Disk FUNCE codes
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*/
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#define CISTPL_IDE_INTERFACE 0x01
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#define CISTPL_FUNCE_IDE_IFACE 0x01
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#define CISTPL_FUNCE_IDE_MASTER 0x02
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#define CISTPL_FUNCE_IDE_SLAVE 0x03
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/* First feature byte */
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#define CISTPL_IDE_SILICON 0x04
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#define CISTPL_IDE_UNIQUE 0x08
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#define CISTPL_IDE_DUAL 0x10
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/* Second feature byte */
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#define CISTPL_IDE_HAS_SLEEP 0x01
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#define CISTPL_IDE_HAS_STANDBY 0x02
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#define CISTPL_IDE_HAS_IDLE 0x04
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#define CISTPL_IDE_LOW_POWER 0x08
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#define CISTPL_IDE_REG_INHIBIT 0x10
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#define CISTPL_IDE_HAS_INDEX 0x20
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#define CISTPL_IDE_IOIS16 0x40
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#endif
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#endif /* _PCMCIA_H */
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@@ -1,156 +0,0 @@
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/*
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* yenta.h 1.20 2001/08/24 12:15:34
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*
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* The contents of this file are subject to the Mozilla Public License
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* Version 1.1 (the "License"); you may not use this file except in
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* compliance with the License. You may obtain a copy of the License
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* at http://www.mozilla.org/MPL/
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*
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* Software distributed under the License is distributed on an "AS IS"
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* basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See
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* the License for the specific language governing rights and
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* limitations under the License.
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*
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* The initial developer of the original code is David A. Hinds
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* <dahinds@users.sourceforge.net>. Portions created by David A. Hinds
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* are Copyright (C) 1999 David A. Hinds. All Rights Reserved.
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*
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* Alternatively, the contents of this file may be used under the
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* terms of the GNU General Public License version 2 (the "GPL"), in
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* which case the provisions of the GPL are applicable instead of the
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* above. If you wish to allow the use of your version of this file
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* only under the terms of the GPL and not to allow others to use
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* your version of this file under the MPL, indicate your decision by
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* deleting the provisions above and replace them with the notice and
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* other provisions required by the GPL. If you do not delete the
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* provisions above, a recipient may use your version of this file
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* under either the MPL or the GPL.
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*/
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#ifndef _LINUX_YENTA_H
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#define _LINUX_YENTA_H
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/* PCI Configuration Registers */
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#define PCI_STATUS_CAPLIST 0x10
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#define PCI_CB_CAPABILITY_POINTER 0x14 /* 8 bit */
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#define PCI_CAPABILITY_ID 0x00 /* 8 bit */
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#define PCI_CAPABILITY_PM 0x01
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#define PCI_NEXT_CAPABILITY 0x01 /* 8 bit */
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#define PCI_PM_CAPABILITIES 0x02 /* 16 bit */
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#define PCI_PMCAP_PME_D3COLD 0x8000
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#define PCI_PMCAP_PME_D3HOT 0x4000
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#define PCI_PMCAP_PME_D2 0x2000
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#define PCI_PMCAP_PME_D1 0x1000
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#define PCI_PMCAP_PME_D0 0x0800
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#define PCI_PMCAP_D2_CAP 0x0400
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#define PCI_PMCAP_D1_CAP 0x0200
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#define PCI_PMCAP_DYN_DATA 0x0100
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#define PCI_PMCAP_DSI 0x0020
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#define PCI_PMCAP_AUX_PWR 0x0010
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#define PCI_PMCAP_PMECLK 0x0008
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#define PCI_PMCAP_VERSION_MASK 0x0007
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#define PCI_PM_CONTROL_STATUS 0x04 /* 16 bit */
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#define PCI_PMCS_PME_STATUS 0x8000
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#define PCI_PMCS_DATASCALE_MASK 0x6000
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#define PCI_PMCS_DATASCALE_SHIFT 13
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#define PCI_PMCS_DATASEL_MASK 0x1e00
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#define PCI_PMCS_DATASEL_SHIFT 9
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#define PCI_PMCS_PME_ENABLE 0x0100
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#define PCI_PMCS_PWR_STATE_MASK 0x0003
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#define PCI_PMCS_PWR_STATE_D0 0x0000
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#define PCI_PMCS_PWR_STATE_D1 0x0001
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#define PCI_PMCS_PWR_STATE_D2 0x0002
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#define PCI_PMCS_PWR_STATE_D3 0x0003
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#define PCI_PM_BRIDGE_EXT 0x06 /* 8 bit */
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#define PCI_PM_DATA 0x07 /* 8 bit */
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#define CB_PRIMARY_BUS 0x18 /* 8 bit */
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#define CB_CARDBUS_BUS 0x19 /* 8 bit */
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#define CB_SUBORD_BUS 0x1a /* 8 bit */
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#define CB_LATENCY_TIMER 0x1b /* 8 bit */
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#define CB_MEM_BASE(m) (0x1c + 8*(m))
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#define CB_MEM_LIMIT(m) (0x20 + 8*(m))
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#define CB_IO_BASE(m) (0x2c + 8*(m))
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#define CB_IO_LIMIT(m) (0x30 + 8*(m))
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#define CB_BRIDGE_CONTROL 0x3e /* 16 bit */
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#define CB_BCR_PARITY_ENA 0x0001
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#define CB_BCR_SERR_ENA 0x0002
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#define CB_BCR_ISA_ENA 0x0004
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#define CB_BCR_VGA_ENA 0x0008
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#define CB_BCR_MABORT 0x0020
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#define CB_BCR_CB_RESET 0x0040
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#define CB_BCR_ISA_IRQ 0x0080
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#define CB_BCR_PREFETCH(m) (0x0100 << (m))
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#define CB_BCR_WRITE_POST 0x0400
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#define CB_LEGACY_MODE_BASE 0x44
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/* Memory mapped registers */
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#define CB_SOCKET_EVENT 0x0000
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#define CB_SE_CSTSCHG 0x00000001
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#define CB_SE_CCD 0x00000006
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#define CB_SE_CCD1 0x00000002
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#define CB_SE_CCD2 0x00000004
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#define CB_SE_PWRCYCLE 0x00000008
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#define CB_SOCKET_MASK 0x0004
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#define CB_SM_CSTSCHG 0x00000001
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#define CB_SM_CCD 0x00000006
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#define CB_SM_PWRCYCLE 0x00000008
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#define CB_SOCKET_STATE 0x0008
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#define CB_SS_CSTSCHG 0x00000001
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#define CB_SS_CCD 0x00000006
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#define CB_SS_CCD1 0x00000002
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#define CB_SS_CCD2 0x00000004
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#define CB_SS_PWRCYCLE 0x00000008
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#define CB_SS_16BIT 0x00000010
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#define CB_SS_32BIT 0x00000020
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#define CB_SS_CINT 0x00000040
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#define CB_SS_BADCARD 0x00000080
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#define CB_SS_DATALOST 0x00000100
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#define CB_SS_BADVCC 0x00000200
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#define CB_SS_5VCARD 0x00000400
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#define CB_SS_3VCARD 0x00000800
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#define CB_SS_XVCARD 0x00001000
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#define CB_SS_YVCARD 0x00002000
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#define CB_SS_VSENSE 0x00003c86
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#define CB_SS_5VSOCKET 0x10000000
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#define CB_SS_3VSOCKET 0x20000000
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#define CB_SS_XVSOCKET 0x40000000
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#define CB_SS_YVSOCKET 0x80000000
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#define CB_SOCKET_FORCE 0x000c
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#define CB_SF_CVSTEST 0x00004000
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#define CB_SOCKET_CONTROL 0x0010
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#define CB_SC_VPP_MASK 0x00000007
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#define CB_SC_VPP_OFF 0x00000000
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#define CB_SC_VPP_12V 0x00000001
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#define CB_SC_VPP_5V 0x00000002
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#define CB_SC_VPP_3V 0x00000003
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#define CB_SC_VPP_XV 0x00000004
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#define CB_SC_VPP_YV 0x00000005
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#define CB_SC_VCC_MASK 0x00000070
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#define CB_SC_VCC_OFF 0x00000000
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#define CB_SC_VCC_5V 0x00000020
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#define CB_SC_VCC_3V 0x00000030
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#define CB_SC_VCC_XV 0x00000040
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#define CB_SC_VCC_YV 0x00000050
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#define CB_SC_CCLK_STOP 0x00000080
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#define CB_SOCKET_POWER 0x0020
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#define CB_SP_CLK_CTRL 0x00000001
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#define CB_SP_CLK_CTRL_ENA 0x00010000
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#define CB_SP_CLK_MODE 0x01000000
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#define CB_SP_ACCESS 0x02000000
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/* Address bits 31..24 for memory windows for 16-bit cards,
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accessable only by memory mapping the 16-bit register set */
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#define CB_MEM_PAGE(map) (0x40 + (map))
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#endif /* _LINUX_YENTA_H */
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